1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* Information about a relocation unspec. SYMBOL is the relocation symbol
60 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
61 is the constant addend. */
68 /* Temporary register allocation support structure. */
69 typedef struct frv_tmp_reg_struct
71 HARD_REG_SET regs; /* possible registers to allocate */
72 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
76 /* Register state information for VLIW re-packing phase. These values must fit
77 within an unsigned char. */
78 #define REGSTATE_DEAD 0x00 /* register is currently dead */
79 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
80 #define REGSTATE_LIVE 0x08 /* register is live */
81 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
82 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
83 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
84 #define REGSTATE_UNUSED 0x80 /* bit for hire */
85 #define REGSTATE_MASK 0xff /* mask for the bits to set */
87 /* conditional expression used */
88 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
90 /* The following is not sure in the reg_state bytes, so can have a larger value
92 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
94 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
102 /* Information required by frv_frame_access. */
105 /* This field is FRV_LOAD if registers are to be loaded from the stack and
106 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
107 the move is being done by the prologue code while FRV_LOAD implies it
108 is being done by the epilogue. */
109 enum frv_stack_op op;
111 /* The base register to use when accessing the stack. This may be the
112 frame pointer, stack pointer, or a temporary. The choice of register
113 depends on which part of the frame is being accessed and how big the
117 /* The offset of BASE from the bottom of the current frame, in bytes. */
119 } frv_frame_accessor_t;
121 /* Define the information needed to generate branch and scc insns. This is
122 stored from the compare operation. */
126 /* Conditional execution support gathered together in one structure. */
129 /* Linked list of insns to add if the conditional execution conversion was
130 successful. Each link points to an EXPR_LIST which points to the pattern
131 of the insn to add, and the insn to be inserted before. */
132 rtx added_insns_list;
134 /* Identify which registers are safe to allocate for if conversions to
135 conditional execution. We keep the last allocated register in the
136 register classes between COND_EXEC statements. This will mean we allocate
137 different registers for each different COND_EXEC group if we can. This
138 might allow the scheduler to intermix two different COND_EXEC sections. */
139 frv_tmp_reg_t tmp_reg;
141 /* For nested IFs, identify which CC registers are used outside of setting
142 via a compare isnsn, and using via a check insn. This will allow us to
143 know if we can rewrite the register to use a different register that will
144 be paired with the CR register controlling the nested IF-THEN blocks. */
145 HARD_REG_SET nested_cc_ok_rewrite;
147 /* Temporary registers allocated to hold constants during conditional
149 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
151 /* Current number of temp registers available. */
152 int cur_scratch_regs;
154 /* Number of nested conditional execution blocks. */
155 int num_nested_cond_exec;
157 /* Map of insns that set up constants in scratch registers. */
158 bitmap scratch_insns_bitmap;
160 /* Conditional execution test register (CC0..CC7). */
163 /* Conditional execution compare register that is paired with cr_reg, so that
164 nested compares can be done. The csubcc and caddcc instructions don't
165 have enough bits to specify both a CC register to be set and a CR register
166 to do the test on, so the same bit number is used for both. Needless to
167 say, this is rather inconvenient for GCC. */
170 /* Extra CR registers used for &&, ||. */
174 /* Previous CR used in nested if, to make sure we are dealing with the same
175 nested if as the previous statement. */
176 rtx last_nested_if_cr;
180 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
182 /* Map register number to smallest register class. */
183 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
185 /* Map class letter into register class. */
186 enum reg_class reg_class_from_letter[256];
188 /* Cached value of frv_stack_info. */
189 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
191 /* -mbranch-cost= support */
192 const char *frv_branch_cost_string;
193 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
196 const char *frv_cpu_string; /* -mcpu= option */
197 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
199 /* -mcond-exec-insns= support */
200 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
201 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
203 /* -mcond-exec-temps= support */
204 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
205 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
207 /* -msched-lookahead=n */
208 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
209 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
211 /* Forward references */
212 static int frv_default_flags_for_cpu (void);
213 static int frv_string_begins_with (tree, const char *);
214 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
215 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
216 static void frv_print_operand_memory_reference_reg
218 static void frv_print_operand_memory_reference (FILE *, rtx, int);
219 static int frv_print_operand_jump_hint (rtx);
220 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
221 static rtx single_set_pattern (rtx);
222 static int frv_function_contains_far_jump (void);
223 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
227 static rtx frv_frame_offset_rtx (int);
228 static rtx frv_frame_mem (enum machine_mode, rtx, int);
229 static rtx frv_dwarf_store (rtx, int);
230 static void frv_frame_insn (rtx, rtx);
231 static void frv_frame_access (frv_frame_accessor_t*,
233 static void frv_frame_access_multi (frv_frame_accessor_t*,
235 static void frv_frame_access_standard_regs (enum frv_stack_op,
237 static struct machine_function *frv_init_machine_status (void);
238 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
239 static rtx frv_int_to_acc (enum insn_code, int, rtx);
240 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
241 static rtx frv_read_argument (tree *);
242 static int frv_check_constant_argument (enum insn_code, int, rtx);
243 static rtx frv_legitimize_target (enum insn_code, rtx);
244 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
245 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
246 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
247 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
248 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
249 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
250 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
251 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
252 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
253 static rtx frv_expand_mclracc_builtin (tree);
254 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
255 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
256 static rtx frv_expand_noargs_builtin (enum insn_code);
257 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
258 static int frv_clear_registers_used (rtx *, void *);
259 static void frv_ifcvt_add_insn (rtx, rtx, int);
260 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
261 static rtx frv_ifcvt_load_value (rtx, rtx);
262 static void frv_registers_update (rtx, unsigned char [],
264 static int frv_registers_used_p (rtx, unsigned char [], int);
265 static int frv_registers_set_p (rtx, unsigned char [], int);
266 static int frv_issue_rate (void);
267 static void frv_pack_insns (void);
268 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
269 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
270 static bool frv_assemble_integer (rtx, unsigned, int);
271 static void frv_init_builtins (void);
272 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
273 static void frv_init_libfuncs (void);
274 static bool frv_in_small_data_p (tree);
275 static void frv_asm_output_mi_thunk
276 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
277 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
280 static rtx frv_expand_builtin_saveregs (void);
281 static bool frv_rtx_costs (rtx, int, int, int*);
282 static void frv_asm_out_constructor (rtx, int);
283 static void frv_asm_out_destructor (rtx, int);
284 static bool frv_function_symbol_referenced_p (rtx);
285 static bool frv_cannot_force_const_mem (rtx);
286 static const char *unspec_got_name (int);
287 static void frv_output_const_unspec (FILE *,
288 const struct frv_unspec *);
289 static bool frv_function_ok_for_sibcall (tree, tree);
290 static rtx frv_struct_value_rtx (tree, int);
291 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
293 /* Initialize the GCC target structure. */
294 #undef TARGET_ASM_FUNCTION_PROLOGUE
295 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
296 #undef TARGET_ASM_FUNCTION_EPILOGUE
297 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
298 #undef TARGET_ASM_INTEGER
299 #define TARGET_ASM_INTEGER frv_assemble_integer
300 #undef TARGET_INIT_BUILTINS
301 #define TARGET_INIT_BUILTINS frv_init_builtins
302 #undef TARGET_EXPAND_BUILTIN
303 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
304 #undef TARGET_INIT_LIBFUNCS
305 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
306 #undef TARGET_IN_SMALL_DATA_P
307 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
308 #undef TARGET_RTX_COSTS
309 #define TARGET_RTX_COSTS frv_rtx_costs
310 #undef TARGET_ASM_CONSTRUCTOR
311 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
312 #undef TARGET_ASM_DESTRUCTOR
313 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
315 #undef TARGET_ASM_OUTPUT_MI_THUNK
316 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
317 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
318 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
320 #undef TARGET_SCHED_ISSUE_RATE
321 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
323 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
324 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
325 #undef TARGET_CANNOT_FORCE_CONST_MEM
326 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
328 #undef TARGET_STRUCT_VALUE_RTX
329 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
330 #undef TARGET_MUST_PASS_IN_STACK
331 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
332 #undef TARGET_PASS_BY_REFERENCE
333 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
335 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
336 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
337 #undef TARGET_SETUP_INCOMING_VARARGS
338 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
340 struct gcc_target targetm = TARGET_INITIALIZER;
342 /* Any function call that satisfies the machine-independent
343 requirements is eligible on FR-V. */
346 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
347 tree exp ATTRIBUTE_UNUSED)
352 /* Return true if SYMBOL is a small data symbol and relocation RELOC
353 can be used to access it directly in a load or store. */
355 static FRV_INLINE bool
356 frv_small_data_reloc_p (rtx symbol, int reloc)
358 return (GET_CODE (symbol) == SYMBOL_REF
359 && SYMBOL_REF_SMALL_P (symbol)
360 && (!TARGET_FDPIC || flag_pic == 1)
361 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
364 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
367 static FRV_INLINE bool
368 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
370 if (GET_CODE (x) == CONST)
374 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
376 unspec->offset += INTVAL (XEXP (x, 1));
379 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
381 unspec->symbol = XVECEXP (x, 0, 0);
382 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
384 if (unspec->offset == 0)
387 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
388 && unspec->offset > 0
389 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
396 /* Decide whether we can force certain constants to memory. If we
397 decide we can't, the caller should be able to cope with it in
400 We never allow constants to be forced into memory for TARGET_FDPIC.
401 This is necessary for several reasons:
403 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
404 target-independent code will try to force them into the constant
405 pool, thus leading to infinite recursion.
407 2. We can never introduce new constant pool references during reload.
408 Any such reference would require use of the pseudo FDPIC register.
410 3. We can't represent a constant added to a function pointer (which is
411 not the same as a pointer to a function+constant).
413 4. In many cases, it's more efficient to calculate the constant in-line. */
416 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
422 frv_default_flags_for_cpu (void)
424 switch (frv_cpu_type)
426 case FRV_CPU_GENERIC:
427 return MASK_DEFAULT_FRV;
431 return MASK_DEFAULT_FR500;
434 return MASK_DEFAULT_FR400;
438 return MASK_DEFAULT_SIMPLE;
443 /* Sometimes certain combinations of command options do not make
444 sense on a particular target machine. You can define a macro
445 `OVERRIDE_OPTIONS' to take account of this. This macro, if
446 defined, is executed once just after all the command options have
449 Don't use this macro to turn on various extra optimizations for
450 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
453 frv_override_options (void)
457 /* Set the cpu type. */
460 if (strcmp (frv_cpu_string, "simple") == 0)
461 frv_cpu_type = FRV_CPU_SIMPLE;
463 else if (strcmp (frv_cpu_string, "tomcat") == 0)
464 frv_cpu_type = FRV_CPU_TOMCAT;
466 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
467 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
471 const char *p = frv_cpu_string + sizeof ("fr") - 1;
472 if (strcmp (p, "500") == 0)
473 frv_cpu_type = FRV_CPU_FR500;
475 else if (strcmp (p, "400") == 0)
476 frv_cpu_type = FRV_CPU_FR400;
478 else if (strcmp (p, "300") == 0)
479 frv_cpu_type = FRV_CPU_FR300;
481 else if (strcmp (p, "v") == 0)
482 frv_cpu_type = FRV_CPU_GENERIC;
485 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
489 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
491 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
492 linker about linking pic and non-pic code. */
495 if (!flag_pic) /* -fPIC */
498 if (! g_switch_set) /* -G0 */
505 /* Change the branch cost value. */
506 if (frv_branch_cost_string)
507 frv_branch_cost_int = atoi (frv_branch_cost_string);
509 /* Change the # of insns to be converted to conditional execution. */
510 if (frv_condexec_insns_str)
511 frv_condexec_insns = atoi (frv_condexec_insns_str);
513 /* Change # of temporary registers used to hold integer constants. */
514 if (frv_condexec_temps_str)
515 frv_condexec_temps = atoi (frv_condexec_temps_str);
517 /* Change scheduling look ahead. */
518 if (frv_sched_lookahead_str)
519 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
521 /* A C expression whose value is a register class containing hard
522 register REGNO. In general there is more than one such class;
523 choose a class which is "minimal", meaning that no smaller class
524 also contains the register. */
526 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
528 enum reg_class class;
532 int gpr_reg = regno - GPR_FIRST;
533 if ((gpr_reg & 3) == 0)
536 else if ((gpr_reg & 1) == 0)
543 else if (FPR_P (regno))
545 int fpr_reg = regno - GPR_FIRST;
546 if ((fpr_reg & 3) == 0)
547 class = QUAD_FPR_REGS;
549 else if ((fpr_reg & 1) == 0)
556 else if (regno == LR_REGNO)
559 else if (regno == LCR_REGNO)
562 else if (ICC_P (regno))
565 else if (FCC_P (regno))
568 else if (ICR_P (regno))
571 else if (FCR_P (regno))
574 else if (ACC_P (regno))
576 int r = regno - ACC_FIRST;
578 class = QUAD_ACC_REGS;
579 else if ((r & 1) == 0)
580 class = EVEN_ACC_REGS;
585 else if (ACCG_P (regno))
591 regno_reg_class[regno] = class;
594 /* Check for small data option */
596 g_switch_value = SDATA_DEFAULT_SIZE;
598 /* A C expression which defines the machine-dependent operand
599 constraint letters for register classes. If CHAR is such a
600 letter, the value should be the register class corresponding to
601 it. Otherwise, the value should be `NO_REGS'. The register
602 letter `r', corresponding to class `GENERAL_REGS', will not be
603 passed to this macro; you do not need to handle it.
605 The following letters are unavailable, due to being used as
610 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
611 'Q', 'R', 'S', 'T', 'U'
613 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
615 for (i = 0; i < 256; i++)
616 reg_class_from_letter[i] = NO_REGS;
618 reg_class_from_letter['a'] = ACC_REGS;
619 reg_class_from_letter['b'] = EVEN_ACC_REGS;
620 reg_class_from_letter['c'] = CC_REGS;
621 reg_class_from_letter['d'] = GPR_REGS;
622 reg_class_from_letter['e'] = EVEN_REGS;
623 reg_class_from_letter['f'] = FPR_REGS;
624 reg_class_from_letter['h'] = FEVEN_REGS;
625 reg_class_from_letter['l'] = LR_REG;
626 reg_class_from_letter['q'] = QUAD_REGS;
627 reg_class_from_letter['t'] = ICC_REGS;
628 reg_class_from_letter['u'] = FCC_REGS;
629 reg_class_from_letter['v'] = ICR_REGS;
630 reg_class_from_letter['w'] = FCR_REGS;
631 reg_class_from_letter['x'] = QUAD_FPR_REGS;
632 reg_class_from_letter['y'] = LCR_REG;
633 reg_class_from_letter['z'] = SPR_REGS;
634 reg_class_from_letter['A'] = QUAD_ACC_REGS;
635 reg_class_from_letter['B'] = ACCG_REGS;
636 reg_class_from_letter['C'] = CR_REGS;
637 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
638 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
640 /* There is no single unaligned SI op for PIC code. Sometimes we
641 need to use ".4byte" and sometimes we need to use ".picptr".
642 See frv_assemble_integer for details. */
643 if (flag_pic || TARGET_FDPIC)
644 targetm.asm_out.unaligned_op.si = 0;
646 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
647 target_flags |= MASK_LINKED_FP;
649 init_machine_status = frv_init_machine_status;
653 /* Some machines may desire to change what optimizations are performed for
654 various optimization levels. This macro, if defined, is executed once just
655 after the optimization level is determined and before the remainder of the
656 command options have been parsed. Values set in this macro are used as the
657 default values for the other command line options.
659 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
660 `-O' is specified, and 0 if neither is specified.
662 SIZE is nonzero if `-Os' is specified, 0 otherwise.
664 You should not use this macro to change options that are not
665 machine-specific. These should uniformly selected by the same optimization
666 level on all supported machines. Use this macro to enable machbine-specific
669 *Do not examine `write_symbols' in this macro!* The debugging options are
670 *not supposed to alter the generated code. */
672 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
673 scheduling pass at the current time. */
675 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
679 #ifdef DISABLE_SCHED2
680 flag_schedule_insns_after_reload = 0;
689 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
692 frv_string_begins_with (tree name, const char *prefix)
694 int prefix_len = strlen (prefix);
696 /* Remember: NAME's length includes the null terminator. */
697 return (TREE_STRING_LENGTH (name) > prefix_len
698 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
701 /* Zero or more C statements that may conditionally modify two variables
702 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
703 been initialized from the two preceding macros.
705 This is necessary in case the fixed or call-clobbered registers depend on
708 You need not define this macro if it has no work to do.
710 If the usage of an entire class of registers depends on the target flags,
711 you may indicate this to GCC by using this macro to modify `fixed_regs' and
712 `call_used_regs' to 1 for each of the registers in the classes which should
713 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
714 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
716 (However, if this class is not included in `GENERAL_REGS' and all of the
717 insn patterns whose constraints permit this class are controlled by target
718 switches, then GCC will automatically avoid using these registers when the
719 target switches are opposed to them.) */
722 frv_conditional_register_usage (void)
726 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
727 fixed_regs[i] = call_used_regs[i] = 1;
729 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
730 fixed_regs[i] = call_used_regs[i] = 1;
732 for (i = ACC_FIRST + NUM_ACCS; i <= ACC_LAST; i++)
733 fixed_regs[i] = call_used_regs[i] = 1;
735 for (i = ACCG_FIRST + NUM_ACCS; i <= ACCG_LAST; i++)
736 fixed_regs[i] = call_used_regs[i] = 1;
738 /* Reserve the registers used for conditional execution. At present, we need
739 1 ICC and 1 ICR register. */
740 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
741 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
745 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
746 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
747 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
748 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
752 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
753 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
756 /* If -fpic, SDA_BASE_REG is the PIC register. */
757 if (g_switch_value == 0 && !flag_pic)
758 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
761 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
767 * Compute the stack frame layout
770 * +---------------+-----------------------+-----------------------+
771 * |Register |type |caller-save/callee-save|
772 * +---------------+-----------------------+-----------------------+
773 * |GR0 |Zero register | - |
774 * |GR1 |Stack pointer(SP) | - |
775 * |GR2 |Frame pointer(FP) | - |
776 * |GR3 |Hidden parameter | caller save |
777 * |GR4-GR7 | - | caller save |
778 * |GR8-GR13 |Argument register | caller save |
779 * |GR14-GR15 | - | caller save |
780 * |GR16-GR31 | - | callee save |
781 * |GR32-GR47 | - | caller save |
782 * |GR48-GR63 | - | callee save |
783 * |FR0-FR15 | - | caller save |
784 * |FR16-FR31 | - | callee save |
785 * |FR32-FR47 | - | caller save |
786 * |FR48-FR63 | - | callee save |
787 * +---------------+-----------------------+-----------------------+
791 * SP-> |-----------------------------------|
793 * |-----------------------------------|
794 * | Register save area |
795 * |-----------------------------------|
796 * | Local variable save area |
797 * FP-> |-----------------------------------|
799 * |-----------------------------------|
800 * | Hidden parameter save area |
801 * |-----------------------------------|
802 * | Return address(LR) storage area |
803 * |-----------------------------------|
804 * | Padding for alignment |
805 * |-----------------------------------|
806 * | Register argument area |
807 * OLD SP-> |-----------------------------------|
809 * |-----------------------------------|
812 * Argument area/Parameter area:
814 * When a function is called, this area is used for argument transfer. When
815 * the argument is set up by the caller function, this area is referred to as
816 * the argument area. When the argument is referenced by the callee function,
817 * this area is referred to as the parameter area. The area is allocated when
818 * all arguments cannot be placed on the argument register at the time of
821 * Register save area:
823 * This is a register save area that must be guaranteed for the caller
824 * function. This area is not secured when the register save operation is not
827 * Local variable save area:
829 * This is the area for local variables and temporary variables.
833 * This area stores the FP value of the caller function.
835 * Hidden parameter save area:
837 * This area stores the start address of the return value storage
838 * area for a struct/union return function.
839 * When a struct/union is used as the return value, the caller
840 * function stores the return value storage area start address in
841 * register GR3 and passes it to the caller function.
842 * The callee function interprets the address stored in the GR3
843 * as the return value storage area start address.
844 * When register GR3 needs to be saved into memory, the callee
845 * function saves it in the hidden parameter save area. This
846 * area is not secured when the save operation is not needed.
848 * Return address(LR) storage area:
850 * This area saves the LR. The LR stores the address of a return to the caller
851 * function for the purpose of function calling.
853 * Argument register area:
855 * This area saves the argument register. This area is not secured when the
856 * save operation is not needed.
860 * Arguments, the count of which equals the count of argument registers (6
861 * words), are positioned in registers GR8 to GR13 and delivered to the callee
862 * function. When a struct/union return function is called, the return value
863 * area address is stored in register GR3. Arguments not placed in the
864 * argument registers will be stored in the stack argument area for transfer
865 * purposes. When an 8-byte type argument is to be delivered using registers,
866 * it is divided into two and placed in two registers for transfer. When
867 * argument registers must be saved to memory, the callee function secures an
868 * argument register save area in the stack. In this case, a continuous
869 * argument register save area must be established in the parameter area. The
870 * argument register save area must be allocated as needed to cover the size of
871 * the argument register to be saved. If the function has a variable count of
872 * arguments, it saves all argument registers in the argument register save
875 * Argument Extension Format:
877 * When an argument is to be stored in the stack, its type is converted to an
878 * extended type in accordance with the individual argument type. The argument
879 * is freed by the caller function after the return from the callee function is
882 * +-----------------------+---------------+------------------------+
883 * | Argument Type |Extended Type |Stack Storage Size(byte)|
884 * +-----------------------+---------------+------------------------+
886 * |signed char |int | 4 |
887 * |unsigned char |int | 4 |
888 * |[signed] short int |int | 4 |
889 * |unsigned short int |int | 4 |
890 * |[signed] int |No extension | 4 |
891 * |unsigned int |No extension | 4 |
892 * |[signed] long int |No extension | 4 |
893 * |unsigned long int |No extension | 4 |
894 * |[signed] long long int |No extension | 8 |
895 * |unsigned long long int |No extension | 8 |
896 * |float |double | 8 |
897 * |double |No extension | 8 |
898 * |long double |No extension | 8 |
899 * |pointer |No extension | 4 |
900 * |struct/union |- | 4 (*1) |
901 * +-----------------------+---------------+------------------------+
903 * When a struct/union is to be delivered as an argument, the caller copies it
904 * to the local variable area and delivers the address of that area.
908 * +-------------------------------+----------------------+
909 * |Return Value Type |Return Value Interface|
910 * +-------------------------------+----------------------+
912 * |[signed|unsigned] char |GR8 |
913 * |[signed|unsigned] short int |GR8 |
914 * |[signed|unsigned] int |GR8 |
915 * |[signed|unsigned] long int |GR8 |
917 * |[signed|unsigned] long long int|GR8 & GR9 |
919 * |double |GR8 & GR9 |
920 * |long double |GR8 & GR9 |
921 * |struct/union |(*1) |
922 * +-------------------------------+----------------------+
924 * When a struct/union is used as the return value, the caller function stores
925 * the start address of the return value storage area into GR3 and then passes
926 * it to the callee function. The callee function interprets GR3 as the start
927 * address of the return value storage area. When this address needs to be
928 * saved in memory, the callee function secures the hidden parameter save area
929 * and saves the address in that area.
933 frv_stack_info (void)
935 static frv_stack_t info, zero_info;
936 frv_stack_t *info_ptr = &info;
937 tree fndecl = current_function_decl;
945 /* If we've already calculated the values and reload is complete,
948 return frv_stack_cache;
950 /* Zero all fields. */
953 /* Set up the register range information. */
954 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
955 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
956 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
957 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
959 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
960 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
961 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
962 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
964 info_ptr->regs[STACK_REGS_LR].name = "lr";
965 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
966 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
967 info_ptr->regs[STACK_REGS_LR].special_p = 1;
969 info_ptr->regs[STACK_REGS_CC].name = "cc";
970 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
971 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
972 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
974 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
975 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
976 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
978 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
979 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
980 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
981 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
982 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
984 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
985 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
986 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
987 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
989 info_ptr->regs[STACK_REGS_FP].name = "fp";
990 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
991 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
992 info_ptr->regs[STACK_REGS_FP].special_p = 1;
994 /* Determine if this is a stdarg function. If so, allocate space to store
1001 /* Find the last argument, and see if it is __builtin_va_alist. */
1002 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1004 next_arg = TREE_CHAIN (cur_arg);
1005 if (next_arg == (tree)0)
1007 if (DECL_NAME (cur_arg)
1008 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1016 /* Iterate over all of the register ranges. */
1017 for (range = 0; range < STACK_REGS_MAX; range++)
1019 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1020 int first = reg_ptr->first;
1021 int last = reg_ptr->last;
1023 int size_2words = 0;
1026 /* Calculate which registers need to be saved & save area size. */
1030 for (regno = first; regno <= last; regno++)
1032 if ((regs_ever_live[regno] && !call_used_regs[regno])
1033 || (current_function_calls_eh_return
1034 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1035 || (!TARGET_FDPIC && flag_pic
1036 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1038 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1039 size_1word += UNITS_PER_WORD;
1044 /* Calculate whether we need to create a frame after everything else
1045 has been processed. */
1050 if (regs_ever_live[LR_REGNO]
1052 /* This is set for __builtin_return_address, etc. */
1053 || cfun->machine->frame_needed
1054 || (TARGET_LINKED_FP && frame_pointer_needed)
1055 || (!TARGET_FDPIC && flag_pic
1056 && cfun->uses_pic_offset_table))
1058 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1059 size_1word += UNITS_PER_WORD;
1063 case STACK_REGS_STDARG:
1066 /* If this is a stdarg function with a non varardic
1067 argument split between registers and the stack,
1068 adjust the saved registers downward. */
1069 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1072 for (regno = first; regno <= last; regno++)
1074 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1075 size_1word += UNITS_PER_WORD;
1078 info_ptr->stdarg_size = size_1word;
1082 case STACK_REGS_STRUCT:
1083 if (cfun->returns_struct)
1085 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1086 size_1word += UNITS_PER_WORD;
1094 /* If this is a field, it only takes one word. */
1095 if (reg_ptr->field_p)
1096 size_1word = UNITS_PER_WORD;
1098 /* Determine which register pairs can be saved together. */
1099 else if (reg_ptr->dword_p && TARGET_DWORD)
1101 for (regno = first; regno < last; regno += 2)
1103 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1105 size_2words += 2 * UNITS_PER_WORD;
1106 size_1word -= 2 * UNITS_PER_WORD;
1107 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1108 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1113 reg_ptr->size_1word = size_1word;
1114 reg_ptr->size_2words = size_2words;
1116 if (! reg_ptr->special_p)
1118 info_ptr->regs_size_1word += size_1word;
1119 info_ptr->regs_size_2words += size_2words;
1124 /* Set up the sizes of each each field in the frame body, making the sizes
1125 of each be divisible by the size of a dword if dword operations might
1126 be used, or the size of a word otherwise. */
1127 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1129 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1130 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1131 + info_ptr->regs_size_1word,
1133 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1135 info_ptr->pretend_size = cfun->pretend_args_size;
1137 /* Work out the size of the frame, excluding the header. Both the frame
1138 body and register parameter area will be dword-aligned. */
1139 info_ptr->total_size
1140 = (ADDR_ALIGN (info_ptr->parameter_size
1141 + info_ptr->regs_size
1142 + info_ptr->vars_size,
1144 + ADDR_ALIGN (info_ptr->pretend_size
1145 + info_ptr->stdarg_size,
1146 2 * UNITS_PER_WORD));
1148 /* See if we need to create a frame at all, if so add header area. */
1149 if (info_ptr->total_size > 0
1150 || frame_pointer_needed
1151 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1152 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1154 offset = info_ptr->parameter_size;
1155 info_ptr->header_size = 4 * UNITS_PER_WORD;
1156 info_ptr->total_size += 4 * UNITS_PER_WORD;
1158 /* Calculate the offsets to save normal register pairs. */
1159 for (range = 0; range < STACK_REGS_MAX; range++)
1161 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1162 if (! reg_ptr->special_p)
1164 int first = reg_ptr->first;
1165 int last = reg_ptr->last;
1168 for (regno = first; regno <= last; regno++)
1169 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1170 && regno != FRAME_POINTER_REGNUM
1171 && (regno < FIRST_ARG_REGNUM
1172 || regno > LAST_ARG_REGNUM))
1174 info_ptr->reg_offset[regno] = offset;
1175 offset += 2 * UNITS_PER_WORD;
1180 /* Calculate the offsets to save normal single registers. */
1181 for (range = 0; range < STACK_REGS_MAX; range++)
1183 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1184 if (! reg_ptr->special_p)
1186 int first = reg_ptr->first;
1187 int last = reg_ptr->last;
1190 for (regno = first; regno <= last; regno++)
1191 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1192 && regno != FRAME_POINTER_REGNUM
1193 && (regno < FIRST_ARG_REGNUM
1194 || regno > LAST_ARG_REGNUM))
1196 info_ptr->reg_offset[regno] = offset;
1197 offset += UNITS_PER_WORD;
1202 /* Calculate the offset to save the local variables at. */
1203 offset = ADDR_ALIGN (offset, alignment);
1204 if (info_ptr->vars_size)
1206 info_ptr->vars_offset = offset;
1207 offset += info_ptr->vars_size;
1210 /* Align header to a dword-boundary. */
1211 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1213 /* Calculate the offsets in the fixed frame. */
1214 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1215 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1216 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1218 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1219 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1220 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1222 if (cfun->returns_struct)
1224 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1225 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1226 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1229 /* Calculate the offsets to store the arguments passed in registers
1230 for stdarg functions. The register pairs are first and the single
1231 register if any is last. The register save area starts on a
1233 if (info_ptr->stdarg_size)
1235 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1236 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1239 /* Skip the header. */
1240 offset += 4 * UNITS_PER_WORD;
1241 for (regno = first; regno <= last; regno++)
1243 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1245 info_ptr->reg_offset[regno] = offset;
1246 offset += 2 * UNITS_PER_WORD;
1248 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1250 info_ptr->reg_offset[regno] = offset;
1251 offset += UNITS_PER_WORD;
1257 if (reload_completed)
1258 frv_stack_cache = info_ptr;
1264 /* Print the information about the frv stack offsets, etc. when debugging. */
1267 frv_debug_stack (frv_stack_t *info)
1272 info = frv_stack_info ();
1274 fprintf (stderr, "\nStack information for function %s:\n",
1275 ((current_function_decl && DECL_NAME (current_function_decl))
1276 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1279 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1280 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1281 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1282 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1283 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1285 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1286 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1287 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1288 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1290 for (range = 0; range < STACK_REGS_MAX; range++)
1292 frv_stack_regs_t *regs = &(info->regs[range]);
1293 if ((regs->size_1word + regs->size_2words) > 0)
1295 int first = regs->first;
1296 int last = regs->last;
1299 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1300 regs->name, regs->size_1word + regs->size_2words,
1301 regs->size_1word, regs->size_2words);
1303 for (regno = first; regno <= last; regno++)
1305 if (info->save_p[regno] == REG_SAVE_1WORD)
1306 fprintf (stderr, " %s (%d)", reg_names[regno],
1307 info->reg_offset[regno]);
1309 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1310 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1311 reg_names[regno+1], info->reg_offset[regno]);
1314 fputc ('\n', stderr);
1324 /* The following variable value is TRUE if the next output insn should
1325 finish cpu cycle. In order words the insn will have packing bit
1326 (which means absence of asm code suffix `.p' on assembler. */
1328 static int frv_insn_packing_flag;
1330 /* True if the current function contains a far jump. */
1333 frv_function_contains_far_jump (void)
1335 rtx insn = get_insns ();
1337 && !(GET_CODE (insn) == JUMP_INSN
1338 /* Ignore tablejump patterns. */
1339 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1340 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1341 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1342 insn = NEXT_INSN (insn);
1343 return (insn != NULL);
1346 /* For the FRV, this function makes sure that a function with far jumps
1347 will return correctly. It also does the VLIW packing. */
1350 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1352 /* If no frame was created, check whether the function uses a call
1353 instruction to implement a far jump. If so, save the link in gr3 and
1354 replace all returns to LR with returns to GR3. GR3 is used because it
1355 is call-clobbered, because is not available to the register allocator,
1356 and because all functions that take a hidden argument pointer will have
1358 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1362 /* Just to check that the above comment is true. */
1363 if (regs_ever_live[GPR_FIRST + 3])
1366 /* Generate the instruction that saves the link register. */
1367 fprintf (file, "\tmovsg lr,gr3\n");
1369 /* Replace the LR with GR3 in *return_internal patterns. The insn
1370 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1371 simply emit a different assembly directive because bralr and jmpl
1372 execute in different units. */
1373 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1374 if (GET_CODE (insn) == JUMP_INSN)
1376 rtx pattern = PATTERN (insn);
1377 if (GET_CODE (pattern) == PARALLEL
1378 && XVECLEN (pattern, 0) >= 2
1379 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1380 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1382 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1383 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1384 REGNO (address) = GPR_FIRST + 3;
1390 frv_insn_packing_flag = TRUE;
1394 /* Return the next available temporary register in a given class. */
1397 frv_alloc_temp_reg (
1398 frv_tmp_reg_t *info, /* which registers are available */
1399 enum reg_class class, /* register class desired */
1400 enum machine_mode mode, /* mode to allocate register with */
1401 int mark_as_used, /* register not available after allocation */
1402 int no_abort) /* return NULL instead of aborting */
1404 int regno = info->next_reg[ (int)class ];
1405 int orig_regno = regno;
1406 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1411 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1412 && TEST_HARD_REG_BIT (info->regs, regno))
1415 if (++regno >= FIRST_PSEUDO_REGISTER)
1417 if (regno == orig_regno)
1426 nr = HARD_REGNO_NREGS (regno, mode);
1427 info->next_reg[ (int)class ] = regno + nr;
1430 for (i = 0; i < nr; i++)
1431 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1433 return gen_rtx_REG (mode, regno);
1437 /* Return an rtx with the value OFFSET, which will either be a register or a
1438 signed 12-bit integer. It can be used as the second operand in an "add"
1439 instruction, or as the index in a load or store.
1441 The function returns a constant rtx if OFFSET is small enough, otherwise
1442 it loads the constant into register OFFSET_REGNO and returns that. */
1444 frv_frame_offset_rtx (int offset)
1446 rtx offset_rtx = GEN_INT (offset);
1447 if (IN_RANGE_P (offset, -2048, 2047))
1451 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1452 if (IN_RANGE_P (offset, -32768, 32767))
1453 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1456 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1457 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1463 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1464 prologue and epilogue uses such expressions to access the stack. */
1466 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1468 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1470 frv_frame_offset_rtx (offset)));
1473 /* Generate a frame-related expression:
1475 (set REG (mem (plus (sp) (const_int OFFSET)))).
1477 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1478 instructions. Marking the expressions as frame-related is superfluous if
1479 the note contains just a single set. But if the note contains a PARALLEL
1480 or SEQUENCE that has several sets, each set must be individually marked
1481 as frame-related. */
1483 frv_dwarf_store (rtx reg, int offset)
1485 rtx set = gen_rtx_SET (VOIDmode,
1486 gen_rtx_MEM (GET_MODE (reg),
1487 plus_constant (stack_pointer_rtx,
1490 RTX_FRAME_RELATED_P (set) = 1;
1494 /* Emit a frame-related instruction whose pattern is PATTERN. The
1495 instruction is the last in a sequence that cumulatively performs the
1496 operation described by DWARF_PATTERN. The instruction is marked as
1497 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1500 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1502 rtx insn = emit_insn (pattern);
1503 RTX_FRAME_RELATED_P (insn) = 1;
1504 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1509 /* Emit instructions that transfer REG to or from the memory location (sp +
1510 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1511 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1512 function to store registers and only the epilogue uses it to load them.
1514 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1515 The generated instruction will use BASE as its base register. BASE may
1516 simply be the stack pointer, but if several accesses are being made to a
1517 region far away from the stack pointer, it may be more efficient to set
1518 up a temporary instead.
1520 Store instructions will be frame-related and will be annotated with the
1521 overall effect of the store. Load instructions will be followed by a
1522 (use) to prevent later optimizations from zapping them.
1524 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1525 as a temporary in such cases. */
1527 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1529 enum machine_mode mode = GET_MODE (reg);
1530 rtx mem = frv_frame_mem (mode,
1532 stack_offset - accessor->base_offset);
1534 if (accessor->op == FRV_LOAD)
1536 if (SPR_P (REGNO (reg)))
1538 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1539 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1540 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1543 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1544 emit_insn (gen_rtx_USE (VOIDmode, reg));
1548 if (SPR_P (REGNO (reg)))
1550 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1551 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1552 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1553 frv_dwarf_store (reg, stack_offset));
1555 else if (GET_MODE (reg) == DImode)
1557 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1558 with a separate save for each register. */
1559 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1560 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1561 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1562 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1563 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1564 gen_rtx_PARALLEL (VOIDmode,
1565 gen_rtvec (2, set1, set2)));
1568 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1569 frv_dwarf_store (reg, stack_offset));
1573 /* A function that uses frv_frame_access to transfer a group of registers to
1574 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1575 is the stack information generated by frv_stack_info, and REG_SET is the
1576 number of the register set to transfer. */
1578 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1582 frv_stack_regs_t *regs_info;
1585 regs_info = &info->regs[reg_set];
1586 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1587 if (info->save_p[regno])
1588 frv_frame_access (accessor,
1589 info->save_p[regno] == REG_SAVE_2WORDS
1590 ? gen_rtx_REG (DImode, regno)
1591 : gen_rtx_REG (SImode, regno),
1592 info->reg_offset[regno]);
1595 /* Save or restore callee-saved registers that are kept outside the frame
1596 header. The function saves the registers if OP is FRV_STORE and restores
1597 them if OP is FRV_LOAD. INFO is the stack information generated by
1600 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1602 frv_frame_accessor_t accessor;
1605 accessor.base = stack_pointer_rtx;
1606 accessor.base_offset = 0;
1607 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1608 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1609 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1613 /* Called after register allocation to add any instructions needed for the
1614 prologue. Using a prologue insn is favored compared to putting all of the
1615 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1616 it allows the scheduler to intermix instructions with the saves of
1617 the caller saved registers. In some cases, it might be necessary
1618 to emit a barrier instruction as the last insn to prevent such
1621 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1622 so that the debug info generation code can handle them properly. */
1624 frv_expand_prologue (void)
1626 frv_stack_t *info = frv_stack_info ();
1627 rtx sp = stack_pointer_rtx;
1628 rtx fp = frame_pointer_rtx;
1629 frv_frame_accessor_t accessor;
1631 if (TARGET_DEBUG_STACK)
1632 frv_debug_stack (info);
1634 if (info->total_size == 0)
1637 /* We're interested in three areas of the frame here:
1639 A: the register save area
1641 C: the header after B
1643 If the frame pointer isn't used, we'll have to set up A, B and C
1644 using the stack pointer. If the frame pointer is used, we'll access
1648 B: set up using sp or a temporary (see below)
1651 We set up B using the stack pointer if the frame is small enough.
1652 Otherwise, it's more efficient to copy the old stack pointer into a
1653 temporary and use that.
1655 Note that it's important to make sure the prologue and epilogue use the
1656 same registers to access A and C, since doing otherwise will confuse
1657 the aliasing code. */
1659 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1660 isn't used, the same method will serve for C. */
1661 accessor.op = FRV_STORE;
1662 if (frame_pointer_needed && info->total_size > 2048)
1666 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1667 accessor.base_offset = info->total_size;
1668 insn = emit_insn (gen_movsi (accessor.base, sp));
1672 accessor.base = stack_pointer_rtx;
1673 accessor.base_offset = 0;
1676 /* Allocate the stack space. */
1678 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1679 rtx dwarf_offset = GEN_INT (-info->total_size);
1681 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1684 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1687 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1688 and point the new one to that location. */
1689 if (frame_pointer_needed)
1691 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1693 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1694 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1696 rtx asm_src = plus_constant (accessor.base,
1697 fp_offset - accessor.base_offset);
1698 rtx dwarf_src = plus_constant (sp, fp_offset);
1700 /* Store the old frame pointer at (sp + FP_OFFSET). */
1701 frv_frame_access (&accessor, fp, fp_offset);
1703 /* Set up the new frame pointer. */
1704 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1705 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1707 /* Access region C from the frame pointer. */
1709 accessor.base_offset = fp_offset;
1712 /* Set up region C. */
1713 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1714 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1715 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1717 /* Set up region A. */
1718 frv_frame_access_standard_regs (FRV_STORE, info);
1720 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1721 scheduler from moving loads before the stores saving the registers. */
1722 if (info->stdarg_size > 0)
1723 emit_insn (gen_blockage ());
1725 /* Set up pic register/small data register for this function. */
1726 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1727 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1728 gen_rtx_REG (Pmode, LR_REGNO),
1729 gen_rtx_REG (SImode, OFFSET_REGNO)));
1733 /* Under frv, all of the work is done via frv_expand_epilogue, but
1734 this function provides a convenient place to do cleanup. */
1737 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1738 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1740 frv_stack_cache = (frv_stack_t *)0;
1742 /* Zap last used registers for conditional execution. */
1743 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1745 /* Release the bitmap of created insns. */
1746 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1750 /* Called after register allocation to add any instructions needed for the
1751 epilogue. Using an epilogue insn is favored compared to putting all of the
1752 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1753 it allows the scheduler to intermix instructions with the saves of
1754 the caller saved registers. In some cases, it might be necessary
1755 to emit a barrier instruction as the last insn to prevent such
1758 If SIBCALL_P is true, the final branch back to the calling function is
1759 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1760 we must not clobber any arguments used for parameter passing or any stack
1761 slots for arguments passed to the current function. */
1764 frv_expand_epilogue (bool emit_return)
1766 frv_stack_t *info = frv_stack_info ();
1767 rtx fp = frame_pointer_rtx;
1768 rtx sp = stack_pointer_rtx;
1772 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1774 /* Restore the stack pointer to its original value if alloca or the like
1776 if (! current_function_sp_is_unchanging)
1777 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1779 /* Restore the callee-saved registers that were used in this function. */
1780 frv_frame_access_standard_regs (FRV_LOAD, info);
1782 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1783 no return instruction should be emitted. */
1784 if (info->save_p[LR_REGNO])
1789 /* Use the same method to access the link register's slot as we did in
1790 the prologue. In other words, use the frame pointer if available,
1791 otherwise use the stack pointer.
1793 LR_OFFSET is the offset of the link register's slot from the start
1794 of the frame and MEM is a memory rtx for it. */
1795 lr_offset = info->reg_offset[LR_REGNO];
1796 if (frame_pointer_needed)
1797 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1799 mem = frv_frame_mem (Pmode, sp, lr_offset);
1801 /* Load the old link register into a GPR. */
1802 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1803 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1806 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1808 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1809 the load is preserved. */
1810 if (frame_pointer_needed)
1812 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1813 emit_insn (gen_rtx_USE (VOIDmode, fp));
1816 /* Deallocate the stack frame. */
1817 if (info->total_size != 0)
1819 rtx offset = frv_frame_offset_rtx (info->total_size);
1820 emit_insn (gen_stack_adjust (sp, sp, offset));
1823 /* If this function uses eh_return, add the final stack adjustment now. */
1824 if (current_function_calls_eh_return)
1825 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1828 emit_jump_insn (gen_epilogue_return (return_addr));
1831 rtx lr = return_addr;
1833 if (REGNO (return_addr) != LR_REGNO)
1835 lr = gen_rtx_REG (Pmode, LR_REGNO);
1836 emit_move_insn (lr, return_addr);
1839 emit_insn (gen_rtx_USE (VOIDmode, lr));
1844 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1847 frv_asm_output_mi_thunk (FILE *file,
1848 tree thunk_fndecl ATTRIBUTE_UNUSED,
1849 HOST_WIDE_INT delta,
1850 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1853 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1854 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1855 const char *name_jmp = reg_names[JUMP_REGNO];
1856 const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1858 /* Do the add using an addi if possible. */
1859 if (IN_RANGE_P (delta, -2048, 2047))
1860 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1863 const char *const name_add = reg_names[TEMP_REGNO];
1864 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1865 parallel, delta, name_add);
1866 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1868 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1873 const char *name_pic = reg_names[FDPIC_REGNO];
1874 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1878 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1879 assemble_name (file, name_func);
1880 fprintf (file, "),%s\n", name_jmp);
1882 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1883 assemble_name (file, name_func);
1884 fprintf (file, "),%s\n", name_jmp);
1886 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1890 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1891 assemble_name (file, name_func);
1892 fprintf (file, "\t)), %s\n", name_jmp);
1897 fprintf (file, "\tsethi%s #hi(", parallel);
1898 assemble_name (file, name_func);
1899 fprintf (file, "),%s\n", name_jmp);
1901 fprintf (file, "\tsetlo #lo(");
1902 assemble_name (file, name_func);
1903 fprintf (file, "),%s\n", name_jmp);
1907 /* Use JUMP_REGNO as a temporary PIC register. */
1908 const char *name_lr = reg_names[LR_REGNO];
1909 const char *name_gppic = name_jmp;
1910 const char *name_tmp = reg_names[TEMP_REGNO];
1912 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
1913 fprintf (file, "\tcall 1f\n");
1914 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
1915 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
1916 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
1917 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
1918 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
1920 fprintf (file, "\tsethi%s #gprelhi(", parallel);
1921 assemble_name (file, name_func);
1922 fprintf (file, "),%s\n", name_tmp);
1924 fprintf (file, "\tsetlo #gprello(");
1925 assemble_name (file, name_func);
1926 fprintf (file, "),%s\n", name_tmp);
1928 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
1931 /* Jump to the function address. */
1932 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
1936 /* A C expression which is nonzero if a function must have and use a frame
1937 pointer. This expression is evaluated in the reload pass. If its value is
1938 nonzero the function will have a frame pointer.
1940 The expression can in principle examine the current function and decide
1941 according to the facts, but on most machines the constant 0 or the constant
1942 1 suffices. Use 0 when the machine allows code to be generated with no
1943 frame pointer, and doing so saves some time or space. Use 1 when there is
1944 no possible advantage to avoiding a frame pointer.
1946 In certain cases, the compiler does not know how to produce valid code
1947 without a frame pointer. The compiler recognizes those cases and
1948 automatically gives the function a frame pointer regardless of what
1949 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1951 In a function that does not require a frame pointer, the frame pointer
1952 register can be allocated for ordinary usage, unless you mark it as a fixed
1953 register. See `FIXED_REGISTERS' for more information. */
1955 /* On frv, create a frame whenever we need to create stack. */
1958 frv_frame_pointer_required (void)
1960 /* If we forgoing the usual linkage requirements, we only need
1961 a frame pointer if the stack pointer might change. */
1962 if (!TARGET_LINKED_FP)
1963 return !current_function_sp_is_unchanging;
1965 if (! current_function_is_leaf)
1968 if (get_frame_size () != 0)
1974 if (!current_function_sp_is_unchanging)
1977 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1983 if (cfun->machine->frame_needed)
1990 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1991 initial difference between the specified pair of registers. This macro must
1992 be defined if `ELIMINABLE_REGS' is defined. */
1994 /* See frv_stack_info for more details on the frv stack frame. */
1997 frv_initial_elimination_offset (int from, int to)
1999 frv_stack_t *info = frv_stack_info ();
2002 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2003 ret = info->total_size - info->pretend_size;
2005 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2006 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2008 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2009 ret = (info->total_size
2010 - info->reg_offset[FRAME_POINTER_REGNUM]
2011 - info->pretend_size);
2016 if (TARGET_DEBUG_STACK)
2017 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2018 reg_names [from], reg_names[to], ret);
2024 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2027 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2028 enum machine_mode mode,
2029 tree type ATTRIBUTE_UNUSED,
2033 if (TARGET_DEBUG_ARG)
2035 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2036 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2040 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2043 frv_expand_builtin_saveregs (void)
2045 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2047 if (TARGET_DEBUG_ARG)
2048 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2051 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2055 /* Expand __builtin_va_start to do the va_start macro. */
2058 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2061 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2063 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2064 GEN_INT (UNITS_PER_WORD * num));
2066 if (TARGET_DEBUG_ARG)
2068 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2069 cfun->args_info, num);
2071 debug_rtx (nextarg);
2074 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2075 make_tree (ptr_type_node, nextarg));
2076 TREE_SIDE_EFFECTS (t) = 1;
2078 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2082 /* Expand a block move operation, and return 1 if successful. Return 0
2083 if we should let the compiler generate normal code.
2085 operands[0] is the destination
2086 operands[1] is the source
2087 operands[2] is the length
2088 operands[3] is the alignment */
2090 /* Maximum number of loads to do before doing the stores */
2091 #ifndef MAX_MOVE_REG
2092 #define MAX_MOVE_REG 4
2095 /* Maximum number of total loads to do. */
2096 #ifndef TOTAL_MOVE_REG
2097 #define TOTAL_MOVE_REG 8
2101 frv_expand_block_move (rtx operands[])
2103 rtx orig_dest = operands[0];
2104 rtx orig_src = operands[1];
2105 rtx bytes_rtx = operands[2];
2106 rtx align_rtx = operands[3];
2107 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2120 rtx stores[MAX_MOVE_REG];
2122 enum machine_mode mode;
2124 /* If this is not a fixed size move, just call memcpy. */
2128 /* If this is not a fixed size alignment, abort. */
2129 if (GET_CODE (align_rtx) != CONST_INT)
2132 align = INTVAL (align_rtx);
2134 /* Anything to move? */
2135 bytes = INTVAL (bytes_rtx);
2139 /* Don't support real large moves. */
2140 if (bytes > TOTAL_MOVE_REG*align)
2143 /* Move the address into scratch registers. */
2144 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2145 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2147 num_reg = offset = 0;
2148 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2150 /* Calculate the correct offset for src/dest. */
2154 dest_addr = dest_reg;
2158 src_addr = plus_constant (src_reg, offset);
2159 dest_addr = plus_constant (dest_reg, offset);
2162 /* Generate the appropriate load and store, saving the stores
2164 if (bytes >= 4 && align >= 4)
2166 else if (bytes >= 2 && align >= 2)
2171 move_bytes = GET_MODE_SIZE (mode);
2172 tmp_reg = gen_reg_rtx (mode);
2173 src_mem = change_address (orig_src, mode, src_addr);
2174 dest_mem = change_address (orig_dest, mode, dest_addr);
2175 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2176 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2178 if (num_reg >= MAX_MOVE_REG)
2180 for (i = 0; i < num_reg; i++)
2181 emit_insn (stores[i]);
2186 for (i = 0; i < num_reg; i++)
2187 emit_insn (stores[i]);
2193 /* Expand a block clear operation, and return 1 if successful. Return 0
2194 if we should let the compiler generate normal code.
2196 operands[0] is the destination
2197 operands[1] is the length
2198 operands[2] is the alignment */
2201 frv_expand_block_clear (rtx operands[])
2203 rtx orig_dest = operands[0];
2204 rtx bytes_rtx = operands[1];
2205 rtx align_rtx = operands[2];
2206 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2215 enum machine_mode mode;
2217 /* If this is not a fixed size move, just call memcpy. */
2221 /* If this is not a fixed size alignment, abort. */
2222 if (GET_CODE (align_rtx) != CONST_INT)
2225 align = INTVAL (align_rtx);
2227 /* Anything to move? */
2228 bytes = INTVAL (bytes_rtx);
2232 /* Don't support real large clears. */
2233 if (bytes > TOTAL_MOVE_REG*align)
2236 /* Move the address into a scratch register. */
2237 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2239 num_reg = offset = 0;
2240 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2242 /* Calculate the correct offset for src/dest. */
2243 dest_addr = ((offset == 0)
2245 : plus_constant (dest_reg, offset));
2247 /* Generate the appropriate store of gr0. */
2248 if (bytes >= 4 && align >= 4)
2250 else if (bytes >= 2 && align >= 2)
2255 clear_bytes = GET_MODE_SIZE (mode);
2256 dest_mem = change_address (orig_dest, mode, dest_addr);
2257 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2264 /* The following variable is used to output modifiers of assembler
2265 code of the current output insn. */
2267 static rtx *frv_insn_operands;
2269 /* The following function is used to add assembler insn code suffix .p
2270 if it is necessary. */
2273 frv_asm_output_opcode (FILE *f, const char *ptr)
2277 if (! PACKING_FLAG_USED_P())
2280 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2283 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2284 || (*ptr >= 'A' && *ptr <= 'Z')))
2286 int letter = *ptr++;
2289 frv_print_operand (f, frv_insn_operands [c], letter);
2290 while ((c = *ptr) >= '0' && c <= '9')
2297 if (!frv_insn_packing_flag)
2303 /* The following function sets up the packing bit for the current
2304 output insn. Remember that the function is not called for asm
2308 frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED)
2310 if (! PACKING_FLAG_USED_P())
2316 frv_insn_operands = opvec;
2318 /* Look for the next printable instruction. frv_pack_insns () has set
2319 things up so that any printable instruction will have TImode if it
2320 starts a new packet and VOIDmode if it should be packed with the
2321 previous instruction.
2323 Printable instructions will be asm_operands or match one of the .md
2324 patterns. Since asm instructions cannot be packed -- and will
2325 therefore have TImode -- this loop terminates on any recognizable
2326 instruction, and on any unrecognizable instruction with TImode. */
2327 for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
2331 else if (!INSN_P (insn))
2333 else if (GET_MODE (insn) == TImode || INSN_CODE (insn) != -1)
2337 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2338 be packed with this one. Set it to TRUE otherwise. If the next
2339 instruction is an asm instruction, this statement will set the
2340 flag to TRUE, and that value will still hold when the asm operands
2341 themselves are printed. */
2342 frv_insn_packing_flag = ! (insn && INSN_P (insn)
2343 && GET_MODE (insn) != TImode);
2348 /* A C expression whose value is RTL representing the address in a stack frame
2349 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2350 an RTL expression for the address of the stack frame itself.
2352 If you don't define this macro, the default is to return the value of
2353 FRAMEADDR--that is, the stack frame address is also the address of the stack
2354 word that points to the previous frame. */
2356 /* The default is correct, but we need to make sure the frame gets created. */
2358 frv_dynamic_chain_address (rtx frame)
2360 cfun->machine->frame_needed = 1;
2365 /* A C expression whose value is RTL representing the value of the return
2366 address for the frame COUNT steps up from the current frame, after the
2367 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2368 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2371 The value of the expression must always be the correct address when COUNT is
2372 zero, but may be `NULL_RTX' if there is not way to determine the return
2373 address of other frames. */
2376 frv_return_addr_rtx (int count, rtx frame)
2380 cfun->machine->frame_needed = 1;
2381 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2384 /* Given a memory reference MEMREF, interpret the referenced memory as
2385 an array of MODE values, and return a reference to the element
2386 specified by INDEX. Assume that any pre-modification implicit in
2387 MEMREF has already happened.
2389 MEMREF must be a legitimate operand for modes larger than SImode.
2390 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2391 this function cannot handle. */
2393 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2395 rtx base = XEXP (memref, 0);
2396 if (GET_CODE (base) == PRE_MODIFY)
2397 base = XEXP (base, 0);
2398 return change_address (memref, mode,
2399 plus_constant (base, index * GET_MODE_SIZE (mode)));
2403 /* Print a memory address as an operand to reference that memory location. */
2405 frv_print_operand_address (FILE * stream, rtx x)
2407 if (GET_CODE (x) == MEM)
2410 switch (GET_CODE (x))
2413 fputs (reg_names [ REGNO (x)], stream);
2417 fprintf (stream, "%ld", (long) INTVAL (x));
2421 assemble_name (stream, XSTR (x, 0));
2426 output_addr_const (stream, x);
2433 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2438 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2440 int regno = true_regnum (x);
2442 fputs (reg_names[regno], stream);
2444 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2447 /* Print a memory reference suitable for the ld/st instructions. */
2450 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2452 struct frv_unspec unspec;
2456 switch (GET_CODE (x))
2463 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2465 x1 = XEXP (XEXP (x, 1), 1);
2475 if (GET_CODE (x0) == CONST_INT)
2483 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2492 else if (GET_CODE (x1) != CONST_INT)
2493 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2496 fputs ("@(", stream);
2498 fputs (reg_names[GPR_R0], stream);
2499 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2500 frv_print_operand_memory_reference_reg (stream, x0);
2502 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2504 fputs (",", stream);
2506 fputs (reg_names [GPR_R0], stream);
2510 switch (GET_CODE (x1))
2514 frv_print_operand_memory_reference_reg (stream, x1);
2518 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2522 if (!frv_const_unspec_p (x1, &unspec))
2523 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2524 frv_output_const_unspec (stream, &unspec);
2528 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2532 fputs (")", stream);
2536 /* Return 2 for likely branches and 0 for non-likely branches */
2538 #define FRV_JUMP_LIKELY 2
2539 #define FRV_JUMP_NOT_LIKELY 0
2542 frv_print_operand_jump_hint (rtx insn)
2547 HOST_WIDE_INT prob = -1;
2548 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2550 if (GET_CODE (insn) != JUMP_INSN)
2553 /* Assume any non-conditional jump is likely. */
2554 if (! any_condjump_p (insn))
2555 ret = FRV_JUMP_LIKELY;
2559 labelref = condjump_label (insn);
2562 rtx label = XEXP (labelref, 0);
2563 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2568 note = find_reg_note (insn, REG_BR_PROB, 0);
2570 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2574 prob = INTVAL (XEXP (note, 0));
2575 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2577 : FRV_JUMP_NOT_LIKELY);
2589 case UNKNOWN: direction = "unknown jump direction"; break;
2590 case BACKWARD: direction = "jump backward"; break;
2591 case FORWARD: direction = "jump forward"; break;
2595 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2596 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2597 (long)INSN_UID (insn), direction, (long)prob,
2598 (long)REG_BR_PROB_BASE, ret);
2606 /* Print an operand to an assembler instruction.
2608 `%' followed by a letter and a digit says to output an operand in an
2609 alternate fashion. Four letters have standard, built-in meanings described
2610 below. The machine description macro `PRINT_OPERAND' can define additional
2611 letters with nonstandard meanings.
2613 `%cDIGIT' can be used to substitute an operand that is a constant value
2614 without the syntax that normally indicates an immediate operand.
2616 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2619 `%aDIGIT' can be used to substitute an operand as if it were a memory
2620 reference, with the actual operand treated as the address. This may be
2621 useful when outputting a "load address" instruction, because often the
2622 assembler syntax for such an instruction requires you to write the operand
2623 as if it were a memory reference.
2625 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2627 `%=' outputs a number which is unique to each instruction in the entire
2628 compilation. This is useful for making local labels to be referred to more
2629 than once in a single template that generates multiple assembler
2632 `%' followed by a punctuation character specifies a substitution that does
2633 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2634 assembler code. Other nonstandard cases can be defined in the
2635 `PRINT_OPERAND' macro. You must also define which punctuation characters
2636 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2639 frv_print_operand (FILE * file, rtx x, int code)
2641 struct frv_unspec unspec;
2642 HOST_WIDE_INT value;
2645 if (code != 0 && !isalpha (code))
2648 else if (GET_CODE (x) == CONST_INT)
2651 else if (GET_CODE (x) == CONST_DOUBLE)
2653 if (GET_MODE (x) == SFmode)
2658 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2659 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2663 else if (GET_MODE (x) == VOIDmode)
2664 value = CONST_DOUBLE_LOW (x);
2667 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2678 fputs (reg_names[GPR_R0], file);
2682 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2686 /* Output small data area base register (gr16). */
2687 fputs (reg_names[SDA_BASE_REG], file);
2691 /* Output pic register (gr17). */
2692 fputs (reg_names[PIC_REGNO], file);
2696 /* Output the temporary integer CCR register. */
2697 fputs (reg_names[ICR_TEMP], file);
2701 /* Output the temporary integer CC register. */
2702 fputs (reg_names[ICC_TEMP], file);
2705 /* case 'a': print an address. */
2708 /* Print appropriate test for integer branch false operation. */
2709 switch (GET_CODE (x))
2712 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
2714 case EQ: fputs ("ne", file); break;
2715 case NE: fputs ("eq", file); break;
2716 case LT: fputs ("ge", file); break;
2717 case LE: fputs ("gt", file); break;
2718 case GT: fputs ("le", file); break;
2719 case GE: fputs ("lt", file); break;
2720 case LTU: fputs ("nc", file); break;
2721 case LEU: fputs ("hi", file); break;
2722 case GTU: fputs ("ls", file); break;
2723 case GEU: fputs ("c", file); break;
2727 /* case 'c': print a constant without the constant prefix. If
2728 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2731 /* Print appropriate test for integer branch true operation. */
2732 switch (GET_CODE (x))
2735 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
2737 case EQ: fputs ("eq", file); break;
2738 case NE: fputs ("ne", file); break;
2739 case LT: fputs ("lt", file); break;
2740 case LE: fputs ("le", file); break;
2741 case GT: fputs ("gt", file); break;
2742 case GE: fputs ("ge", file); break;
2743 case LTU: fputs ("c", file); break;
2744 case LEU: fputs ("ls", file); break;
2745 case GTU: fputs ("hi", file); break;
2746 case GEU: fputs ("nc", file); break;
2751 /* Print 1 for a NE and 0 for an EQ to give the final argument
2752 for a conditional instruction. */
2753 if (GET_CODE (x) == NE)
2756 else if (GET_CODE (x) == EQ)
2760 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2764 /* Print appropriate test for floating point branch false operation. */
2765 switch (GET_CODE (x))
2768 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2770 case EQ: fputs ("ne", file); break;
2771 case NE: fputs ("eq", file); break;
2772 case LT: fputs ("uge", file); break;
2773 case LE: fputs ("ug", file); break;
2774 case GT: fputs ("ule", file); break;
2775 case GE: fputs ("ul", file); break;
2780 /* Print appropriate test for floating point branch true operation. */
2781 switch (GET_CODE (x))
2784 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2786 case EQ: fputs ("eq", file); break;
2787 case NE: fputs ("ne", file); break;
2788 case LT: fputs ("lt", file); break;
2789 case LE: fputs ("le", file); break;
2790 case GT: fputs ("gt", file); break;
2791 case GE: fputs ("ge", file); break;
2796 /* Print appropriate GOT function. */
2797 if (GET_CODE (x) != CONST_INT)
2798 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2799 fputs (unspec_got_name (INTVAL (x)), file);
2803 /* Print 'i' if the operand is a constant, or is a memory reference that
2805 if (GET_CODE (x) == MEM)
2806 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2807 ? XEXP (XEXP (x, 0), 1)
2809 else if (GET_CODE (x) == PLUS)
2812 switch (GET_CODE (x))
2826 /* For jump instructions, print 'i' if the operand is a constant or
2827 is an expression that adds a constant. */
2828 if (GET_CODE (x) == CONST_INT)
2833 if (GET_CODE (x) == CONST_INT
2834 || (GET_CODE (x) == PLUS
2835 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2836 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2842 /* Print the lower register of a double word register pair */
2843 if (GET_CODE (x) == REG)
2844 fputs (reg_names[ REGNO (x)+1 ], file);
2846 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2849 /* case 'l': print a LABEL_REF. */
2853 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2854 for the second word of double memory operations. */
2855 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2856 switch (GET_CODE (x))
2859 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2862 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2870 frv_print_operand_memory_reference (file, x, offset);
2876 /* Print the opcode of a command. */
2877 switch (GET_CODE (x))
2880 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2882 case PLUS: fputs ("add", file); break;
2883 case MINUS: fputs ("sub", file); break;
2884 case AND: fputs ("and", file); break;
2885 case IOR: fputs ("or", file); break;
2886 case XOR: fputs ("xor", file); break;
2887 case ASHIFT: fputs ("sll", file); break;
2888 case ASHIFTRT: fputs ("sra", file); break;
2889 case LSHIFTRT: fputs ("srl", file); break;
2893 /* case 'n': negate and print a constant int. */
2896 /* Print PIC label using operand as the number. */
2897 if (GET_CODE (x) != CONST_INT)
2898 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2900 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2904 /* Print 'u' if the operand is a update load/store. */
2905 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2910 /* If value is 0, print gr0, otherwise it must be a register. */
2911 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2912 fputs (reg_names[GPR_R0], file);
2914 else if (GET_CODE (x) == REG)
2915 fputs (reg_names [REGNO (x)], file);
2918 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2922 /* Print constant in hex. */
2923 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2925 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2932 if (GET_CODE (x) == REG)
2933 fputs (reg_names [REGNO (x)], file);
2935 else if (GET_CODE (x) == CONST_INT
2936 || GET_CODE (x) == CONST_DOUBLE)
2937 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
2939 else if (frv_const_unspec_p (x, &unspec))
2940 frv_output_const_unspec (file, &unspec);
2942 else if (GET_CODE (x) == MEM)
2943 frv_print_operand_address (file, XEXP (x, 0));
2945 else if (CONSTANT_ADDRESS_P (x))
2946 frv_print_operand_address (file, x);
2949 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
2954 fatal_insn ("frv_print_operand: unknown code", x);
2962 /* A C statement (sans semicolon) for initializing the variable CUM for the
2963 state at the beginning of the argument list. The variable has type
2964 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2965 of the function which will receive the args, or 0 if the args are to a
2966 compiler support library function. The value of INDIRECT is nonzero when
2967 processing an indirect call, for example a call through a function pointer.
2968 The value of INDIRECT is zero for a call to an explicitly named function, a
2969 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
2970 arguments for the function being compiled.
2972 When processing a call to a compiler support library function, LIBNAME
2973 identifies which one. It is a `symbol_ref' rtx which contains the name of
2974 the function, as a string. LIBNAME is 0 when an ordinary C function call is
2975 being processed. Thus, each time this macro is called, either LIBNAME or
2976 FNTYPE is nonzero, but never both of them at once. */
2979 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
2985 *cum = FIRST_ARG_REGNUM;
2987 if (TARGET_DEBUG_ARG)
2989 fprintf (stderr, "\ninit_cumulative_args:");
2990 if (!fndecl && fntype)
2991 fputs (" indirect", stderr);
2994 fputs (" incoming", stderr);
2998 tree ret_type = TREE_TYPE (fntype);
2999 fprintf (stderr, " return=%s,",
3000 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3003 if (libname && GET_CODE (libname) == SYMBOL_REF)
3004 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3006 if (cfun->returns_struct)
3007 fprintf (stderr, " return-struct");
3009 putc ('\n', stderr);
3014 /* Return true if we should pass an argument on the stack rather than
3018 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3020 if (mode == BLKmode)
3024 return AGGREGATE_TYPE_P (type);
3027 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3028 argument with the specified mode and type. If it is not defined,
3029 `PARM_BOUNDARY' is used for all arguments. */
3032 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3033 tree type ATTRIBUTE_UNUSED)
3035 return BITS_PER_WORD;
3039 frv_function_arg (CUMULATIVE_ARGS *cum,
3040 enum machine_mode mode,
3041 tree type ATTRIBUTE_UNUSED,
3043 int incoming ATTRIBUTE_UNUSED)
3045 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3050 /* Return a marker for use in the call instruction. */
3051 if (xmode == VOIDmode)
3057 else if (arg_num <= LAST_ARG_REGNUM)
3059 ret = gen_rtx_REG (xmode, arg_num);
3060 debstr = reg_names[arg_num];
3069 if (TARGET_DEBUG_ARG)
3071 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3072 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3078 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3079 advance past an argument in the argument list. The values MODE, TYPE and
3080 NAMED describe that argument. Once this is done, the variable CUM is
3081 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3083 This macro need not do anything if the argument in question was passed on
3084 the stack. The compiler knows how to track the amount of stack space used
3085 for arguments without any special help. */
3088 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3089 enum machine_mode mode,
3090 tree type ATTRIBUTE_UNUSED,
3093 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3094 int bytes = GET_MODE_SIZE (xmode);
3095 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3098 *cum = arg_num + words;
3100 if (TARGET_DEBUG_ARG)
3102 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3103 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3107 /* A C expression for the number of words, at the beginning of an argument,
3108 must be put in registers. The value must be zero for arguments that are
3109 passed entirely in registers or that are entirely pushed on the stack.
3111 On some machines, certain arguments must be passed partially in registers
3112 and partially in memory. On these machines, typically the first N words of
3113 arguments are passed in registers, and the rest on the stack. If a
3114 multi-word argument (a `double' or a structure) crosses that boundary, its
3115 first few words must be passed in registers and the rest must be pushed.
3116 This macro tells the compiler when this occurs, and how many of the words
3117 should go in registers.
3119 `FUNCTION_ARG' for these arguments should return the first register to be
3120 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3121 the called function. */
3124 frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum,
3125 enum machine_mode mode,
3126 tree type ATTRIBUTE_UNUSED,
3127 int named ATTRIBUTE_UNUSED)
3129 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3130 int bytes = GET_MODE_SIZE (xmode);
3131 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3135 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3136 ? LAST_ARG_REGNUM - arg_num + 1
3139 if (TARGET_DEBUG_ARG && ret)
3140 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3147 /* If defined, a C expression that indicates when it is the called function's
3148 responsibility to make a copy of arguments passed by invisible reference.
3149 Normally, the caller makes a copy and passes the address of the copy to the
3150 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3151 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3152 the "live" value. The called function must not modify this value. If it
3153 can be determined that the value won't be modified, it need not make a copy;
3154 otherwise a copy must be made. */
3157 frv_function_arg_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3158 enum machine_mode mode ATTRIBUTE_UNUSED,
3159 tree type ATTRIBUTE_UNUSED,
3160 int named ATTRIBUTE_UNUSED)
3166 /* Return true if a register is ok to use as a base or index register. */
3168 static FRV_INLINE int
3169 frv_regno_ok_for_base_p (int regno, int strict_p)
3175 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3177 if (regno == ARG_POINTER_REGNUM)
3180 return (regno >= FIRST_PSEUDO_REGISTER);
3184 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3185 RTX) is a legitimate memory address on the target machine for a memory
3186 operand of mode MODE.
3188 It usually pays to define several simpler macros to serve as subroutines for
3189 this one. Otherwise it may be too complicated to understand.
3191 This macro must exist in two variants: a strict variant and a non-strict
3192 one. The strict variant is used in the reload pass. It must be defined so
3193 that any pseudo-register that has not been allocated a hard register is
3194 considered a memory reference. In contexts where some kind of register is
3195 required, a pseudo-register with no hard register must be rejected.
3197 The non-strict variant is used in other passes. It must be defined to
3198 accept all pseudo-registers in every context where some kind of register is
3201 Compiler source files that want to use the strict variant of this macro
3202 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3203 conditional to define the strict variant in that case and the non-strict
3206 Subroutines to check for acceptable registers for various purposes (one for
3207 base registers, one for index registers, and so on) are typically among the
3208 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3209 subroutine macros need have two variants; the higher levels of macros may be
3210 the same whether strict or not.
3212 Normally, constant addresses which are the sum of a `symbol_ref' and an
3213 integer are stored inside a `const' RTX to mark them as constant.
3214 Therefore, there is no need to recognize such sums specifically as
3215 legitimate addresses. Normally you would simply recognize any `const' as
3218 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3219 are not marked with `const'. It assumes that a naked `plus' indicates
3220 indexing. If so, then you *must* reject such naked constant sums as
3221 illegitimate addresses, so that none of them will be given to
3222 `PRINT_OPERAND_ADDRESS'.
3224 On some machines, whether a symbolic address is legitimate depends on the
3225 section that the address refers to. On these machines, define the macro
3226 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3227 then check for it here. When you see a `const', you will have to look
3228 inside it to find the `symbol_ref' in order to determine the section.
3230 The best way to modify the name string is by adding text to the beginning,
3231 with suitable punctuation to prevent any ambiguity. Allocate the new name
3232 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3233 remove and decode the added text and output the name accordingly, and define
3234 `(* targetm.strip_name_encoding)' to access the original name string.
3236 You can check the information stored here into the `symbol_ref' in the
3237 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3238 `PRINT_OPERAND_ADDRESS'. */
3241 frv_legitimate_address_p (enum machine_mode mode,
3245 int allow_double_reg_p)
3249 HOST_WIDE_INT value;
3252 switch (GET_CODE (x))
3259 if (GET_CODE (x) != REG)
3265 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3271 if (GET_CODE (x0) != REG
3272 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3273 || GET_CODE (x1) != PLUS
3274 || ! rtx_equal_p (x0, XEXP (x1, 0))
3275 || GET_CODE (XEXP (x1, 1)) != REG
3276 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3283 /* 12 bit immediate */
3288 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3290 /* If we can't use load/store double operations, make sure we can
3291 address the second word. */
3292 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3293 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3302 if (GET_CODE (x0) == SUBREG)
3303 x0 = SUBREG_REG (x0);
3305 if (GET_CODE (x0) != REG)
3308 regno0 = REGNO (x0);
3309 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3312 switch (GET_CODE (x1))
3318 x1 = SUBREG_REG (x1);
3319 if (GET_CODE (x1) != REG)
3325 /* Do not allow reg+reg addressing for modes > 1 word if we
3326 can't depend on having move double instructions. */
3327 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3330 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3334 /* 12 bit immediate */
3339 value = INTVAL (x1);
3340 ret = IN_RANGE_P (value, -2048, 2047);
3342 /* If we can't use load/store double operations, make sure we can
3343 address the second word. */
3344 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3345 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3350 if (!condexec_p && got12_operand (x1, VOIDmode))
3358 if (TARGET_DEBUG_ADDR)
3360 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3361 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3362 (condexec_p) ? ", inside conditional code" : "");
3370 /* Test whether a local function descriptor is canonical, i.e.,
3371 whether we can use FUNCDESC_GOTOFF to compute the address of the
3375 frv_local_funcdesc_p (rtx fnx)
3378 enum symbol_visibility vis;
3381 if (! SYMBOL_REF_LOCAL_P (fnx))
3384 fn = SYMBOL_REF_DECL (fnx);
3389 vis = DECL_VISIBILITY (fn);
3391 if (vis == VISIBILITY_PROTECTED)
3392 /* Private function descriptors for protected functions are not
3393 canonical. Temporarily change the visibility to global. */
3394 vis = VISIBILITY_DEFAULT;
3395 else if (flag_shlib)
3396 /* If we're already compiling for a shared library (that, unlike
3397 executables, can't assume that the existence of a definition
3398 implies local binding), we can skip the re-testing. */
3401 ret = default_binds_local_p_1 (fn, flag_pic);
3403 DECL_VISIBILITY (fn) = vis;
3408 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3412 frv_gen_GPsym2reg (rtx dest, rtx src)
3414 tree gp = get_identifier ("_gp");
3415 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3417 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3421 unspec_got_name (int i)
3425 case R_FRV_GOT12: return "got12";
3426 case R_FRV_GOTHI: return "gothi";
3427 case R_FRV_GOTLO: return "gotlo";
3428 case R_FRV_FUNCDESC: return "funcdesc";
3429 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3430 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3431 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3432 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3433 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3434 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3435 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3436 case R_FRV_GOTOFF12: return "gotoff12";
3437 case R_FRV_GOTOFFHI: return "gotoffhi";
3438 case R_FRV_GOTOFFLO: return "gotofflo";
3439 case R_FRV_GPREL12: return "gprel12";
3440 case R_FRV_GPRELHI: return "gprelhi";
3441 case R_FRV_GPRELLO: return "gprello";
3446 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3447 is added inside the relocation operator. */
3450 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3452 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3453 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3454 fputs (")", stream);
3457 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3458 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3459 otherwise return ORIG_X. */
3462 frv_find_base_term (rtx x)
3464 struct frv_unspec unspec;
3466 if (frv_const_unspec_p (x, &unspec)
3467 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3468 return plus_constant (unspec.symbol, unspec.offset);
3473 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3474 the operand is used by a predicated instruction. */
3477 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3479 return ((GET_MODE (op) == mode || mode == VOIDmode)
3480 && GET_CODE (op) == MEM
3481 && frv_legitimate_address_p (mode, XEXP (op, 0),
3482 reload_completed, condexec_p, FALSE));
3486 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3488 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3489 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3495 rvrtx = operands[0];
3499 addr = XEXP (operands[0], 0);
3501 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3502 any calls that would involve a PLT, but can't tell, since we
3503 don't know whether an extern function is going to be provided by
3504 a separate translation unit or imported from a separate module.
3505 When compiling for shared libraries, if the function has default
3506 visibility, we assume it's overridable, so we inline the PLT, but
3507 for executables, we don't really have a way to make a good
3508 decision: a function is as likely to be imported from a shared
3509 library as it is to be defined in the executable itself. We
3510 assume executables will get global functions defined locally,
3511 whereas shared libraries will have them potentially overridden,
3512 so we only inline PLTs when compiling for shared libraries.
3514 In order to mark a function as local to a shared library, any
3515 non-default visibility attribute suffices. Unfortunately,
3516 there's no simple way to tag a function declaration as ``in a
3517 different module'', which we could then use to trigger PLT
3518 inlining on executables. There's -minline-plt, but it affects
3519 all external functions, so one would have to also mark function
3520 declarations available in the same module with non-default
3521 visibility, which is advantageous in itself. */
3522 if (GET_CODE (addr) == SYMBOL_REF
3523 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3527 dest = gen_reg_rtx (SImode);
3529 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3530 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3532 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3533 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3535 cfun->uses_pic_offset_table = TRUE;
3538 else if (GET_CODE (addr) == SYMBOL_REF)
3540 /* These are always either local, or handled through a local
3543 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3544 operands[2], picreg, lr);
3546 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3550 else if (! ldd_address_operand (addr, Pmode))
3551 addr = force_reg (Pmode, addr);
3553 picreg = gen_reg_rtx (DImode);
3554 emit_insn (gen_movdi_ldd (picreg, addr));
3556 if (sibcall && ret_value)
3557 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3559 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3561 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3563 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3567 /* An address operand that may use a pair of registers, an addressing
3568 mode that we reject in general. */
3571 ldd_address_operand (rtx x, enum machine_mode mode)
3573 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3576 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3580 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3582 if (GET_MODE (op) != mode && mode != VOIDmode)
3584 if (GET_CODE (op) != REG)
3586 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3591 /* Return 1 is OP is a memory operand, or will be turned into one by
3595 frv_load_operand (rtx op, enum machine_mode mode)
3597 if (GET_MODE (op) != mode && mode != VOIDmode)
3600 if (reload_in_progress)
3603 if (GET_CODE (tmp) == SUBREG)
3604 tmp = SUBREG_REG (tmp);
3605 if (GET_CODE (tmp) == REG
3606 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3607 op = reg_equiv_memory_loc[REGNO (tmp)];
3610 return op && memory_operand (op, mode);
3614 /* Return 1 if operand is a GPR register or a FPR register. */
3617 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3621 if (GET_MODE (op) != mode && mode != VOIDmode)
3624 if (GET_CODE (op) == SUBREG)
3626 if (GET_CODE (SUBREG_REG (op)) != REG)
3627 return register_operand (op, mode);
3629 op = SUBREG_REG (op);
3632 if (GET_CODE (op) != REG)
3636 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3642 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3645 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3647 if (GET_CODE (op) == CONST_INT)
3648 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3650 if (got12_operand (op, mode))
3653 if (GET_MODE (op) != mode && mode != VOIDmode)
3656 if (GET_CODE (op) == SUBREG)
3658 if (GET_CODE (SUBREG_REG (op)) != REG)
3659 return register_operand (op, mode);
3661 op = SUBREG_REG (op);
3664 if (GET_CODE (op) != REG)
3667 return GPR_OR_PSEUDO_P (REGNO (op));
3670 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3671 signed immediate. */
3674 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3678 if (GET_CODE (op) == CONST_INT)
3679 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3681 if (GET_MODE (op) != mode && mode != VOIDmode)
3684 if (GET_CODE (op) == SUBREG)
3686 if (GET_CODE (SUBREG_REG (op)) != REG)
3687 return register_operand (op, mode);
3689 op = SUBREG_REG (op);
3692 if (GET_CODE (op) != REG)
3696 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3702 /* Return 1 if operand is a register or 6 bit signed immediate. */
3705 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3707 if (GET_CODE (op) == CONST_INT)
3708 return IN_RANGE_P (INTVAL (op), -32, 31);
3710 if (GET_MODE (op) != mode && mode != VOIDmode)
3713 if (GET_CODE (op) == SUBREG)
3715 if (GET_CODE (SUBREG_REG (op)) != REG)
3716 return register_operand (op, mode);
3718 op = SUBREG_REG (op);
3721 if (GET_CODE (op) != REG)
3724 return FPR_OR_PSEUDO_P (REGNO (op));
3727 /* Return 1 if operand is a register or 10 bit signed immediate. */
3730 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3732 if (GET_CODE (op) == CONST_INT)
3733 return IN_RANGE_P (INTVAL (op), -512, 511);
3735 if (GET_MODE (op) != mode && mode != VOIDmode)
3738 if (GET_CODE (op) == SUBREG)
3740 if (GET_CODE (SUBREG_REG (op)) != REG)
3741 return register_operand (op, mode);
3743 op = SUBREG_REG (op);
3746 if (GET_CODE (op) != REG)
3749 return GPR_OR_PSEUDO_P (REGNO (op));
3752 /* Return 1 if operand is a register or an integer immediate. */
3755 gpr_or_int_operand (rtx op, enum machine_mode mode)
3757 if (GET_CODE (op) == CONST_INT)
3760 if (GET_MODE (op) != mode && mode != VOIDmode)
3763 if (GET_CODE (op) == SUBREG)
3765 if (GET_CODE (SUBREG_REG (op)) != REG)
3766 return register_operand (op, mode);
3768 op = SUBREG_REG (op);
3771 if (GET_CODE (op) != REG)
3774 return GPR_OR_PSEUDO_P (REGNO (op));
3777 /* Return 1 if operand is a 12 bit signed immediate. */
3780 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3782 if (GET_CODE (op) != CONST_INT)
3785 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3788 /* Return 1 if operand is a 6 bit signed immediate. */
3791 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3793 if (GET_CODE (op) != CONST_INT)
3796 return IN_RANGE_P (INTVAL (op), -32, 31);
3799 /* Return 1 if operand is a 5 bit signed immediate. */
3802 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3804 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3807 /* Return 1 if operand is a 5 bit unsigned immediate. */
3810 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3812 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3815 /* Return 1 if operand is a 4 bit unsigned immediate. */
3818 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3820 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3823 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3826 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3828 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3831 /* Return 1 if operand is an integer constant that takes 2 instructions
3832 to load up and can be split into sethi/setlo instructions.. */
3835 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3837 HOST_WIDE_INT value;
3841 switch (GET_CODE (op))
3850 return (flag_pic == 0);
3853 if (flag_pic || TARGET_FDPIC)
3857 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3859 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
3865 /* small data references are already 1 word */
3866 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3869 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3872 if (GET_MODE (op) == SFmode)
3874 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3875 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3877 return ! IN_RANGE_P (value, -32768, 32767);
3879 else if (GET_MODE (op) == VOIDmode)
3881 value = CONST_DOUBLE_LOW (op);
3882 return ! IN_RANGE_P (value, -32768, 32767);
3890 /* Return 1 if operand is a 16 bit unsigned immediate. */
3893 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3895 if (GET_CODE (op) != CONST_INT)
3898 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3901 /* Return 1 if operand is an integer constant with the bottom 16 bits
3905 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3907 if (GET_CODE (op) != CONST_INT)
3910 return ((INTVAL (op) & 0xffff) == 0);
3913 /* Return true if operand is a GPR register. */
3916 integer_register_operand (rtx op, enum machine_mode mode)
3918 if (GET_MODE (op) != mode && mode != VOIDmode)
3921 if (GET_CODE (op) == SUBREG)
3923 if (GET_CODE (SUBREG_REG (op)) != REG)
3924 return register_operand (op, mode);
3926 op = SUBREG_REG (op);
3929 if (GET_CODE (op) != REG)
3932 return GPR_OR_PSEUDO_P (REGNO (op));
3935 /* Return true if operand is a GPR register. Do not allow SUBREG's
3936 here, in order to prevent a combine bug. */
3939 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
3941 if (GET_MODE (op) != mode && mode != VOIDmode)
3944 if (GET_CODE (op) != REG)
3947 return GPR_OR_PSEUDO_P (REGNO (op));
3950 /* Return true if operand is a FPR register. */
3953 fpr_operand (rtx op, enum machine_mode mode)
3955 if (GET_MODE (op) != mode && mode != VOIDmode)
3958 if (GET_CODE (op) == SUBREG)
3960 if (GET_CODE (SUBREG_REG (op)) != REG)
3961 return register_operand (op, mode);
3963 op = SUBREG_REG (op);
3966 if (GET_CODE (op) != REG)
3969 return FPR_OR_PSEUDO_P (REGNO (op));
3972 /* Return true if operand is an even GPR or FPR register. */
3975 even_reg_operand (rtx op, enum machine_mode mode)
3979 if (GET_MODE (op) != mode && mode != VOIDmode)
3982 if (GET_CODE (op) == SUBREG)
3984 if (GET_CODE (SUBREG_REG (op)) != REG)
3985 return register_operand (op, mode);
3987 op = SUBREG_REG (op);
3990 if (GET_CODE (op) != REG)
3994 if (regno >= FIRST_PSEUDO_REGISTER)
3998 return (((regno - GPR_FIRST) & 1) == 0);
4001 return (((regno - FPR_FIRST) & 1) == 0);
4006 /* Return true if operand is an odd GPR register. */
4009 odd_reg_operand (rtx op, enum machine_mode mode)
4013 if (GET_MODE (op) != mode && mode != VOIDmode)
4016 if (GET_CODE (op) == SUBREG)
4018 if (GET_CODE (SUBREG_REG (op)) != REG)
4019 return register_operand (op, mode);
4021 op = SUBREG_REG (op);
4024 if (GET_CODE (op) != REG)
4028 /* Assume that reload will give us an even register. */
4029 if (regno >= FIRST_PSEUDO_REGISTER)
4033 return (((regno - GPR_FIRST) & 1) != 0);
4036 return (((regno - FPR_FIRST) & 1) != 0);
4041 /* Return true if operand is an even GPR register. */
4044 even_gpr_operand (rtx op, enum machine_mode mode)
4048 if (GET_MODE (op) != mode && mode != VOIDmode)
4051 if (GET_CODE (op) == SUBREG)
4053 if (GET_CODE (SUBREG_REG (op)) != REG)
4054 return register_operand (op, mode);
4056 op = SUBREG_REG (op);
4059 if (GET_CODE (op) != REG)
4063 if (regno >= FIRST_PSEUDO_REGISTER)
4066 if (! GPR_P (regno))
4069 return (((regno - GPR_FIRST) & 1) == 0);
4072 /* Return true if operand is an odd GPR register. */
4075 odd_gpr_operand (rtx op, enum machine_mode mode)
4079 if (GET_MODE (op) != mode && mode != VOIDmode)
4082 if (GET_CODE (op) == SUBREG)
4084 if (GET_CODE (SUBREG_REG (op)) != REG)
4085 return register_operand (op, mode);
4087 op = SUBREG_REG (op);
4090 if (GET_CODE (op) != REG)
4094 /* Assume that reload will give us an even register. */
4095 if (regno >= FIRST_PSEUDO_REGISTER)
4098 if (! GPR_P (regno))
4101 return (((regno - GPR_FIRST) & 1) != 0);
4104 /* Return true if operand is a quad aligned FPR register. */
4107 quad_fpr_operand (rtx op, enum machine_mode mode)
4111 if (GET_MODE (op) != mode && mode != VOIDmode)
4114 if (GET_CODE (op) == SUBREG)
4116 if (GET_CODE (SUBREG_REG (op)) != REG)
4117 return register_operand (op, mode);
4119 op = SUBREG_REG (op);
4122 if (GET_CODE (op) != REG)
4126 if (regno >= FIRST_PSEUDO_REGISTER)
4129 if (! FPR_P (regno))
4132 return (((regno - FPR_FIRST) & 3) == 0);
4135 /* Return true if operand is an even FPR register. */
4138 even_fpr_operand (rtx op, enum machine_mode mode)
4142 if (GET_MODE (op) != mode && mode != VOIDmode)
4145 if (GET_CODE (op) == SUBREG)
4147 if (GET_CODE (SUBREG_REG (op)) != REG)
4148 return register_operand (op, mode);
4150 op = SUBREG_REG (op);
4153 if (GET_CODE (op) != REG)
4157 if (regno >= FIRST_PSEUDO_REGISTER)
4160 if (! FPR_P (regno))
4163 return (((regno - FPR_FIRST) & 1) == 0);
4166 /* Return true if operand is an odd FPR register. */
4169 odd_fpr_operand (rtx op, enum machine_mode mode)
4173 if (GET_MODE (op) != mode && mode != VOIDmode)
4176 if (GET_CODE (op) == SUBREG)
4178 if (GET_CODE (SUBREG_REG (op)) != REG)
4179 return register_operand (op, mode);
4181 op = SUBREG_REG (op);
4184 if (GET_CODE (op) != REG)
4188 /* Assume that reload will give us an even register. */
4189 if (regno >= FIRST_PSEUDO_REGISTER)
4192 if (! FPR_P (regno))
4195 return (((regno - FPR_FIRST) & 1) != 0);
4198 /* Return true if operand is a 2 word memory address that can be loaded in one
4199 instruction to load or store. We assume the stack and frame pointers are
4200 suitably aligned, and variables in the small data area. FIXME -- at some we
4201 should recognize other globals and statics. We can't assume that any old
4202 pointer is aligned, given that arguments could be passed on an odd word on
4203 the stack and the address taken and passed through to another function. */
4206 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4214 if (GET_CODE (op) != MEM)
4217 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4220 addr = XEXP (op, 0);
4221 if (GET_CODE (addr) == REG)
4224 else if (GET_CODE (addr) == PLUS)
4226 rtx addr0 = XEXP (addr, 0);
4227 rtx addr1 = XEXP (addr, 1);
4229 if (GET_CODE (addr0) != REG)
4232 if (got12_operand (addr1, VOIDmode))
4235 if (GET_CODE (addr1) != CONST_INT)
4238 if ((INTVAL (addr1) & 7) != 0)
4247 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4253 /* Return true if operand is a 2 word memory address that needs to
4254 use two instructions to load or store. */
4257 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4259 if (GET_CODE (op) != MEM)
4262 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4268 return ! dbl_memory_one_insn_operand (op, mode);
4271 /* Return true if operand is something that can be an output for a move
4275 move_destination_operand (rtx op, enum machine_mode mode)
4280 switch (GET_CODE (op))
4286 if (GET_MODE (op) != mode && mode != VOIDmode)
4289 subreg = SUBREG_REG (op);
4290 code = GET_CODE (subreg);
4292 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4293 reload_completed, FALSE, FALSE);
4295 return (code == REG);
4298 if (GET_MODE (op) != mode && mode != VOIDmode)
4304 return frv_legitimate_memory_operand (op, mode, FALSE);
4310 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4311 process these separately from any offsets, such that we add any
4312 offsets to the function descriptor (the actual pointer), not to the
4313 function address. */
4316 frv_function_symbol_referenced_p (rtx x)
4322 if (GET_CODE (x) == SYMBOL_REF)
4323 return SYMBOL_REF_FUNCTION_P (x);
4325 length = GET_RTX_LENGTH (GET_CODE (x));
4326 format = GET_RTX_FORMAT (GET_CODE (x));
4328 for (j = 0; j < length; ++j)
4333 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4339 if (XVEC (x, j) != 0)
4342 for (k = 0; k < XVECLEN (x, j); ++k)
4343 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4349 /* Nothing to do. */
4357 /* Return true if operand is something that can be an input for a move
4361 move_source_operand (rtx op, enum machine_mode mode)
4366 switch (GET_CODE (op))
4373 return immediate_operand (op, mode);
4376 if (GET_MODE (op) != mode && mode != VOIDmode)
4379 subreg = SUBREG_REG (op);
4380 code = GET_CODE (subreg);
4382 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4383 reload_completed, FALSE, FALSE);
4385 return (code == REG);
4388 if (GET_MODE (op) != mode && mode != VOIDmode)
4394 return frv_legitimate_memory_operand (op, mode, FALSE);
4400 /* Return true if operand is something that can be an output for a conditional
4404 condexec_dest_operand (rtx op, enum machine_mode mode)
4409 switch (GET_CODE (op))
4415 if (GET_MODE (op) != mode && mode != VOIDmode)
4418 subreg = SUBREG_REG (op);
4419 code = GET_CODE (subreg);
4421 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4422 reload_completed, TRUE, FALSE);
4424 return (code == REG);
4427 if (GET_MODE (op) != mode && mode != VOIDmode)
4433 return frv_legitimate_memory_operand (op, mode, TRUE);
4439 /* Return true if operand is something that can be an input for a conditional
4443 condexec_source_operand (rtx op, enum machine_mode mode)
4448 switch (GET_CODE (op))
4458 if (GET_MODE (op) != mode && mode != VOIDmode)
4461 subreg = SUBREG_REG (op);
4462 code = GET_CODE (subreg);
4464 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4465 reload_completed, TRUE, FALSE);
4467 return (code == REG);
4470 if (GET_MODE (op) != mode && mode != VOIDmode)
4476 return frv_legitimate_memory_operand (op, mode, TRUE);
4482 /* Return true if operand is a register of any flavor or a 0 of the
4483 appropriate type. */
4486 reg_or_0_operand (rtx op, enum machine_mode mode)
4488 switch (GET_CODE (op))
4495 if (GET_MODE (op) != mode && mode != VOIDmode)
4498 return register_operand (op, mode);
4508 /* Return true if operand is the link register. */
4511 lr_operand (rtx op, enum machine_mode mode)
4513 if (GET_CODE (op) != REG)
4516 if (GET_MODE (op) != mode && mode != VOIDmode)
4519 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4525 /* Return true if operand is the uClinux PIC register. */
4528 fdpic_operand (rtx op, enum machine_mode mode)
4533 if (GET_CODE (op) != REG)
4536 if (GET_MODE (op) != mode && mode != VOIDmode)
4539 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4546 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4548 struct frv_unspec unspec;
4550 if (frv_const_unspec_p (op, &unspec))
4551 switch (unspec.reloc)
4554 case R_FRV_GOTOFF12:
4555 case R_FRV_FUNCDESC_GOT12:
4556 case R_FRV_FUNCDESC_GOTOFF12:
4563 /* Return true if OP is a valid const-unspec expression. */
4566 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4568 struct frv_unspec unspec;
4570 return frv_const_unspec_p (op, &unspec);
4572 /* Return true if operand is a gpr register or a valid memory operation. */
4575 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4577 return (integer_register_operand (op, mode)
4578 || frv_legitimate_memory_operand (op, mode, FALSE));
4581 /* Return true if operand is a fpr register or a valid memory operation. */
4584 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4586 return (fpr_operand (op, mode)
4587 || frv_legitimate_memory_operand (op, mode, FALSE));
4590 /* Return true if operand is an icc register. */
4593 icc_operand (rtx op, enum machine_mode mode)
4597 if (GET_MODE (op) != mode && mode != VOIDmode)
4600 if (GET_CODE (op) != REG)
4604 return ICC_OR_PSEUDO_P (regno);
4607 /* Return true if operand is an fcc register. */
4610 fcc_operand (rtx op, enum machine_mode mode)
4614 if (GET_MODE (op) != mode && mode != VOIDmode)
4617 if (GET_CODE (op) != REG)
4621 return FCC_OR_PSEUDO_P (regno);
4624 /* Return true if operand is either an fcc or icc register. */
4627 cc_operand (rtx op, enum machine_mode mode)
4631 if (GET_MODE (op) != mode && mode != VOIDmode)
4634 if (GET_CODE (op) != REG)
4638 if (CC_OR_PSEUDO_P (regno))
4644 /* Return true if operand is an integer CCR register. */
4647 icr_operand (rtx op, enum machine_mode mode)
4651 if (GET_MODE (op) != mode && mode != VOIDmode)
4654 if (GET_CODE (op) != REG)
4658 return ICR_OR_PSEUDO_P (regno);
4661 /* Return true if operand is an fcc register. */
4664 fcr_operand (rtx op, enum machine_mode mode)
4668 if (GET_MODE (op) != mode && mode != VOIDmode)
4671 if (GET_CODE (op) != REG)
4675 return FCR_OR_PSEUDO_P (regno);
4678 /* Return true if operand is either an fcc or icc register. */
4681 cr_operand (rtx op, enum machine_mode mode)
4685 if (GET_MODE (op) != mode && mode != VOIDmode)
4688 if (GET_CODE (op) != REG)
4692 if (CR_OR_PSEUDO_P (regno))
4698 /* Return true if operand is a memory reference suitable for a call. */
4701 call_operand (rtx op, enum machine_mode mode)
4703 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4706 if (GET_CODE (op) == SYMBOL_REF)
4709 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4710 never occur anyway), but prevents reload from not handling the case
4711 properly of a call through a pointer on a function that calls
4712 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4713 return gpr_or_int12_operand (op, mode);
4716 /* Return true if operand is a memory reference suitable for a sibcall. */
4719 sibcall_operand (rtx op, enum machine_mode mode)
4721 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4724 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4725 never occur anyway), but prevents reload from not handling the case
4726 properly of a call through a pointer on a function that calls
4727 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4728 return gpr_or_int12_operand (op, mode);
4731 /* Return true if operator is a kind of relational operator. */
4734 relational_operator (rtx op, enum machine_mode mode)
4740 if (mode != VOIDmode && mode != GET_MODE (op))
4743 switch (GET_CODE (op))
4762 if (op1 != const0_rtx)
4766 if (GET_CODE (op0) != REG)
4769 regno = REGNO (op0);
4770 switch (GET_MODE (op0))
4777 return ICC_OR_PSEUDO_P (regno);
4780 return FCC_OR_PSEUDO_P (regno);
4783 return CR_OR_PSEUDO_P (regno);
4789 /* Return true if operator is a signed integer relational operator. */
4792 signed_relational_operator (rtx op, enum machine_mode mode)
4798 if (mode != VOIDmode && mode != GET_MODE (op))
4801 switch (GET_CODE (op))
4816 if (op1 != const0_rtx)
4820 if (GET_CODE (op0) != REG)
4823 regno = REGNO (op0);
4824 if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
4827 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4833 /* Return true if operator is a signed integer relational operator. */
4836 unsigned_relational_operator (rtx op, enum machine_mode mode)
4842 if (mode != VOIDmode && mode != GET_MODE (op))
4845 switch (GET_CODE (op))
4858 if (op1 != const0_rtx)
4862 if (GET_CODE (op0) != REG)
4865 regno = REGNO (op0);
4866 if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
4869 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4875 /* Return true if operator is a floating point relational operator. */
4878 float_relational_operator (rtx op, enum machine_mode mode)
4884 if (mode != VOIDmode && mode != GET_MODE (op))
4887 switch (GET_CODE (op))
4906 if (op1 != const0_rtx)
4910 if (GET_CODE (op0) != REG)
4913 regno = REGNO (op0);
4914 if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
4917 if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4923 /* Return true if operator is EQ/NE of a conditional execution register. */
4926 ccr_eqne_operator (rtx op, enum machine_mode mode)
4928 enum machine_mode op_mode = GET_MODE (op);
4933 if (mode != VOIDmode && op_mode != mode)
4936 switch (GET_CODE (op))
4947 if (op1 != const0_rtx)
4951 if (GET_CODE (op0) != REG)
4954 regno = REGNO (op0);
4955 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4961 /* Return true if operator is a minimum or maximum operator (both signed and
4965 minmax_operator (rtx op, enum machine_mode mode)
4967 if (mode != VOIDmode && mode != GET_MODE (op))
4970 switch (GET_CODE (op))
4982 if (! integer_register_operand (XEXP (op, 0), mode))
4985 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
4991 /* Return true if operator is an integer binary operator that can executed
4992 conditionally and takes 1 cycle. */
4995 condexec_si_binary_operator (rtx op, enum machine_mode mode)
4997 enum machine_mode op_mode = GET_MODE (op);
4999 if (mode != VOIDmode && op_mode != mode)
5002 switch (GET_CODE (op))
5019 /* Return true if operator is an integer binary operator that can be
5020 executed conditionally by a media instruction. */
5023 condexec_si_media_operator (rtx op, enum machine_mode mode)
5025 enum machine_mode op_mode = GET_MODE (op);
5027 if (mode != VOIDmode && op_mode != mode)
5030 switch (GET_CODE (op))
5042 /* Return true if operator is an integer division operator that can executed
5046 condexec_si_divide_operator (rtx op, enum machine_mode mode)
5048 enum machine_mode op_mode = GET_MODE (op);
5050 if (mode != VOIDmode && op_mode != mode)
5053 switch (GET_CODE (op))
5064 /* Return true if operator is an integer unary operator that can executed
5068 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5070 enum machine_mode op_mode = GET_MODE (op);
5072 if (mode != VOIDmode && op_mode != mode)
5075 switch (GET_CODE (op))
5086 /* Return true if operator is a conversion-type expression that can be
5087 evaluated conditionally by floating-point instructions. */
5090 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5092 enum machine_mode op_mode = GET_MODE (op);
5094 if (mode != VOIDmode && op_mode != mode)
5097 switch (GET_CODE (op))
5108 /* Return true if operator is an addition or subtraction expression.
5109 Such expressions can be evaluated conditionally by floating-point
5113 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5115 enum machine_mode op_mode = GET_MODE (op);
5117 if (mode != VOIDmode && op_mode != mode)
5120 switch (GET_CODE (op))
5131 /* Return true if the memory operand is one that can be conditionally
5135 condexec_memory_operand (rtx op, enum machine_mode mode)
5137 enum machine_mode op_mode = GET_MODE (op);
5140 if (mode != VOIDmode && op_mode != mode)
5155 if (GET_CODE (op) != MEM)
5158 addr = XEXP (op, 0);
5159 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5162 /* Return true if operator is an integer binary operator that can be combined
5163 with a setcc operation. Do not allow the arithmetic operations that could
5164 potentially overflow since the FR-V sets the condition code based on the
5165 "true" value of the result, not the result after truncating to a 32-bit
5169 intop_compare_operator (rtx op, enum machine_mode mode)
5171 enum machine_mode op_mode = GET_MODE (op);
5173 if (mode != VOIDmode && op_mode != mode)
5176 switch (GET_CODE (op))
5189 if (! integer_register_operand (XEXP (op, 0), SImode))
5192 if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
5198 /* Return true if operator is an integer binary operator that can be combined
5199 with a setcc operation inside of a conditional execution. */
5202 condexec_intop_cmp_operator (rtx op, enum machine_mode mode)
5204 enum machine_mode op_mode = GET_MODE (op);
5206 if (mode != VOIDmode && op_mode != mode)
5209 switch (GET_CODE (op))
5222 if (! integer_register_operand (XEXP (op, 0), SImode))
5225 if (! integer_register_operand (XEXP (op, 1), SImode))
5231 /* Return 1 if operand is a valid ACC register number. */
5234 acc_operand (rtx op, enum machine_mode mode)
5238 if (GET_MODE (op) != mode && mode != VOIDmode)
5241 if (GET_CODE (op) == SUBREG)
5243 if (GET_CODE (SUBREG_REG (op)) != REG)
5244 return register_operand (op, mode);
5246 op = SUBREG_REG (op);
5249 if (GET_CODE (op) != REG)
5253 return ACC_OR_PSEUDO_P (regno);
5256 /* Return 1 if operand is a valid even ACC register number. */
5259 even_acc_operand (rtx op, enum machine_mode mode)
5263 if (GET_MODE (op) != mode && mode != VOIDmode)
5266 if (GET_CODE (op) == SUBREG)
5268 if (GET_CODE (SUBREG_REG (op)) != REG)
5269 return register_operand (op, mode);
5271 op = SUBREG_REG (op);
5274 if (GET_CODE (op) != REG)
5278 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0);
5281 /* Return 1 if operand is zero or four. */
5284 quad_acc_operand (rtx op, enum machine_mode mode)
5288 if (GET_MODE (op) != mode && mode != VOIDmode)
5291 if (GET_CODE (op) == SUBREG)
5293 if (GET_CODE (SUBREG_REG (op)) != REG)
5294 return register_operand (op, mode);
5296 op = SUBREG_REG (op);
5299 if (GET_CODE (op) != REG)
5303 return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0);
5306 /* Return 1 if operand is a valid ACCG register number. */
5309 accg_operand (rtx op, enum machine_mode mode)
5311 if (GET_MODE (op) != mode && mode != VOIDmode)
5314 if (GET_CODE (op) == SUBREG)
5316 if (GET_CODE (SUBREG_REG (op)) != REG)
5317 return register_operand (op, mode);
5319 op = SUBREG_REG (op);
5322 if (GET_CODE (op) != REG)
5325 return ACCG_OR_PSEUDO_P (REGNO (op));
5329 /* Return true if the bare return instruction can be used outside of the
5330 epilog code. For frv, we only do it if there was no stack allocation. */
5333 direct_return_p (void)
5337 if (!reload_completed)
5340 info = frv_stack_info ();
5341 return (info->total_size == 0);
5345 /* Emit code to handle a MOVSI, adding in the small data register or pic
5346 register if needed to load up addresses. Return TRUE if the appropriate
5347 instructions are emitted. */
5350 frv_emit_movsi (rtx dest, rtx src)
5352 int base_regno = -1;
5355 struct frv_unspec old_unspec;
5357 if (!reload_in_progress
5358 && !reload_completed
5359 && !register_operand (dest, SImode)
5360 && (!reg_or_0_operand (src, SImode)
5361 /* Virtual registers will almost always be replaced by an
5362 add instruction, so expose this to CSE by copying to
5363 an intermediate register. */
5364 || (GET_CODE (src) == REG
5365 && IN_RANGE_P (REGNO (src),
5366 FIRST_VIRTUAL_REGISTER,
5367 LAST_VIRTUAL_REGISTER))))
5369 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5373 /* Explicitly add in the PIC or small data register if needed. */
5374 switch (GET_CODE (src))
5383 /* Using GPREL12, we use a single GOT entry for all symbols
5384 in read-only sections, but trade sequences such as:
5386 sethi #gothi(label), gr#
5387 setlo #gotlo(label), gr#
5392 ld @(gr15,#got12(_gp)), gr#
5393 sethi #gprelhi(label), gr##
5394 setlo #gprello(label), gr##
5397 We may often be able to share gr# for multiple
5398 computations of GPREL addresses, and we may often fold
5399 the final add into the pair of registers of a load or
5400 store instruction, so it's often profitable. Even when
5401 optimizing for size, we're trading a GOT entry for an
5402 additional instruction, which trades GOT space
5403 (read-write) for code size (read-only, shareable), as
5404 long as the symbol is not used in more than two different
5407 With -fpie/-fpic, we'd be trading a single load for a
5408 sequence of 4 instructions, because the offset of the
5409 label can't be assumed to be addressable with 12 bits, so
5410 we don't do this. */
5411 if (TARGET_GPREL_RO)
5412 unspec = R_FRV_GPREL12;
5414 unspec = R_FRV_GOT12;
5417 base_regno = PIC_REGNO;
5422 if (frv_const_unspec_p (src, &old_unspec))
5425 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5428 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5429 emit_move_insn (dest, src);
5434 sym = XEXP (sym, 0);
5435 if (GET_CODE (sym) == PLUS
5436 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5437 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5438 sym = XEXP (sym, 0);
5439 if (GET_CODE (sym) == SYMBOL_REF)
5441 else if (GET_CODE (sym) == LABEL_REF)
5444 goto handle_whatever;
5452 if (SYMBOL_REF_FUNCTION_P (sym))
5454 if (frv_local_funcdesc_p (sym))
5455 unspec = R_FRV_FUNCDESC_GOTOFF12;
5457 unspec = R_FRV_FUNCDESC_GOT12;
5461 if (CONSTANT_POOL_ADDRESS_P (sym))
5462 switch (GET_CODE (get_pool_constant (sym)))
5469 unspec = R_FRV_GOTOFF12;
5474 if (TARGET_GPREL_RO)
5475 unspec = R_FRV_GPREL12;
5477 unspec = R_FRV_GOT12;
5480 else if (SYMBOL_REF_LOCAL_P (sym)
5481 && !SYMBOL_REF_EXTERNAL_P (sym)
5482 && SYMBOL_REF_DECL (sym)
5483 && (!DECL_P (SYMBOL_REF_DECL (sym))
5484 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5486 tree decl = SYMBOL_REF_DECL (sym);
5487 tree init = TREE_CODE (decl) == VAR_DECL
5488 ? DECL_INITIAL (decl)
5489 : TREE_CODE (decl) == CONSTRUCTOR
5492 bool named_section, readonly;
5494 if (init && init != error_mark_node)
5495 reloc = compute_reloc_for_constant (init);
5497 named_section = TREE_CODE (decl) == VAR_DECL
5498 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5499 readonly = decl_readonly_section (decl, reloc);
5502 unspec = R_FRV_GOT12;
5504 unspec = R_FRV_GOTOFF12;
5505 else if (readonly && TARGET_GPREL_RO)
5506 unspec = R_FRV_GPREL12;
5508 unspec = R_FRV_GOT12;
5511 unspec = R_FRV_GOT12;
5515 else if (SYMBOL_REF_SMALL_P (sym))
5516 base_regno = SDA_BASE_REG;
5519 base_regno = PIC_REGNO;
5524 if (base_regno >= 0)
5526 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5527 emit_insn (gen_symGOTOFF2reg (dest, src,
5528 gen_rtx_REG (Pmode, base_regno),
5529 GEN_INT (R_FRV_GPREL12)));
5531 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5532 gen_rtx_REG (Pmode, base_regno),
5533 GEN_INT (R_FRV_GPREL12)));
5534 if (base_regno == PIC_REGNO)
5535 cfun->uses_pic_offset_table = TRUE;
5543 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5544 new uses of it once reload has begun. */
5545 if (reload_in_progress || reload_completed)
5550 case R_FRV_GOTOFF12:
5551 if (!frv_small_data_reloc_p (sym, unspec))
5552 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5555 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5558 if (!frv_small_data_reloc_p (sym, unspec))
5559 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5562 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5564 case R_FRV_FUNCDESC_GOTOFF12:
5566 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5569 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5573 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5576 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5580 cfun->uses_pic_offset_table = TRUE;
5589 /* Return a string to output a single word move. */
5592 output_move_single (rtx operands[], rtx insn)
5594 rtx dest = operands[0];
5595 rtx src = operands[1];
5597 if (GET_CODE (dest) == REG)
5599 int dest_regno = REGNO (dest);
5600 enum machine_mode mode = GET_MODE (dest);
5602 if (GPR_P (dest_regno))
5604 if (GET_CODE (src) == REG)
5606 /* gpr <- some sort of register */
5607 int src_regno = REGNO (src);
5609 if (GPR_P (src_regno))
5610 return "mov %1, %0";
5612 else if (FPR_P (src_regno))
5613 return "movfg %1, %0";
5615 else if (SPR_P (src_regno))
5616 return "movsg %1, %0";
5619 else if (GET_CODE (src) == MEM)
5628 return "ldsb%I1%U1 %M1,%0";
5631 return "ldsh%I1%U1 %M1,%0";
5635 return "ld%I1%U1 %M1, %0";
5639 else if (GET_CODE (src) == CONST_INT
5640 || GET_CODE (src) == CONST_DOUBLE)
5642 /* gpr <- integer/floating constant */
5643 HOST_WIDE_INT value;
5645 if (GET_CODE (src) == CONST_INT)
5646 value = INTVAL (src);
5648 else if (mode == SFmode)
5653 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5654 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5659 value = CONST_DOUBLE_LOW (src);
5661 if (IN_RANGE_P (value, -32768, 32767))
5662 return "setlos %1, %0";
5667 else if (GET_CODE (src) == SYMBOL_REF
5668 || GET_CODE (src) == LABEL_REF
5669 || GET_CODE (src) == CONST)
5675 else if (FPR_P (dest_regno))
5677 if (GET_CODE (src) == REG)
5679 /* fpr <- some sort of register */
5680 int src_regno = REGNO (src);
5682 if (GPR_P (src_regno))
5683 return "movgf %1, %0";
5685 else if (FPR_P (src_regno))
5687 if (TARGET_HARD_FLOAT)
5688 return "fmovs %1, %0";
5690 return "mor %1, %1, %0";
5694 else if (GET_CODE (src) == MEM)
5703 return "ldbf%I1%U1 %M1,%0";
5706 return "ldhf%I1%U1 %M1,%0";
5710 return "ldf%I1%U1 %M1, %0";
5714 else if (ZERO_P (src))
5715 return "movgf %., %0";
5718 else if (SPR_P (dest_regno))
5720 if (GET_CODE (src) == REG)
5722 /* spr <- some sort of register */
5723 int src_regno = REGNO (src);
5725 if (GPR_P (src_regno))
5726 return "movgs %1, %0";
5731 else if (GET_CODE (dest) == MEM)
5733 if (GET_CODE (src) == REG)
5735 int src_regno = REGNO (src);
5736 enum machine_mode mode = GET_MODE (dest);
5738 if (GPR_P (src_regno))
5746 return "stb%I0%U0 %1, %M0";
5749 return "sth%I0%U0 %1, %M0";
5753 return "st%I0%U0 %1, %M0";
5757 else if (FPR_P (src_regno))
5765 return "stbf%I0%U0 %1, %M0";
5768 return "sthf%I0%U0 %1, %M0";
5772 return "stf%I0%U0 %1, %M0";
5777 else if (ZERO_P (src))
5779 switch (GET_MODE (dest))
5785 return "stb%I0%U0 %., %M0";
5788 return "sth%I0%U0 %., %M0";
5792 return "st%I0%U0 %., %M0";
5797 fatal_insn ("Bad output_move_single operand", insn);
5802 /* Return a string to output a double word move. */
5805 output_move_double (rtx operands[], rtx insn)
5807 rtx dest = operands[0];
5808 rtx src = operands[1];
5809 enum machine_mode mode = GET_MODE (dest);
5811 if (GET_CODE (dest) == REG)
5813 int dest_regno = REGNO (dest);
5815 if (GPR_P (dest_regno))
5817 if (GET_CODE (src) == REG)
5819 /* gpr <- some sort of register */
5820 int src_regno = REGNO (src);
5822 if (GPR_P (src_regno))
5825 else if (FPR_P (src_regno))
5827 if (((dest_regno - GPR_FIRST) & 1) == 0
5828 && ((src_regno - FPR_FIRST) & 1) == 0)
5829 return "movfgd %1, %0";
5835 else if (GET_CODE (src) == MEM)
5838 if (dbl_memory_one_insn_operand (src, mode))
5839 return "ldd%I1%U1 %M1, %0";
5844 else if (GET_CODE (src) == CONST_INT
5845 || GET_CODE (src) == CONST_DOUBLE)
5849 else if (FPR_P (dest_regno))
5851 if (GET_CODE (src) == REG)
5853 /* fpr <- some sort of register */
5854 int src_regno = REGNO (src);
5856 if (GPR_P (src_regno))
5858 if (((dest_regno - FPR_FIRST) & 1) == 0
5859 && ((src_regno - GPR_FIRST) & 1) == 0)
5860 return "movgfd %1, %0";
5865 else if (FPR_P (src_regno))
5868 && ((dest_regno - FPR_FIRST) & 1) == 0
5869 && ((src_regno - FPR_FIRST) & 1) == 0)
5870 return "fmovd %1, %0";
5876 else if (GET_CODE (src) == MEM)
5879 if (dbl_memory_one_insn_operand (src, mode))
5880 return "lddf%I1%U1 %M1, %0";
5885 else if (ZERO_P (src))
5890 else if (GET_CODE (dest) == MEM)
5892 if (GET_CODE (src) == REG)
5894 int src_regno = REGNO (src);
5896 if (GPR_P (src_regno))
5898 if (((src_regno - GPR_FIRST) & 1) == 0
5899 && dbl_memory_one_insn_operand (dest, mode))
5900 return "std%I0%U0 %1, %M0";
5905 if (FPR_P (src_regno))
5907 if (((src_regno - FPR_FIRST) & 1) == 0
5908 && dbl_memory_one_insn_operand (dest, mode))
5909 return "stdf%I0%U0 %1, %M0";
5915 else if (ZERO_P (src))
5917 if (dbl_memory_one_insn_operand (dest, mode))
5918 return "std%I0%U0 %., %M0";
5924 fatal_insn ("Bad output_move_double operand", insn);
5929 /* Return a string to output a single word conditional move.
5930 Operand0 -- EQ/NE of ccr register and 0
5931 Operand1 -- CCR register
5932 Operand2 -- destination
5933 Operand3 -- source */
5936 output_condmove_single (rtx operands[], rtx insn)
5938 rtx dest = operands[2];
5939 rtx src = operands[3];
5941 if (GET_CODE (dest) == REG)
5943 int dest_regno = REGNO (dest);
5944 enum machine_mode mode = GET_MODE (dest);
5946 if (GPR_P (dest_regno))
5948 if (GET_CODE (src) == REG)
5950 /* gpr <- some sort of register */
5951 int src_regno = REGNO (src);
5953 if (GPR_P (src_regno))
5954 return "cmov %z3, %2, %1, %e0";
5956 else if (FPR_P (src_regno))
5957 return "cmovfg %3, %2, %1, %e0";
5960 else if (GET_CODE (src) == MEM)
5969 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5972 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5976 return "cld%I3%U3 %M3, %2, %1, %e0";
5980 else if (ZERO_P (src))
5981 return "cmov %., %2, %1, %e0";
5984 else if (FPR_P (dest_regno))
5986 if (GET_CODE (src) == REG)
5988 /* fpr <- some sort of register */
5989 int src_regno = REGNO (src);
5991 if (GPR_P (src_regno))
5992 return "cmovgf %3, %2, %1, %e0";
5994 else if (FPR_P (src_regno))
5996 if (TARGET_HARD_FLOAT)
5997 return "cfmovs %3,%2,%1,%e0";
5999 return "cmor %3, %3, %2, %1, %e0";
6003 else if (GET_CODE (src) == MEM)
6006 if (mode == SImode || mode == SFmode)
6007 return "cldf%I3%U3 %M3, %2, %1, %e0";
6010 else if (ZERO_P (src))
6011 return "cmovgf %., %2, %1, %e0";
6015 else if (GET_CODE (dest) == MEM)
6017 if (GET_CODE (src) == REG)
6019 int src_regno = REGNO (src);
6020 enum machine_mode mode = GET_MODE (dest);
6022 if (GPR_P (src_regno))
6030 return "cstb%I2%U2 %3, %M2, %1, %e0";
6033 return "csth%I2%U2 %3, %M2, %1, %e0";
6037 return "cst%I2%U2 %3, %M2, %1, %e0";
6041 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
6042 return "cstf%I2%U2 %3, %M2, %1, %e0";
6045 else if (ZERO_P (src))
6047 enum machine_mode mode = GET_MODE (dest);
6054 return "cstb%I2%U2 %., %M2, %1, %e0";
6057 return "csth%I2%U2 %., %M2, %1, %e0";
6061 return "cst%I2%U2 %., %M2, %1, %e0";
6066 fatal_insn ("Bad output_condmove_single operand", insn);
6071 /* Emit the appropriate code to do a comparison, returning the register the
6072 comparison was done it. */
6075 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
6077 enum machine_mode cc_mode;
6080 /* Floating point doesn't have comparison against a constant. */
6081 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
6082 op1 = force_reg (GET_MODE (op0), op1);
6084 /* Possibly disable using anything but a fixed register in order to work
6085 around cse moving comparisons past function calls. */
6086 cc_mode = SELECT_CC_MODE (test, op0, op1);
6087 cc_reg = ((TARGET_ALLOC_CC)
6088 ? gen_reg_rtx (cc_mode)
6089 : gen_rtx_REG (cc_mode,
6090 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
6092 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6093 gen_rtx_COMPARE (cc_mode, op0, op1)));
6099 /* Emit code for a conditional branch. The comparison operands were previously
6100 stored in frv_compare_op0 and frv_compare_op1.
6102 XXX: I originally wanted to add a clobber of a CCR register to use in
6103 conditional execution, but that confuses the rest of the compiler. */
6106 frv_emit_cond_branch (enum rtx_code test, rtx label)
6111 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6112 enum machine_mode cc_mode = GET_MODE (cc_reg);
6114 /* Branches generate:
6116 (if_then_else (<test>, <cc_reg>, (const_int 0))
6117 (label_ref <branch_label>)
6119 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
6120 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6121 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
6122 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
6127 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6128 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6131 frv_emit_scc (enum rtx_code test, rtx target)
6137 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6139 /* SCC instructions generate:
6140 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6141 (clobber (<ccr_reg>))]) */
6142 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6143 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6145 cr_reg = ((TARGET_ALLOC_CC)
6146 ? gen_reg_rtx (CC_CCRmode)
6147 : gen_rtx_REG (CC_CCRmode,
6148 ((GET_MODE (cc_reg) == CC_FPmode)
6152 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6153 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6158 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6159 the separate insns. */
6162 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6168 /* Set the appropriate CCR bit. */
6169 emit_insn (gen_rtx_SET (VOIDmode,
6171 gen_rtx_fmt_ee (GET_CODE (test),
6176 /* Move the value into the destination. */
6177 emit_move_insn (dest, GEN_INT (value));
6179 /* Move 0 into the destination if the test failed */
6180 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6181 gen_rtx_EQ (GET_MODE (cr_reg),
6184 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6186 /* Finish up, return sequence. */
6193 /* Emit the code for a conditional move, return TRUE if we could do the
6197 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6204 enum rtx_code test = GET_CODE (test_rtx);
6205 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6206 enum machine_mode cc_mode = GET_MODE (cc_reg);
6208 /* Conditional move instructions generate:
6209 (parallel [(set <target>
6210 (if_then_else (<test> <cc_reg> (const_int 0))
6213 (clobber (<ccr_reg>))]) */
6215 /* Handle various cases of conditional move involving two constants. */
6216 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6218 HOST_WIDE_INT value1 = INTVAL (src1);
6219 HOST_WIDE_INT value2 = INTVAL (src2);
6221 /* Having 0 as one of the constants can be done by loading the other
6222 constant, and optionally moving in gr0. */
6223 if (value1 == 0 || value2 == 0)
6226 /* If the first value is within an addi range and also the difference
6227 between the two fits in an addi's range, load up the difference, then
6228 conditionally move in 0, and then unconditionally add the first
6230 else if (IN_RANGE_P (value1, -2048, 2047)
6231 && IN_RANGE_P (value2 - value1, -2048, 2047))
6234 /* If neither condition holds, just force the constant into a
6238 src1 = force_reg (GET_MODE (dest), src1);
6239 src2 = force_reg (GET_MODE (dest), src2);
6243 /* If one value is a register, insure the other value is either 0 or a
6247 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6248 src1 = force_reg (GET_MODE (dest), src1);
6250 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6251 src2 = force_reg (GET_MODE (dest), src2);
6254 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6255 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6257 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6259 cr_reg = ((TARGET_ALLOC_CC)
6260 ? gen_reg_rtx (CC_CCRmode)
6261 : gen_rtx_REG (CC_CCRmode,
6262 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6264 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6265 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6270 /* Split a conditional move into constituent parts, returning a SEQUENCE
6271 containing all of the insns. */
6274 frv_split_cond_move (rtx operands[])
6276 rtx dest = operands[0];
6277 rtx test = operands[1];
6278 rtx cc_reg = operands[2];
6279 rtx src1 = operands[3];
6280 rtx src2 = operands[4];
6281 rtx cr_reg = operands[5];
6283 enum machine_mode cr_mode = GET_MODE (cr_reg);
6287 /* Set the appropriate CCR bit. */
6288 emit_insn (gen_rtx_SET (VOIDmode,
6290 gen_rtx_fmt_ee (GET_CODE (test),
6295 /* Handle various cases of conditional move involving two constants. */
6296 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6298 HOST_WIDE_INT value1 = INTVAL (src1);
6299 HOST_WIDE_INT value2 = INTVAL (src2);
6301 /* Having 0 as one of the constants can be done by loading the other
6302 constant, and optionally moving in gr0. */
6305 emit_move_insn (dest, src2);
6306 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6307 gen_rtx_NE (cr_mode, cr_reg,
6309 gen_rtx_SET (VOIDmode, dest, src1)));
6312 else if (value2 == 0)
6314 emit_move_insn (dest, src1);
6315 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6316 gen_rtx_EQ (cr_mode, cr_reg,
6318 gen_rtx_SET (VOIDmode, dest, src2)));
6321 /* If the first value is within an addi range and also the difference
6322 between the two fits in an addi's range, load up the difference, then
6323 conditionally move in 0, and then unconditionally add the first
6325 else if (IN_RANGE_P (value1, -2048, 2047)
6326 && IN_RANGE_P (value2 - value1, -2048, 2047))
6328 rtx dest_si = ((GET_MODE (dest) == SImode)
6330 : gen_rtx_SUBREG (SImode, dest, 0));
6332 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6333 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6334 gen_rtx_NE (cr_mode, cr_reg,
6336 gen_rtx_SET (VOIDmode, dest_si,
6338 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6346 /* Emit the conditional move for the test being true if needed. */
6347 if (! rtx_equal_p (dest, src1))
6348 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6349 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6350 gen_rtx_SET (VOIDmode, dest, src1)));
6352 /* Emit the conditional move for the test being false if needed. */
6353 if (! rtx_equal_p (dest, src2))
6354 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6355 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6356 gen_rtx_SET (VOIDmode, dest, src2)));
6359 /* Finish up, return sequence. */
6366 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6367 memory location that is not known to be dword-aligned. */
6369 frv_split_double_load (rtx dest, rtx source)
6371 int regno = REGNO (dest);
6372 rtx dest1 = gen_highpart (SImode, dest);
6373 rtx dest2 = gen_lowpart (SImode, dest);
6374 rtx address = XEXP (source, 0);
6376 /* If the address is pre-modified, load the lower-numbered register
6377 first, then load the other register using an integer offset from
6378 the modified base register. This order should always be safe,
6379 since the pre-modification cannot affect the same registers as the
6382 The situation for other loads is more complicated. Loading one
6383 of the registers could affect the value of ADDRESS, so we must
6384 be careful which order we do them in. */
6385 if (GET_CODE (address) == PRE_MODIFY
6386 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6388 /* It is safe to load the lower-numbered register first. */
6389 emit_move_insn (dest1, change_address (source, SImode, NULL));
6390 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6394 /* ADDRESS is not pre-modified and the address depends on the
6395 lower-numbered register. Load the higher-numbered register
6397 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6398 emit_move_insn (dest1, change_address (source, SImode, NULL));
6402 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6403 and SOURCE is either a double register or the constant zero. */
6405 frv_split_double_store (rtx dest, rtx source)
6407 rtx dest1 = change_address (dest, SImode, NULL);
6408 rtx dest2 = frv_index_memory (dest, SImode, 1);
6409 if (ZERO_P (source))
6411 emit_move_insn (dest1, CONST0_RTX (SImode));
6412 emit_move_insn (dest2, CONST0_RTX (SImode));
6416 emit_move_insn (dest1, gen_highpart (SImode, source));
6417 emit_move_insn (dest2, gen_lowpart (SImode, source));
6422 /* Split a min/max operation returning a SEQUENCE containing all of the
6426 frv_split_minmax (rtx operands[])
6428 rtx dest = operands[0];
6429 rtx minmax = operands[1];
6430 rtx src1 = operands[2];
6431 rtx src2 = operands[3];
6432 rtx cc_reg = operands[4];
6433 rtx cr_reg = operands[5];
6435 enum rtx_code test_code;
6436 enum machine_mode cr_mode = GET_MODE (cr_reg);
6440 /* Figure out which test to use. */
6441 switch (GET_CODE (minmax))
6446 case SMIN: test_code = LT; break;
6447 case SMAX: test_code = GT; break;
6448 case UMIN: test_code = LTU; break;
6449 case UMAX: test_code = GTU; break;
6452 /* Issue the compare instruction. */
6453 emit_insn (gen_rtx_SET (VOIDmode,
6455 gen_rtx_COMPARE (GET_MODE (cc_reg),
6458 /* Set the appropriate CCR bit. */
6459 emit_insn (gen_rtx_SET (VOIDmode,
6461 gen_rtx_fmt_ee (test_code,
6466 /* If are taking the min/max of a nonzero constant, load that first, and
6467 then do a conditional move of the other value. */
6468 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6470 if (rtx_equal_p (dest, src1))
6473 emit_move_insn (dest, src2);
6474 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6475 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6476 gen_rtx_SET (VOIDmode, dest, src1)));
6479 /* Otherwise, do each half of the move. */
6482 /* Emit the conditional move for the test being true if needed. */
6483 if (! rtx_equal_p (dest, src1))
6484 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6485 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6486 gen_rtx_SET (VOIDmode, dest, src1)));
6488 /* Emit the conditional move for the test being false if needed. */
6489 if (! rtx_equal_p (dest, src2))
6490 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6491 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6492 gen_rtx_SET (VOIDmode, dest, src2)));
6495 /* Finish up, return sequence. */
6502 /* Split an integer abs operation returning a SEQUENCE containing all of the
6506 frv_split_abs (rtx operands[])
6508 rtx dest = operands[0];
6509 rtx src = operands[1];
6510 rtx cc_reg = operands[2];
6511 rtx cr_reg = operands[3];
6516 /* Issue the compare < 0 instruction. */
6517 emit_insn (gen_rtx_SET (VOIDmode,
6519 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6521 /* Set the appropriate CCR bit. */
6522 emit_insn (gen_rtx_SET (VOIDmode,
6524 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6526 /* Emit the conditional negate if the value is negative. */
6527 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6528 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6529 gen_negsi2 (dest, src)));
6531 /* Emit the conditional move for the test being false if needed. */
6532 if (! rtx_equal_p (dest, src))
6533 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6534 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6535 gen_rtx_SET (VOIDmode, dest, src)));
6537 /* Finish up, return sequence. */
6544 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6545 register used in an insn. */
6548 frv_clear_registers_used (rtx *ptr, void *data)
6550 if (GET_CODE (*ptr) == REG)
6552 int regno = REGNO (*ptr);
6553 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6555 if (regno < FIRST_PSEUDO_REGISTER)
6557 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6559 while (regno < reg_max)
6561 CLEAR_HARD_REG_BIT (*p_regs, regno);
6571 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6573 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6574 initialize the static storage. */
6576 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6578 frv_ifcvt.added_insns_list = NULL_RTX;
6579 frv_ifcvt.cur_scratch_regs = 0;
6580 frv_ifcvt.num_nested_cond_exec = 0;
6581 frv_ifcvt.cr_reg = NULL_RTX;
6582 frv_ifcvt.nested_cc_reg = NULL_RTX;
6583 frv_ifcvt.extra_int_cr = NULL_RTX;
6584 frv_ifcvt.extra_fp_cr = NULL_RTX;
6585 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6589 /* Internal function to add a potential insn to the list of insns to be inserted
6590 if the conditional execution conversion is successful. */
6593 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6595 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6597 link->jump = before_p; /* Mark to add this before or after insn. */
6598 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6599 frv_ifcvt.added_insns_list);
6601 if (TARGET_DEBUG_COND_EXEC)
6604 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6605 (before_p) ? "before" : "after",
6606 (int)INSN_UID (insn));
6608 debug_rtx (pattern);
6613 /* A C expression to modify the code described by the conditional if
6614 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6615 FALSE_EXPR for converting if-then and if-then-else code to conditional
6616 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6617 tests cannot be converted. */
6620 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6622 basic_block test_bb = ce_info->test_bb; /* test basic block */
6623 basic_block then_bb = ce_info->then_bb; /* THEN */
6624 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6625 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6626 rtx true_expr = *p_true;
6630 enum machine_mode mode = GET_MODE (true_expr);
6634 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6636 rtx sub_cond_exec_reg;
6638 enum rtx_code code_true;
6639 enum rtx_code code_false;
6640 enum reg_class cc_class;
6641 enum reg_class cr_class;
6645 /* Make sure we are only dealing with hard registers. Also honor the
6646 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6648 if (!reload_completed || TARGET_NO_COND_EXEC
6649 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6652 /* Figure out which registers we can allocate for our own purposes. Only
6653 consider registers that are not preserved across function calls and are
6654 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6655 if we did not need to use them in reloading other registers. */
6656 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6657 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6658 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6659 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6660 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6662 /* If this is a nested IF, we need to discover whether the CC registers that
6663 are set/used inside of the block are used anywhere else. If not, we can
6664 change them to be the CC register that is paired with the CR register that
6665 controls the outermost IF block. */
6666 if (ce_info->pass > 1)
6668 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6669 for (j = CC_FIRST; j <= CC_LAST; j++)
6670 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6672 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6675 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6678 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6681 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6685 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6686 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6688 frv_ifcvt.added_insns_list = NULL_RTX;
6689 frv_ifcvt.cur_scratch_regs = 0;
6691 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6692 * sizeof (basic_block));
6698 /* Remove anything live at the beginning of the join block from being
6699 available for allocation. */
6700 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno,
6702 if (regno < FIRST_PSEUDO_REGISTER)
6703 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6707 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6709 if (ce_info->num_multiple_test_blocks)
6711 basic_block multiple_test_bb = ce_info->last_test_bb;
6713 while (multiple_test_bb != test_bb)
6715 bb[num_bb++] = multiple_test_bb;
6716 multiple_test_bb = multiple_test_bb->pred->src;
6720 /* Add in the THEN and ELSE blocks to be scanned. */
6721 bb[num_bb++] = then_bb;
6723 bb[num_bb++] = else_bb;
6725 sub_cond_exec_reg = NULL_RTX;
6726 frv_ifcvt.num_nested_cond_exec = 0;
6728 /* Scan all of the blocks for registers that must not be allocated. */
6729 for (j = 0; j < num_bb; j++)
6731 rtx last_insn = BB_END (bb[j]);
6732 rtx insn = BB_HEAD (bb[j]);
6736 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6737 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6739 (int) INSN_UID (BB_HEAD (bb[j])),
6740 (int) INSN_UID (BB_END (bb[j])));
6742 /* Anything live at the beginning of the block is obviously unavailable
6744 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno,
6746 if (regno < FIRST_PSEUDO_REGISTER)
6747 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6750 /* Loop through the insns in the block. */
6753 /* Mark any new registers that are created as being unavailable for
6754 allocation. Also see if the CC register used in nested IFs can be
6760 int skip_nested_if = FALSE;
6762 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6763 (void *)&tmp_reg->regs);
6765 pattern = PATTERN (insn);
6766 if (GET_CODE (pattern) == COND_EXEC)
6768 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6770 if (reg != sub_cond_exec_reg)
6772 sub_cond_exec_reg = reg;
6773 frv_ifcvt.num_nested_cond_exec++;
6777 set = single_set_pattern (pattern);
6780 rtx dest = SET_DEST (set);
6781 rtx src = SET_SRC (set);
6783 if (GET_CODE (dest) == REG)
6785 int regno = REGNO (dest);
6786 enum rtx_code src_code = GET_CODE (src);
6788 if (CC_P (regno) && src_code == COMPARE)
6789 skip_nested_if = TRUE;
6791 else if (CR_P (regno)
6792 && (src_code == IF_THEN_ELSE
6793 || COMPARISON_P (src)))
6794 skip_nested_if = TRUE;
6798 if (! skip_nested_if)
6799 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6800 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6803 if (insn == last_insn)
6806 insn = NEXT_INSN (insn);
6810 /* If this is a nested if, rewrite the CC registers that are available to
6811 include the ones that can be rewritten, to increase the chance of being
6812 able to allocate a paired CC/CR register combination. */
6813 if (ce_info->pass > 1)
6815 for (j = CC_FIRST; j <= CC_LAST; j++)
6816 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6817 SET_HARD_REG_BIT (tmp_reg->regs, j);
6819 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6825 fprintf (dump_file, "Available GPRs: ");
6827 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6828 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6830 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6831 if (++num_gprs > GPR_TEMP_NUM+2)
6835 fprintf (dump_file, "%s\nAvailable CRs: ",
6836 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6838 for (j = CR_FIRST; j <= CR_LAST; j++)
6839 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6840 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6842 fputs ("\n", dump_file);
6844 if (ce_info->pass > 1)
6846 fprintf (dump_file, "Modifiable CCs: ");
6847 for (j = CC_FIRST; j <= CC_LAST; j++)
6848 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6849 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6851 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6852 frv_ifcvt.num_nested_cond_exec);
6856 /* Allocate the appropriate temporary condition code register. Try to
6857 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6858 that conditional cmp's can be done. */
6859 if (mode == CCmode || mode == CC_UNSmode)
6861 cr_class = ICR_REGS;
6862 cc_class = ICC_REGS;
6863 cc_first = ICC_FIRST;
6866 else if (mode == CC_FPmode)
6868 cr_class = FCR_REGS;
6869 cc_class = FCC_REGS;
6870 cc_first = FCC_FIRST;
6875 cc_first = cc_last = 0;
6876 cr_class = cc_class = NO_REGS;
6879 cc = XEXP (true_expr, 0);
6880 nested_cc = cr = NULL_RTX;
6881 if (cc_class != NO_REGS)
6883 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6884 so we can execute a csubcc/caddcc/cfcmps instruction. */
6887 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6889 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6891 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6892 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6894 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6895 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6898 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6899 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6909 fprintf (dump_file, "Could not allocate a CR temporary register\n");
6916 "Will use %s for conditional execution, %s for nested comparisons\n",
6917 reg_names[ REGNO (cr)],
6918 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6920 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6921 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6922 bit being true. We don't do this for floating point, because of NaNs. */
6923 code = GET_CODE (true_expr);
6924 if (GET_MODE (cc) != CC_FPmode)
6926 code = reverse_condition (code);
6936 check_insn = gen_rtx_SET (VOIDmode, cr,
6937 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6939 /* Record the check insn to be inserted later. */
6940 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6942 /* Update the tests. */
6943 frv_ifcvt.cr_reg = cr;
6944 frv_ifcvt.nested_cc_reg = nested_cc;
6945 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6946 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6949 /* Fail, don't do this conditional execution. */
6952 *p_false = NULL_RTX;
6954 fprintf (dump_file, "Disabling this conditional execution.\n");
6960 /* A C expression to modify the code described by the conditional if
6961 information CE_INFO, for the basic block BB, possibly updating the tests in
6962 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6963 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6964 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6966 /* p_true and p_false are given expressions of the form:
6968 (and (eq:CC_CCR (reg:CC_CCR)
6974 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
6979 rtx old_true = XEXP (*p_true, 0);
6980 rtx old_false = XEXP (*p_false, 0);
6981 rtx true_expr = XEXP (*p_true, 1);
6982 rtx false_expr = XEXP (*p_false, 1);
6985 rtx cr = XEXP (old_true, 0);
6987 rtx new_cr = NULL_RTX;
6988 rtx *p_new_cr = (rtx *)0;
6992 enum reg_class cr_class;
6993 enum machine_mode mode = GET_MODE (true_expr);
6994 rtx (*logical_func)(rtx, rtx, rtx);
6996 if (TARGET_DEBUG_COND_EXEC)
6999 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
7000 ce_info->and_and_p ? "&&" : "||");
7002 debug_rtx (*p_true);
7004 fputs ("\nfalse insn:\n", stderr);
7005 debug_rtx (*p_false);
7008 if (TARGET_NO_MULTI_CE)
7011 if (GET_CODE (cr) != REG)
7014 if (mode == CCmode || mode == CC_UNSmode)
7016 cr_class = ICR_REGS;
7017 p_new_cr = &frv_ifcvt.extra_int_cr;
7019 else if (mode == CC_FPmode)
7021 cr_class = FCR_REGS;
7022 p_new_cr = &frv_ifcvt.extra_fp_cr;
7027 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
7028 more &&/|| tests. */
7032 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
7033 CC_CCRmode, TRUE, TRUE);
7038 if (ce_info->and_and_p)
7040 old_test = old_false;
7041 test_expr = true_expr;
7042 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
7043 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7044 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7048 old_test = old_false;
7049 test_expr = false_expr;
7050 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
7051 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
7052 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
7055 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7056 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7058 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
7060 /* Now add the conditional check insn. */
7061 cc = XEXP (test_expr, 0);
7062 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
7063 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
7065 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
7067 /* Add the new check insn to the list of check insns that need to be
7069 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
7071 if (TARGET_DEBUG_COND_EXEC)
7073 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7076 debug_rtx (*p_true);
7078 fputs ("\nfalse insn:\n", stderr);
7079 debug_rtx (*p_false);
7085 *p_true = *p_false = NULL_RTX;
7087 /* If we allocated a CR register, release it. */
7090 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
7091 *p_new_cr = NULL_RTX;
7094 if (TARGET_DEBUG_COND_EXEC)
7095 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
7101 /* Return a register which will be loaded with a value if an IF block is
7102 converted to conditional execution. This is used to rewrite instructions
7103 that use constants to ones that just use registers. */
7106 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
7108 int num_alloc = frv_ifcvt.cur_scratch_regs;
7112 /* We know gr0 == 0, so replace any errant uses. */
7113 if (value == const0_rtx)
7114 return gen_rtx_REG (SImode, GPR_FIRST);
7116 /* First search all registers currently loaded to see if we have an
7117 applicable constant. */
7118 if (CONSTANT_P (value)
7119 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
7121 for (i = 0; i < num_alloc; i++)
7123 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
7124 return SET_DEST (frv_ifcvt.scratch_regs[i]);
7128 /* Have we exhausted the number of registers available? */
7129 if (num_alloc >= GPR_TEMP_NUM)
7132 fprintf (dump_file, "Too many temporary registers allocated\n");
7137 /* Allocate the new register. */
7138 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7142 fputs ("Could not find a scratch register\n", dump_file);
7147 frv_ifcvt.cur_scratch_regs++;
7148 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7152 if (GET_CODE (value) == CONST_INT)
7153 fprintf (dump_file, "Register %s will hold %ld\n",
7154 reg_names[ REGNO (reg)], (long)INTVAL (value));
7156 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7157 fprintf (dump_file, "Register %s will hold LR\n",
7158 reg_names[ REGNO (reg)]);
7161 fprintf (dump_file, "Register %s will hold a saved value\n",
7162 reg_names[ REGNO (reg)]);
7169 /* Update a MEM used in conditional code that might contain an offset to put
7170 the offset into a scratch register, so that the conditional load/store
7171 operations can be used. This function returns the original pointer if the
7172 MEM is valid to use in conditional code, NULL if we can't load up the offset
7173 into a temporary register, or the new MEM if we were successful. */
7176 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7178 rtx addr = XEXP (mem, 0);
7180 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7182 if (GET_CODE (addr) == PLUS)
7184 rtx addr_op0 = XEXP (addr, 0);
7185 rtx addr_op1 = XEXP (addr, 1);
7187 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7189 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7193 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7200 else if (CONSTANT_P (addr))
7201 addr = frv_ifcvt_load_value (addr, insn);
7206 if (addr == NULL_RTX)
7209 else if (XEXP (mem, 0) != addr)
7210 return change_address (mem, mode, addr);
7217 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7218 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7221 single_set_pattern (rtx pattern)
7226 if (GET_CODE (pattern) == COND_EXEC)
7227 pattern = COND_EXEC_CODE (pattern);
7229 if (GET_CODE (pattern) == SET)
7232 else if (GET_CODE (pattern) == PARALLEL)
7234 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7236 rtx sub = XVECEXP (pattern, 0, i);
7238 switch (GET_CODE (sub))
7262 /* A C expression to modify the code described by the conditional if
7263 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7264 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7265 insn cannot be converted to be executed conditionally. */
7268 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7272 rtx orig_ce_pattern = pattern;
7278 if (GET_CODE (pattern) != COND_EXEC)
7281 test = COND_EXEC_TEST (pattern);
7282 if (GET_CODE (test) == AND)
7284 rtx cr = frv_ifcvt.cr_reg;
7287 op0 = XEXP (test, 0);
7288 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7291 op1 = XEXP (test, 1);
7292 test_reg = XEXP (op1, 0);
7293 if (GET_CODE (test_reg) != REG)
7296 /* Is this the first nested if block in this sequence? If so, generate
7297 an andcr or andncr. */
7298 if (! frv_ifcvt.last_nested_if_cr)
7302 frv_ifcvt.last_nested_if_cr = test_reg;
7303 if (GET_CODE (op0) == NE)
7304 and_op = gen_andcr (test_reg, cr, test_reg);
7306 and_op = gen_andncr (test_reg, cr, test_reg);
7308 frv_ifcvt_add_insn (and_op, insn, TRUE);
7311 /* If this isn't the first statement in the nested if sequence, see if we
7312 are dealing with the same register. */
7313 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7316 COND_EXEC_TEST (pattern) = test = op1;
7319 /* If this isn't a nested if, reset state variables. */
7322 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7325 set = single_set_pattern (pattern);
7328 rtx dest = SET_DEST (set);
7329 rtx src = SET_SRC (set);
7330 enum machine_mode mode = GET_MODE (dest);
7332 /* Check for normal binary operators. */
7333 if (mode == SImode && ARITHMETIC_P (src))
7335 op0 = XEXP (src, 0);
7336 op1 = XEXP (src, 1);
7338 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7340 op1 = frv_ifcvt_load_value (op1, insn);
7342 COND_EXEC_CODE (pattern)
7343 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7351 /* For multiply by a constant, we need to handle the sign extending
7352 correctly. Add a USE of the value after the multiply to prevent flow
7353 from cratering because only one register out of the two were used. */
7354 else if (mode == DImode && GET_CODE (src) == MULT)
7356 op0 = XEXP (src, 0);
7357 op1 = XEXP (src, 1);
7358 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7360 op1 = frv_ifcvt_load_value (op1, insn);
7363 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7364 COND_EXEC_CODE (pattern)
7365 = gen_rtx_SET (VOIDmode, dest,
7366 gen_rtx_MULT (DImode, op0, op1));
7372 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7375 /* If we are just loading a constant created for a nested conditional
7376 execution statement, just load the constant without any conditional
7377 execution, since we know that the constant will not interfere with any
7379 else if (frv_ifcvt.scratch_insns_bitmap
7380 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7382 /* We must not unconditionally set a reg set used as
7383 scratch in the THEN branch if the same reg is live
7384 in the ELSE branch. */
7385 && REG_P (SET_DEST (set))
7386 && (! ce_info->else_bb
7387 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7388 || ! (REGNO_REG_SET_P
7389 (ce_info->else_bb->global_live_at_start,
7390 REGNO (SET_DEST (set))))))
7393 else if (mode == QImode || mode == HImode || mode == SImode
7396 int changed_p = FALSE;
7398 /* Check for just loading up a constant */
7399 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7401 src = frv_ifcvt_load_value (src, insn);
7408 /* See if we need to fix up stores */
7409 if (GET_CODE (dest) == MEM)
7411 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7416 else if (new_mem != dest)
7423 /* See if we need to fix up loads */
7424 if (GET_CODE (src) == MEM)
7426 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7431 else if (new_mem != src)
7438 /* If either src or destination changed, redo SET. */
7440 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7443 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7444 rewriting the CC register to be the same as the paired CC/CR register
7446 else if (mode == CC_CCRmode && COMPARISON_P (src))
7448 int regno = REGNO (XEXP (src, 0));
7451 if (ce_info->pass > 1
7452 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7453 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7455 src = gen_rtx_fmt_ee (GET_CODE (src),
7457 frv_ifcvt.nested_cc_reg,
7461 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7462 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7465 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7466 else if (ce_info->pass > 1
7467 && GET_CODE (dest) == REG
7468 && CC_P (REGNO (dest))
7469 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7470 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7472 && GET_CODE (src) == COMPARE)
7474 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7475 COND_EXEC_CODE (pattern)
7476 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7480 if (TARGET_DEBUG_COND_EXEC)
7482 rtx orig_pattern = PATTERN (insn);
7484 PATTERN (insn) = pattern;
7486 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7490 PATTERN (insn) = orig_pattern;
7496 if (TARGET_DEBUG_COND_EXEC)
7498 rtx orig_pattern = PATTERN (insn);
7500 PATTERN (insn) = orig_ce_pattern;
7502 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7506 PATTERN (insn) = orig_pattern;
7513 /* A C expression to perform any final machine dependent modifications in
7514 converting code to conditional execution in the code described by the
7515 conditional if information CE_INFO. */
7518 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7522 rtx p = frv_ifcvt.added_insns_list;
7525 /* Loop inserting the check insns. The last check insn is the first test,
7526 and is the appropriate place to insert constants. */
7532 rtx check_and_insert_insns = XEXP (p, 0);
7535 check_insn = XEXP (check_and_insert_insns, 0);
7536 existing_insn = XEXP (check_and_insert_insns, 1);
7539 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7540 the existing insn, otherwise it is to be inserted AFTER. */
7541 if (check_and_insert_insns->jump)
7543 emit_insn_before (check_insn, existing_insn);
7544 check_and_insert_insns->jump = 0;
7547 emit_insn_after (check_insn, existing_insn);
7549 free_EXPR_LIST_node (check_and_insert_insns);
7550 free_EXPR_LIST_node (old_p);
7552 while (p != NULL_RTX);
7554 /* Load up any constants needed into temp gprs */
7555 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7557 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7558 if (! frv_ifcvt.scratch_insns_bitmap)
7559 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7560 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7561 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7564 frv_ifcvt.added_insns_list = NULL_RTX;
7565 frv_ifcvt.cur_scratch_regs = 0;
7569 /* A C expression to cancel any machine dependent modifications in converting
7570 code to conditional execution in the code described by the conditional if
7571 information CE_INFO. */
7574 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7577 rtx p = frv_ifcvt.added_insns_list;
7579 /* Loop freeing up the EXPR_LIST's allocated. */
7580 while (p != NULL_RTX)
7582 rtx check_and_jump = XEXP (p, 0);
7586 free_EXPR_LIST_node (check_and_jump);
7587 free_EXPR_LIST_node (old_p);
7590 /* Release any temporary gprs allocated. */
7591 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7592 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7594 frv_ifcvt.added_insns_list = NULL_RTX;
7595 frv_ifcvt.cur_scratch_regs = 0;
7599 /* A C expression for the size in bytes of the trampoline, as an integer.
7603 setlo #0, <static_chain>
7605 sethi #0, <static_chain>
7606 jmpl @(gr0,<jmp_reg>) */
7609 frv_trampoline_size (void)
7612 /* Allocate room for the function descriptor and the lddi
7615 return 5 /* instructions */ * 4 /* instruction size. */;
7619 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7620 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7621 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7622 should be passed to the function when it is called.
7627 setlo #0, <static_chain>
7629 sethi #0, <static_chain>
7630 jmpl @(gr0,<jmp_reg>) */
7633 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7635 rtx sc_reg = force_reg (Pmode, static_chain);
7637 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7640 GEN_INT (frv_trampoline_size ()), SImode,
7646 /* Many machines have some registers that cannot be copied directly to or from
7647 memory or even from other types of registers. An example is the `MQ'
7648 register, which on most machines, can only be copied to or from general
7649 registers, but not memory. Some machines allow copying all registers to and
7650 from memory, but require a scratch register for stores to some memory
7651 locations (e.g., those with symbolic address on the RT, and those with
7652 certain symbolic address on the SPARC when compiling PIC). In some cases,
7653 both an intermediate and a scratch register are required.
7655 You should define these macros to indicate to the reload phase that it may
7656 need to allocate at least one register for a reload in addition to the
7657 register to contain the data. Specifically, if copying X to a register
7658 CLASS in MODE requires an intermediate register, you should define
7659 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7660 whose registers can be used as intermediate registers or scratch registers.
7662 If copying a register CLASS in MODE to X requires an intermediate or scratch
7663 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7664 largest register class required. If the requirements for input and output
7665 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7666 instead of defining both macros identically.
7668 The values returned by these macros are often `GENERAL_REGS'. Return
7669 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7670 to or from a register of CLASS in MODE without requiring a scratch register.
7671 Do not define this macro if it would always return `NO_REGS'.
7673 If a scratch register is required (either with or without an intermediate
7674 register), you should define patterns for `reload_inM' or `reload_outM', as
7675 required.. These patterns, which will normally be implemented with a
7676 `define_expand', should be similar to the `movM' patterns, except that
7677 operand 2 is the scratch register.
7679 Define constraints for the reload register and scratch register that contain
7680 a single register class. If the original reload register (whose class is
7681 CLASS) can meet the constraint given in the pattern, the value returned by
7682 these macros is used for the class of the scratch register. Otherwise, two
7683 additional reload registers are required. Their classes are obtained from
7684 the constraints in the insn pattern.
7686 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7687 either be in a hard register or in memory. Use `true_regnum' to find out;
7688 it will return -1 if the pseudo is in memory and the hard register number if
7689 it is in a register.
7691 These macros should not be used in the case where a particular class of
7692 registers can only be copied to memory and not to another class of
7693 registers. In that case, secondary reload registers are not needed and
7694 would not be helpful. Instead, a stack location must be used to perform the
7695 copy and the `movM' pattern should use memory as an intermediate storage.
7696 This case often occurs between floating-point and general registers. */
7699 frv_secondary_reload_class (enum reg_class class,
7700 enum machine_mode mode ATTRIBUTE_UNUSED,
7702 int in_p ATTRIBUTE_UNUSED)
7712 /* Accumulators/Accumulator guard registers need to go through floating
7718 if (x && GET_CODE (x) == REG)
7720 int regno = REGNO (x);
7722 if (ACC_P (regno) || ACCG_P (regno))
7727 /* Nonzero constants should be loaded into an FPR through a GPR. */
7731 if (x && CONSTANT_P (x) && !ZERO_P (x))
7737 /* All of these types need gpr registers. */
7749 /* The accumulators need fpr registers */
7762 /* A C expression whose value is nonzero if pseudos that have been assigned to
7763 registers of class CLASS would likely be spilled because registers of CLASS
7764 are needed for spill registers.
7766 The default value of this macro returns 1 if CLASS has exactly one register
7767 and zero otherwise. On most machines, this default should be used. Only
7768 define this macro to some other expression if pseudo allocated by
7769 `local-alloc.c' end up in memory because their hard registers were needed
7770 for spill registers. If this macro returns nonzero for those classes, those
7771 pseudos will only be allocated by `global.c', which knows how to reallocate
7772 the pseudo to another register. If there would not be another register
7773 available for reallocation, you should not change the definition of this
7774 macro since the only effect of such a definition would be to slow down
7775 register allocation. */
7778 frv_class_likely_spilled_p (enum reg_class class)
7805 /* An expression for the alignment of a structure field FIELD if the
7806 alignment computed in the usual way is COMPUTED. GCC uses this
7807 value instead of the value in `BIGGEST_ALIGNMENT' or
7808 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7810 /* The definition type of the bit field data is either char, short, long or
7811 long long. The maximum bit size is the number of bits of its own type.
7813 The bit field data is assigned to a storage unit that has an adequate size
7814 for bit field data retention and is located at the smallest address.
7816 Consecutive bit field data are packed at consecutive bits having the same
7817 storage unit, with regard to the type, beginning with the MSB and continuing
7820 If a field to be assigned lies over a bit field type boundary, its
7821 assignment is completed by aligning it with a boundary suitable for the
7824 When a bit field having a bit length of 0 is declared, it is forcibly
7825 assigned to the next storage unit.
7838 &x 00000000 00000000 00000000 00000000
7841 &x+4 00000000 00000000 00000000 00000000
7844 &x+8 00000000 00000000 00000000 00000000
7847 &x+12 00000000 00000000 00000000 00000000
7853 frv_adjust_field_align (tree field, int computed)
7855 /* Make sure that the bitfield is not wider than the type. */
7856 if (DECL_BIT_FIELD (field)
7857 && !DECL_ARTIFICIAL (field))
7859 tree parent = DECL_CONTEXT (field);
7860 tree prev = NULL_TREE;
7863 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7865 if (TREE_CODE (cur) != FIELD_DECL)
7874 /* If this isn't a :0 field and if the previous element is a bitfield
7875 also, see if the type is different, if so, we will need to align the
7876 bit-field to the next boundary. */
7878 && ! DECL_PACKED (field)
7879 && ! integer_zerop (DECL_SIZE (field))
7880 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7882 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7883 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7884 computed = (prev_align > cur_align) ? prev_align : cur_align;
7892 /* A C expression that is nonzero if it is permissible to store a value of mode
7893 MODE in hard register number REGNO (or in several registers starting with
7894 that one). For a machine where all registers are equivalent, a suitable
7897 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7899 It is not necessary for this macro to check for the numbers of fixed
7900 registers, because the allocation mechanism considers them to be always
7903 On some machines, double-precision values must be kept in even/odd register
7904 pairs. The way to implement that is to define this macro to reject odd
7905 register numbers for such modes.
7907 The minimum requirement for a mode to be OK in a register is that the
7908 `movMODE' instruction pattern support moves between the register and any
7909 other hard register for which the mode is OK; and that moving a value into
7910 the register and back out not alter it.
7912 Since the same instruction used to move `SImode' will work for all narrower
7913 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7914 to distinguish between these modes, provided you define patterns `movhi',
7915 etc., to take advantage of this. This is useful because of the interaction
7916 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7917 all integer modes to be tieable.
7919 Many machines have special registers for floating point arithmetic. Often
7920 people assume that floating point machine modes are allowed only in floating
7921 point registers. This is not true. Any registers that can hold integers
7922 can safely *hold* a floating point machine mode, whether or not floating
7923 arithmetic can be done on it in those registers. Integer move instructions
7924 can be used to move the values.
7926 On some machines, though, the converse is true: fixed-point machine modes
7927 may not go in floating registers. This is true if the floating registers
7928 normalize any value stored in them, because storing a non-floating value
7929 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7930 fixed-point machine modes in floating registers. But if the floating
7931 registers do not automatically normalize, if you can store any bit pattern
7932 in one and retrieve it unchanged without a trap, then any machine mode may
7933 go in a floating register, so you can define this macro to say so.
7935 The primary significance of special floating registers is rather that they
7936 are the registers acceptable in floating point arithmetic instructions.
7937 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7938 writing the proper constraints for those instructions.
7940 On some machines, the floating registers are especially slow to access, so
7941 that it is better to store a value in a stack frame than in such a register
7942 if floating point arithmetic is not being done. As long as the floating
7943 registers are not in class `GENERAL_REGS', they will not be used unless some
7944 pattern's constraint asks for one. */
7947 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7956 return ICC_P (regno) || GPR_P (regno);
7959 return CR_P (regno) || GPR_P (regno);
7962 return FCC_P (regno) || GPR_P (regno);
7968 /* Set BASE to the first register in REGNO's class. Set MASK to the
7969 bits that must be clear in (REGNO - BASE) for the register to be
7971 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7975 /* ACCGs store one byte. Two-byte quantities must start in
7976 even-numbered registers, four-byte ones in registers whose
7977 numbers are divisible by four, and so on. */
7979 mask = GET_MODE_SIZE (mode) - 1;
7983 /* The other registers store one word. */
7984 if (GPR_P (regno) || regno == AP_FIRST)
7987 else if (FPR_P (regno))
7990 else if (ACC_P (regno))
7993 else if (SPR_P (regno))
7994 return mode == SImode;
7996 /* Fill in the table. */
8000 /* Anything smaller than an SI is OK in any word-sized register. */
8001 if (GET_MODE_SIZE (mode) < 4)
8004 mask = (GET_MODE_SIZE (mode) / 4) - 1;
8006 return (((regno - base) & mask) == 0);
8013 /* A C expression for the number of consecutive hard registers, starting at
8014 register number REGNO, required to hold a value of mode MODE.
8016 On a machine where all registers are exactly one word, a suitable definition
8019 #define HARD_REGNO_NREGS(REGNO, MODE) \
8020 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8021 / UNITS_PER_WORD)) */
8023 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8024 that we can build the appropriate instructions to properly reload the
8025 values. Also, make the byte-sized accumulator guards use one guard
8029 frv_hard_regno_nregs (int regno, enum machine_mode mode)
8032 return GET_MODE_SIZE (mode);
8034 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8038 /* A C expression for the maximum number of consecutive registers of
8039 class CLASS needed to hold a value of mode MODE.
8041 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8042 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8043 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8045 This macro helps control the handling of multiple-word values in
8048 This declaration is required. */
8051 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
8053 if (class == ACCG_REGS)
8054 /* An N-byte value requires N accumulator guards. */
8055 return GET_MODE_SIZE (mode);
8057 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8061 /* A C expression that is nonzero if X is a legitimate constant for an
8062 immediate operand on the target machine. You can assume that X satisfies
8063 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8064 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8067 frv_legitimate_constant_p (rtx x)
8069 enum machine_mode mode = GET_MODE (x);
8071 /* frv_cannot_force_const_mem always returns true for FDPIC. This
8072 means that the move expanders will be expected to deal with most
8073 kinds of constant, regardless of what we return here.
8075 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
8076 a constant can be entered into reg_equiv_constant[]. If we return true,
8077 reload can create new instances of the constant whenever it likes.
8079 The idea is therefore to accept as many constants as possible (to give
8080 reload more freedom) while rejecting constants that can only be created
8081 at certain times. In particular, anything with a symbolic component will
8082 require use of the pseudo FDPIC register, which is only available before
8085 return LEGITIMATE_PIC_OPERAND_P (x);
8087 /* All of the integer constants are ok. */
8088 if (GET_CODE (x) != CONST_DOUBLE)
8091 /* double integer constants are ok. */
8092 if (mode == VOIDmode || mode == DImode)
8095 /* 0 is always ok. */
8096 if (x == CONST0_RTX (mode))
8099 /* If floating point is just emulated, allow any constant, since it will be
8100 constructed in the GPRs. */
8101 if (!TARGET_HAS_FPRS)
8104 if (mode == DFmode && !TARGET_DOUBLE)
8107 /* Otherwise store the constant away and do a load. */
8111 /* A C expression for the cost of moving data from a register in class FROM to
8112 one in class TO. The classes are expressed using the enumeration values
8113 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8114 interpreted relative to that.
8116 It is not required that the cost always equal 2 when FROM is the same as TO;
8117 on some machines it is expensive to move between registers if they are not
8120 If reload sees an insn consisting of a single `set' between two hard
8121 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8122 value of 2, reload does not check to ensure that the constraints of the insn
8123 are met. Setting a cost of other than 2 will allow reload to verify that
8124 the constraints are met. You should do this if the `movM' pattern's
8125 constraints do not allow such copying. */
8127 #define HIGH_COST 40
8128 #define MEDIUM_COST 3
8132 frv_register_move_cost (enum reg_class from, enum reg_class to)
8216 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8217 use ".picptr" to generate safe relocations for PIC code. We also
8218 need a fixup entry for aligned (non-debugging) code. */
8221 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8223 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8225 if (GET_CODE (value) == CONST
8226 || GET_CODE (value) == SYMBOL_REF
8227 || GET_CODE (value) == LABEL_REF)
8229 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8230 && SYMBOL_REF_FUNCTION_P (value))
8232 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8233 output_addr_const (asm_out_file, value);
8234 fputs (")\n", asm_out_file);
8237 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8238 && frv_function_symbol_referenced_p (value))
8240 if (aligned_p && !TARGET_FDPIC)
8242 static int label_num = 0;
8246 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8247 p = (* targetm.strip_name_encoding) (buf);
8249 fprintf (asm_out_file, "%s:\n", p);
8250 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8251 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8252 fprintf (asm_out_file, "\t.previous\n");
8254 assemble_integer_with_op ("\t.picptr\t", value);
8259 /* We've set the unaligned SI op to NULL, so we always have to
8260 handle the unaligned case here. */
8261 assemble_integer_with_op ("\t.4byte\t", value);
8265 return default_assemble_integer (value, size, aligned_p);
8268 /* Function to set up the backend function structure. */
8270 static struct machine_function *
8271 frv_init_machine_status (void)
8273 return ggc_alloc_cleared (sizeof (struct machine_function));
8276 /* Implement TARGET_SCHED_ISSUE_RATE. */
8279 frv_issue_rate (void)
8284 switch (frv_cpu_type)
8288 case FRV_CPU_SIMPLE:
8294 case FRV_CPU_GENERIC:
8296 case FRV_CPU_TOMCAT:
8301 /* Update the register state information, to know about which registers are set
8305 frv_registers_update (rtx x,
8306 unsigned char reg_state[],
8318 switch (GET_CODE (x))
8323 /* Clobber just modifies a register, it doesn't make it live. */
8325 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8326 flag | REGSTATE_MODIFIED);
8329 /* Pre modify updates the first argument, just references the second. */
8332 frv_registers_update (XEXP (x, 0), reg_state, modified, p_num_mod,
8333 flag | REGSTATE_MODIFIED | REGSTATE_LIVE);
8334 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod, flag);
8337 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8338 statement, but just to be sure, make sure it is the type of cond_exec
8342 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8343 && GET_CODE (XEXP (cond, 0)) == REG
8344 && CR_P (REGNO (XEXP (cond, 0)))
8345 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8346 && INTVAL (XEXP (cond, 1)) == 0
8347 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8349 frv_registers_update (cond, reg_state, modified, p_num_mod, flag);
8350 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8351 | ((GET_CODE (cond) == NE)
8353 : REGSTATE_IF_FALSE));
8355 frv_registers_update (XEXP (x, 1), reg_state, modified, p_num_mod,
8360 fatal_insn ("frv_registers_update", x);
8362 /* MEM resets the modification bits. */
8364 flag &= ~REGSTATE_MODIFIED;
8367 /* See if we need to set the modified flag. */
8369 reg = SUBREG_REG (x);
8370 if (GET_CODE (reg) == REG)
8372 regno = subreg_regno (x);
8373 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8380 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8384 if (flag & REGSTATE_MODIFIED)
8386 flag &= REGSTATE_MASK;
8387 while (regno < reg_max)
8389 int rs = reg_state[regno];
8393 if ((rs & REGSTATE_MODIFIED) == 0)
8395 modified[ *p_num_mod ] = regno;
8399 /* If the previous register state had the register as
8400 modified, possibly in some conditional execution context,
8401 and the current insn modifies in some other context, or
8402 outside of conditional execution, just mark the variable
8405 flag &= ~(REGSTATE_IF_EITHER | REGSTATE_CC_MASK);
8407 reg_state[regno] = (rs | flag);
8416 length = GET_RTX_LENGTH (GET_CODE (x));
8417 format = GET_RTX_FORMAT (GET_CODE (x));
8419 for (j = 0; j < length; ++j)
8424 frv_registers_update (XEXP (x, j), reg_state, modified, p_num_mod,
8430 if (XVEC (x, j) != 0)
8433 for (k = 0; k < XVECLEN (x, j); ++k)
8434 frv_registers_update (XVECEXP (x, j, k), reg_state, modified,
8440 /* Nothing to do. */
8449 /* Return if any registers in a hard register set were used an insn. */
8452 frv_registers_used_p (rtx x, unsigned char reg_state[], int flag)
8463 switch (GET_CODE (x))
8468 /* Skip clobber, that doesn't use the previous value. */
8472 /* For SET, if a conditional jump has occurred in the same insn, only
8473 allow a set of a CR register if that register is not currently live.
8474 This is because on the FR-V, B0/B1 instructions are always last.
8475 Otherwise, don't look at the result, except within a MEM, but do look
8478 dest = SET_DEST (x);
8479 if (flag & REGSTATE_CONDJUMP
8480 && GET_CODE (dest) == REG && CR_P (REGNO (dest))
8481 && (reg_state[ REGNO (dest) ] & REGSTATE_LIVE) != 0)
8484 if (GET_CODE (dest) == MEM)
8486 result = frv_registers_used_p (XEXP (dest, 0), reg_state, flag);
8491 return frv_registers_used_p (SET_SRC (x), reg_state, flag);
8493 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8494 statement, but just to be sure, make sure it is the type of cond_exec
8498 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8499 && GET_CODE (XEXP (cond, 0)) == REG
8500 && CR_P (REGNO (XEXP (cond, 0)))
8501 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8502 && INTVAL (XEXP (cond, 1)) == 0
8503 && (flag & (REGSTATE_MODIFIED | REGSTATE_IF_EITHER)) == 0)
8505 result = frv_registers_used_p (cond, reg_state, flag);
8509 flag |= ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8510 | ((GET_CODE (cond) == NE)
8512 : REGSTATE_IF_FALSE));
8514 return frv_registers_used_p (XEXP (x, 1), reg_state, flag);
8517 fatal_insn ("frv_registers_used_p", x);
8519 /* See if a register or subreg was modified in the same VLIW insn. */
8521 reg = SUBREG_REG (x);
8522 if (GET_CODE (reg) == REG)
8524 regno = subreg_regno (x);
8525 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8532 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8536 while (regno < reg_max)
8538 int rs = reg_state[regno];
8540 if (rs & REGSTATE_MODIFIED)
8542 int rs_if = rs & REGSTATE_IF_EITHER;
8543 int flag_if = flag & REGSTATE_IF_EITHER;
8545 /* Simple modification, no conditional execution */
8546 if ((rs & REGSTATE_IF_EITHER) == 0)
8549 /* See if the variable is only modified in a conditional
8550 execution expression opposite to the conditional execution
8551 expression that governs this expression (ie, true vs. false
8552 for the same CC register). If this isn't two halves of the
8553 same conditional expression, consider the register
8555 if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE)
8556 || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE))
8557 && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK)))
8569 length = GET_RTX_LENGTH (GET_CODE (x));
8570 format = GET_RTX_FORMAT (GET_CODE (x));
8572 for (j = 0; j < length; ++j)
8577 result = frv_registers_used_p (XEXP (x, j), reg_state, flag);
8584 if (XVEC (x, j) != 0)
8587 for (k = 0; k < XVECLEN (x, j); ++k)
8589 result = frv_registers_used_p (XVECEXP (x, j, k), reg_state,
8598 /* Nothing to do. */
8606 /* Return if any registers in a hard register set were set in an insn. */
8609 frv_registers_set_p (rtx x, unsigned char reg_state[], int modify_p)
8618 switch (GET_CODE (x))
8624 return frv_registers_set_p (XEXP (x, 0), reg_state, TRUE);
8628 return (frv_registers_set_p (XEXP (x, 0), reg_state, TRUE)
8629 || frv_registers_set_p (XEXP (x, 1), reg_state, FALSE));
8633 /* Just to be sure, make sure it is the type of cond_exec we
8635 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8636 && GET_CODE (XEXP (cond, 0)) == REG
8637 && CR_P (REGNO (XEXP (cond, 0)))
8638 && GET_CODE (XEXP (cond, 1)) == CONST_INT
8639 && INTVAL (XEXP (cond, 1)) == 0
8641 return frv_registers_set_p (XEXP (x, 1), reg_state, modify_p);
8643 fatal_insn ("frv_registers_set_p", x);
8645 /* MEM resets the modification bits. */
8650 /* See if we need to set the modified modify_p. */
8652 reg = SUBREG_REG (x);
8653 if (GET_CODE (reg) == REG)
8655 regno = subreg_regno (x);
8656 reg_max = REGNO (reg) + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8663 reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
8668 while (regno < reg_max)
8670 int rs = reg_state[regno];
8672 if (rs & REGSTATE_MODIFIED)
8680 length = GET_RTX_LENGTH (GET_CODE (x));
8681 format = GET_RTX_FORMAT (GET_CODE (x));
8683 for (j = 0; j < length; ++j)
8688 if (frv_registers_set_p (XEXP (x, j), reg_state, modify_p))
8694 if (XVEC (x, j) != 0)
8697 for (k = 0; k < XVECLEN (x, j); ++k)
8698 if (frv_registers_set_p (XVECEXP (x, j, k), reg_state,
8705 /* Nothing to do. */
8714 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8715 conditional branches/calls/jumps, etc. with previous insns where it can. It
8716 does not reorder the instructions. We assume the scheduler left the flow
8717 information in a reasonable state. */
8720 frv_pack_insns (void)
8722 state_t frv_state; /* frv state machine */
8723 int cur_start_vliw_p; /* current insn starts a VLIW insn */
8724 int next_start_vliw_p; /* next insn starts a VLIW insn */
8725 int cur_condjump_p; /* flag if current insn is a cond jump*/
8726 int next_condjump_p; /* flag if next insn is a cond jump */
8730 int num_mod = 0; /* # of modified registers */
8731 int modified[FIRST_PSEUDO_REGISTER]; /* registers modified in current VLIW */
8732 /* register state information */
8733 unsigned char reg_state[FIRST_PSEUDO_REGISTER];
8735 /* If we weren't going to pack the insns, don't bother with this pass. */
8737 || !flag_schedule_insns_after_reload
8738 || TARGET_NO_VLIW_BRANCH
8739 || frv_issue_rate () == 1)
8742 /* Set up the instruction and register states. */
8744 frv_state = (state_t) xmalloc (state_size ());
8745 memset (reg_state, REGSTATE_DEAD, sizeof (reg_state));
8747 /* Go through the insns, and repack the insns. */
8748 state_reset (frv_state);
8749 cur_start_vliw_p = FALSE;
8750 next_start_vliw_p = TRUE;
8752 next_condjump_p = 0;
8754 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
8756 enum rtx_code code = GET_CODE (insn);
8757 enum rtx_code pattern_code;
8759 /* For basic block begin notes redo the live information, and skip other
8763 if (NOTE_LINE_NUMBER (insn) == (int)NOTE_INSN_BASIC_BLOCK)
8767 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
8768 reg_state[j] &= ~ REGSTATE_LIVE;
8770 live = NOTE_BASIC_BLOCK (insn)->global_live_at_start;
8771 EXECUTE_IF_SET_IN_REG_SET(live, 0, j,
8773 reg_state[j] |= REGSTATE_LIVE;
8780 /* Things like labels reset everything. */
8783 next_start_vliw_p = TRUE;
8787 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8788 set on the USE insn that precedes the return, and potentially on
8789 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8790 holding the case table labels. */
8791 pattern_code = GET_CODE (PATTERN (insn));
8792 if (pattern_code == USE || pattern_code == CLOBBER
8793 || pattern_code == ADDR_VEC || pattern_code == ADDR_DIFF_VEC)
8795 CLEAR_VLIW_START (insn);
8799 cur_start_vliw_p = next_start_vliw_p;
8800 next_start_vliw_p = FALSE;
8802 cur_condjump_p |= next_condjump_p;
8803 next_condjump_p = 0;
8805 /* Unconditional branches and calls end the current VLIW insn. */
8806 if (code == CALL_INSN)
8808 next_start_vliw_p = TRUE;
8810 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8811 if (frv_cpu_type == FRV_CPU_TOMCAT)
8812 cur_start_vliw_p = TRUE;
8814 else if (code == JUMP_INSN)
8816 if (any_condjump_p (insn))
8817 next_condjump_p = REGSTATE_CONDJUMP;
8819 next_start_vliw_p = TRUE;
8822 /* Only allow setting a CCR register after a conditional branch. */
8823 else if (((cur_condjump_p & REGSTATE_CONDJUMP) != 0)
8824 && get_attr_type (insn) != TYPE_CCR)
8825 cur_start_vliw_p = TRUE;
8827 /* Determine if we need to start a new VLIW instruction. */
8828 if (cur_start_vliw_p
8829 /* Do not check for register conflicts in a setlo instruction
8830 because any output or true dependencies will be with the
8831 partnering sethi instruction, with which it can be packed.
8833 Although output dependencies are rare they are still
8834 possible. So check output dependencies in VLIW insn. */
8835 || (get_attr_type (insn) != TYPE_SETLO
8836 && (frv_registers_used_p (PATTERN (insn),
8839 || frv_registers_set_p (PATTERN (insn), reg_state, FALSE)))
8840 || state_transition (frv_state, insn) >= 0)
8842 SET_VLIW_START (insn);
8843 state_reset (frv_state);
8844 state_transition (frv_state, insn);
8847 /* Update the modified registers. */
8848 for (j = 0; j < num_mod; j++)
8849 reg_state[ modified[j] ] &= ~(REGSTATE_CC_MASK
8850 | REGSTATE_IF_EITHER
8851 | REGSTATE_MODIFIED);
8856 CLEAR_VLIW_START (insn);
8858 /* Record which registers are modified. */
8859 frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0);
8861 /* Process the death notices. */
8862 for (link = REG_NOTES (insn);
8864 link = XEXP (link, 1))
8866 rtx reg = XEXP (link, 0);
8868 if (REG_NOTE_KIND (link) == REG_DEAD && GET_CODE (reg) == REG)
8870 int regno = REGNO (reg);
8871 int n = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
8872 for (; regno < n; regno++)
8873 reg_state[regno] &= ~REGSTATE_LIVE;
8884 #define def_builtin(name, type, code) \
8885 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8887 struct builtin_description
8889 enum insn_code icode;
8891 enum frv_builtins code;
8892 enum rtx_code comparison;
8896 /* Media intrinsics that take a single, constant argument. */
8898 static struct builtin_description bdesc_set[] =
8900 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8903 /* Media intrinsics that take just one argument. */
8905 static struct builtin_description bdesc_1arg[] =
8907 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8908 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8909 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8910 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8911 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 }
8914 /* Media intrinsics that take two arguments. */
8916 static struct builtin_description bdesc_2arg[] =
8918 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8919 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8920 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8921 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8922 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8923 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8924 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8925 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8926 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8927 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8928 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8929 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8930 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8931 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8932 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8933 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
8934 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8935 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8936 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8937 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 }
8940 /* Media intrinsics that take two arguments, the first being an ACC number. */
8942 static struct builtin_description bdesc_cut[] =
8944 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8945 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8946 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8949 /* Two-argument media intrinsics with an immediate second argument. */
8951 static struct builtin_description bdesc_2argimm[] =
8953 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8954 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8955 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8956 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8957 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8958 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8959 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8960 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8961 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8962 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8963 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8964 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8965 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8966 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8967 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 }
8970 /* Media intrinsics that take two arguments and return void, the first argument
8971 being a pointer to 4 words in memory. */
8973 static struct builtin_description bdesc_void2arg[] =
8975 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8976 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8979 /* Media intrinsics that take three arguments, the first being a const_int that
8980 denotes an accumulator, and that return void. */
8982 static struct builtin_description bdesc_void3arg[] =
8984 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8985 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8986 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8987 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8988 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8989 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8990 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8991 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8992 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8993 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8994 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8995 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8996 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8997 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8998 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8999 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9000 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9001 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9002 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9003 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9004 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9005 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9006 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9007 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9008 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9011 /* Media intrinsics that take two accumulator numbers as argument and
9014 static struct builtin_description bdesc_voidacc[] =
9016 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9017 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9018 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9019 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9020 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9021 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9024 /* Initialize media builtins. */
9027 frv_init_builtins (void)
9029 tree endlink = void_list_node;
9030 tree accumulator = integer_type_node;
9031 tree integer = integer_type_node;
9032 tree voidt = void_type_node;
9033 tree uhalf = short_unsigned_type_node;
9034 tree sword1 = long_integer_type_node;
9035 tree uword1 = long_unsigned_type_node;
9036 tree sword2 = long_long_integer_type_node;
9037 tree uword2 = long_long_unsigned_type_node;
9038 tree uword4 = build_pointer_type (uword1);
9040 #define UNARY(RET, T1) \
9041 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9043 #define BINARY(RET, T1, T2) \
9044 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9045 tree_cons (NULL_TREE, T2, endlink)))
9047 #define TRINARY(RET, T1, T2, T3) \
9048 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9049 tree_cons (NULL_TREE, T2, \
9050 tree_cons (NULL_TREE, T3, endlink))))
9052 tree void_ftype_void = build_function_type (voidt, endlink);
9054 tree void_ftype_acc = UNARY (voidt, accumulator);
9055 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9056 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9057 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9058 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9059 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9060 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9061 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9062 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9064 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9065 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9066 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9067 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9068 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9069 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9070 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9071 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9072 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9073 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9074 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9076 tree sw1_ftype_int = UNARY (sword1, integer);
9077 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9078 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9080 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9081 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9082 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9083 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9084 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9086 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9088 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9089 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9090 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9091 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9092 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9093 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9094 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9095 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9096 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9097 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9098 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9099 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9100 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9101 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9102 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9103 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9104 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9105 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9106 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9107 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9108 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9109 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9110 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9111 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9112 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9113 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9114 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9115 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9116 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9117 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9118 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9119 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9120 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9121 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9122 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9123 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9124 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9125 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9126 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9127 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9128 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9129 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9130 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9131 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9132 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9133 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9134 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9135 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9136 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9137 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9138 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9139 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9140 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9141 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9142 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9143 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9144 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9145 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9146 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9147 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9148 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9149 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9150 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9151 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9152 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9153 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9154 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9155 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9156 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9157 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9158 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9159 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9160 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9161 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9162 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9163 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9164 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9165 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9166 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9167 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9168 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9169 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9170 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9171 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9178 /* Set the names for various arithmetic operations according to the
9181 frv_init_libfuncs (void)
9183 set_optab_libfunc (smod_optab, SImode, "__modi");
9184 set_optab_libfunc (umod_optab, SImode, "__umodi");
9186 set_optab_libfunc (add_optab, DImode, "__addll");
9187 set_optab_libfunc (sub_optab, DImode, "__subll");
9188 set_optab_libfunc (smul_optab, DImode, "__mulll");
9189 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9190 set_optab_libfunc (smod_optab, DImode, "__modll");
9191 set_optab_libfunc (umod_optab, DImode, "__umodll");
9192 set_optab_libfunc (and_optab, DImode, "__andll");
9193 set_optab_libfunc (ior_optab, DImode, "__orll");
9194 set_optab_libfunc (xor_optab, DImode, "__xorll");
9195 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9197 set_optab_libfunc (add_optab, SFmode, "__addf");
9198 set_optab_libfunc (sub_optab, SFmode, "__subf");
9199 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9200 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9202 set_optab_libfunc (add_optab, DFmode, "__addd");
9203 set_optab_libfunc (sub_optab, DFmode, "__subd");
9204 set_optab_libfunc (smul_optab, DFmode, "__muld");
9205 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9207 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9208 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9210 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9211 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9212 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9213 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9215 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9216 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9217 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9218 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9220 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9221 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9222 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9223 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9226 /* Convert an integer constant to an accumulator register. ICODE is the
9227 code of the target instruction, OPNUM is the number of the
9228 accumulator operand and OPVAL is the constant integer. Try both
9229 ACC and ACCG registers; only report an error if neither fit the
9233 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9237 if (GET_CODE (opval) != CONST_INT)
9239 error ("accumulator is not a constant integer");
9242 if (! IN_RANGE_P (INTVAL (opval), 0, NUM_ACCS - 1))
9244 error ("accumulator number is out of bounds");
9248 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9249 ACC_FIRST + INTVAL (opval));
9250 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9251 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9253 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9255 error ("inappropriate accumulator for `%s'", insn_data[icode].name);
9261 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9264 static enum machine_mode
9265 frv_matching_accg_mode (enum machine_mode mode)
9283 /* Return the accumulator guard that should be paired with accumulator
9284 register ACC. The mode of the returned register is in the same
9285 class as ACC, but is four times smaller. */
9288 frv_matching_accg_for_acc (rtx acc)
9290 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9291 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9294 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9295 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9299 frv_read_argument (tree *arglistptr)
9301 tree next = TREE_VALUE (*arglistptr);
9302 *arglistptr = TREE_CHAIN (*arglistptr);
9303 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9306 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9307 The instruction should require a constant operand of some sort. The
9308 function prints an error if OPVAL is not valid. */
9311 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9313 if (GET_CODE (opval) != CONST_INT)
9315 error ("`%s' expects a constant argument", insn_data[icode].name);
9318 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9320 error ("constant argument out of range for `%s'", insn_data[icode].name);
9326 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9327 if it's not null, has the right mode, and satisfies operand 0's
9331 frv_legitimize_target (enum insn_code icode, rtx target)
9333 enum machine_mode mode = insn_data[icode].operand[0].mode;
9336 || GET_MODE (target) != mode
9337 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9338 return gen_reg_rtx (mode);
9343 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9344 check whether ARG satisfies the operand's constraints. If it doesn't,
9345 copy ARG to a temporary register and return that. Otherwise return ARG
9349 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9351 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9353 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9356 return copy_to_mode_reg (mode, arg);
9359 /* Expand builtins that take a single, constant argument. At the moment,
9360 only MHDSETS falls into this category. */
9363 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9366 rtx op0 = frv_read_argument (&arglist);
9368 if (! frv_check_constant_argument (icode, 1, op0))
9371 target = frv_legitimize_target (icode, target);
9372 pat = GEN_FCN (icode) (target, op0);
9380 /* Expand builtins that take one operand. */
9383 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9386 rtx op0 = frv_read_argument (&arglist);
9388 target = frv_legitimize_target (icode, target);
9389 op0 = frv_legitimize_argument (icode, 1, op0);
9390 pat = GEN_FCN (icode) (target, op0);
9398 /* Expand builtins that take two operands. */
9401 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9404 rtx op0 = frv_read_argument (&arglist);
9405 rtx op1 = frv_read_argument (&arglist);
9407 target = frv_legitimize_target (icode, target);
9408 op0 = frv_legitimize_argument (icode, 1, op0);
9409 op1 = frv_legitimize_argument (icode, 2, op1);
9410 pat = GEN_FCN (icode) (target, op0, op1);
9418 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9422 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9425 rtx op0 = frv_read_argument (&arglist);
9426 rtx op1 = frv_read_argument (&arglist);
9429 target = frv_legitimize_target (icode, target);
9430 op0 = frv_int_to_acc (icode, 1, op0);
9434 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9436 if (! frv_check_constant_argument (icode, 2, op1))
9440 op1 = frv_legitimize_argument (icode, 2, op1);
9442 op2 = frv_matching_accg_for_acc (op0);
9443 pat = GEN_FCN (icode) (target, op0, op1, op2);
9451 /* Expand builtins that take two operands and the second is immediate. */
9454 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9457 rtx op0 = frv_read_argument (&arglist);
9458 rtx op1 = frv_read_argument (&arglist);
9460 if (! frv_check_constant_argument (icode, 2, op1))
9463 target = frv_legitimize_target (icode, target);
9464 op0 = frv_legitimize_argument (icode, 1, op0);
9465 pat = GEN_FCN (icode) (target, op0, op1);
9473 /* Expand builtins that take two operands, the first operand being a pointer to
9474 ints and return void. */
9477 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9480 rtx op0 = frv_read_argument (&arglist);
9481 rtx op1 = frv_read_argument (&arglist);
9482 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9485 if (GET_CODE (op0) != MEM)
9489 if (! offsettable_address_p (0, mode0, op0))
9491 reg = gen_reg_rtx (Pmode);
9492 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9495 op0 = gen_rtx_MEM (SImode, reg);
9498 addr = XEXP (op0, 0);
9499 if (! offsettable_address_p (0, mode0, addr))
9500 addr = copy_to_mode_reg (Pmode, op0);
9502 op0 = change_address (op0, V4SImode, addr);
9503 op1 = frv_legitimize_argument (icode, 1, op1);
9504 pat = GEN_FCN (icode) (op0, op1);
9512 /* Expand builtins that take three operands and return void. The first
9513 argument must be a constant that describes a pair or quad accumulators. A
9514 fourth argument is created that is the accumulator guard register that
9515 corresponds to the accumulator. */
9518 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9521 rtx op0 = frv_read_argument (&arglist);
9522 rtx op1 = frv_read_argument (&arglist);
9523 rtx op2 = frv_read_argument (&arglist);
9526 op0 = frv_int_to_acc (icode, 0, op0);
9530 op1 = frv_legitimize_argument (icode, 1, op1);
9531 op2 = frv_legitimize_argument (icode, 2, op2);
9532 op3 = frv_matching_accg_for_acc (op0);
9533 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9541 /* Expand builtins that perform accumulator-to-accumulator operations.
9542 These builtins take two accumulator numbers as argument and return
9546 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9549 rtx op0 = frv_read_argument (&arglist);
9550 rtx op1 = frv_read_argument (&arglist);
9554 op0 = frv_int_to_acc (icode, 0, op0);
9558 op1 = frv_int_to_acc (icode, 1, op1);
9562 op2 = frv_matching_accg_for_acc (op0);
9563 op3 = frv_matching_accg_for_acc (op1);
9564 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9572 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9573 number as argument. */
9576 frv_expand_mclracc_builtin (tree arglist)
9578 enum insn_code icode = CODE_FOR_mclracc;
9580 rtx op0 = frv_read_argument (&arglist);
9582 op0 = frv_int_to_acc (icode, 0, op0);
9586 pat = GEN_FCN (icode) (op0);
9593 /* Expand builtins that take no arguments. */
9596 frv_expand_noargs_builtin (enum insn_code icode)
9598 rtx pat = GEN_FCN (icode) (const0_rtx);
9605 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9606 number or accumulator guard number as argument and return an SI integer. */
9609 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
9612 rtx target = gen_reg_rtx (SImode);
9613 rtx op0 = frv_read_argument (&arglist);
9615 op0 = frv_int_to_acc (icode, 1, op0);
9619 pat = GEN_FCN (icode) (target, op0);
9627 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9628 accumulator guard as their first argument and an SImode value as their
9632 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
9635 rtx op0 = frv_read_argument (&arglist);
9636 rtx op1 = frv_read_argument (&arglist);
9638 op0 = frv_int_to_acc (icode, 0, op0);
9642 op1 = frv_legitimize_argument (icode, 1, op1);
9643 pat = GEN_FCN (icode) (op0, op1);
9650 /* Expand builtins. */
9653 frv_expand_builtin (tree exp,
9655 rtx subtarget ATTRIBUTE_UNUSED,
9656 enum machine_mode mode ATTRIBUTE_UNUSED,
9657 int ignore ATTRIBUTE_UNUSED)
9659 tree arglist = TREE_OPERAND (exp, 1);
9660 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9661 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9663 struct builtin_description *d;
9667 error ("media functions are not available unless -mmedia is used");
9673 case FRV_BUILTIN_MCOP1:
9674 case FRV_BUILTIN_MCOP2:
9675 case FRV_BUILTIN_MDUNPACKH:
9676 case FRV_BUILTIN_MBTOHE:
9677 if (! TARGET_MEDIA_REV1)
9679 error ("this media function is only available on the fr500");
9684 case FRV_BUILTIN_MQXMACHS:
9685 case FRV_BUILTIN_MQXMACXHS:
9686 case FRV_BUILTIN_MQMACXHS:
9687 case FRV_BUILTIN_MADDACCS:
9688 case FRV_BUILTIN_MSUBACCS:
9689 case FRV_BUILTIN_MASACCS:
9690 case FRV_BUILTIN_MDADDACCS:
9691 case FRV_BUILTIN_MDSUBACCS:
9692 case FRV_BUILTIN_MDASACCS:
9693 case FRV_BUILTIN_MABSHS:
9694 case FRV_BUILTIN_MDROTLI:
9695 case FRV_BUILTIN_MCPLHI:
9696 case FRV_BUILTIN_MCPLI:
9697 case FRV_BUILTIN_MDCUTSSI:
9698 case FRV_BUILTIN_MQSATHS:
9699 case FRV_BUILTIN_MHSETLOS:
9700 case FRV_BUILTIN_MHSETLOH:
9701 case FRV_BUILTIN_MHSETHIS:
9702 case FRV_BUILTIN_MHSETHIH:
9703 case FRV_BUILTIN_MHDSETS:
9704 case FRV_BUILTIN_MHDSETH:
9705 if (! TARGET_MEDIA_REV2)
9707 error ("this media function is only available on the fr400");
9716 /* Expand unique builtins. */
9720 case FRV_BUILTIN_MTRAP:
9721 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9723 case FRV_BUILTIN_MCLRACC:
9724 return frv_expand_mclracc_builtin (arglist);
9726 case FRV_BUILTIN_MCLRACCA:
9728 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9730 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9732 case FRV_BUILTIN_MRDACC:
9733 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
9735 case FRV_BUILTIN_MRDACCG:
9736 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
9738 case FRV_BUILTIN_MWTACC:
9739 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
9741 case FRV_BUILTIN_MWTACCG:
9742 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
9748 /* Expand groups of builtins. */
9750 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9751 if (d->code == fcode)
9752 return frv_expand_set_builtin (d->icode, arglist, target);
9754 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9755 if (d->code == fcode)
9756 return frv_expand_unop_builtin (d->icode, arglist, target);
9758 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9759 if (d->code == fcode)
9760 return frv_expand_binop_builtin (d->icode, arglist, target);
9762 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9763 if (d->code == fcode)
9764 return frv_expand_cut_builtin (d->icode, arglist, target);
9766 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9767 if (d->code == fcode)
9768 return frv_expand_binopimm_builtin (d->icode, arglist, target);
9770 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9771 if (d->code == fcode)
9772 return frv_expand_voidbinop_builtin (d->icode, arglist);
9774 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9775 if (d->code == fcode)
9776 return frv_expand_voidtriop_builtin (d->icode, arglist);
9778 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9779 if (d->code == fcode)
9780 return frv_expand_voidaccop_builtin (d->icode, arglist);
9786 frv_in_small_data_p (tree decl)
9791 /* Don't apply the -G flag to internal compiler structures. We
9792 should leave such structures in the main data section, partly
9793 for efficiency and partly because the size of some of them
9794 (such as C++ typeinfos) is not known until later. */
9795 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9798 /* If we already know which section the decl should be in, see if
9799 it's a small data section. */
9800 section_name = DECL_SECTION_NAME (decl);
9803 if (TREE_CODE (section_name) != STRING_CST)
9805 if (frv_string_begins_with (section_name, ".sdata"))
9807 if (frv_string_begins_with (section_name, ".sbss"))
9812 size = int_size_in_bytes (TREE_TYPE (decl));
9813 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9820 frv_rtx_costs (rtx x,
9821 int code ATTRIBUTE_UNUSED,
9822 int outer_code ATTRIBUTE_UNUSED,
9825 if (outer_code == MEM)
9827 /* Don't differentiate between memory addresses. All the ones
9828 we accept have equal cost. */
9829 *total = COSTS_N_INSNS (0);
9836 /* Make 12 bit integers really cheap. */
9837 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9848 *total = COSTS_N_INSNS (2);
9862 if (GET_MODE (x) == SImode)
9863 *total = COSTS_N_INSNS (1);
9864 else if (GET_MODE (x) == DImode)
9865 *total = COSTS_N_INSNS (2);
9867 *total = COSTS_N_INSNS (3);
9871 if (GET_MODE (x) == SImode)
9872 *total = COSTS_N_INSNS (2);
9874 *total = COSTS_N_INSNS (6); /* guess */
9881 *total = COSTS_N_INSNS (18);
9885 *total = COSTS_N_INSNS (3);
9894 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9897 assemble_align (POINTER_SIZE);
9900 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9904 assemble_integer_with_op ("\t.picptr\t", symbol);
9908 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9911 assemble_align (POINTER_SIZE);
9914 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9918 assemble_integer_with_op ("\t.picptr\t", symbol);
9921 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9924 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9925 int incoming ATTRIBUTE_UNUSED)
9927 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);