1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Define the information needed to generate branch and scc insns. This is
197 stored from the compare operation. */
201 /* Conditional execution support gathered together in one structure. */
204 /* Linked list of insns to add if the conditional execution conversion was
205 successful. Each link points to an EXPR_LIST which points to the pattern
206 of the insn to add, and the insn to be inserted before. */
207 rtx added_insns_list;
209 /* Identify which registers are safe to allocate for if conversions to
210 conditional execution. We keep the last allocated register in the
211 register classes between COND_EXEC statements. This will mean we allocate
212 different registers for each different COND_EXEC group if we can. This
213 might allow the scheduler to intermix two different COND_EXEC sections. */
214 frv_tmp_reg_t tmp_reg;
216 /* For nested IFs, identify which CC registers are used outside of setting
217 via a compare isnsn, and using via a check insn. This will allow us to
218 know if we can rewrite the register to use a different register that will
219 be paired with the CR register controlling the nested IF-THEN blocks. */
220 HARD_REG_SET nested_cc_ok_rewrite;
222 /* Temporary registers allocated to hold constants during conditional
224 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
226 /* Current number of temp registers available. */
227 int cur_scratch_regs;
229 /* Number of nested conditional execution blocks. */
230 int num_nested_cond_exec;
232 /* Map of insns that set up constants in scratch registers. */
233 bitmap scratch_insns_bitmap;
235 /* Conditional execution test register (CC0..CC7). */
238 /* Conditional execution compare register that is paired with cr_reg, so that
239 nested compares can be done. The csubcc and caddcc instructions don't
240 have enough bits to specify both a CC register to be set and a CR register
241 to do the test on, so the same bit number is used for both. Needless to
242 say, this is rather inconvenient for GCC. */
245 /* Extra CR registers used for &&, ||. */
249 /* Previous CR used in nested if, to make sure we are dealing with the same
250 nested if as the previous statement. */
251 rtx last_nested_if_cr;
255 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
257 /* Map register number to smallest register class. */
258 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
260 /* Map class letter into register class. */
261 enum reg_class reg_class_from_letter[256];
263 /* Cached value of frv_stack_info. */
264 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
267 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
269 /* Forward references */
271 static bool frv_handle_option (size_t, const char *, int);
272 static int frv_default_flags_for_cpu (void);
273 static int frv_string_begins_with (const_tree, const char *);
274 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
281 static rtx single_set_pattern (rtx);
282 static int frv_function_contains_far_jump (void);
283 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
287 static rtx frv_frame_offset_rtx (int);
288 static rtx frv_frame_mem (enum machine_mode, rtx, int);
289 static rtx frv_dwarf_store (rtx, int);
290 static void frv_frame_insn (rtx, rtx);
291 static void frv_frame_access (frv_frame_accessor_t*,
293 static void frv_frame_access_multi (frv_frame_accessor_t*,
295 static void frv_frame_access_standard_regs (enum frv_stack_op,
297 static struct machine_function *frv_init_machine_status (void);
298 static rtx frv_int_to_acc (enum insn_code, int, rtx);
299 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
300 static rtx frv_read_argument (tree, unsigned int);
301 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
302 static int frv_check_constant_argument (enum insn_code, int, rtx);
303 static rtx frv_legitimize_target (enum insn_code, rtx);
304 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
305 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static int frv_clear_registers_used (rtx *, void *);
323 static void frv_ifcvt_add_insn (rtx, rtx, int);
324 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
325 static rtx frv_ifcvt_load_value (rtx, rtx);
326 static int frv_acc_group_1 (rtx *, void *);
327 static unsigned int frv_insn_unit (rtx);
328 static bool frv_issues_to_branch_unit_p (rtx);
329 static int frv_cond_flags (rtx);
330 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
331 static int frv_registers_conflict_p_1 (rtx *, void *);
332 static bool frv_registers_conflict_p (rtx);
333 static void frv_registers_update_1 (rtx, const_rtx, void *);
334 static void frv_registers_update (rtx);
335 static void frv_start_packet (void);
336 static void frv_start_packet_block (void);
337 static void frv_finish_packet (void (*) (void));
338 static bool frv_pack_insn_p (rtx);
339 static void frv_add_insn_to_packet (rtx);
340 static void frv_insert_nop_in_packet (rtx);
341 static bool frv_for_each_packet (void (*) (void));
342 static bool frv_sort_insn_group_1 (enum frv_insn_group,
343 unsigned int, unsigned int,
344 unsigned int, unsigned int,
346 static int frv_compare_insns (const void *, const void *);
347 static void frv_sort_insn_group (enum frv_insn_group);
348 static void frv_reorder_packet (void);
349 static void frv_fill_unused_units (enum frv_insn_group);
350 static void frv_align_label (void);
351 static void frv_reorg_packet (void);
352 static void frv_register_nop (rtx);
353 static void frv_reorg (void);
354 static void frv_pack_insns (void);
355 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
356 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
357 static bool frv_assemble_integer (rtx, unsigned, int);
358 static void frv_init_builtins (void);
359 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
360 static void frv_init_libfuncs (void);
361 static bool frv_in_small_data_p (const_tree);
362 static void frv_asm_output_mi_thunk
363 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
364 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
367 static rtx frv_expand_builtin_saveregs (void);
368 static void frv_expand_builtin_va_start (tree, rtx);
369 static bool frv_rtx_costs (rtx, int, int, int*, bool);
370 static void frv_asm_out_constructor (rtx, int);
371 static void frv_asm_out_destructor (rtx, int);
372 static bool frv_function_symbol_referenced_p (rtx);
373 static bool frv_cannot_force_const_mem (rtx);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec *);
377 static bool frv_function_ok_for_sibcall (tree, tree);
378 static rtx frv_struct_value_rtx (tree, int);
379 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
380 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
382 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
384 static bool frv_secondary_reload (bool, rtx, enum reg_class,
386 secondary_reload_info *);
388 /* Allow us to easily change the default for -malloc-cc. */
389 #ifndef DEFAULT_NO_ALLOC_CC
390 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
392 #define MASK_DEFAULT_ALLOC_CC 0
395 /* Initialize the GCC target structure. */
396 #undef TARGET_ASM_FUNCTION_PROLOGUE
397 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
398 #undef TARGET_ASM_FUNCTION_EPILOGUE
399 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
400 #undef TARGET_ASM_INTEGER
401 #define TARGET_ASM_INTEGER frv_assemble_integer
402 #undef TARGET_DEFAULT_TARGET_FLAGS
403 #define TARGET_DEFAULT_TARGET_FLAGS \
404 (MASK_DEFAULT_ALLOC_CC \
411 #undef TARGET_HANDLE_OPTION
412 #define TARGET_HANDLE_OPTION frv_handle_option
413 #undef TARGET_INIT_BUILTINS
414 #define TARGET_INIT_BUILTINS frv_init_builtins
415 #undef TARGET_EXPAND_BUILTIN
416 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
417 #undef TARGET_INIT_LIBFUNCS
418 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
419 #undef TARGET_IN_SMALL_DATA_P
420 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
421 #undef TARGET_RTX_COSTS
422 #define TARGET_RTX_COSTS frv_rtx_costs
423 #undef TARGET_ASM_CONSTRUCTOR
424 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
425 #undef TARGET_ASM_DESTRUCTOR
426 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
428 #undef TARGET_ASM_OUTPUT_MI_THUNK
429 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
430 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
431 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
433 #undef TARGET_SCHED_ISSUE_RATE
434 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
436 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
437 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
438 #undef TARGET_CANNOT_FORCE_CONST_MEM
439 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
441 #undef TARGET_HAVE_TLS
442 #define TARGET_HAVE_TLS HAVE_AS_TLS
444 #undef TARGET_STRUCT_VALUE_RTX
445 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
446 #undef TARGET_MUST_PASS_IN_STACK
447 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
448 #undef TARGET_PASS_BY_REFERENCE
449 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
450 #undef TARGET_ARG_PARTIAL_BYTES
451 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
453 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
454 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
455 #undef TARGET_SETUP_INCOMING_VARARGS
456 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
457 #undef TARGET_MACHINE_DEPENDENT_REORG
458 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
460 #undef TARGET_EXPAND_BUILTIN_VA_START
461 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
464 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
465 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
468 #undef TARGET_SECONDARY_RELOAD
469 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
471 struct gcc_target targetm = TARGET_INITIALIZER;
473 #define FRV_SYMBOL_REF_TLS_P(RTX) \
474 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
477 /* Any function call that satisfies the machine-independent
478 requirements is eligible on FR-V. */
481 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
482 tree exp ATTRIBUTE_UNUSED)
487 /* Return true if SYMBOL is a small data symbol and relocation RELOC
488 can be used to access it directly in a load or store. */
490 static FRV_INLINE bool
491 frv_small_data_reloc_p (rtx symbol, int reloc)
493 return (GET_CODE (symbol) == SYMBOL_REF
494 && SYMBOL_REF_SMALL_P (symbol)
495 && (!TARGET_FDPIC || flag_pic == 1)
496 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
499 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
503 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
505 if (GET_CODE (x) == CONST)
509 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
511 unspec->offset += INTVAL (XEXP (x, 1));
514 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
516 unspec->symbol = XVECEXP (x, 0, 0);
517 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
519 if (unspec->offset == 0)
522 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
523 && unspec->offset > 0
524 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
531 /* Decide whether we can force certain constants to memory. If we
532 decide we can't, the caller should be able to cope with it in
535 We never allow constants to be forced into memory for TARGET_FDPIC.
536 This is necessary for several reasons:
538 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
539 target-independent code will try to force them into the constant
540 pool, thus leading to infinite recursion.
542 2. We can never introduce new constant pool references during reload.
543 Any such reference would require use of the pseudo FDPIC register.
545 3. We can't represent a constant added to a function pointer (which is
546 not the same as a pointer to a function+constant).
548 4. In many cases, it's more efficient to calculate the constant in-line. */
551 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
556 /* Implement TARGET_HANDLE_OPTION. */
559 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
564 if (strcmp (arg, "simple") == 0)
565 frv_cpu_type = FRV_CPU_SIMPLE;
566 else if (strcmp (arg, "tomcat") == 0)
567 frv_cpu_type = FRV_CPU_TOMCAT;
568 else if (strcmp (arg, "fr550") == 0)
569 frv_cpu_type = FRV_CPU_FR550;
570 else if (strcmp (arg, "fr500") == 0)
571 frv_cpu_type = FRV_CPU_FR500;
572 else if (strcmp (arg, "fr450") == 0)
573 frv_cpu_type = FRV_CPU_FR450;
574 else if (strcmp (arg, "fr405") == 0)
575 frv_cpu_type = FRV_CPU_FR405;
576 else if (strcmp (arg, "fr400") == 0)
577 frv_cpu_type = FRV_CPU_FR400;
578 else if (strcmp (arg, "fr300") == 0)
579 frv_cpu_type = FRV_CPU_FR300;
580 else if (strcmp (arg, "frv") == 0)
581 frv_cpu_type = FRV_CPU_GENERIC;
592 frv_default_flags_for_cpu (void)
594 switch (frv_cpu_type)
596 case FRV_CPU_GENERIC:
597 return MASK_DEFAULT_FRV;
600 return MASK_DEFAULT_FR550;
604 return MASK_DEFAULT_FR500;
607 return MASK_DEFAULT_FR450;
611 return MASK_DEFAULT_FR400;
615 return MASK_DEFAULT_SIMPLE;
622 /* Sometimes certain combinations of command options do not make
623 sense on a particular target machine. You can define a macro
624 `OVERRIDE_OPTIONS' to take account of this. This macro, if
625 defined, is executed once just after all the command options have
628 Don't use this macro to turn on various extra optimizations for
629 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
632 frv_override_options (void)
637 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
639 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
640 linker about linking pic and non-pic code. */
643 if (!flag_pic) /* -fPIC */
646 if (! g_switch_set) /* -G0 */
653 /* A C expression whose value is a register class containing hard
654 register REGNO. In general there is more than one such class;
655 choose a class which is "minimal", meaning that no smaller class
656 also contains the register. */
658 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
660 enum reg_class rclass;
664 int gpr_reg = regno - GPR_FIRST;
666 if (gpr_reg == GR8_REG)
669 else if (gpr_reg == GR9_REG)
672 else if (gpr_reg == GR14_REG)
673 rclass = FDPIC_FPTR_REGS;
675 else if (gpr_reg == FDPIC_REGNO)
678 else if ((gpr_reg & 3) == 0)
681 else if ((gpr_reg & 1) == 0)
688 else if (FPR_P (regno))
690 int fpr_reg = regno - GPR_FIRST;
691 if ((fpr_reg & 3) == 0)
692 rclass = QUAD_FPR_REGS;
694 else if ((fpr_reg & 1) == 0)
701 else if (regno == LR_REGNO)
704 else if (regno == LCR_REGNO)
707 else if (ICC_P (regno))
710 else if (FCC_P (regno))
713 else if (ICR_P (regno))
716 else if (FCR_P (regno))
719 else if (ACC_P (regno))
721 int r = regno - ACC_FIRST;
723 rclass = QUAD_ACC_REGS;
724 else if ((r & 1) == 0)
725 rclass = EVEN_ACC_REGS;
730 else if (ACCG_P (regno))
736 regno_reg_class[regno] = rclass;
739 /* Check for small data option */
741 g_switch_value = SDATA_DEFAULT_SIZE;
743 /* A C expression which defines the machine-dependent operand
744 constraint letters for register classes. If CHAR is such a
745 letter, the value should be the register class corresponding to
746 it. Otherwise, the value should be `NO_REGS'. The register
747 letter `r', corresponding to class `GENERAL_REGS', will not be
748 passed to this macro; you do not need to handle it.
750 The following letters are unavailable, due to being used as
755 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
756 'Q', 'R', 'S', 'T', 'U'
758 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
760 for (i = 0; i < 256; i++)
761 reg_class_from_letter[i] = NO_REGS;
763 reg_class_from_letter['a'] = ACC_REGS;
764 reg_class_from_letter['b'] = EVEN_ACC_REGS;
765 reg_class_from_letter['c'] = CC_REGS;
766 reg_class_from_letter['d'] = GPR_REGS;
767 reg_class_from_letter['e'] = EVEN_REGS;
768 reg_class_from_letter['f'] = FPR_REGS;
769 reg_class_from_letter['h'] = FEVEN_REGS;
770 reg_class_from_letter['l'] = LR_REG;
771 reg_class_from_letter['q'] = QUAD_REGS;
772 reg_class_from_letter['t'] = ICC_REGS;
773 reg_class_from_letter['u'] = FCC_REGS;
774 reg_class_from_letter['v'] = ICR_REGS;
775 reg_class_from_letter['w'] = FCR_REGS;
776 reg_class_from_letter['x'] = QUAD_FPR_REGS;
777 reg_class_from_letter['y'] = LCR_REG;
778 reg_class_from_letter['z'] = SPR_REGS;
779 reg_class_from_letter['A'] = QUAD_ACC_REGS;
780 reg_class_from_letter['B'] = ACCG_REGS;
781 reg_class_from_letter['C'] = CR_REGS;
782 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
783 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
785 /* There is no single unaligned SI op for PIC code. Sometimes we
786 need to use ".4byte" and sometimes we need to use ".picptr".
787 See frv_assemble_integer for details. */
788 if (flag_pic || TARGET_FDPIC)
789 targetm.asm_out.unaligned_op.si = 0;
791 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
792 target_flags |= MASK_LINKED_FP;
794 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
795 target_flags |= MASK_OPTIMIZE_MEMBAR;
797 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
798 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
800 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
801 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
803 init_machine_status = frv_init_machine_status;
807 /* Some machines may desire to change what optimizations are performed for
808 various optimization levels. This macro, if defined, is executed once just
809 after the optimization level is determined and before the remainder of the
810 command options have been parsed. Values set in this macro are used as the
811 default values for the other command line options.
813 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
814 `-O' is specified, and 0 if neither is specified.
816 SIZE is nonzero if `-Os' is specified, 0 otherwise.
818 You should not use this macro to change options that are not
819 machine-specific. These should uniformly selected by the same optimization
820 level on all supported machines. Use this macro to enable machine-specific
823 *Do not examine `write_symbols' in this macro!* The debugging options are
824 *not supposed to alter the generated code. */
826 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
827 scheduling pass at the current time. */
829 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
833 #ifdef DISABLE_SCHED2
834 flag_schedule_insns_after_reload = 0;
843 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
846 frv_string_begins_with (const_tree name, const char *prefix)
848 const int prefix_len = strlen (prefix);
850 /* Remember: NAME's length includes the null terminator. */
851 return (TREE_STRING_LENGTH (name) > prefix_len
852 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
855 /* Zero or more C statements that may conditionally modify two variables
856 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
857 been initialized from the two preceding macros.
859 This is necessary in case the fixed or call-clobbered registers depend on
862 You need not define this macro if it has no work to do.
864 If the usage of an entire class of registers depends on the target flags,
865 you may indicate this to GCC by using this macro to modify `fixed_regs' and
866 `call_used_regs' to 1 for each of the registers in the classes which should
867 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
868 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
870 (However, if this class is not included in `GENERAL_REGS' and all of the
871 insn patterns whose constraints permit this class are controlled by target
872 switches, then GCC will automatically avoid using these registers when the
873 target switches are opposed to them.) */
876 frv_conditional_register_usage (void)
880 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
881 fixed_regs[i] = call_used_regs[i] = 1;
883 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
884 fixed_regs[i] = call_used_regs[i] = 1;
886 /* Reserve the registers used for conditional execution. At present, we need
887 1 ICC and 1 ICR register. */
888 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
889 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
893 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
894 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
895 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
896 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
900 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
901 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
904 /* If -fpic, SDA_BASE_REG is the PIC register. */
905 if (g_switch_value == 0 && !flag_pic)
906 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
909 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
915 * Compute the stack frame layout
918 * +---------------+-----------------------+-----------------------+
919 * |Register |type |caller-save/callee-save|
920 * +---------------+-----------------------+-----------------------+
921 * |GR0 |Zero register | - |
922 * |GR1 |Stack pointer(SP) | - |
923 * |GR2 |Frame pointer(FP) | - |
924 * |GR3 |Hidden parameter | caller save |
925 * |GR4-GR7 | - | caller save |
926 * |GR8-GR13 |Argument register | caller save |
927 * |GR14-GR15 | - | caller save |
928 * |GR16-GR31 | - | callee save |
929 * |GR32-GR47 | - | caller save |
930 * |GR48-GR63 | - | callee save |
931 * |FR0-FR15 | - | caller save |
932 * |FR16-FR31 | - | callee save |
933 * |FR32-FR47 | - | caller save |
934 * |FR48-FR63 | - | callee save |
935 * +---------------+-----------------------+-----------------------+
939 * SP-> |-----------------------------------|
941 * |-----------------------------------|
942 * | Register save area |
943 * |-----------------------------------|
944 * | Local variable save area |
945 * FP-> |-----------------------------------|
947 * |-----------------------------------|
948 * | Hidden parameter save area |
949 * |-----------------------------------|
950 * | Return address(LR) storage area |
951 * |-----------------------------------|
952 * | Padding for alignment |
953 * |-----------------------------------|
954 * | Register argument area |
955 * OLD SP-> |-----------------------------------|
957 * |-----------------------------------|
960 * Argument area/Parameter area:
962 * When a function is called, this area is used for argument transfer. When
963 * the argument is set up by the caller function, this area is referred to as
964 * the argument area. When the argument is referenced by the callee function,
965 * this area is referred to as the parameter area. The area is allocated when
966 * all arguments cannot be placed on the argument register at the time of
969 * Register save area:
971 * This is a register save area that must be guaranteed for the caller
972 * function. This area is not secured when the register save operation is not
975 * Local variable save area:
977 * This is the area for local variables and temporary variables.
981 * This area stores the FP value of the caller function.
983 * Hidden parameter save area:
985 * This area stores the start address of the return value storage
986 * area for a struct/union return function.
987 * When a struct/union is used as the return value, the caller
988 * function stores the return value storage area start address in
989 * register GR3 and passes it to the caller function.
990 * The callee function interprets the address stored in the GR3
991 * as the return value storage area start address.
992 * When register GR3 needs to be saved into memory, the callee
993 * function saves it in the hidden parameter save area. This
994 * area is not secured when the save operation is not needed.
996 * Return address(LR) storage area:
998 * This area saves the LR. The LR stores the address of a return to the caller
999 * function for the purpose of function calling.
1001 * Argument register area:
1003 * This area saves the argument register. This area is not secured when the
1004 * save operation is not needed.
1008 * Arguments, the count of which equals the count of argument registers (6
1009 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1010 * function. When a struct/union return function is called, the return value
1011 * area address is stored in register GR3. Arguments not placed in the
1012 * argument registers will be stored in the stack argument area for transfer
1013 * purposes. When an 8-byte type argument is to be delivered using registers,
1014 * it is divided into two and placed in two registers for transfer. When
1015 * argument registers must be saved to memory, the callee function secures an
1016 * argument register save area in the stack. In this case, a continuous
1017 * argument register save area must be established in the parameter area. The
1018 * argument register save area must be allocated as needed to cover the size of
1019 * the argument register to be saved. If the function has a variable count of
1020 * arguments, it saves all argument registers in the argument register save
1023 * Argument Extension Format:
1025 * When an argument is to be stored in the stack, its type is converted to an
1026 * extended type in accordance with the individual argument type. The argument
1027 * is freed by the caller function after the return from the callee function is
1030 * +-----------------------+---------------+------------------------+
1031 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1032 * +-----------------------+---------------+------------------------+
1034 * |signed char |int | 4 |
1035 * |unsigned char |int | 4 |
1036 * |[signed] short int |int | 4 |
1037 * |unsigned short int |int | 4 |
1038 * |[signed] int |No extension | 4 |
1039 * |unsigned int |No extension | 4 |
1040 * |[signed] long int |No extension | 4 |
1041 * |unsigned long int |No extension | 4 |
1042 * |[signed] long long int |No extension | 8 |
1043 * |unsigned long long int |No extension | 8 |
1044 * |float |double | 8 |
1045 * |double |No extension | 8 |
1046 * |long double |No extension | 8 |
1047 * |pointer |No extension | 4 |
1048 * |struct/union |- | 4 (*1) |
1049 * +-----------------------+---------------+------------------------+
1051 * When a struct/union is to be delivered as an argument, the caller copies it
1052 * to the local variable area and delivers the address of that area.
1056 * +-------------------------------+----------------------+
1057 * |Return Value Type |Return Value Interface|
1058 * +-------------------------------+----------------------+
1060 * |[signed|unsigned] char |GR8 |
1061 * |[signed|unsigned] short int |GR8 |
1062 * |[signed|unsigned] int |GR8 |
1063 * |[signed|unsigned] long int |GR8 |
1065 * |[signed|unsigned] long long int|GR8 & GR9 |
1067 * |double |GR8 & GR9 |
1068 * |long double |GR8 & GR9 |
1069 * |struct/union |(*1) |
1070 * +-------------------------------+----------------------+
1072 * When a struct/union is used as the return value, the caller function stores
1073 * the start address of the return value storage area into GR3 and then passes
1074 * it to the callee function. The callee function interprets GR3 as the start
1075 * address of the return value storage area. When this address needs to be
1076 * saved in memory, the callee function secures the hidden parameter save area
1077 * and saves the address in that area.
1081 frv_stack_info (void)
1083 static frv_stack_t info, zero_info;
1084 frv_stack_t *info_ptr = &info;
1085 tree fndecl = current_function_decl;
1093 /* If we've already calculated the values and reload is complete,
1095 if (frv_stack_cache)
1096 return frv_stack_cache;
1098 /* Zero all fields. */
1101 /* Set up the register range information. */
1102 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1103 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1104 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1105 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1107 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1108 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1109 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1110 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1112 info_ptr->regs[STACK_REGS_LR].name = "lr";
1113 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1114 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1115 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1117 info_ptr->regs[STACK_REGS_CC].name = "cc";
1118 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1119 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1120 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1122 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1123 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1124 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1126 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1127 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1128 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1129 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1130 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1132 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1133 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1134 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1135 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1137 info_ptr->regs[STACK_REGS_FP].name = "fp";
1138 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1139 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1140 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1142 /* Determine if this is a stdarg function. If so, allocate space to store
1149 /* Find the last argument, and see if it is __builtin_va_alist. */
1150 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1152 next_arg = TREE_CHAIN (cur_arg);
1153 if (next_arg == (tree)0)
1155 if (DECL_NAME (cur_arg)
1156 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1164 /* Iterate over all of the register ranges. */
1165 for (range = 0; range < STACK_REGS_MAX; range++)
1167 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1168 int first = reg_ptr->first;
1169 int last = reg_ptr->last;
1171 int size_2words = 0;
1174 /* Calculate which registers need to be saved & save area size. */
1178 for (regno = first; regno <= last; regno++)
1180 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1181 || (crtl->calls_eh_return
1182 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1183 || (!TARGET_FDPIC && flag_pic
1184 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1186 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1187 size_1word += UNITS_PER_WORD;
1192 /* Calculate whether we need to create a frame after everything else
1193 has been processed. */
1198 if (df_regs_ever_live_p (LR_REGNO)
1200 /* This is set for __builtin_return_address, etc. */
1201 || cfun->machine->frame_needed
1202 || (TARGET_LINKED_FP && frame_pointer_needed)
1203 || (!TARGET_FDPIC && flag_pic
1204 && crtl->uses_pic_offset_table))
1206 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1207 size_1word += UNITS_PER_WORD;
1211 case STACK_REGS_STDARG:
1214 /* If this is a stdarg function with a non varardic
1215 argument split between registers and the stack,
1216 adjust the saved registers downward. */
1217 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1220 for (regno = first; regno <= last; regno++)
1222 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1223 size_1word += UNITS_PER_WORD;
1226 info_ptr->stdarg_size = size_1word;
1230 case STACK_REGS_STRUCT:
1231 if (cfun->returns_struct)
1233 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1234 size_1word += UNITS_PER_WORD;
1242 /* If this is a field, it only takes one word. */
1243 if (reg_ptr->field_p)
1244 size_1word = UNITS_PER_WORD;
1246 /* Determine which register pairs can be saved together. */
1247 else if (reg_ptr->dword_p && TARGET_DWORD)
1249 for (regno = first; regno < last; regno += 2)
1251 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1253 size_2words += 2 * UNITS_PER_WORD;
1254 size_1word -= 2 * UNITS_PER_WORD;
1255 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1256 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1261 reg_ptr->size_1word = size_1word;
1262 reg_ptr->size_2words = size_2words;
1264 if (! reg_ptr->special_p)
1266 info_ptr->regs_size_1word += size_1word;
1267 info_ptr->regs_size_2words += size_2words;
1272 /* Set up the sizes of each each field in the frame body, making the sizes
1273 of each be divisible by the size of a dword if dword operations might
1274 be used, or the size of a word otherwise. */
1275 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1277 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1278 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1279 + info_ptr->regs_size_1word,
1281 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1283 info_ptr->pretend_size = crtl->args.pretend_args_size;
1285 /* Work out the size of the frame, excluding the header. Both the frame
1286 body and register parameter area will be dword-aligned. */
1287 info_ptr->total_size
1288 = (ADDR_ALIGN (info_ptr->parameter_size
1289 + info_ptr->regs_size
1290 + info_ptr->vars_size,
1292 + ADDR_ALIGN (info_ptr->pretend_size
1293 + info_ptr->stdarg_size,
1294 2 * UNITS_PER_WORD));
1296 /* See if we need to create a frame at all, if so add header area. */
1297 if (info_ptr->total_size > 0
1298 || frame_pointer_needed
1299 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1300 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1302 offset = info_ptr->parameter_size;
1303 info_ptr->header_size = 4 * UNITS_PER_WORD;
1304 info_ptr->total_size += 4 * UNITS_PER_WORD;
1306 /* Calculate the offsets to save normal register pairs. */
1307 for (range = 0; range < STACK_REGS_MAX; range++)
1309 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1310 if (! reg_ptr->special_p)
1312 int first = reg_ptr->first;
1313 int last = reg_ptr->last;
1316 for (regno = first; regno <= last; regno++)
1317 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1318 && regno != FRAME_POINTER_REGNUM
1319 && (regno < FIRST_ARG_REGNUM
1320 || regno > LAST_ARG_REGNUM))
1322 info_ptr->reg_offset[regno] = offset;
1323 offset += 2 * UNITS_PER_WORD;
1328 /* Calculate the offsets to save normal single registers. */
1329 for (range = 0; range < STACK_REGS_MAX; range++)
1331 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1332 if (! reg_ptr->special_p)
1334 int first = reg_ptr->first;
1335 int last = reg_ptr->last;
1338 for (regno = first; regno <= last; regno++)
1339 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1340 && regno != FRAME_POINTER_REGNUM
1341 && (regno < FIRST_ARG_REGNUM
1342 || regno > LAST_ARG_REGNUM))
1344 info_ptr->reg_offset[regno] = offset;
1345 offset += UNITS_PER_WORD;
1350 /* Calculate the offset to save the local variables at. */
1351 offset = ADDR_ALIGN (offset, alignment);
1352 if (info_ptr->vars_size)
1354 info_ptr->vars_offset = offset;
1355 offset += info_ptr->vars_size;
1358 /* Align header to a dword-boundary. */
1359 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1361 /* Calculate the offsets in the fixed frame. */
1362 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1363 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1364 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1366 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1367 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1368 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1370 if (cfun->returns_struct)
1372 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1373 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1374 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1377 /* Calculate the offsets to store the arguments passed in registers
1378 for stdarg functions. The register pairs are first and the single
1379 register if any is last. The register save area starts on a
1381 if (info_ptr->stdarg_size)
1383 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1384 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1387 /* Skip the header. */
1388 offset += 4 * UNITS_PER_WORD;
1389 for (regno = first; regno <= last; regno++)
1391 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1393 info_ptr->reg_offset[regno] = offset;
1394 offset += 2 * UNITS_PER_WORD;
1396 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1398 info_ptr->reg_offset[regno] = offset;
1399 offset += UNITS_PER_WORD;
1405 if (reload_completed)
1406 frv_stack_cache = info_ptr;
1412 /* Print the information about the frv stack offsets, etc. when debugging. */
1415 frv_debug_stack (frv_stack_t *info)
1420 info = frv_stack_info ();
1422 fprintf (stderr, "\nStack information for function %s:\n",
1423 ((current_function_decl && DECL_NAME (current_function_decl))
1424 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1427 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1428 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1429 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1430 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1431 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1433 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1434 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1435 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1436 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1438 for (range = 0; range < STACK_REGS_MAX; range++)
1440 frv_stack_regs_t *regs = &(info->regs[range]);
1441 if ((regs->size_1word + regs->size_2words) > 0)
1443 int first = regs->first;
1444 int last = regs->last;
1447 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1448 regs->name, regs->size_1word + regs->size_2words,
1449 regs->size_1word, regs->size_2words);
1451 for (regno = first; regno <= last; regno++)
1453 if (info->save_p[regno] == REG_SAVE_1WORD)
1454 fprintf (stderr, " %s (%d)", reg_names[regno],
1455 info->reg_offset[regno]);
1457 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1458 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1459 reg_names[regno+1], info->reg_offset[regno]);
1462 fputc ('\n', stderr);
1472 /* Used during final to control the packing of insns. The value is
1473 1 if the current instruction should be packed with the next one,
1474 0 if it shouldn't or -1 if packing is disabled altogether. */
1476 static int frv_insn_packing_flag;
1478 /* True if the current function contains a far jump. */
1481 frv_function_contains_far_jump (void)
1483 rtx insn = get_insns ();
1485 && !(GET_CODE (insn) == JUMP_INSN
1486 /* Ignore tablejump patterns. */
1487 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1488 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1489 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1490 insn = NEXT_INSN (insn);
1491 return (insn != NULL);
1494 /* For the FRV, this function makes sure that a function with far jumps
1495 will return correctly. It also does the VLIW packing. */
1498 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1500 /* If no frame was created, check whether the function uses a call
1501 instruction to implement a far jump. If so, save the link in gr3 and
1502 replace all returns to LR with returns to GR3. GR3 is used because it
1503 is call-clobbered, because is not available to the register allocator,
1504 and because all functions that take a hidden argument pointer will have
1506 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1510 /* Just to check that the above comment is true. */
1511 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1513 /* Generate the instruction that saves the link register. */
1514 fprintf (file, "\tmovsg lr,gr3\n");
1516 /* Replace the LR with GR3 in *return_internal patterns. The insn
1517 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1518 simply emit a different assembly directive because bralr and jmpl
1519 execute in different units. */
1520 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1521 if (GET_CODE (insn) == JUMP_INSN)
1523 rtx pattern = PATTERN (insn);
1524 if (GET_CODE (pattern) == PARALLEL
1525 && XVECLEN (pattern, 0) >= 2
1526 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1527 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1529 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1530 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1531 SET_REGNO (address, GPR_FIRST + 3);
1538 /* Allow the garbage collector to free the nops created by frv_reorg. */
1539 memset (frv_nops, 0, sizeof (frv_nops));
1543 /* Return the next available temporary register in a given class. */
1546 frv_alloc_temp_reg (
1547 frv_tmp_reg_t *info, /* which registers are available */
1548 enum reg_class rclass, /* register class desired */
1549 enum machine_mode mode, /* mode to allocate register with */
1550 int mark_as_used, /* register not available after allocation */
1551 int no_abort) /* return NULL instead of aborting */
1553 int regno = info->next_reg[ (int)rclass ];
1554 int orig_regno = regno;
1555 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1560 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1561 && TEST_HARD_REG_BIT (info->regs, regno))
1564 if (++regno >= FIRST_PSEUDO_REGISTER)
1566 if (regno == orig_regno)
1568 gcc_assert (no_abort);
1573 nr = HARD_REGNO_NREGS (regno, mode);
1574 info->next_reg[ (int)rclass ] = regno + nr;
1577 for (i = 0; i < nr; i++)
1578 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1580 return gen_rtx_REG (mode, regno);
1584 /* Return an rtx with the value OFFSET, which will either be a register or a
1585 signed 12-bit integer. It can be used as the second operand in an "add"
1586 instruction, or as the index in a load or store.
1588 The function returns a constant rtx if OFFSET is small enough, otherwise
1589 it loads the constant into register OFFSET_REGNO and returns that. */
1591 frv_frame_offset_rtx (int offset)
1593 rtx offset_rtx = GEN_INT (offset);
1594 if (IN_RANGE_P (offset, -2048, 2047))
1598 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1599 if (IN_RANGE_P (offset, -32768, 32767))
1600 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1603 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1604 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1610 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1611 prologue and epilogue uses such expressions to access the stack. */
1613 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1615 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1617 frv_frame_offset_rtx (offset)));
1620 /* Generate a frame-related expression:
1622 (set REG (mem (plus (sp) (const_int OFFSET)))).
1624 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1625 instructions. Marking the expressions as frame-related is superfluous if
1626 the note contains just a single set. But if the note contains a PARALLEL
1627 or SEQUENCE that has several sets, each set must be individually marked
1628 as frame-related. */
1630 frv_dwarf_store (rtx reg, int offset)
1632 rtx set = gen_rtx_SET (VOIDmode,
1633 gen_rtx_MEM (GET_MODE (reg),
1634 plus_constant (stack_pointer_rtx,
1637 RTX_FRAME_RELATED_P (set) = 1;
1641 /* Emit a frame-related instruction whose pattern is PATTERN. The
1642 instruction is the last in a sequence that cumulatively performs the
1643 operation described by DWARF_PATTERN. The instruction is marked as
1644 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1647 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1649 rtx insn = emit_insn (pattern);
1650 RTX_FRAME_RELATED_P (insn) = 1;
1651 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1656 /* Emit instructions that transfer REG to or from the memory location (sp +
1657 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1658 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1659 function to store registers and only the epilogue uses it to load them.
1661 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1662 The generated instruction will use BASE as its base register. BASE may
1663 simply be the stack pointer, but if several accesses are being made to a
1664 region far away from the stack pointer, it may be more efficient to set
1665 up a temporary instead.
1667 Store instructions will be frame-related and will be annotated with the
1668 overall effect of the store. Load instructions will be followed by a
1669 (use) to prevent later optimizations from zapping them.
1671 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1672 as a temporary in such cases. */
1674 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1676 enum machine_mode mode = GET_MODE (reg);
1677 rtx mem = frv_frame_mem (mode,
1679 stack_offset - accessor->base_offset);
1681 if (accessor->op == FRV_LOAD)
1683 if (SPR_P (REGNO (reg)))
1685 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1686 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1687 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1690 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1695 if (SPR_P (REGNO (reg)))
1697 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1698 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1699 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1700 frv_dwarf_store (reg, stack_offset));
1702 else if (GET_MODE (reg) == DImode)
1704 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1705 with a separate save for each register. */
1706 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1707 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1708 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1709 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1710 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1711 gen_rtx_PARALLEL (VOIDmode,
1712 gen_rtvec (2, set1, set2)));
1715 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1716 frv_dwarf_store (reg, stack_offset));
1720 /* A function that uses frv_frame_access to transfer a group of registers to
1721 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1722 is the stack information generated by frv_stack_info, and REG_SET is the
1723 number of the register set to transfer. */
1725 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1729 frv_stack_regs_t *regs_info;
1732 regs_info = &info->regs[reg_set];
1733 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1734 if (info->save_p[regno])
1735 frv_frame_access (accessor,
1736 info->save_p[regno] == REG_SAVE_2WORDS
1737 ? gen_rtx_REG (DImode, regno)
1738 : gen_rtx_REG (SImode, regno),
1739 info->reg_offset[regno]);
1742 /* Save or restore callee-saved registers that are kept outside the frame
1743 header. The function saves the registers if OP is FRV_STORE and restores
1744 them if OP is FRV_LOAD. INFO is the stack information generated by
1747 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1749 frv_frame_accessor_t accessor;
1752 accessor.base = stack_pointer_rtx;
1753 accessor.base_offset = 0;
1754 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1755 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1756 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1760 /* Called after register allocation to add any instructions needed for the
1761 prologue. Using a prologue insn is favored compared to putting all of the
1762 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1763 it allows the scheduler to intermix instructions with the saves of
1764 the caller saved registers. In some cases, it might be necessary
1765 to emit a barrier instruction as the last insn to prevent such
1768 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1769 so that the debug info generation code can handle them properly. */
1771 frv_expand_prologue (void)
1773 frv_stack_t *info = frv_stack_info ();
1774 rtx sp = stack_pointer_rtx;
1775 rtx fp = frame_pointer_rtx;
1776 frv_frame_accessor_t accessor;
1778 if (TARGET_DEBUG_STACK)
1779 frv_debug_stack (info);
1781 if (info->total_size == 0)
1784 /* We're interested in three areas of the frame here:
1786 A: the register save area
1788 C: the header after B
1790 If the frame pointer isn't used, we'll have to set up A, B and C
1791 using the stack pointer. If the frame pointer is used, we'll access
1795 B: set up using sp or a temporary (see below)
1798 We set up B using the stack pointer if the frame is small enough.
1799 Otherwise, it's more efficient to copy the old stack pointer into a
1800 temporary and use that.
1802 Note that it's important to make sure the prologue and epilogue use the
1803 same registers to access A and C, since doing otherwise will confuse
1804 the aliasing code. */
1806 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1807 isn't used, the same method will serve for C. */
1808 accessor.op = FRV_STORE;
1809 if (frame_pointer_needed && info->total_size > 2048)
1813 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1814 accessor.base_offset = info->total_size;
1815 insn = emit_insn (gen_movsi (accessor.base, sp));
1819 accessor.base = stack_pointer_rtx;
1820 accessor.base_offset = 0;
1823 /* Allocate the stack space. */
1825 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1826 rtx dwarf_offset = GEN_INT (-info->total_size);
1828 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1831 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1834 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1835 and point the new one to that location. */
1836 if (frame_pointer_needed)
1838 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1840 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1841 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1843 rtx asm_src = plus_constant (accessor.base,
1844 fp_offset - accessor.base_offset);
1845 rtx dwarf_src = plus_constant (sp, fp_offset);
1847 /* Store the old frame pointer at (sp + FP_OFFSET). */
1848 frv_frame_access (&accessor, fp, fp_offset);
1850 /* Set up the new frame pointer. */
1851 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1852 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1854 /* Access region C from the frame pointer. */
1856 accessor.base_offset = fp_offset;
1859 /* Set up region C. */
1860 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1861 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1862 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1864 /* Set up region A. */
1865 frv_frame_access_standard_regs (FRV_STORE, info);
1867 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1868 scheduler from moving loads before the stores saving the registers. */
1869 if (info->stdarg_size > 0)
1870 emit_insn (gen_blockage ());
1872 /* Set up pic register/small data register for this function. */
1873 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1874 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1875 gen_rtx_REG (Pmode, LR_REGNO),
1876 gen_rtx_REG (SImode, OFFSET_REGNO)));
1880 /* Under frv, all of the work is done via frv_expand_epilogue, but
1881 this function provides a convenient place to do cleanup. */
1884 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1885 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1887 frv_stack_cache = (frv_stack_t *)0;
1889 /* Zap last used registers for conditional execution. */
1890 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1892 /* Release the bitmap of created insns. */
1893 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1897 /* Called after register allocation to add any instructions needed for the
1898 epilogue. Using an epilogue insn is favored compared to putting all of the
1899 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1900 it allows the scheduler to intermix instructions with the saves of
1901 the caller saved registers. In some cases, it might be necessary
1902 to emit a barrier instruction as the last insn to prevent such
1906 frv_expand_epilogue (bool emit_return)
1908 frv_stack_t *info = frv_stack_info ();
1909 rtx fp = frame_pointer_rtx;
1910 rtx sp = stack_pointer_rtx;
1914 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1916 /* Restore the stack pointer to its original value if alloca or the like
1918 if (! current_function_sp_is_unchanging)
1919 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1921 /* Restore the callee-saved registers that were used in this function. */
1922 frv_frame_access_standard_regs (FRV_LOAD, info);
1924 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1925 no return instruction should be emitted. */
1926 if (info->save_p[LR_REGNO])
1931 /* Use the same method to access the link register's slot as we did in
1932 the prologue. In other words, use the frame pointer if available,
1933 otherwise use the stack pointer.
1935 LR_OFFSET is the offset of the link register's slot from the start
1936 of the frame and MEM is a memory rtx for it. */
1937 lr_offset = info->reg_offset[LR_REGNO];
1938 if (frame_pointer_needed)
1939 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1941 mem = frv_frame_mem (Pmode, sp, lr_offset);
1943 /* Load the old link register into a GPR. */
1944 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1945 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1948 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1950 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1951 the load is preserved. */
1952 if (frame_pointer_needed)
1954 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1958 /* Deallocate the stack frame. */
1959 if (info->total_size != 0)
1961 rtx offset = frv_frame_offset_rtx (info->total_size);
1962 emit_insn (gen_stack_adjust (sp, sp, offset));
1965 /* If this function uses eh_return, add the final stack adjustment now. */
1966 if (crtl->calls_eh_return)
1967 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1970 emit_jump_insn (gen_epilogue_return (return_addr));
1973 rtx lr = return_addr;
1975 if (REGNO (return_addr) != LR_REGNO)
1977 lr = gen_rtx_REG (Pmode, LR_REGNO);
1978 emit_move_insn (lr, return_addr);
1986 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1989 frv_asm_output_mi_thunk (FILE *file,
1990 tree thunk_fndecl ATTRIBUTE_UNUSED,
1991 HOST_WIDE_INT delta,
1992 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1995 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1996 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1997 const char *name_jmp = reg_names[JUMP_REGNO];
1998 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2000 /* Do the add using an addi if possible. */
2001 if (IN_RANGE_P (delta, -2048, 2047))
2002 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2005 const char *const name_add = reg_names[TEMP_REGNO];
2006 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2007 parallel, delta, name_add);
2008 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2010 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2015 const char *name_pic = reg_names[FDPIC_REGNO];
2016 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2020 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2021 assemble_name (file, name_func);
2022 fprintf (file, "),%s\n", name_jmp);
2024 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2025 assemble_name (file, name_func);
2026 fprintf (file, "),%s\n", name_jmp);
2028 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2032 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2033 assemble_name (file, name_func);
2034 fprintf (file, "\t)), %s\n", name_jmp);
2039 fprintf (file, "\tsethi%s #hi(", parallel);
2040 assemble_name (file, name_func);
2041 fprintf (file, "),%s\n", name_jmp);
2043 fprintf (file, "\tsetlo #lo(");
2044 assemble_name (file, name_func);
2045 fprintf (file, "),%s\n", name_jmp);
2049 /* Use JUMP_REGNO as a temporary PIC register. */
2050 const char *name_lr = reg_names[LR_REGNO];
2051 const char *name_gppic = name_jmp;
2052 const char *name_tmp = reg_names[TEMP_REGNO];
2054 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2055 fprintf (file, "\tcall 1f\n");
2056 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2057 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2058 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2059 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2060 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2062 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2063 assemble_name (file, name_func);
2064 fprintf (file, "),%s\n", name_tmp);
2066 fprintf (file, "\tsetlo #gprello(");
2067 assemble_name (file, name_func);
2068 fprintf (file, "),%s\n", name_tmp);
2070 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2073 /* Jump to the function address. */
2074 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2078 /* A C expression which is nonzero if a function must have and use a frame
2079 pointer. This expression is evaluated in the reload pass. If its value is
2080 nonzero the function will have a frame pointer.
2082 The expression can in principle examine the current function and decide
2083 according to the facts, but on most machines the constant 0 or the constant
2084 1 suffices. Use 0 when the machine allows code to be generated with no
2085 frame pointer, and doing so saves some time or space. Use 1 when there is
2086 no possible advantage to avoiding a frame pointer.
2088 In certain cases, the compiler does not know how to produce valid code
2089 without a frame pointer. The compiler recognizes those cases and
2090 automatically gives the function a frame pointer regardless of what
2091 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2093 In a function that does not require a frame pointer, the frame pointer
2094 register can be allocated for ordinary usage, unless you mark it as a fixed
2095 register. See `FIXED_REGISTERS' for more information. */
2097 /* On frv, create a frame whenever we need to create stack. */
2100 frv_frame_pointer_required (void)
2102 /* If we forgoing the usual linkage requirements, we only need
2103 a frame pointer if the stack pointer might change. */
2104 if (!TARGET_LINKED_FP)
2105 return !current_function_sp_is_unchanging;
2107 if (! current_function_is_leaf)
2110 if (get_frame_size () != 0)
2116 if (!current_function_sp_is_unchanging)
2119 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2125 if (cfun->machine->frame_needed)
2132 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2133 initial difference between the specified pair of registers. This macro must
2134 be defined if `ELIMINABLE_REGS' is defined. */
2136 /* See frv_stack_info for more details on the frv stack frame. */
2139 frv_initial_elimination_offset (int from, int to)
2141 frv_stack_t *info = frv_stack_info ();
2144 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2145 ret = info->total_size - info->pretend_size;
2147 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2148 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2150 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2151 ret = (info->total_size
2152 - info->reg_offset[FRAME_POINTER_REGNUM]
2153 - info->pretend_size);
2158 if (TARGET_DEBUG_STACK)
2159 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2160 reg_names [from], reg_names[to], ret);
2166 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2169 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2170 enum machine_mode mode,
2171 tree type ATTRIBUTE_UNUSED,
2175 if (TARGET_DEBUG_ARG)
2177 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2178 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2182 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2185 frv_expand_builtin_saveregs (void)
2187 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2189 if (TARGET_DEBUG_ARG)
2190 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2193 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2197 /* Expand __builtin_va_start to do the va_start macro. */
2200 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2203 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2205 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2206 GEN_INT (UNITS_PER_WORD * num));
2208 if (TARGET_DEBUG_ARG)
2210 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2211 crtl->args.info, num);
2213 debug_rtx (nextarg);
2216 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2217 fold_convert (TREE_TYPE (valist),
2218 make_tree (sizetype, nextarg)));
2219 TREE_SIDE_EFFECTS (t) = 1;
2221 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2225 /* Expand a block move operation, and return 1 if successful. Return 0
2226 if we should let the compiler generate normal code.
2228 operands[0] is the destination
2229 operands[1] is the source
2230 operands[2] is the length
2231 operands[3] is the alignment */
2233 /* Maximum number of loads to do before doing the stores */
2234 #ifndef MAX_MOVE_REG
2235 #define MAX_MOVE_REG 4
2238 /* Maximum number of total loads to do. */
2239 #ifndef TOTAL_MOVE_REG
2240 #define TOTAL_MOVE_REG 8
2244 frv_expand_block_move (rtx operands[])
2246 rtx orig_dest = operands[0];
2247 rtx orig_src = operands[1];
2248 rtx bytes_rtx = operands[2];
2249 rtx align_rtx = operands[3];
2250 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2263 rtx stores[MAX_MOVE_REG];
2265 enum machine_mode mode;
2267 /* If this is not a fixed size move, just call memcpy. */
2271 /* This should be a fixed size alignment. */
2272 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2274 align = INTVAL (align_rtx);
2276 /* Anything to move? */
2277 bytes = INTVAL (bytes_rtx);
2281 /* Don't support real large moves. */
2282 if (bytes > TOTAL_MOVE_REG*align)
2285 /* Move the address into scratch registers. */
2286 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2287 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2289 num_reg = offset = 0;
2290 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2292 /* Calculate the correct offset for src/dest. */
2296 dest_addr = dest_reg;
2300 src_addr = plus_constant (src_reg, offset);
2301 dest_addr = plus_constant (dest_reg, offset);
2304 /* Generate the appropriate load and store, saving the stores
2306 if (bytes >= 4 && align >= 4)
2308 else if (bytes >= 2 && align >= 2)
2313 move_bytes = GET_MODE_SIZE (mode);
2314 tmp_reg = gen_reg_rtx (mode);
2315 src_mem = change_address (orig_src, mode, src_addr);
2316 dest_mem = change_address (orig_dest, mode, dest_addr);
2317 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2318 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2320 if (num_reg >= MAX_MOVE_REG)
2322 for (i = 0; i < num_reg; i++)
2323 emit_insn (stores[i]);
2328 for (i = 0; i < num_reg; i++)
2329 emit_insn (stores[i]);
2335 /* Expand a block clear operation, and return 1 if successful. Return 0
2336 if we should let the compiler generate normal code.
2338 operands[0] is the destination
2339 operands[1] is the length
2340 operands[3] is the alignment */
2343 frv_expand_block_clear (rtx operands[])
2345 rtx orig_dest = operands[0];
2346 rtx bytes_rtx = operands[1];
2347 rtx align_rtx = operands[3];
2348 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2357 enum machine_mode mode;
2359 /* If this is not a fixed size move, just call memcpy. */
2363 /* This should be a fixed size alignment. */
2364 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2366 align = INTVAL (align_rtx);
2368 /* Anything to move? */
2369 bytes = INTVAL (bytes_rtx);
2373 /* Don't support real large clears. */
2374 if (bytes > TOTAL_MOVE_REG*align)
2377 /* Move the address into a scratch register. */
2378 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2380 num_reg = offset = 0;
2381 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2383 /* Calculate the correct offset for src/dest. */
2384 dest_addr = ((offset == 0)
2386 : plus_constant (dest_reg, offset));
2388 /* Generate the appropriate store of gr0. */
2389 if (bytes >= 4 && align >= 4)
2391 else if (bytes >= 2 && align >= 2)
2396 clear_bytes = GET_MODE_SIZE (mode);
2397 dest_mem = change_address (orig_dest, mode, dest_addr);
2398 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2405 /* The following variable is used to output modifiers of assembler
2406 code of the current output insn. */
2408 static rtx *frv_insn_operands;
2410 /* The following function is used to add assembler insn code suffix .p
2411 if it is necessary. */
2414 frv_asm_output_opcode (FILE *f, const char *ptr)
2418 if (frv_insn_packing_flag <= 0)
2421 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2424 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2425 || (*ptr >= 'A' && *ptr <= 'Z')))
2427 int letter = *ptr++;
2430 frv_print_operand (f, frv_insn_operands [c], letter);
2431 while ((c = *ptr) >= '0' && c <= '9')
2443 /* Set up the packing bit for the current output insn. Note that this
2444 function is not called for asm insns. */
2447 frv_final_prescan_insn (rtx insn, rtx *opvec,
2448 int noperands ATTRIBUTE_UNUSED)
2452 if (frv_insn_packing_flag >= 0)
2454 frv_insn_operands = opvec;
2455 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2457 else if (recog_memoized (insn) >= 0
2458 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2459 /* Packing optimizations have been disabled, but INSN can only
2460 be issued in M1. Insert an mnop in M0. */
2461 fprintf (asm_out_file, "\tmnop.p\n");
2467 /* A C expression whose value is RTL representing the address in a stack frame
2468 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2469 an RTL expression for the address of the stack frame itself.
2471 If you don't define this macro, the default is to return the value of
2472 FRAMEADDR--that is, the stack frame address is also the address of the stack
2473 word that points to the previous frame. */
2475 /* The default is correct, but we need to make sure the frame gets created. */
2477 frv_dynamic_chain_address (rtx frame)
2479 cfun->machine->frame_needed = 1;
2484 /* A C expression whose value is RTL representing the value of the return
2485 address for the frame COUNT steps up from the current frame, after the
2486 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2487 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2490 The value of the expression must always be the correct address when COUNT is
2491 zero, but may be `NULL_RTX' if there is not way to determine the return
2492 address of other frames. */
2495 frv_return_addr_rtx (int count, rtx frame)
2499 cfun->machine->frame_needed = 1;
2500 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2503 /* Given a memory reference MEMREF, interpret the referenced memory as
2504 an array of MODE values, and return a reference to the element
2505 specified by INDEX. Assume that any pre-modification implicit in
2506 MEMREF has already happened.
2508 MEMREF must be a legitimate operand for modes larger than SImode.
2509 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2510 this function cannot handle. */
2512 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2514 rtx base = XEXP (memref, 0);
2515 if (GET_CODE (base) == PRE_MODIFY)
2516 base = XEXP (base, 0);
2517 return change_address (memref, mode,
2518 plus_constant (base, index * GET_MODE_SIZE (mode)));
2522 /* Print a memory address as an operand to reference that memory location. */
2524 frv_print_operand_address (FILE * stream, rtx x)
2526 if (GET_CODE (x) == MEM)
2529 switch (GET_CODE (x))
2532 fputs (reg_names [ REGNO (x)], stream);
2536 fprintf (stream, "%ld", (long) INTVAL (x));
2540 assemble_name (stream, XSTR (x, 0));
2545 output_addr_const (stream, x);
2552 fatal_insn ("bad insn to frv_print_operand_address:", x);
2557 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2559 int regno = true_regnum (x);
2561 fputs (reg_names[regno], stream);
2563 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2566 /* Print a memory reference suitable for the ld/st instructions. */
2569 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2571 struct frv_unspec unspec;
2575 switch (GET_CODE (x))
2582 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2584 x1 = XEXP (XEXP (x, 1), 1);
2594 if (GET_CODE (x0) == CONST_INT)
2602 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2611 else if (GET_CODE (x1) != CONST_INT)
2612 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2615 fputs ("@(", stream);
2617 fputs (reg_names[GPR_R0], stream);
2618 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2619 frv_print_operand_memory_reference_reg (stream, x0);
2621 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2623 fputs (",", stream);
2625 fputs (reg_names [GPR_R0], stream);
2629 switch (GET_CODE (x1))
2633 frv_print_operand_memory_reference_reg (stream, x1);
2637 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2641 if (!frv_const_unspec_p (x1, &unspec))
2642 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2643 frv_output_const_unspec (stream, &unspec);
2647 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2651 fputs (")", stream);
2655 /* Return 2 for likely branches and 0 for non-likely branches */
2657 #define FRV_JUMP_LIKELY 2
2658 #define FRV_JUMP_NOT_LIKELY 0
2661 frv_print_operand_jump_hint (rtx insn)
2666 HOST_WIDE_INT prob = -1;
2667 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2669 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2671 /* Assume any non-conditional jump is likely. */
2672 if (! any_condjump_p (insn))
2673 ret = FRV_JUMP_LIKELY;
2677 labelref = condjump_label (insn);
2680 rtx label = XEXP (labelref, 0);
2681 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2686 note = find_reg_note (insn, REG_BR_PROB, 0);
2688 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2692 prob = INTVAL (XEXP (note, 0));
2693 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2695 : FRV_JUMP_NOT_LIKELY);
2707 case UNKNOWN: direction = "unknown jump direction"; break;
2708 case BACKWARD: direction = "jump backward"; break;
2709 case FORWARD: direction = "jump forward"; break;
2713 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2714 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2715 (long)INSN_UID (insn), direction, (long)prob,
2716 (long)REG_BR_PROB_BASE, ret);
2724 /* Return the comparison operator to use for CODE given that the ICC
2728 comparison_string (enum rtx_code code, rtx op0)
2730 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2733 default: output_operand_lossage ("bad condition code");
2734 case EQ: return "eq";
2735 case NE: return "ne";
2736 case LT: return is_nz_p ? "n" : "lt";
2737 case LE: return "le";
2738 case GT: return "gt";
2739 case GE: return is_nz_p ? "p" : "ge";
2740 case LTU: return is_nz_p ? "no" : "c";
2741 case LEU: return is_nz_p ? "eq" : "ls";
2742 case GTU: return is_nz_p ? "ne" : "hi";
2743 case GEU: return is_nz_p ? "ra" : "nc";
2747 /* Print an operand to an assembler instruction.
2749 `%' followed by a letter and a digit says to output an operand in an
2750 alternate fashion. Four letters have standard, built-in meanings described
2751 below. The machine description macro `PRINT_OPERAND' can define additional
2752 letters with nonstandard meanings.
2754 `%cDIGIT' can be used to substitute an operand that is a constant value
2755 without the syntax that normally indicates an immediate operand.
2757 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2760 `%aDIGIT' can be used to substitute an operand as if it were a memory
2761 reference, with the actual operand treated as the address. This may be
2762 useful when outputting a "load address" instruction, because often the
2763 assembler syntax for such an instruction requires you to write the operand
2764 as if it were a memory reference.
2766 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2768 `%=' outputs a number which is unique to each instruction in the entire
2769 compilation. This is useful for making local labels to be referred to more
2770 than once in a single template that generates multiple assembler
2773 `%' followed by a punctuation character specifies a substitution that does
2774 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2775 assembler code. Other nonstandard cases can be defined in the
2776 `PRINT_OPERAND' macro. You must also define which punctuation characters
2777 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2780 frv_print_operand (FILE * file, rtx x, int code)
2782 struct frv_unspec unspec;
2783 HOST_WIDE_INT value;
2786 if (code != 0 && !ISALPHA (code))
2789 else if (GET_CODE (x) == CONST_INT)
2792 else if (GET_CODE (x) == CONST_DOUBLE)
2794 if (GET_MODE (x) == SFmode)
2799 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2800 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2804 else if (GET_MODE (x) == VOIDmode)
2805 value = CONST_DOUBLE_LOW (x);
2808 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2819 fputs (reg_names[GPR_R0], file);
2823 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2827 /* Output small data area base register (gr16). */
2828 fputs (reg_names[SDA_BASE_REG], file);
2832 /* Output pic register (gr17). */
2833 fputs (reg_names[PIC_REGNO], file);
2837 /* Output the temporary integer CCR register. */
2838 fputs (reg_names[ICR_TEMP], file);
2842 /* Output the temporary integer CC register. */
2843 fputs (reg_names[ICC_TEMP], file);
2846 /* case 'a': print an address. */
2849 /* Print appropriate test for integer branch false operation. */
2850 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2851 XEXP (x, 0)), file);
2855 /* Print appropriate test for integer branch true operation. */
2856 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2860 /* Print 1 for a NE and 0 for an EQ to give the final argument
2861 for a conditional instruction. */
2862 if (GET_CODE (x) == NE)
2865 else if (GET_CODE (x) == EQ)
2869 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2873 /* Print appropriate test for floating point branch false operation. */
2874 switch (GET_CODE (x))
2877 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2879 case EQ: fputs ("ne", file); break;
2880 case NE: fputs ("eq", file); break;
2881 case LT: fputs ("uge", file); break;
2882 case LE: fputs ("ug", file); break;
2883 case GT: fputs ("ule", file); break;
2884 case GE: fputs ("ul", file); break;
2889 /* Print appropriate test for floating point branch true operation. */
2890 switch (GET_CODE (x))
2893 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2895 case EQ: fputs ("eq", file); break;
2896 case NE: fputs ("ne", file); break;
2897 case LT: fputs ("lt", file); break;
2898 case LE: fputs ("le", file); break;
2899 case GT: fputs ("gt", file); break;
2900 case GE: fputs ("ge", file); break;
2905 /* Print appropriate GOT function. */
2906 if (GET_CODE (x) != CONST_INT)
2907 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2908 fputs (unspec_got_name (INTVAL (x)), file);
2912 /* Print 'i' if the operand is a constant, or is a memory reference that
2914 if (GET_CODE (x) == MEM)
2915 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2916 ? XEXP (XEXP (x, 0), 1)
2918 else if (GET_CODE (x) == PLUS)
2921 switch (GET_CODE (x))
2935 /* For jump instructions, print 'i' if the operand is a constant or
2936 is an expression that adds a constant. */
2937 if (GET_CODE (x) == CONST_INT)
2942 if (GET_CODE (x) == CONST_INT
2943 || (GET_CODE (x) == PLUS
2944 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2945 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2951 /* Print the lower register of a double word register pair */
2952 if (GET_CODE (x) == REG)
2953 fputs (reg_names[ REGNO (x)+1 ], file);
2955 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2958 /* case 'l': print a LABEL_REF. */
2962 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2963 for the second word of double memory operations. */
2964 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2965 switch (GET_CODE (x))
2968 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
2971 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2979 frv_print_operand_memory_reference (file, x, offset);
2985 /* Print the opcode of a command. */
2986 switch (GET_CODE (x))
2989 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
2991 case PLUS: fputs ("add", file); break;
2992 case MINUS: fputs ("sub", file); break;
2993 case AND: fputs ("and", file); break;
2994 case IOR: fputs ("or", file); break;
2995 case XOR: fputs ("xor", file); break;
2996 case ASHIFT: fputs ("sll", file); break;
2997 case ASHIFTRT: fputs ("sra", file); break;
2998 case LSHIFTRT: fputs ("srl", file); break;
3002 /* case 'n': negate and print a constant int. */
3005 /* Print PIC label using operand as the number. */
3006 if (GET_CODE (x) != CONST_INT)
3007 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3009 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3013 /* Print 'u' if the operand is a update load/store. */
3014 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3019 /* If value is 0, print gr0, otherwise it must be a register. */
3020 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3021 fputs (reg_names[GPR_R0], file);
3023 else if (GET_CODE (x) == REG)
3024 fputs (reg_names [REGNO (x)], file);
3027 fatal_insn ("bad insn in frv_print_operand, z case", x);
3031 /* Print constant in hex. */
3032 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3034 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3041 if (GET_CODE (x) == REG)
3042 fputs (reg_names [REGNO (x)], file);
3044 else if (GET_CODE (x) == CONST_INT
3045 || GET_CODE (x) == CONST_DOUBLE)
3046 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3048 else if (frv_const_unspec_p (x, &unspec))
3049 frv_output_const_unspec (file, &unspec);
3051 else if (GET_CODE (x) == MEM)
3052 frv_print_operand_address (file, XEXP (x, 0));
3054 else if (CONSTANT_ADDRESS_P (x))
3055 frv_print_operand_address (file, x);
3058 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3063 fatal_insn ("frv_print_operand: unknown code", x);
3071 /* A C statement (sans semicolon) for initializing the variable CUM for the
3072 state at the beginning of the argument list. The variable has type
3073 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3074 of the function which will receive the args, or 0 if the args are to a
3075 compiler support library function. The value of INDIRECT is nonzero when
3076 processing an indirect call, for example a call through a function pointer.
3077 The value of INDIRECT is zero for a call to an explicitly named function, a
3078 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3079 arguments for the function being compiled.
3081 When processing a call to a compiler support library function, LIBNAME
3082 identifies which one. It is a `symbol_ref' rtx which contains the name of
3083 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3084 being processed. Thus, each time this macro is called, either LIBNAME or
3085 FNTYPE is nonzero, but never both of them at once. */
3088 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3094 *cum = FIRST_ARG_REGNUM;
3096 if (TARGET_DEBUG_ARG)
3098 fprintf (stderr, "\ninit_cumulative_args:");
3099 if (!fndecl && fntype)
3100 fputs (" indirect", stderr);
3103 fputs (" incoming", stderr);
3107 tree ret_type = TREE_TYPE (fntype);
3108 fprintf (stderr, " return=%s,",
3109 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3112 if (libname && GET_CODE (libname) == SYMBOL_REF)
3113 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3115 if (cfun->returns_struct)
3116 fprintf (stderr, " return-struct");
3118 putc ('\n', stderr);
3123 /* Return true if we should pass an argument on the stack rather than
3127 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3129 if (mode == BLKmode)
3133 return AGGREGATE_TYPE_P (type);
3136 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3137 argument with the specified mode and type. If it is not defined,
3138 `PARM_BOUNDARY' is used for all arguments. */
3141 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3142 tree type ATTRIBUTE_UNUSED)
3144 return BITS_PER_WORD;
3148 frv_function_arg (CUMULATIVE_ARGS *cum,
3149 enum machine_mode mode,
3150 tree type ATTRIBUTE_UNUSED,
3152 int incoming ATTRIBUTE_UNUSED)
3154 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3159 /* Return a marker for use in the call instruction. */
3160 if (xmode == VOIDmode)
3166 else if (arg_num <= LAST_ARG_REGNUM)
3168 ret = gen_rtx_REG (xmode, arg_num);
3169 debstr = reg_names[arg_num];
3178 if (TARGET_DEBUG_ARG)
3180 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3181 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3187 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3188 advance past an argument in the argument list. The values MODE, TYPE and
3189 NAMED describe that argument. Once this is done, the variable CUM is
3190 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3192 This macro need not do anything if the argument in question was passed on
3193 the stack. The compiler knows how to track the amount of stack space used
3194 for arguments without any special help. */
3197 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3198 enum machine_mode mode,
3199 tree type ATTRIBUTE_UNUSED,
3202 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3203 int bytes = GET_MODE_SIZE (xmode);
3204 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3207 *cum = arg_num + words;
3209 if (TARGET_DEBUG_ARG)
3211 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3212 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3216 /* A C expression for the number of words, at the beginning of an argument,
3217 must be put in registers. The value must be zero for arguments that are
3218 passed entirely in registers or that are entirely pushed on the stack.
3220 On some machines, certain arguments must be passed partially in registers
3221 and partially in memory. On these machines, typically the first N words of
3222 arguments are passed in registers, and the rest on the stack. If a
3223 multi-word argument (a `double' or a structure) crosses that boundary, its
3224 first few words must be passed in registers and the rest must be pushed.
3225 This macro tells the compiler when this occurs, and how many of the words
3226 should go in registers.
3228 `FUNCTION_ARG' for these arguments should return the first register to be
3229 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3230 the called function. */
3233 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3234 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3236 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3237 int bytes = GET_MODE_SIZE (xmode);
3238 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3242 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3243 ? LAST_ARG_REGNUM - arg_num + 1
3245 ret *= UNITS_PER_WORD;
3247 if (TARGET_DEBUG_ARG && ret)
3248 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3254 /* Return true if a register is ok to use as a base or index register. */
3256 static FRV_INLINE int
3257 frv_regno_ok_for_base_p (int regno, int strict_p)
3263 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3265 if (regno == ARG_POINTER_REGNUM)
3268 return (regno >= FIRST_PSEUDO_REGISTER);
3272 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3273 RTX) is a legitimate memory address on the target machine for a memory
3274 operand of mode MODE.
3276 It usually pays to define several simpler macros to serve as subroutines for
3277 this one. Otherwise it may be too complicated to understand.
3279 This macro must exist in two variants: a strict variant and a non-strict
3280 one. The strict variant is used in the reload pass. It must be defined so
3281 that any pseudo-register that has not been allocated a hard register is
3282 considered a memory reference. In contexts where some kind of register is
3283 required, a pseudo-register with no hard register must be rejected.
3285 The non-strict variant is used in other passes. It must be defined to
3286 accept all pseudo-registers in every context where some kind of register is
3289 Compiler source files that want to use the strict variant of this macro
3290 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3291 conditional to define the strict variant in that case and the non-strict
3294 Subroutines to check for acceptable registers for various purposes (one for
3295 base registers, one for index registers, and so on) are typically among the
3296 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3297 subroutine macros need have two variants; the higher levels of macros may be
3298 the same whether strict or not.
3300 Normally, constant addresses which are the sum of a `symbol_ref' and an
3301 integer are stored inside a `const' RTX to mark them as constant.
3302 Therefore, there is no need to recognize such sums specifically as
3303 legitimate addresses. Normally you would simply recognize any `const' as
3306 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3307 are not marked with `const'. It assumes that a naked `plus' indicates
3308 indexing. If so, then you *must* reject such naked constant sums as
3309 illegitimate addresses, so that none of them will be given to
3310 `PRINT_OPERAND_ADDRESS'.
3312 On some machines, whether a symbolic address is legitimate depends on the
3313 section that the address refers to. On these machines, define the macro
3314 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3315 then check for it here. When you see a `const', you will have to look
3316 inside it to find the `symbol_ref' in order to determine the section.
3318 The best way to modify the name string is by adding text to the beginning,
3319 with suitable punctuation to prevent any ambiguity. Allocate the new name
3320 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3321 remove and decode the added text and output the name accordingly, and define
3322 `(* targetm.strip_name_encoding)' to access the original name string.
3324 You can check the information stored here into the `symbol_ref' in the
3325 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3326 `PRINT_OPERAND_ADDRESS'. */
3329 frv_legitimate_address_p (enum machine_mode mode,
3333 int allow_double_reg_p)
3337 HOST_WIDE_INT value;
3340 if (FRV_SYMBOL_REF_TLS_P (x))
3343 switch (GET_CODE (x))
3350 if (GET_CODE (x) != REG)
3356 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3362 if (GET_CODE (x0) != REG
3363 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3364 || GET_CODE (x1) != PLUS
3365 || ! rtx_equal_p (x0, XEXP (x1, 0))
3366 || GET_CODE (XEXP (x1, 1)) != REG
3367 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3374 /* 12-bit immediate */
3379 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3381 /* If we can't use load/store double operations, make sure we can
3382 address the second word. */
3383 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3384 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3393 if (GET_CODE (x0) == SUBREG)
3394 x0 = SUBREG_REG (x0);
3396 if (GET_CODE (x0) != REG)
3399 regno0 = REGNO (x0);
3400 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3403 switch (GET_CODE (x1))
3409 x1 = SUBREG_REG (x1);
3410 if (GET_CODE (x1) != REG)
3416 /* Do not allow reg+reg addressing for modes > 1 word if we
3417 can't depend on having move double instructions. */
3418 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3421 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3425 /* 12-bit immediate */
3430 value = INTVAL (x1);
3431 ret = IN_RANGE_P (value, -2048, 2047);
3433 /* If we can't use load/store double operations, make sure we can
3434 address the second word. */
3435 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3436 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3441 if (!condexec_p && got12_operand (x1, VOIDmode))
3449 if (TARGET_DEBUG_ADDR)
3451 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3452 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3453 (condexec_p) ? ", inside conditional code" : "");
3460 /* Given an ADDR, generate code to inline the PLT. */
3462 gen_inlined_tls_plt (rtx addr)
3465 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3468 dest = gen_reg_rtx (DImode);
3475 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3476 calll #gettlsoff(ADDR)@(gr8, gr0)
3478 emit_insn (gen_tls_lddi (dest, addr, picreg));
3485 sethi.p #gottlsdeschi(ADDR), gr8
3486 setlo #gottlsdesclo(ADDR), gr8
3487 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3488 calll #gettlsoff(ADDR)@(gr8, gr0)
3490 rtx reguse = gen_reg_rtx (Pmode);
3491 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3492 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3495 retval = gen_reg_rtx (Pmode);
3496 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3500 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3501 the destination address. */
3503 gen_tlsmoff (rtx addr, rtx reg)
3505 rtx dest = gen_reg_rtx (Pmode);
3509 /* sethi.p #tlsmoffhi(x), grA
3510 setlo #tlsmofflo(x), grA
3512 dest = gen_reg_rtx (Pmode);
3513 emit_insn (gen_tlsoff_hilo (dest, addr,
3514 GEN_INT (R_FRV_TLSMOFFHI)));
3515 dest = gen_rtx_PLUS (Pmode, dest, reg);
3519 /* addi grB, #tlsmoff12(x), grC
3521 ld/st @(grB, #tlsmoff12(x)), grC
3523 dest = gen_reg_rtx (Pmode);
3524 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3525 GEN_INT (R_FRV_TLSMOFF12)));
3530 /* Generate code for a TLS address. */
3532 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3534 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3535 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3539 case TLS_MODEL_INITIAL_EXEC:
3543 ldi @(gr15, #gottlsoff12(x)), gr5
3545 dest = gen_reg_rtx (Pmode);
3546 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3547 dest = gen_rtx_PLUS (Pmode, tp, dest);
3551 /* -fPIC or anything else.
3553 sethi.p #gottlsoffhi(x), gr14
3554 setlo #gottlsofflo(x), gr14
3555 ld #tlsoff(x)@(gr15, gr14), gr9
3557 rtx tmp = gen_reg_rtx (Pmode);
3558 dest = gen_reg_rtx (Pmode);
3559 emit_insn (gen_tlsoff_hilo (tmp, addr,
3560 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3562 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3563 dest = gen_rtx_PLUS (Pmode, tp, dest);
3566 case TLS_MODEL_LOCAL_DYNAMIC:
3570 if (TARGET_INLINE_PLT)
3571 retval = gen_inlined_tls_plt (GEN_INT (0));
3574 /* call #gettlsoff(0) */
3575 retval = gen_reg_rtx (Pmode);
3576 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3579 reg = gen_reg_rtx (Pmode);
3580 emit_insn (gen_rtx_SET (VOIDmode, reg,
3581 gen_rtx_PLUS (Pmode,
3584 dest = gen_tlsmoff (addr, reg);
3587 dest = gen_reg_rtx (Pmode);
3588 emit_insn (gen_tlsoff_hilo (dest, addr,
3589 GEN_INT (R_FRV_TLSMOFFHI)));
3590 dest = gen_rtx_PLUS (Pmode, dest, reg);
3594 case TLS_MODEL_LOCAL_EXEC:
3595 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3597 case TLS_MODEL_GLOBAL_DYNAMIC:
3601 if (TARGET_INLINE_PLT)
3602 retval = gen_inlined_tls_plt (addr);
3605 /* call #gettlsoff(x) */
3606 retval = gen_reg_rtx (Pmode);
3607 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3609 dest = gen_rtx_PLUS (Pmode, retval, tp);
3620 frv_legitimize_address (rtx x,
3621 rtx oldx ATTRIBUTE_UNUSED,
3622 enum machine_mode mode ATTRIBUTE_UNUSED)
3624 if (GET_CODE (x) == SYMBOL_REF)
3626 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3628 return frv_legitimize_tls_address (x, model);
3634 /* Test whether a local function descriptor is canonical, i.e.,
3635 whether we can use FUNCDESC_GOTOFF to compute the address of the
3639 frv_local_funcdesc_p (rtx fnx)
3642 enum symbol_visibility vis;
3645 if (! SYMBOL_REF_LOCAL_P (fnx))
3648 fn = SYMBOL_REF_DECL (fnx);
3653 vis = DECL_VISIBILITY (fn);
3655 if (vis == VISIBILITY_PROTECTED)
3656 /* Private function descriptors for protected functions are not
3657 canonical. Temporarily change the visibility to global. */
3658 vis = VISIBILITY_DEFAULT;
3659 else if (flag_shlib)
3660 /* If we're already compiling for a shared library (that, unlike
3661 executables, can't assume that the existence of a definition
3662 implies local binding), we can skip the re-testing. */
3665 ret = default_binds_local_p_1 (fn, flag_pic);
3667 DECL_VISIBILITY (fn) = vis;
3672 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3676 frv_gen_GPsym2reg (rtx dest, rtx src)
3678 tree gp = get_identifier ("_gp");
3679 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3681 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3685 unspec_got_name (int i)
3689 case R_FRV_GOT12: return "got12";
3690 case R_FRV_GOTHI: return "gothi";
3691 case R_FRV_GOTLO: return "gotlo";
3692 case R_FRV_FUNCDESC: return "funcdesc";
3693 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3694 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3695 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3696 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3697 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3698 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3699 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3700 case R_FRV_GOTOFF12: return "gotoff12";
3701 case R_FRV_GOTOFFHI: return "gotoffhi";
3702 case R_FRV_GOTOFFLO: return "gotofflo";
3703 case R_FRV_GPREL12: return "gprel12";
3704 case R_FRV_GPRELHI: return "gprelhi";
3705 case R_FRV_GPRELLO: return "gprello";
3706 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3707 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3708 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3709 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3710 case R_FRV_TLSMOFF12: return "tlsmoff12";
3711 case R_FRV_TLSDESCHI: return "tlsdeschi";
3712 case R_FRV_TLSDESCLO: return "tlsdesclo";
3713 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3714 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3715 default: gcc_unreachable ();
3719 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3720 is added inside the relocation operator. */
3723 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3725 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3726 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3727 fputs (")", stream);
3730 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3731 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3732 otherwise return ORIG_X. */
3735 frv_find_base_term (rtx x)
3737 struct frv_unspec unspec;
3739 if (frv_const_unspec_p (x, &unspec)
3740 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3741 return plus_constant (unspec.symbol, unspec.offset);
3746 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3747 the operand is used by a predicated instruction. */
3750 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3752 return ((GET_MODE (op) == mode || mode == VOIDmode)
3753 && GET_CODE (op) == MEM
3754 && frv_legitimate_address_p (mode, XEXP (op, 0),
3755 reload_completed, condexec_p, FALSE));
3759 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3761 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3762 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3768 rvrtx = operands[0];
3772 addr = XEXP (operands[0], 0);
3774 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3775 any calls that would involve a PLT, but can't tell, since we
3776 don't know whether an extern function is going to be provided by
3777 a separate translation unit or imported from a separate module.
3778 When compiling for shared libraries, if the function has default
3779 visibility, we assume it's overridable, so we inline the PLT, but
3780 for executables, we don't really have a way to make a good
3781 decision: a function is as likely to be imported from a shared
3782 library as it is to be defined in the executable itself. We
3783 assume executables will get global functions defined locally,
3784 whereas shared libraries will have them potentially overridden,
3785 so we only inline PLTs when compiling for shared libraries.
3787 In order to mark a function as local to a shared library, any
3788 non-default visibility attribute suffices. Unfortunately,
3789 there's no simple way to tag a function declaration as ``in a
3790 different module'', which we could then use to trigger PLT
3791 inlining on executables. There's -minline-plt, but it affects
3792 all external functions, so one would have to also mark function
3793 declarations available in the same module with non-default
3794 visibility, which is advantageous in itself. */
3795 if (GET_CODE (addr) == SYMBOL_REF
3796 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3800 dest = gen_reg_rtx (SImode);
3802 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3803 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3805 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3806 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3808 crtl->uses_pic_offset_table = TRUE;
3811 else if (GET_CODE (addr) == SYMBOL_REF)
3813 /* These are always either local, or handled through a local
3816 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3817 operands[2], picreg, lr);
3819 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3823 else if (! ldd_address_operand (addr, Pmode))
3824 addr = force_reg (Pmode, addr);
3826 picreg = gen_reg_rtx (DImode);
3827 emit_insn (gen_movdi_ldd (picreg, addr));
3829 if (sibcall && ret_value)
3830 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3832 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3834 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3836 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3840 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3841 process these separately from any offsets, such that we add any
3842 offsets to the function descriptor (the actual pointer), not to the
3843 function address. */
3846 frv_function_symbol_referenced_p (rtx x)
3852 if (GET_CODE (x) == SYMBOL_REF)
3853 return SYMBOL_REF_FUNCTION_P (x);
3855 length = GET_RTX_LENGTH (GET_CODE (x));
3856 format = GET_RTX_FORMAT (GET_CODE (x));
3858 for (j = 0; j < length; ++j)
3863 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3869 if (XVEC (x, j) != 0)
3872 for (k = 0; k < XVECLEN (x, j); ++k)
3873 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3879 /* Nothing to do. */
3887 /* Return true if the memory operand is one that can be conditionally
3891 condexec_memory_operand (rtx op, enum machine_mode mode)
3893 enum machine_mode op_mode = GET_MODE (op);
3896 if (mode != VOIDmode && op_mode != mode)
3911 if (GET_CODE (op) != MEM)
3914 addr = XEXP (op, 0);
3915 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
3918 /* Return true if the bare return instruction can be used outside of the
3919 epilog code. For frv, we only do it if there was no stack allocation. */
3922 direct_return_p (void)
3926 if (!reload_completed)
3929 info = frv_stack_info ();
3930 return (info->total_size == 0);
3935 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3937 if (GET_CODE (src) == SYMBOL_REF)
3939 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3941 src = frv_legitimize_tls_address (src, model);
3947 if (frv_emit_movsi (dest, src))
3956 if (!reload_in_progress
3957 && !reload_completed
3958 && !register_operand (dest, mode)
3959 && !reg_or_0_operand (src, mode))
3960 src = copy_to_mode_reg (mode, src);
3967 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3970 /* Emit code to handle a MOVSI, adding in the small data register or pic
3971 register if needed to load up addresses. Return TRUE if the appropriate
3972 instructions are emitted. */
3975 frv_emit_movsi (rtx dest, rtx src)
3977 int base_regno = -1;
3980 struct frv_unspec old_unspec;
3982 if (!reload_in_progress
3983 && !reload_completed
3984 && !register_operand (dest, SImode)
3985 && (!reg_or_0_operand (src, SImode)
3986 /* Virtual registers will almost always be replaced by an
3987 add instruction, so expose this to CSE by copying to
3988 an intermediate register. */
3989 || (GET_CODE (src) == REG
3990 && IN_RANGE_P (REGNO (src),
3991 FIRST_VIRTUAL_REGISTER,
3992 LAST_VIRTUAL_REGISTER))))
3994 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
3998 /* Explicitly add in the PIC or small data register if needed. */
3999 switch (GET_CODE (src))
4008 /* Using GPREL12, we use a single GOT entry for all symbols
4009 in read-only sections, but trade sequences such as:
4011 sethi #gothi(label), gr#
4012 setlo #gotlo(label), gr#
4017 ld @(gr15,#got12(_gp)), gr#
4018 sethi #gprelhi(label), gr##
4019 setlo #gprello(label), gr##
4022 We may often be able to share gr# for multiple
4023 computations of GPREL addresses, and we may often fold
4024 the final add into the pair of registers of a load or
4025 store instruction, so it's often profitable. Even when
4026 optimizing for size, we're trading a GOT entry for an
4027 additional instruction, which trades GOT space
4028 (read-write) for code size (read-only, shareable), as
4029 long as the symbol is not used in more than two different
4032 With -fpie/-fpic, we'd be trading a single load for a
4033 sequence of 4 instructions, because the offset of the
4034 label can't be assumed to be addressable with 12 bits, so
4035 we don't do this. */
4036 if (TARGET_GPREL_RO)
4037 unspec = R_FRV_GPREL12;
4039 unspec = R_FRV_GOT12;
4042 base_regno = PIC_REGNO;
4047 if (frv_const_unspec_p (src, &old_unspec))
4050 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4053 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4054 emit_move_insn (dest, src);
4059 sym = XEXP (sym, 0);
4060 if (GET_CODE (sym) == PLUS
4061 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4062 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4063 sym = XEXP (sym, 0);
4064 if (GET_CODE (sym) == SYMBOL_REF)
4066 else if (GET_CODE (sym) == LABEL_REF)
4069 goto handle_whatever;
4077 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4081 src = frv_legitimize_tls_address (src, model);
4082 emit_move_insn (dest, src);
4086 if (SYMBOL_REF_FUNCTION_P (sym))
4088 if (frv_local_funcdesc_p (sym))
4089 unspec = R_FRV_FUNCDESC_GOTOFF12;
4091 unspec = R_FRV_FUNCDESC_GOT12;
4095 if (CONSTANT_POOL_ADDRESS_P (sym))
4096 switch (GET_CODE (get_pool_constant (sym)))
4103 unspec = R_FRV_GOTOFF12;
4108 if (TARGET_GPREL_RO)
4109 unspec = R_FRV_GPREL12;
4111 unspec = R_FRV_GOT12;
4114 else if (SYMBOL_REF_LOCAL_P (sym)
4115 && !SYMBOL_REF_EXTERNAL_P (sym)
4116 && SYMBOL_REF_DECL (sym)
4117 && (!DECL_P (SYMBOL_REF_DECL (sym))
4118 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4120 tree decl = SYMBOL_REF_DECL (sym);
4121 tree init = TREE_CODE (decl) == VAR_DECL
4122 ? DECL_INITIAL (decl)
4123 : TREE_CODE (decl) == CONSTRUCTOR
4126 bool named_section, readonly;
4128 if (init && init != error_mark_node)
4129 reloc = compute_reloc_for_constant (init);
4131 named_section = TREE_CODE (decl) == VAR_DECL
4132 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4133 readonly = decl_readonly_section (decl, reloc);
4136 unspec = R_FRV_GOT12;
4138 unspec = R_FRV_GOTOFF12;
4139 else if (readonly && TARGET_GPREL_RO)
4140 unspec = R_FRV_GPREL12;
4142 unspec = R_FRV_GOT12;
4145 unspec = R_FRV_GOT12;
4149 else if (SYMBOL_REF_SMALL_P (sym))
4150 base_regno = SDA_BASE_REG;
4153 base_regno = PIC_REGNO;
4158 if (base_regno >= 0)
4160 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4161 emit_insn (gen_symGOTOFF2reg (dest, src,
4162 gen_rtx_REG (Pmode, base_regno),
4163 GEN_INT (R_FRV_GPREL12)));
4165 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4166 gen_rtx_REG (Pmode, base_regno),
4167 GEN_INT (R_FRV_GPREL12)));
4168 if (base_regno == PIC_REGNO)
4169 crtl->uses_pic_offset_table = TRUE;
4177 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4178 new uses of it once reload has begun. */
4179 gcc_assert (!reload_in_progress && !reload_completed);
4183 case R_FRV_GOTOFF12:
4184 if (!frv_small_data_reloc_p (sym, unspec))
4185 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4188 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4191 if (!frv_small_data_reloc_p (sym, unspec))
4192 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4195 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4197 case R_FRV_FUNCDESC_GOTOFF12:
4199 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4202 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4206 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4209 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4213 crtl->uses_pic_offset_table = TRUE;
4222 /* Return a string to output a single word move. */
4225 output_move_single (rtx operands[], rtx insn)
4227 rtx dest = operands[0];
4228 rtx src = operands[1];
4230 if (GET_CODE (dest) == REG)
4232 int dest_regno = REGNO (dest);
4233 enum machine_mode mode = GET_MODE (dest);
4235 if (GPR_P (dest_regno))
4237 if (GET_CODE (src) == REG)
4239 /* gpr <- some sort of register */
4240 int src_regno = REGNO (src);
4242 if (GPR_P (src_regno))
4243 return "mov %1, %0";
4245 else if (FPR_P (src_regno))
4246 return "movfg %1, %0";
4248 else if (SPR_P (src_regno))
4249 return "movsg %1, %0";
4252 else if (GET_CODE (src) == MEM)
4261 return "ldsb%I1%U1 %M1,%0";
4264 return "ldsh%I1%U1 %M1,%0";
4268 return "ld%I1%U1 %M1, %0";
4272 else if (GET_CODE (src) == CONST_INT
4273 || GET_CODE (src) == CONST_DOUBLE)
4275 /* gpr <- integer/floating constant */
4276 HOST_WIDE_INT value;
4278 if (GET_CODE (src) == CONST_INT)
4279 value = INTVAL (src);
4281 else if (mode == SFmode)
4286 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4287 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4292 value = CONST_DOUBLE_LOW (src);
4294 if (IN_RANGE_P (value, -32768, 32767))
4295 return "setlos %1, %0";
4300 else if (GET_CODE (src) == SYMBOL_REF
4301 || GET_CODE (src) == LABEL_REF
4302 || GET_CODE (src) == CONST)
4308 else if (FPR_P (dest_regno))
4310 if (GET_CODE (src) == REG)
4312 /* fpr <- some sort of register */
4313 int src_regno = REGNO (src);
4315 if (GPR_P (src_regno))
4316 return "movgf %1, %0";
4318 else if (FPR_P (src_regno))
4320 if (TARGET_HARD_FLOAT)
4321 return "fmovs %1, %0";
4323 return "mor %1, %1, %0";
4327 else if (GET_CODE (src) == MEM)
4336 return "ldbf%I1%U1 %M1,%0";
4339 return "ldhf%I1%U1 %M1,%0";
4343 return "ldf%I1%U1 %M1, %0";
4347 else if (ZERO_P (src))
4348 return "movgf %., %0";
4351 else if (SPR_P (dest_regno))
4353 if (GET_CODE (src) == REG)
4355 /* spr <- some sort of register */
4356 int src_regno = REGNO (src);
4358 if (GPR_P (src_regno))
4359 return "movgs %1, %0";
4361 else if (ZERO_P (src))
4362 return "movgs %., %0";
4366 else if (GET_CODE (dest) == MEM)
4368 if (GET_CODE (src) == REG)
4370 int src_regno = REGNO (src);
4371 enum machine_mode mode = GET_MODE (dest);
4373 if (GPR_P (src_regno))
4381 return "stb%I0%U0 %1, %M0";
4384 return "sth%I0%U0 %1, %M0";
4388 return "st%I0%U0 %1, %M0";
4392 else if (FPR_P (src_regno))
4400 return "stbf%I0%U0 %1, %M0";
4403 return "sthf%I0%U0 %1, %M0";
4407 return "stf%I0%U0 %1, %M0";
4412 else if (ZERO_P (src))
4414 switch (GET_MODE (dest))
4420 return "stb%I0%U0 %., %M0";
4423 return "sth%I0%U0 %., %M0";
4427 return "st%I0%U0 %., %M0";
4432 fatal_insn ("bad output_move_single operand", insn);
4437 /* Return a string to output a double word move. */
4440 output_move_double (rtx operands[], rtx insn)
4442 rtx dest = operands[0];
4443 rtx src = operands[1];
4444 enum machine_mode mode = GET_MODE (dest);
4446 if (GET_CODE (dest) == REG)
4448 int dest_regno = REGNO (dest);
4450 if (GPR_P (dest_regno))
4452 if (GET_CODE (src) == REG)
4454 /* gpr <- some sort of register */
4455 int src_regno = REGNO (src);
4457 if (GPR_P (src_regno))
4460 else if (FPR_P (src_regno))
4462 if (((dest_regno - GPR_FIRST) & 1) == 0
4463 && ((src_regno - FPR_FIRST) & 1) == 0)
4464 return "movfgd %1, %0";
4470 else if (GET_CODE (src) == MEM)
4473 if (dbl_memory_one_insn_operand (src, mode))
4474 return "ldd%I1%U1 %M1, %0";
4479 else if (GET_CODE (src) == CONST_INT
4480 || GET_CODE (src) == CONST_DOUBLE)
4484 else if (FPR_P (dest_regno))
4486 if (GET_CODE (src) == REG)
4488 /* fpr <- some sort of register */
4489 int src_regno = REGNO (src);
4491 if (GPR_P (src_regno))
4493 if (((dest_regno - FPR_FIRST) & 1) == 0
4494 && ((src_regno - GPR_FIRST) & 1) == 0)
4495 return "movgfd %1, %0";
4500 else if (FPR_P (src_regno))
4503 && ((dest_regno - FPR_FIRST) & 1) == 0
4504 && ((src_regno - FPR_FIRST) & 1) == 0)
4505 return "fmovd %1, %0";
4511 else if (GET_CODE (src) == MEM)
4514 if (dbl_memory_one_insn_operand (src, mode))
4515 return "lddf%I1%U1 %M1, %0";
4520 else if (ZERO_P (src))
4525 else if (GET_CODE (dest) == MEM)
4527 if (GET_CODE (src) == REG)
4529 int src_regno = REGNO (src);
4531 if (GPR_P (src_regno))
4533 if (((src_regno - GPR_FIRST) & 1) == 0
4534 && dbl_memory_one_insn_operand (dest, mode))
4535 return "std%I0%U0 %1, %M0";
4540 if (FPR_P (src_regno))
4542 if (((src_regno - FPR_FIRST) & 1) == 0
4543 && dbl_memory_one_insn_operand (dest, mode))
4544 return "stdf%I0%U0 %1, %M0";
4550 else if (ZERO_P (src))
4552 if (dbl_memory_one_insn_operand (dest, mode))
4553 return "std%I0%U0 %., %M0";
4559 fatal_insn ("bad output_move_double operand", insn);
4564 /* Return a string to output a single word conditional move.
4565 Operand0 -- EQ/NE of ccr register and 0
4566 Operand1 -- CCR register
4567 Operand2 -- destination
4568 Operand3 -- source */
4571 output_condmove_single (rtx operands[], rtx insn)
4573 rtx dest = operands[2];
4574 rtx src = operands[3];
4576 if (GET_CODE (dest) == REG)
4578 int dest_regno = REGNO (dest);
4579 enum machine_mode mode = GET_MODE (dest);
4581 if (GPR_P (dest_regno))
4583 if (GET_CODE (src) == REG)
4585 /* gpr <- some sort of register */
4586 int src_regno = REGNO (src);
4588 if (GPR_P (src_regno))
4589 return "cmov %z3, %2, %1, %e0";
4591 else if (FPR_P (src_regno))
4592 return "cmovfg %3, %2, %1, %e0";
4595 else if (GET_CODE (src) == MEM)
4604 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4607 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4611 return "cld%I3%U3 %M3, %2, %1, %e0";
4615 else if (ZERO_P (src))
4616 return "cmov %., %2, %1, %e0";
4619 else if (FPR_P (dest_regno))
4621 if (GET_CODE (src) == REG)
4623 /* fpr <- some sort of register */
4624 int src_regno = REGNO (src);
4626 if (GPR_P (src_regno))
4627 return "cmovgf %3, %2, %1, %e0";
4629 else if (FPR_P (src_regno))
4631 if (TARGET_HARD_FLOAT)
4632 return "cfmovs %3,%2,%1,%e0";
4634 return "cmor %3, %3, %2, %1, %e0";
4638 else if (GET_CODE (src) == MEM)
4641 if (mode == SImode || mode == SFmode)
4642 return "cldf%I3%U3 %M3, %2, %1, %e0";
4645 else if (ZERO_P (src))
4646 return "cmovgf %., %2, %1, %e0";
4650 else if (GET_CODE (dest) == MEM)
4652 if (GET_CODE (src) == REG)
4654 int src_regno = REGNO (src);
4655 enum machine_mode mode = GET_MODE (dest);
4657 if (GPR_P (src_regno))
4665 return "cstb%I2%U2 %3, %M2, %1, %e0";
4668 return "csth%I2%U2 %3, %M2, %1, %e0";
4672 return "cst%I2%U2 %3, %M2, %1, %e0";
4676 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4677 return "cstf%I2%U2 %3, %M2, %1, %e0";
4680 else if (ZERO_P (src))
4682 enum machine_mode mode = GET_MODE (dest);
4689 return "cstb%I2%U2 %., %M2, %1, %e0";
4692 return "csth%I2%U2 %., %M2, %1, %e0";
4696 return "cst%I2%U2 %., %M2, %1, %e0";
4701 fatal_insn ("bad output_condmove_single operand", insn);
4706 /* Emit the appropriate code to do a comparison, returning the register the
4707 comparison was done it. */
4710 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4712 enum machine_mode cc_mode;
4715 /* Floating point doesn't have comparison against a constant. */
4716 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4717 op1 = force_reg (GET_MODE (op0), op1);
4719 /* Possibly disable using anything but a fixed register in order to work
4720 around cse moving comparisons past function calls. */
4721 cc_mode = SELECT_CC_MODE (test, op0, op1);
4722 cc_reg = ((TARGET_ALLOC_CC)
4723 ? gen_reg_rtx (cc_mode)
4724 : gen_rtx_REG (cc_mode,
4725 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4727 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4728 gen_rtx_COMPARE (cc_mode, op0, op1)));
4734 /* Emit code for a conditional branch. The comparison operands were previously
4735 stored in frv_compare_op0 and frv_compare_op1.
4737 XXX: I originally wanted to add a clobber of a CCR register to use in
4738 conditional execution, but that confuses the rest of the compiler. */
4741 frv_emit_cond_branch (enum rtx_code test, rtx label)
4746 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4747 enum machine_mode cc_mode = GET_MODE (cc_reg);
4749 /* Branches generate:
4751 (if_then_else (<test>, <cc_reg>, (const_int 0))
4752 (label_ref <branch_label>)
4754 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
4755 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4756 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4757 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4762 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
4763 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
4766 frv_emit_scc (enum rtx_code test, rtx target)
4772 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4774 /* SCC instructions generate:
4775 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4776 (clobber (<ccr_reg>))]) */
4777 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4778 set = gen_rtx_SET (VOIDmode, target, test_rtx);
4780 cr_reg = ((TARGET_ALLOC_CC)
4781 ? gen_reg_rtx (CC_CCRmode)
4782 : gen_rtx_REG (CC_CCRmode,
4783 ((GET_MODE (cc_reg) == CC_FPmode)
4787 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4788 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4793 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4794 the separate insns. */
4797 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4803 /* Set the appropriate CCR bit. */
4804 emit_insn (gen_rtx_SET (VOIDmode,
4806 gen_rtx_fmt_ee (GET_CODE (test),
4811 /* Move the value into the destination. */
4812 emit_move_insn (dest, GEN_INT (value));
4814 /* Move 0 into the destination if the test failed */
4815 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4816 gen_rtx_EQ (GET_MODE (cr_reg),
4819 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4821 /* Finish up, return sequence. */
4828 /* Emit the code for a conditional move, return TRUE if we could do the
4832 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4839 enum rtx_code test = GET_CODE (test_rtx);
4840 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4841 enum machine_mode cc_mode = GET_MODE (cc_reg);
4843 /* Conditional move instructions generate:
4844 (parallel [(set <target>
4845 (if_then_else (<test> <cc_reg> (const_int 0))
4848 (clobber (<ccr_reg>))]) */
4850 /* Handle various cases of conditional move involving two constants. */
4851 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4853 HOST_WIDE_INT value1 = INTVAL (src1);
4854 HOST_WIDE_INT value2 = INTVAL (src2);
4856 /* Having 0 as one of the constants can be done by loading the other
4857 constant, and optionally moving in gr0. */
4858 if (value1 == 0 || value2 == 0)
4861 /* If the first value is within an addi range and also the difference
4862 between the two fits in an addi's range, load up the difference, then
4863 conditionally move in 0, and then unconditionally add the first
4865 else if (IN_RANGE_P (value1, -2048, 2047)
4866 && IN_RANGE_P (value2 - value1, -2048, 2047))
4869 /* If neither condition holds, just force the constant into a
4873 src1 = force_reg (GET_MODE (dest), src1);
4874 src2 = force_reg (GET_MODE (dest), src2);
4878 /* If one value is a register, insure the other value is either 0 or a
4882 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4883 src1 = force_reg (GET_MODE (dest), src1);
4885 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4886 src2 = force_reg (GET_MODE (dest), src2);
4889 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4890 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4892 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4894 cr_reg = ((TARGET_ALLOC_CC)
4895 ? gen_reg_rtx (CC_CCRmode)
4896 : gen_rtx_REG (CC_CCRmode,
4897 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4899 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4900 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4905 /* Split a conditional move into constituent parts, returning a SEQUENCE
4906 containing all of the insns. */
4909 frv_split_cond_move (rtx operands[])
4911 rtx dest = operands[0];
4912 rtx test = operands[1];
4913 rtx cc_reg = operands[2];
4914 rtx src1 = operands[3];
4915 rtx src2 = operands[4];
4916 rtx cr_reg = operands[5];
4918 enum machine_mode cr_mode = GET_MODE (cr_reg);
4922 /* Set the appropriate CCR bit. */
4923 emit_insn (gen_rtx_SET (VOIDmode,
4925 gen_rtx_fmt_ee (GET_CODE (test),
4930 /* Handle various cases of conditional move involving two constants. */
4931 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4933 HOST_WIDE_INT value1 = INTVAL (src1);
4934 HOST_WIDE_INT value2 = INTVAL (src2);
4936 /* Having 0 as one of the constants can be done by loading the other
4937 constant, and optionally moving in gr0. */
4940 emit_move_insn (dest, src2);
4941 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4942 gen_rtx_NE (cr_mode, cr_reg,
4944 gen_rtx_SET (VOIDmode, dest, src1)));
4947 else if (value2 == 0)
4949 emit_move_insn (dest, src1);
4950 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4951 gen_rtx_EQ (cr_mode, cr_reg,
4953 gen_rtx_SET (VOIDmode, dest, src2)));
4956 /* If the first value is within an addi range and also the difference
4957 between the two fits in an addi's range, load up the difference, then
4958 conditionally move in 0, and then unconditionally add the first
4960 else if (IN_RANGE_P (value1, -2048, 2047)
4961 && IN_RANGE_P (value2 - value1, -2048, 2047))
4963 rtx dest_si = ((GET_MODE (dest) == SImode)
4965 : gen_rtx_SUBREG (SImode, dest, 0));
4967 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4968 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4969 gen_rtx_NE (cr_mode, cr_reg,
4971 gen_rtx_SET (VOIDmode, dest_si,
4973 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4981 /* Emit the conditional move for the test being true if needed. */
4982 if (! rtx_equal_p (dest, src1))
4983 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4984 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4985 gen_rtx_SET (VOIDmode, dest, src1)));
4987 /* Emit the conditional move for the test being false if needed. */
4988 if (! rtx_equal_p (dest, src2))
4989 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4990 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4991 gen_rtx_SET (VOIDmode, dest, src2)));
4994 /* Finish up, return sequence. */
5001 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5002 memory location that is not known to be dword-aligned. */
5004 frv_split_double_load (rtx dest, rtx source)
5006 int regno = REGNO (dest);
5007 rtx dest1 = gen_highpart (SImode, dest);
5008 rtx dest2 = gen_lowpart (SImode, dest);
5009 rtx address = XEXP (source, 0);
5011 /* If the address is pre-modified, load the lower-numbered register
5012 first, then load the other register using an integer offset from
5013 the modified base register. This order should always be safe,
5014 since the pre-modification cannot affect the same registers as the
5017 The situation for other loads is more complicated. Loading one
5018 of the registers could affect the value of ADDRESS, so we must
5019 be careful which order we do them in. */
5020 if (GET_CODE (address) == PRE_MODIFY
5021 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5023 /* It is safe to load the lower-numbered register first. */
5024 emit_move_insn (dest1, change_address (source, SImode, NULL));
5025 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5029 /* ADDRESS is not pre-modified and the address depends on the
5030 lower-numbered register. Load the higher-numbered register
5032 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5033 emit_move_insn (dest1, change_address (source, SImode, NULL));
5037 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5038 and SOURCE is either a double register or the constant zero. */
5040 frv_split_double_store (rtx dest, rtx source)
5042 rtx dest1 = change_address (dest, SImode, NULL);
5043 rtx dest2 = frv_index_memory (dest, SImode, 1);
5044 if (ZERO_P (source))
5046 emit_move_insn (dest1, CONST0_RTX (SImode));
5047 emit_move_insn (dest2, CONST0_RTX (SImode));
5051 emit_move_insn (dest1, gen_highpart (SImode, source));
5052 emit_move_insn (dest2, gen_lowpart (SImode, source));
5057 /* Split a min/max operation returning a SEQUENCE containing all of the
5061 frv_split_minmax (rtx operands[])
5063 rtx dest = operands[0];
5064 rtx minmax = operands[1];
5065 rtx src1 = operands[2];
5066 rtx src2 = operands[3];
5067 rtx cc_reg = operands[4];
5068 rtx cr_reg = operands[5];
5070 enum rtx_code test_code;
5071 enum machine_mode cr_mode = GET_MODE (cr_reg);
5075 /* Figure out which test to use. */
5076 switch (GET_CODE (minmax))
5081 case SMIN: test_code = LT; break;
5082 case SMAX: test_code = GT; break;
5083 case UMIN: test_code = LTU; break;
5084 case UMAX: test_code = GTU; break;
5087 /* Issue the compare instruction. */
5088 emit_insn (gen_rtx_SET (VOIDmode,
5090 gen_rtx_COMPARE (GET_MODE (cc_reg),
5093 /* Set the appropriate CCR bit. */
5094 emit_insn (gen_rtx_SET (VOIDmode,
5096 gen_rtx_fmt_ee (test_code,
5101 /* If are taking the min/max of a nonzero constant, load that first, and
5102 then do a conditional move of the other value. */
5103 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5105 gcc_assert (!rtx_equal_p (dest, src1));
5107 emit_move_insn (dest, src2);
5108 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5109 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5110 gen_rtx_SET (VOIDmode, dest, src1)));
5113 /* Otherwise, do each half of the move. */
5116 /* Emit the conditional move for the test being true if needed. */
5117 if (! rtx_equal_p (dest, src1))
5118 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5119 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5120 gen_rtx_SET (VOIDmode, dest, src1)));
5122 /* Emit the conditional move for the test being false if needed. */
5123 if (! rtx_equal_p (dest, src2))
5124 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5125 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5126 gen_rtx_SET (VOIDmode, dest, src2)));
5129 /* Finish up, return sequence. */
5136 /* Split an integer abs operation returning a SEQUENCE containing all of the
5140 frv_split_abs (rtx operands[])
5142 rtx dest = operands[0];
5143 rtx src = operands[1];
5144 rtx cc_reg = operands[2];
5145 rtx cr_reg = operands[3];
5150 /* Issue the compare < 0 instruction. */
5151 emit_insn (gen_rtx_SET (VOIDmode,
5153 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5155 /* Set the appropriate CCR bit. */
5156 emit_insn (gen_rtx_SET (VOIDmode,
5158 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5160 /* Emit the conditional negate if the value is negative. */
5161 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5162 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5163 gen_negsi2 (dest, src)));
5165 /* Emit the conditional move for the test being false if needed. */
5166 if (! rtx_equal_p (dest, src))
5167 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5168 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5169 gen_rtx_SET (VOIDmode, dest, src)));
5171 /* Finish up, return sequence. */
5178 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5179 register used in an insn. */
5182 frv_clear_registers_used (rtx *ptr, void *data)
5184 if (GET_CODE (*ptr) == REG)
5186 int regno = REGNO (*ptr);
5187 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5189 if (regno < FIRST_PSEUDO_REGISTER)
5191 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5193 while (regno < reg_max)
5195 CLEAR_HARD_REG_BIT (*p_regs, regno);
5205 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5207 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5208 initialize the static storage. */
5210 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5212 frv_ifcvt.added_insns_list = NULL_RTX;
5213 frv_ifcvt.cur_scratch_regs = 0;
5214 frv_ifcvt.num_nested_cond_exec = 0;
5215 frv_ifcvt.cr_reg = NULL_RTX;
5216 frv_ifcvt.nested_cc_reg = NULL_RTX;
5217 frv_ifcvt.extra_int_cr = NULL_RTX;
5218 frv_ifcvt.extra_fp_cr = NULL_RTX;
5219 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5223 /* Internal function to add a potential insn to the list of insns to be inserted
5224 if the conditional execution conversion is successful. */
5227 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5229 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5231 link->jump = before_p; /* Mark to add this before or after insn. */
5232 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5233 frv_ifcvt.added_insns_list);
5235 if (TARGET_DEBUG_COND_EXEC)
5238 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5239 (before_p) ? "before" : "after",
5240 (int)INSN_UID (insn));
5242 debug_rtx (pattern);
5247 /* A C expression to modify the code described by the conditional if
5248 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5249 FALSE_EXPR for converting if-then and if-then-else code to conditional
5250 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5251 tests cannot be converted. */
5254 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5256 basic_block test_bb = ce_info->test_bb; /* test basic block */
5257 basic_block then_bb = ce_info->then_bb; /* THEN */
5258 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5259 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5260 rtx true_expr = *p_true;
5264 enum machine_mode mode = GET_MODE (true_expr);
5268 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5270 rtx sub_cond_exec_reg;
5272 enum rtx_code code_true;
5273 enum rtx_code code_false;
5274 enum reg_class cc_class;
5275 enum reg_class cr_class;
5278 reg_set_iterator rsi;
5280 /* Make sure we are only dealing with hard registers. Also honor the
5281 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5283 if (!reload_completed || !TARGET_COND_EXEC
5284 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5287 /* Figure out which registers we can allocate for our own purposes. Only
5288 consider registers that are not preserved across function calls and are
5289 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5290 if we did not need to use them in reloading other registers. */
5291 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5292 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5293 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5294 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5295 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5297 /* If this is a nested IF, we need to discover whether the CC registers that
5298 are set/used inside of the block are used anywhere else. If not, we can
5299 change them to be the CC register that is paired with the CR register that
5300 controls the outermost IF block. */
5301 if (ce_info->pass > 1)
5303 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5304 for (j = CC_FIRST; j <= CC_LAST; j++)
5305 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5307 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5311 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5315 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5318 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5322 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5323 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5325 frv_ifcvt.added_insns_list = NULL_RTX;
5326 frv_ifcvt.cur_scratch_regs = 0;
5328 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5329 * sizeof (basic_block));
5335 /* Remove anything live at the beginning of the join block from being
5336 available for allocation. */
5337 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5339 if (regno < FIRST_PSEUDO_REGISTER)
5340 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5344 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5346 if (ce_info->num_multiple_test_blocks)
5348 basic_block multiple_test_bb = ce_info->last_test_bb;
5350 while (multiple_test_bb != test_bb)
5352 bb[num_bb++] = multiple_test_bb;
5353 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5357 /* Add in the THEN and ELSE blocks to be scanned. */
5358 bb[num_bb++] = then_bb;
5360 bb[num_bb++] = else_bb;
5362 sub_cond_exec_reg = NULL_RTX;
5363 frv_ifcvt.num_nested_cond_exec = 0;
5365 /* Scan all of the blocks for registers that must not be allocated. */
5366 for (j = 0; j < num_bb; j++)
5368 rtx last_insn = BB_END (bb[j]);
5369 rtx insn = BB_HEAD (bb[j]);
5373 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5374 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5376 (int) INSN_UID (BB_HEAD (bb[j])),
5377 (int) INSN_UID (BB_END (bb[j])));
5379 /* Anything live at the beginning of the block is obviously unavailable
5381 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5383 if (regno < FIRST_PSEUDO_REGISTER)
5384 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5387 /* Loop through the insns in the block. */
5390 /* Mark any new registers that are created as being unavailable for
5391 allocation. Also see if the CC register used in nested IFs can be
5397 int skip_nested_if = FALSE;
5399 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5400 (void *)&tmp_reg->regs);
5402 pattern = PATTERN (insn);
5403 if (GET_CODE (pattern) == COND_EXEC)
5405 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5407 if (reg != sub_cond_exec_reg)
5409 sub_cond_exec_reg = reg;
5410 frv_ifcvt.num_nested_cond_exec++;
5414 set = single_set_pattern (pattern);
5417 rtx dest = SET_DEST (set);
5418 rtx src = SET_SRC (set);
5420 if (GET_CODE (dest) == REG)
5422 int regno = REGNO (dest);
5423 enum rtx_code src_code = GET_CODE (src);
5425 if (CC_P (regno) && src_code == COMPARE)
5426 skip_nested_if = TRUE;
5428 else if (CR_P (regno)
5429 && (src_code == IF_THEN_ELSE
5430 || COMPARISON_P (src)))
5431 skip_nested_if = TRUE;
5435 if (! skip_nested_if)
5436 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5437 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5440 if (insn == last_insn)
5443 insn = NEXT_INSN (insn);
5447 /* If this is a nested if, rewrite the CC registers that are available to
5448 include the ones that can be rewritten, to increase the chance of being
5449 able to allocate a paired CC/CR register combination. */
5450 if (ce_info->pass > 1)
5452 for (j = CC_FIRST; j <= CC_LAST; j++)
5453 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5454 SET_HARD_REG_BIT (tmp_reg->regs, j);
5456 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5462 fprintf (dump_file, "Available GPRs: ");
5464 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5465 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5467 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5468 if (++num_gprs > GPR_TEMP_NUM+2)
5472 fprintf (dump_file, "%s\nAvailable CRs: ",
5473 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5475 for (j = CR_FIRST; j <= CR_LAST; j++)
5476 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5477 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5479 fputs ("\n", dump_file);
5481 if (ce_info->pass > 1)
5483 fprintf (dump_file, "Modifiable CCs: ");
5484 for (j = CC_FIRST; j <= CC_LAST; j++)
5485 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5486 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5488 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5489 frv_ifcvt.num_nested_cond_exec);
5493 /* Allocate the appropriate temporary condition code register. Try to
5494 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5495 that conditional cmp's can be done. */
5496 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5498 cr_class = ICR_REGS;
5499 cc_class = ICC_REGS;
5500 cc_first = ICC_FIRST;
5503 else if (mode == CC_FPmode)
5505 cr_class = FCR_REGS;
5506 cc_class = FCC_REGS;
5507 cc_first = FCC_FIRST;
5512 cc_first = cc_last = 0;
5513 cr_class = cc_class = NO_REGS;
5516 cc = XEXP (true_expr, 0);
5517 nested_cc = cr = NULL_RTX;
5518 if (cc_class != NO_REGS)
5520 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5521 so we can execute a csubcc/caddcc/cfcmps instruction. */
5524 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5526 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5528 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5529 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5531 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5532 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5535 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5536 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5546 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5553 "Will use %s for conditional execution, %s for nested comparisons\n",
5554 reg_names[ REGNO (cr)],
5555 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5557 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5558 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5559 bit being true. We don't do this for floating point, because of NaNs. */
5560 code = GET_CODE (true_expr);
5561 if (GET_MODE (cc) != CC_FPmode)
5563 code = reverse_condition (code);
5573 check_insn = gen_rtx_SET (VOIDmode, cr,
5574 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5576 /* Record the check insn to be inserted later. */
5577 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5579 /* Update the tests. */
5580 frv_ifcvt.cr_reg = cr;
5581 frv_ifcvt.nested_cc_reg = nested_cc;
5582 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5583 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5586 /* Fail, don't do this conditional execution. */
5589 *p_false = NULL_RTX;
5591 fprintf (dump_file, "Disabling this conditional execution.\n");
5597 /* A C expression to modify the code described by the conditional if
5598 information CE_INFO, for the basic block BB, possibly updating the tests in
5599 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5600 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5601 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5603 /* p_true and p_false are given expressions of the form:
5605 (and (eq:CC_CCR (reg:CC_CCR)
5611 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5616 rtx old_true = XEXP (*p_true, 0);
5617 rtx old_false = XEXP (*p_false, 0);
5618 rtx true_expr = XEXP (*p_true, 1);
5619 rtx false_expr = XEXP (*p_false, 1);
5622 rtx cr = XEXP (old_true, 0);
5624 rtx new_cr = NULL_RTX;
5625 rtx *p_new_cr = (rtx *)0;
5629 enum reg_class cr_class;
5630 enum machine_mode mode = GET_MODE (true_expr);
5631 rtx (*logical_func)(rtx, rtx, rtx);
5633 if (TARGET_DEBUG_COND_EXEC)
5636 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5637 ce_info->and_and_p ? "&&" : "||");
5639 debug_rtx (*p_true);
5641 fputs ("\nfalse insn:\n", stderr);
5642 debug_rtx (*p_false);
5645 if (!TARGET_MULTI_CE)
5648 if (GET_CODE (cr) != REG)
5651 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5653 cr_class = ICR_REGS;
5654 p_new_cr = &frv_ifcvt.extra_int_cr;
5656 else if (mode == CC_FPmode)
5658 cr_class = FCR_REGS;
5659 p_new_cr = &frv_ifcvt.extra_fp_cr;
5664 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5665 more &&/|| tests. */
5669 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5670 CC_CCRmode, TRUE, TRUE);
5675 if (ce_info->and_and_p)
5677 old_test = old_false;
5678 test_expr = true_expr;
5679 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5680 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5681 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5685 old_test = old_false;
5686 test_expr = false_expr;
5687 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5688 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5689 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5692 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5693 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5695 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5697 /* Now add the conditional check insn. */
5698 cc = XEXP (test_expr, 0);
5699 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5700 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5702 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5704 /* Add the new check insn to the list of check insns that need to be
5706 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5708 if (TARGET_DEBUG_COND_EXEC)
5710 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5713 debug_rtx (*p_true);
5715 fputs ("\nfalse insn:\n", stderr);
5716 debug_rtx (*p_false);
5722 *p_true = *p_false = NULL_RTX;
5724 /* If we allocated a CR register, release it. */
5727 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5728 *p_new_cr = NULL_RTX;
5731 if (TARGET_DEBUG_COND_EXEC)
5732 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5738 /* Return a register which will be loaded with a value if an IF block is
5739 converted to conditional execution. This is used to rewrite instructions
5740 that use constants to ones that just use registers. */
5743 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5745 int num_alloc = frv_ifcvt.cur_scratch_regs;
5749 /* We know gr0 == 0, so replace any errant uses. */
5750 if (value == const0_rtx)
5751 return gen_rtx_REG (SImode, GPR_FIRST);
5753 /* First search all registers currently loaded to see if we have an
5754 applicable constant. */
5755 if (CONSTANT_P (value)
5756 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5758 for (i = 0; i < num_alloc; i++)
5760 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5761 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5765 /* Have we exhausted the number of registers available? */
5766 if (num_alloc >= GPR_TEMP_NUM)
5769 fprintf (dump_file, "Too many temporary registers allocated\n");
5774 /* Allocate the new register. */
5775 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5779 fputs ("Could not find a scratch register\n", dump_file);
5784 frv_ifcvt.cur_scratch_regs++;
5785 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5789 if (GET_CODE (value) == CONST_INT)
5790 fprintf (dump_file, "Register %s will hold %ld\n",
5791 reg_names[ REGNO (reg)], (long)INTVAL (value));
5793 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5794 fprintf (dump_file, "Register %s will hold LR\n",
5795 reg_names[ REGNO (reg)]);
5798 fprintf (dump_file, "Register %s will hold a saved value\n",
5799 reg_names[ REGNO (reg)]);
5806 /* Update a MEM used in conditional code that might contain an offset to put
5807 the offset into a scratch register, so that the conditional load/store
5808 operations can be used. This function returns the original pointer if the
5809 MEM is valid to use in conditional code, NULL if we can't load up the offset
5810 into a temporary register, or the new MEM if we were successful. */
5813 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5815 rtx addr = XEXP (mem, 0);
5817 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
5819 if (GET_CODE (addr) == PLUS)
5821 rtx addr_op0 = XEXP (addr, 0);
5822 rtx addr_op1 = XEXP (addr, 1);
5824 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5826 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5830 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5837 else if (CONSTANT_P (addr))
5838 addr = frv_ifcvt_load_value (addr, insn);
5843 if (addr == NULL_RTX)
5846 else if (XEXP (mem, 0) != addr)
5847 return change_address (mem, mode, addr);
5854 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5855 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5858 single_set_pattern (rtx pattern)
5863 if (GET_CODE (pattern) == COND_EXEC)
5864 pattern = COND_EXEC_CODE (pattern);
5866 if (GET_CODE (pattern) == SET)
5869 else if (GET_CODE (pattern) == PARALLEL)
5871 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5873 rtx sub = XVECEXP (pattern, 0, i);
5875 switch (GET_CODE (sub))
5899 /* A C expression to modify the code described by the conditional if
5900 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5901 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5902 insn cannot be converted to be executed conditionally. */
5905 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5909 rtx orig_ce_pattern = pattern;
5915 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5917 test = COND_EXEC_TEST (pattern);
5918 if (GET_CODE (test) == AND)
5920 rtx cr = frv_ifcvt.cr_reg;
5923 op0 = XEXP (test, 0);
5924 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5927 op1 = XEXP (test, 1);
5928 test_reg = XEXP (op1, 0);
5929 if (GET_CODE (test_reg) != REG)
5932 /* Is this the first nested if block in this sequence? If so, generate
5933 an andcr or andncr. */
5934 if (! frv_ifcvt.last_nested_if_cr)
5938 frv_ifcvt.last_nested_if_cr = test_reg;
5939 if (GET_CODE (op0) == NE)
5940 and_op = gen_andcr (test_reg, cr, test_reg);
5942 and_op = gen_andncr (test_reg, cr, test_reg);
5944 frv_ifcvt_add_insn (and_op, insn, TRUE);
5947 /* If this isn't the first statement in the nested if sequence, see if we
5948 are dealing with the same register. */
5949 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5952 COND_EXEC_TEST (pattern) = test = op1;
5955 /* If this isn't a nested if, reset state variables. */
5958 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5961 set = single_set_pattern (pattern);
5964 rtx dest = SET_DEST (set);
5965 rtx src = SET_SRC (set);
5966 enum machine_mode mode = GET_MODE (dest);
5968 /* Check for normal binary operators. */
5969 if (mode == SImode && ARITHMETIC_P (src))
5971 op0 = XEXP (src, 0);
5972 op1 = XEXP (src, 1);
5974 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5976 op1 = frv_ifcvt_load_value (op1, insn);
5978 COND_EXEC_CODE (pattern)
5979 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
5987 /* For multiply by a constant, we need to handle the sign extending
5988 correctly. Add a USE of the value after the multiply to prevent flow
5989 from cratering because only one register out of the two were used. */
5990 else if (mode == DImode && GET_CODE (src) == MULT)
5992 op0 = XEXP (src, 0);
5993 op1 = XEXP (src, 1);
5994 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
5996 op1 = frv_ifcvt_load_value (op1, insn);
5999 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6000 COND_EXEC_CODE (pattern)
6001 = gen_rtx_SET (VOIDmode, dest,
6002 gen_rtx_MULT (DImode, op0, op1));
6008 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6011 /* If we are just loading a constant created for a nested conditional
6012 execution statement, just load the constant without any conditional
6013 execution, since we know that the constant will not interfere with any
6015 else if (frv_ifcvt.scratch_insns_bitmap
6016 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6018 && REG_P (SET_DEST (set))
6019 /* We must not unconditionally set a scratch reg chosen
6020 for a nested if-converted block if its incoming
6021 value from the TEST block (or the result of the THEN
6022 branch) could/should propagate to the JOIN block.
6023 It suffices to test whether the register is live at
6024 the JOIN point: if it's live there, we can infer
6025 that we set it in the former JOIN block of the
6026 nested if-converted block (otherwise it wouldn't
6027 have been available as a scratch register), and it
6028 is either propagated through or set in the other
6029 conditional block. It's probably not worth trying
6030 to catch the latter case, and it could actually
6031 limit scheduling of the combined block quite
6034 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6035 REGNO (SET_DEST (set))))
6036 /* Similarly, we must not unconditionally set a reg
6037 used as scratch in the THEN branch if the same reg
6038 is live in the ELSE branch. */
6039 && (! ce_info->else_bb
6040 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6041 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6042 REGNO (SET_DEST (set))))))
6045 else if (mode == QImode || mode == HImode || mode == SImode
6048 int changed_p = FALSE;
6050 /* Check for just loading up a constant */
6051 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6053 src = frv_ifcvt_load_value (src, insn);
6060 /* See if we need to fix up stores */
6061 if (GET_CODE (dest) == MEM)
6063 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6068 else if (new_mem != dest)
6075 /* See if we need to fix up loads */
6076 if (GET_CODE (src) == MEM)
6078 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6083 else if (new_mem != src)
6090 /* If either src or destination changed, redo SET. */
6092 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6095 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6096 rewriting the CC register to be the same as the paired CC/CR register
6098 else if (mode == CC_CCRmode && COMPARISON_P (src))
6100 int regno = REGNO (XEXP (src, 0));
6103 if (ce_info->pass > 1
6104 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6105 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6107 src = gen_rtx_fmt_ee (GET_CODE (src),
6109 frv_ifcvt.nested_cc_reg,
6113 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6114 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6117 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6118 else if (ce_info->pass > 1
6119 && GET_CODE (dest) == REG
6120 && CC_P (REGNO (dest))
6121 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6122 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6124 && GET_CODE (src) == COMPARE)
6126 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6127 COND_EXEC_CODE (pattern)
6128 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6132 if (TARGET_DEBUG_COND_EXEC)
6134 rtx orig_pattern = PATTERN (insn);
6136 PATTERN (insn) = pattern;
6138 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6142 PATTERN (insn) = orig_pattern;
6148 if (TARGET_DEBUG_COND_EXEC)
6150 rtx orig_pattern = PATTERN (insn);
6152 PATTERN (insn) = orig_ce_pattern;
6154 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6158 PATTERN (insn) = orig_pattern;
6165 /* A C expression to perform any final machine dependent modifications in
6166 converting code to conditional execution in the code described by the
6167 conditional if information CE_INFO. */
6170 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6174 rtx p = frv_ifcvt.added_insns_list;
6177 /* Loop inserting the check insns. The last check insn is the first test,
6178 and is the appropriate place to insert constants. */
6183 rtx check_and_insert_insns = XEXP (p, 0);
6186 check_insn = XEXP (check_and_insert_insns, 0);
6187 existing_insn = XEXP (check_and_insert_insns, 1);
6190 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6191 the existing insn, otherwise it is to be inserted AFTER. */
6192 if (check_and_insert_insns->jump)
6194 emit_insn_before (check_insn, existing_insn);
6195 check_and_insert_insns->jump = 0;
6198 emit_insn_after (check_insn, existing_insn);
6200 free_EXPR_LIST_node (check_and_insert_insns);
6201 free_EXPR_LIST_node (old_p);
6203 while (p != NULL_RTX);
6205 /* Load up any constants needed into temp gprs */
6206 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6208 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6209 if (! frv_ifcvt.scratch_insns_bitmap)
6210 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6211 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6212 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6215 frv_ifcvt.added_insns_list = NULL_RTX;
6216 frv_ifcvt.cur_scratch_regs = 0;
6220 /* A C expression to cancel any machine dependent modifications in converting
6221 code to conditional execution in the code described by the conditional if
6222 information CE_INFO. */
6225 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6228 rtx p = frv_ifcvt.added_insns_list;
6230 /* Loop freeing up the EXPR_LIST's allocated. */
6231 while (p != NULL_RTX)
6233 rtx check_and_jump = XEXP (p, 0);
6237 free_EXPR_LIST_node (check_and_jump);
6238 free_EXPR_LIST_node (old_p);
6241 /* Release any temporary gprs allocated. */
6242 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6243 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6245 frv_ifcvt.added_insns_list = NULL_RTX;
6246 frv_ifcvt.cur_scratch_regs = 0;
6250 /* A C expression for the size in bytes of the trampoline, as an integer.
6254 setlo #0, <static_chain>
6256 sethi #0, <static_chain>
6257 jmpl @(gr0,<jmp_reg>) */
6260 frv_trampoline_size (void)
6263 /* Allocate room for the function descriptor and the lddi
6266 return 5 /* instructions */ * 4 /* instruction size. */;
6270 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6271 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6272 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6273 should be passed to the function when it is called.
6278 setlo #0, <static_chain>
6280 sethi #0, <static_chain>
6281 jmpl @(gr0,<jmp_reg>) */
6284 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6286 rtx sc_reg = force_reg (Pmode, static_chain);
6288 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6291 GEN_INT (frv_trampoline_size ()), SImode,
6297 /* Many machines have some registers that cannot be copied directly to or from
6298 memory or even from other types of registers. An example is the `MQ'
6299 register, which on most machines, can only be copied to or from general
6300 registers, but not memory. Some machines allow copying all registers to and
6301 from memory, but require a scratch register for stores to some memory
6302 locations (e.g., those with symbolic address on the RT, and those with
6303 certain symbolic address on the SPARC when compiling PIC). In some cases,
6304 both an intermediate and a scratch register are required.
6306 You should define these macros to indicate to the reload phase that it may
6307 need to allocate at least one register for a reload in addition to the
6308 register to contain the data. Specifically, if copying X to a register
6309 RCLASS in MODE requires an intermediate register, you should define
6310 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6311 whose registers can be used as intermediate registers or scratch registers.
6313 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6314 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6315 largest register class required. If the requirements for input and output
6316 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6317 instead of defining both macros identically.
6319 The values returned by these macros are often `GENERAL_REGS'. Return
6320 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6321 to or from a register of RCLASS in MODE without requiring a scratch register.
6322 Do not define this macro if it would always return `NO_REGS'.
6324 If a scratch register is required (either with or without an intermediate
6325 register), you should define patterns for `reload_inM' or `reload_outM', as
6326 required.. These patterns, which will normally be implemented with a
6327 `define_expand', should be similar to the `movM' patterns, except that
6328 operand 2 is the scratch register.
6330 Define constraints for the reload register and scratch register that contain
6331 a single register class. If the original reload register (whose class is
6332 RCLASS) can meet the constraint given in the pattern, the value returned by
6333 these macros is used for the class of the scratch register. Otherwise, two
6334 additional reload registers are required. Their classes are obtained from
6335 the constraints in the insn pattern.
6337 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6338 either be in a hard register or in memory. Use `true_regnum' to find out;
6339 it will return -1 if the pseudo is in memory and the hard register number if
6340 it is in a register.
6342 These macros should not be used in the case where a particular class of
6343 registers can only be copied to memory and not to another class of
6344 registers. In that case, secondary reload registers are not needed and
6345 would not be helpful. Instead, a stack location must be used to perform the
6346 copy and the `movM' pattern should use memory as an intermediate storage.
6347 This case often occurs between floating-point and general registers. */
6350 frv_secondary_reload_class (enum reg_class rclass,
6351 enum machine_mode mode ATTRIBUTE_UNUSED,
6362 /* Accumulators/Accumulator guard registers need to go through floating
6368 if (x && GET_CODE (x) == REG)
6370 int regno = REGNO (x);
6372 if (ACC_P (regno) || ACCG_P (regno))
6377 /* Nonzero constants should be loaded into an FPR through a GPR. */
6381 if (x && CONSTANT_P (x) && !ZERO_P (x))
6387 /* All of these types need gpr registers. */
6399 /* The accumulators need fpr registers. */
6411 /* This hook exists to catch the case where secondary_reload_class() is
6412 called from init_reg_autoinc() in regclass.c - before the reload optabs
6413 have been initialised. */
6416 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6417 enum machine_mode reload_mode,
6418 secondary_reload_info * sri)
6420 enum reg_class rclass = NO_REGS;
6422 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6424 sri->icode = sri->prev_sri->t_icode;
6428 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6430 if (rclass != NO_REGS)
6432 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6433 : reload_out_optab[(int) reload_mode]);
6436 /* This happens when then the reload_[in|out]_optabs have
6437 not been initialised. */
6438 sri->t_icode = CODE_FOR_nothing;
6443 /* Fall back to the default secondary reload handler. */
6444 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6448 /* A C expression whose value is nonzero if pseudos that have been assigned to
6449 registers of class RCLASS would likely be spilled because registers of RCLASS
6450 are needed for spill registers.
6452 The default value of this macro returns 1 if RCLASS has exactly one register
6453 and zero otherwise. On most machines, this default should be used. Only
6454 define this macro to some other expression if pseudo allocated by
6455 `local-alloc.c' end up in memory because their hard registers were needed
6456 for spill registers. If this macro returns nonzero for those classes, those
6457 pseudos will only be allocated by `global.c', which knows how to reallocate
6458 the pseudo to another register. If there would not be another register
6459 available for reallocation, you should not change the definition of this
6460 macro since the only effect of such a definition would be to slow down
6461 register allocation. */
6464 frv_class_likely_spilled_p (enum reg_class rclass)
6474 case FDPIC_FPTR_REGS:
6496 /* An expression for the alignment of a structure field FIELD if the
6497 alignment computed in the usual way is COMPUTED. GCC uses this
6498 value instead of the value in `BIGGEST_ALIGNMENT' or
6499 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6501 /* The definition type of the bit field data is either char, short, long or
6502 long long. The maximum bit size is the number of bits of its own type.
6504 The bit field data is assigned to a storage unit that has an adequate size
6505 for bit field data retention and is located at the smallest address.
6507 Consecutive bit field data are packed at consecutive bits having the same
6508 storage unit, with regard to the type, beginning with the MSB and continuing
6511 If a field to be assigned lies over a bit field type boundary, its
6512 assignment is completed by aligning it with a boundary suitable for the
6515 When a bit field having a bit length of 0 is declared, it is forcibly
6516 assigned to the next storage unit.
6529 &x 00000000 00000000 00000000 00000000
6532 &x+4 00000000 00000000 00000000 00000000
6535 &x+8 00000000 00000000 00000000 00000000
6538 &x+12 00000000 00000000 00000000 00000000
6544 frv_adjust_field_align (tree field, int computed)
6546 /* Make sure that the bitfield is not wider than the type. */
6547 if (DECL_BIT_FIELD (field)
6548 && !DECL_ARTIFICIAL (field))
6550 tree parent = DECL_CONTEXT (field);
6551 tree prev = NULL_TREE;
6554 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6556 if (TREE_CODE (cur) != FIELD_DECL)
6564 /* If this isn't a :0 field and if the previous element is a bitfield
6565 also, see if the type is different, if so, we will need to align the
6566 bit-field to the next boundary. */
6568 && ! DECL_PACKED (field)
6569 && ! integer_zerop (DECL_SIZE (field))
6570 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6572 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6573 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6574 computed = (prev_align > cur_align) ? prev_align : cur_align;
6582 /* A C expression that is nonzero if it is permissible to store a value of mode
6583 MODE in hard register number REGNO (or in several registers starting with
6584 that one). For a machine where all registers are equivalent, a suitable
6587 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6589 It is not necessary for this macro to check for the numbers of fixed
6590 registers, because the allocation mechanism considers them to be always
6593 On some machines, double-precision values must be kept in even/odd register
6594 pairs. The way to implement that is to define this macro to reject odd
6595 register numbers for such modes.
6597 The minimum requirement for a mode to be OK in a register is that the
6598 `movMODE' instruction pattern support moves between the register and any
6599 other hard register for which the mode is OK; and that moving a value into
6600 the register and back out not alter it.
6602 Since the same instruction used to move `SImode' will work for all narrower
6603 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6604 to distinguish between these modes, provided you define patterns `movhi',
6605 etc., to take advantage of this. This is useful because of the interaction
6606 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6607 all integer modes to be tieable.
6609 Many machines have special registers for floating point arithmetic. Often
6610 people assume that floating point machine modes are allowed only in floating
6611 point registers. This is not true. Any registers that can hold integers
6612 can safely *hold* a floating point machine mode, whether or not floating
6613 arithmetic can be done on it in those registers. Integer move instructions
6614 can be used to move the values.
6616 On some machines, though, the converse is true: fixed-point machine modes
6617 may not go in floating registers. This is true if the floating registers
6618 normalize any value stored in them, because storing a non-floating value
6619 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6620 fixed-point machine modes in floating registers. But if the floating
6621 registers do not automatically normalize, if you can store any bit pattern
6622 in one and retrieve it unchanged without a trap, then any machine mode may
6623 go in a floating register, so you can define this macro to say so.
6625 The primary significance of special floating registers is rather that they
6626 are the registers acceptable in floating point arithmetic instructions.
6627 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6628 writing the proper constraints for those instructions.
6630 On some machines, the floating registers are especially slow to access, so
6631 that it is better to store a value in a stack frame than in such a register
6632 if floating point arithmetic is not being done. As long as the floating
6633 registers are not in class `GENERAL_REGS', they will not be used unless some
6634 pattern's constraint asks for one. */
6637 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6647 return ICC_P (regno) || GPR_P (regno);
6650 return CR_P (regno) || GPR_P (regno);
6653 return FCC_P (regno) || GPR_P (regno);
6659 /* Set BASE to the first register in REGNO's class. Set MASK to the
6660 bits that must be clear in (REGNO - BASE) for the register to be
6662 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6666 /* ACCGs store one byte. Two-byte quantities must start in
6667 even-numbered registers, four-byte ones in registers whose
6668 numbers are divisible by four, and so on. */
6670 mask = GET_MODE_SIZE (mode) - 1;
6674 /* The other registers store one word. */
6675 if (GPR_P (regno) || regno == AP_FIRST)
6678 else if (FPR_P (regno))
6681 else if (ACC_P (regno))
6684 else if (SPR_P (regno))
6685 return mode == SImode;
6687 /* Fill in the table. */
6691 /* Anything smaller than an SI is OK in any word-sized register. */
6692 if (GET_MODE_SIZE (mode) < 4)
6695 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6697 return (((regno - base) & mask) == 0);
6704 /* A C expression for the number of consecutive hard registers, starting at
6705 register number REGNO, required to hold a value of mode MODE.
6707 On a machine where all registers are exactly one word, a suitable definition
6710 #define HARD_REGNO_NREGS(REGNO, MODE) \
6711 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6712 / UNITS_PER_WORD)) */
6714 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6715 that we can build the appropriate instructions to properly reload the
6716 values. Also, make the byte-sized accumulator guards use one guard
6720 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6723 return GET_MODE_SIZE (mode);
6725 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6729 /* A C expression for the maximum number of consecutive registers of
6730 class RCLASS needed to hold a value of mode MODE.
6732 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6733 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6734 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6736 This macro helps control the handling of multiple-word values in
6739 This declaration is required. */
6742 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6744 if (rclass == ACCG_REGS)
6745 /* An N-byte value requires N accumulator guards. */
6746 return GET_MODE_SIZE (mode);
6748 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6752 /* A C expression that is nonzero if X is a legitimate constant for an
6753 immediate operand on the target machine. You can assume that X satisfies
6754 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6755 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6758 frv_legitimate_constant_p (rtx x)
6760 enum machine_mode mode = GET_MODE (x);
6762 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6763 means that the move expanders will be expected to deal with most
6764 kinds of constant, regardless of what we return here.
6766 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6767 a constant can be entered into reg_equiv_constant[]. If we return true,
6768 reload can create new instances of the constant whenever it likes.
6770 The idea is therefore to accept as many constants as possible (to give
6771 reload more freedom) while rejecting constants that can only be created
6772 at certain times. In particular, anything with a symbolic component will
6773 require use of the pseudo FDPIC register, which is only available before
6776 return LEGITIMATE_PIC_OPERAND_P (x);
6778 /* All of the integer constants are ok. */
6779 if (GET_CODE (x) != CONST_DOUBLE)
6782 /* double integer constants are ok. */
6783 if (mode == VOIDmode || mode == DImode)
6786 /* 0 is always ok. */
6787 if (x == CONST0_RTX (mode))
6790 /* If floating point is just emulated, allow any constant, since it will be
6791 constructed in the GPRs. */
6792 if (!TARGET_HAS_FPRS)
6795 if (mode == DFmode && !TARGET_DOUBLE)
6798 /* Otherwise store the constant away and do a load. */
6802 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6803 CC_NZ for comparisons against zero in which a single Z or N flag test
6804 is enough, CC_UNS for other unsigned comparisons, and CC for other
6805 signed comparisons. */
6808 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6810 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6819 return y == const0_rtx ? CC_NZmode : CCmode;
6825 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6832 /* A C expression for the cost of moving data from a register in class FROM to
6833 one in class TO. The classes are expressed using the enumeration values
6834 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6835 interpreted relative to that.
6837 It is not required that the cost always equal 2 when FROM is the same as TO;
6838 on some machines it is expensive to move between registers if they are not
6841 If reload sees an insn consisting of a single `set' between two hard
6842 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6843 value of 2, reload does not check to ensure that the constraints of the insn
6844 are met. Setting a cost of other than 2 will allow reload to verify that
6845 the constraints are met. You should do this if the `movM' pattern's
6846 constraints do not allow such copying. */
6848 #define HIGH_COST 40
6849 #define MEDIUM_COST 3
6853 frv_register_move_cost (enum reg_class from, enum reg_class to)
6937 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6938 use ".picptr" to generate safe relocations for PIC code. We also
6939 need a fixup entry for aligned (non-debugging) code. */
6942 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6944 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6946 if (GET_CODE (value) == CONST
6947 || GET_CODE (value) == SYMBOL_REF
6948 || GET_CODE (value) == LABEL_REF)
6950 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6951 && SYMBOL_REF_FUNCTION_P (value))
6953 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6954 output_addr_const (asm_out_file, value);
6955 fputs (")\n", asm_out_file);
6958 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6959 && frv_function_symbol_referenced_p (value))
6961 if (aligned_p && !TARGET_FDPIC)
6963 static int label_num = 0;
6967 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6968 p = (* targetm.strip_name_encoding) (buf);
6970 fprintf (asm_out_file, "%s:\n", p);
6971 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6972 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6973 fprintf (asm_out_file, "\t.previous\n");
6975 assemble_integer_with_op ("\t.picptr\t", value);
6980 /* We've set the unaligned SI op to NULL, so we always have to
6981 handle the unaligned case here. */
6982 assemble_integer_with_op ("\t.4byte\t", value);
6986 return default_assemble_integer (value, size, aligned_p);
6989 /* Function to set up the backend function structure. */
6991 static struct machine_function *
6992 frv_init_machine_status (void)
6994 return GGC_CNEW (struct machine_function);
6997 /* Implement TARGET_SCHED_ISSUE_RATE. */
7000 frv_issue_rate (void)
7005 switch (frv_cpu_type)
7009 case FRV_CPU_SIMPLE:
7017 case FRV_CPU_GENERIC:
7019 case FRV_CPU_TOMCAT:
7027 /* A for_each_rtx callback. If X refers to an accumulator, return
7028 ACC_GROUP_ODD if the bit 2 of the register number is set and
7029 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7033 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7037 if (ACC_P (REGNO (*x)))
7038 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7039 if (ACCG_P (REGNO (*x)))
7040 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7045 /* Return the value of INSN's acc_group attribute. */
7048 frv_acc_group (rtx insn)
7050 /* This distinction only applies to the FR550 packing constraints. */
7051 if (frv_cpu_type != FRV_CPU_FR550)
7052 return ACC_GROUP_NONE;
7053 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7056 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7057 INSN will try to claim first. Since this value depends only on the
7058 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7061 frv_insn_unit (rtx insn)
7063 enum attr_type type;
7065 type = get_attr_type (insn);
7066 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7068 /* We haven't seen this type of instruction before. */
7072 /* Issue the instruction on its own to see which unit it prefers. */
7073 state = alloca (state_size ());
7074 state_reset (state);
7075 state_transition (state, insn);
7077 /* Find out which unit was taken. */
7078 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7079 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7082 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7084 frv_type_to_unit[type] = unit;
7086 return frv_type_to_unit[type];
7089 /* Return true if INSN issues to a branch unit. */
7092 frv_issues_to_branch_unit_p (rtx insn)
7094 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7097 /* The current state of the packing pass, implemented by frv_pack_insns. */
7099 /* The state of the pipeline DFA. */
7102 /* Which hardware registers are set within the current packet,
7103 and the conditions under which they are set. */
7104 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7106 /* The memory locations that have been modified so far in this
7107 packet. MEM is the memref and COND is the regstate_t condition
7108 under which it is set. */
7114 /* The number of valid entries in MEMS. The value is larger than
7115 ARRAY_SIZE (mems) if there were too many mems to record. */
7116 unsigned int num_mems;
7118 /* The maximum number of instructions that can be packed together. */
7119 unsigned int issue_rate;
7121 /* The instructions in the packet, partitioned into groups. */
7122 struct frv_packet_group {
7123 /* How many instructions in the packet belong to this group. */
7124 unsigned int num_insns;
7126 /* A list of the instructions that belong to this group, in the order
7127 they appear in the rtl stream. */
7128 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7130 /* The contents of INSNS after they have been sorted into the correct
7131 assembly-language order. Element X issues to unit X. The list may
7132 contain extra nops. */
7133 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7135 /* The member of frv_nops[] to use in sorted[]. */
7137 } groups[NUM_GROUPS];
7139 /* The instructions that make up the current packet. */
7140 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7141 unsigned int num_insns;
7144 /* Return the regstate_t flags for the given COND_EXEC condition.
7145 Abort if the condition isn't in the right form. */
7148 frv_cond_flags (rtx cond)
7150 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7151 && GET_CODE (XEXP (cond, 0)) == REG
7152 && CR_P (REGNO (XEXP (cond, 0)))
7153 && XEXP (cond, 1) == const0_rtx);
7154 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7155 | (GET_CODE (cond) == NE
7157 : REGSTATE_IF_FALSE));
7161 /* Return true if something accessed under condition COND2 can
7162 conflict with something written under condition COND1. */
7165 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7167 /* If either reference was unconditional, we have a conflict. */
7168 if ((cond1 & REGSTATE_IF_EITHER) == 0
7169 || (cond2 & REGSTATE_IF_EITHER) == 0)
7172 /* The references might conflict if they were controlled by
7174 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7177 /* They definitely conflict if they are controlled by the
7179 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7186 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7187 the current packet. DATA points to a regstate_t that describes the
7188 condition under which *X might be set or used. */
7191 frv_registers_conflict_p_1 (rtx *x, void *data)
7193 unsigned int regno, i;
7196 cond = *(regstate_t *) data;
7198 if (GET_CODE (*x) == REG)
7199 FOR_EACH_REGNO (regno, *x)
7200 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7201 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7204 if (GET_CODE (*x) == MEM)
7206 /* If we ran out of memory slots, assume a conflict. */
7207 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7210 /* Check for output or true dependencies with earlier MEMs. */
7211 for (i = 0; i < frv_packet.num_mems; i++)
7212 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7214 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7218 if (output_dependence (frv_packet.mems[i].mem, *x))
7223 /* The return values of calls aren't significant: they describe
7224 the effect of the call as a whole, not of the insn itself. */
7225 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7227 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7232 /* Check subexpressions. */
7237 /* Return true if something in X might depend on an instruction
7238 in the current packet. */
7241 frv_registers_conflict_p (rtx x)
7246 if (GET_CODE (x) == COND_EXEC)
7248 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7251 flags |= frv_cond_flags (XEXP (x, 0));
7254 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7258 /* A note_stores callback. DATA points to the regstate_t condition
7259 under which X is modified. Update FRV_PACKET accordingly. */
7262 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7266 if (GET_CODE (x) == REG)
7267 FOR_EACH_REGNO (regno, x)
7268 frv_packet.regstate[regno] |= *(regstate_t *) data;
7270 if (GET_CODE (x) == MEM)
7272 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7274 frv_packet.mems[frv_packet.num_mems].mem = x;
7275 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7277 frv_packet.num_mems++;
7282 /* Update the register state information for an instruction whose
7286 frv_registers_update (rtx x)
7290 flags = REGSTATE_MODIFIED;
7291 if (GET_CODE (x) == COND_EXEC)
7293 flags |= frv_cond_flags (XEXP (x, 0));
7296 note_stores (x, frv_registers_update_1, &flags);
7300 /* Initialize frv_packet for the start of a new packet. */
7303 frv_start_packet (void)
7305 enum frv_insn_group group;
7307 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7308 frv_packet.num_mems = 0;
7309 frv_packet.num_insns = 0;
7310 for (group = 0; group < NUM_GROUPS; group++)
7311 frv_packet.groups[group].num_insns = 0;
7315 /* Likewise for the start of a new basic block. */
7318 frv_start_packet_block (void)
7320 state_reset (frv_packet.dfa_state);
7321 frv_start_packet ();
7325 /* Finish the current packet, if any, and start a new one. Call
7326 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7329 frv_finish_packet (void (*handle_packet) (void))
7331 if (frv_packet.num_insns > 0)
7334 state_transition (frv_packet.dfa_state, 0);
7335 frv_start_packet ();
7340 /* Return true if INSN can be added to the current packet. Update
7341 the DFA state on success. */
7344 frv_pack_insn_p (rtx insn)
7346 /* See if the packet is already as long as it can be. */
7347 if (frv_packet.num_insns == frv_packet.issue_rate)
7350 /* If the scheduler thought that an instruction should start a packet,
7351 it's usually a good idea to believe it. It knows much more about
7352 the latencies than we do.
7354 There are some exceptions though:
7356 - Conditional instructions are scheduled on the assumption that
7357 they will be executed. This is usually a good thing, since it
7358 tends to avoid unnecessary stalls in the conditional code.
7359 But we want to pack conditional instructions as tightly as
7360 possible, in order to optimize the case where they aren't
7363 - The scheduler will always put branches on their own, even
7364 if there's no real dependency.
7366 - There's no point putting a call in its own packet unless
7368 if (frv_packet.num_insns > 0
7369 && GET_CODE (insn) == INSN
7370 && GET_MODE (insn) == TImode
7371 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7374 /* Check for register conflicts. Don't do this for setlo since any
7375 conflict will be with the partnering sethi, with which it can
7377 if (get_attr_type (insn) != TYPE_SETLO)
7378 if (frv_registers_conflict_p (PATTERN (insn)))
7381 return state_transition (frv_packet.dfa_state, insn) < 0;
7385 /* Add instruction INSN to the current packet. */
7388 frv_add_insn_to_packet (rtx insn)
7390 struct frv_packet_group *packet_group;
7392 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7393 packet_group->insns[packet_group->num_insns++] = insn;
7394 frv_packet.insns[frv_packet.num_insns++] = insn;
7396 frv_registers_update (PATTERN (insn));
7400 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7401 packet ends in a branch or call, insert the nop before it, otherwise
7405 frv_insert_nop_in_packet (rtx insn)
7407 struct frv_packet_group *packet_group;
7410 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7411 last = frv_packet.insns[frv_packet.num_insns - 1];
7412 if (GET_CODE (last) != INSN)
7414 insn = emit_insn_before (PATTERN (insn), last);
7415 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7416 frv_packet.insns[frv_packet.num_insns++] = last;
7420 insn = emit_insn_after (PATTERN (insn), last);
7421 frv_packet.insns[frv_packet.num_insns++] = insn;
7423 packet_group->insns[packet_group->num_insns++] = insn;
7427 /* If packing is enabled, divide the instructions into packets and
7428 return true. Call HANDLE_PACKET for each complete packet. */
7431 frv_for_each_packet (void (*handle_packet) (void))
7433 rtx insn, next_insn;
7435 frv_packet.issue_rate = frv_issue_rate ();
7437 /* Early exit if we don't want to pack insns. */
7439 || !flag_schedule_insns_after_reload
7440 || !TARGET_VLIW_BRANCH
7441 || frv_packet.issue_rate == 1)
7444 /* Set up the initial packing state. */
7446 frv_packet.dfa_state = alloca (state_size ());
7448 frv_start_packet_block ();
7449 for (insn = get_insns (); insn != 0; insn = next_insn)
7454 code = GET_CODE (insn);
7455 next_insn = NEXT_INSN (insn);
7457 if (code == CODE_LABEL)
7459 frv_finish_packet (handle_packet);
7460 frv_start_packet_block ();
7464 switch (GET_CODE (PATTERN (insn)))
7473 /* Calls mustn't be packed on a TOMCAT. */
7474 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7475 frv_finish_packet (handle_packet);
7477 /* Since the last instruction in a packet determines the EH
7478 region, any exception-throwing instruction must come at
7479 the end of reordered packet. Insns that issue to a
7480 branch unit are bound to come last; for others it's
7481 too hard to predict. */
7482 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7483 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7484 frv_finish_packet (handle_packet);
7486 /* Finish the current packet if we can't add INSN to it.
7487 Simulate cycles until INSN is ready to issue. */
7488 if (!frv_pack_insn_p (insn))
7490 frv_finish_packet (handle_packet);
7491 while (!frv_pack_insn_p (insn))
7492 state_transition (frv_packet.dfa_state, 0);
7495 /* Add the instruction to the packet. */
7496 frv_add_insn_to_packet (insn);
7498 /* Calls and jumps end a packet, as do insns that throw
7500 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7501 frv_finish_packet (handle_packet);
7505 frv_finish_packet (handle_packet);
7510 /* Subroutine of frv_sort_insn_group. We are trying to sort
7511 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7512 language order. We have already picked a new position for
7513 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7514 These instructions will occupy elements [0, LOWER_SLOT) and
7515 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7516 the DFA state after issuing these instructions.
7518 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7519 of the unused instructions. Return true if one such permutation gives
7520 a valid ordering, leaving the successful permutation in sorted[].
7521 Do not modify sorted[] until a valid permutation is found. */
7524 frv_sort_insn_group_1 (enum frv_insn_group group,
7525 unsigned int lower_slot, unsigned int upper_slot,
7526 unsigned int issued, unsigned int num_insns,
7529 struct frv_packet_group *packet_group;
7535 /* Early success if we've filled all the slots. */
7536 if (lower_slot == upper_slot)
7539 packet_group = &frv_packet.groups[group];
7540 dfa_size = state_size ();
7541 test_state = alloca (dfa_size);
7543 /* Try issuing each unused instruction. */
7544 for (i = num_insns - 1; i + 1 != 0; i--)
7545 if (~issued & (1 << i))
7547 insn = packet_group->sorted[i];
7548 memcpy (test_state, state, dfa_size);
7549 if (state_transition (test_state, insn) < 0
7550 && cpu_unit_reservation_p (test_state,
7551 NTH_UNIT (group, upper_slot - 1))
7552 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7553 issued | (1 << i), num_insns,
7556 packet_group->sorted[upper_slot - 1] = insn;
7564 /* Compare two instructions by their frv_insn_unit. */
7567 frv_compare_insns (const void *first, const void *second)
7569 const rtx *const insn1 = (rtx const *) first,
7570 *const insn2 = (rtx const *) second;
7571 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7574 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7575 and sort it into assembly language order. See frv.md for a description of
7579 frv_sort_insn_group (enum frv_insn_group group)
7581 struct frv_packet_group *packet_group;
7582 unsigned int first, i, nop, max_unit, num_slots;
7583 state_t state, test_state;
7586 packet_group = &frv_packet.groups[group];
7588 /* Assume no nop is needed. */
7589 packet_group->nop = 0;
7591 if (packet_group->num_insns == 0)
7594 /* Copy insns[] to sorted[]. */
7595 memcpy (packet_group->sorted, packet_group->insns,
7596 sizeof (rtx) * packet_group->num_insns);
7598 /* Sort sorted[] by the unit that each insn tries to take first. */
7599 if (packet_group->num_insns > 1)
7600 qsort (packet_group->sorted, packet_group->num_insns,
7601 sizeof (rtx), frv_compare_insns);
7603 /* That's always enough for branch and control insns. */
7604 if (group == GROUP_B || group == GROUP_C)
7607 dfa_size = state_size ();
7608 state = alloca (dfa_size);
7609 test_state = alloca (dfa_size);
7611 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7612 consecutively and such that the DFA takes unit X when sorted[X]
7613 is added. Set STATE to the new DFA state. */
7614 state_reset (test_state);
7615 for (first = 0; first < packet_group->num_insns; first++)
7617 memcpy (state, test_state, dfa_size);
7618 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7619 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7623 /* If all the instructions issued in ascending order, we're done. */
7624 if (first == packet_group->num_insns)
7627 /* Add nops to the end of sorted[] and try each permutation until
7628 we find one that works. */
7629 for (nop = 0; nop < frv_num_nops; nop++)
7631 max_unit = frv_insn_unit (frv_nops[nop]);
7632 if (frv_unit_groups[max_unit] == group)
7634 packet_group->nop = frv_nops[nop];
7635 num_slots = UNIT_NUMBER (max_unit) + 1;
7636 for (i = packet_group->num_insns; i < num_slots; i++)
7637 packet_group->sorted[i] = frv_nops[nop];
7638 if (frv_sort_insn_group_1 (group, first, num_slots,
7639 (1 << first) - 1, num_slots, state))
7646 /* Sort the current packet into assembly-language order. Set packing
7647 flags as appropriate. */
7650 frv_reorder_packet (void)
7652 unsigned int cursor[NUM_GROUPS];
7653 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7654 unsigned int unit, to, from;
7655 enum frv_insn_group group;
7656 struct frv_packet_group *packet_group;
7658 /* First sort each group individually. */
7659 for (group = 0; group < NUM_GROUPS; group++)
7662 frv_sort_insn_group (group);
7665 /* Go through the unit template and try add an instruction from
7666 that unit's group. */
7668 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7670 group = frv_unit_groups[unit];
7671 packet_group = &frv_packet.groups[group];
7672 if (cursor[group] < packet_group->num_insns)
7674 /* frv_reorg should have added nops for us. */
7675 gcc_assert (packet_group->sorted[cursor[group]]
7676 != packet_group->nop);
7677 insns[to++] = packet_group->sorted[cursor[group]++];
7681 gcc_assert (to == frv_packet.num_insns);
7683 /* Clear the last instruction's packing flag, thus marking the end of
7684 a packet. Reorder the other instructions relative to it. */
7685 CLEAR_PACKING_FLAG (insns[to - 1]);
7686 for (from = 0; from < to - 1; from++)
7688 remove_insn (insns[from]);
7689 add_insn_before (insns[from], insns[to - 1], NULL);
7690 SET_PACKING_FLAG (insns[from]);
7695 /* Divide instructions into packets. Reorder the contents of each
7696 packet so that they are in the correct assembly-language order.
7698 Since this pass can change the raw meaning of the rtl stream, it must
7699 only be called at the last minute, just before the instructions are
7703 frv_pack_insns (void)
7705 if (frv_for_each_packet (frv_reorder_packet))
7706 frv_insn_packing_flag = 0;
7708 frv_insn_packing_flag = -1;
7711 /* See whether we need to add nops to group GROUP in order to
7712 make a valid packet. */
7715 frv_fill_unused_units (enum frv_insn_group group)
7717 unsigned int non_nops, nops, i;
7718 struct frv_packet_group *packet_group;
7720 packet_group = &frv_packet.groups[group];
7722 /* Sort the instructions into assembly-language order.
7723 Use nops to fill slots that are otherwise unused. */
7724 frv_sort_insn_group (group);
7726 /* See how many nops are needed before the final useful instruction. */
7728 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7729 while (packet_group->sorted[i++] == packet_group->nop)
7732 /* Insert that many nops into the instruction stream. */
7734 frv_insert_nop_in_packet (packet_group->nop);
7737 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7740 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7742 if (io1->const_address != 0 && io2->const_address != 0)
7743 return io1->const_address == io2->const_address;
7745 if (io1->var_address != 0 && io2->var_address != 0)
7746 return rtx_equal_p (io1->var_address, io2->var_address);
7751 /* Return true if operations IO1 and IO2 are guaranteed to complete
7755 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7757 /* The order of writes is always preserved. */
7758 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7761 /* The order of reads isn't preserved. */
7762 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7765 /* One operation is a write and the other is (or could be) a read.
7766 The order is only guaranteed if the accesses are to the same
7768 return frv_same_doubleword_p (io1, io2);
7771 /* Generalize I/O operation X so that it covers both X and Y. */
7774 frv_io_union (struct frv_io *x, const struct frv_io *y)
7776 if (x->type != y->type)
7777 x->type = FRV_IO_UNKNOWN;
7778 if (!frv_same_doubleword_p (x, y))
7780 x->const_address = 0;
7785 /* Fill IO with information about the load or store associated with
7786 membar instruction INSN. */
7789 frv_extract_membar (struct frv_io *io, rtx insn)
7791 extract_insn (insn);
7792 io->type = INTVAL (recog_data.operand[2]);
7793 io->const_address = INTVAL (recog_data.operand[1]);
7794 io->var_address = XEXP (recog_data.operand[0], 0);
7797 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7798 if X is a register and *DATA depends on X. */
7801 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7803 rtx *other = (rtx *) data;
7805 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7809 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7810 Remove every modified register from the set. */
7813 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7815 HARD_REG_SET *set = (HARD_REG_SET *) data;
7819 FOR_EACH_REGNO (regno, x)
7820 CLEAR_HARD_REG_BIT (*set, regno);
7823 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7824 Add every register in *X to the set. */
7827 frv_io_handle_use_1 (rtx *x, void *data)
7829 HARD_REG_SET *set = (HARD_REG_SET *) data;
7833 FOR_EACH_REGNO (regno, *x)
7834 SET_HARD_REG_BIT (*set, regno);
7839 /* A note_stores callback that applies frv_io_handle_use_1 to an
7840 entire rhs value. */
7843 frv_io_handle_use (rtx *x, void *data)
7845 for_each_rtx (x, frv_io_handle_use_1, data);
7848 /* Go through block BB looking for membars to remove. There are two
7849 cases where intra-block analysis is enough:
7851 - a membar is redundant if it occurs between two consecutive I/O
7852 operations and if those operations are guaranteed to complete
7855 - a membar for a __builtin_read is redundant if the result is
7856 used before the next I/O operation is issued.
7858 If the last membar in the block could not be removed, and there
7859 are guaranteed to be no I/O operations between that membar and
7860 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7863 Describe the block's first I/O operation in *NEXT_IO. Describe
7864 an unknown operation if the block doesn't do any I/O. */
7867 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7870 HARD_REG_SET used_regs;
7871 rtx next_membar, set, insn;
7874 /* NEXT_IO is the next I/O operation to be performed after the current
7875 instruction. It starts off as being an unknown operation. */
7876 memset (next_io, 0, sizeof (*next_io));
7878 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7879 next_is_end_p = true;
7881 /* If the current instruction is a __builtin_read or __builtin_write,
7882 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7883 is null if the membar has already been deleted.
7885 Note that the initialization here should only be needed to
7886 suppress warnings. */
7889 /* USED_REGS is the set of registers that are used before the
7890 next I/O instruction. */
7891 CLEAR_HARD_REG_SET (used_regs);
7893 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7894 if (GET_CODE (insn) == CALL_INSN)
7896 /* We can't predict what a call will do to volatile memory. */
7897 memset (next_io, 0, sizeof (struct frv_io));
7898 next_is_end_p = false;
7899 CLEAR_HARD_REG_SET (used_regs);
7901 else if (INSN_P (insn))
7902 switch (recog_memoized (insn))
7904 case CODE_FOR_optional_membar_qi:
7905 case CODE_FOR_optional_membar_hi:
7906 case CODE_FOR_optional_membar_si:
7907 case CODE_FOR_optional_membar_di:
7911 /* Local information isn't enough to decide whether this
7912 membar is needed. Stash it away for later. */
7913 *last_membar = insn;
7914 frv_extract_membar (next_io, insn);
7915 next_is_end_p = false;
7919 /* Check whether the I/O operation before INSN could be
7920 reordered with one described by NEXT_IO. If it can't,
7921 INSN will not be needed. */
7922 struct frv_io prev_io;
7924 frv_extract_membar (&prev_io, insn);
7925 if (frv_io_fixed_order_p (&prev_io, next_io))
7929 ";; [Local] Removing membar %d since order"
7930 " of accesses is guaranteed\n",
7931 INSN_UID (next_membar));
7933 insn = NEXT_INSN (insn);
7934 delete_insn (next_membar);
7942 /* Invalidate NEXT_IO's address if it depends on something that
7943 is clobbered by INSN. */
7944 if (next_io->var_address)
7945 note_stores (PATTERN (insn), frv_io_check_address,
7946 &next_io->var_address);
7948 /* If the next membar is associated with a __builtin_read,
7949 see if INSN reads from that address. If it does, and if
7950 the destination register is used before the next I/O access,
7951 there is no need for the membar. */
7952 set = PATTERN (insn);
7953 if (next_io->type == FRV_IO_READ
7954 && next_io->var_address != 0
7956 && GET_CODE (set) == SET
7957 && GET_CODE (SET_DEST (set)) == REG
7958 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7962 src = SET_SRC (set);
7963 if (GET_CODE (src) == ZERO_EXTEND)
7964 src = XEXP (src, 0);
7966 if (GET_CODE (src) == MEM
7967 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7971 ";; [Local] Removing membar %d since the target"
7972 " of %d is used before the I/O operation\n",
7973 INSN_UID (next_membar), INSN_UID (insn));
7975 if (next_membar == *last_membar)
7978 delete_insn (next_membar);
7983 /* If INSN has volatile references, forget about any registers
7984 that are used after it. Otherwise forget about uses that
7985 are (or might be) defined by INSN. */
7986 if (volatile_refs_p (PATTERN (insn)))
7987 CLEAR_HARD_REG_SET (used_regs);
7989 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
7991 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
7996 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7997 FIRST_IO[X] describes the first operation performed by basic block X. */
8000 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8003 struct frv_io this_io, next_io;
8007 /* We need to keep the membar if there is an edge to the exit block. */
8008 FOR_EACH_EDGE (succ, ei, bb->succs)
8009 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8010 if (succ->dest == EXIT_BLOCK_PTR)
8013 /* Work out the union of all successor blocks. */
8014 ei = ei_start (bb->succs);
8015 ei_cond (ei, &succ);
8016 /* next_io = first_io[bb->succ->dest->index]; */
8017 next_io = first_io[succ->dest->index];
8018 ei = ei_start (bb->succs);
8019 if (ei_cond (ei, &succ))
8021 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8022 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8023 frv_io_union (&next_io, &first_io[succ->dest->index]);
8028 frv_extract_membar (&this_io, membar);
8029 if (frv_io_fixed_order_p (&this_io, &next_io))
8033 ";; [Global] Removing membar %d since order of accesses"
8034 " is guaranteed\n", INSN_UID (membar));
8036 delete_insn (membar);
8040 /* Remove redundant membars from the current function. */
8043 frv_optimize_membar (void)
8046 struct frv_io *first_io;
8049 compute_bb_for_insn ();
8050 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8051 last_membar = XCNEWVEC (rtx, last_basic_block);
8054 frv_optimize_membar_local (bb, &first_io[bb->index],
8055 &last_membar[bb->index]);
8058 if (last_membar[bb->index] != 0)
8059 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8065 /* Used by frv_reorg to keep track of the current packet's address. */
8066 static unsigned int frv_packet_address;
8068 /* If the current packet falls through to a label, try to pad the packet
8069 with nops in order to fit the label's alignment requirements. */
8072 frv_align_label (void)
8074 unsigned int alignment, target, nop;
8075 rtx x, last, barrier, label;
8077 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8078 maximum alignment of that packet, LABEL to the last label between
8079 the packets, and BARRIER to the last barrier. */
8080 last = frv_packet.insns[frv_packet.num_insns - 1];
8081 label = barrier = 0;
8083 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8087 unsigned int subalign = 1 << label_to_alignment (x);
8088 alignment = MAX (alignment, subalign);
8095 /* If -malign-labels, and the packet falls through to an unaligned
8096 label, try introducing a nop to align that label to 8 bytes. */
8097 if (TARGET_ALIGN_LABELS
8100 && frv_packet.num_insns < frv_packet.issue_rate)
8101 alignment = MAX (alignment, 8);
8103 /* Advance the address to the end of the current packet. */
8104 frv_packet_address += frv_packet.num_insns * 4;
8106 /* Work out the target address, after alignment. */
8107 target = (frv_packet_address + alignment - 1) & -alignment;
8109 /* If the packet falls through to the label, try to find an efficient
8110 padding sequence. */
8113 /* First try adding nops to the current packet. */
8114 for (nop = 0; nop < frv_num_nops; nop++)
8115 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8117 frv_insert_nop_in_packet (frv_nops[nop]);
8118 frv_packet_address += 4;
8121 /* If we still haven't reached the target, add some new packets that
8122 contain only nops. If there are two types of nop, insert an
8123 alternating sequence of frv_nops[0] and frv_nops[1], which will
8124 lead to packets like:
8131 etc. Just emit frv_nops[0] if that's the only nop we have. */
8132 last = frv_packet.insns[frv_packet.num_insns - 1];
8134 while (frv_packet_address < target)
8136 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8137 frv_packet_address += 4;
8138 if (frv_num_nops > 1)
8143 frv_packet_address = target;
8146 /* Subroutine of frv_reorg, called after each packet has been constructed
8150 frv_reorg_packet (void)
8152 frv_fill_unused_units (GROUP_I);
8153 frv_fill_unused_units (GROUP_FM);
8157 /* Add an instruction with pattern NOP to frv_nops[]. */
8160 frv_register_nop (rtx nop)
8162 nop = make_insn_raw (nop);
8163 NEXT_INSN (nop) = 0;
8164 PREV_INSN (nop) = 0;
8165 frv_nops[frv_num_nops++] = nop;
8168 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8169 into packets and check whether we need to insert nops in order to
8170 fulfill the processor's issue requirements. Also, if the user has
8171 requested a certain alignment for a label, try to meet that alignment
8172 by inserting nops in the previous packet. */
8177 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8178 frv_optimize_membar ();
8181 frv_register_nop (gen_nop ());
8183 frv_register_nop (gen_mnop ());
8184 if (TARGET_HARD_FLOAT)
8185 frv_register_nop (gen_fnop ());
8187 /* Estimate the length of each branch. Although this may change after
8188 we've inserted nops, it will only do so in big functions. */
8189 shorten_branches (get_insns ());
8191 frv_packet_address = 0;
8192 frv_for_each_packet (frv_reorg_packet);
8195 #define def_builtin(name, type, code) \
8196 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8198 struct builtin_description
8200 enum insn_code icode;
8202 enum frv_builtins code;
8203 enum rtx_code comparison;
8207 /* Media intrinsics that take a single, constant argument. */
8209 static struct builtin_description bdesc_set[] =
8211 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8214 /* Media intrinsics that take just one argument. */
8216 static struct builtin_description bdesc_1arg[] =
8218 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8219 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8220 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8221 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8222 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8223 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8226 /* Media intrinsics that take two arguments. */
8228 static struct builtin_description bdesc_2arg[] =
8230 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8231 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8232 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8233 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8234 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8235 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8236 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8237 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8238 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8239 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8240 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8241 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8242 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8243 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8244 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8245 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8246 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8247 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8248 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8249 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8250 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8251 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8252 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8253 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8254 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8255 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8256 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8259 /* Integer intrinsics that take two arguments and have no return value. */
8261 static struct builtin_description bdesc_int_void2arg[] =
8263 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8264 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8265 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8268 static struct builtin_description bdesc_prefetches[] =
8270 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8271 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8274 /* Media intrinsics that take two arguments, the first being an ACC number. */
8276 static struct builtin_description bdesc_cut[] =
8278 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8279 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8280 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8283 /* Two-argument media intrinsics with an immediate second argument. */
8285 static struct builtin_description bdesc_2argimm[] =
8287 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8288 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8289 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8290 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8291 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8292 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8293 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8294 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8295 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8296 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8297 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8298 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8299 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8300 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8301 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8302 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8303 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8306 /* Media intrinsics that take two arguments and return void, the first argument
8307 being a pointer to 4 words in memory. */
8309 static struct builtin_description bdesc_void2arg[] =
8311 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8312 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8315 /* Media intrinsics that take three arguments, the first being a const_int that
8316 denotes an accumulator, and that return void. */
8318 static struct builtin_description bdesc_void3arg[] =
8320 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8321 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8322 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8323 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8324 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8325 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8326 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8327 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8328 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8329 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8330 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8331 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8332 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8333 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8334 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8335 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8336 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8337 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8338 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8339 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8340 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8341 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8342 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8343 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8344 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8347 /* Media intrinsics that take two accumulator numbers as argument and
8350 static struct builtin_description bdesc_voidacc[] =
8352 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8353 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8354 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8355 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8356 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8357 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8360 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8361 a normal move and the ICODE is for the membar. */
8363 static struct builtin_description bdesc_loads[] =
8365 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8366 FRV_BUILTIN_READ8, 0, 0 },
8367 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8368 FRV_BUILTIN_READ16, 0, 0 },
8369 { CODE_FOR_optional_membar_si, "__builtin_read32",
8370 FRV_BUILTIN_READ32, 0, 0 },
8371 { CODE_FOR_optional_membar_di, "__builtin_read64",
8372 FRV_BUILTIN_READ64, 0, 0 }
8375 /* Likewise stores. */
8377 static struct builtin_description bdesc_stores[] =
8379 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8380 FRV_BUILTIN_WRITE8, 0, 0 },
8381 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8382 FRV_BUILTIN_WRITE16, 0, 0 },
8383 { CODE_FOR_optional_membar_si, "__builtin_write32",
8384 FRV_BUILTIN_WRITE32, 0, 0 },
8385 { CODE_FOR_optional_membar_di, "__builtin_write64",
8386 FRV_BUILTIN_WRITE64, 0, 0 },
8389 /* Initialize media builtins. */
8392 frv_init_builtins (void)
8394 tree endlink = void_list_node;
8395 tree accumulator = integer_type_node;
8396 tree integer = integer_type_node;
8397 tree voidt = void_type_node;
8398 tree uhalf = short_unsigned_type_node;
8399 tree sword1 = long_integer_type_node;
8400 tree uword1 = long_unsigned_type_node;
8401 tree sword2 = long_long_integer_type_node;
8402 tree uword2 = long_long_unsigned_type_node;
8403 tree uword4 = build_pointer_type (uword1);
8404 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8405 tree ubyte = unsigned_char_type_node;
8406 tree iacc = integer_type_node;
8408 #define UNARY(RET, T1) \
8409 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8411 #define BINARY(RET, T1, T2) \
8412 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8413 tree_cons (NULL_TREE, T2, endlink)))
8415 #define TRINARY(RET, T1, T2, T3) \
8416 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8417 tree_cons (NULL_TREE, T2, \
8418 tree_cons (NULL_TREE, T3, endlink))))
8420 #define QUAD(RET, T1, T2, T3, T4) \
8421 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8422 tree_cons (NULL_TREE, T2, \
8423 tree_cons (NULL_TREE, T3, \
8424 tree_cons (NULL_TREE, T4, endlink)))))
8426 tree void_ftype_void = build_function_type (voidt, endlink);
8428 tree void_ftype_acc = UNARY (voidt, accumulator);
8429 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8430 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8431 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8432 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8433 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8434 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8435 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8436 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8438 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8439 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8440 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8441 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8442 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8443 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8444 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8445 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8446 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8447 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8448 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8450 tree sw1_ftype_int = UNARY (sword1, integer);
8451 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8452 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8454 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8455 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8456 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8457 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8458 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8459 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8461 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8462 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8463 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8464 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8465 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8466 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8467 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8468 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8469 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8470 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8471 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8472 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8473 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8474 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8475 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8476 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8477 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8479 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8480 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8481 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8482 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8483 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8484 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8485 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8486 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8487 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8488 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8489 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8490 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8491 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8492 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8493 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8494 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8495 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8496 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8497 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8498 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8499 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8500 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8501 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8502 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8503 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8504 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8505 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8506 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8507 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8508 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8509 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8510 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8511 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8512 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8513 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8514 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8515 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8516 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8517 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8518 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8519 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8520 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8521 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8522 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8523 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8524 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8525 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8526 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8527 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8528 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8529 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8530 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8531 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8532 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8533 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8534 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8535 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8536 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8537 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8538 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8539 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8540 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8541 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8542 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8543 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8544 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8545 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8546 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8547 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8548 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8549 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8550 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8551 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8552 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8553 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8554 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8555 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8556 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8557 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8558 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8559 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8560 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8561 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8562 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8563 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8564 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8565 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8566 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8567 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8568 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8569 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8570 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8571 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8572 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8573 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8574 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8575 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8576 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8577 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8578 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8579 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8580 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8581 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8582 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8583 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8584 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8585 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8586 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8588 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8589 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8590 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8591 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8599 /* Set the names for various arithmetic operations according to the
8602 frv_init_libfuncs (void)
8604 set_optab_libfunc (smod_optab, SImode, "__modi");
8605 set_optab_libfunc (umod_optab, SImode, "__umodi");
8607 set_optab_libfunc (add_optab, DImode, "__addll");
8608 set_optab_libfunc (sub_optab, DImode, "__subll");
8609 set_optab_libfunc (smul_optab, DImode, "__mulll");
8610 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8611 set_optab_libfunc (smod_optab, DImode, "__modll");
8612 set_optab_libfunc (umod_optab, DImode, "__umodll");
8613 set_optab_libfunc (and_optab, DImode, "__andll");
8614 set_optab_libfunc (ior_optab, DImode, "__orll");
8615 set_optab_libfunc (xor_optab, DImode, "__xorll");
8616 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8618 set_optab_libfunc (add_optab, SFmode, "__addf");
8619 set_optab_libfunc (sub_optab, SFmode, "__subf");
8620 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8621 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8623 set_optab_libfunc (add_optab, DFmode, "__addd");
8624 set_optab_libfunc (sub_optab, DFmode, "__subd");
8625 set_optab_libfunc (smul_optab, DFmode, "__muld");
8626 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8628 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8629 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8631 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8632 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8633 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8634 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8636 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8637 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8638 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8639 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8641 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8642 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8643 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8644 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8647 /* Convert an integer constant to an accumulator register. ICODE is the
8648 code of the target instruction, OPNUM is the number of the
8649 accumulator operand and OPVAL is the constant integer. Try both
8650 ACC and ACCG registers; only report an error if neither fit the
8654 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8659 /* ACCs and ACCGs are implicit global registers if media intrinsics
8660 are being used. We set up this lazily to avoid creating lots of
8661 unnecessary call_insn rtl in non-media code. */
8662 for (i = 0; i <= ACC_MASK; i++)
8663 if ((i & ACC_MASK) == i)
8664 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8666 if (GET_CODE (opval) != CONST_INT)
8668 error ("accumulator is not a constant integer");
8671 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8673 error ("accumulator number is out of bounds");
8677 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8678 ACC_FIRST + INTVAL (opval));
8679 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8680 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8682 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8684 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8690 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8693 static enum machine_mode
8694 frv_matching_accg_mode (enum machine_mode mode)
8712 /* Given that a __builtin_read or __builtin_write function is accessing
8713 address ADDRESS, return the value that should be used as operand 1
8717 frv_io_address_cookie (rtx address)
8719 return (GET_CODE (address) == CONST_INT
8720 ? GEN_INT (INTVAL (address) / 8 * 8)
8724 /* Return the accumulator guard that should be paired with accumulator
8725 register ACC. The mode of the returned register is in the same
8726 class as ACC, but is four times smaller. */
8729 frv_matching_accg_for_acc (rtx acc)
8731 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8732 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8735 /* Read the requested argument from the call EXP given by INDEX.
8736 Return the value as an rtx. */
8739 frv_read_argument (tree exp, unsigned int index)
8741 return expand_expr (CALL_EXPR_ARG (exp, index),
8742 NULL_RTX, VOIDmode, 0);
8745 /* Like frv_read_argument, but interpret the argument as the number
8746 of an IACC register and return a (reg:MODE ...) rtx for it. */
8749 frv_read_iacc_argument (enum machine_mode mode, tree call,
8755 op = frv_read_argument (call, index);
8756 if (GET_CODE (op) != CONST_INT
8758 || INTVAL (op) > IACC_LAST - IACC_FIRST
8759 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8761 error ("invalid IACC argument");
8765 /* IACCs are implicit global registers. We set up this lazily to
8766 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8768 regno = INTVAL (op) + IACC_FIRST;
8769 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8770 global_regs[regno + i] = 1;
8772 return gen_rtx_REG (mode, regno);
8775 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8776 The instruction should require a constant operand of some sort. The
8777 function prints an error if OPVAL is not valid. */
8780 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8782 if (GET_CODE (opval) != CONST_INT)
8784 error ("%qs expects a constant argument", insn_data[icode].name);
8787 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8789 error ("constant argument out of range for %qs", insn_data[icode].name);
8795 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8796 if it's not null, has the right mode, and satisfies operand 0's
8800 frv_legitimize_target (enum insn_code icode, rtx target)
8802 enum machine_mode mode = insn_data[icode].operand[0].mode;
8805 || GET_MODE (target) != mode
8806 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8807 return gen_reg_rtx (mode);
8812 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8813 check whether ARG satisfies the operand's constraints. If it doesn't,
8814 copy ARG to a temporary register and return that. Otherwise return ARG
8818 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8820 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8822 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8825 return copy_to_mode_reg (mode, arg);
8828 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8831 frv_volatile_memref (enum machine_mode mode, rtx arg)
8835 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8836 MEM_VOLATILE_P (mem) = 1;
8840 /* Expand builtins that take a single, constant argument. At the moment,
8841 only MHDSETS falls into this category. */
8844 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8847 rtx op0 = frv_read_argument (call, 0);
8849 if (! frv_check_constant_argument (icode, 1, op0))
8852 target = frv_legitimize_target (icode, target);
8853 pat = GEN_FCN (icode) (target, op0);
8861 /* Expand builtins that take one operand. */
8864 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8867 rtx op0 = frv_read_argument (call, 0);
8869 target = frv_legitimize_target (icode, target);
8870 op0 = frv_legitimize_argument (icode, 1, op0);
8871 pat = GEN_FCN (icode) (target, op0);
8879 /* Expand builtins that take two operands. */
8882 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8885 rtx op0 = frv_read_argument (call, 0);
8886 rtx op1 = frv_read_argument (call, 1);
8888 target = frv_legitimize_target (icode, target);
8889 op0 = frv_legitimize_argument (icode, 1, op0);
8890 op1 = frv_legitimize_argument (icode, 2, op1);
8891 pat = GEN_FCN (icode) (target, op0, op1);
8899 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8903 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8906 rtx op0 = frv_read_argument (call, 0);
8907 rtx op1 = frv_read_argument (call, 1);
8910 target = frv_legitimize_target (icode, target);
8911 op0 = frv_int_to_acc (icode, 1, op0);
8915 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8917 if (! frv_check_constant_argument (icode, 2, op1))
8921 op1 = frv_legitimize_argument (icode, 2, op1);
8923 op2 = frv_matching_accg_for_acc (op0);
8924 pat = GEN_FCN (icode) (target, op0, op1, op2);
8932 /* Expand builtins that take two operands and the second is immediate. */
8935 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8938 rtx op0 = frv_read_argument (call, 0);
8939 rtx op1 = frv_read_argument (call, 1);
8941 if (! frv_check_constant_argument (icode, 2, op1))
8944 target = frv_legitimize_target (icode, target);
8945 op0 = frv_legitimize_argument (icode, 1, op0);
8946 pat = GEN_FCN (icode) (target, op0, op1);
8954 /* Expand builtins that take two operands, the first operand being a pointer to
8955 ints and return void. */
8958 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8961 rtx op0 = frv_read_argument (call, 0);
8962 rtx op1 = frv_read_argument (call, 1);
8963 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8966 if (GET_CODE (op0) != MEM)
8970 if (! offsettable_address_p (0, mode0, op0))
8972 reg = gen_reg_rtx (Pmode);
8973 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8976 op0 = gen_rtx_MEM (SImode, reg);
8979 addr = XEXP (op0, 0);
8980 if (! offsettable_address_p (0, mode0, addr))
8981 addr = copy_to_mode_reg (Pmode, op0);
8983 op0 = change_address (op0, V4SImode, addr);
8984 op1 = frv_legitimize_argument (icode, 1, op1);
8985 pat = GEN_FCN (icode) (op0, op1);
8993 /* Expand builtins that take two long operands and return void. */
8996 frv_expand_int_void2arg (enum insn_code icode, tree call)
8999 rtx op0 = frv_read_argument (call, 0);
9000 rtx op1 = frv_read_argument (call, 1);
9002 op0 = frv_legitimize_argument (icode, 1, op0);
9003 op1 = frv_legitimize_argument (icode, 1, op1);
9004 pat = GEN_FCN (icode) (op0, op1);
9012 /* Expand prefetch builtins. These take a single address as argument. */
9015 frv_expand_prefetches (enum insn_code icode, tree call)
9018 rtx op0 = frv_read_argument (call, 0);
9020 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9028 /* Expand builtins that take three operands and return void. The first
9029 argument must be a constant that describes a pair or quad accumulators. A
9030 fourth argument is created that is the accumulator guard register that
9031 corresponds to the accumulator. */
9034 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9037 rtx op0 = frv_read_argument (call, 0);
9038 rtx op1 = frv_read_argument (call, 1);
9039 rtx op2 = frv_read_argument (call, 2);
9042 op0 = frv_int_to_acc (icode, 0, op0);
9046 op1 = frv_legitimize_argument (icode, 1, op1);
9047 op2 = frv_legitimize_argument (icode, 2, op2);
9048 op3 = frv_matching_accg_for_acc (op0);
9049 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9057 /* Expand builtins that perform accumulator-to-accumulator operations.
9058 These builtins take two accumulator numbers as argument and return
9062 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9065 rtx op0 = frv_read_argument (call, 0);
9066 rtx op1 = frv_read_argument (call, 1);
9070 op0 = frv_int_to_acc (icode, 0, op0);
9074 op1 = frv_int_to_acc (icode, 1, op1);
9078 op2 = frv_matching_accg_for_acc (op0);
9079 op3 = frv_matching_accg_for_acc (op1);
9080 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9088 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9089 membar and TARGET_MODE is the mode that the loaded value should have. */
9092 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9093 tree call, rtx target)
9095 rtx op0 = frv_read_argument (call, 0);
9096 rtx cookie = frv_io_address_cookie (op0);
9098 if (target == 0 || !REG_P (target))
9099 target = gen_reg_rtx (target_mode);
9100 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9101 convert_move (target, op0, 1);
9102 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9103 cfun->machine->has_membar_p = 1;
9107 /* Likewise __builtin_write* functions. */
9110 frv_expand_store_builtin (enum insn_code icode, tree call)
9112 rtx op0 = frv_read_argument (call, 0);
9113 rtx op1 = frv_read_argument (call, 1);
9114 rtx cookie = frv_io_address_cookie (op0);
9116 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9117 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9118 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9119 cfun->machine->has_membar_p = 1;
9123 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9124 each argument forms one word of the two double-word input registers.
9125 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9126 to put the return value. */
9129 frv_expand_mdpackh_builtin (tree call, rtx target)
9131 enum insn_code icode = CODE_FOR_mdpackh;
9133 rtx arg1 = frv_read_argument (call, 0);
9134 rtx arg2 = frv_read_argument (call, 1);
9135 rtx arg3 = frv_read_argument (call, 2);
9136 rtx arg4 = frv_read_argument (call, 3);
9138 target = frv_legitimize_target (icode, target);
9139 op0 = gen_reg_rtx (DImode);
9140 op1 = gen_reg_rtx (DImode);
9142 /* The high half of each word is not explicitly initialized, so indicate
9143 that the input operands are not live before this point. */
9147 /* Move each argument into the low half of its associated input word. */
9148 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9149 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9150 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9151 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9153 pat = GEN_FCN (icode) (target, op0, op1);
9161 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9162 number as argument. */
9165 frv_expand_mclracc_builtin (tree call)
9167 enum insn_code icode = CODE_FOR_mclracc;
9169 rtx op0 = frv_read_argument (call, 0);
9171 op0 = frv_int_to_acc (icode, 0, op0);
9175 pat = GEN_FCN (icode) (op0);
9182 /* Expand builtins that take no arguments. */
9185 frv_expand_noargs_builtin (enum insn_code icode)
9187 rtx pat = GEN_FCN (icode) (const0_rtx);
9194 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9195 number or accumulator guard number as argument and return an SI integer. */
9198 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9201 rtx target = gen_reg_rtx (SImode);
9202 rtx op0 = frv_read_argument (call, 0);
9204 op0 = frv_int_to_acc (icode, 1, op0);
9208 pat = GEN_FCN (icode) (target, op0);
9216 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9217 accumulator guard as their first argument and an SImode value as their
9221 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9224 rtx op0 = frv_read_argument (call, 0);
9225 rtx op1 = frv_read_argument (call, 1);
9227 op0 = frv_int_to_acc (icode, 0, op0);
9231 op1 = frv_legitimize_argument (icode, 1, op1);
9232 pat = GEN_FCN (icode) (op0, op1);
9239 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9240 to move DImode values into and out of IACC0. */
9243 frv_split_iacc_move (rtx dest, rtx src)
9245 enum machine_mode inner;
9248 inner = GET_MODE (dest);
9249 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9250 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9251 simplify_gen_subreg (SImode, src, inner, i));
9254 /* Expand builtins. */
9257 frv_expand_builtin (tree exp,
9259 rtx subtarget ATTRIBUTE_UNUSED,
9260 enum machine_mode mode ATTRIBUTE_UNUSED,
9261 int ignore ATTRIBUTE_UNUSED)
9263 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9264 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9266 struct builtin_description *d;
9268 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9270 error ("media functions are not available unless -mmedia is used");
9276 case FRV_BUILTIN_MCOP1:
9277 case FRV_BUILTIN_MCOP2:
9278 case FRV_BUILTIN_MDUNPACKH:
9279 case FRV_BUILTIN_MBTOHE:
9280 if (! TARGET_MEDIA_REV1)
9282 error ("this media function is only available on the fr500");
9287 case FRV_BUILTIN_MQXMACHS:
9288 case FRV_BUILTIN_MQXMACXHS:
9289 case FRV_BUILTIN_MQMACXHS:
9290 case FRV_BUILTIN_MADDACCS:
9291 case FRV_BUILTIN_MSUBACCS:
9292 case FRV_BUILTIN_MASACCS:
9293 case FRV_BUILTIN_MDADDACCS:
9294 case FRV_BUILTIN_MDSUBACCS:
9295 case FRV_BUILTIN_MDASACCS:
9296 case FRV_BUILTIN_MABSHS:
9297 case FRV_BUILTIN_MDROTLI:
9298 case FRV_BUILTIN_MCPLHI:
9299 case FRV_BUILTIN_MCPLI:
9300 case FRV_BUILTIN_MDCUTSSI:
9301 case FRV_BUILTIN_MQSATHS:
9302 case FRV_BUILTIN_MHSETLOS:
9303 case FRV_BUILTIN_MHSETLOH:
9304 case FRV_BUILTIN_MHSETHIS:
9305 case FRV_BUILTIN_MHSETHIH:
9306 case FRV_BUILTIN_MHDSETS:
9307 case FRV_BUILTIN_MHDSETH:
9308 if (! TARGET_MEDIA_REV2)
9310 error ("this media function is only available on the fr400"
9316 case FRV_BUILTIN_SMASS:
9317 case FRV_BUILTIN_SMSSS:
9318 case FRV_BUILTIN_SMU:
9319 case FRV_BUILTIN_ADDSS:
9320 case FRV_BUILTIN_SUBSS:
9321 case FRV_BUILTIN_SLASS:
9322 case FRV_BUILTIN_SCUTSS:
9323 case FRV_BUILTIN_IACCreadll:
9324 case FRV_BUILTIN_IACCreadl:
9325 case FRV_BUILTIN_IACCsetll:
9326 case FRV_BUILTIN_IACCsetl:
9327 if (!TARGET_FR405_BUILTINS)
9329 error ("this builtin function is only available"
9330 " on the fr405 and fr450");
9335 case FRV_BUILTIN_PREFETCH:
9336 if (!TARGET_FR500_FR550_BUILTINS)
9338 error ("this builtin function is only available on the fr500"
9344 case FRV_BUILTIN_MQLCLRHS:
9345 case FRV_BUILTIN_MQLMTHS:
9346 case FRV_BUILTIN_MQSLLHI:
9347 case FRV_BUILTIN_MQSRAHI:
9348 if (!TARGET_MEDIA_FR450)
9350 error ("this builtin function is only available on the fr450");
9359 /* Expand unique builtins. */
9363 case FRV_BUILTIN_MTRAP:
9364 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9366 case FRV_BUILTIN_MCLRACC:
9367 return frv_expand_mclracc_builtin (exp);
9369 case FRV_BUILTIN_MCLRACCA:
9371 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9373 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9375 case FRV_BUILTIN_MRDACC:
9376 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9378 case FRV_BUILTIN_MRDACCG:
9379 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9381 case FRV_BUILTIN_MWTACC:
9382 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9384 case FRV_BUILTIN_MWTACCG:
9385 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9387 case FRV_BUILTIN_MDPACKH:
9388 return frv_expand_mdpackh_builtin (exp, target);
9390 case FRV_BUILTIN_IACCreadll:
9392 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9393 if (target == 0 || !REG_P (target))
9394 target = gen_reg_rtx (DImode);
9395 frv_split_iacc_move (target, src);
9399 case FRV_BUILTIN_IACCreadl:
9400 return frv_read_iacc_argument (SImode, exp, 0);
9402 case FRV_BUILTIN_IACCsetll:
9404 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9405 rtx src = frv_read_argument (exp, 1);
9406 frv_split_iacc_move (dest, force_reg (DImode, src));
9410 case FRV_BUILTIN_IACCsetl:
9412 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9413 rtx src = frv_read_argument (exp, 1);
9414 emit_move_insn (dest, force_reg (SImode, src));
9422 /* Expand groups of builtins. */
9424 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9425 if (d->code == fcode)
9426 return frv_expand_set_builtin (d->icode, exp, target);
9428 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9429 if (d->code == fcode)
9430 return frv_expand_unop_builtin (d->icode, exp, target);
9432 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9433 if (d->code == fcode)
9434 return frv_expand_binop_builtin (d->icode, exp, target);
9436 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9437 if (d->code == fcode)
9438 return frv_expand_cut_builtin (d->icode, exp, target);
9440 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9441 if (d->code == fcode)
9442 return frv_expand_binopimm_builtin (d->icode, exp, target);
9444 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9445 if (d->code == fcode)
9446 return frv_expand_voidbinop_builtin (d->icode, exp);
9448 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9449 if (d->code == fcode)
9450 return frv_expand_voidtriop_builtin (d->icode, exp);
9452 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9453 if (d->code == fcode)
9454 return frv_expand_voidaccop_builtin (d->icode, exp);
9456 for (i = 0, d = bdesc_int_void2arg;
9457 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9458 if (d->code == fcode)
9459 return frv_expand_int_void2arg (d->icode, exp);
9461 for (i = 0, d = bdesc_prefetches;
9462 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9463 if (d->code == fcode)
9464 return frv_expand_prefetches (d->icode, exp);
9466 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9467 if (d->code == fcode)
9468 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9471 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9472 if (d->code == fcode)
9473 return frv_expand_store_builtin (d->icode, exp);
9479 frv_in_small_data_p (const_tree decl)
9482 const_tree section_name;
9484 /* Don't apply the -G flag to internal compiler structures. We
9485 should leave such structures in the main data section, partly
9486 for efficiency and partly because the size of some of them
9487 (such as C++ typeinfos) is not known until later. */
9488 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9491 /* If we already know which section the decl should be in, see if
9492 it's a small data section. */
9493 section_name = DECL_SECTION_NAME (decl);
9496 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9497 if (frv_string_begins_with (section_name, ".sdata"))
9499 if (frv_string_begins_with (section_name, ".sbss"))
9504 size = int_size_in_bytes (TREE_TYPE (decl));
9505 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9512 frv_rtx_costs (rtx x,
9513 int code ATTRIBUTE_UNUSED,
9514 int outer_code ATTRIBUTE_UNUSED,
9516 bool speed ATTRIBUTE_UNUSED)
9518 if (outer_code == MEM)
9520 /* Don't differentiate between memory addresses. All the ones
9521 we accept have equal cost. */
9522 *total = COSTS_N_INSNS (0);
9529 /* Make 12-bit integers really cheap. */
9530 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9541 *total = COSTS_N_INSNS (2);
9555 if (GET_MODE (x) == SImode)
9556 *total = COSTS_N_INSNS (1);
9557 else if (GET_MODE (x) == DImode)
9558 *total = COSTS_N_INSNS (2);
9560 *total = COSTS_N_INSNS (3);
9564 if (GET_MODE (x) == SImode)
9565 *total = COSTS_N_INSNS (2);
9567 *total = COSTS_N_INSNS (6); /* guess */
9574 *total = COSTS_N_INSNS (18);
9578 *total = COSTS_N_INSNS (3);
9587 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9589 switch_to_section (ctors_section);
9590 assemble_align (POINTER_SIZE);
9593 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9598 assemble_integer_with_op ("\t.picptr\t", symbol);
9602 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9604 switch_to_section (dtors_section);
9605 assemble_align (POINTER_SIZE);
9608 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9613 assemble_integer_with_op ("\t.picptr\t", symbol);
9616 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9619 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9620 int incoming ATTRIBUTE_UNUSED)
9622 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9625 #define TLS_BIAS (2048 - 16)
9627 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9628 We need to emit DTP-relative relocations. */
9631 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9633 gcc_assert (size == 4);
9634 fputs ("\t.picptr\ttlsmoff(", file);
9635 /* We want the unbiased TLS offset, so add the bias to the
9636 expression, such that the implicit biasing cancels out. */
9637 output_addr_const (file, plus_constant (x, TLS_BIAS));