1 ;; GCC machine description for CRX.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA. */
26 [(SP_REGNUM 15) ; Stack pointer
27 (RA_REGNUM 14) ; Return address
28 (LO_REGNUM 16) ; LO register
29 (HI_REGNUM 17) ; HI register
30 (CC_REGNUM 18) ; Condition code register
34 (define_attr "length" "" ( const_int 6 ) )
36 (define_asm_attributes
37 [(set_attr "length" "6")]
42 (define_predicate "u4bits_operand"
43 (match_code "const_int,const_double")
45 if (GET_CODE (op) == CONST_DOUBLE)
46 return crx_const_double_ok (op);
47 return (UNSIGNED_INT_FITS_N_BITS(INTVAL(op), 4)) ? 1 : 0;
51 (define_predicate "cst4_operand"
52 (and (match_code "const_int")
53 (match_test "INT_CST4(INTVAL(op))")))
55 (define_predicate "reg_or_u4bits_operand"
56 (ior (match_operand 0 "u4bits_operand")
57 (match_operand 0 "register_operand")))
59 (define_predicate "reg_or_cst4_operand"
60 (ior (match_operand 0 "cst4_operand")
61 (match_operand 0 "register_operand")))
63 (define_predicate "reg_or_sym_operand"
64 (ior (match_code "symbol_ref")
65 (match_operand 0 "register_operand")))
67 (define_predicate "nosp_reg_operand"
68 (and (match_operand 0 "register_operand")
69 (match_test "REGNO (op) != SP_REGNUM")))
71 (define_predicate "store_operand"
72 (and (match_operand 0 "memory_operand")
73 (not (match_operand 0 "push_operand"))))
75 ;; Mode Macro Definitions
77 (define_mode_macro ALLMT [QI HI SI SF DI DF])
78 (define_mode_macro CRXMM [QI HI SI SF])
79 (define_mode_macro CRXIM [QI HI SI])
80 (define_mode_macro DIDFM [DI DF])
81 (define_mode_macro SISFM [SI SF])
82 (define_mode_macro SHORT [QI HI])
84 (define_mode_attr tIsa [(QI "b") (HI "w") (SI "d") (SF "d")])
85 (define_mode_attr lImmArith [(QI "4") (HI "4") (SI "6")])
86 (define_mode_attr lImmRotl [(QI "2") (HI "2") (SI "4")])
87 (define_mode_attr IJK [(QI "I") (HI "J") (SI "K")])
88 (define_mode_attr iF [(QI "i") (HI "i") (SI "i") (DI "i") (SF "F") (DF "F")])
89 (define_mode_attr JG [(QI "J") (HI "J") (SI "J") (DI "J") (SF "G") (DF "G")])
90 ; In HI or QI mode we push 4 bytes.
91 (define_mode_attr pushCnstr [(QI "X") (HI "X") (SI "<") (SF "<") (DI "<") (DF "<")])
92 (define_mode_attr tpush [(QI "") (HI "") (SI "") (SF "") (DI "sp, ") (DF "sp, ")])
93 (define_mode_attr lpush [(QI "2") (HI "2") (SI "2") (SF "2") (DI "4") (DF "4")])
96 ;; Code Macro Definitions
98 (define_code_macro sz_xtnd [sign_extend zero_extend])
99 (define_code_attr sIsa [(sign_extend "") (zero_extend "u")])
100 (define_code_attr sPat [(sign_extend "s") (zero_extend "u")])
101 (define_code_attr szPat [(sign_extend "") (zero_extend "zero_")])
102 (define_code_attr szIsa [(sign_extend "s") (zero_extend "z")])
104 (define_code_macro sh_oprnd [ashift ashiftrt lshiftrt])
105 (define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")])
106 (define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
108 (define_code_macro mima_oprnd [smax umax smin umin])
109 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")])
111 (define_code_macro any_cond [eq ne gt gtu lt ltu ge geu le leu])
113 ;; Addition Instructions
115 (define_insn "adddi3"
116 [(set (match_operand:DI 0 "register_operand" "=r,r")
117 (plus:DI (match_operand:DI 1 "register_operand" "%0,0")
118 (match_operand:DI 2 "nonmemory_operand" "r,i")))
119 (clobber (reg:CC CC_REGNUM))]
121 "addd\\t%L2, %L1\;addcd\\t%H2, %H1"
122 [(set_attr "length" "4,12")]
125 (define_insn "add<mode>3"
126 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
127 (plus:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
128 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
129 (clobber (reg:CC CC_REGNUM))]
132 [(set_attr "length" "2,<lImmArith>")]
135 ;; Subtract Instructions
137 (define_insn "subdi3"
138 [(set (match_operand:DI 0 "register_operand" "=r,r")
139 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
140 (match_operand:DI 2 "nonmemory_operand" "r,i")))
141 (clobber (reg:CC CC_REGNUM))]
143 "subd\\t%L2, %L1\;subcd\\t%H2, %H1"
144 [(set_attr "length" "4,12")]
147 (define_insn "sub<mode>3"
148 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
149 (minus:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
150 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
151 (clobber (reg:CC CC_REGNUM))]
154 [(set_attr "length" "2,<lImmArith>")]
157 ;; Multiply Instructions
159 (define_insn "mul<mode>3"
160 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
161 (mult:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
162 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
163 (clobber (reg:CC CC_REGNUM))]
166 [(set_attr "length" "2,<lImmArith>")]
169 ;; Widening-multiplication Instructions
171 (define_insn "<sIsa>mulsidi3"
172 [(set (match_operand:DI 0 "register_operand" "=k")
173 (mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
174 (sz_xtnd:DI (match_operand:SI 2 "register_operand" "r"))))
175 (clobber (reg:CC CC_REGNUM))]
177 "mull<sPat>d\\t%2, %1"
178 [(set_attr "length" "4")]
181 (define_insn "<sIsa>mulhisi3"
182 [(set (match_operand:SI 0 "register_operand" "=r")
183 (mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%0"))
184 (sz_xtnd:SI (match_operand:HI 2 "register_operand" "r"))))
185 (clobber (reg:CC CC_REGNUM))]
187 "mul<sPat>wd\\t%2, %0"
188 [(set_attr "length" "4")]
191 (define_insn "<sIsa>mulqihi3"
192 [(set (match_operand:HI 0 "register_operand" "=r")
193 (mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%0"))
194 (sz_xtnd:HI (match_operand:QI 2 "register_operand" "r"))))
195 (clobber (reg:CC CC_REGNUM))]
197 "mul<sPat>bw\\t%2, %0"
198 [(set_attr "length" "4")]
201 ;; Logical Instructions - and
203 (define_insn "and<mode>3"
204 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
205 (and:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
206 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
207 (clobber (reg:CC CC_REGNUM))]
210 [(set_attr "length" "2,<lImmArith>")]
213 ;; Logical Instructions - or
215 (define_insn "ior<mode>3"
216 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
217 (ior:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
218 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
219 (clobber (reg:CC CC_REGNUM))]
222 [(set_attr "length" "2,<lImmArith>")]
225 ;; Logical Instructions - xor
227 (define_insn "xor<mode>3"
228 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
229 (xor:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
230 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
231 (clobber (reg:CC CC_REGNUM))]
234 [(set_attr "length" "2,<lImmArith>")]
237 ;; Sign and Zero Extend Instructions
239 (define_insn "<szPat>extendhisi2"
240 [(set (match_operand:SI 0 "register_operand" "=r")
241 (sz_xtnd:SI (match_operand:HI 1 "register_operand" "r")))
242 (clobber (reg:CC CC_REGNUM))]
244 "<szIsa>extwd\\t%1, %0"
245 [(set_attr "length" "4")]
248 (define_insn "<szPat>extendqisi2"
249 [(set (match_operand:SI 0 "register_operand" "=r")
250 (sz_xtnd:SI (match_operand:QI 1 "register_operand" "r")))
251 (clobber (reg:CC CC_REGNUM))]
253 "<szIsa>extbd\\t%1, %0"
254 [(set_attr "length" "4")]
257 (define_insn "<szPat>extendqihi2"
258 [(set (match_operand:HI 0 "register_operand" "=r")
259 (sz_xtnd:HI (match_operand:QI 1 "register_operand" "r")))
260 (clobber (reg:CC CC_REGNUM))]
262 "<szIsa>extbw\\t%1, %0"
263 [(set_attr "length" "4")]
266 ;; Negation Instructions
268 (define_insn "neg<mode>2"
269 [(set (match_operand:CRXIM 0 "register_operand" "=r")
270 (neg:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
271 (clobber (reg:CC CC_REGNUM))]
274 [(set_attr "length" "4")]
277 ;; Absolute Instructions
279 (define_insn "abs<mode>2"
280 [(set (match_operand:CRXIM 0 "register_operand" "=r")
281 (abs:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
282 (clobber (reg:CC CC_REGNUM))]
285 [(set_attr "length" "4")]
288 ;; Max and Min Instructions
290 (define_insn "<code><mode>3"
291 [(set (match_operand:CRXIM 0 "register_operand" "=r")
292 (mima_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "%0")
293 (match_operand:CRXIM 2 "register_operand" "r")))]
295 "<mimaIsa><tIsa>\\t%2, %0"
296 [(set_attr "length" "4")]
301 (define_insn "one_cmpl<mode>2"
302 [(set (match_operand:CRXIM 0 "register_operand" "=r")
303 (not:CRXIM (match_operand:CRXIM 1 "register_operand" "0")))
304 (clobber (reg:CC CC_REGNUM))]
306 "xor<tIsa>\\t$-1, %0"
307 [(set_attr "length" "2")]
310 ;; Rotate Instructions
312 (define_insn "rotl<mode>3"
313 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
314 (rotate:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
315 (match_operand:CRXIM 2 "nonmemory_operand" "r,<IJK>")))
316 (clobber (reg:CC CC_REGNUM))]
321 [(set_attr "length" "4,<lImmRotl>")]
324 (define_insn "rotr<mode>3"
325 [(set (match_operand:CRXIM 0 "register_operand" "=r")
326 (rotatert:CRXIM (match_operand:CRXIM 1 "register_operand" "0")
327 (match_operand:CRXIM 2 "register_operand" "r")))
328 (clobber (reg:CC CC_REGNUM))]
330 "rotr<tIsa>\\t%2, %0"
331 [(set_attr "length" "4")]
334 ;; Arithmetic Left and Right Shift Instructions
336 (define_insn "<shPat><mode>3"
337 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
338 (sh_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
339 (match_operand:QI 2 "nonmemory_operand" "r,<IJK>")))
340 (clobber (reg:CC CC_REGNUM))]
342 "s<shIsa><tIsa>\\t%2, %0"
343 [(set_attr "length" "2,2")]
346 ;; Bit Set Instructions
349 [(set (match_operand:SI 0 "register_operand" "=r")
350 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
351 (match_operand:SI 2 "const_int_operand" "n")
352 (match_operand:SI 3 "const_int_operand" "n")))]
355 static char buf[100];
357 int size = INTVAL (operands[2]);
358 int pos = INTVAL (operands[3]);
359 strpntr = sprintf (buf, "ram\t$%d, $31, $%d, %%1, %%0\;",
360 BITS_PER_WORD - (size + pos), BITS_PER_WORD - size);
361 sprintf (buf + strpntr, "srad\t$%d, %%0", BITS_PER_WORD - size);
364 [(set_attr "length" "6")]
368 [(set (match_operand:SI 0 "register_operand" "=r")
369 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
370 (match_operand:SI 2 "const_int_operand" "n")
371 (match_operand:SI 3 "const_int_operand" "n")))]
375 int size = INTVAL (operands[2]);
376 int pos = INTVAL (operands[3]);
377 sprintf (buf, "ram\t$%d, $%d, $0, %%1, %%0",
378 (BITS_PER_WORD - pos) % BITS_PER_WORD, size - 1);
381 [(set_attr "length" "4")]
385 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
386 (match_operand:SI 1 "const_int_operand" "n")
387 (match_operand:SI 2 "const_int_operand" "n"))
388 (match_operand:SI 3 "register_operand" "r"))]
392 int size = INTVAL (operands[1]);
393 int pos = INTVAL (operands[2]);
394 sprintf (buf, "rim\t$%d, $%d, $%d, %%3, %%0",
395 pos, size + pos - 1, pos);
398 [(set_attr "length" "4")]
403 (define_expand "mov<mode>"
404 [(set (match_operand:ALLMT 0 "nonimmediate_operand" "")
405 (match_operand:ALLMT 1 "general_operand" ""))]
408 if (!(reload_in_progress || reload_completed))
410 if (!register_operand (operands[0], <MODE>mode))
412 if (push_operand (operands[0], <MODE>mode) ?
413 !nosp_reg_operand (operands[1], <MODE>mode) :
414 !reg_or_u4bits_operand (operands[1], <MODE>mode))
416 operands[1] = copy_to_mode_reg (<MODE>mode, operands[1]);
423 (define_insn "push<mode>_internal"
424 [(set (match_operand:ALLMT 0 "push_operand" "=<pushCnstr>")
425 (match_operand:ALLMT 1 "nosp_reg_operand" "b"))]
428 [(set_attr "length" "<lpush>")]
431 (define_insn "mov<mode>_regs"
432 [(set (match_operand:SISFM 0 "register_operand" "=r, r, r, k")
433 (match_operand:SISFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
440 [(set_attr "length" "2,6,4,4")]
443 (define_insn "mov<mode>_regs"
444 [(set (match_operand:DIDFM 0 "register_operand" "=r, r, r, k")
445 (match_operand:DIDFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
448 switch (which_alternative)
450 case 0: if (REGNO (operands[0]) > REGNO (operands[1]))
451 return "movd\t%H1, %H0\;movd\t%L1, %L0";
453 return "movd\t%L1, %L0\;movd\t%H1, %H0";
454 case 1: return "movd\t%H1, %H0\;movd\t%L1, %L0";
455 case 2: return "mfpr\t%H1, %H0\;mfpr\t%L1, %L0";
456 case 3: return "mtpr\t%H1, %H0\;mtpr\t%L1, %L0";
457 default: gcc_unreachable ();
460 [(set_attr "length" "4,12,8,8")]
463 (define_insn "mov<mode>_regs" ; no HI/QI mode in HILO regs
464 [(set (match_operand:SHORT 0 "register_operand" "=r, r")
465 (match_operand:SHORT 1 "nonmemory_operand" "r, i"))]
468 [(set_attr "length" "2,<lImmArith>")]
471 (define_insn "mov<mode>_load"
472 [(set (match_operand:CRXMM 0 "register_operand" "=r")
473 (match_operand:CRXMM 1 "memory_operand" "m"))]
475 "load<tIsa>\\t%1, %0"
476 [(set_attr "length" "6")]
479 (define_insn "mov<mode>_load"
480 [(set (match_operand:DIDFM 0 "register_operand" "=r")
481 (match_operand:DIDFM 1 "memory_operand" "m"))]
484 rtx first_dest_reg = gen_rtx_REG (SImode, REGNO (operands[0]));
485 if (reg_overlap_mentioned_p (first_dest_reg, operands[1]))
486 return "loadd\t%H1, %H0\;loadd\t%L1, %L0";
487 return "loadd\t%L1, %L0\;loadd\t%H1, %H0";
489 [(set_attr "length" "12")]
492 (define_insn "mov<mode>_store"
493 [(set (match_operand:CRXMM 0 "store_operand" "=m, m")
494 (match_operand:CRXMM 1 "reg_or_u4bits_operand" "r, <JG>"))]
496 "stor<tIsa>\\t%1, %0"
497 [(set_attr "length" "6")]
500 (define_insn "mov<mode>_store"
501 [(set (match_operand:DIDFM 0 "store_operand" "=m, m")
502 (match_operand:DIDFM 1 "reg_or_u4bits_operand" "r, <JG>"))]
504 "stord\t%H1, %H0\;stord\t%L1, %L0"
505 [(set_attr "length" "12")]
508 ;; Movmem Instruction
510 (define_expand "movmemsi"
511 [(use (match_operand:BLK 0 "memory_operand" ""))
512 (use (match_operand:BLK 1 "memory_operand" ""))
513 (use (match_operand:SI 2 "nonmemory_operand" ""))
514 (use (match_operand:SI 3 "const_int_operand" ""))]
517 if (crx_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
524 ;; Compare and Branch Instructions
526 (define_insn "cbranch<mode>4"
528 (if_then_else (match_operator 0 "comparison_operator"
529 [(match_operand:CRXIM 1 "register_operand" "r")
530 (match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")])
531 (label_ref (match_operand 3 "" ""))
534 "cmpb%d0<tIsa>\\t%2, %1, %l3"
535 [(set_attr "length" "6")]
538 ;; Compare Instructions
540 (define_expand "cmp<mode>"
541 [(set (reg:CC CC_REGNUM)
542 (compare:CC (match_operand:CRXIM 0 "register_operand" "")
543 (match_operand:CRXIM 1 "nonmemory_operand" "")))]
546 crx_compare_op0 = operands[0];
547 crx_compare_op1 = operands[1];
552 (define_insn "cmp<mode>_internal"
553 [(set (reg:CC CC_REGNUM)
554 (compare:CC (match_operand:CRXIM 0 "register_operand" "r,r")
555 (match_operand:CRXIM 1 "nonmemory_operand" "r,i")))]
558 [(set_attr "length" "2,<lImmArith>")]
561 ;; Conditional Branch Instructions
563 (define_expand "b<code>"
565 (if_then_else (any_cond (reg:CC CC_REGNUM)
567 (label_ref (match_operand 0 ""))
571 crx_expand_branch (<CODE>, operands[0]);
576 (define_insn "bCOND_internal"
578 (if_then_else (match_operator 0 "comparison_operator"
581 (label_ref (match_operand 1 ""))
585 [(set_attr "length" "6")]
588 ;; Scond Instructions
590 (define_expand "s<code>"
591 [(set (match_operand:SI 0 "register_operand")
592 (any_cond:SI (reg:CC CC_REGNUM) (const_int 0)))]
595 crx_expand_scond (<CODE>, operands[0]);
600 (define_insn "sCOND_internal"
601 [(set (match_operand:SI 0 "register_operand" "=r")
602 (match_operator:SI 1 "comparison_operator"
603 [(reg:CC CC_REGNUM) (const_int 0)]))]
606 [(set_attr "length" "2")]
609 ;; Jumps and Branches
611 (define_insn "indirect_jump_return"
619 [(set_attr "length" "2")]
622 (define_insn "indirect_jump"
624 (match_operand:SI 0 "reg_or_sym_operand" "r,i"))]
629 [(set_attr "length" "2,6")]
632 (define_insn "interrupt_return"
634 [(unspec_volatile [(const_int 0)] 0)
638 return crx_prepare_push_pop_string (1);
640 [(set_attr "length" "14")]
643 (define_insn "jump_to_imm"
645 (match_operand 0 "immediate_operand" "i"))]
648 [(set_attr "length" "6")]
653 (label_ref (match_operand 0 "" "")))]
656 [(set_attr "length" "6")]
659 ;; Function Prologue and Epilogue
661 (define_expand "prologue"
665 crx_expand_prologue ();
670 (define_insn "push_for_prologue"
672 [(set (reg:SI SP_REGNUM)
673 (minus:SI (reg:SI SP_REGNUM)
674 (match_operand:SI 0 "immediate_operand" "i")))])]
677 return crx_prepare_push_pop_string (0);
679 [(set_attr "length" "4")]
682 (define_expand "epilogue"
686 crx_expand_epilogue ();
691 (define_insn "pop_and_popret_return"
693 [(set (reg:SI SP_REGNUM)
694 (plus:SI (reg:SI SP_REGNUM)
695 (match_operand:SI 0 "immediate_operand" "i")))
696 (use (reg:SI RA_REGNUM))
701 return crx_prepare_push_pop_string (1);
703 [(set_attr "length" "4")]
706 (define_insn "popret_RA_return"
708 [(use (reg:SI RA_REGNUM))
713 [(set_attr "length" "2")]
718 (define_insn "tablejump"
720 (match_operand:SI 0 "register_operand" "r"))
721 (use (label_ref:SI (match_operand 1 "" "" )))]
724 [(set_attr "length" "2")]
729 (define_expand "call"
730 [(call (match_operand:QI 0 "memory_operand" "")
731 (match_operand 1 "" ""))]
734 emit_call_insn (gen_crx_call (operands[0], operands[1]));
739 (define_expand "crx_call"
741 [(call (match_operand:QI 0 "memory_operand" "")
742 (match_operand 1 "" ""))
743 (clobber (reg:SI RA_REGNUM))])]
748 (define_insn "crx_call_insn_branch"
749 [(call (mem:QI (match_operand:SI 0 "immediate_operand" "i"))
750 (match_operand 1 "" ""))
751 (clobber (match_operand:SI 2 "register_operand" "+r"))]
754 [(set_attr "length" "6")]
757 (define_insn "crx_call_insn_jump"
758 [(call (mem:QI (match_operand:SI 0 "register_operand" "r"))
759 (match_operand 1 "" ""))
760 (clobber (match_operand:SI 2 "register_operand" "+r"))]
763 [(set_attr "length" "2")]
766 (define_insn "crx_call_insn_jalid"
767 [(call (mem:QI (mem:SI (plus:SI
768 (match_operand:SI 0 "register_operand" "r")
769 (match_operand:SI 1 "register_operand" "r"))))
770 (match_operand 2 "" ""))
771 (clobber (match_operand:SI 3 "register_operand" "+r"))]
774 [(set_attr "length" "4")]
777 ;; Call Value Instructions
779 (define_expand "call_value"
780 [(set (match_operand 0 "general_operand" "")
781 (call (match_operand:QI 1 "memory_operand" "")
782 (match_operand 2 "" "")))]
785 emit_call_insn (gen_crx_call_value (operands[0], operands[1], operands[2]));
790 (define_expand "crx_call_value"
792 [(set (match_operand 0 "general_operand" "")
793 (call (match_operand 1 "memory_operand" "")
794 (match_operand 2 "" "")))
795 (clobber (reg:SI RA_REGNUM))])]
800 (define_insn "crx_call_value_insn_branch"
801 [(set (match_operand 0 "" "=g")
802 (call (mem:QI (match_operand:SI 1 "immediate_operand" "i"))
803 (match_operand 2 "" "")))
804 (clobber (match_operand:SI 3 "register_operand" "+r"))]
807 [(set_attr "length" "6")]
810 (define_insn "crx_call_value_insn_jump"
811 [(set (match_operand 0 "" "=g")
812 (call (mem:QI (match_operand:SI 1 "register_operand" "r"))
813 (match_operand 2 "" "")))
814 (clobber (match_operand:SI 3 "register_operand" "+r"))]
817 [(set_attr "length" "2")]
820 (define_insn "crx_call_value_insn_jalid"
821 [(set (match_operand 0 "" "=g")
822 (call (mem:QI (mem:SI (plus:SI
823 (match_operand:SI 1 "register_operand" "r")
824 (match_operand:SI 2 "register_operand" "r"))))
825 (match_operand 3 "" "")))
826 (clobber (match_operand:SI 4 "register_operand" "+r"))]
829 [(set_attr "length" "4")]
840 ;; Multiply and Accumulate Instructions
842 (define_insn "<sPat>madsidi3"
843 [(set (match_operand:DI 0 "register_operand" "+k")
845 (mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
846 (sz_xtnd:DI (match_operand:SI 2 "register_operand" "r")))
848 (clobber (reg:CC CC_REGNUM))]
850 "mac<sPat>d\\t%2, %1"
851 [(set_attr "length" "4")]
854 (define_insn "<sPat>madhisi3"
855 [(set (match_operand:SI 0 "register_operand" "+l")
857 (mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%r"))
858 (sz_xtnd:SI (match_operand:HI 2 "register_operand" "r")))
860 (clobber (reg:CC CC_REGNUM))]
862 "mac<sPat>w\\t%2, %1"
863 [(set_attr "length" "4")]
866 (define_insn "<sPat>madqihi3"
867 [(set (match_operand:HI 0 "register_operand" "+l")
869 (mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%r"))
870 (sz_xtnd:HI (match_operand:QI 2 "register_operand" "r")))
872 (clobber (reg:CC CC_REGNUM))]
874 "mac<sPat>b\\t%2, %1"
875 [(set_attr "length" "4")]
880 (define_expand "doloop_end"
881 [(use (match_operand 0 "" "")) ; loop pseudo
882 (use (match_operand 1 "" "")) ; iterations; zero if unknown
883 (use (match_operand 2 "" "")) ; max iterations
884 (use (match_operand 3 "" "")) ; loop level
885 (use (match_operand 4 "" ""))] ; label
888 switch (GET_MODE (operands[0]))
891 emit_jump_insn (gen_doloop_end_si (operands[4], operands[0], operands[0]));
894 emit_jump_insn (gen_doloop_end_hi (operands[4], operands[0], operands[0]));
897 emit_jump_insn (gen_doloop_end_qi (operands[4], operands[0], operands[0]));
906 (define_insn "doloop_end_<mode>"
908 (if_then_else (ne (match_operand:CRXIM 1 "register_operand" "r,m")
910 (label_ref (match_operand 0 "" ""))
912 (set (match_operand:CRXIM 2 "register_operand" "=r,m") (plus:CRXIM (match_dup 1) (const_int -1)))
913 (clobber (match_scratch:CRXIM 3 "=X,r"))
914 (clobber (reg:CC CC_REGNUM))]
918 load<tIsa>\\t%1, %3\;add<tIsa>\\t$-1, %3\;stor<tIsa>\\t%3, %1\;bne\\t%l0"
919 [(set_attr "length" "6, 12")]