1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
58 ;; 0 PLT reference from call expansion: operand 0 is the address,
59 ;; the mode is VOIDmode. Always wrapped in CONST.
60 ;; 1 Stack frame deallocation barrier.
61 ;; 2 The address of the global offset table as a source operand.
62 ;; 3 The address of a global-offset-table-relative symbol + offset.
63 ;; 4 The offset within GOT of a symbol.
64 ;; 5 The offset within GOT of a symbol that has a PLT.
66 (define_constants ; FIXME: reorder sanely.
68 (CRIS_UNSPEC_FRAME_DEALLOC 1)
70 (CRIS_UNSPEC_GOTREL 3)
71 (CRIS_UNSPEC_GOTREAD 4)
72 (CRIS_UNSPEC_PLTGOTREAD 5)
73 (CRIS_UNSPEC_SWAP_BITS 6)])
78 (CRIS_STATIC_CHAIN_REGNUM 7)
87 ;; We need an attribute to define whether an instruction can be put in
88 ;; a branch-delay slot or not, and whether it has a delay slot.
90 ;; Branches and return instructions have a delay slot, and cannot
91 ;; themselves be put in a delay slot. This has changed *for short
92 ;; branches only* between architecture variants, but the possible win
93 ;; is presumed negligible compared to the added complexity of the machine
94 ;; description: one would have to add always-correct infrastructure to
95 ;; distinguish short branches.
97 ;; Whether an instruction can be put in a delay slot depends on the
98 ;; instruction (all short instructions except jumps and branches)
99 ;; and the addressing mode (must not be prefixed or referring to pc).
100 ;; In short, any "slottable" instruction must be 16 bit and not refer
101 ;; to pc, or alter it.
103 ;; The possible values are "yes", "no" and "has_slot". Yes/no means if
104 ;; the insn is slottable or not. Has_slot means that the insn is a
105 ;; return insn or branch insn (which are not considered slottable since
106 ;; that is generally true). Having the seemingly illogical value
107 ;; "has_slot" means we do not have to add another attribute just to say
108 ;; that an insn has a delay-slot, since it also infers that it is not
109 ;; slottable. Better names for the attribute were found to be longer and
110 ;; not add readability to the machine description.
112 ;; The default that is defined here for this attribute is "no", not
113 ;; slottable, not having a delay-slot, so there's no need to worry about
114 ;; it being wrong for non-branch and return instructions.
115 ;; The default could depend on the kind of insn and the addressing
116 ;; mode, but that would need more attributes and hairier, more error
119 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
120 ;; register. The constraints 'Q' and '>' together match all possible
121 ;; memory operands that are slottable.
122 ;; For other operands, you need to check if it has a valid "slottable"
123 ;; quick-immediate operand, where the particular signedness-variation
124 ;; may match the constraints 'I' or 'J'.), and include it in the
125 ;; constraint pattern for the slottable pattern. An alternative using
126 ;; only "r" constraints is most often slottable.
128 (define_attr "slottable" "no,yes,has_slot" (const_string "no"))
130 ;; We also need attributes to sanely determine the condition code
131 ;; state. See cris_notice_update_cc for how this is used.
133 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
135 ;; At the moment, this attribute is just used to help bb-reorder do its
136 ;; work; the default 0 doesn't help it. Many insns have other lengths,
137 ;; though none are shorter.
138 (define_attr "length" "" (const_int 2))
140 ;; A branch or return has one delay-slot. The instruction in the
141 ;; delay-slot is always executed, independent of whether the branch is
142 ;; taken or not. Note that besides setting "slottable" to "has_slot",
143 ;; there also has to be a "%#" at the end of a "delayed" instruction
144 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
145 ;; catch it and print a "nop" if necessary. This method was stolen from
148 (define_delay (eq_attr "slottable" "has_slot")
149 [(eq_attr "slottable" "yes") (nil) (nil)])
151 ;; Iterator definitions.
153 ;; For the "usual" pattern size alternatives.
154 (define_mode_iterator BWD [SI HI QI])
155 (define_mode_iterator WD [SI HI])
156 (define_mode_iterator BW [HI QI])
157 (define_mode_attr S [(SI "HI") (HI "QI")])
158 (define_mode_attr s [(SI "hi") (HI "qi")])
159 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
160 (define_mode_attr mm [(SI ".w") (HI ".b")])
161 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
163 ;; For the sign_extend+zero_extend variants.
164 (define_code_iterator szext [sign_extend zero_extend])
165 (define_code_attr u [(sign_extend "") (zero_extend "u")])
166 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
168 ;; For the shift variants.
169 (define_code_iterator shift [ashiftrt lshiftrt ashift])
170 (define_code_iterator shiftrt [ashiftrt lshiftrt])
171 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
172 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
174 (define_code_iterator ncond [eq ne gtu ltu geu leu])
175 (define_code_iterator ocond [gt le])
176 (define_code_iterator rcond [lt ge])
177 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
178 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
179 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
180 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
181 (define_code_attr oCC [(lt "mi") (ge "pl")])
182 (define_code_attr roCC [(lt "pl") (ge "mi")])
184 ;; Operand and operator predicates.
186 (include "predicates.md")
192 ;; Allow register and offsettable mem operands only; post-increment is
193 ;; not worth the trouble.
197 (match_operand:DI 0 "nonimmediate_operand" "r,o"))]
199 "test.d %M0\;ax\;test.d %H0")
201 ;; No test insns with side-effect on the mem addressing.
203 ;; See note on cmp-insns with side-effects (or lack of them)
205 ;; Normal named test patterns from SI on.
206 ;; FIXME: Seems they should change to be in order smallest..largest.
208 (define_insn "tst<mode>"
210 (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m"))]
213 [(set_attr "slottable" "yes,yes,no")])
215 ;; It seems that the position of the sign-bit and the fact that 0.0 is
216 ;; all 0-bits would make "tstsf" a straight-forward implementation;
217 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
220 ;; FIXME: Do that some time; check next_cc0_user to determine if
221 ;; zero or negative is tested for.
225 ;; We could optimize the sizes of the immediate operands for various
226 ;; cases, but that is not worth it because of the very little usage of
227 ;; DImode for anything else but a structure/block-mode. Just do the
228 ;; obvious stuff for the straight-forward constraint letters.
232 (compare (match_operand:DI 0 "nonimmediate_operand" "r,r,r,r,r,r,o")
233 (match_operand:DI 1 "general_operand" "K,I,P,n,r,o,r")))]
236 cmpq %1,%M0\;ax\;cmpq 0,%H0
237 cmpq %1,%M0\;ax\;cmpq -1,%H0
238 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
239 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
240 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
241 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
242 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
244 ;; Note that compare insns with side effect addressing mode (e.g.):
246 ;; cmp.S [rx=ry+i],rz;
247 ;; cmp.S [%3=%1+%2],%0
249 ;; are *not* usable for gcc since the reloader *does not accept*
250 ;; cc0-changing insns with side-effects other than setting the condition
251 ;; codes. The reason is that the reload stage *may* cause another insn to
252 ;; be output after the main instruction, in turn invalidating cc0 for the
253 ;; insn using the test. (This does not apply to the CRIS case, since a
254 ;; reload for output -- move to memory -- does not change the condition
255 ;; code. Unfortunately we have no way to describe that at the moment. I
256 ;; think code would improve being in the order of one percent faster.
258 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
259 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
260 ;; constants, but sometimes gcc will find its way to use it for other
261 ;; (memory) operands. Avoid side-effect patterns, though (see above).
263 (define_insn "*cmp_ext<mode>"
266 (match_operand:SI 0 "register_operand" "r,r")
267 (match_operator:SI 2 "cris_extend_operator"
268 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
271 [(set_attr "slottable" "yes,no")])
273 ;; Swap operands; it seems the canonical look (if any) is not enforced.
275 ;; FIXME: Investigate that.
277 (define_insn "*cmp_swapext<mode>"
280 (match_operator:SI 2 "cris_extend_operator"
281 [(match_operand:BW 0 "memory_operand" "Q>,m")])
282 (match_operand:SI 1 "register_operand" "r,r")))]
284 "cmp%e2<m> %0,%1" ; The function cris_notice_update_cc knows about
285 ; swapped operands to compares.
286 [(set_attr "slottable" "yes,no")])
288 ;; The "normal" compare patterns, from SI on.
293 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, r,Q>,Q>,r,r,m,m")
294 (match_operand:SI 1 "general_operand" "I,r,Q>,M,M, r, P,g,M,r")))]
307 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")])
309 (define_insn "cmp<mode>"
312 (match_operand:BW 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m")
313 (match_operand:BW 1 "general_operand" "r,Q>,M,M, r, g,M,r")))]
324 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
326 ;; Pattern matching the BTST insn.
327 ;; It is useful for "if (i & val)" constructs, where val is an exact
328 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
329 ;; of zeros starting at bit 0).
331 ;; SImode. This mode is the only one needed, since gcc automatically
332 ;; extends subregs for lower-size modes. FIXME: Add testcase.
336 (match_operand:SI 0 "nonmemory_operand" "r,r,r,r,r,r,n")
337 (match_operand:SI 1 "const_int_operand" "K,n,K,n,K,n,n")
338 (match_operand:SI 2 "nonmemory_operand" "M,M,K,n,r,r,r")))]
339 ;; Either it is a single bit, or consecutive ones starting at 0.
340 "CONST_INT_P (operands[1])
341 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
342 && (REG_S_P (operands[0])
343 || (operands[1] == const1_rtx
344 && REG_S_P (operands[2])
345 && CONST_INT_P (operands[0])
346 && exact_log2 (INTVAL (operands[0])) >= 0))"
348 ;; The last "&&" condition above should be caught by some kind of
349 ;; canonicalization in gcc, but we can easily help with it here.
350 ;; It results from expressions of the type
351 ;; "power_of_2_value & (1 << y)".
353 ;; Since there may be codes with tests in on bits (in constant position)
354 ;; beyond the size of a word, handle that by assuming those bits are 0.
355 ;; GCC should handle that, but it's a matter of easily-added belts while
356 ;; having suspenders.
366 [(set_attr "slottable" "yes")])
370 ;; The whole mandatory movdi family is here; expander, "anonymous"
371 ;; recognizer and splitter. We're forced to have a movdi pattern,
372 ;; although GCC should be able to split it up itself. Normally it can,
373 ;; but if other insns have DI operands (as is the case here), reload
374 ;; must be able to generate or match a movdi. many testcases fail at
375 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
376 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
377 ;; However, a patch from Richard Kenner (similar to the cause of
378 ;; discussion at the URL above), indicates otherwise. See
379 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
380 ;; The truth has IMO is not been decided yet, so check from time to
381 ;; time by disabling the movdi patterns.
383 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
384 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
385 ;; A cmpdi RTX needs reloading (global):
386 ;; (insn 185 326 186 (set (cc0)
387 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
388 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
390 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
391 ;; out of the instruction (into a register), since one of the operands
392 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
393 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
394 ;; wrt. overlap). The bad things happen with the synthesis in
395 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
396 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
397 ;; 22 is recognized to have an equivalent in memory which is substituted
398 ;; straight in, and we end up with an unrecognizable insn:
399 ;; (insn 325 324 326 (set (reg:SI 9 r9)
400 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
401 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
403 ;; which is the first part of the reloaded synthesized "movdi".
404 ;; The right thing would be to add equivalent replacement locations for
405 ;; insn with pseudos that need more reloading. The question is where.
407 (define_expand "movdi"
408 [(set (match_operand:DI 0 "nonimmediate_operand" "")
409 (match_operand:DI 1 "general_operand" ""))]
412 if (MEM_P (operands[0]) && operands[1] != const0_rtx)
413 operands[1] = copy_to_mode_reg (DImode, operands[1]);
415 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
416 prefer to split up constants early, like this. The testcase in
417 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
418 resulting subreg sets when using the construct from mcore (as of FSF
419 CVS, version -r 1.5), and it believes that the high part (the last one
420 emitted) is the final value. This construct from romp seems more
421 robust, especially considering the head comments from
422 emit_no_conflict_block. */
423 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
424 && ! reload_completed
425 && ! reload_in_progress)
428 rtx op0 = operands[0];
429 rtx op1 = operands[1];
432 emit_move_insn (operand_subword (op0, 0, 1, DImode),
433 operand_subword (op1, 0, 1, DImode));
434 emit_move_insn (operand_subword (op0, 1, 1, DImode),
435 operand_subword (op1, 1, 1, DImode));
436 insns = get_insns ();
439 emit_no_conflict_block (insns, op0, op1, 0, op1);
444 (define_insn "*movdi_insn"
445 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
446 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
447 "register_operand (operands[0], DImode)
448 || register_operand (operands[1], DImode)
449 || operands[1] == const0_rtx"
453 [(set (match_operand:DI 0 "nonimmediate_operand" "")
454 (match_operand:DI 1 "general_operand" ""))]
457 "operands[2] = cris_split_movdx (operands);")
459 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
460 ;; and move.S1 [rx=ry+i],rz
461 ;; Then movs.S1 and movu.S1 for both modes.
463 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
464 ;; FIXME: These could have anonymous mode for operand 0.
466 (define_insn "*mov_side<mode>_biap"
467 [(set (match_operand:BW 0 "register_operand" "=r,r")
469 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
470 (match_operand:SI 2 "const_int_operand" "n,n"))
471 (match_operand:SI 3 "register_operand" "r,r"))))
472 (set (match_operand:SI 4 "register_operand" "=*3,r")
473 (plus:SI (mult:SI (match_dup 1)
476 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
479 move<m> [%4=%3+%1%T2],%0")
481 (define_insn "*mov_sidesisf_biap"
482 [(set (match_operand 0 "register_operand" "=r,r,x,x")
484 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
485 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
486 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
487 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
488 (plus:SI (mult:SI (match_dup 1)
491 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
492 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
495 move.%s0 [%4=%3+%1%T2],%0
497 move [%4=%3+%1%T2],%0")
499 ;; move.S1 [rx=ry+i],rz
500 ;; avoiding move.S1 [ry=ry+i],rz
501 ;; and move.S1 [rz=ry+i],rz
502 ;; Note that "i" is allowed to be a register.
504 (define_insn "*mov_side<mode>"
505 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
507 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
508 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
509 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
510 (plus:SI (match_dup 1)
512 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
514 if ((which_alternative == 0 || which_alternative == 3)
515 && (!CONST_INT_P (operands[2])
516 || INTVAL (operands[2]) > 127
517 || INTVAL (operands[2]) < -128
518 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
519 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
521 if (which_alternative == 4)
522 return "move<m> [%3=%2%S1],%0";
523 return "move<m> [%3=%1%S2],%0";
526 (define_insn "*mov_sidesisf"
527 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
530 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
531 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
532 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
533 (plus:SI (match_dup 1)
535 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
536 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
538 if ((which_alternative == 0
539 || which_alternative == 3
540 || which_alternative == 6
541 || which_alternative == 8)
542 && (!CONST_INT_P (operands[2])
543 || INTVAL (operands[2]) > 127
544 || INTVAL (operands[2]) < -128
545 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
546 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
548 if (which_alternative < 3)
549 return "move.%s0 [%3=%1%S2],%0";
550 if (which_alternative == 7)
551 return "move.%s0 [%3=%2%S1],%0";
552 if (which_alternative == 9)
553 return "move [%3=%2%S1],%0";
554 return "move [%3=%1%S2],%0";
557 ;; Other way around; move to memory.
559 ;; Note that the condition (which for side-effect patterns is usually a
560 ;; call to cris_side_effect_mode_ok), isn't consulted for register
561 ;; allocation preferences -- constraints is the method for that. The
562 ;; drawback is that we can't exclude register allocation to cause
563 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
564 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
565 ;; Instead of that, we recognize and split the cases where dangerous
566 ;; register combinations are spotted: where a register is set in the
567 ;; side-effect, and used in the main insn. We don't handle the case where
568 ;; the set in the main insn overlaps the set in the side-effect; that case
569 ;; must be handled in gcc. We handle just the case where the set in the
570 ;; side-effect overlaps the input operand of the main insn (i.e. just
574 ;; move.s rz,[ry=rx+rw.S]
576 (define_insn "*mov_side<mode>_biap_mem"
577 [(set (mem:BW (plus:SI
578 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
579 (match_operand:SI 1 "const_int_operand" "n,n,n"))
580 (match_operand:SI 2 "register_operand" "r,r,r")))
581 (match_operand:BW 3 "register_operand" "r,r,r"))
582 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
583 (plus:SI (mult:SI (match_dup 0)
586 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
590 move<m> %3,[%4=%2+%0%T1]")
592 (define_insn "*mov_sidesisf_biap_mem"
594 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
595 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
596 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
597 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
598 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
599 (plus:SI (mult:SI (match_dup 0)
602 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
603 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
607 move.%s3 %3,[%4=%2+%0%T1]
610 move %3,[%4=%2+%0%T1]")
612 ;; Split for the case above where we're out of luck with register
613 ;; allocation (again, the condition isn't checked for that), and we end up
614 ;; with the set in the side-effect getting the same register as the input
619 [(set (match_operator
622 (mult:SI (match_operand:SI 0 "register_operand" "")
623 (match_operand:SI 1 "const_int_operand" ""))
624 (match_operand:SI 2 "register_operand" ""))])
625 (match_operand 3 "register_operand" ""))
626 (set (match_operand:SI 4 "register_operand" "")
627 (plus:SI (mult:SI (match_dup 0)
630 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
631 [(set (match_dup 5) (match_dup 3))
632 (set (match_dup 4) (match_dup 2))
634 (plus:SI (mult:SI (match_dup 0)
638 = replace_equiv_address (operands[6],
639 gen_rtx_PLUS (SImode,
640 gen_rtx_MULT (SImode,
645 ;; move.s rx,[ry=rz+i]
646 ;; FIXME: These could have anonymous mode for operand 2.
650 (define_insn "*mov_side<mode>_mem"
652 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
653 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
654 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
655 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
656 (plus:SI (match_dup 0)
658 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
660 if ((which_alternative == 0 || which_alternative == 4)
661 && (!CONST_INT_P (operands[1])
662 || INTVAL (operands[1]) > 127
663 || INTVAL (operands[1]) < -128
664 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
665 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
667 if (which_alternative == 1 || which_alternative == 5)
669 if (which_alternative == 6)
670 return "move.%s2 %2,[%3=%1%S0]";
671 return "move<m> %2,[%3=%0%S1]";
676 (define_insn "*mov_sidesisf_mem"
680 0 "cris_bdap_operand"
681 "%r, r, r,r, r, r,r, R,R, R,R, R")
683 1 "cris_bdap_operand"
684 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
685 (match_operand 2 "register_operand"
686 "r, r, r,r, x, x,x, r,r, r,x, x"))
687 (set (match_operand:SI 3 "register_operand"
688 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
689 (plus:SI (match_dup 0)
691 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
692 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
694 if ((which_alternative == 0 || which_alternative == 4)
695 && (!CONST_INT_P (operands[1])
696 || INTVAL (operands[1]) > 127
697 || INTVAL (operands[1]) < -128
698 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
699 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
701 if (which_alternative == 1
702 || which_alternative == 7
703 || which_alternative == 8
704 || which_alternative == 10)
706 if (which_alternative < 4)
707 return "move.%s2 %2,[%3=%0%S1]";
708 if (which_alternative == 9)
709 return "move.%s2 %2,[%3=%1%S0]";
710 if (which_alternative == 11)
711 return "move %2,[%3=%1%S0]";
712 return "move %2,[%3=%0%S1]";
715 ;; Like the biap case, a split where the set in the side-effect gets the
716 ;; same register as the input register to the main insn, since the
717 ;; condition isn't checked at register allocation.
721 [(set (match_operator
724 (match_operand:SI 0 "cris_bdap_operand" "")
725 (match_operand:SI 1 "cris_bdap_operand" ""))])
726 (match_operand 2 "register_operand" ""))
727 (set (match_operand:SI 3 "register_operand" "")
728 (plus:SI (match_dup 0) (match_dup 1)))])]
729 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
730 [(set (match_dup 4) (match_dup 2))
731 (set (match_dup 3) (match_dup 0))
732 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
735 ;; Clear memory side-effect patterns. It is hard to get to the mode if
736 ;; the MEM was anonymous, so there will be one for each mode.
738 ;; clear.[bwd] [ry=rx+rw.s2]
740 (define_insn "*clear_side<mode>_biap"
741 [(set (mem:BWD (plus:SI
742 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
743 (match_operand:SI 1 "const_int_operand" "n,n"))
744 (match_operand:SI 2 "register_operand" "r,r")))
746 (set (match_operand:SI 3 "register_operand" "=*2,r")
747 (plus:SI (mult:SI (match_dup 0)
750 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
753 clear<m> [%3=%2+%0%T1]")
755 ;; clear.[bwd] [ry=rz+i]
757 (define_insn "*clear_side<mode>"
759 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
760 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
762 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
763 (plus:SI (match_dup 0)
765 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
767 if ((which_alternative == 0 || which_alternative == 3)
768 && (!CONST_INT_P (operands[1])
769 || INTVAL (operands[1]) > 127
770 || INTVAL (operands[1]) < -128
771 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
772 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
774 if (which_alternative == 4)
775 return "clear<m> [%2=%1%S0]";
776 return "clear<m> [%2=%0%S1]";
779 ;; Normal move patterns from SI on.
781 (define_expand "movsi"
783 (match_operand:SI 0 "nonimmediate_operand" "")
784 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
787 /* If the output goes to a MEM, make sure we have zero or a register as
789 if (MEM_P (operands[0])
790 && ! REG_S_P (operands[1])
791 && operands[1] != const0_rtx
792 && can_create_pseudo_p ())
793 operands[1] = force_reg (SImode, operands[1]);
795 /* If we're generating PIC and have an incoming symbol, validize it to a
796 general operand or something that will match a special pattern.
798 FIXME: Do we *have* to recognize anything that would normally be a
799 valid symbol? Can we exclude global PIC addresses with an added
802 && CONSTANT_ADDRESS_P (operands[1])
803 && !cris_valid_pic_const (operands[1]))
805 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);
807 gcc_assert (t != cris_no_symbol);
809 if (! REG_S_P (operands[0]))
811 /* We must have a register as destination for what we're about to
812 do, and for the patterns we generate. */
813 CRIS_ASSERT (can_create_pseudo_p ());
814 operands[1] = force_reg (SImode, operands[1]);
818 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
819 destination register for the symbol. It might not be
820 worth it. Measure. */
821 current_function_uses_pic_offset_table = 1;
822 if (t == cris_gotrel_symbol)
824 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
825 "move.d (const (plus (unspec [sym]
826 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN" */
827 rtx tem, rm, rn = operands[0];
828 rtx sym = GET_CODE (operands[1]) != CONST
829 ? operands[1] : get_related_value (operands[1]);
830 HOST_WIDE_INT offs = get_integer_term (operands[1]);
832 gcc_assert (can_create_pseudo_p ());
833 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
836 tem = plus_constant (tem, offs);
837 rm = gen_reg_rtx (Pmode);
838 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
839 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
840 rn, 0, OPTAB_LIB_WIDEN) != rn)
841 internal_error ("expand_binop failed in movsi gotrel");
844 else if (t == cris_got_symbol)
846 /* Change a "move.d sym,rN" into (allocate register rM, rO)
847 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
848 "add.d rPIC,rM,rO", "move.d [rO],rN" with
849 the memory access marked as read-only. */
850 rtx tem, mem, rm, ro, rn = operands[0];
851 gcc_assert (can_create_pseudo_p ());
852 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
853 CRIS_UNSPEC_GOTREAD);
854 rm = gen_reg_rtx (Pmode);
855 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
856 ro = gen_reg_rtx (Pmode);
857 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
858 ro, 0, OPTAB_LIB_WIDEN) != ro)
859 internal_error ("expand_binop failed in movsi got");
860 mem = gen_rtx_MEM (Pmode, ro);
862 /* This MEM doesn't alias anything. Whether it
863 aliases other same symbols is unimportant. */
864 set_mem_alias_set (mem, new_alias_set ());
865 MEM_NOTRAP_P (mem) = 1;
866 MEM_READONLY_P (mem) = 1;
867 emit_move_insn (rn, mem);
872 /* We get here when we have to change something that would
873 be recognizable if it wasn't PIC. A ``sym'' is ok for
874 PIC symbols both with and without a GOT entry. And ``sym
875 + offset'' is ok for local symbols, so the only thing it
876 could be, is a global symbol with an offset. Check and
878 rtx reg = gen_reg_rtx (Pmode);
879 rtx sym = get_related_value (operands[1]);
880 HOST_WIDE_INT offs = get_integer_term (operands[1]);
882 gcc_assert (can_create_pseudo_p ()
883 && t == cris_got_symbol_needing_fixup
884 && sym != NULL_RTX && offs != 0);
886 emit_move_insn (reg, sym);
887 if (expand_binop (SImode, add_optab, reg,
888 GEN_INT (offs), operands[0], 0,
889 OPTAB_LIB_WIDEN) != operands[0])
890 internal_error ("expand_binop failed in movsi got+offs");
897 (define_insn "*movsi_got_load"
898 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
900 "move.d $pc,%:\;sub.d .:GOTOFF,%:"
901 [(set_attr "cc" "clobber")])
903 (define_insn "*movsi_internal"
905 (match_operand:SI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
906 ;; Note that we prefer not to use the S alternative (if for some reason
907 ;; it competes with others), but g matches S.
908 (match_operand:SI 1 "general_operand" "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
911 /* Better to have c-switch here; it is worth it to optimize the size of
912 move insns. The alternative would be to try to find more constraint
913 letters. FIXME: Check again. It seems this could shrink a bit. */
914 switch (which_alternative)
921 return "move.d %1,%0";
927 return "move %d1,%0";
934 /* Constants -32..31 except 0. */
936 return "moveq %1,%0";
938 /* We can win a little on constants -32768..-33, 32..65535. */
940 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
942 if (INTVAL (operands[1]) < 256)
943 return "movu.b %1,%0";
944 return "movu.w %1,%0";
946 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
948 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
949 return "movs.b %1,%0";
950 return "movs.w %1,%0";
952 return "move.d %1,%0";
956 rtx tem = operands[1];
957 gcc_assert (GET_CODE (tem) == CONST);
959 if (GET_CODE (tem) == PLUS
960 && GET_CODE (XEXP (tem, 0)) == UNSPEC
961 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
962 && CONST_INT_P (XEXP (tem, 1)))
964 gcc_assert (GET_CODE (tem) == UNSPEC);
965 switch (XINT (tem, 1))
967 case CRIS_UNSPEC_GOTREAD:
968 case CRIS_UNSPEC_PLTGOTREAD:
969 /* Using sign-extend mostly to be consistent with the
970 indexed addressing mode. */
972 return "movs.w %1,%0";
973 case CRIS_UNSPEC_GOTREL:
974 case CRIS_UNSPEC_PLT:
975 return "move.d %1,%0";
982 return "BOGUS: %1 to %0";
985 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
986 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
988 ;; Extend operations with side-effect from mem to register, using
989 ;; MOVS/MOVU. These are from mem to register only.
995 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
996 ;; HImode by itself? Perhaps use only anonymous modes?
998 (define_insn "*ext_sideqihi_biap"
999 [(set (match_operand:HI 0 "register_operand" "=r,r")
1001 5 "cris_extend_operator"
1003 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1004 (match_operand:SI 2 "const_int_operand" "n,n"))
1005 (match_operand:SI 3 "register_operand" "r,r")))]))
1006 (set (match_operand:SI 4 "register_operand" "=*3,r")
1007 (plus:SI (mult:SI (match_dup 1)
1010 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1013 mov%e5.%m5 [%4=%3+%1%T2],%0")
1015 (define_insn "*ext_side<mode>si_biap"
1016 [(set (match_operand:SI 0 "register_operand" "=r,r")
1018 5 "cris_extend_operator"
1020 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1021 (match_operand:SI 2 "const_int_operand" "n,n"))
1022 (match_operand:SI 3 "register_operand" "r,r")))]))
1023 (set (match_operand:SI 4 "register_operand" "=*3,r")
1024 (plus:SI (mult:SI (match_dup 1)
1027 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1030 mov%e5<m> [%4=%3+%1%T2],%0")
1032 ;; Same but [rx=ry+i]
1036 (define_insn "*ext_sideqihi"
1037 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1039 4 "cris_extend_operator"
1041 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1042 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1043 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1044 (plus:SI (match_dup 1)
1046 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1048 if ((which_alternative == 0 || which_alternative == 3)
1049 && (!CONST_INT_P (operands[2])
1050 || INTVAL (operands[2]) > 127
1051 || INTVAL (operands[2]) < -128
1052 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1053 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1055 if (which_alternative == 4)
1056 return "mov%e4.%m4 [%3=%2%S1],%0";
1057 return "mov%e4.%m4 [%3=%1%S2],%0";
1060 (define_insn "*ext_side<mode>si"
1061 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1063 4 "cris_extend_operator"
1065 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1066 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1067 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1068 (plus:SI (match_dup 1)
1070 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1072 if ((which_alternative == 0 || which_alternative == 3)
1073 && (!CONST_INT_P (operands[2])
1074 || INTVAL (operands[2]) > 127
1075 || INTVAL (operands[2]) < -128
1076 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1077 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1079 if (which_alternative == 4)
1080 return "mov%e4<m> [%3=%2%S1],%0";
1081 return "mov%e4<m> [%3=%1%S2],%0";
1084 ;; FIXME: See movsi.
1086 (define_insn "movhi"
1088 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1089 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1092 switch (which_alternative)
1099 return "move.w %1,%0";
1102 return "move %1,%0";
1106 return "clear.w %0";
1108 return "moveq %1,%0";
1111 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1113 if (INTVAL (operands[1]) > 0)
1114 return "movu.b %1,%0";
1115 return "movs.b %1,%0";
1117 return "move.w %1,%0";
1119 return "movEq %b1,%0";
1121 return "BOGUS: %1 to %0";
1124 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1125 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1127 (define_insn "movstricthi"
1130 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1131 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1142 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1144 (define_expand "reload_in<mode>"
1145 [(set (match_operand:BW 2 "register_operand" "=r")
1146 (match_operand:BW 1 "memory_operand" "m"))
1147 (set (match_operand:BW 0 "register_operand" "=x")
1152 (define_expand "reload_out<mode>"
1153 [(set (match_operand:BW 2 "register_operand" "=&r")
1154 (match_operand:BW 1 "register_operand" "x"))
1155 (set (match_operand:BW 0 "memory_operand" "=m")
1160 (define_insn "movqi"
1161 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1162 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1177 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1178 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1180 (define_insn "movstrictqi"
1181 [(set (strict_low_part
1182 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1183 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1194 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1196 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1197 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1198 ;; all ones); the worthwhile one is "0.0".
1199 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1201 (define_insn "movsf"
1202 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1203 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1220 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1222 ;; Note that the memory layout of the registers is the reverse of that
1223 ;; of the standard patterns "load_multiple" and "store_multiple".
1224 (define_insn "*cris_load_multiple"
1225 [(match_parallel 0 "cris_load_multiple_op"
1226 [(set (match_operand:SI 1 "register_operand" "=r,r")
1227 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1230 [(set_attr "cc" "none")
1231 (set_attr "slottable" "yes,no")
1232 ;; Not true, but setting the length to 0 causes return sequences (ret
1233 ;; movem) to have the cost they had when (return) included the movem
1234 ;; and reduces the performance penalty taken for needing to emit an
1235 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1236 ;; FIXME: temporary change until all insn lengths are correctly
1237 ;; described. FIXME: have better target control over bb-reorder.
1238 (set_attr "length" "0")])
1240 (define_insn "*cris_store_multiple"
1241 [(match_parallel 0 "cris_store_multiple_op"
1242 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1243 (match_operand:SI 1 "register_operand" "r,r"))])]
1246 [(set_attr "cc" "none")
1247 (set_attr "slottable" "yes,no")])
1250 ;; Sign- and zero-extend insns with standard names.
1251 ;; Those for integer source operand are ordered with the widest source
1256 (define_insn "extendsidi2"
1257 [(set (match_operand:DI 0 "register_operand" "=r")
1258 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1260 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1262 (define_insn "extend<mode>di2"
1263 [(set (match_operand:DI 0 "register_operand" "=r")
1264 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1266 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1268 (define_insn "extend<mode>si2"
1269 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1270 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1273 [(set_attr "slottable" "yes,yes,no")])
1275 ;; To do a byte->word extension, extend to dword, exept that the top half
1276 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1278 (define_insn "extendqihi2"
1279 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1280 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1283 [(set_attr "slottable" "yes,yes,no")])
1286 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1287 ;; specify them here.
1289 (define_insn "zero_extend<mode>si2"
1290 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1292 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1295 [(set_attr "slottable" "yes,yes,no")])
1297 ;; Same comment as sign-extend QImode to HImode above applies.
1299 (define_insn "zero_extendqihi2"
1300 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1302 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1305 [(set_attr "slottable" "yes,yes,no")])
1307 ;; All kinds of arithmetic and logical instructions.
1309 ;; First, anonymous patterns to match addressing modes with
1312 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1316 (define_insn "*op_side<mode>_biap"
1317 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1319 6 "cris_orthogonal_operator"
1320 [(match_operand:BWD 1 "register_operand" "0,0")
1322 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1323 (match_operand:SI 3 "const_int_operand" "n,n"))
1324 (match_operand:SI 4 "register_operand" "r,r")))]))
1325 (set (match_operand:SI 5 "register_operand" "=*4,r")
1326 (plus:SI (mult:SI (match_dup 2)
1329 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1332 %x6<m> [%5=%4+%2%T3],%0")
1334 ;; [rx=ry+i] ([%4=%2+%3])
1336 (define_insn "*op_side<mode>"
1337 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1339 5 "cris_orthogonal_operator"
1340 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1342 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1343 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1344 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1345 (plus:SI (match_dup 2)
1347 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1349 if ((which_alternative == 0 || which_alternative == 3)
1350 && (!CONST_INT_P (operands[3])
1351 || INTVAL (operands[3]) > 127
1352 || INTVAL (operands[3]) < -128
1353 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1354 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1356 if (which_alternative == 4)
1357 return "%x5.%s0 [%4=%3%S2],%0";
1358 return "%x5<m> [%4=%2%S3],%0";
1361 ;; To match all cases for commutative operations we may have to have the
1362 ;; following pattern for add, or & and. I do not know really, but it does
1363 ;; not break anything.
1365 ;; FIXME: This really ought to be checked.
1367 ;; op.S [rx=ry+I],rz;
1371 (define_insn "*op_swap_side<mode>_biap"
1372 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1374 6 "cris_commutative_orth_op"
1376 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1377 (match_operand:SI 3 "const_int_operand" "n,n"))
1378 (match_operand:SI 4 "register_operand" "r,r")))
1379 (match_operand:BWD 1 "register_operand" "0,0")]))
1380 (set (match_operand:SI 5 "register_operand" "=*4,r")
1381 (plus:SI (mult:SI (match_dup 2)
1384 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1387 %x6<m> [%5=%4+%2%T3],%0")
1389 ;; [rx=ry+i] ([%4=%2+%3])
1390 ;; FIXME: These could have anonymous mode for operand 0.
1394 (define_insn "*op_swap_side<mode>"
1395 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1397 5 "cris_commutative_orth_op"
1399 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1400 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1401 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1402 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1403 (plus:SI (match_dup 2)
1405 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1407 if ((which_alternative == 0 || which_alternative == 3)
1408 && (!CONST_INT_P (operands[3])
1409 || INTVAL (operands[3]) > 127
1410 || INTVAL (operands[3]) < -128
1411 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1412 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1414 if (which_alternative == 4)
1415 return "%x5<m> [%4=%3%S2],%0";
1416 return "%x5<m> [%4=%2%S3],%0";
1419 ;; Add operations, standard names.
1421 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1422 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1424 (define_insn "adddi3"
1425 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1426 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1427 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1430 addq %2,%M0\;ax\;addq 0,%H0
1431 subq %n2,%M0\;ax\;subq 0,%H0
1432 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1433 add.d %M2,%M0\;ax\;add.d %H2,%H0
1434 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1436 (define_insn "addsi3"
1437 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1439 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1440 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1442 ;; The last constraint is due to that after reload, the '%' is not
1443 ;; honored, and canonicalization doesn't care about keeping the same
1444 ;; register as in destination. This will happen after insn splitting.
1445 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1449 switch (which_alternative)
1453 return "add.d %2,%0";
1455 return "addq %2,%0";
1457 return "subq %n2,%0";
1459 /* 'Known value', but not in -63..63.
1460 Check if addu/subu may be used. */
1461 if (INTVAL (operands[2]) > 0)
1463 if (INTVAL (operands[2]) < 256)
1464 return "addu.b %2,%0";
1465 if (INTVAL (operands[2]) < 65536)
1466 return "addu.w %2,%0";
1470 if (INTVAL (operands[2]) >= -255)
1471 return "subu.b %n2,%0";
1472 if (INTVAL (operands[2]) >= -65535)
1473 return "subu.w %n2,%0";
1475 return "add.d %2,%0";
1478 rtx tem = operands[2];
1479 gcc_assert (GET_CODE (tem) == CONST);
1480 tem = XEXP (tem, 0);
1481 if (GET_CODE (tem) == PLUS
1482 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1483 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1484 && CONST_INT_P (XEXP (tem, 1)))
1485 tem = XEXP (tem, 0);
1486 gcc_assert (GET_CODE (tem) == UNSPEC);
1487 switch (XINT (tem, 1))
1489 case CRIS_UNSPEC_GOTREAD:
1490 case CRIS_UNSPEC_PLTGOTREAD:
1491 /* Using sign-extend mostly to be consistent with the
1492 indexed addressing mode. */
1494 return "adds.w %2,%0";
1496 case CRIS_UNSPEC_PLT:
1497 case CRIS_UNSPEC_GOTREL:
1498 return "add.d %2,%0";
1504 return "add.d %2,%0";
1506 return "add.d %2,%1,%0";
1508 return "add.d %1,%0";
1510 return "BOGUS addsi %2+%1 to %0";
1513 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1515 (define_insn "addhi3"
1516 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1517 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1518 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1527 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1528 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1530 (define_insn "addqi3"
1531 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1532 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1533 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1543 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1544 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1548 ;; Note that because of insn canonicalization these will *seldom* but
1549 ;; rarely be used with a known constant as an operand.
1551 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1552 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1554 (define_insn "subdi3"
1555 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1556 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1557 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1560 subq %2,%M0\;ax\;subq 0,%H0
1561 addq %n2,%M0\;ax\;addq 0,%H0
1562 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1563 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1564 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1566 (define_insn "subsi3"
1567 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1569 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1570 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1573 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1574 ;; But then again, %2 should not be negative.
1585 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1587 (define_insn "sub<mode>3"
1588 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
1589 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
1590 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
1599 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1600 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1602 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
1603 ;; Although these perform sign/zero-extension to SImode, they are
1604 ;; equally applicable for the HImode case.
1605 ;; FIXME: Check; GCC should handle the widening.
1606 ;; Note that these must be located after the normal add/sub patterns,
1607 ;; so not to get constants into any less specific operands.
1609 ;; Extend with add/sub and side-effect.
1611 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
1613 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
1616 ;; FIXME: GCC should widen.
1618 (define_insn "*extopqihi_side_biap"
1619 [(set (match_operand:HI 0 "register_operand" "=r,r")
1621 6 "cris_additive_operand_extend_operator"
1622 [(match_operand:HI 1 "register_operand" "0,0")
1624 7 "cris_extend_operator"
1626 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1627 (match_operand:SI 3 "const_int_operand" "n,n"))
1628 (match_operand:SI 4 "register_operand" "r,r")))])]))
1629 (set (match_operand:SI 5 "register_operand" "=*4,r")
1630 (plus:SI (mult:SI (match_dup 2)
1633 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1636 %x6%e7.%m7 [%5=%4+%2%T3],%0")
1638 (define_insn "*extop<mode>si_side_biap"
1639 [(set (match_operand:SI 0 "register_operand" "=r,r")
1641 6 "cris_operand_extend_operator"
1642 [(match_operand:SI 1 "register_operand" "0,0")
1644 7 "cris_extend_operator"
1646 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1647 (match_operand:SI 3 "const_int_operand" "n,n"))
1648 (match_operand:SI 4 "register_operand" "r,r")))])]))
1649 (set (match_operand:SI 5 "register_operand" "=*4,r")
1650 (plus:SI (mult:SI (match_dup 2)
1653 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
1654 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1657 %x6%e7<m> [%5=%4+%2%T3],%0")
1664 (define_insn "*extopqihi_side"
1665 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1667 5 "cris_additive_operand_extend_operator"
1668 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
1670 6 "cris_extend_operator"
1672 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1673 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
1675 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1676 (plus:SI (match_dup 2)
1678 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1680 if ((which_alternative == 0 || which_alternative == 3)
1681 && (!CONST_INT_P (operands[3])
1682 || INTVAL (operands[3]) > 127
1683 || INTVAL (operands[3]) < -128
1684 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1685 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1687 if (which_alternative == 4)
1688 return "%x5%E6.%m6 [%4=%3%S2],%0";
1689 return "%x5%E6.%m6 [%4=%2%S3],%0";
1692 (define_insn "*extop<mode>si_side"
1693 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1695 5 "cris_operand_extend_operator"
1696 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
1698 6 "cris_extend_operator"
1700 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1701 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
1703 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1704 (plus:SI (match_dup 2)
1706 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
1707 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1709 if ((which_alternative == 0 || which_alternative == 3)
1710 && (!CONST_INT_P (operands[3])
1711 || INTVAL (operands[3]) > 127
1712 || INTVAL (operands[3]) < -128
1713 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1714 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1716 if (which_alternative == 4)
1717 return "%x5%E6<m> [%4=%3%S2],%0";
1718 return "%x5%E6<m> [%4=%2%S3],%0";
1722 ;; As with op.S we may have to add special pattern to match commuted
1723 ;; operands to adds/addu and bound
1725 ;; adds/addu/bound [rx=ry+rz.S]
1728 ;; FIXME: GCC should widen.
1730 (define_insn "*extopqihi_swap_side_biap"
1731 [(set (match_operand:HI 0 "register_operand" "=r,r")
1734 6 "cris_extend_operator"
1736 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1737 (match_operand:SI 3 "const_int_operand" "n,n"))
1738 (match_operand:SI 4 "register_operand" "r,r")))])
1739 (match_operand:HI 1 "register_operand" "0,0")))
1740 (set (match_operand:SI 5 "register_operand" "=*4,r")
1741 (plus:SI (mult:SI (match_dup 2)
1744 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1747 add%e6.b [%5=%4+%2%T3],%0")
1749 (define_insn "*extop<mode>si_swap_side_biap"
1750 [(set (match_operand:SI 0 "register_operand" "=r,r")
1752 7 "cris_plus_or_bound_operator"
1754 6 "cris_extend_operator"
1756 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1757 (match_operand:SI 3 "const_int_operand" "n,n"))
1758 (match_operand:SI 4 "register_operand" "r,r")))])
1759 (match_operand:SI 1 "register_operand" "0,0")]))
1760 (set (match_operand:SI 5 "register_operand" "=*4,r")
1761 (plus:SI (mult:SI (match_dup 2)
1764 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
1765 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1768 %x7%E6<m> [%5=%4+%2%T3],%0")
1771 ;; FIXME: GCC should widen.
1775 (define_insn "*extopqihi_swap_side"
1776 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1779 5 "cris_extend_operator"
1781 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1782 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
1783 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
1784 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1785 (plus:SI (match_dup 2)
1787 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1789 if ((which_alternative == 0 || which_alternative == 3)
1790 && (!CONST_INT_P (operands[3])
1791 || INTVAL (operands[3]) > 127
1792 || INTVAL (operands[3]) < -128
1793 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1794 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1796 if (which_alternative == 4)
1797 return "add%e5.b [%4=%3%S2],%0";
1798 return "add%e5.b [%4=%2%S3],%0";
1801 (define_insn "*extop<mode>si_swap_side"
1802 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1804 6 "cris_plus_or_bound_operator"
1806 5 "cris_extend_operator"
1808 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1809 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
1810 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
1811 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1812 (plus:SI (match_dup 2)
1814 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
1815 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1817 if ((which_alternative == 0 || which_alternative == 3)
1818 && (!CONST_INT_P (operands[3])
1819 || INTVAL (operands[3]) > 127
1820 || INTVAL (operands[3]) < -128
1821 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1822 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1824 if (which_alternative == 4)
1825 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
1826 return "%x6%E5<m> [%4=%2%S3],%0";
1829 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
1832 ;; FIXME: GCC should widen.
1834 (define_insn "*extopqihi"
1835 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1837 3 "cris_additive_operand_extend_operator"
1838 [(match_operand:HI 1 "register_operand" "0,0,0,r")
1840 4 "cris_extend_operator"
1841 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
1842 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
1843 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
1848 %x3%E4.%m4 %2,%1,%0"
1849 [(set_attr "slottable" "yes,yes,no,no")
1850 (set_attr "cc" "clobber")])
1854 (define_insn "*extop<mode>si"
1855 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1857 3 "cris_operand_extend_operator"
1858 [(match_operand:SI 1 "register_operand" "0,0,0,r")
1860 4 "cris_extend_operator"
1861 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
1862 "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
1863 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
1864 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
1870 [(set_attr "slottable" "yes,yes,no,no")])
1873 ;; As with the side-effect patterns, may have to have swapped operands for add.
1874 ;; FIXME: *should* be redundant to gcc.
1878 (define_insn "*extopqihi_swap"
1879 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1882 3 "cris_extend_operator"
1883 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
1884 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
1885 "operands[1] != frame_pointer_rtx"
1891 [(set_attr "slottable" "yes,yes,no,no")
1892 (set_attr "cc" "clobber")])
1894 (define_insn "*extop<mode>si_swap"
1895 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1897 4 "cris_plus_or_bound_operator"
1899 3 "cris_extend_operator"
1900 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
1901 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
1902 "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
1903 && operands[1] != frame_pointer_rtx"
1909 [(set_attr "slottable" "yes,yes,no,no")])
1911 ;; This is the special case when we use what corresponds to the
1912 ;; instruction above in "casesi". Do *not* change it to use the generic
1913 ;; pattern and "REG 15" as pc; I did that and it led to madness and
1914 ;; maintenance problems: Instead of (as imagined) recognizing and removing
1915 ;; or replacing this pattern with something simpler, other variant
1916 ;; patterns were recognized or combined, including some prefix variants
1917 ;; where the value in pc is not that of the next instruction (which means
1918 ;; this instruction actually *is* special and *should* be marked as such).
1919 ;; When switching from the "generic pattern match" approach to this simpler
1920 ;; approach, there were insignificant differences in gcc, ipps and
1921 ;; product code, somehow due to scratching reload behind the ear or
1922 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
1923 ;; product code became .001% smaller but "looked better". The testcase
1924 ;; "ipps" was just different at register allocation).
1926 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
1927 ;; pattern with the default-label as the else, with the "if" being
1928 ;; index-is-less-than the max number of cases plus one. The default-label
1929 ;; is attached to the end of the case-table at time of output.
1931 (define_insn "*casesi_adds_w"
1934 (ltu (match_operand:SI 0 "register_operand" "r")
1935 (match_operand:SI 1 "const_int_operand" "n"))
1936 (plus:SI (sign_extend:SI
1938 (plus:SI (mult:SI (match_dup 0) (const_int 2))
1941 (label_ref (match_operand 2 "" ""))))
1942 (use (label_ref (match_operand 3 "" "")))]
1944 "operands[0] != frame_pointer_rtx"
1946 "adds.w [$pc+%0.w],$pc"
1947 [(set_attr "cc" "clobber")])
1949 ;; Multiply instructions.
1951 ;; Sometimes powers of 2 (which are normally canonicalized to a
1952 ;; left-shift) appear here, as a result of address reloading.
1953 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
1955 ;; FIXME: This may be unnecessary now.
1956 ;; Explicitly named for convenience of having a gen_... function.
1958 (define_insn "addi_mul"
1959 [(set (match_operand:SI 0 "register_operand" "=r")
1961 (match_operand:SI 1 "register_operand" "%0")
1962 (match_operand:SI 2 "const_int_operand" "n")))]
1963 "operands[0] != frame_pointer_rtx
1964 && operands[1] != frame_pointer_rtx
1965 && CONST_INT_P (operands[2])
1966 && (INTVAL (operands[2]) == 2
1967 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
1968 || INTVAL (operands[2]) == 5)"
1970 if (INTVAL (operands[2]) == 2)
1972 else if (INTVAL (operands[2]) == 4)
1974 else if (INTVAL (operands[2]) == 3)
1975 return "addi %0.w,%0";
1976 else if (INTVAL (operands[2]) == 5)
1977 return "addi %0.d,%0";
1978 return "BAD: adr_mulsi: %0=%1*%2";
1980 [(set_attr "slottable" "yes")
1981 ;; No flags are changed if this insn is "addi", but it does not seem
1982 ;; worth the trouble to distinguish that to the lslq cases.
1983 (set_attr "cc" "clobber")])
1985 ;; The addi insn as it is normally used.
1987 (define_insn "*addi"
1988 [(set (match_operand:SI 0 "register_operand" "=r")
1990 (mult:SI (match_operand:SI 2 "register_operand" "r")
1991 (match_operand:SI 3 "const_int_operand" "n"))
1992 (match_operand:SI 1 "register_operand" "0")))]
1993 "operands[0] != frame_pointer_rtx
1994 && operands[1] != frame_pointer_rtx
1995 && CONST_INT_P (operands[3])
1996 && (INTVAL (operands[3]) == 1
1997 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
1999 [(set_attr "slottable" "yes")
2000 (set_attr "cc" "none")])
2002 ;; The mstep instruction. Probably not useful by itself; it's to
2003 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2006 (define_insn "mstep_shift"
2007 [(set (match_operand:SI 0 "register_operand" "=r")
2009 (lt:SI (cc0) (const_int 0))
2010 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2012 (match_operand:SI 2 "register_operand" "r"))
2013 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2017 [(set_attr "slottable" "yes")])
2019 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2020 ;; to canonicalize the multiplications.
2022 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2024 (define_insn "mstep_mul"
2025 [(set (match_operand:SI 0 "register_operand" "=r")
2027 (lt:SI (cc0) (const_int 0))
2028 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2030 (match_operand:SI 2 "register_operand" "r"))
2031 (mult:SI (match_operand:SI 3 "register_operand" "0")
2033 "operands[0] != frame_pointer_rtx
2034 && operands[1] != frame_pointer_rtx
2035 && operands[2] != frame_pointer_rtx
2036 && operands[3] != frame_pointer_rtx"
2038 [(set_attr "slottable" "yes")])
2040 (define_insn "<u>mul<s><mode>3"
2041 [(set (match_operand:WD 0 "register_operand" "=r")
2043 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2044 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2045 (clobber (match_scratch:SI 3 "=h"))]
2046 "TARGET_HAS_MUL_INSNS"
2047 "%!mul<su><mm> %2,%0"
2048 [(set (attr "slottable")
2049 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2051 (const_string "yes")))
2052 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2053 ;; For muls.b, this really extends to SImode, so cc should be
2054 ;; considered clobbered.
2055 ;; For muls.w, it's just N unusable here, but let's be safe.
2056 (set_attr "cc" "clobber")])
2058 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2059 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2060 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2061 ;; Inspection of optab code shows that there must be only one widening
2062 ;; multiplication per mode widened to.
2064 (define_insn "mulsi3"
2065 [(set (match_operand:SI 0 "register_operand" "=r")
2066 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2067 (match_operand:SI 2 "register_operand" "r")))
2068 (clobber (match_scratch:SI 3 "=h"))]
2069 "TARGET_HAS_MUL_INSNS"
2071 [(set (attr "slottable")
2072 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2074 (const_string "yes")))
2075 ;; Just N unusable here, but let's be safe.
2076 (set_attr "cc" "clobber")])
2078 ;; A few multiply variations.
2080 ;; When needed, we can get the high 32 bits from the overflow
2081 ;; register. We don't care to split and optimize these.
2083 ;; Note that cc0 is still valid after the move-from-overflow-register
2084 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2086 (define_insn "<u>mulsidi3"
2087 [(set (match_operand:DI 0 "register_operand" "=r")
2089 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2090 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2091 (clobber (match_scratch:SI 3 "=h"))]
2092 "TARGET_HAS_MUL_INSNS"
2093 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2095 ;; These two patterns may be expressible by other means, perhaps by making
2096 ;; [u]?mulsidi3 a define_expand.
2098 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2099 ;; cause a move into the clobbered register *before* the insn, then
2100 ;; after the insn, mof is moved too, rather than the clobber assigned
2101 ;; the last mof target. This became apparent when making MOF and SRP
2102 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2103 ;; Because these patterns are used in division by constants, that damage
2104 ;; is visible (ipps regression tests). Therefore the last two
2105 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2106 ;; punished by force of one "?". Check code from "int d (int a) {return
2107 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2109 (define_insn "<su>mulsi3_highpart"
2110 [(set (match_operand:SI 0 "nonimmediate_operand" "=h,h,?r,?r")
2114 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2115 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2117 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2118 "TARGET_HAS_MUL_INSNS"
2122 %!mul<su>.d %2,%1\;move $mof,%0
2123 %!mul<su>.d %1,%2\;move $mof,%0"
2124 [(set_attr "slottable" "yes,yes,no,no")
2125 (set_attr "cc" "clobber")])
2127 ;; Divide and modulus instructions. CRIS only has a step instruction.
2129 (define_insn "dstep_shift"
2130 [(set (match_operand:SI 0 "register_operand" "=r")
2132 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2134 (match_operand:SI 2 "register_operand" "r"))
2135 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2137 (match_operand:SI 4 "register_operand" "2"))
2138 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2142 [(set_attr "slottable" "yes")])
2144 ;; Here's a variant with mult instead of ashift.
2146 ;; FIXME: This should be investigated. Which one matches through combination?
2148 (define_insn "dstep_mul"
2149 [(set (match_operand:SI 0 "register_operand" "=r")
2151 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2153 (match_operand:SI 2 "register_operand" "r"))
2154 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2156 (match_operand:SI 4 "register_operand" "2"))
2157 (mult:SI (match_operand:SI 5 "register_operand" "0")
2159 "operands[0] != frame_pointer_rtx
2160 && operands[1] != frame_pointer_rtx
2161 && operands[2] != frame_pointer_rtx
2162 && operands[3] != frame_pointer_rtx"
2164 [(set_attr "slottable" "yes")])
2166 ;; Logical operators.
2170 ;; There is no use in defining "anddi3", because gcc can expand this by
2171 ;; itself, and make reasonable code without interference.
2173 ;; If the first operand is memory or a register and is the same as the
2174 ;; second operand, and the third operand is -256 or -65536, we can use
2175 ;; CLEAR instead. Or, if the first operand is a register, and the third
2176 ;; operand is 255 or 65535, we can zero_extend.
2177 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2178 ;; to be common enough to be worthwhile.
2179 ;; FIXME: This should be made obsolete.
2181 (define_expand "andsi3"
2182 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2183 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2184 (match_operand:SI 2 "general_operand" "")))]
2187 if (! (CONST_INT_P (operands[2])
2188 && (((INTVAL (operands[2]) == -256
2189 || INTVAL (operands[2]) == -65536)
2190 && rtx_equal_p (operands[1], operands[0]))
2191 || ((INTVAL (operands[2]) == 255
2192 || INTVAL (operands[2]) == 65535)
2193 && REG_P (operands[0])))))
2195 /* Make intermediate steps if operand0 is not a register or
2196 operand1 is not a register, and hope that the reload pass will
2197 make something useful out of it. Note that the operands are
2198 *not* canonicalized. For the moment, I chicken out on this,
2199 because all or most ports do not describe 'and' with
2200 canonicalized operands, and I seem to remember magic in reload,
2201 checking that operand1 has constraint '%0', in which case
2202 operand0 and operand1 must have similar predicates.
2203 FIXME: Investigate. */
2204 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2205 rtx reg1 = operands[1];
2209 emit_move_insn (reg0, reg1);
2213 emit_insn (gen_rtx_SET (SImode, reg0,
2214 gen_rtx_AND (SImode, reg1, operands[2])));
2216 /* Make sure we get the right *final* destination. */
2217 if (! REG_P (operands[0]))
2218 emit_move_insn (operands[0], reg0);
2224 ;; Some special cases of andsi3.
2226 (define_insn "*andsi_movu"
2227 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2228 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2229 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2230 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2231 && !side_effects_p (operands[1])"
2233 [(set_attr "slottable" "yes,yes,no")])
2235 (define_insn "*andsi_clear"
2236 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2237 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2238 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2239 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2240 && !side_effects_p (operands[0])"
2248 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2249 (set_attr "cc" "none")])
2251 ;; This is a catch-all pattern, taking care of everything that was not
2252 ;; matched in the insns above.
2254 ;; Sidenote: the tightening from "nonimmediate_operand" to
2255 ;; "register_operand" for operand 1 actually increased the register
2256 ;; pressure (worse code). That will hopefully change with an
2257 ;; improved reload pass.
2259 (define_insn "*expanded_andsi"
2260 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2261 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2262 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2270 [(set_attr "slottable" "yes,yes,yes,no,no")])
2272 ;; For both QI and HI we may use the quick patterns. This results in
2273 ;; useless condition codes, but that is used rarely enough for it to
2274 ;; normally be a win (could check ahead for use of cc0, but seems to be
2275 ;; more pain than win).
2277 ;; FIXME: See note for andsi3
2279 (define_expand "andhi3"
2280 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2281 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2282 (match_operand:HI 2 "general_operand" "")))]
2285 if (! (CONST_INT_P (operands[2])
2286 && (((INTVAL (operands[2]) == -256
2287 || INTVAL (operands[2]) == 65280)
2288 && rtx_equal_p (operands[1], operands[0]))
2289 || (INTVAL (operands[2]) == 255
2290 && REG_P (operands[0])))))
2292 /* See comment for andsi3. */
2293 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2294 rtx reg1 = operands[1];
2298 emit_move_insn (reg0, reg1);
2302 emit_insn (gen_rtx_SET (HImode, reg0,
2303 gen_rtx_AND (HImode, reg1, operands[2])));
2305 /* Make sure we get the right destination. */
2306 if (! REG_P (operands[0]))
2307 emit_move_insn (operands[0], reg0);
2313 ;; Some fast andhi3 special cases.
2315 (define_insn "*andhi_movu"
2316 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2317 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2319 "!side_effects_p (operands[1])"
2321 [(set_attr "slottable" "yes,yes,no")])
2323 (define_insn "*andhi_clear"
2324 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2325 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2327 "!side_effects_p (operands[0])"
2329 [(set_attr "slottable" "yes,yes,no")
2330 (set_attr "cc" "none")])
2332 ;; Catch-all andhi3 pattern.
2334 (define_insn "*expanded_andhi"
2335 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2336 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2337 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2339 ;; Sidenote: the tightening from "general_operand" to
2340 ;; "register_operand" for operand 1 actually increased the register
2341 ;; pressure (worse code). That will hopefully change with an
2342 ;; improved reload pass.
2353 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2354 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2356 ;; A strict_low_part pattern.
2358 (define_insn "*andhi_lowpart"
2359 [(set (strict_low_part
2360 (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
2361 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
2362 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2371 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2372 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2374 (define_insn "andqi3"
2375 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2376 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2377 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2386 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2387 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2389 (define_insn "*andqi_lowpart"
2390 [(set (strict_low_part
2391 (match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
2392 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
2393 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2401 [(set_attr "slottable" "yes,yes,yes,no,no")
2402 (set_attr "cc" "normal,normal,clobber,normal,normal")])
2406 ;; Same comment as anddi3 applies here - no need for such a pattern.
2408 ;; It seems there's no need to jump through hoops to get good code such as
2411 (define_insn "iorsi3"
2412 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
2413 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
2414 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
2423 [(set_attr "slottable" "yes,yes,yes,no,no,no")
2424 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2426 (define_insn "iorhi3"
2427 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2428 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2429 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2439 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2440 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2442 (define_insn "iorqi3"
2443 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2444 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2445 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2454 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2455 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2459 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
2460 ;; FIXME: Do we really need the shorter variants?
2462 (define_insn "xorsi3"
2463 [(set (match_operand:SI 0 "register_operand" "=r")
2464 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2465 (match_operand:SI 2 "register_operand" "r")))]
2468 [(set_attr "slottable" "yes")])
2470 (define_insn "xor<mode>3"
2471 [(set (match_operand:BW 0 "register_operand" "=r")
2472 (xor:BW (match_operand:BW 1 "register_operand" "%0")
2473 (match_operand:BW 2 "register_operand" "r")))]
2476 [(set_attr "slottable" "yes")
2477 (set_attr "cc" "clobber")])
2481 ;; Questionable use, here mostly as a (slightly usable) define_expand
2484 (define_expand "negsf2"
2487 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
2488 (neg:SF (match_operand:SF 1
2489 "register_operand" "0")))
2490 (use (match_dup 2))])]
2493 operands[2] = gen_reg_rtx (SImode);
2494 operands[3] = GEN_INT (1 << 31);
2497 (define_insn "*expanded_negsf2"
2498 [(set (match_operand:SF 0 "register_operand" "=r")
2499 (neg:SF (match_operand:SF 1 "register_operand" "0")))
2500 (use (match_operand:SI 2 "register_operand" "r"))]
2503 [(set_attr "slottable" "yes")])
2505 ;; No "negdi2" although we could make one up that may be faster than
2506 ;; the one in libgcc.
2508 (define_insn "neg<mode>2"
2509 [(set (match_operand:BWD 0 "register_operand" "=r")
2510 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
2513 [(set_attr "slottable" "yes")])
2517 ;; See comment on anddi3 - no need for a DImode pattern.
2518 ;; See also xor comment.
2520 (define_insn "one_cmplsi2"
2521 [(set (match_operand:SI 0 "register_operand" "=r")
2522 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2525 [(set_attr "slottable" "yes")])
2527 (define_insn "one_cmpl<mode>2"
2528 [(set (match_operand:BW 0 "register_operand" "=r")
2529 (not:BW (match_operand:BW 1 "register_operand" "0")))]
2532 [(set_attr "slottable" "yes")
2533 (set_attr "cc" "clobber")])
2535 ;; Arithmetic/Logical shift right (and SI left).
2537 (define_insn "<shlr>si3"
2538 [(set (match_operand:SI 0 "register_operand" "=r")
2539 (shift:SI (match_operand:SI 1 "register_operand" "0")
2540 (match_operand:SI 2 "nonmemory_operand" "Kr")))]
2543 if (REG_S_P (operands[2]))
2544 return "<slr>.d %2,%0";
2546 return "<slr>q %2,%0";
2548 [(set_attr "slottable" "yes")])
2550 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
2551 ;; the destination) when it changes shifts of lower modes into SImode,
2552 ;; it is better to make these expands an anonymous patterns instead of
2553 ;; the more correct define_insns. This occurs when gcc thinks that is
2554 ;; is better to widen to SImode and use immediate shift count.
2556 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
2558 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
2559 ;; mentioning "shiftrt"), so we need two patterns.
2560 (define_expand "ashr<mode>3"
2562 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
2564 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
2565 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
2566 (set (match_operand:BW 0 "general_operand" "")
2567 (subreg:BW (match_dup 5) 0))]
2572 for (i = 3; i < 6; i++)
2573 operands[i] = gen_reg_rtx (SImode);
2576 (define_expand "lshr<mode>3"
2578 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
2580 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
2581 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
2582 (set (match_operand:BW 0 "general_operand" "")
2583 (subreg:BW (match_dup 5) 0))]
2588 for (i = 3; i < 6; i++)
2589 operands[i] = gen_reg_rtx (SImode);
2592 (define_insn "*expanded_<shlr><mode>"
2593 [(set (match_operand:BW 0 "register_operand" "=r")
2594 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
2595 (match_operand:BW 2 "register_operand" "r")))]
2598 [(set_attr "slottable" "yes")])
2600 (define_insn "*<shlr><mode>_lowpart"
2601 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2602 (shiftrt:BW (match_dup 0)
2603 (match_operand:BW 1 "register_operand" "r")))]
2606 [(set_attr "slottable" "yes")])
2608 ;; Arithmetic/logical shift left.
2610 ;; For narrower modes than SI, we can use lslq although it makes cc
2611 ;; unusable. The win is that we do not have to reload the shift-count
2614 (define_insn "ashl<mode>3"
2615 [(set (match_operand:BW 0 "register_operand" "=r,r")
2616 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
2617 (match_operand:BW 2 "nonmemory_operand" "r,K")))]
2621 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
2623 : (CONSTANT_P (operands[2])
2624 ? "lslq %2,%0" : "lsl<m> %2,%0");
2626 [(set_attr "slottable" "yes")
2627 (set_attr "cc" "normal,clobber")])
2629 ;; A strict_low_part matcher.
2631 (define_insn "*ashl<mode>_lowpart"
2632 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2633 (ashift:BW (match_dup 0)
2634 (match_operand:HI 1 "register_operand" "r")))]
2637 [(set_attr "slottable" "yes")])
2639 ;; Various strange insns that gcc likes.
2641 ;; Fortunately, it is simple to construct an abssf (although it may not
2642 ;; be very much used in practice).
2644 (define_insn "abssf2"
2645 [(set (match_operand:SF 0 "register_operand" "=r")
2646 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2648 "lslq 1,%0\;lsrq 1,%0")
2650 (define_insn "abssi2"
2651 [(set (match_operand:SI 0 "register_operand" "=r")
2652 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
2655 [(set_attr "slottable" "yes")])
2657 ;; FIXME: GCC should be able to do these expansions itself.
2659 (define_expand "abs<mode>2"
2661 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
2662 (set (match_dup 3) (abs:SI (match_dup 2)))
2663 (set (match_operand:BW 0 "register_operand" "")
2664 (subreg:BW (match_dup 3) 0))]
2666 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
2668 (define_insn "clzsi2"
2669 [(set (match_operand:SI 0 "register_operand" "=r")
2670 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
2673 [(set_attr "slottable" "yes")])
2675 (define_insn "bswapsi2"
2676 [(set (match_operand:SI 0 "register_operand" "=r")
2677 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
2680 [(set_attr "slottable" "yes")])
2682 ;; This instruction swaps all bits in a register.
2683 ;; That means that the most significant bit is put in the place
2684 ;; of the least significant bit, and so on.
2686 (define_insn "cris_swap_bits"
2687 [(set (match_operand:SI 0 "register_operand" "=r")
2688 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
2689 CRIS_UNSPEC_SWAP_BITS))]
2692 [(set_attr "slottable" "yes")])
2694 ;; Implement ctz using two instructions, one for bit swap and one for clz.
2695 ;; Defines a scratch register to avoid clobbering input.
2697 (define_expand "ctzsi2"
2699 (match_operand:SI 1 "register_operand"))
2701 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
2702 (set (match_operand:SI 0 "register_operand")
2703 (clz:SI (match_dup 2)))]
2704 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
2705 "operands[2] = gen_reg_rtx (SImode);")
2707 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
2708 ;; operation supported by gcc. Used in casesi, but used now and then in
2711 (define_insn "uminsi3"
2712 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
2713 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
2714 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
2717 if (CONST_INT_P (operands[2]))
2719 /* Constant operands are zero-extended, so only 32-bit operands
2721 if (INTVAL (operands[2]) >= 0)
2723 if (INTVAL (operands[2]) < 256)
2724 return "bound.b %2,%0";
2726 if (INTVAL (operands[2]) < 65536)
2727 return "bound.w %2,%0";
2730 else if (which_alternative == 3)
2731 return "bound.d %2,%1,%0";
2733 return "bound.d %2,%0";
2735 [(set_attr "slottable" "yes,yes,no,no")])
2737 ;; Jump and branch insns.
2741 (label_ref (match_operand 0 "" "")))]
2744 [(set_attr "slottable" "has_slot")])
2746 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
2747 ;; here, since the insn is not recognized as an indirect jump by
2748 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
2749 ;; change from general_operand to nonimmediate_operand (at least the docs
2750 ;; should be changed), but then again the pattern is called indirect_jump.
2751 (define_insn "indirect_jump"
2752 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
2756 ;; Return insn. Used whenever the epilogue is very simple; if it is only
2757 ;; a single ret or jump [sp+]. No allocated stack space or saved
2758 ;; registers are allowed.
2759 ;; Note that for this pattern, although named, it is ok to check the
2760 ;; context of the insn in the test, not only compiler switches.
2762 (define_expand "return"
2764 "cris_simple_epilogue ()"
2765 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
2767 (define_insn "*return_expanded"
2771 return cris_return_address_on_stack_for_return ()
2772 ? "jump [$sp+]" : "ret%#";
2774 [(set (attr "slottable")
2777 "(cris_return_address_on_stack_for_return ())")
2780 (const_string "has_slot")))])
2782 (define_expand "prologue"
2784 "TARGET_PROLOGUE_EPILOGUE"
2785 "cris_expand_prologue (); DONE;")
2787 ;; Note that the (return) from the expander itself is always the last
2788 ;; insn in the epilogue.
2789 (define_expand "epilogue"
2791 "TARGET_PROLOGUE_EPILOGUE"
2792 "cris_expand_epilogue (); DONE;")
2794 ;; Conditional branches.
2796 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
2797 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
2800 (define_insn "b<ncond:code>"
2802 (if_then_else (ncond (cc0)
2804 (label_ref (match_operand 0 "" ""))
2808 [(set_attr "slottable" "has_slot")])
2810 (define_insn "b<ocond:code>"
2812 (if_then_else (ocond (cc0)
2814 (label_ref (match_operand 0 "" ""))
2819 (cc_prev_status.flags & CC_NO_OVERFLOW)
2820 ? 0 : "b<CC> %l0%#";
2822 [(set_attr "slottable" "has_slot")])
2824 (define_insn "b<rcond:code>"
2826 (if_then_else (rcond (cc0)
2828 (label_ref (match_operand 0 "" ""))
2833 (cc_prev_status.flags & CC_NO_OVERFLOW)
2834 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
2836 [(set_attr "slottable" "has_slot")])
2838 ;; Reversed anonymous patterns to the ones above, as mandated.
2840 (define_insn "*b<ncond:code>_reversed"
2842 (if_then_else (ncond (cc0)
2845 (label_ref (match_operand 0 "" ""))))]
2848 [(set_attr "slottable" "has_slot")])
2850 (define_insn "*b<ocond:code>_reversed"
2852 (if_then_else (ocond (cc0)
2855 (label_ref (match_operand 0 "" ""))))]
2859 (cc_prev_status.flags & CC_NO_OVERFLOW)
2860 ? 0 : "b<rCC> %l0%#";
2862 [(set_attr "slottable" "has_slot")])
2864 (define_insn "*b<rcond:code>_reversed"
2866 (if_then_else (rcond (cc0)
2869 (label_ref (match_operand 0 "" ""))))]
2873 (cc_prev_status.flags & CC_NO_OVERFLOW)
2874 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
2876 [(set_attr "slottable" "has_slot")])
2878 ;; Set on condition: sCC.
2880 ;; Like bCC, we have to check the overflow bit for
2881 ;; signed conditions.
2883 (define_insn "s<ncond:code>"
2884 [(set (match_operand:SI 0 "register_operand" "=r")
2885 (ncond:SI (cc0) (const_int 0)))]
2888 [(set_attr "slottable" "yes")
2889 (set_attr "cc" "none")])
2891 (define_insn "s<rcond:code>"
2892 [(set (match_operand:SI 0 "register_operand" "=r")
2893 (rcond:SI (cc0) (const_int 0)))]
2897 (cc_prev_status.flags & CC_NO_OVERFLOW)
2898 ? "s<oCC> %0" : "s<CC> %0";
2900 [(set_attr "slottable" "yes")
2901 (set_attr "cc" "none")])
2903 (define_insn "s<ocond:code>"
2904 [(set (match_operand:SI 0 "register_operand" "=r")
2905 (ocond:SI (cc0) (const_int 0)))]
2909 (cc_prev_status.flags & CC_NO_OVERFLOW)
2912 [(set_attr "slottable" "yes")
2913 (set_attr "cc" "none")])
2917 ;; We need to make these patterns "expand", since the real operand is
2918 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
2919 ;; and cannot be checked if it were a "normal" pattern.
2920 ;; Note that "call" and "call_value" are *always* called with a
2921 ;; mem-operand for operand 0 and 1 respective. What happens for combined
2922 ;; instructions is a different issue.
2924 (define_expand "call"
2925 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
2926 (match_operand 1 "general_operand" ""))
2927 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2930 gcc_assert (MEM_P (operands[0]));
2932 cris_expand_pic_call_address (&operands[0]);
2935 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
2936 ;; order of preference.
2938 (define_insn "*expanded_call"
2939 [(call (mem:QI (match_operand:SI
2940 0 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
2941 (match_operand 1 "" ""))
2942 (clobber (reg:SI CRIS_SRP_REGNUM))]
2946 ;; Parallel when calculating and reusing address of indirect pointer
2947 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
2948 ;; wrong not to have the clobber last, but that's the way combine
2949 ;; generates it (except it doesn' look into the *inner* mem, so this
2950 ;; just matches a peephole2). FIXME: investigate that.
2951 (define_insn "*expanded_call_side"
2954 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
2955 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
2956 (match_operand 2 "" ""))
2957 (clobber (reg:SI CRIS_SRP_REGNUM))
2958 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
2959 (plus:SI (match_dup 0)
2961 "! TARGET_AVOID_GOTPLT"
2964 (define_expand "call_value"
2965 [(parallel [(set (match_operand 0 "" "")
2966 (call (match_operand:QI 1 "cris_mem_call_operand" "")
2967 (match_operand 2 "" "")))
2968 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2971 gcc_assert (MEM_P (operands[1]));
2973 cris_expand_pic_call_address (&operands[1]);
2976 ;; Accept *anything* as operand 2. The validity other than "general" of
2977 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
2978 ;; order of preference (Q includes r, but r is shorter, faster).
2979 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
2980 ;; than requiring getting rPIC + sym:PLT into a register.
2982 (define_insn "*expanded_call_value"
2983 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
2984 (call (mem:QI (match_operand:SI
2985 1 "cris_general_operand_or_plt_symbol" "r,Q>,g"))
2986 (match_operand 2 "" "")))
2987 (clobber (reg:SI CRIS_SRP_REGNUM))]
2990 [(set_attr "cc" "clobber")])
2992 ;; See similar call special-case.
2993 (define_insn "*expanded_call_value_side"
2994 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
2998 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
2999 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3000 (match_operand 3 "" "")))
3001 (clobber (reg:SI CRIS_SRP_REGNUM))
3002 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3003 (plus:SI (match_dup 1)
3005 "! TARGET_AVOID_GOTPLT"
3007 [(set_attr "cc" "clobber")])
3009 ;; Used in debugging. No use for the direct pattern; unfilled
3010 ;; delayed-branches are taken care of by other means.
3016 [(set_attr "cc" "none")])
3018 ;; We need to stop accesses to the stack after the memory is
3019 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3020 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3021 ;; want to use a naked (unspec_volatile) as that would stop any
3022 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3023 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3024 ;; still has the effect of an unspec_volatile.
3025 (define_insn "cris_frame_deallocated_barrier"
3026 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3027 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3030 [(set_attr "length" "0")])
3032 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3033 ;; a table to pc" (adds.w [pc+%0.w],pc).
3035 ;; Note: if you change the "parallel" (or add anything after it) in
3036 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3037 ;; accordingly, to add the default case at the end of the jump-table.
3039 (define_expand "casesi"
3040 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3042 (minus:SI (match_dup 5)
3043 (match_operand:SI 1 "const_int_operand" "n")))
3045 (umin:SI (match_dup 6)
3046 (match_operand:SI 2 "const_int_operand" "n")))
3050 (ltu (match_dup 7) (match_dup 2))
3051 (plus:SI (sign_extend:SI
3053 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3056 (label_ref (match_operand 4 "" ""))))
3057 (use (label_ref (match_operand 3 "" "")))])]
3060 operands[2] = plus_constant (operands[2], 1);
3061 operands[5] = gen_reg_rtx (SImode);
3062 operands[6] = gen_reg_rtx (SImode);
3063 operands[7] = gen_reg_rtx (SImode);
3066 ;; Split-patterns. Some of them have modes unspecified. This
3067 ;; should always be ok; if for no other reason sparc.md has it as
3070 ;; When register_operand is specified for an operand, we can get a
3071 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3072 ;; for a register_operand and that REGNO can be used as is. It is best to
3073 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3075 ;; op [rx + 0],ry,rz
3076 ;; The index to rx is optimized into zero, and gone.
3078 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3079 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3083 ;; Lose if rz=ry or rx=rz.
3084 ;; Call this op-extend-split
3087 [(set (match_operand 0 "register_operand" "")
3089 4 "cris_operand_extend_operator"
3090 [(match_operand 1 "register_operand" "")
3092 3 "cris_extend_operator"
3093 [(match_operand 2 "memory_operand" "")])]))]
3094 "REG_P (operands[0])
3095 && REG_P (operands[1])
3096 && REGNO (operands[1]) != REGNO (operands[0])
3097 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3098 && REG_P (XEXP (operands[2], 0))
3099 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3105 (match_op_dup 3 [(match_dup 2)])]))]
3108 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3111 ;; Do this for plus or bound only, being commutative operations, since we
3112 ;; have swapped the operands.
3113 ;; Call this op-extend-split-rx=rz
3116 [(set (match_operand 0 "register_operand" "")
3118 4 "cris_plus_or_bound_operator"
3119 [(match_operand 1 "register_operand" "")
3121 3 "cris_extend_operator"
3122 [(match_operand 2 "memory_operand" "")])]))]
3123 "REG_P (operands[0])
3124 && REG_P (operands[1])
3125 && REGNO (operands[1]) != REGNO (operands[0])
3126 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3127 && REG_P (XEXP (operands[2], 0))
3128 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3130 (match_op_dup 3 [(match_dup 2)]))
3137 ;; As the op-extend-split, but swapped operands, and only for
3138 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
3139 ;; this needed? Is it?
3140 ;; Call this op-extend-split-swapped
3143 [(set (match_operand 0 "register_operand" "")
3145 4 "cris_plus_or_bound_operator"
3147 3 "cris_extend_operator"
3148 [(match_operand 2 "memory_operand" "")])
3149 (match_operand 1 "register_operand" "")]))]
3150 "REG_P (operands[0])
3151 && REG_P (operands[1])
3152 && REGNO (operands[1]) != REGNO (operands[0])
3153 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3154 && REG_P (XEXP (operands[2], 0))
3155 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3161 (match_op_dup 3 [(match_dup 2)])]))]
3164 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
3165 ;; bound. Call this op-extend-split-swapped-rx=rz.
3168 [(set (match_operand 0 "register_operand" "")
3170 4 "cris_plus_or_bound_operator"
3172 3 "cris_extend_operator"
3173 [(match_operand 2 "memory_operand" "")])
3174 (match_operand 1 "register_operand" "")]))]
3175 "REG_P (operands[0])
3176 && REG_P (operands[1])
3177 && REGNO (operands[1]) != REGNO (operands[0])
3178 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3179 && REG_P (XEXP (operands[2], 0))
3180 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3182 (match_op_dup 3 [(match_dup 2)]))
3189 ;; As op-extend-split, but the mem operand is not extended.
3191 ;; op [rx],ry,rz changed into
3194 ;; lose if ry=rz or rx=rz
3195 ;; Call this op-extend.
3198 [(set (match_operand 0 "register_operand" "")
3200 3 "cris_orthogonal_operator"
3201 [(match_operand 1 "register_operand" "")
3202 (match_operand 2 "memory_operand" "")]))]
3203 "REG_P (operands[0])
3204 && REG_P (operands[1])
3205 && REGNO (operands[1]) != REGNO (operands[0])
3206 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3207 && REG_P (XEXP (operands[2], 0))
3208 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3217 ;; As op-extend-split-rx=rz, non-extended.
3218 ;; Call this op-split-rx=rz
3221 [(set (match_operand 0 "register_operand" "")
3223 3 "cris_commutative_orth_op"
3224 [(match_operand 2 "memory_operand" "")
3225 (match_operand 1 "register_operand" "")]))]
3226 "REG_P (operands[0])
3227 && REG_P (operands[1])
3228 && REGNO (operands[1]) != REGNO (operands[0])
3229 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3230 && REG_P (XEXP (operands[2], 0))
3231 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3240 ;; As op-extend-split-swapped, nonextended.
3241 ;; Call this op-split-swapped.
3244 [(set (match_operand 0 "register_operand" "")
3246 3 "cris_commutative_orth_op"
3247 [(match_operand 1 "register_operand" "")
3248 (match_operand 2 "memory_operand" "")]))]
3249 "REG_P (operands[0]) && REG_P (operands[1])
3250 && REGNO (operands[1]) != REGNO (operands[0])
3251 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3252 && REG_P (XEXP (operands[2], 0))
3253 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3262 ;; As op-extend-split-swapped-rx=rz, non-extended.
3263 ;; Call this op-split-swapped-rx=rz.
3266 [(set (match_operand 0 "register_operand" "")
3268 3 "cris_orthogonal_operator"
3269 [(match_operand 2 "memory_operand" "")
3270 (match_operand 1 "register_operand" "")]))]
3271 "REG_P (operands[0]) && REG_P (operands[1])
3272 && REGNO (operands[1]) != REGNO (operands[0])
3273 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3274 && REG_P (XEXP (operands[2], 0))
3275 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3284 ;; Splits for all cases in side-effect insns where (possibly after reload
3285 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
3287 ;; move.S1 [rx=rx+rz.S2],ry
3291 [(set (match_operand 0 "register_operand" "")
3295 (mult:SI (match_operand:SI 1 "register_operand" "")
3296 (match_operand:SI 2 "const_int_operand" ""))
3297 (match_operand:SI 3 "register_operand" ""))]))
3298 (set (match_operand:SI 4 "register_operand" "")
3299 (plus:SI (mult:SI (match_dup 1)
3302 "REG_P (operands[3]) && REG_P (operands[4])
3303 && REGNO (operands[3]) == REGNO (operands[4])"
3304 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
3306 (set (match_dup 0) (match_dup 5))]
3307 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
3309 ;; move.S1 [rx=rx+i],ry
3313 [(set (match_operand 0 "register_operand" "")
3316 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
3317 (match_operand:SI 2 "cris_bdap_operand" ""))]))
3318 (set (match_operand:SI 3 "register_operand" "")
3319 (plus:SI (match_dup 1)
3321 "(rtx_equal_p (operands[3], operands[1])
3322 || rtx_equal_p (operands[3], operands[2]))"
3323 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
3324 (set (match_dup 0) (match_dup 4))]
3326 operands[4] = replace_equiv_address (operands[5], operands[3]);
3327 cris_order_for_addsi3 (operands, 1);
3330 ;; move.S1 ry,[rx=rx+rz.S2]
3334 [(set (match_operator
3337 (mult:SI (match_operand:SI 0 "register_operand" "")
3338 (match_operand:SI 1 "const_int_operand" ""))
3339 (match_operand:SI 2 "register_operand" ""))])
3340 (match_operand 3 "register_operand" ""))
3341 (set (match_operand:SI 4 "register_operand" "")
3342 (plus:SI (mult:SI (match_dup 0)
3345 "REG_P (operands[2]) && REG_P (operands[4])
3346 && REGNO (operands[4]) == REGNO (operands[2])"
3347 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3349 (set (match_dup 5) (match_dup 3))]
3350 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
3352 ;; move.S1 ry,[rx=rx+i]
3356 [(set (match_operator
3358 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
3359 (match_operand:SI 1 "cris_bdap_operand" ""))])
3360 (match_operand 2 "register_operand" ""))
3361 (set (match_operand:SI 3 "register_operand" "")
3362 (plus:SI (match_dup 0)
3364 "(rtx_equal_p (operands[3], operands[0])
3365 || rtx_equal_p (operands[3], operands[1]))"
3366 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
3367 (set (match_dup 5) (match_dup 2))]
3369 operands[5] = replace_equiv_address (operands[6], operands[3]);
3370 cris_order_for_addsi3 (operands, 0);
3373 ;; clear.[bwd] [rx=rx+rz.S2]
3377 [(set (mem:BWD (plus:SI
3378 (mult:SI (match_operand:SI 0 "register_operand" "")
3379 (match_operand:SI 1 "const_int_operand" ""))
3380 (match_operand:SI 2 "register_operand" "")))
3382 (set (match_operand:SI 3 "register_operand" "")
3383 (plus:SI (mult:SI (match_dup 0)
3386 "REG_P (operands[2]) && REG_P (operands[3])
3387 && REGNO (operands[3]) == REGNO (operands[2])"
3388 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3390 (set (mem:BWD (match_dup 3)) (const_int 0))]
3393 ;; clear.[bwd] [rx=rx+i]
3398 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
3399 (match_operand:SI 1 "cris_bdap_operand" "")))
3401 (set (match_operand:SI 2 "register_operand" "")
3402 (plus:SI (match_dup 0)
3404 "(rtx_equal_p (operands[0], operands[2])
3405 || rtx_equal_p (operands[2], operands[1]))"
3406 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
3407 (set (mem:BWD (match_dup 2)) (const_int 0))]
3408 "cris_order_for_addsi3 (operands, 0);")
3410 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
3414 [(set (match_operand 0 "register_operand" "")
3416 5 "cris_extend_operator"
3418 (mult:SI (match_operand:SI 1 "register_operand" "")
3419 (match_operand:SI 2 "const_int_operand" ""))
3420 (match_operand:SI 3 "register_operand" "")))]))
3421 (set (match_operand:SI 4 "register_operand" "")
3422 (plus:SI (mult:SI (match_dup 1)
3425 "REG_P (operands[3])
3426 && REG_P (operands[4])
3427 && REGNO (operands[3]) == REGNO (operands[4])"
3428 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
3430 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
3431 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
3433 ;; mov(s|u).S1 [rx=rx+i],ry
3437 [(set (match_operand 0 "register_operand" "")
3439 4 "cris_extend_operator"
3441 (match_operand:SI 1 "cris_bdap_operand" "")
3442 (match_operand:SI 2 "cris_bdap_operand" "")))]))
3443 (set (match_operand:SI 3 "register_operand" "")
3444 (plus:SI (match_dup 1)
3446 "(rtx_equal_p (operands[1], operands[3])
3447 || rtx_equal_p (operands[2], operands[3]))"
3448 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
3449 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
3451 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
3452 cris_order_for_addsi3 (operands, 1);
3455 ;; op.S1 [rx=rx+i],ry
3459 [(set (match_operand 0 "register_operand" "")
3461 5 "cris_orthogonal_operator"
3462 [(match_operand 1 "register_operand" "")
3464 (match_operand:SI 2 "cris_bdap_operand" "")
3465 (match_operand:SI 3 "cris_bdap_operand" "")))]))
3466 (set (match_operand:SI 4 "register_operand" "")
3467 (plus:SI (match_dup 2)
3469 "(rtx_equal_p (operands[4], operands[2])
3470 || rtx_equal_p (operands[4], operands[3]))"
3471 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3472 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
3474 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
3475 cris_order_for_addsi3 (operands, 2);
3478 ;; op.S1 [rx=rx+rz.S2],ry
3482 [(set (match_operand 0 "register_operand" "")
3484 6 "cris_orthogonal_operator"
3485 [(match_operand 1 "register_operand" "")
3487 (mult:SI (match_operand:SI 2 "register_operand" "")
3488 (match_operand:SI 3 "const_int_operand" ""))
3489 (match_operand:SI 4 "register_operand" "")))]))
3490 (set (match_operand:SI 5 "register_operand" "")
3491 (plus:SI (mult:SI (match_dup 2)
3494 "REG_P (operands[4])
3495 && REG_P (operands[5])
3496 && REGNO (operands[5]) == REGNO (operands[4])"
3497 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3499 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
3500 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
3502 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
3506 [(set (match_operand 0 "register_operand" "")
3508 6 "cris_commutative_orth_op"
3510 (mult:SI (match_operand:SI 2 "register_operand" "")
3511 (match_operand:SI 3 "const_int_operand" ""))
3512 (match_operand:SI 4 "register_operand" "")))
3513 (match_operand 1 "register_operand" "")]))
3514 (set (match_operand:SI 5 "register_operand" "")
3515 (plus:SI (mult:SI (match_dup 2)
3518 "REG_P (operands[4])
3519 && REG_P (operands[5])
3520 && REGNO (operands[5]) == REGNO (operands[4])"
3521 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3523 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
3524 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
3526 ;; op.S1 [rx=rx+i],ry (swapped)
3530 [(set (match_operand 0 "register_operand" "")
3532 5 "cris_commutative_orth_op"
3534 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
3535 (match_operand:SI 3 "cris_bdap_operand" "")))
3536 (match_operand 1 "register_operand" "")]))
3537 (set (match_operand:SI 4 "register_operand" "")
3538 (plus:SI (match_dup 2)
3540 "(rtx_equal_p (operands[4], operands[2])
3541 || rtx_equal_p (operands[4], operands[3]))"
3542 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3543 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
3545 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
3546 cris_order_for_addsi3 (operands, 2);
3549 ;; op(s|u).S1 [rx=rx+rz.S2],ry
3553 [(set (match_operand 0 "register_operand" "")
3555 6 "cris_operand_extend_operator"
3556 [(match_operand 1 "register_operand" "")
3558 7 "cris_extend_operator"
3560 (mult:SI (match_operand:SI 2 "register_operand" "")
3561 (match_operand:SI 3 "const_int_operand" ""))
3562 (match_operand:SI 4 "register_operand" "")))])]))
3563 (set (match_operand:SI 5 "register_operand" "")
3564 (plus:SI (mult:SI (match_dup 2)
3567 "REG_P (operands[4])
3568 && REG_P (operands[5])
3569 && REGNO (operands[5]) == REGNO (operands[4])"
3570 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3572 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
3573 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
3574 replace_equiv_address (XEXP (operands[7], 0),
3577 ;; op(s|u).S1 [rx=rx+i],ry
3581 [(set (match_operand 0 "register_operand" "")
3583 5 "cris_operand_extend_operator"
3584 [(match_operand 1 "register_operand" "")
3586 6 "cris_extend_operator"
3588 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
3589 (match_operand:SI 3 "cris_bdap_operand" "")
3591 (set (match_operand:SI 4 "register_operand" "")
3592 (plus:SI (match_dup 2)
3594 "(rtx_equal_p (operands[4], operands[2])
3595 || rtx_equal_p (operands[4], operands[3]))"
3596 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3597 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
3599 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
3600 replace_equiv_address (XEXP (operands[6], 0),
3602 cris_order_for_addsi3 (operands, 2);
3605 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
3609 [(set (match_operand 0 "register_operand" "")
3611 7 "cris_plus_or_bound_operator"
3613 6 "cris_extend_operator"
3615 (mult:SI (match_operand:SI 2 "register_operand" "")
3616 (match_operand:SI 3 "const_int_operand" ""))
3617 (match_operand:SI 4 "register_operand" "")))])
3618 (match_operand 1 "register_operand" "")]))
3619 (set (match_operand:SI 5 "register_operand" "")
3620 (plus:SI (mult:SI (match_dup 2)
3623 "REG_P (operands[4]) && REG_P (operands[5])
3624 && REGNO (operands[5]) == REGNO (operands[4])"
3625 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
3627 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
3628 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
3629 replace_equiv_address (XEXP (operands[6], 0),
3632 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
3636 [(set (match_operand 0 "register_operand" "")
3638 6 "cris_plus_or_bound_operator"
3640 5 "cris_extend_operator"
3642 (match_operand:SI 2 "cris_bdap_operand" "")
3643 (match_operand:SI 3 "cris_bdap_operand" "")))])
3644 (match_operand 1 "register_operand" "")]))
3645 (set (match_operand:SI 4 "register_operand" "")
3646 (plus:SI (match_dup 2)
3648 "(rtx_equal_p (operands[4], operands[2])
3649 || rtx_equal_p (operands[4], operands[3]))"
3650 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
3651 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
3653 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
3654 replace_equiv_address (XEXP (operands[5], 0),
3656 cris_order_for_addsi3 (operands, 2);
3659 ;; Splits for addressing prefixes that have no side-effects, so we can
3660 ;; fill a delay slot. Never split if we lose something, though.
3663 ;; move [indirect_ref],rx
3664 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
3665 ;; move indirect_ref,rx
3667 ;; Take care not to allow indirect_ref = register.
3669 ;; We're not allowed to generate copies of registers with different mode
3670 ;; until after reload; copying pseudos upsets reload. CVS as of
3671 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
3672 ;; cselib_invalidate_regno.
3674 (define_split ; indir_to_reg_split
3675 [(set (match_operand 0 "register_operand" "")
3676 (match_operand 1 "indirect_operand" ""))]
3678 && REG_P (operands[0])
3679 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3680 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
3681 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
3682 [(set (match_dup 2) (match_dup 4))
3683 (set (match_dup 0) (match_dup 3))]
3684 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
3685 operands[3] = replace_equiv_address (operands[1], operands[2]);
3686 operands[4] = XEXP (operands[1], 0);")
3688 ;; As the above, but MOVS and MOVU.
3691 [(set (match_operand 0 "register_operand" "")
3693 4 "cris_extend_operator"
3694 [(match_operand 1 "indirect_operand" "")]))]
3696 && REG_P (operands[0])
3697 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3698 && (MEM_P (XEXP (operands[1], 0))
3699 || CONSTANT_P (XEXP (operands[1], 0)))"
3700 [(set (match_dup 2) (match_dup 5))
3701 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
3702 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
3703 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
3704 operands[5] = XEXP (operands[1], 0);")
3706 ;; Various peephole optimizations.
3708 ;; Watch out: when you exchange one set of instructions for another, the
3709 ;; condition codes setting must be the same, or you have to CC_INIT or
3710 ;; whatever is appropriate, in the pattern before you emit the
3711 ;; assembly text. This is best done here, not in cris_notice_update_cc,
3712 ;; to keep changes local to their cause.
3714 ;; Do not add patterns that you do not know will be matched.
3715 ;; Please also add a self-contained testcase.
3717 ;; We have trouble with and:s and shifts. Maybe something is broken in
3718 ;; gcc? Or it could just be that bit-field insn expansion is a bit
3719 ;; suboptimal when not having extzv insns.
3720 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
3722 (define_peephole2 ; asrandb (peephole casesi+31)
3723 [(set (match_operand:SI 0 "register_operand" "")
3724 (ashiftrt:SI (match_dup 0)
3725 (match_operand:SI 1 "const_int_operand" "")))
3727 (and:SI (match_dup 0)
3728 (match_operand 2 "const_int_operand" "")))]
3729 "INTVAL (operands[2]) > 31
3730 && INTVAL (operands[2]) < 255
3731 && INTVAL (operands[1]) > 23
3732 /* Check that the and-operation enables us to use logical-shift. */
3733 && (INTVAL (operands[2])
3734 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
3735 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3736 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
3737 ;; FIXME: CC0 is valid except for the M bit.
3739 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
3740 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
3743 (define_peephole2 ; asrandw (peephole casesi+32)
3744 [(set (match_operand:SI 0 "register_operand" "")
3745 (ashiftrt:SI (match_dup 0)
3746 (match_operand:SI 1 "const_int_operand" "")))
3748 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3749 "INTVAL (operands[2]) > 31
3750 && INTVAL (operands[2]) < 65535
3751 && INTVAL (operands[2]) != 255
3752 && INTVAL (operands[1]) > 15
3753 /* Check that the and-operation enables us to use logical-shift. */
3754 && (INTVAL (operands[2])
3755 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
3756 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3757 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
3758 ;; FIXME: CC0 is valid except for the M bit.
3760 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3761 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
3764 (define_peephole2 ; lsrandb (peephole casesi+33)
3765 [(set (match_operand:SI 0 "register_operand" "")
3766 (lshiftrt:SI (match_dup 0)
3767 (match_operand:SI 1 "const_int_operand" "")))
3769 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3770 "INTVAL (operands[2]) > 31
3771 && INTVAL (operands[2]) < 255
3772 && INTVAL (operands[1]) > 23"
3773 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3774 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
3775 ;; FIXME: CC0 is valid except for the M bit.
3777 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
3778 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
3781 (define_peephole2 ; lsrandw (peephole casesi+34)
3782 [(set (match_operand:SI 0 "register_operand" "")
3783 (lshiftrt:SI (match_dup 0)
3784 (match_operand:SI 1 "const_int_operand" "")))
3786 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
3787 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
3788 && INTVAL (operands[2]) != 255
3789 && INTVAL (operands[1]) > 15"
3790 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
3791 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
3792 ;; FIXME: CC0 is valid except for the M bit.
3794 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3795 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
3803 ;; move [rx=rx+n],ry
3804 ;; when -128 <= n <= 127.
3805 ;; This will reduce the size of the assembler code for n = [-128..127],
3806 ;; and speed up accordingly. Don't match if the previous insn is
3807 ;; (set rx rz) because that combination is matched by another peephole.
3808 ;; No stable test-case.
3810 (define_peephole2 ; moversideqi (peephole casesi+35)
3811 [(set (match_operand:SI 0 "register_operand" "")
3812 (plus:SI (match_operand:SI 1 "register_operand" "")
3813 (match_operand:SI 2 "const_int_operand" "")))
3814 (set (match_operand 3 "register_operand" "")
3815 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
3816 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
3817 && REGNO (operands[3]) != REGNO (operands[0])
3818 && (BASE_P (operands[1]) || BASE_P (operands[2]))
3819 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3820 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3821 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
3823 [(set (match_dup 3) (match_dup 5))
3824 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3825 ;; Checking the previous insn is a bit too awkward for the condition.
3827 rtx prev = prev_nonnote_insn (curr_insn);
3828 if (prev != NULL_RTX)
3830 rtx set = single_set (prev);
3832 && REG_S_P (SET_DEST (set))
3833 && REGNO (SET_DEST (set)) == REGNO (operands[0])
3834 && REG_S_P (SET_SRC (set)))
3838 = replace_equiv_address (operands[4],
3839 gen_rtx_PLUS (SImode,
3840 operands[1], operands[2]));
3843 ;; Vice versa: move ry,[rx=rx+n]
3845 (define_peephole2 ; movemsideqi (peephole casesi+36)
3846 [(set (match_operand:SI 0 "register_operand" "")
3847 (plus:SI (match_operand:SI 1 "register_operand" "")
3848 (match_operand:SI 2 "const_int_operand" "")))
3849 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
3850 (match_operand 4 "register_operand" ""))]
3851 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
3852 && REGNO (operands[4]) != REGNO (operands[0])
3853 && (BASE_P (operands[1]) || BASE_P (operands[2]))
3854 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3855 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3856 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)"
3858 [(set (match_dup 5) (match_dup 4))
3859 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3861 = replace_equiv_address (operands[3],
3862 gen_rtx_PLUS (SImode,
3863 operands[1], operands[2]));")
3865 ;; As above, change:
3869 ;; op.d [rx=rx+n],ry
3870 ;; Saves when n = [-128..127].
3872 ;; Splitting and joining combinations for side-effect modes are slightly
3873 ;; out of hand. They probably will not save the time they take typing in,
3874 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
3875 ;; the splits and peepholes as possible.
3876 ;; No stable test-case.
3878 (define_peephole2 ; mover2side (peephole casesi+37)
3879 [(set (match_operand:SI 0 "register_operand" "")
3880 (plus:SI (match_operand:SI 1 "register_operand" "")
3881 (match_operand:SI 2 "const_int_operand" "")))
3882 (set (match_operand 3 "register_operand" "")
3883 (match_operator 4 "cris_orthogonal_operator"
3886 5 "cris_mem_op" [(match_dup 0)])]))]
3887 ;; FIXME: What about DFmode?
3888 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
3889 "GET_MODE (operands[3]) != DImode
3890 && REGNO (operands[0]) != REGNO (operands[3])
3891 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
3892 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
3893 && INTVAL (operands[2]) >= -128
3894 && INTVAL (operands[2]) <= 127"
3896 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
3897 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
3899 = replace_equiv_address (operands[5],
3900 gen_rtx_PLUS (SImode,
3901 operands[1], operands[2]));")
3903 ;; Sometimes, for some reason the pattern
3907 ;; will occur. Solve this, and likewise for to-memory.
3908 ;; No stable test-case.
3910 (define_peephole2 ; moverside (peephole casesi+38)
3911 [(set (match_operand:SI 0 "register_operand" "")
3912 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
3914 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
3915 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
3916 (set (match_operand 4 "register_operand" "")
3917 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
3918 "(rtx_equal_p (operands[2], operands[0])
3919 || rtx_equal_p (operands[3], operands[0]))
3920 && cris_side_effect_mode_ok (PLUS, operands, 0,
3921 (REG_S_P (operands[1])
3923 : (rtx_equal_p (operands[2], operands[0])
3925 (! REG_S_P (operands[1])
3927 : (rtx_equal_p (operands[2], operands[0])
3931 [(set (match_dup 4) (match_dup 6))
3932 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
3935 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
3937 /* Make sure we have canonical RTX so we match the insn pattern -
3938 not a constant in the first operand. We also require the order
3939 (plus reg mem) to match the final pattern. */
3940 if (CONSTANT_P (otherop) || MEM_P (otherop))
3942 operands[7] = operands[1];
3943 operands[8] = otherop;
3947 operands[7] = otherop;
3948 operands[8] = operands[1];
3951 = replace_equiv_address (operands[5],
3952 gen_rtx_PLUS (SImode,
3953 operands[7], operands[8]));
3956 ;; As above but to memory.
3957 ;; FIXME: Split movemside and moverside into variants and prune
3958 ;; the ones that don't trig.
3959 ;; No stable test-case.
3961 (define_peephole2 ; movemside (peephole casesi+39)
3962 [(set (match_operand:SI 0 "register_operand" "")
3963 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
3965 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
3966 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
3967 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
3968 (match_operand 5 "register_operand" ""))]
3969 "(rtx_equal_p (operands[2], operands[0])
3970 || rtx_equal_p (operands[3], operands[0]))
3971 && cris_side_effect_mode_ok (PLUS, operands, 0,
3972 (REG_S_P (operands[1])
3974 : (rtx_equal_p (operands[2], operands[0])
3976 (! REG_S_P (operands[1])
3978 : (rtx_equal_p (operands[2], operands[0])
3982 [(set (match_dup 6) (match_dup 5))
3983 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
3986 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
3988 /* Make sure we have canonical RTX so we match the insn pattern -
3989 not a constant in the first operand. We also require the order
3990 (plus reg mem) to match the final pattern. */
3991 if (CONSTANT_P (otherop) || MEM_P (otherop))
3993 operands[7] = operands[1];
3994 operands[8] = otherop;
3998 operands[7] = otherop;
3999 operands[8] = operands[1];
4002 = replace_equiv_address (operands[4],
4003 gen_rtx_PLUS (SImode,
4004 operands[7], operands[8]));
4007 ;; Another spotted bad code:
4010 ;; No stable test-case.
4012 (define_peephole2 ; movei (peephole casesi+42)
4013 [(set (match_operand:SI 0 "register_operand" "")
4014 (match_operand:SI 1 "register_operand" ""))
4015 (set (match_operand 2 "register_operand" "")
4016 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4017 "REGNO (operands[0]) == REGNO (operands[2])
4018 && (REGNO_REG_CLASS (REGNO (operands[0]))
4019 == REGNO_REG_CLASS (REGNO (operands[1])))
4020 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4021 [(set (match_dup 2) (match_dup 4))]
4022 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4024 ;; move.d [r10+16],r9
4027 ;; and.d [r10+16],r12,r9
4028 ;; With generalization of the operation, the size and the addressing mode.
4029 ;; This seems to be the result of a quirk in register allocation
4030 ;; missing the three-operand cases when having different predicates.
4031 ;; Maybe that it matters that it is a commutative operation.
4032 ;; This pattern helps that situation, but there's still the increased
4033 ;; register pressure.
4034 ;; Note that adding the noncommutative variant did not show any matches
4035 ;; in ipps and cc1, so it's not here.
4036 ;; No stable test-case.
4038 (define_peephole2 ; op3 (peephole casesi+44)
4039 [(set (match_operand 0 "register_operand" "")
4043 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4044 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4047 5 "cris_commutative_orth_op"
4048 [(match_operand 3 "register_operand" "")
4049 (match_operand 4 "register_operand" "")]))]
4050 "(rtx_equal_p (operands[3], operands[0])
4051 || rtx_equal_p (operands[4], operands[0]))
4052 && ! rtx_equal_p (operands[3], operands[4])
4053 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4054 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4055 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4057 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4059 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
4061 ;; and.b some_byte,const,reg_32
4062 ;; where reg_32 is the destination of the "three-address" code optimally.
4064 ;; movu.b some_byte,reg_32
4065 ;; and.b const,reg_32
4066 ;; but is turns into:
4067 ;; move.b some_byte,reg_32
4068 ;; and.d const,reg_32
4070 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4072 (define_peephole2 ; andu (casesi+45)
4073 [(set (match_operand:SI 0 "register_operand" "")
4074 (match_operand:SI 1 "nonimmediate_operand" ""))
4075 (set (match_operand:SI 2 "register_operand" "")
4076 (and:SI (match_dup 0)
4077 (match_operand:SI 3 "const_int_operand" "")))]
4078 ;; Since the size of the memory access could be made different here,
4079 ;; don't do this for a mem-volatile access.
4080 "REGNO (operands[2]) == REGNO (operands[0])
4081 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4082 && !CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
4083 && !side_effects_p (operands[1])"
4084 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4085 [(set (match_dup 0) (match_dup 4))
4086 (set (match_dup 5) (match_dup 6))]
4088 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
4089 enum machine_mode amode
4090 = CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
4092 = (REG_S_P (operands[1])
4093 ? gen_rtx_REG (zmode, REGNO (operands[1]))
4094 : adjust_address (operands[1], zmode, 0));
4096 = gen_rtx_ZERO_EXTEND (SImode, op1);
4097 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
4099 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
4100 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
4102 ? QImode : amode)));
4105 ;; Try and avoid GOTPLT reads escaping a call: transform them into
4106 ;; PLT. Curiously (but thankfully), peepholes for instructions
4107 ;; *without side-effects* that just feed a call (or call_value) are
4108 ;; not matched neither in a build or test-suite, so those patterns are
4111 ;; A "normal" move where we don't check the consumer.
4113 (define_peephole2 ; gotplt-to-plt
4115 (match_operand:SI 0 "register_operand" "")
4119 (reg:SI CRIS_GOT_REGNUM)
4121 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
4122 CRIS_UNSPEC_PLTGOTREAD)))]))]
4124 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1))
4125 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
4126 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT)))
4127 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
4130 ;; And one set with a side-effect getting the PLTGOT offset.
4131 ;; First call and call_value variants.
4133 (define_peephole2 ; gotplt-to-plt-side-call
4136 (match_operand:SI 0 "register_operand" "")
4140 (reg:SI CRIS_GOT_REGNUM)
4142 (unspec:SI [(match_operand:SI
4143 2 "cris_general_operand_or_symbol" "")]
4144 CRIS_UNSPEC_PLTGOTREAD)))]))
4145 (set (match_operand:SI 3 "register_operand" "")
4146 (plus:SI (reg:SI CRIS_GOT_REGNUM)
4148 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
4149 (parallel [(call (mem:QI (match_dup 0))
4150 (match_operand 4 "" ""))
4151 (clobber (reg:SI CRIS_SRP_REGNUM))])]
4153 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1))
4154 && peep2_reg_dead_p (2, operands[0])"
4155 [(parallel [(call (mem:QI (match_dup 1))
4157 (clobber (reg:SI CRIS_SRP_REGNUM))
4159 (plus:SI (reg:SI CRIS_GOT_REGNUM)
4161 (unspec:SI [(match_dup 2)]
4162 CRIS_UNSPEC_PLTGOTREAD))))])]
4165 (define_peephole2 ; gotplt-to-plt-side-call-value
4168 (match_operand:SI 0 "register_operand" "")
4172 (reg:SI CRIS_GOT_REGNUM)
4174 (unspec:SI [(match_operand:SI
4175 2 "cris_general_operand_or_symbol" "")]
4176 CRIS_UNSPEC_PLTGOTREAD)))]))
4177 (set (match_operand:SI 3 "register_operand" "")
4178 (plus:SI (reg:SI CRIS_GOT_REGNUM)
4180 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
4181 (parallel [(set (match_operand 5 "" "")
4182 (call (mem:QI (match_dup 0))
4183 (match_operand 4 "" "")))
4184 (clobber (reg:SI CRIS_SRP_REGNUM))])]
4186 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1))
4187 && peep2_reg_dead_p (2, operands[0])"
4188 [(parallel [(set (match_dup 5)
4189 (call (mem:QI (match_dup 1))
4191 (clobber (reg:SI CRIS_SRP_REGNUM))
4193 (plus:SI (reg:SI CRIS_GOT_REGNUM)
4195 (unspec:SI [(match_dup 2)]
4196 CRIS_UNSPEC_PLTGOTREAD))))])]
4199 (define_peephole2 ; gotplt-to-plt-side
4202 (match_operand:SI 0 "register_operand" "")
4206 (reg:SI CRIS_GOT_REGNUM)
4208 (unspec:SI [(match_operand:SI
4209 2 "cris_general_operand_or_symbol" "")]
4210 CRIS_UNSPEC_PLTGOTREAD)))]))
4211 (set (match_operand:SI 3 "register_operand" "")
4212 (plus:SI (reg:SI CRIS_GOT_REGNUM)
4214 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
4216 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1))
4217 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
4219 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
4220 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
4221 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT)))
4222 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
4227 ;; comment-start: ";; "
4228 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
4229 ;; eval: (modify-syntax-entry ?[ "(]")
4230 ;; eval: (modify-syntax-entry ?] ")[")
4231 ;; eval: (modify-syntax-entry ?{ "(}")
4232 ;; eval: (modify-syntax-entry ?} "){")
4233 ;; eval: (setq indent-tabs-mode t)