1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
45 #include "target-def.h"
49 /* Usable when we have an amount to add or subtract, and want the
50 optimal size of the insn. */
51 #define ADDITIVE_SIZE_MODIFIER(size) \
52 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54 #define ASSERT_PLT_UNSPEC(x) \
55 CRIS_ASSERT (XINT (x, 1) == CRIS_UNSPEC_PLT \
56 && ((GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF) \
57 || GET_CODE (XVECEXP (x, 0, 0)) == LABEL_REF))
59 #define LOSE_AND_RETURN(msgid, x) \
62 cris_operand_lossage (msgid, x); \
66 enum cris_retinsn_type
67 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
69 /* Per-function machine data. */
70 struct machine_function GTY(())
72 int needs_return_address_on_stack;
74 /* This is the number of registers we save in the prologue due to
78 enum cris_retinsn_type return_type;
81 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
83 static char cris_output_insn_is_bound = 0;
85 /* In code for output macros, this is how we know whether e.g. constant
86 goes in code or in a static initializer. */
87 static int in_code = 0;
89 /* Fix for reg_overlap_mentioned_p. */
90 static int cris_reg_overlap_mentioned_p (rtx, rtx);
92 static void cris_print_base (rtx, FILE *);
94 static void cris_print_index (rtx, FILE *);
96 static void cris_output_addr_const (FILE *, rtx);
98 static struct machine_function * cris_init_machine_status (void);
100 static rtx cris_struct_value_rtx (tree, int);
102 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
103 tree type, int *, int);
105 static int cris_initial_frame_pointer_offset (void);
107 static int saved_regs_mentioned (rtx);
109 static void cris_operand_lossage (const char *, rtx);
111 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
113 static void cris_asm_output_mi_thunk
114 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
116 static void cris_file_start (void);
117 static void cris_init_libfuncs (void);
119 static bool cris_rtx_costs (rtx, int, int, int *);
120 static int cris_address_cost (rtx);
121 static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
123 static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
125 static tree cris_md_asm_clobbers (tree, tree, tree);
127 static bool cris_handle_option (size_t, const char *, int);
129 /* This is the parsed result of the "-max-stack-stackframe=" option. If
130 it (still) is zero, then there was no such option given. */
131 int cris_max_stackframe = 0;
133 /* This is the parsed result of the "-march=" option, if given. */
134 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
136 #undef TARGET_ASM_ALIGNED_HI_OP
137 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
138 #undef TARGET_ASM_ALIGNED_SI_OP
139 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
140 #undef TARGET_ASM_ALIGNED_DI_OP
141 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
143 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
144 available in ELF. These "normal" pseudos do not have any alignment
145 constraints or side-effects. */
146 #undef TARGET_ASM_UNALIGNED_HI_OP
147 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
149 #undef TARGET_ASM_UNALIGNED_SI_OP
150 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
152 #undef TARGET_ASM_UNALIGNED_DI_OP
153 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
155 #undef TARGET_ASM_OUTPUT_MI_THUNK
156 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
157 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
158 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
160 #undef TARGET_ASM_FILE_START
161 #define TARGET_ASM_FILE_START cris_file_start
163 #undef TARGET_INIT_LIBFUNCS
164 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
166 #undef TARGET_RTX_COSTS
167 #define TARGET_RTX_COSTS cris_rtx_costs
168 #undef TARGET_ADDRESS_COST
169 #define TARGET_ADDRESS_COST cris_address_cost
171 #undef TARGET_PROMOTE_FUNCTION_ARGS
172 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
173 #undef TARGET_STRUCT_VALUE_RTX
174 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
175 #undef TARGET_SETUP_INCOMING_VARARGS
176 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
177 #undef TARGET_PASS_BY_REFERENCE
178 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
179 #undef TARGET_ARG_PARTIAL_BYTES
180 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
181 #undef TARGET_MD_ASM_CLOBBERS
182 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
183 #undef TARGET_DEFAULT_TARGET_FLAGS
184 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
185 #undef TARGET_HANDLE_OPTION
186 #define TARGET_HANDLE_OPTION cris_handle_option
188 struct gcc_target targetm = TARGET_INITIALIZER;
190 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
193 cris_movem_load_rest_p (rtx op, int offs)
195 unsigned int reg_count = XVECLEN (op, 0) - offs;
201 unsigned int regno = 0;
203 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
204 other than (MEM reg). */
206 || GET_CODE (XVECEXP (op, 0, offs)) != SET
207 || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
208 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
211 /* Check a possible post-inc indicator. */
212 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
214 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
215 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
221 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
222 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
223 || !CONST_INT_P (inc)
224 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
231 /* FIXME: These two only for pre-v32. */
233 regno = reg_count - 1;
235 elt = XVECEXP (op, 0, offs);
236 src_addr = XEXP (SET_SRC (elt), 0);
238 if (GET_CODE (elt) != SET
239 || !REG_P (SET_DEST (elt))
240 || GET_MODE (SET_DEST (elt)) != SImode
241 || REGNO (SET_DEST (elt)) != regno
242 || !MEM_P (SET_SRC (elt))
243 || GET_MODE (SET_SRC (elt)) != SImode
244 || !memory_address_p (SImode, src_addr))
247 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
249 rtx elt = XVECEXP (op, 0, i);
252 if (GET_CODE (elt) != SET
253 || !REG_P (SET_DEST (elt))
254 || GET_MODE (SET_DEST (elt)) != SImode
255 || REGNO (SET_DEST (elt)) != regno
256 || !MEM_P (SET_SRC (elt))
257 || GET_MODE (SET_SRC (elt)) != SImode
258 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
259 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
260 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
261 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
268 /* Worker function for predicate for the parallel contents in a movem
272 cris_store_multiple_op_p (rtx op)
274 int reg_count = XVECLEN (op, 0);
285 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
286 other than (MEM reg) and (MEM (PLUS reg const)). */
290 elt = XVECEXP (op, 0, 0);
292 if (GET_CODE (elt) != SET)
295 dest = SET_DEST (elt);
297 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
300 dest_addr = XEXP (dest, 0);
302 /* Check a possible post-inc indicator. */
303 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
305 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
306 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
312 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
313 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
314 || !CONST_INT_P (inc)
315 /* Support increment by number of registers, and by the offset
316 of the destination, if it has the form (MEM (PLUS reg
318 || !((REG_P (dest_addr)
319 && REGNO (dest_addr) == REGNO (reg)
320 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
321 || (GET_CODE (dest_addr) == PLUS
322 && REG_P (XEXP (dest_addr, 0))
323 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
324 && CONST_INT_P (XEXP (dest_addr, 1))
325 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
333 /* FIXME: These two only for pre-v32. */
335 regno = reg_count - 1;
337 if (GET_CODE (elt) != SET
338 || !REG_P (SET_SRC (elt))
339 || GET_MODE (SET_SRC (elt)) != SImode
340 || REGNO (SET_SRC (elt)) != (unsigned int) regno
341 || !MEM_P (SET_DEST (elt))
342 || GET_MODE (SET_DEST (elt)) != SImode)
345 if (REG_P (dest_addr))
347 dest_base = dest_addr;
350 else if (GET_CODE (dest_addr) == PLUS
351 && REG_P (XEXP (dest_addr, 0))
352 && CONST_INT_P (XEXP (dest_addr, 1)))
354 dest_base = XEXP (dest_addr, 0);
355 offset = INTVAL (XEXP (dest_addr, 1));
360 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
362 rtx elt = XVECEXP (op, 0, i);
365 if (GET_CODE (elt) != SET
366 || !REG_P (SET_SRC (elt))
367 || GET_MODE (SET_SRC (elt)) != SImode
368 || REGNO (SET_SRC (elt)) != (unsigned int) regno
369 || !MEM_P (SET_DEST (elt))
370 || GET_MODE (SET_DEST (elt)) != SImode
371 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
372 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
373 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
374 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
381 /* The CONDITIONAL_REGISTER_USAGE worker. */
384 cris_conditional_register_usage (void)
386 /* FIXME: This isn't nice. We should be able to use that register for
387 something else if the PIC table isn't needed. */
389 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
390 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
392 if (TARGET_HAS_MUL_INSNS)
393 fixed_regs[CRIS_MOF_REGNUM] = 0;
395 /* On early versions, we must use the 16-bit condition-code register,
396 which has another name. */
397 if (cris_cpu_version < 8)
398 reg_names[CRIS_CC0_REGNUM] = "ccr";
401 /* Return current_function_uses_pic_offset_table. For use in cris.md,
402 since some generated files do not include function.h. */
405 cris_cfun_uses_pic_table (void)
407 return current_function_uses_pic_offset_table;
410 /* Given an rtx, return the text string corresponding to the CODE of X.
411 Intended for use in the assembly language output section of a
417 cris_output_insn_is_bound = 0;
418 switch (GET_CODE (x))
429 /* This function is for retrieving a part of an instruction name for
430 an operator, for immediate output. If that ever happens for
431 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
433 internal_error ("MULT case in cris_op_str");
469 /* Used to control the sign/zero-extend character for the 'E' modifier.
471 cris_output_insn_is_bound = 1;
476 return "Unknown operator";
481 /* Emit an error message when we're in an asm, and a fatal error for
482 "normal" insns. Formatted output isn't easily implemented, since we
483 use output_operand_lossage to output the actual message and handle the
484 categorization of the error. */
487 cris_operand_lossage (const char *msgid, rtx op)
490 output_operand_lossage ("%s", msgid);
493 /* Print an index part of an address to file. */
496 cris_print_index (rtx index, FILE *file)
498 /* Make the index "additive" unless we'll output a negative number, in
499 which case the sign character is free (as in free beer). */
500 if (!CONST_INT_P (index) || INTVAL (index) >= 0)
504 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
505 else if (CONSTANT_P (index))
506 cris_output_addr_const (file, index);
507 else if (GET_CODE (index) == MULT)
509 fprintf (file, "$%s.",
510 reg_names[REGNO (XEXP (index, 0))]);
512 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
514 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
516 rtx inner = XEXP (index, 0);
517 rtx inner_inner = XEXP (inner, 0);
519 if (GET_CODE (inner_inner) == POST_INC)
521 fprintf (file, "[$%s+].",
522 reg_names[REGNO (XEXP (inner_inner, 0))]);
523 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
527 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
529 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
532 else if (MEM_P (index))
534 rtx inner = XEXP (index, 0);
535 if (GET_CODE (inner) == POST_INC)
536 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
538 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
541 cris_operand_lossage ("unexpected index-type in cris_print_index",
545 /* Print a base rtx of an address to file. */
548 cris_print_base (rtx base, FILE *file)
551 fprintf (file, "$%s", reg_names[REGNO (base)]);
552 else if (GET_CODE (base) == POST_INC)
553 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
555 cris_operand_lossage ("unexpected base-type in cris_print_base",
559 /* Usable as a guard in expressions. */
562 cris_fatal (char *arg)
564 internal_error (arg);
566 /* We'll never get here; this is just to appease compilers. */
570 /* Return nonzero if REGNO is an ordinary register that *needs* to be
571 saved together with other registers, possibly by a MOVEM instruction,
572 or is saved for target-independent reasons. There may be
573 target-dependent reasons to save the register anyway; this is just a
574 wrapper for a complicated conditional. */
577 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
580 (((df_regs_ever_live_p (regno)
581 && !call_used_regs[regno])
582 || (regno == PIC_OFFSET_TABLE_REGNUM
584 /* It is saved anyway, if there would be a gap. */
586 && df_regs_ever_live_p (regno + 1)
587 && !call_used_regs[regno + 1]))))
588 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
589 && regno != CRIS_SRP_REGNUM)
590 || (current_function_calls_eh_return
591 && (regno == EH_RETURN_DATA_REGNO (0)
592 || regno == EH_RETURN_DATA_REGNO (1)
593 || regno == EH_RETURN_DATA_REGNO (2)
594 || regno == EH_RETURN_DATA_REGNO (3)));
597 /* Return nonzero if there are regs mentioned in the insn that are not all
598 in the call_used regs. This is part of the decision whether an insn
599 can be put in the epilogue. */
602 saved_regs_mentioned (rtx x)
608 /* Mainly stolen from refers_to_regno_p in rtlanal.c. */
616 return !call_used_regs[i];
619 /* If this is a SUBREG of a hard reg, we can see exactly which
620 registers are being modified. Otherwise, handle normally. */
621 i = REGNO (SUBREG_REG (x));
622 return !call_used_regs[i];
628 fmt = GET_RTX_FORMAT (code);
629 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
633 if (saved_regs_mentioned (XEXP (x, i)))
636 else if (fmt[i] == 'E')
639 for (j = XVECLEN (x, i) - 1; j >=0; j--)
640 if (saved_regs_mentioned (XEXP (x, i)))
648 /* The PRINT_OPERAND worker. */
651 cris_print_operand (FILE *file, rtx x, int code)
655 /* Size-strings corresponding to MULT expressions. */
656 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
658 /* New code entries should just be added to the switch below. If
659 handling is finished, just return. If handling was just a
660 modification of the operand, the modified operand should be put in
661 "operand", and then do a break to let default handling
662 (zero-modifier) output the operand. */
667 /* Print the unsigned supplied integer as if it were signed
668 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
670 || ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
671 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
672 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
673 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
677 /* Print assembler code for operator. */
678 fprintf (file, "%s", cris_op_str (operand));
683 /* A movem modifier working on a parallel; output the register
687 if (GET_CODE (x) != PARALLEL)
688 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
690 /* The second item can be (set reg (plus reg const)) to denote a
693 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
695 : XVECLEN (x, 0) - 1);
697 fprintf (file, "$%s", reg_names [regno]);
703 /* A similar movem modifier; output the memory operand. */
706 if (GET_CODE (x) != PARALLEL)
707 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
709 /* The lowest mem operand is in the first item, but perhaps it
710 needs to be output as postincremented. */
711 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
712 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
713 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
715 /* The second item can be a (set reg (plus reg const)) to denote
717 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
719 /* It's a post-increment, if the address is a naked (reg). */
721 addr = gen_rtx_POST_INC (SImode, addr);
724 /* Otherwise, it's a side-effect; RN=RN+M. */
725 fprintf (file, "[$%s=$%s%s%d]",
726 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
727 reg_names [REGNO (XEXP (addr, 0))],
728 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
729 (int) INTVAL (XEXP (addr, 1)));
733 output_address (addr);
738 /* Adjust a power of two to its log2. */
739 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
740 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
741 fprintf (file, "%d", exact_log2 (INTVAL (x)));
745 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
746 respectively. This modifier also terminates the inhibiting
747 effects of the 'x' modifier. */
748 cris_output_insn_is_bound = 0;
749 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
753 if (INTVAL (x) <= 255)
755 else if (INTVAL (x) <= 65535)
765 /* For a non-integer, print the size of the operand. */
766 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
767 ? 'd' : GET_MODE (x) == HImode ? 'w'
768 : GET_MODE (x) == QImode ? 'b'
769 /* If none of the above, emit an erroneous size letter. */
775 /* Const_int: print b for -127 <= x <= 255,
776 w for -32768 <= x <= 65535, else die. */
778 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
779 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
780 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
784 /* Output a 'nop' if there's nothing for the delay slot.
785 This method stolen from the sparc files. */
786 if (dbr_sequence_length () == 0)
787 fputs ("\n\tnop", file);
791 /* Output directive for alignment padded with "nop" insns.
792 Optimizing for size, it's plain 4-byte alignment, otherwise we
793 align the section to a cache-line (32 bytes) and skip at max 2
794 bytes, i.e. we skip if it's the last insn on a cache-line. The
795 latter is faster by a small amount (for two test-programs 99.6%
796 and 99.9%) and larger by a small amount (ditto 100.1% and
797 100.2%). This is supposed to be the simplest yet performance-
798 wise least intrusive way to make sure the immediately following
799 (supposed) muls/mulu insn isn't located at the end of a
803 ? ".p2alignw 2,0x050f\n\t"
804 : ".p2alignw 5,0x050f,2\n\t", file);
808 /* The PIC register. */
810 internal_error ("invalid use of ':' modifier");
811 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
815 /* Print high (most significant) part of something. */
816 switch (GET_CODE (operand))
819 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
820 value is kept here, and so may be other than 0 or -1. */
821 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
822 INTVAL (operand_subword (operand, 1, 0, DImode)));
826 /* High part of a long long constant. */
827 if (GET_MODE (operand) == VOIDmode)
829 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
833 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
836 /* Print reg + 1. Check that there's not an attempt to print
837 high-parts of registers like stack-pointer or higher. */
838 if (REGNO (operand) > STACK_POINTER_REGNUM - 2)
839 LOSE_AND_RETURN ("bad register", operand);
840 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
844 /* Adjust memory address to high part. */
846 rtx adj_mem = operand;
848 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
850 /* Adjust so we can use two SImode in DImode.
851 Calling adj_offsettable_operand will make sure it is an
852 offsettable address. Don't do this for a postincrement
853 though; it should remain as it was. */
854 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
856 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
858 output_address (XEXP (adj_mem, 0));
863 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
867 /* Strip the MEM expression. */
868 operand = XEXP (operand, 0);
872 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
873 iterators and attributes in cris.md to avoid the need for %x
874 and %E (and %e) and state passed between those modifiers. */
875 cris_output_insn_is_bound = 0;
878 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
879 cris_output_insn_is_bound is nonzero. */
880 if (GET_CODE (operand) != SIGN_EXTEND
881 && GET_CODE (operand) != ZERO_EXTEND
882 && !CONST_INT_P (operand))
883 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
885 if (cris_output_insn_is_bound)
887 cris_output_insn_is_bound = 0;
891 putc (GET_CODE (operand) == SIGN_EXTEND
892 || (CONST_INT_P (operand) && INTVAL (operand) < 0)
897 /* Print the size letter of the inner element. We can do it by
898 calling ourselves with the 's' modifier. */
899 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
900 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
901 cris_print_operand (file, XEXP (operand, 0), 's');
905 /* Print the least significant part of operand. */
906 if (GET_CODE (operand) == CONST_DOUBLE)
908 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
911 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
913 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
914 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
917 /* Otherwise the least significant part equals the normal part,
918 so handle it normally. */
922 /* When emitting an add for the high part of a DImode constant, we
923 want to use addq for 0 and adds.w for -1. */
924 if (!CONST_INT_P (operand))
925 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
926 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
930 /* If this is a GOT symbol, force it to be emitted as :GOT and
931 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
932 Avoid making this too much of a special case. */
933 if (flag_pic == 1 && CONSTANT_P (operand))
935 int flag_pic_save = flag_pic;
938 cris_output_addr_const (file, operand);
939 flag_pic = flag_pic_save;
945 /* When emitting an sub for the high part of a DImode constant, we
946 want to use subq for 0 and subs.w for -1. */
947 if (!CONST_INT_P (operand))
948 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
949 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
953 /* Print the operand as the index-part of an address.
954 Easiest way out is to use cris_print_index. */
955 cris_print_index (operand, file);
959 /* Print the size letter for an operand to a MULT, which must be a
960 const_int with a suitable value. */
961 if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
962 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
963 fprintf (file, "%s", mults[INTVAL (operand)]);
967 /* No code, print as usual. */
971 LOSE_AND_RETURN ("invalid operand modifier letter", x);
974 /* Print an operand as without a modifier letter. */
975 switch (GET_CODE (operand))
978 if (REGNO (operand) > 15
979 && REGNO (operand) != CRIS_MOF_REGNUM
980 && REGNO (operand) != CRIS_SRP_REGNUM
981 && REGNO (operand) != CRIS_CC0_REGNUM)
982 internal_error ("internal error: bad register: %d", REGNO (operand));
983 fprintf (file, "$%s", reg_names[REGNO (operand)]);
987 output_address (XEXP (operand, 0));
991 if (GET_MODE (operand) == VOIDmode)
992 /* A long long constant. */
993 output_addr_const (file, operand);
996 /* Only single precision is allowed as plain operands the
997 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1002 /* FIXME: Perhaps check overflow of the "single". */
1003 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1004 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1006 fprintf (file, "0x%lx", l);
1013 cris_output_addr_const (file, operand);
1019 /* For a (MULT (reg X) const_int) we output "rX.S". */
1020 int i = CONST_INT_P (XEXP (operand, 1))
1021 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1022 rtx reg = CONST_INT_P (XEXP (operand, 1))
1023 ? XEXP (operand, 0) : XEXP (operand, 1);
1026 || (!CONST_INT_P (XEXP (operand, 0))
1027 && !CONST_INT_P (XEXP (operand, 1))))
1028 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1030 cris_print_base (reg, file);
1031 fprintf (file, ".%c",
1032 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1034 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1040 /* No need to handle all strange variants, let output_addr_const
1042 if (CONSTANT_P (operand))
1044 cris_output_addr_const (file, operand);
1048 LOSE_AND_RETURN ("unexpected operand", x);
1052 /* The PRINT_OPERAND_ADDRESS worker. */
1055 cris_print_operand_address (FILE *file, rtx x)
1057 /* All these were inside MEM:s so output indirection characters. */
1060 if (CONSTANT_ADDRESS_P (x))
1061 cris_output_addr_const (file, x);
1062 else if (BASE_OR_AUTOINCR_P (x))
1063 cris_print_base (x, file);
1064 else if (GET_CODE (x) == PLUS)
1072 cris_print_base (x1, file);
1073 cris_print_index (x2, file);
1075 else if (BASE_P (x2))
1077 cris_print_base (x2, file);
1078 cris_print_index (x1, file);
1081 LOSE_AND_RETURN ("unrecognized address", x);
1085 /* A DIP. Output more indirection characters. */
1087 cris_print_base (XEXP (x, 0), file);
1091 LOSE_AND_RETURN ("unrecognized address", x);
1096 /* The RETURN_ADDR_RTX worker.
1097 We mark that the return address is used, either by EH or
1098 __builtin_return_address, for use by the function prologue and
1099 epilogue. FIXME: This isn't optimal; we just use the mark in the
1100 prologue and epilogue to say that the return address is to be stored
1101 in the stack frame. We could return SRP for leaf-functions and use the
1102 initial-value machinery. */
1105 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1107 cfun->machine->needs_return_address_on_stack = 1;
1109 /* The return-address is stored just above the saved frame-pointer (if
1110 present). Apparently we can't eliminate from the frame-pointer in
1111 that direction, so use the incoming args (maybe pretended) pointer. */
1113 ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1117 /* Accessor used in cris.md:return because cfun->machine isn't available
1121 cris_return_address_on_stack (void)
1123 return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1124 || cfun->machine->needs_return_address_on_stack;
1127 /* Accessor used in cris.md:return because cfun->machine isn't available
1131 cris_return_address_on_stack_for_return (void)
1133 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1134 : cris_return_address_on_stack ();
1137 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1138 handles FP -> SP elimination offset. */
1141 cris_initial_frame_pointer_offset (void)
1145 /* Initial offset is 0 if we don't have a frame pointer. */
1147 bool got_really_used = false;
1149 if (current_function_uses_pic_offset_table)
1151 push_topmost_sequence ();
1153 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1155 pop_topmost_sequence ();
1158 /* And 4 for each register pushed. */
1159 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1160 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1163 /* And then, last, we add the locals allocated. */
1164 offs += get_frame_size ();
1166 /* And more; the accumulated args size. */
1167 offs += current_function_outgoing_args_size;
1169 /* Then round it off, in case we use aligned stack. */
1170 if (TARGET_STACK_ALIGN)
1171 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1176 /* The INITIAL_ELIMINATION_OFFSET worker.
1177 Calculate the difference between imaginary registers such as frame
1178 pointer and the stack pointer. Used to eliminate the frame pointer
1179 and imaginary arg pointer. */
1182 cris_initial_elimination_offset (int fromreg, int toreg)
1185 = cris_initial_frame_pointer_offset ();
1187 /* We should be able to use regs_ever_live and related prologue
1188 information here, or alpha should not as well. */
1189 bool return_address_on_stack = cris_return_address_on_stack ();
1191 /* Here we act as if the frame-pointer were needed. */
1192 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1194 if (fromreg == ARG_POINTER_REGNUM
1195 && toreg == FRAME_POINTER_REGNUM)
1196 return ap_fp_offset;
1198 /* Between the frame pointer and the stack are only "normal" stack
1199 variables and saved registers. */
1200 if (fromreg == FRAME_POINTER_REGNUM
1201 && toreg == STACK_POINTER_REGNUM)
1202 return fp_sp_offset;
1204 /* We need to balance out the frame pointer here. */
1205 if (fromreg == ARG_POINTER_REGNUM
1206 && toreg == STACK_POINTER_REGNUM)
1207 return ap_fp_offset + fp_sp_offset - 4;
1212 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1215 cris_reload_address_legitimized (rtx x,
1216 enum machine_mode mode ATTRIBUTE_UNUSED,
1217 int opnum ATTRIBUTE_UNUSED,
1219 int ind_levels ATTRIBUTE_UNUSED)
1221 enum reload_type type = itype;
1226 if (GET_CODE (x) != PLUS)
1230 op0p = &XEXP (x, 0);
1232 op1p = &XEXP (x, 1);
1237 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1239 rtx op00 = XEXP (op0, 0);
1240 rtx op000 = XEXP (op00, 0);
1241 rtx *op000p = &XEXP (op00, 0);
1243 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1245 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1247 bool something_reloaded = false;
1249 if (GET_CODE (op000) == POST_INC
1250 && REG_P (XEXP (op000, 0))
1251 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1252 /* No, this gets too complicated and is too rare to care
1253 about trying to improve on the general code Here.
1254 As the return-value is an all-or-nothing indicator, we
1255 punt on the other register too. */
1259 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1261 /* The address of the inner mem is a pseudo or wrong
1262 reg: reload that. */
1263 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1264 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1265 something_reloaded = true;
1268 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1270 /* Base register is a pseudo or wrong reg: reload it. */
1271 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1272 GET_MODE (x), VOIDmode, 0, 0,
1274 something_reloaded = true;
1277 gcc_assert (something_reloaded);
1286 /* This function looks into the pattern to see how this insn affects
1289 Used when to eliminate test insns before a condition-code user,
1290 such as a "scc" insn or a conditional branch. This includes
1291 checking if the entities that cc was updated by, are changed by the
1294 Currently a jumble of the old peek-inside-the-insn and the newer
1295 check-cc-attribute methods. */
1298 cris_notice_update_cc (rtx exp, rtx insn)
1300 /* Check if user specified "-mcc-init" as a bug-workaround. FIXME:
1301 TARGET_CCINIT does not work; we must set CC_REVERSED as below.
1302 Several testcases will otherwise fail, for example
1303 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1310 /* Slowly, we're converting to using attributes to control the setting
1311 of condition-code status. */
1312 switch (get_attr_cc (insn))
1315 /* Even if it is "none", a setting may clobber a previous
1316 cc-value, so check. */
1317 if (GET_CODE (exp) == SET)
1319 if (cc_status.value1
1320 && modified_in_p (cc_status.value1, insn))
1321 cc_status.value1 = 0;
1323 if (cc_status.value2
1324 && modified_in_p (cc_status.value2, insn))
1325 cc_status.value2 = 0;
1334 /* Which means, for:
1339 CC is (reg) and (...) - unless (...) is 0, then CC does not change.
1340 CC_NO_OVERFLOW unless (...) is reg or mem.
1349 (set (reg1) (mem (bdap/biap)))
1350 (set (reg2) (bdap/biap))):
1351 CC is (reg1) and (mem (reg2))
1354 (set (mem (bdap/biap)) (reg1)) [or 0]
1355 (set (reg2) (bdap/biap))):
1358 (where reg and mem includes strict_low_parts variants thereof)
1360 For all others, assume CC is clobbered.
1361 Note that we do not have to care about setting CC_NO_OVERFLOW,
1362 since the overflow flag is set to 0 (i.e. right) for
1363 instructions where it does not have any sane sense, but where
1364 other flags have meanings. (This includes shifts; the carry is
1367 Note that there are other parallel constructs we could match,
1368 but we don't do that yet. */
1370 if (GET_CODE (exp) == SET)
1372 /* FIXME: Check when this happens. It looks like we should
1373 actually do a CC_STATUS_INIT here to be safe. */
1374 if (SET_DEST (exp) == pc_rtx)
1377 /* Record CC0 changes, so we do not have to output multiple
1379 if (SET_DEST (exp) == cc0_rtx)
1381 cc_status.value1 = SET_SRC (exp);
1382 cc_status.value2 = 0;
1384 /* Handle flags for the special btstq on one bit. */
1385 if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
1386 && XEXP (SET_SRC (exp), 1) == const1_rtx)
1388 if (CONST_INT_P (XEXP (SET_SRC (exp), 0)))
1390 cc_status.flags = CC_INVERTED;
1392 /* A one-bit btstq. */
1393 cc_status.flags = CC_Z_IN_NOT_N;
1396 cc_status.flags = 0;
1398 if (GET_CODE (SET_SRC (exp)) == COMPARE)
1400 if (!REG_P (XEXP (SET_SRC (exp), 0))
1401 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1402 /* For some reason gcc will not canonicalize compare
1403 operations, reversing the sign by itself if
1404 operands are in wrong order. */
1405 /* (But NOT inverted; eq is still eq.) */
1406 cc_status.flags = CC_REVERSED;
1408 /* This seems to be overlooked by gcc. FIXME: Check again.
1409 FIXME: Is it really safe? */
1411 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1412 XEXP (SET_SRC (exp), 0),
1413 XEXP (SET_SRC (exp), 1));
1417 else if (REG_P (SET_DEST (exp))
1418 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1419 && REG_P (XEXP (SET_DEST (exp), 0))))
1421 /* A register is set; normally CC is set to show that no
1422 test insn is needed. Catch the exceptions. */
1424 /* If not to cc0, then no "set"s in non-natural mode give
1426 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1427 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1429 /* ... except add:s and sub:s in DImode. */
1430 if (GET_MODE (SET_DEST (exp)) == DImode
1431 && (GET_CODE (SET_SRC (exp)) == PLUS
1432 || GET_CODE (SET_SRC (exp)) == MINUS))
1434 cc_status.flags = 0;
1435 cc_status.value1 = SET_DEST (exp);
1436 cc_status.value2 = SET_SRC (exp);
1438 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1440 cc_status.value2 = 0;
1442 /* Add and sub may set V, which gets us
1443 unoptimizable results in "gt" and "le" condition
1445 cc_status.flags |= CC_NO_OVERFLOW;
1450 else if (SET_SRC (exp) == const0_rtx)
1452 /* There's no CC0 change when clearing a register or
1453 memory. Just check for overlap. */
1454 if (cc_status.value1
1455 && modified_in_p (cc_status.value1, insn))
1456 cc_status.value1 = 0;
1458 if (cc_status.value2
1459 && modified_in_p (cc_status.value2, insn))
1460 cc_status.value2 = 0;
1466 cc_status.flags = 0;
1467 cc_status.value1 = SET_DEST (exp);
1468 cc_status.value2 = SET_SRC (exp);
1470 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1472 cc_status.value2 = 0;
1474 /* Some operations may set V, which gets us
1475 unoptimizable results in "gt" and "le" condition
1477 if (GET_CODE (SET_SRC (exp)) == PLUS
1478 || GET_CODE (SET_SRC (exp)) == MINUS
1479 || GET_CODE (SET_SRC (exp)) == NEG)
1480 cc_status.flags |= CC_NO_OVERFLOW;
1485 else if (MEM_P (SET_DEST (exp))
1486 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1487 && MEM_P (XEXP (SET_DEST (exp), 0))))
1489 /* When SET to MEM, then CC is not changed (except for
1491 if (cc_status.value1
1492 && modified_in_p (cc_status.value1, insn))
1493 cc_status.value1 = 0;
1495 if (cc_status.value2
1496 && modified_in_p (cc_status.value2, insn))
1497 cc_status.value2 = 0;
1502 else if (GET_CODE (exp) == PARALLEL)
1504 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1505 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1506 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1508 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1509 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1511 /* For "move.S [rx=ry+o],rz", say CC reflects
1512 value1=rz and value2=[rx] */
1513 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1515 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1516 XEXP (XVECEXP (exp, 0, 1), 0));
1517 cc_status.flags = 0;
1519 /* Huh? A side-effect cannot change the destination
1521 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1523 internal_error ("internal error: sideeffect-insn affecting main effect");
1526 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1527 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1528 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1530 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1531 say flags are not changed, except for overlap. */
1532 if (cc_status.value1
1533 && modified_in_p (cc_status.value1, insn))
1534 cc_status.value1 = 0;
1536 if (cc_status.value2
1537 && modified_in_p (cc_status.value2, insn))
1538 cc_status.value2 = 0;
1547 internal_error ("unknown cc_attr value");
1553 /* Return != 0 if the return sequence for the current function is short,
1554 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1555 registers must be saved, so return 0 then. */
1558 cris_simple_epilogue (void)
1561 unsigned int reglimit = STACK_POINTER_REGNUM;
1562 bool got_really_used = false;
1564 if (! reload_completed
1565 || frame_pointer_needed
1566 || get_frame_size () != 0
1567 || current_function_pretend_args_size
1568 || current_function_args_size
1569 || current_function_outgoing_args_size
1570 || current_function_calls_eh_return
1572 /* If we're not supposed to emit prologue and epilogue, we must
1573 not emit return-type instructions. */
1574 || !TARGET_PROLOGUE_EPILOGUE)
1577 if (current_function_uses_pic_offset_table)
1579 push_topmost_sequence ();
1581 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1582 pop_topmost_sequence ();
1585 /* No simple epilogue if there are saved registers. */
1586 for (regno = 0; regno < reglimit; regno++)
1587 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1593 /* Expand a return insn (just one insn) marked as using SRP or stack
1594 slot depending on parameter ON_STACK. */
1597 cris_expand_return (bool on_stack)
1599 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1600 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1601 GCC expect just (return) to do the right thing when optimizing, so
1602 we do that until they're fixed. Currently, all return insns in a
1603 function must be the same (not really a limiting factor) so we need
1604 to check that it doesn't change half-way through. */
1605 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1607 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1608 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1610 cfun->machine->return_type
1611 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1614 /* Compute a (partial) cost for rtx X. Return true if the complete
1615 cost has been computed, and false if subexpressions should be
1616 scanned. In either case, *TOTAL contains the cost result. */
1619 cris_rtx_costs (rtx x, int code, int outer_code, int *total)
1625 HOST_WIDE_INT val = INTVAL (x);
1628 else if (val < 32 && val >= -32)
1630 /* Eight or 16 bits are a word and cycle more expensive. */
1631 else if (val <= 32767 && val >= -32768)
1633 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1634 another word. FIXME: This isn't linear to 16 bits. */
1650 if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1653 /* Make 0.0 cheap, else test-insns will not be used. */
1658 /* Identify values that are no powers of two. Powers of 2 are
1659 taken care of already and those values should not be changed. */
1660 if (!CONST_INT_P (XEXP (x, 1))
1661 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1663 /* If we have a multiply insn, then the cost is between
1664 1 and 2 "fast" instructions. */
1665 if (TARGET_HAS_MUL_INSNS)
1667 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1671 /* Estimate as 4 + 4 * #ofbits. */
1672 *total = COSTS_N_INSNS (132);
1681 if (!CONST_INT_P (XEXP (x, 1))
1682 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1684 /* Estimate this as 4 + 8 * #of bits. */
1685 *total = COSTS_N_INSNS (260);
1691 if (CONST_INT_P (XEXP (x, 1))
1692 /* Two constants may actually happen before optimization. */
1693 && !CONST_INT_P (XEXP (x, 0))
1694 && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1696 *total = (rtx_cost (XEXP (x, 0), outer_code) + 2
1697 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1702 case ZERO_EXTEND: case SIGN_EXTEND:
1703 *total = rtx_cost (XEXP (x, 0), outer_code);
1711 /* The ADDRESS_COST worker. */
1714 cris_address_cost (rtx x)
1716 /* The metric to use for the cost-macros is unclear.
1717 The metric used here is (the number of cycles needed) / 2,
1718 where we consider equal a cycle for a word of code and a cycle to
1721 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1722 if (BASE_OR_AUTOINCR_P (x))
1725 /* An indirect mem must be a DIP. This means two bytes extra for code,
1726 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1730 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1731 an extra DIP prefix and 4 bytes of constant in most cases. */
1735 /* Handle BIAP and BDAP prefixes. */
1736 if (GET_CODE (x) == PLUS)
1738 rtx tem1 = XEXP (x, 0);
1739 rtx tem2 = XEXP (x, 1);
1741 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1742 recognize the typical MULT which is always in tem1 because of
1743 insn canonicalization. */
1744 if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1748 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1749 PLUS is always found in tem2. */
1750 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1753 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1755 if (CONST_INT_P (tem2) && CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1758 /* A BDAP with some other constant is 2 bytes extra. */
1759 if (CONSTANT_P (tem2))
1760 return (2 + 2 + 2) / 2;
1762 /* BDAP with something indirect should have a higher cost than
1763 BIAP with register. FIXME: Should it cost like a MEM or more? */
1764 /* Don't need to check it, it's the only one left.
1765 FIXME: There was a REG test missing, perhaps there are others.
1767 return (2 + 2 + 2) / 2;
1770 /* What else? Return a high cost. It matters only for valid
1771 addressing modes. */
1775 /* Check various objections to the side-effect. Used in the test-part
1776 of an anonymous insn describing an insn with a possible side-effect.
1777 Returns nonzero if the implied side-effect is ok.
1780 ops : An array of rtx:es. lreg, rreg, rval,
1781 The variables multop and other_op are indexes into this,
1782 or -1 if they are not applicable.
1783 lreg : The register that gets assigned in the side-effect.
1784 rreg : One register in the side-effect expression
1785 rval : The other register, or an int.
1786 multop : An integer to multiply rval with.
1787 other_op : One of the entities of the main effect,
1788 whose mode we must consider. */
1791 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
1792 int lreg, int rreg, int rval,
1793 int multop, int other_op)
1795 /* Find what value to multiply with, for rx =ry + rz * n. */
1796 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
1798 rtx reg_rtx = ops[rreg];
1799 rtx val_rtx = ops[rval];
1801 /* The operands may be swapped. Canonicalize them in reg_rtx and
1802 val_rtx, where reg_rtx always is a reg (for this constraint to
1804 if (! BASE_P (reg_rtx))
1805 reg_rtx = val_rtx, val_rtx = ops[rreg];
1807 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
1808 we have no business. */
1809 if (! BASE_P (reg_rtx))
1812 /* Don't do this when -mno-split. */
1813 if (!TARGET_SIDE_EFFECT_PREFIXES)
1816 /* The mult expression may be hidden in lreg. FIXME: Add more
1817 commentary about that. */
1818 if (GET_CODE (val_rtx) == MULT)
1820 mult = INTVAL (XEXP (val_rtx, 1));
1821 val_rtx = XEXP (val_rtx, 0);
1825 /* First check the "other operand". */
1828 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
1831 /* Check if the lvalue register is the same as the "other
1832 operand". If so, the result is undefined and we shouldn't do
1833 this. FIXME: Check again. */
1834 if ((BASE_P (ops[lreg])
1835 && BASE_P (ops[other_op])
1836 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
1837 || rtx_equal_p (ops[other_op], ops[lreg]))
1841 /* Do not accept frame_pointer_rtx as any operand. */
1842 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
1843 || ops[rval] == frame_pointer_rtx
1844 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
1848 && ! BASE_P (val_rtx))
1851 /* Do not allow rx = rx + n if a normal add or sub with same size
1853 if (rtx_equal_p (ops[lreg], reg_rtx)
1854 && CONST_INT_P (val_rtx)
1855 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
1858 /* Check allowed cases, like [r(+)?].[bwd] and const. */
1859 if (CONSTANT_P (val_rtx))
1862 if (MEM_P (val_rtx) && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
1865 if (GET_CODE (val_rtx) == SIGN_EXTEND
1866 && MEM_P (XEXP (val_rtx, 0))
1867 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
1870 /* If we got here, it's not a valid addressing mode. */
1873 else if (code == MULT
1874 || (code == PLUS && BASE_P (val_rtx)))
1876 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
1877 if (rtx_equal_p (ops[lreg], reg_rtx)
1878 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
1881 /* Do not allow bad multiply-values. */
1882 if (mult != 1 && mult != 2 && mult != 4)
1885 /* Only allow r + ... */
1886 if (! BASE_P (reg_rtx))
1889 /* If we got here, all seems ok.
1890 (All checks need to be done above). */
1894 /* If we get here, the caller got its initial tests wrong. */
1895 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
1898 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
1899 does not handle the case where the IN operand is strict_low_part; it
1900 does handle it for X. Test-case in Axis-20010516. This function takes
1901 care of that for THIS port. FIXME: strict_low_part is going away
1905 cris_reg_overlap_mentioned_p (rtx x, rtx in)
1907 /* The function reg_overlap_mentioned now handles when X is
1908 strict_low_part, but not when IN is a STRICT_LOW_PART. */
1909 if (GET_CODE (in) == STRICT_LOW_PART)
1912 return reg_overlap_mentioned_p (x, in);
1915 /* The TARGET_ASM_NAMED_SECTION worker.
1916 We just dispatch to the functions for ELF and a.out. */
1919 cris_target_asm_named_section (const char *name, unsigned int flags,
1923 default_no_named_section (name, flags, decl);
1925 default_elf_asm_named_section (name, flags, decl);
1928 /* Return TRUE iff X is a CONST valid for e.g. indexing. */
1931 cris_valid_pic_const (rtx x)
1933 gcc_assert (flag_pic);
1935 switch (GET_CODE (x))
1944 if (GET_CODE (x) != CONST)
1949 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
1950 if (GET_CODE (x) == PLUS
1951 && GET_CODE (XEXP (x, 0)) == UNSPEC
1952 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
1953 && CONST_INT_P (XEXP (x, 1)))
1956 if (GET_CODE (x) == UNSPEC)
1957 switch (XINT (x, 1))
1959 case CRIS_UNSPEC_PLT:
1960 case CRIS_UNSPEC_PLTGOTREAD:
1961 case CRIS_UNSPEC_GOTREAD:
1962 case CRIS_UNSPEC_GOTREL:
1968 return cris_pic_symbol_type_of (x) == cris_no_symbol;
1971 /* Helper function to find the right PIC-type symbol to generate,
1972 given the original (non-PIC) representation. */
1974 enum cris_pic_symbol_type
1975 cris_pic_symbol_type_of (rtx x)
1977 switch (GET_CODE (x))
1980 return SYMBOL_REF_LOCAL_P (x)
1981 ? cris_gotrel_symbol : cris_got_symbol;
1984 return cris_gotrel_symbol;
1987 return cris_pic_symbol_type_of (XEXP (x, 0));
1992 enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
1993 enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
1995 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
1997 if (t1 == cris_got_symbol || t1 == cris_got_symbol)
1998 return cris_got_symbol_needing_fixup;
2000 return t1 != cris_no_symbol ? t1 : t2;
2005 return cris_no_symbol;
2008 /* Likely an offsettability-test attempting to add a constant to
2009 a GOTREAD symbol, which can't be handled. */
2010 return cris_invalid_pic_symbol;
2013 fatal_insn ("unrecognized supposed constant", x);
2019 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2022 cris_legitimate_pic_operand (rtx x)
2024 /* Symbols are not valid PIC operands as-is; just constants. */
2025 return cris_valid_pic_const (x);
2028 /* TARGET_HANDLE_OPTION worker. We just store the values into local
2029 variables here. Checks for correct semantics are in
2030 cris_override_options. */
2033 cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
2034 int value ATTRIBUTE_UNUSED)
2042 + MASK_ALIGN_BY_32);
2045 case OPT_mno_etrax100:
2049 + MASK_ALIGN_BY_32);
2055 |= (MASK_STACK_ALIGN
2058 + MASK_ALIGN_BY_32);
2064 |= (MASK_STACK_ALIGN
2072 &= ~(MASK_STACK_ALIGN
2081 CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2086 /* The OVERRIDE_OPTIONS worker.
2087 As is the norm, this also parses -mfoo=bar type parameters. */
2090 cris_override_options (void)
2092 if (cris_max_stackframe_str)
2094 cris_max_stackframe = atoi (cris_max_stackframe_str);
2096 /* Do some sanity checking. */
2097 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2098 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2099 cris_max_stackframe, 0x20000000);
2102 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2103 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2104 cris_cpu_version = CRIS_CPU_SVINTO;
2105 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2106 cris_cpu_version = CRIS_CPU_ETRAX4;
2108 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2112 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2114 if (strcmp ("etrax4", cris_cpu_str) == 0)
2115 cris_cpu_version = 3;
2117 if (strcmp ("svinto", cris_cpu_str) == 0
2118 || strcmp ("etrax100", cris_cpu_str) == 0)
2119 cris_cpu_version = 8;
2121 if (strcmp ("ng", cris_cpu_str) == 0
2122 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2123 cris_cpu_version = 10;
2125 if (cris_cpu_version < 0 || cris_cpu_version > 10)
2126 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2129 /* Set the target flags. */
2130 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2131 target_flags |= MASK_ETRAX4_ADD;
2133 /* If this is Svinto or higher, align for 32 bit accesses. */
2134 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2136 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2137 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2140 /* Note that we do not add new flags when it can be completely
2141 described with a macro that uses -mcpu=X. So
2142 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2148 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2150 if (strcmp ("etrax4", cris_tune_str) == 0)
2153 if (strcmp ("svinto", cris_tune_str) == 0
2154 || strcmp ("etrax100", cris_tune_str) == 0)
2157 if (strcmp ("ng", cris_tune_str) == 0
2158 || strcmp ("etrax100lx", cris_tune_str) == 0)
2161 if (cris_tune < 0 || cris_tune > 10)
2162 error ("unknown CRIS cpu version specification in -mtune= : %s",
2165 if (cris_tune >= CRIS_CPU_SVINTO)
2166 /* We have currently nothing more to tune than alignment for
2169 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2170 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2175 /* Use error rather than warning, so invalid use is easily
2176 detectable. Still change to the values we expect, to avoid
2180 error ("-fPIC and -fpic are not supported in this configuration");
2184 /* Turn off function CSE. We need to have the addresses reach the
2185 call expanders to get PLT-marked, as they could otherwise be
2186 compared against zero directly or indirectly. After visiting the
2187 call expanders they will then be cse:ed, as the call expanders
2188 force_reg the addresses, effectively forcing flag_no_function_cse
2190 flag_no_function_cse = 1;
2193 if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2195 warning (0, "that particular -g option is invalid with -maout and -melinux");
2196 write_symbols = DBX_DEBUG;
2199 /* Set the per-function-data initializer. */
2200 init_machine_status = cris_init_machine_status;
2203 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2206 cris_asm_output_mi_thunk (FILE *stream,
2207 tree thunkdecl ATTRIBUTE_UNUSED,
2208 HOST_WIDE_INT delta,
2209 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2213 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2214 ADDITIVE_SIZE_MODIFIER (delta), delta,
2215 reg_names[CRIS_FIRST_ARG_REG]);
2217 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2218 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2219 reg_names[CRIS_FIRST_ARG_REG]);
2223 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2225 name = (* targetm.strip_name_encoding) (name);
2226 fprintf (stream, "add.d ");
2227 assemble_name (stream, name);
2228 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2232 fprintf (stream, "jump ");
2233 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2234 fprintf (stream, "\n");
2238 /* Boilerplate emitted at start of file.
2240 NO_APP *only at file start* means faster assembly. It also means
2241 comments are not allowed. In some cases comments will be output
2242 for debugging purposes. Make sure they are allowed then.
2244 We want a .file directive only if TARGET_ELF. */
2246 cris_file_start (void)
2248 /* These expressions can vary at run time, so we cannot put
2249 them into TARGET_INITIALIZER. */
2250 targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2251 targetm.file_start_file_directive = TARGET_ELF;
2253 default_file_start ();
2256 /* Rename the function calls for integer multiply and divide. */
2258 cris_init_libfuncs (void)
2260 set_optab_libfunc (smul_optab, SImode, "__Mul");
2261 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2262 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2263 set_optab_libfunc (smod_optab, SImode, "__Mod");
2264 set_optab_libfunc (umod_optab, SImode, "__Umod");
2267 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2271 cris_init_expanders (void)
2273 /* Nothing here at the moment. */
2276 /* Zero initialization is OK for all current fields. */
2278 static struct machine_function *
2279 cris_init_machine_status (void)
2281 return ggc_alloc_cleared (sizeof (struct machine_function));
2284 /* Split a 2 word move (DI or presumably DF) into component parts.
2285 Originally a copy of gen_split_move_double in m32r.c. */
2288 cris_split_movdx (rtx *operands)
2290 enum machine_mode mode = GET_MODE (operands[0]);
2291 rtx dest = operands[0];
2292 rtx src = operands[1];
2295 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2296 longer happen; after reload there are no SUBREGs any more, and we're
2297 only called after reload. */
2298 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2303 int dregno = REGNO (dest);
2305 /* Reg-to-reg copy. */
2308 int sregno = REGNO (src);
2310 int reverse = (dregno == sregno + 1);
2312 /* We normally copy the low-numbered register first. However, if
2313 the first register operand 0 is the same as the second register of
2314 operand 1, we must copy in the opposite order. */
2315 emit_insn (gen_rtx_SET (VOIDmode,
2316 operand_subword (dest, reverse, TRUE, mode),
2317 operand_subword (src, reverse, TRUE, mode)));
2319 emit_insn (gen_rtx_SET (VOIDmode,
2320 operand_subword (dest, !reverse, TRUE, mode),
2321 operand_subword (src, !reverse, TRUE, mode)));
2323 /* Constant-to-reg copy. */
2324 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2327 split_double (src, &words[0], &words[1]);
2328 emit_insn (gen_rtx_SET (VOIDmode,
2329 operand_subword (dest, 0, TRUE, mode),
2332 emit_insn (gen_rtx_SET (VOIDmode,
2333 operand_subword (dest, 1, TRUE, mode),
2336 /* Mem-to-reg copy. */
2337 else if (MEM_P (src))
2339 /* If the high-address word is used in the address, we must load it
2340 last. Otherwise, load it first. */
2341 rtx addr = XEXP (src, 0);
2343 = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2345 /* The original code implies that we can't do
2346 move.x [rN+],rM move.x [rN],rM+1
2347 when rN is dead, because of REG_NOTES damage. That is
2348 consistent with what I've seen, so don't try it.
2350 We have two different cases here; if the addr is POST_INC,
2351 just pass it through, otherwise add constants. */
2353 if (GET_CODE (addr) == POST_INC)
2358 /* Whenever we emit insns with post-incremented
2359 addresses ourselves, we must add a post-inc note
2361 mem = change_address (src, SImode, addr);
2363 = gen_rtx_SET (VOIDmode,
2364 operand_subword (dest, 0, TRUE, mode), mem);
2365 insn = emit_insn (insn);
2366 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2368 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2371 mem = change_address (src, SImode, addr);
2373 = gen_rtx_SET (VOIDmode,
2374 operand_subword (dest, 1, TRUE, mode), mem);
2375 insn = emit_insn (insn);
2376 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2378 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2383 /* Make sure we don't get any other addresses with
2384 embedded postincrements. They should be stopped in
2385 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2387 if (side_effects_p (addr))
2388 fatal_insn ("unexpected side-effects in address", addr);
2390 emit_insn (gen_rtx_SET
2392 operand_subword (dest, reverse, TRUE, mode),
2395 plus_constant (addr,
2396 reverse * UNITS_PER_WORD))));
2397 emit_insn (gen_rtx_SET
2399 operand_subword (dest, ! reverse, TRUE, mode),
2402 plus_constant (addr,
2408 internal_error ("Unknown src");
2410 /* Reg-to-mem copy or clear mem. */
2411 else if (MEM_P (dest)
2413 || src == const0_rtx
2414 || src == CONST0_RTX (DFmode)))
2416 rtx addr = XEXP (dest, 0);
2418 if (GET_CODE (addr) == POST_INC)
2423 /* Whenever we emit insns with post-incremented addresses
2424 ourselves, we must add a post-inc note manually. */
2425 mem = change_address (dest, SImode, addr);
2427 = gen_rtx_SET (VOIDmode,
2428 mem, operand_subword (src, 0, TRUE, mode));
2429 insn = emit_insn (insn);
2430 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2432 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2435 mem = change_address (dest, SImode, addr);
2437 = gen_rtx_SET (VOIDmode,
2439 operand_subword (src, 1, TRUE, mode));
2440 insn = emit_insn (insn);
2441 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2443 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2448 /* Make sure we don't get any other addresses with embedded
2449 postincrements. They should be stopped in
2450 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2451 if (side_effects_p (addr))
2452 fatal_insn ("unexpected side-effects in address", addr);
2454 emit_insn (gen_rtx_SET
2456 change_address (dest, SImode, addr),
2457 operand_subword (src, 0, TRUE, mode)));
2459 emit_insn (gen_rtx_SET
2461 change_address (dest, SImode,
2462 plus_constant (addr,
2464 operand_subword (src, 1, TRUE, mode)));
2469 internal_error ("Unknown dest");
2476 /* The expander for the prologue pattern name. */
2479 cris_expand_prologue (void)
2482 int size = get_frame_size ();
2483 /* Shorten the used name for readability. */
2484 int cfoa_size = current_function_outgoing_args_size;
2485 int last_movem_reg = -1;
2488 int return_address_on_stack = cris_return_address_on_stack ();
2489 int got_really_used = false;
2490 int n_movem_regs = 0;
2491 int pretend = current_function_pretend_args_size;
2493 /* Don't do anything if no prologues or epilogues are wanted. */
2494 if (!TARGET_PROLOGUE_EPILOGUE)
2497 CRIS_ASSERT (size >= 0);
2499 if (current_function_uses_pic_offset_table)
2501 /* A reference may have been optimized out (like the abort () in
2502 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2504 push_topmost_sequence ();
2506 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2507 pop_topmost_sequence ();
2510 /* Align the size to what's best for the CPU model. */
2511 if (TARGET_STACK_ALIGN)
2512 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2516 /* See also cris_setup_incoming_varargs where
2517 cfun->machine->stdarg_regs is set. There are other setters of
2518 current_function_pretend_args_size than stdarg handling, like
2519 for an argument passed with parts in R13 and stack. We must
2520 not store R13 into the pretend-area for that case, as GCC does
2521 that itself. "Our" store would be marked as redundant and GCC
2522 will attempt to remove it, which will then be flagged as an
2523 internal error; trying to remove a frame-related insn. */
2524 int stdarg_regs = cfun->machine->stdarg_regs;
2526 framesize += pretend;
2528 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2530 regno--, pretend -= 4, stdarg_regs--)
2532 insn = emit_insn (gen_rtx_SET (VOIDmode,
2534 plus_constant (stack_pointer_rtx,
2536 /* FIXME: When dwarf2 frame output and unless asynchronous
2537 exceptions, make dwarf2 bundle together all stack
2538 adjustments like it does for registers between stack
2540 RTX_FRAME_RELATED_P (insn) = 1;
2542 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2543 set_mem_alias_set (mem, get_varargs_alias_set ());
2544 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2546 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2547 the value isn't restored, so we don't want to tell dwarf2
2548 that it's been stored to stack, else EH handling info would
2552 /* For other setters of current_function_pretend_args_size, we
2553 just adjust the stack by leaving the remaining size in
2554 "pretend", handled below. */
2557 /* Save SRP if not a leaf function. */
2558 if (return_address_on_stack)
2560 insn = emit_insn (gen_rtx_SET (VOIDmode,
2562 plus_constant (stack_pointer_rtx,
2565 RTX_FRAME_RELATED_P (insn) = 1;
2567 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2568 set_mem_alias_set (mem, get_frame_alias_set ());
2569 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2570 RTX_FRAME_RELATED_P (insn) = 1;
2574 /* Set up the frame pointer, if needed. */
2575 if (frame_pointer_needed)
2577 insn = emit_insn (gen_rtx_SET (VOIDmode,
2579 plus_constant (stack_pointer_rtx,
2582 RTX_FRAME_RELATED_P (insn) = 1;
2584 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2585 set_mem_alias_set (mem, get_frame_alias_set ());
2586 insn = emit_move_insn (mem, frame_pointer_rtx);
2587 RTX_FRAME_RELATED_P (insn) = 1;
2589 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2590 RTX_FRAME_RELATED_P (insn) = 1;
2595 /* Between frame-pointer and saved registers lie the area for local
2596 variables. If we get here with "pretended" size remaining, count
2597 it into the general stack size. */
2600 /* Get a contiguous sequence of registers, starting with R0, that need
2602 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2604 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2608 /* Check if movem may be used for registers so far. */
2609 if (regno == last_movem_reg + 1)
2610 /* Yes, update next expected register. */
2611 last_movem_reg = regno;
2614 /* We cannot use movem for all registers. We have to flush
2615 any movem:ed registers we got so far. */
2616 if (last_movem_reg != -1)
2619 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2621 /* It is a win to use a side-effect assignment for
2622 64 <= size <= 128. But side-effect on movem was
2623 not usable for CRIS v0..3. Also only do it if
2624 side-effects insns are allowed. */
2625 if ((last_movem_reg + 1) * 4 + size >= 64
2626 && (last_movem_reg + 1) * 4 + size <= 128
2627 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2628 && TARGET_SIDE_EFFECT_PREFIXES)
2631 = gen_rtx_MEM (SImode,
2632 plus_constant (stack_pointer_rtx,
2633 -(n_saved * 4 + size)));
2634 set_mem_alias_set (mem, get_frame_alias_set ());
2636 = cris_emit_movem_store (mem, GEN_INT (n_saved),
2637 -(n_saved * 4 + size),
2643 = gen_rtx_SET (VOIDmode,
2645 plus_constant (stack_pointer_rtx,
2646 -(n_saved * 4 + size)));
2647 insn = emit_insn (insn);
2648 RTX_FRAME_RELATED_P (insn) = 1;
2650 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2651 set_mem_alias_set (mem, get_frame_alias_set ());
2652 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2656 framesize += n_saved * 4 + size;
2657 last_movem_reg = -1;
2661 insn = emit_insn (gen_rtx_SET (VOIDmode,
2663 plus_constant (stack_pointer_rtx,
2665 RTX_FRAME_RELATED_P (insn) = 1;
2667 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2668 set_mem_alias_set (mem, get_frame_alias_set ());
2669 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2670 RTX_FRAME_RELATED_P (insn) = 1;
2672 framesize += 4 + size;
2678 /* Check after, if we could movem all registers. This is the normal case. */
2679 if (last_movem_reg != -1)
2682 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2684 /* Side-effect on movem was not usable for CRIS v0..3. Also only
2685 do it if side-effects insns are allowed. */
2686 if ((last_movem_reg + 1) * 4 + size >= 64
2687 && (last_movem_reg + 1) * 4 + size <= 128
2688 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2689 && TARGET_SIDE_EFFECT_PREFIXES)
2692 = gen_rtx_MEM (SImode,
2693 plus_constant (stack_pointer_rtx,
2694 -(n_saved * 4 + size)));
2695 set_mem_alias_set (mem, get_frame_alias_set ());
2696 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2697 -(n_saved * 4 + size), true);
2702 = gen_rtx_SET (VOIDmode,
2704 plus_constant (stack_pointer_rtx,
2705 -(n_saved * 4 + size)));
2706 insn = emit_insn (insn);
2707 RTX_FRAME_RELATED_P (insn) = 1;
2709 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2710 set_mem_alias_set (mem, get_frame_alias_set ());
2711 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
2714 framesize += n_saved * 4 + size;
2715 /* We have to put outgoing argument space after regs. */
2718 insn = emit_insn (gen_rtx_SET (VOIDmode,
2720 plus_constant (stack_pointer_rtx,
2722 RTX_FRAME_RELATED_P (insn) = 1;
2723 framesize += cfoa_size;
2726 else if ((size + cfoa_size) > 0)
2728 insn = emit_insn (gen_rtx_SET (VOIDmode,
2730 plus_constant (stack_pointer_rtx,
2731 -(cfoa_size + size))));
2732 RTX_FRAME_RELATED_P (insn) = 1;
2733 framesize += size + cfoa_size;
2736 /* Set up the PIC register, if it is used. */
2737 if (got_really_used)
2740 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
2741 emit_move_insn (pic_offset_table_rtx, got);
2743 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
2744 follow exceptional paths and tries to delete the GOT load as
2745 unused, if it isn't used on the non-exceptional paths. Other
2746 ports have similar or other cover-ups, or plain bugs marking
2747 the GOT register load as maybe-dead. To see this, remove the
2748 line below and try libsupc++/vec.cc or a trivial
2749 "static void y (); void x () {try {y ();} catch (...) {}}". */
2750 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2753 if (cris_max_stackframe && framesize > cris_max_stackframe)
2754 warning (0, "stackframe too big: %d bytes", framesize);
2757 /* The expander for the epilogue pattern. */
2760 cris_expand_epilogue (void)
2763 int size = get_frame_size ();
2764 int last_movem_reg = -1;
2765 int argspace_offset = current_function_outgoing_args_size;
2766 int pretend = current_function_pretend_args_size;
2768 bool return_address_on_stack = cris_return_address_on_stack ();
2769 /* A reference may have been optimized out
2770 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2771 so check that it's still used. */
2772 int got_really_used = false;
2773 int n_movem_regs = 0;
2775 if (!TARGET_PROLOGUE_EPILOGUE)
2778 if (current_function_uses_pic_offset_table)
2780 /* A reference may have been optimized out (like the abort () in
2781 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2783 push_topmost_sequence ();
2785 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2786 pop_topmost_sequence ();
2789 /* Align byte count of stack frame. */
2790 if (TARGET_STACK_ALIGN)
2791 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2793 /* Check how many saved regs we can movem. They start at r0 and must
2796 regno < FIRST_PSEUDO_REGISTER;
2798 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2802 if (regno == last_movem_reg + 1)
2803 last_movem_reg = regno;
2808 /* If there was only one register that really needed to be saved
2809 through movem, don't use movem. */
2810 if (n_movem_regs == 1)
2811 last_movem_reg = -1;
2813 /* Now emit "normal" move insns for all regs higher than the movem
2815 for (regno = FIRST_PSEUDO_REGISTER - 1;
2816 regno > last_movem_reg;
2818 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2822 if (argspace_offset)
2824 /* There is an area for outgoing parameters located before
2825 the saved registers. We have to adjust for that. */
2826 emit_insn (gen_rtx_SET (VOIDmode,
2828 plus_constant (stack_pointer_rtx,
2830 /* Make sure we only do this once. */
2831 argspace_offset = 0;
2834 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2835 stack_pointer_rtx));
2836 set_mem_alias_set (mem, get_frame_alias_set ());
2837 insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
2839 /* Whenever we emit insns with post-incremented addresses
2840 ourselves, we must add a post-inc note manually. */
2842 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2845 /* If we have any movem-restore, do it now. */
2846 if (last_movem_reg != -1)
2850 if (argspace_offset)
2852 emit_insn (gen_rtx_SET (VOIDmode,
2854 plus_constant (stack_pointer_rtx,
2856 argspace_offset = 0;
2859 mem = gen_rtx_MEM (SImode,
2860 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
2861 set_mem_alias_set (mem, get_frame_alias_set ());
2863 = emit_insn (cris_gen_movem_load (mem,
2864 GEN_INT (last_movem_reg + 1), 0));
2865 /* Whenever we emit insns with post-incremented addresses
2866 ourselves, we must add a post-inc note manually. */
2867 if (side_effects_p (PATTERN (insn)))
2869 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2872 /* If we don't clobber all of the allocated stack area (we've already
2873 deallocated saved registers), GCC might want to schedule loads from
2874 the stack to *after* the stack-pointer restore, which introduces an
2875 interrupt race condition. This happened for the initial-value
2876 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
2877 other failure for that test). It also happened for the stack slot
2878 for the return value in (one version of)
2879 linux/fs/dcache.c:__d_lookup, at least with "-O2
2880 -fno-omit-frame-pointer". */
2882 /* Restore frame pointer if necessary. */
2883 if (frame_pointer_needed)
2887 emit_insn (gen_cris_frame_deallocated_barrier ());
2889 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
2890 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2891 stack_pointer_rtx));
2892 set_mem_alias_set (mem, get_frame_alias_set ());
2893 insn = emit_move_insn (frame_pointer_rtx, mem);
2895 /* Whenever we emit insns with post-incremented addresses
2896 ourselves, we must add a post-inc note manually. */
2898 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2900 else if ((size + argspace_offset) != 0)
2902 emit_insn (gen_cris_frame_deallocated_barrier ());
2904 /* If there was no frame-pointer to restore sp from, we must
2905 explicitly deallocate local variables. */
2907 /* Handle space for outgoing parameters that hasn't been handled
2909 size += argspace_offset;
2911 emit_insn (gen_rtx_SET (VOIDmode,
2913 plus_constant (stack_pointer_rtx, size)));
2916 /* If this function has no pushed register parameters
2917 (stdargs/varargs), and if it is not a leaf function, then we have
2918 the return address on the stack. */
2919 if (return_address_on_stack && pretend == 0)
2921 if (current_function_calls_eh_return)
2925 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2926 mem = gen_rtx_MEM (SImode,
2927 gen_rtx_POST_INC (SImode,
2928 stack_pointer_rtx));
2929 set_mem_alias_set (mem, get_frame_alias_set ());
2930 insn = emit_move_insn (srpreg, mem);
2932 /* Whenever we emit insns with post-incremented addresses
2933 ourselves, we must add a post-inc note manually. */
2935 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2937 emit_insn (gen_addsi3 (stack_pointer_rtx,
2939 gen_rtx_raw_REG (SImode,
2940 CRIS_STACKADJ_REG)));
2941 cris_expand_return (false);
2944 cris_expand_return (true);
2949 /* If we pushed some register parameters, then adjust the stack for
2953 /* If SRP is stored on the way, we need to restore it first. */
2954 if (return_address_on_stack)
2957 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2960 mem = gen_rtx_MEM (SImode,
2961 gen_rtx_POST_INC (SImode,
2962 stack_pointer_rtx));
2963 set_mem_alias_set (mem, get_frame_alias_set ());
2964 insn = emit_move_insn (srpreg, mem);
2966 /* Whenever we emit insns with post-incremented addresses
2967 ourselves, we must add a post-inc note manually. */
2969 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2972 emit_insn (gen_rtx_SET (VOIDmode,
2974 plus_constant (stack_pointer_rtx, pretend)));
2977 /* Perform the "physical" unwinding that the EH machinery calculated. */
2978 if (current_function_calls_eh_return)
2979 emit_insn (gen_addsi3 (stack_pointer_rtx,
2981 gen_rtx_raw_REG (SImode,
2982 CRIS_STACKADJ_REG)));
2983 cris_expand_return (false);
2986 /* Worker function for generating movem from mem for load_multiple. */
2989 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
2991 int nregs = INTVAL (nregs_rtx);
2995 rtx srcreg = XEXP (src, 0);
2996 unsigned int regno = nregs - 1;
2999 if (GET_CODE (srcreg) == POST_INC)
3000 srcreg = XEXP (srcreg, 0);
3002 CRIS_ASSERT (REG_P (srcreg));
3004 /* Don't use movem for just one insn. The insns are equivalent except
3005 for the pipeline hazard (on v32); movem does not forward the loaded
3006 registers so there's a three cycles penalty for their use. */
3008 return gen_movsi (gen_rtx_REG (SImode, 0), src);
3010 vec = rtvec_alloc (nprefix + nregs
3011 + (GET_CODE (XEXP (src, 0)) == POST_INC));
3013 if (GET_CODE (XEXP (src, 0)) == POST_INC)
3015 RTVEC_ELT (vec, nprefix + 1)
3016 = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
3020 src = replace_equiv_address (src, srcreg);
3021 RTVEC_ELT (vec, nprefix)
3022 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3025 for (i = 1; i < nregs; i++, eltno++)
3027 RTVEC_ELT (vec, nprefix + eltno)
3028 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3029 adjust_address_nv (src, SImode, i * 4));
3033 return gen_rtx_PARALLEL (VOIDmode, vec);
3036 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3037 are added that the dwarf2 machinery understands. */
3040 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3043 int nregs = INTVAL (nregs_rtx);
3048 rtx destreg = XEXP (dest, 0);
3049 unsigned int regno = nregs - 1;
3052 if (GET_CODE (destreg) == POST_INC)
3053 increment += nregs * 4;
3055 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3056 destreg = XEXP (destreg, 0);
3058 CRIS_ASSERT (REG_P (destreg));
3060 /* Don't use movem for just one insn. The insns are equivalent except
3061 for the pipeline hazard (on v32); movem does not forward the loaded
3062 registers so there's a three cycles penalty for use. */
3065 rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3069 insn = emit_insn (mov);
3071 RTX_FRAME_RELATED_P (insn) = 1;
3075 /* If there was a request for a side-effect, create the ordinary
3077 vec = rtvec_alloc (2);
3079 RTVEC_ELT (vec, 0) = mov;
3080 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3081 plus_constant (destreg, increment));
3084 RTX_FRAME_RELATED_P (mov) = 1;
3085 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3090 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3092 = gen_rtx_SET (VOIDmode,
3093 replace_equiv_address (dest,
3094 plus_constant (destreg,
3096 gen_rtx_REG (SImode, regno));
3099 /* The dwarf2 info wants this mark on each component in a parallel
3100 that's part of the prologue (though it's optional on the first
3103 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3108 = gen_rtx_SET (VOIDmode, destreg,
3109 plus_constant (destreg,
3111 ? increment : nregs * 4));
3115 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3117 /* Don't call adjust_address_nv on a post-incremented address if
3119 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3120 dest = replace_equiv_address (dest, destreg);
3123 for (i = 1; i < nregs; i++, eltno++)
3125 RTVEC_ELT (vec, eltno)
3126 = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3127 gen_rtx_REG (SImode, regno));
3129 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3134 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3136 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3137 we need to keep the stack adjustment separate, after the
3138 MEM-setters. Else the stack-adjustment in the second component of
3139 the parallel would be mishandled; the offsets for the SETs that
3140 follow it would be wrong. We prepare for this by adding a
3141 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3142 followed by the increment. Note that we have FRAME_RELATED_P on
3143 all the SETs, including the original stack adjustment SET in the
3149 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3150 XVECEXP (seq, 0, 0) = XVECEXP (PATTERN (insn), 0, 0);
3151 for (i = 1; i < nregs; i++)
3152 XVECEXP (seq, 0, i) = XVECEXP (PATTERN (insn), 0, i + 1);
3153 XVECEXP (seq, 0, nregs) = XVECEXP (PATTERN (insn), 0, 1);
3155 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq,
3159 RTX_FRAME_RELATED_P (insn) = 1;
3165 /* Worker function for expanding the address for PIC function calls. */
3168 cris_expand_pic_call_address (rtx *opp)
3172 gcc_assert (MEM_P (op));
3175 /* It might be that code can be generated that jumps to 0 (or to a
3176 specific address). Don't die on that. (There is a
3178 if (CONSTANT_ADDRESS_P (op) && CONST_INT_P (op))
3180 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3182 CRIS_ASSERT (can_create_pseudo_p ());
3184 /* For local symbols (non-PLT), just get the plain symbol
3185 reference into a register. For symbols that can be PLT, make
3187 if (t == cris_gotrel_symbol)
3188 op = force_reg (Pmode, op);
3189 else if (t == cris_got_symbol)
3191 if (TARGET_AVOID_GOTPLT)
3193 /* Change a "jsr sym" into (allocate register rM, rO)
3194 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT)),rM"
3195 "add.d rPIC,rM,rO", "jsr rO". */
3197 gcc_assert (can_create_pseudo_p ());
3198 current_function_uses_pic_offset_table = 1;
3199 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), CRIS_UNSPEC_PLT);
3200 rm = gen_reg_rtx (Pmode);
3201 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3202 ro = gen_reg_rtx (Pmode);
3203 if (expand_binop (Pmode, add_optab, rm,
3204 pic_offset_table_rtx,
3205 ro, 0, OPTAB_LIB_WIDEN) != ro)
3206 internal_error ("expand_binop failed in movsi got");
3211 /* Change a "jsr sym" into (allocate register rM, rO)
3212 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOT)),rM"
3213 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3214 marked as not trapping and not aliasing. No "move.d
3215 [rO],rP" as that would invite to re-use of a value
3216 that should not be reused. FIXME: Need a peephole2
3217 for cases when this is cse:d from the call, to change
3218 back to just get the PLT entry address, so we don't
3219 resolve the same symbol over and over (the memory
3220 access of the PLTGOT isn't constant). */
3221 rtx tem, mem, rm, ro;
3223 gcc_assert (can_create_pseudo_p ());
3224 current_function_uses_pic_offset_table = 1;
3225 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3226 CRIS_UNSPEC_PLTGOTREAD);
3227 rm = gen_reg_rtx (Pmode);
3228 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3229 ro = gen_reg_rtx (Pmode);
3230 if (expand_binop (Pmode, add_optab, rm,
3231 pic_offset_table_rtx,
3232 ro, 0, OPTAB_LIB_WIDEN) != ro)
3233 internal_error ("expand_binop failed in movsi got");
3234 mem = gen_rtx_MEM (Pmode, ro);
3236 /* This MEM doesn't alias anything. Whether it aliases
3237 other same symbols is unimportant. */
3238 set_mem_alias_set (mem, new_alias_set ());
3239 MEM_NOTRAP_P (mem) = 1;
3244 /* Can't possibly get a GOT-needing-fixup for a function-call,
3246 fatal_insn ("Unidentifiable call op", op);
3248 *opp = replace_equiv_address (*opp, op);
3252 /* Make sure operands are in the right order for an addsi3 insn as
3253 generated by a define_split. A MEM as the first operand isn't
3254 recognized by addsi3 after reload. OPERANDS contains the operands,
3255 with the first at OPERANDS[N] and the second at OPERANDS[N+1]. */
3258 cris_order_for_addsi3 (rtx *operands, int n)
3260 if (MEM_P (operands[n]))
3262 rtx tem = operands[n];
3263 operands[n] = operands[n + 1];
3264 operands[n + 1] = tem;
3268 /* Use from within code, from e.g. PRINT_OPERAND and
3269 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3270 different things depending on whether code operand or constant is
3274 cris_output_addr_const (FILE *file, rtx x)
3277 output_addr_const (file, x);
3281 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3284 cris_asm_output_symbol_ref (FILE *file, rtx x)
3286 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3288 if (flag_pic && in_code > 0)
3290 const char *origstr = XSTR (x, 0);
3292 str = (* targetm.strip_name_encoding) (origstr);
3293 assemble_name (file, str);
3296 if (! current_function_uses_pic_offset_table)
3297 output_operand_lossage ("PIC register isn't set up");
3300 assemble_name (file, XSTR (x, 0));
3303 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3306 cris_asm_output_label_ref (FILE *file, char *buf)
3308 if (flag_pic && in_code > 0)
3310 assemble_name (file, buf);
3313 if (! current_function_uses_pic_offset_table)
3314 internal_error ("emitting PIC operand, but PIC register isn't set up");
3317 assemble_name (file, buf);
3320 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3323 cris_output_addr_const_extra (FILE *file, rtx xconst)
3325 switch (GET_CODE (xconst))
3330 x = XVECEXP (xconst, 0, 0);
3331 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3332 || GET_CODE (x) == LABEL_REF
3333 || GET_CODE (x) == CONST);
3334 output_addr_const (file, x);
3335 switch (XINT (xconst, 1))
3337 case CRIS_UNSPEC_PLT:
3338 fprintf (file, ":PLTG");
3341 case CRIS_UNSPEC_GOTREL:
3342 fprintf (file, ":GOTOFF");
3345 case CRIS_UNSPEC_GOTREAD:
3347 fprintf (file, ":GOT16");
3349 fprintf (file, ":GOT");
3352 case CRIS_UNSPEC_PLTGOTREAD:
3354 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3356 fprintf (file, CRIS_GOTPLT_SUFFIX);
3369 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3372 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3373 int incoming ATTRIBUTE_UNUSED)
3375 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3378 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3381 cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3382 enum machine_mode mode ATTRIBUTE_UNUSED,
3383 tree type ATTRIBUTE_UNUSED,
3384 int *pretend_arg_size,
3387 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3389 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3390 cfun->machine->stdarg_regs = stdarg_regs;
3391 *pretend_arg_size = stdarg_regs * 4;
3395 fprintf (asm_out_file,
3396 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3397 ca->regs, *pretend_arg_size, second_time);
3400 /* Return true if TYPE must be passed by invisible reference.
3401 For cris, we pass <= 8 bytes by value, others by reference. */
3404 cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3405 enum machine_mode mode, tree type,
3406 bool named ATTRIBUTE_UNUSED)
3408 return (targetm.calls.must_pass_in_stack (mode, type)
3409 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3414 cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3415 tree type, bool named ATTRIBUTE_UNUSED)
3417 if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3418 && !targetm.calls.must_pass_in_stack (mode, type)
3419 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3420 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3421 return UNITS_PER_WORD;
3426 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3429 cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3431 HARD_REG_SET mof_set;
3435 CLEAR_HARD_REG_SET (mof_set);
3436 SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3438 /* For the time being, all asms clobber condition codes. Revisit when
3439 there's a reasonable use for inputs/outputs that mention condition
3442 = tree_cons (NULL_TREE,
3443 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3444 reg_names[CRIS_CC0_REGNUM]),
3447 for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3449 tree val = TREE_VALUE (t);
3451 /* The constraint letter for the singleton register class of MOF
3452 is 'h'. If it's mentioned in the constraints, the asm is
3453 MOF-aware and adding it to the clobbers would cause it to have
3454 impossible constraints. */
3455 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3457 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3461 for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3463 tree val = TREE_VALUE (t);
3465 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3467 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3471 return tree_cons (NULL_TREE,
3472 build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3473 reg_names[CRIS_MOF_REGNUM]),
3478 /* Various small functions to replace macros. Only called from a
3479 debugger. They might collide with gcc functions or system functions,
3480 so only emit them when '#if 1' above. */
3482 enum rtx_code Get_code (rtx);
3487 return GET_CODE (x);
3490 const char *Get_mode (rtx);
3495 return GET_MODE_NAME (GET_MODE (x));
3498 rtx Xexp (rtx, int);
3506 rtx Xvecexp (rtx, int, int);
3509 Xvecexp (rtx x, int n, int m)
3511 return XVECEXP (x, n, m);
3514 int Get_rtx_len (rtx);
3519 return GET_RTX_LENGTH (GET_CODE (x));
3522 /* Use upper-case to distinguish from local variables that are sometimes
3523 called next_insn and prev_insn. */
3525 rtx Next_insn (rtx);
3528 Next_insn (rtx insn)
3530 return NEXT_INSN (insn);
3533 rtx Prev_insn (rtx);
3536 Prev_insn (rtx insn)
3538 return PREV_INSN (insn);
3542 #include "gt-cris.h"
3546 * eval: (c-set-style "gnu")
3547 * indent-tabs-mode: t