1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
45 #include "target-def.h"
49 /* Usable when we have an amount to add or subtract, and want the
50 optimal size of the insn. */
51 #define ADDITIVE_SIZE_MODIFIER(size) \
52 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54 #define ASSERT_PLT_UNSPEC(x) \
55 CRIS_ASSERT (XINT (x, 1) == CRIS_UNSPEC_PLT \
56 && ((GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF) \
57 || GET_CODE (XVECEXP (x, 0, 0)) == LABEL_REF))
59 #define LOSE_AND_RETURN(msgid, x) \
62 cris_operand_lossage (msgid, x); \
66 enum cris_retinsn_type
67 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
69 /* Per-function machine data. */
70 struct machine_function GTY(())
72 int needs_return_address_on_stack;
74 /* This is the number of registers we save in the prologue due to
78 enum cris_retinsn_type return_type;
81 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
83 static char cris_output_insn_is_bound = 0;
85 /* In code for output macros, this is how we know whether e.g. constant
86 goes in code or in a static initializer. */
87 static int in_code = 0;
89 /* Fix for reg_overlap_mentioned_p. */
90 static int cris_reg_overlap_mentioned_p (rtx, rtx);
92 static void cris_print_base (rtx, FILE *);
94 static void cris_print_index (rtx, FILE *);
96 static void cris_output_addr_const (FILE *, rtx);
98 static struct machine_function * cris_init_machine_status (void);
100 static rtx cris_struct_value_rtx (tree, int);
102 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
103 tree type, int *, int);
105 static int cris_initial_frame_pointer_offset (void);
107 static int saved_regs_mentioned (rtx);
109 static void cris_operand_lossage (const char *, rtx);
111 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
113 static void cris_asm_output_mi_thunk
114 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
116 static void cris_file_start (void);
117 static void cris_init_libfuncs (void);
119 static bool cris_rtx_costs (rtx, int, int, int *);
120 static int cris_address_cost (rtx);
121 static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
123 static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
125 static tree cris_md_asm_clobbers (tree, tree, tree);
127 static bool cris_handle_option (size_t, const char *, int);
129 /* This is the parsed result of the "-max-stack-stackframe=" option. If
130 it (still) is zero, then there was no such option given. */
131 int cris_max_stackframe = 0;
133 /* This is the parsed result of the "-march=" option, if given. */
134 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
136 #undef TARGET_ASM_ALIGNED_HI_OP
137 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
138 #undef TARGET_ASM_ALIGNED_SI_OP
139 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
140 #undef TARGET_ASM_ALIGNED_DI_OP
141 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
143 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
144 available in ELF. These "normal" pseudos do not have any alignment
145 constraints or side-effects. */
146 #undef TARGET_ASM_UNALIGNED_HI_OP
147 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
149 #undef TARGET_ASM_UNALIGNED_SI_OP
150 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
152 #undef TARGET_ASM_UNALIGNED_DI_OP
153 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
155 #undef TARGET_ASM_OUTPUT_MI_THUNK
156 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
157 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
158 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
160 #undef TARGET_ASM_FILE_START
161 #define TARGET_ASM_FILE_START cris_file_start
163 #undef TARGET_INIT_LIBFUNCS
164 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
166 #undef TARGET_RTX_COSTS
167 #define TARGET_RTX_COSTS cris_rtx_costs
168 #undef TARGET_ADDRESS_COST
169 #define TARGET_ADDRESS_COST cris_address_cost
171 #undef TARGET_PROMOTE_FUNCTION_ARGS
172 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
173 #undef TARGET_STRUCT_VALUE_RTX
174 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
175 #undef TARGET_SETUP_INCOMING_VARARGS
176 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
177 #undef TARGET_PASS_BY_REFERENCE
178 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
179 #undef TARGET_ARG_PARTIAL_BYTES
180 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
181 #undef TARGET_MD_ASM_CLOBBERS
182 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
183 #undef TARGET_DEFAULT_TARGET_FLAGS
184 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
185 #undef TARGET_HANDLE_OPTION
186 #define TARGET_HANDLE_OPTION cris_handle_option
188 struct gcc_target targetm = TARGET_INITIALIZER;
190 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
193 cris_movem_load_rest_p (rtx op, int offs)
195 unsigned int reg_count = XVECLEN (op, 0) - offs;
201 unsigned int regno = 0;
203 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
204 other than (MEM reg). */
206 || GET_CODE (XVECEXP (op, 0, offs)) != SET
207 || GET_CODE (SET_DEST (XVECEXP (op, 0, offs))) != REG
208 || GET_CODE (SET_SRC (XVECEXP (op, 0, offs))) != MEM)
211 /* Check a possible post-inc indicator. */
212 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
214 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
215 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
221 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
222 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
223 || GET_CODE (inc) != CONST_INT
224 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
231 /* FIXME: These two only for pre-v32. */
233 regno = reg_count - 1;
235 elt = XVECEXP (op, 0, offs);
236 src_addr = XEXP (SET_SRC (elt), 0);
238 if (GET_CODE (elt) != SET
239 || GET_CODE (SET_DEST (elt)) != REG
240 || GET_MODE (SET_DEST (elt)) != SImode
241 || REGNO (SET_DEST (elt)) != regno
242 || GET_CODE (SET_SRC (elt)) != MEM
243 || GET_MODE (SET_SRC (elt)) != SImode
244 || !memory_address_p (SImode, src_addr))
247 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
249 rtx elt = XVECEXP (op, 0, i);
252 if (GET_CODE (elt) != SET
253 || GET_CODE (SET_DEST (elt)) != REG
254 || GET_MODE (SET_DEST (elt)) != SImode
255 || REGNO (SET_DEST (elt)) != regno
256 || GET_CODE (SET_SRC (elt)) != MEM
257 || GET_MODE (SET_SRC (elt)) != SImode
258 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
259 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
260 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
261 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
268 /* Worker function for predicate for the parallel contents in a movem
272 cris_store_multiple_op_p (rtx op)
274 int reg_count = XVECLEN (op, 0);
285 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
286 other than (MEM reg) and (MEM (PLUS reg const)). */
290 elt = XVECEXP (op, 0, 0);
292 if (GET_CODE (elt) != SET)
295 dest = SET_DEST (elt);
297 if (GET_CODE (SET_SRC (elt)) != REG
298 || GET_CODE (dest) != MEM)
301 dest_addr = XEXP (dest, 0);
303 /* Check a possible post-inc indicator. */
304 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
306 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
307 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
313 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
314 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
315 || GET_CODE (inc) != CONST_INT
316 /* Support increment by number of registers, and by the offset
317 of the destination, if it has the form (MEM (PLUS reg
319 || !((REG_P (dest_addr)
320 && REGNO (dest_addr) == REGNO (reg)
321 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
322 || (GET_CODE (dest_addr) == PLUS
323 && REG_P (XEXP (dest_addr, 0))
324 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
325 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT
326 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
334 /* FIXME: These two only for pre-v32. */
336 regno = reg_count - 1;
338 if (GET_CODE (elt) != SET
339 || GET_CODE (SET_SRC (elt)) != REG
340 || GET_MODE (SET_SRC (elt)) != SImode
341 || REGNO (SET_SRC (elt)) != (unsigned int) regno
342 || GET_CODE (SET_DEST (elt)) != MEM
343 || GET_MODE (SET_DEST (elt)) != SImode)
346 if (REG_P (dest_addr))
348 dest_base = dest_addr;
351 else if (GET_CODE (dest_addr) == PLUS
352 && REG_P (XEXP (dest_addr, 0))
353 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
355 dest_base = XEXP (dest_addr, 0);
356 offset = INTVAL (XEXP (dest_addr, 1));
361 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
363 rtx elt = XVECEXP (op, 0, i);
366 if (GET_CODE (elt) != SET
367 || GET_CODE (SET_SRC (elt)) != REG
368 || GET_MODE (SET_SRC (elt)) != SImode
369 || REGNO (SET_SRC (elt)) != (unsigned int) regno
370 || GET_CODE (SET_DEST (elt)) != MEM
371 || GET_MODE (SET_DEST (elt)) != SImode
372 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
373 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
374 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
375 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
382 /* The CONDITIONAL_REGISTER_USAGE worker. */
385 cris_conditional_register_usage (void)
387 /* FIXME: This isn't nice. We should be able to use that register for
388 something else if the PIC table isn't needed. */
390 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
391 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
393 if (TARGET_HAS_MUL_INSNS)
394 fixed_regs[CRIS_MOF_REGNUM] = 0;
396 /* On early versions, we must use the 16-bit condition-code register,
397 which has another name. */
398 if (cris_cpu_version < 8)
399 reg_names[CRIS_CC0_REGNUM] = "ccr";
402 /* Return current_function_uses_pic_offset_table. For use in cris.md,
403 since some generated files do not include function.h. */
406 cris_cfun_uses_pic_table (void)
408 return current_function_uses_pic_offset_table;
411 /* Given an rtx, return the text string corresponding to the CODE of X.
412 Intended for use in the assembly language output section of a
418 cris_output_insn_is_bound = 0;
419 switch (GET_CODE (x))
430 /* This function is for retrieving a part of an instruction name for
431 an operator, for immediate output. If that ever happens for
432 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
434 internal_error ("MULT case in cris_op_str");
470 /* Used to control the sign/zero-extend character for the 'e' modifier.
472 cris_output_insn_is_bound = 1;
477 return "Unknown operator";
482 /* Emit an error message when we're in an asm, and a fatal error for
483 "normal" insns. Formatted output isn't easily implemented, since we
484 use output_operand_lossage to output the actual message and handle the
485 categorization of the error. */
488 cris_operand_lossage (const char *msgid, rtx op)
491 output_operand_lossage ("%s", msgid);
494 /* Print an index part of an address to file. */
497 cris_print_index (rtx index, FILE *file)
499 rtx inner = XEXP (index, 0);
501 /* Make the index "additive" unless we'll output a negative number, in
502 which case the sign character is free (as in free beer). */
503 if (GET_CODE (index) != CONST_INT || INTVAL (index) >= 0)
507 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
508 else if (CONSTANT_P (index))
509 cris_output_addr_const (file, index);
510 else if (GET_CODE (index) == MULT)
512 fprintf (file, "$%s.",
513 reg_names[REGNO (XEXP (index, 0))]);
515 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
517 else if (GET_CODE (index) == SIGN_EXTEND &&
518 GET_CODE (inner) == MEM)
520 rtx inner_inner = XEXP (inner, 0);
522 if (GET_CODE (inner_inner) == POST_INC)
524 fprintf (file, "[$%s+].",
525 reg_names[REGNO (XEXP (inner_inner, 0))]);
526 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
530 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
532 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
535 else if (GET_CODE (index) == MEM)
537 if (GET_CODE (inner) == POST_INC)
538 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
540 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
543 cris_operand_lossage ("unexpected index-type in cris_print_index",
547 /* Print a base rtx of an address to file. */
550 cris_print_base (rtx base, FILE *file)
553 fprintf (file, "$%s", reg_names[REGNO (base)]);
554 else if (GET_CODE (base) == POST_INC)
555 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
557 cris_operand_lossage ("unexpected base-type in cris_print_base",
561 /* Usable as a guard in expressions. */
564 cris_fatal (char *arg)
566 internal_error (arg);
568 /* We'll never get here; this is just to appease compilers. */
572 /* Return nonzero if REGNO is an ordinary register that *needs* to be
573 saved together with other registers, possibly by a MOVEM instruction,
574 or is saved for target-independent reasons. There may be
575 target-dependent reasons to save the register anyway; this is just a
576 wrapper for a complicated conditional. */
579 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
582 (((regs_ever_live[regno]
583 && !call_used_regs[regno])
584 || (regno == PIC_OFFSET_TABLE_REGNUM
586 /* It is saved anyway, if there would be a gap. */
588 && regs_ever_live[regno + 1]
589 && !call_used_regs[regno + 1]))))
590 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
591 && regno != CRIS_SRP_REGNUM)
592 || (current_function_calls_eh_return
593 && (regno == EH_RETURN_DATA_REGNO (0)
594 || regno == EH_RETURN_DATA_REGNO (1)
595 || regno == EH_RETURN_DATA_REGNO (2)
596 || regno == EH_RETURN_DATA_REGNO (3)));
599 /* Return nonzero if there are regs mentioned in the insn that are not all
600 in the call_used regs. This is part of the decision whether an insn
601 can be put in the epilogue. */
604 saved_regs_mentioned (rtx x)
610 /* Mainly stolen from refers_to_regno_p in rtlanal.c. */
618 return !call_used_regs[i];
621 /* If this is a SUBREG of a hard reg, we can see exactly which
622 registers are being modified. Otherwise, handle normally. */
623 i = REGNO (SUBREG_REG (x));
624 return !call_used_regs[i];
630 fmt = GET_RTX_FORMAT (code);
631 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
635 if (saved_regs_mentioned (XEXP (x, i)))
638 else if (fmt[i] == 'E')
641 for (j = XVECLEN (x, i) - 1; j >=0; j--)
642 if (saved_regs_mentioned (XEXP (x, i)))
650 /* The PRINT_OPERAND worker. */
653 cris_print_operand (FILE *file, rtx x, int code)
657 /* Size-strings corresponding to MULT expressions. */
658 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
660 /* New code entries should just be added to the switch below. If
661 handling is finished, just return. If handling was just a
662 modification of the operand, the modified operand should be put in
663 "operand", and then do a break to let default handling
664 (zero-modifier) output the operand. */
669 /* Print the unsigned supplied integer as if it were signed
670 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
671 if (GET_CODE (x) != CONST_INT
672 || ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
673 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
674 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
675 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
679 /* Print assembler code for operator. */
680 fprintf (file, "%s", cris_op_str (operand));
685 /* A movem modifier working on a parallel; output the register
689 if (GET_CODE (x) != PARALLEL)
690 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
692 /* The second item can be (set reg (plus reg const)) to denote a
695 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
697 : XVECLEN (x, 0) - 1);
699 fprintf (file, "$%s", reg_names [regno]);
705 /* A similar movem modifier; output the memory operand. */
708 if (GET_CODE (x) != PARALLEL)
709 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
711 /* The lowest mem operand is in the first item, but perhaps it
712 needs to be output as postincremented. */
713 addr = GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == MEM
714 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
715 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
717 /* The second item can be a (set reg (plus reg const)) to denote
719 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
721 /* It's a post-increment, if the address is a naked (reg). */
723 addr = gen_rtx_POST_INC (SImode, addr);
726 /* Otherwise, it's a side-effect; RN=RN+M. */
727 fprintf (file, "[$%s=$%s%s%d]",
728 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
729 reg_names [REGNO (XEXP (addr, 0))],
730 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
731 (int) INTVAL (XEXP (addr, 1)));
735 output_address (addr);
740 /* Adjust a power of two to its log2. */
741 if (GET_CODE (x) != CONST_INT || exact_log2 (INTVAL (x)) < 0 )
742 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
743 fprintf (file, "%d", exact_log2 (INTVAL (x)));
747 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
748 respectively. This modifier also terminates the inhibiting
749 effects of the 'x' modifier. */
750 cris_output_insn_is_bound = 0;
751 if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
755 if (INTVAL (x) <= 255)
757 else if (INTVAL (x) <= 65535)
767 /* For a non-integer, print the size of the operand. */
768 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
769 ? 'd' : GET_MODE (x) == HImode ? 'w'
770 : GET_MODE (x) == QImode ? 'b'
771 /* If none of the above, emit an erroneous size letter. */
777 /* Const_int: print b for -127 <= x <= 255,
778 w for -32768 <= x <= 65535, else die. */
779 if (GET_CODE (x) != CONST_INT
780 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
781 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
782 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
786 /* Output a 'nop' if there's nothing for the delay slot.
787 This method stolen from the sparc files. */
788 if (dbr_sequence_length () == 0)
789 fputs ("\n\tnop", file);
793 /* Output directive for alignment padded with "nop" insns.
794 Optimizing for size, it's plain 4-byte alignment, otherwise we
795 align the section to a cache-line (32 bytes) and skip at max 2
796 bytes, i.e. we skip if it's the last insn on a cache-line. The
797 latter is faster by a small amount (for two test-programs 99.6%
798 and 99.9%) and larger by a small amount (ditto 100.1% and
799 100.2%). This is supposed to be the simplest yet performance-
800 wise least intrusive way to make sure the immediately following
801 (supposed) muls/mulu insn isn't located at the end of a
805 ? ".p2alignw 2,0x050f\n\t"
806 : ".p2alignw 5,0x050f,2\n\t", file);
810 /* The PIC register. */
812 internal_error ("invalid use of ':' modifier");
813 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
817 /* Print high (most significant) part of something. */
818 switch (GET_CODE (operand))
821 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
822 value is kept here, and so may be other than 0 or -1. */
823 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
824 INTVAL (operand_subword (operand, 1, 0, DImode)));
828 /* High part of a long long constant. */
829 if (GET_MODE (operand) == VOIDmode)
831 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
835 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
838 /* Print reg + 1. Check that there's not an attempt to print
839 high-parts of registers like stack-pointer or higher. */
840 if (REGNO (operand) > STACK_POINTER_REGNUM - 2)
841 LOSE_AND_RETURN ("bad register", operand);
842 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
846 /* Adjust memory address to high part. */
848 rtx adj_mem = operand;
850 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
852 /* Adjust so we can use two SImode in DImode.
853 Calling adj_offsettable_operand will make sure it is an
854 offsettable address. Don't do this for a postincrement
855 though; it should remain as it was. */
856 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
858 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
860 output_address (XEXP (adj_mem, 0));
865 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
869 /* Strip the MEM expression. */
870 operand = XEXP (operand, 0);
874 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
875 cris_output_insn_is_bound is nonzero. */
876 if (GET_CODE (operand) != SIGN_EXTEND
877 && GET_CODE (operand) != ZERO_EXTEND
878 && GET_CODE (operand) != CONST_INT)
879 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
881 if (cris_output_insn_is_bound)
883 cris_output_insn_is_bound = 0;
887 putc (GET_CODE (operand) == SIGN_EXTEND
888 || (GET_CODE (operand) == CONST_INT && INTVAL (operand) < 0)
893 /* Print the size letter of the inner element. We can do it by
894 calling ourselves with the 's' modifier. */
895 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
896 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
897 cris_print_operand (file, XEXP (operand, 0), 's');
901 /* Print the least significant part of operand. */
902 if (GET_CODE (operand) == CONST_DOUBLE)
904 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
907 else if (HOST_BITS_PER_WIDE_INT > 32 && GET_CODE (operand) == CONST_INT)
909 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
910 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
913 /* Otherwise the least significant part equals the normal part,
914 so handle it normally. */
918 /* When emitting an add for the high part of a DImode constant, we
919 want to use addq for 0 and adds.w for -1. */
920 if (GET_CODE (operand) != CONST_INT)
921 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
922 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
926 /* If this is a GOT symbol, force it to be emitted as :GOT and
927 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
928 Avoid making this too much of a special case. */
929 if (flag_pic == 1 && CONSTANT_P (operand))
931 int flag_pic_save = flag_pic;
934 cris_output_addr_const (file, operand);
935 flag_pic = flag_pic_save;
941 /* When emitting an sub for the high part of a DImode constant, we
942 want to use subq for 0 and subs.w for -1. */
943 if (GET_CODE (operand) != CONST_INT)
944 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
945 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
949 /* Print the operand as the index-part of an address.
950 Easiest way out is to use cris_print_index. */
951 cris_print_index (operand, file);
955 /* Print the size letter for an operand to a MULT, which must be a
956 const_int with a suitable value. */
957 if (GET_CODE (operand) != CONST_INT || INTVAL (operand) > 4)
958 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
959 fprintf (file, "%s", mults[INTVAL (operand)]);
963 /* No code, print as usual. */
967 LOSE_AND_RETURN ("invalid operand modifier letter", x);
970 /* Print an operand as without a modifier letter. */
971 switch (GET_CODE (operand))
974 if (REGNO (operand) > 15
975 && REGNO (operand) != CRIS_MOF_REGNUM
976 && REGNO (operand) != CRIS_SRP_REGNUM
977 && REGNO (operand) != CRIS_CC0_REGNUM)
978 internal_error ("internal error: bad register: %d", REGNO (operand));
979 fprintf (file, "$%s", reg_names[REGNO (operand)]);
983 output_address (XEXP (operand, 0));
987 if (GET_MODE (operand) == VOIDmode)
988 /* A long long constant. */
989 output_addr_const (file, operand);
992 /* Only single precision is allowed as plain operands the
993 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
998 /* FIXME: Perhaps check overflow of the "single". */
999 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1000 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1002 fprintf (file, "0x%lx", l);
1009 cris_output_addr_const (file, operand);
1015 /* For a (MULT (reg X) const_int) we output "rX.S". */
1016 int i = GET_CODE (XEXP (operand, 1)) == CONST_INT
1017 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1018 rtx reg = GET_CODE (XEXP (operand, 1)) == CONST_INT
1019 ? XEXP (operand, 0) : XEXP (operand, 1);
1021 if (GET_CODE (reg) != REG
1022 || (GET_CODE (XEXP (operand, 0)) != CONST_INT
1023 && GET_CODE (XEXP (operand, 1)) != CONST_INT))
1024 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1026 cris_print_base (reg, file);
1027 fprintf (file, ".%c",
1028 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1030 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1036 /* No need to handle all strange variants, let output_addr_const
1038 if (CONSTANT_P (operand))
1040 cris_output_addr_const (file, operand);
1044 LOSE_AND_RETURN ("unexpected operand", x);
1048 /* The PRINT_OPERAND_ADDRESS worker. */
1051 cris_print_operand_address (FILE *file, rtx x)
1053 /* All these were inside MEM:s so output indirection characters. */
1056 if (CONSTANT_ADDRESS_P (x))
1057 cris_output_addr_const (file, x);
1058 else if (BASE_OR_AUTOINCR_P (x))
1059 cris_print_base (x, file);
1060 else if (GET_CODE (x) == PLUS)
1068 cris_print_base (x1, file);
1069 cris_print_index (x2, file);
1071 else if (BASE_P (x2))
1073 cris_print_base (x2, file);
1074 cris_print_index (x1, file);
1077 LOSE_AND_RETURN ("unrecognized address", x);
1079 else if (GET_CODE (x) == MEM)
1081 /* A DIP. Output more indirection characters. */
1083 cris_print_base (XEXP (x, 0), file);
1087 LOSE_AND_RETURN ("unrecognized address", x);
1092 /* The RETURN_ADDR_RTX worker.
1093 We mark that the return address is used, either by EH or
1094 __builtin_return_address, for use by the function prologue and
1095 epilogue. FIXME: This isn't optimal; we just use the mark in the
1096 prologue and epilogue to say that the return address is to be stored
1097 in the stack frame. We could return SRP for leaf-functions and use the
1098 initial-value machinery. */
1101 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1103 cfun->machine->needs_return_address_on_stack = 1;
1105 /* The return-address is stored just above the saved frame-pointer (if
1106 present). Apparently we can't eliminate from the frame-pointer in
1107 that direction, so use the incoming args (maybe pretended) pointer. */
1109 ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1113 /* Accessor used in cris.md:return because cfun->machine isn't available
1117 cris_return_address_on_stack (void)
1119 return regs_ever_live[CRIS_SRP_REGNUM]
1120 || cfun->machine->needs_return_address_on_stack;
1123 /* Accessor used in cris.md:return because cfun->machine isn't available
1127 cris_return_address_on_stack_for_return (void)
1129 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1130 : cris_return_address_on_stack ();
1133 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1134 handles FP -> SP elimination offset. */
1137 cris_initial_frame_pointer_offset (void)
1141 /* Initial offset is 0 if we don't have a frame pointer. */
1143 bool got_really_used = false;
1145 if (current_function_uses_pic_offset_table)
1147 push_topmost_sequence ();
1149 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1151 pop_topmost_sequence ();
1154 /* And 4 for each register pushed. */
1155 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1156 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1159 /* And then, last, we add the locals allocated. */
1160 offs += get_frame_size ();
1162 /* And more; the accumulated args size. */
1163 offs += current_function_outgoing_args_size;
1165 /* Then round it off, in case we use aligned stack. */
1166 if (TARGET_STACK_ALIGN)
1167 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1172 /* The INITIAL_ELIMINATION_OFFSET worker.
1173 Calculate the difference between imaginary registers such as frame
1174 pointer and the stack pointer. Used to eliminate the frame pointer
1175 and imaginary arg pointer. */
1178 cris_initial_elimination_offset (int fromreg, int toreg)
1181 = cris_initial_frame_pointer_offset ();
1183 /* We should be able to use regs_ever_live and related prologue
1184 information here, or alpha should not as well. */
1185 bool return_address_on_stack = cris_return_address_on_stack ();
1187 /* Here we act as if the frame-pointer were needed. */
1188 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1190 if (fromreg == ARG_POINTER_REGNUM
1191 && toreg == FRAME_POINTER_REGNUM)
1192 return ap_fp_offset;
1194 /* Between the frame pointer and the stack are only "normal" stack
1195 variables and saved registers. */
1196 if (fromreg == FRAME_POINTER_REGNUM
1197 && toreg == STACK_POINTER_REGNUM)
1198 return fp_sp_offset;
1200 /* We need to balance out the frame pointer here. */
1201 if (fromreg == ARG_POINTER_REGNUM
1202 && toreg == STACK_POINTER_REGNUM)
1203 return ap_fp_offset + fp_sp_offset - 4;
1208 /* This function looks into the pattern to see how this insn affects
1211 Used when to eliminate test insns before a condition-code user,
1212 such as a "scc" insn or a conditional branch. This includes
1213 checking if the entities that cc was updated by, are changed by the
1216 Currently a jumble of the old peek-inside-the-insn and the newer
1217 check-cc-attribute methods. */
1220 cris_notice_update_cc (rtx exp, rtx insn)
1222 /* Check if user specified "-mcc-init" as a bug-workaround. FIXME:
1223 TARGET_CCINIT does not work; we must set CC_REVERSED as below.
1224 Several testcases will otherwise fail, for example
1225 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1232 /* Slowly, we're converting to using attributes to control the setting
1233 of condition-code status. */
1234 switch (get_attr_cc (insn))
1237 /* Even if it is "none", a setting may clobber a previous
1238 cc-value, so check. */
1239 if (GET_CODE (exp) == SET)
1241 if (cc_status.value1
1242 && modified_in_p (cc_status.value1, insn))
1243 cc_status.value1 = 0;
1245 if (cc_status.value2
1246 && modified_in_p (cc_status.value2, insn))
1247 cc_status.value2 = 0;
1256 /* Which means, for:
1261 CC is (reg) and (...) - unless (...) is 0, then CC does not change.
1262 CC_NO_OVERFLOW unless (...) is reg or mem.
1271 (set (reg1) (mem (bdap/biap)))
1272 (set (reg2) (bdap/biap))):
1273 CC is (reg1) and (mem (reg2))
1276 (set (mem (bdap/biap)) (reg1)) [or 0]
1277 (set (reg2) (bdap/biap))):
1280 (where reg and mem includes strict_low_parts variants thereof)
1282 For all others, assume CC is clobbered.
1283 Note that we do not have to care about setting CC_NO_OVERFLOW,
1284 since the overflow flag is set to 0 (i.e. right) for
1285 instructions where it does not have any sane sense, but where
1286 other flags have meanings. (This includes shifts; the carry is
1289 Note that there are other parallel constructs we could match,
1290 but we don't do that yet. */
1292 if (GET_CODE (exp) == SET)
1294 /* FIXME: Check when this happens. It looks like we should
1295 actually do a CC_STATUS_INIT here to be safe. */
1296 if (SET_DEST (exp) == pc_rtx)
1299 /* Record CC0 changes, so we do not have to output multiple
1301 if (SET_DEST (exp) == cc0_rtx)
1303 cc_status.value1 = SET_SRC (exp);
1304 cc_status.value2 = 0;
1306 /* Handle flags for the special btstq on one bit. */
1307 if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
1308 && XEXP (SET_SRC (exp), 1) == const1_rtx)
1310 if (GET_CODE (XEXP (SET_SRC (exp), 0)) == CONST_INT)
1312 cc_status.flags = CC_INVERTED;
1314 /* A one-bit btstq. */
1315 cc_status.flags = CC_Z_IN_NOT_N;
1318 cc_status.flags = 0;
1320 if (GET_CODE (SET_SRC (exp)) == COMPARE)
1322 if (!REG_P (XEXP (SET_SRC (exp), 0))
1323 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1324 /* For some reason gcc will not canonicalize compare
1325 operations, reversing the sign by itself if
1326 operands are in wrong order. */
1327 /* (But NOT inverted; eq is still eq.) */
1328 cc_status.flags = CC_REVERSED;
1330 /* This seems to be overlooked by gcc. FIXME: Check again.
1331 FIXME: Is it really safe? */
1333 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1334 XEXP (SET_SRC (exp), 0),
1335 XEXP (SET_SRC (exp), 1));
1339 else if (REG_P (SET_DEST (exp))
1340 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1341 && REG_P (XEXP (SET_DEST (exp), 0))))
1343 /* A register is set; normally CC is set to show that no
1344 test insn is needed. Catch the exceptions. */
1346 /* If not to cc0, then no "set"s in non-natural mode give
1348 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1349 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1351 /* ... except add:s and sub:s in DImode. */
1352 if (GET_MODE (SET_DEST (exp)) == DImode
1353 && (GET_CODE (SET_SRC (exp)) == PLUS
1354 || GET_CODE (SET_SRC (exp)) == MINUS))
1356 cc_status.flags = 0;
1357 cc_status.value1 = SET_DEST (exp);
1358 cc_status.value2 = SET_SRC (exp);
1360 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1362 cc_status.value2 = 0;
1364 /* Add and sub may set V, which gets us
1365 unoptimizable results in "gt" and "le" condition
1367 cc_status.flags |= CC_NO_OVERFLOW;
1372 else if (SET_SRC (exp) == const0_rtx)
1374 /* There's no CC0 change when clearing a register or
1375 memory. Just check for overlap. */
1376 if (cc_status.value1
1377 && modified_in_p (cc_status.value1, insn))
1378 cc_status.value1 = 0;
1380 if (cc_status.value2
1381 && modified_in_p (cc_status.value2, insn))
1382 cc_status.value2 = 0;
1388 cc_status.flags = 0;
1389 cc_status.value1 = SET_DEST (exp);
1390 cc_status.value2 = SET_SRC (exp);
1392 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1394 cc_status.value2 = 0;
1396 /* Some operations may set V, which gets us
1397 unoptimizable results in "gt" and "le" condition
1399 if (GET_CODE (SET_SRC (exp)) == PLUS
1400 || GET_CODE (SET_SRC (exp)) == MINUS
1401 || GET_CODE (SET_SRC (exp)) == NEG)
1402 cc_status.flags |= CC_NO_OVERFLOW;
1407 else if (GET_CODE (SET_DEST (exp)) == MEM
1408 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1409 && GET_CODE (XEXP (SET_DEST (exp), 0)) == MEM))
1411 /* When SET to MEM, then CC is not changed (except for
1413 if (cc_status.value1
1414 && modified_in_p (cc_status.value1, insn))
1415 cc_status.value1 = 0;
1417 if (cc_status.value2
1418 && modified_in_p (cc_status.value2, insn))
1419 cc_status.value2 = 0;
1424 else if (GET_CODE (exp) == PARALLEL)
1426 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1427 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1428 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1430 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1431 && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 1)) == MEM)
1433 /* For "move.S [rx=ry+o],rz", say CC reflects
1434 value1=rz and value2=[rx] */
1435 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1437 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1438 XEXP (XVECEXP (exp, 0, 1), 0));
1439 cc_status.flags = 0;
1441 /* Huh? A side-effect cannot change the destination
1443 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1445 internal_error ("internal error: sideeffect-insn affecting main effect");
1448 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1449 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1450 && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 0)) == MEM)
1452 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1453 say flags are not changed, except for overlap. */
1454 if (cc_status.value1
1455 && modified_in_p (cc_status.value1, insn))
1456 cc_status.value1 = 0;
1458 if (cc_status.value2
1459 && modified_in_p (cc_status.value2, insn))
1460 cc_status.value2 = 0;
1469 internal_error ("unknown cc_attr value");
1475 /* Return != 0 if the return sequence for the current function is short,
1476 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1477 registers must be saved, so return 0 then. */
1480 cris_simple_epilogue (void)
1483 unsigned int reglimit = STACK_POINTER_REGNUM;
1484 bool got_really_used = false;
1486 if (! reload_completed
1487 || frame_pointer_needed
1488 || get_frame_size () != 0
1489 || current_function_pretend_args_size
1490 || current_function_args_size
1491 || current_function_outgoing_args_size
1492 || current_function_calls_eh_return
1494 /* If we're not supposed to emit prologue and epilogue, we must
1495 not emit return-type instructions. */
1496 || !TARGET_PROLOGUE_EPILOGUE)
1499 if (current_function_uses_pic_offset_table)
1501 push_topmost_sequence ();
1503 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1504 pop_topmost_sequence ();
1507 /* No simple epilogue if there are saved registers. */
1508 for (regno = 0; regno < reglimit; regno++)
1509 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1515 /* Expand a return insn (just one insn) marked as using SRP or stack
1516 slot depending on parameter ON_STACK. */
1519 cris_expand_return (bool on_stack)
1521 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1522 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1523 GCC expect just (return) to do the right thing when optimizing, so
1524 we do that until they're fixed. Currently, all return insns in a
1525 function must be the same (not really a limiting factor) so we need
1526 to check that it doesn't change half-way through. */
1527 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1529 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1530 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1532 cfun->machine->return_type
1533 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1536 /* Compute a (partial) cost for rtx X. Return true if the complete
1537 cost has been computed, and false if subexpressions should be
1538 scanned. In either case, *TOTAL contains the cost result. */
1541 cris_rtx_costs (rtx x, int code, int outer_code, int *total)
1547 HOST_WIDE_INT val = INTVAL (x);
1550 else if (val < 32 && val >= -32)
1552 /* Eight or 16 bits are a word and cycle more expensive. */
1553 else if (val <= 32767 && val >= -32768)
1555 /* A 32 bit constant (or very seldom, unsigned 16 bits) costs
1556 another word. FIXME: This isn't linear to 16 bits. */
1572 if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1575 /* Make 0.0 cheap, else test-insns will not be used. */
1580 /* Identify values that are no powers of two. Powers of 2 are
1581 taken care of already and those values should not be changed. */
1582 if (GET_CODE (XEXP (x, 1)) != CONST_INT
1583 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1585 /* If we have a multiply insn, then the cost is between
1586 1 and 2 "fast" instructions. */
1587 if (TARGET_HAS_MUL_INSNS)
1589 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1593 /* Estimate as 4 + 4 * #ofbits. */
1594 *total = COSTS_N_INSNS (132);
1603 if (GET_CODE (XEXP (x, 1)) != CONST_INT
1604 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1606 /* Estimate this as 4 + 8 * #of bits. */
1607 *total = COSTS_N_INSNS (260);
1613 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1614 /* Two constants may actually happen before optimization. */
1615 && GET_CODE (XEXP (x, 0)) != CONST_INT
1616 && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1618 *total = (rtx_cost (XEXP (x, 0), outer_code) + 2
1619 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1624 case ZERO_EXTEND: case SIGN_EXTEND:
1625 *total = rtx_cost (XEXP (x, 0), outer_code);
1633 /* The ADDRESS_COST worker. */
1636 cris_address_cost (rtx x)
1638 /* The metric to use for the cost-macros is unclear.
1639 The metric used here is (the number of cycles needed) / 2,
1640 where we consider equal a cycle for a word of code and a cycle to
1643 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1644 if (BASE_OR_AUTOINCR_P (x))
1647 /* An indirect mem must be a DIP. This means two bytes extra for code,
1648 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1649 if (GET_CODE (x) == MEM)
1652 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1653 an extra DIP prefix and 4 bytes of constant in most cases. */
1657 /* Handle BIAP and BDAP prefixes. */
1658 if (GET_CODE (x) == PLUS)
1660 rtx tem1 = XEXP (x, 0);
1661 rtx tem2 = XEXP (x, 1);
1663 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1664 recognize the typical MULT which is always in tem1 because of
1665 insn canonicalization. */
1666 if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1670 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1671 PLUS is always found in tem2. */
1672 if (GET_CODE (tem2) == CONST_INT
1673 && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1676 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1678 if (GET_CODE (tem2) == CONST_INT
1679 && CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1682 /* A BDAP with some other constant is 2 bytes extra. */
1683 if (CONSTANT_P (tem2))
1684 return (2 + 2 + 2) / 2;
1686 /* BDAP with something indirect should have a higher cost than
1687 BIAP with register. FIXME: Should it cost like a MEM or more? */
1688 /* Don't need to check it, it's the only one left.
1689 FIXME: There was a REG test missing, perhaps there are others.
1691 return (2 + 2 + 2) / 2;
1694 /* What else? Return a high cost. It matters only for valid
1695 addressing modes. */
1699 /* Check various objections to the side-effect. Used in the test-part
1700 of an anonymous insn describing an insn with a possible side-effect.
1701 Returns nonzero if the implied side-effect is ok.
1704 ops : An array of rtx:es. lreg, rreg, rval,
1705 The variables multop and other_op are indexes into this,
1706 or -1 if they are not applicable.
1707 lreg : The register that gets assigned in the side-effect.
1708 rreg : One register in the side-effect expression
1709 rval : The other register, or an int.
1710 multop : An integer to multiply rval with.
1711 other_op : One of the entities of the main effect,
1712 whose mode we must consider. */
1715 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
1716 int lreg, int rreg, int rval,
1717 int multop, int other_op)
1719 /* Find what value to multiply with, for rx =ry + rz * n. */
1720 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
1722 rtx reg_rtx = ops[rreg];
1723 rtx val_rtx = ops[rval];
1725 /* The operands may be swapped. Canonicalize them in reg_rtx and
1726 val_rtx, where reg_rtx always is a reg (for this constraint to
1728 if (! BASE_P (reg_rtx))
1729 reg_rtx = val_rtx, val_rtx = ops[rreg];
1731 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
1732 we have no business. */
1733 if (! BASE_P (reg_rtx))
1736 /* Don't do this when -mno-split. */
1737 if (!TARGET_SIDE_EFFECT_PREFIXES)
1740 /* The mult expression may be hidden in lreg. FIXME: Add more
1741 commentary about that. */
1742 if (GET_CODE (val_rtx) == MULT)
1744 mult = INTVAL (XEXP (val_rtx, 1));
1745 val_rtx = XEXP (val_rtx, 0);
1749 /* First check the "other operand". */
1752 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
1755 /* Check if the lvalue register is the same as the "other
1756 operand". If so, the result is undefined and we shouldn't do
1757 this. FIXME: Check again. */
1758 if ((BASE_P (ops[lreg])
1759 && BASE_P (ops[other_op])
1760 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
1761 || rtx_equal_p (ops[other_op], ops[lreg]))
1765 /* Do not accept frame_pointer_rtx as any operand. */
1766 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
1767 || ops[rval] == frame_pointer_rtx
1768 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
1772 && ! BASE_P (val_rtx))
1775 /* Do not allow rx = rx + n if a normal add or sub with same size
1777 if (rtx_equal_p (ops[lreg], reg_rtx)
1778 && GET_CODE (val_rtx) == CONST_INT
1779 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
1782 /* Check allowed cases, like [r(+)?].[bwd] and const. */
1783 if (CONSTANT_P (val_rtx))
1786 if (GET_CODE (val_rtx) == MEM
1787 && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
1790 if (GET_CODE (val_rtx) == SIGN_EXTEND
1791 && GET_CODE (XEXP (val_rtx, 0)) == MEM
1792 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
1795 /* If we got here, it's not a valid addressing mode. */
1798 else if (code == MULT
1799 || (code == PLUS && BASE_P (val_rtx)))
1801 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
1802 if (rtx_equal_p (ops[lreg], reg_rtx)
1803 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
1806 /* Do not allow bad multiply-values. */
1807 if (mult != 1 && mult != 2 && mult != 4)
1810 /* Only allow r + ... */
1811 if (! BASE_P (reg_rtx))
1814 /* If we got here, all seems ok.
1815 (All checks need to be done above). */
1819 /* If we get here, the caller got its initial tests wrong. */
1820 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
1823 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
1824 does not handle the case where the IN operand is strict_low_part; it
1825 does handle it for X. Test-case in Axis-20010516. This function takes
1826 care of that for THIS port. FIXME: strict_low_part is going away
1830 cris_reg_overlap_mentioned_p (rtx x, rtx in)
1832 /* The function reg_overlap_mentioned now handles when X is
1833 strict_low_part, but not when IN is a STRICT_LOW_PART. */
1834 if (GET_CODE (in) == STRICT_LOW_PART)
1837 return reg_overlap_mentioned_p (x, in);
1840 /* The TARGET_ASM_NAMED_SECTION worker.
1841 We just dispatch to the functions for ELF and a.out. */
1844 cris_target_asm_named_section (const char *name, unsigned int flags,
1848 default_no_named_section (name, flags, decl);
1850 default_elf_asm_named_section (name, flags, decl);
1853 /* Return TRUE iff X is a CONST valid for e.g. indexing. */
1856 cris_valid_pic_const (rtx x)
1858 gcc_assert (flag_pic);
1860 switch (GET_CODE (x))
1869 if (GET_CODE (x) != CONST)
1874 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
1875 if (GET_CODE (x) == PLUS
1876 && GET_CODE (XEXP (x, 0)) == UNSPEC
1877 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
1878 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1881 if (GET_CODE (x) == UNSPEC)
1882 switch (XINT (x, 1))
1884 case CRIS_UNSPEC_PLT:
1885 case CRIS_UNSPEC_PLTGOTREAD:
1886 case CRIS_UNSPEC_GOTREAD:
1887 case CRIS_UNSPEC_GOTREL:
1893 return cris_pic_symbol_type_of (x) == cris_no_symbol;
1896 /* Helper function to find the right PIC-type symbol to generate,
1897 given the original (non-PIC) representation. */
1899 enum cris_pic_symbol_type
1900 cris_pic_symbol_type_of (rtx x)
1902 switch (GET_CODE (x))
1905 return SYMBOL_REF_LOCAL_P (x)
1906 ? cris_gotrel_symbol : cris_got_symbol;
1909 return cris_gotrel_symbol;
1912 return cris_pic_symbol_type_of (XEXP (x, 0));
1917 enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
1918 enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
1920 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
1922 if (t1 == cris_got_symbol || t1 == cris_got_symbol)
1923 return cris_got_symbol_needing_fixup;
1925 return t1 != cris_no_symbol ? t1 : t2;
1930 return cris_no_symbol;
1933 /* Likely an offsettability-test attempting to add a constant to
1934 a GOTREAD symbol, which can't be handled. */
1935 return cris_invalid_pic_symbol;
1938 fatal_insn ("unrecognized supposed constant", x);
1944 /* The LEGITIMATE_PIC_OPERAND_P worker. */
1947 cris_legitimate_pic_operand (rtx x)
1949 /* Symbols are not valid PIC operands as-is; just constants. */
1950 return cris_valid_pic_const (x);
1953 /* TARGET_HANDLE_OPTION worker. We just store the values into local
1954 variables here. Checks for correct semantics are in
1955 cris_override_options. */
1958 cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
1959 int value ATTRIBUTE_UNUSED)
1967 + MASK_ALIGN_BY_32);
1970 case OPT_mno_etrax100:
1974 + MASK_ALIGN_BY_32);
1980 |= (MASK_STACK_ALIGN
1983 + MASK_ALIGN_BY_32);
1989 |= (MASK_STACK_ALIGN
1997 &= ~(MASK_STACK_ALIGN
2006 CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2011 /* The OVERRIDE_OPTIONS worker.
2012 As is the norm, this also parses -mfoo=bar type parameters. */
2015 cris_override_options (void)
2017 if (cris_max_stackframe_str)
2019 cris_max_stackframe = atoi (cris_max_stackframe_str);
2021 /* Do some sanity checking. */
2022 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2023 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2024 cris_max_stackframe, 0x20000000);
2027 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2028 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2029 cris_cpu_version = CRIS_CPU_SVINTO;
2030 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2031 cris_cpu_version = CRIS_CPU_ETRAX4;
2033 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2037 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2039 if (strcmp ("etrax4", cris_cpu_str) == 0)
2040 cris_cpu_version = 3;
2042 if (strcmp ("svinto", cris_cpu_str) == 0
2043 || strcmp ("etrax100", cris_cpu_str) == 0)
2044 cris_cpu_version = 8;
2046 if (strcmp ("ng", cris_cpu_str) == 0
2047 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2048 cris_cpu_version = 10;
2050 if (cris_cpu_version < 0 || cris_cpu_version > 10)
2051 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2054 /* Set the target flags. */
2055 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2056 target_flags |= MASK_ETRAX4_ADD;
2058 /* If this is Svinto or higher, align for 32 bit accesses. */
2059 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2061 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2062 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2065 /* Note that we do not add new flags when it can be completely
2066 described with a macro that uses -mcpu=X. So
2067 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2073 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2075 if (strcmp ("etrax4", cris_tune_str) == 0)
2078 if (strcmp ("svinto", cris_tune_str) == 0
2079 || strcmp ("etrax100", cris_tune_str) == 0)
2082 if (strcmp ("ng", cris_tune_str) == 0
2083 || strcmp ("etrax100lx", cris_tune_str) == 0)
2086 if (cris_tune < 0 || cris_tune > 10)
2087 error ("unknown CRIS cpu version specification in -mtune= : %s",
2090 if (cris_tune >= CRIS_CPU_SVINTO)
2091 /* We have currently nothing more to tune than alignment for
2094 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2095 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2100 /* Use error rather than warning, so invalid use is easily
2101 detectable. Still change to the values we expect, to avoid
2105 error ("-fPIC and -fpic are not supported in this configuration");
2109 /* Turn off function CSE. We need to have the addresses reach the
2110 call expanders to get PLT-marked, as they could otherwise be
2111 compared against zero directly or indirectly. After visiting the
2112 call expanders they will then be cse:ed, as the call expanders
2113 force_reg the addresses, effectively forcing flag_no_function_cse
2115 flag_no_function_cse = 1;
2118 if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2120 warning (0, "that particular -g option is invalid with -maout and -melinux");
2121 write_symbols = DBX_DEBUG;
2124 /* Set the per-function-data initializer. */
2125 init_machine_status = cris_init_machine_status;
2128 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2131 cris_asm_output_mi_thunk (FILE *stream,
2132 tree thunkdecl ATTRIBUTE_UNUSED,
2133 HOST_WIDE_INT delta,
2134 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2138 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2139 ADDITIVE_SIZE_MODIFIER (delta), delta,
2140 reg_names[CRIS_FIRST_ARG_REG]);
2142 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2143 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2144 reg_names[CRIS_FIRST_ARG_REG]);
2148 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2150 name = (* targetm.strip_name_encoding) (name);
2151 fprintf (stream, "add.d ");
2152 assemble_name (stream, name);
2153 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2157 fprintf (stream, "jump ");
2158 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2159 fprintf (stream, "\n");
2163 /* Boilerplate emitted at start of file.
2165 NO_APP *only at file start* means faster assembly. It also means
2166 comments are not allowed. In some cases comments will be output
2167 for debugging purposes. Make sure they are allowed then.
2169 We want a .file directive only if TARGET_ELF. */
2171 cris_file_start (void)
2173 /* These expressions can vary at run time, so we cannot put
2174 them into TARGET_INITIALIZER. */
2175 targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2176 targetm.file_start_file_directive = TARGET_ELF;
2178 default_file_start ();
2181 /* Rename the function calls for integer multiply and divide. */
2183 cris_init_libfuncs (void)
2185 set_optab_libfunc (smul_optab, SImode, "__Mul");
2186 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2187 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2188 set_optab_libfunc (smod_optab, SImode, "__Mod");
2189 set_optab_libfunc (umod_optab, SImode, "__Umod");
2192 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2196 cris_init_expanders (void)
2198 /* Nothing here at the moment. */
2201 /* Zero initialization is OK for all current fields. */
2203 static struct machine_function *
2204 cris_init_machine_status (void)
2206 return ggc_alloc_cleared (sizeof (struct machine_function));
2209 /* Split a 2 word move (DI or presumably DF) into component parts.
2210 Originally a copy of gen_split_move_double in m32r.c. */
2213 cris_split_movdx (rtx *operands)
2215 enum machine_mode mode = GET_MODE (operands[0]);
2216 rtx dest = operands[0];
2217 rtx src = operands[1];
2220 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2221 longer happen; after reload there are no SUBREGs any more, and we're
2222 only called after reload. */
2223 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2226 if (GET_CODE (dest) == REG)
2228 int dregno = REGNO (dest);
2230 /* Reg-to-reg copy. */
2231 if (GET_CODE (src) == REG)
2233 int sregno = REGNO (src);
2235 int reverse = (dregno == sregno + 1);
2237 /* We normally copy the low-numbered register first. However, if
2238 the first register operand 0 is the same as the second register of
2239 operand 1, we must copy in the opposite order. */
2240 emit_insn (gen_rtx_SET (VOIDmode,
2241 operand_subword (dest, reverse, TRUE, mode),
2242 operand_subword (src, reverse, TRUE, mode)));
2244 emit_insn (gen_rtx_SET (VOIDmode,
2245 operand_subword (dest, !reverse, TRUE, mode),
2246 operand_subword (src, !reverse, TRUE, mode)));
2248 /* Constant-to-reg copy. */
2249 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
2252 split_double (src, &words[0], &words[1]);
2253 emit_insn (gen_rtx_SET (VOIDmode,
2254 operand_subword (dest, 0, TRUE, mode),
2257 emit_insn (gen_rtx_SET (VOIDmode,
2258 operand_subword (dest, 1, TRUE, mode),
2261 /* Mem-to-reg copy. */
2262 else if (GET_CODE (src) == MEM)
2264 /* If the high-address word is used in the address, we must load it
2265 last. Otherwise, load it first. */
2266 rtx addr = XEXP (src, 0);
2268 = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2270 /* The original code implies that we can't do
2271 move.x [rN+],rM move.x [rN],rM+1
2272 when rN is dead, because of REG_NOTES damage. That is
2273 consistent with what I've seen, so don't try it.
2275 We have two different cases here; if the addr is POST_INC,
2276 just pass it through, otherwise add constants. */
2278 if (GET_CODE (addr) == POST_INC)
2280 emit_insn (gen_rtx_SET (VOIDmode,
2281 operand_subword (dest, 0, TRUE, mode),
2282 change_address (src, SImode, addr)));
2283 emit_insn (gen_rtx_SET (VOIDmode,
2284 operand_subword (dest, 1, TRUE, mode),
2285 change_address (src, SImode, addr)));
2289 /* Make sure we don't get any other addresses with
2290 embedded postincrements. They should be stopped in
2291 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2293 if (side_effects_p (addr))
2294 fatal_insn ("unexpected side-effects in address", addr);
2296 emit_insn (gen_rtx_SET
2298 operand_subword (dest, reverse, TRUE, mode),
2301 plus_constant (addr,
2302 reverse * UNITS_PER_WORD))));
2303 emit_insn (gen_rtx_SET
2305 operand_subword (dest, ! reverse, TRUE, mode),
2308 plus_constant (addr,
2314 internal_error ("Unknown src");
2316 /* Reg-to-mem copy or clear mem. */
2317 else if (GET_CODE (dest) == MEM
2318 && (GET_CODE (src) == REG
2319 || src == const0_rtx
2320 || src == CONST0_RTX (DFmode)))
2322 rtx addr = XEXP (dest, 0);
2324 if (GET_CODE (addr) == POST_INC)
2326 emit_insn (gen_rtx_SET (VOIDmode,
2327 change_address (dest, SImode, addr),
2328 operand_subword (src, 0, TRUE, mode)));
2329 emit_insn (gen_rtx_SET (VOIDmode,
2330 change_address (dest, SImode, addr),
2331 operand_subword (src, 1, TRUE, mode)));
2335 /* Make sure we don't get any other addresses with embedded
2336 postincrements. They should be stopped in
2337 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2338 if (side_effects_p (addr))
2339 fatal_insn ("unexpected side-effects in address", addr);
2341 emit_insn (gen_rtx_SET
2343 change_address (dest, SImode, addr),
2344 operand_subword (src, 0, TRUE, mode)));
2346 emit_insn (gen_rtx_SET
2348 change_address (dest, SImode,
2349 plus_constant (addr,
2351 operand_subword (src, 1, TRUE, mode)));
2356 internal_error ("Unknown dest");
2363 /* The expander for the prologue pattern name. */
2366 cris_expand_prologue (void)
2369 int size = get_frame_size ();
2370 /* Shorten the used name for readability. */
2371 int cfoa_size = current_function_outgoing_args_size;
2372 int last_movem_reg = -1;
2375 int return_address_on_stack = cris_return_address_on_stack ();
2376 int got_really_used = false;
2377 int n_movem_regs = 0;
2378 int pretend = current_function_pretend_args_size;
2380 /* Don't do anything if no prologues or epilogues are wanted. */
2381 if (!TARGET_PROLOGUE_EPILOGUE)
2384 CRIS_ASSERT (size >= 0);
2386 if (current_function_uses_pic_offset_table)
2388 /* A reference may have been optimized out (like the abort () in
2389 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2391 push_topmost_sequence ();
2393 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2394 pop_topmost_sequence ();
2397 /* Align the size to what's best for the CPU model. */
2398 if (TARGET_STACK_ALIGN)
2399 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2403 /* See also cris_setup_incoming_varargs where
2404 cfun->machine->stdarg_regs is set. There are other setters of
2405 current_function_pretend_args_size than stdarg handling, like
2406 for an argument passed with parts in R13 and stack. We must
2407 not store R13 into the pretend-area for that case, as GCC does
2408 that itself. "Our" store would be marked as redundant and GCC
2409 will attempt to remove it, which will then be flagged as an
2410 internal error; trying to remove a frame-related insn. */
2411 int stdarg_regs = cfun->machine->stdarg_regs;
2413 framesize += pretend;
2415 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2417 regno--, pretend -= 4, stdarg_regs--)
2419 insn = emit_insn (gen_rtx_SET (VOIDmode,
2421 plus_constant (stack_pointer_rtx,
2423 /* FIXME: When dwarf2 frame output and unless asynchronous
2424 exceptions, make dwarf2 bundle together all stack
2425 adjustments like it does for registers between stack
2427 RTX_FRAME_RELATED_P (insn) = 1;
2429 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2430 set_mem_alias_set (mem, get_varargs_alias_set ());
2431 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2433 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2434 the value isn't restored, so we don't want to tell dwarf2
2435 that it's been stored to stack, else EH handling info would
2439 /* For other setters of current_function_pretend_args_size, we
2440 just adjust the stack by leaving the remaining size in
2441 "pretend", handled below. */
2444 /* Save SRP if not a leaf function. */
2445 if (return_address_on_stack)
2447 insn = emit_insn (gen_rtx_SET (VOIDmode,
2449 plus_constant (stack_pointer_rtx,
2452 RTX_FRAME_RELATED_P (insn) = 1;
2454 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2455 set_mem_alias_set (mem, get_frame_alias_set ());
2456 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2457 RTX_FRAME_RELATED_P (insn) = 1;
2461 /* Set up the frame pointer, if needed. */
2462 if (frame_pointer_needed)
2464 insn = emit_insn (gen_rtx_SET (VOIDmode,
2466 plus_constant (stack_pointer_rtx,
2469 RTX_FRAME_RELATED_P (insn) = 1;
2471 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2472 set_mem_alias_set (mem, get_frame_alias_set ());
2473 insn = emit_move_insn (mem, frame_pointer_rtx);
2474 RTX_FRAME_RELATED_P (insn) = 1;
2476 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2477 RTX_FRAME_RELATED_P (insn) = 1;
2482 /* Between frame-pointer and saved registers lie the area for local
2483 variables. If we get here with "pretended" size remaining, count
2484 it into the general stack size. */
2487 /* Get a contiguous sequence of registers, starting with R0, that need
2489 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2491 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2495 /* Check if movem may be used for registers so far. */
2496 if (regno == last_movem_reg + 1)
2497 /* Yes, update next expected register. */
2498 last_movem_reg = regno;
2501 /* We cannot use movem for all registers. We have to flush
2502 any movem:ed registers we got so far. */
2503 if (last_movem_reg != -1)
2506 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2508 /* It is a win to use a side-effect assignment for
2509 64 <= size <= 128. But side-effect on movem was
2510 not usable for CRIS v0..3. Also only do it if
2511 side-effects insns are allowed. */
2512 if ((last_movem_reg + 1) * 4 + size >= 64
2513 && (last_movem_reg + 1) * 4 + size <= 128
2514 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2515 && TARGET_SIDE_EFFECT_PREFIXES)
2518 = gen_rtx_MEM (SImode,
2519 plus_constant (stack_pointer_rtx,
2520 -(n_saved * 4 + size)));
2521 set_mem_alias_set (mem, get_frame_alias_set ());
2523 = cris_emit_movem_store (mem, GEN_INT (n_saved),
2524 -(n_saved * 4 + size),
2530 = gen_rtx_SET (VOIDmode,
2532 plus_constant (stack_pointer_rtx,
2533 -(n_saved * 4 + size)));
2534 insn = emit_insn (insn);
2535 RTX_FRAME_RELATED_P (insn) = 1;
2537 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2538 set_mem_alias_set (mem, get_frame_alias_set ());
2539 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2543 framesize += n_saved * 4 + size;
2544 last_movem_reg = -1;
2548 insn = emit_insn (gen_rtx_SET (VOIDmode,
2550 plus_constant (stack_pointer_rtx,
2552 RTX_FRAME_RELATED_P (insn) = 1;
2554 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2555 set_mem_alias_set (mem, get_frame_alias_set ());
2556 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2557 RTX_FRAME_RELATED_P (insn) = 1;
2559 framesize += 4 + size;
2565 /* Check after, if we could movem all registers. This is the normal case. */
2566 if (last_movem_reg != -1)
2569 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2571 /* Side-effect on movem was not usable for CRIS v0..3. Also only
2572 do it if side-effects insns are allowed. */
2573 if ((last_movem_reg + 1) * 4 + size >= 64
2574 && (last_movem_reg + 1) * 4 + size <= 128
2575 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2576 && TARGET_SIDE_EFFECT_PREFIXES)
2579 = gen_rtx_MEM (SImode,
2580 plus_constant (stack_pointer_rtx,
2581 -(n_saved * 4 + size)));
2582 set_mem_alias_set (mem, get_frame_alias_set ());
2583 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2584 -(n_saved * 4 + size), true);
2589 = gen_rtx_SET (VOIDmode,
2591 plus_constant (stack_pointer_rtx,
2592 -(n_saved * 4 + size)));
2593 insn = emit_insn (insn);
2594 RTX_FRAME_RELATED_P (insn) = 1;
2596 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2597 set_mem_alias_set (mem, get_frame_alias_set ());
2598 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
2601 framesize += n_saved * 4 + size;
2602 /* We have to put outgoing argument space after regs. */
2605 insn = emit_insn (gen_rtx_SET (VOIDmode,
2607 plus_constant (stack_pointer_rtx,
2609 RTX_FRAME_RELATED_P (insn) = 1;
2610 framesize += cfoa_size;
2613 else if ((size + cfoa_size) > 0)
2615 insn = emit_insn (gen_rtx_SET (VOIDmode,
2617 plus_constant (stack_pointer_rtx,
2618 -(cfoa_size + size))));
2619 RTX_FRAME_RELATED_P (insn) = 1;
2620 framesize += size + cfoa_size;
2623 /* Set up the PIC register, if it is used. */
2624 if (got_really_used)
2627 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
2628 emit_move_insn (pic_offset_table_rtx, got);
2630 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
2631 follow exceptional paths and tries to delete the GOT load as
2632 unused, if it isn't used on the non-exceptional paths. Other
2633 ports have similar or other cover-ups, or plain bugs marking
2634 the GOT register load as maybe-dead. To see this, remove the
2635 line below and try libsupc++/vec.cc or a trivial
2636 "static void y (); void x () {try {y ();} catch (...) {}}". */
2637 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2640 if (cris_max_stackframe && framesize > cris_max_stackframe)
2641 warning (0, "stackframe too big: %d bytes", framesize);
2644 /* The expander for the epilogue pattern. */
2647 cris_expand_epilogue (void)
2650 int size = get_frame_size ();
2651 int last_movem_reg = -1;
2652 int argspace_offset = current_function_outgoing_args_size;
2653 int pretend = current_function_pretend_args_size;
2655 bool return_address_on_stack = cris_return_address_on_stack ();
2656 /* A reference may have been optimized out
2657 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2658 so check that it's still used. */
2659 int got_really_used = false;
2660 int n_movem_regs = 0;
2662 if (!TARGET_PROLOGUE_EPILOGUE)
2665 if (current_function_uses_pic_offset_table)
2667 /* A reference may have been optimized out (like the abort () in
2668 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2670 push_topmost_sequence ();
2672 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2673 pop_topmost_sequence ();
2676 /* Align byte count of stack frame. */
2677 if (TARGET_STACK_ALIGN)
2678 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2680 /* Check how many saved regs we can movem. They start at r0 and must
2683 regno < FIRST_PSEUDO_REGISTER;
2685 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2689 if (regno == last_movem_reg + 1)
2690 last_movem_reg = regno;
2695 /* If there was only one register that really needed to be saved
2696 through movem, don't use movem. */
2697 if (n_movem_regs == 1)
2698 last_movem_reg = -1;
2700 /* Now emit "normal" move insns for all regs higher than the movem
2702 for (regno = FIRST_PSEUDO_REGISTER - 1;
2703 regno > last_movem_reg;
2705 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2707 if (argspace_offset)
2709 /* There is an area for outgoing parameters located before
2710 the saved registers. We have to adjust for that. */
2711 emit_insn (gen_rtx_SET (VOIDmode,
2713 plus_constant (stack_pointer_rtx,
2715 /* Make sure we only do this once. */
2716 argspace_offset = 0;
2719 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2720 stack_pointer_rtx));
2721 set_mem_alias_set (mem, get_frame_alias_set ());
2722 emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
2725 /* If we have any movem-restore, do it now. */
2726 if (last_movem_reg != -1)
2728 if (argspace_offset)
2730 emit_insn (gen_rtx_SET (VOIDmode,
2732 plus_constant (stack_pointer_rtx,
2734 argspace_offset = 0;
2737 mem = gen_rtx_MEM (SImode,
2738 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
2739 set_mem_alias_set (mem, get_frame_alias_set ());
2740 emit_insn (cris_gen_movem_load (mem, GEN_INT (last_movem_reg + 1), 0));
2743 /* If we don't clobber all of the allocated stack area (we've already
2744 deallocated saved registers), GCC might want to schedule loads from
2745 the stack to *after* the stack-pointer restore, which introduces an
2746 interrupt race condition. This happened for the initial-value
2747 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
2748 other failure for that test). It also happened for the stack slot
2749 for the return value in (one version of)
2750 linux/fs/dcache.c:__d_lookup, at least with "-O2
2751 -fno-omit-frame-pointer". */
2753 /* Restore frame pointer if necessary. */
2754 if (frame_pointer_needed)
2756 emit_insn (gen_cris_frame_deallocated_barrier ());
2758 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
2759 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2760 stack_pointer_rtx));
2761 set_mem_alias_set (mem, get_frame_alias_set ());
2762 emit_move_insn (frame_pointer_rtx, mem);
2764 else if ((size + argspace_offset) != 0)
2766 emit_insn (gen_cris_frame_deallocated_barrier ());
2768 /* If there was no frame-pointer to restore sp from, we must
2769 explicitly deallocate local variables. */
2771 /* Handle space for outgoing parameters that hasn't been handled
2773 size += argspace_offset;
2775 emit_insn (gen_rtx_SET (VOIDmode,
2777 plus_constant (stack_pointer_rtx, size)));
2780 /* If this function has no pushed register parameters
2781 (stdargs/varargs), and if it is not a leaf function, then we have
2782 the return address on the stack. */
2783 if (return_address_on_stack && pretend == 0)
2785 if (current_function_calls_eh_return)
2788 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2789 mem = gen_rtx_MEM (SImode,
2790 gen_rtx_POST_INC (SImode,
2791 stack_pointer_rtx));
2792 set_mem_alias_set (mem, get_frame_alias_set ());
2793 emit_move_insn (srpreg, mem);
2795 emit_insn (gen_addsi3 (stack_pointer_rtx,
2797 gen_rtx_raw_REG (SImode,
2798 CRIS_STACKADJ_REG)));
2799 cris_expand_return (false);
2802 cris_expand_return (true);
2807 /* If we pushed some register parameters, then adjust the stack for
2811 /* If SRP is stored on the way, we need to restore it first. */
2812 if (return_address_on_stack)
2815 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2816 mem = gen_rtx_MEM (SImode,
2817 gen_rtx_POST_INC (SImode,
2818 stack_pointer_rtx));
2819 set_mem_alias_set (mem, get_frame_alias_set ());
2820 emit_move_insn (srpreg, mem);
2823 emit_insn (gen_rtx_SET (VOIDmode,
2825 plus_constant (stack_pointer_rtx, pretend)));
2828 /* Perform the "physical" unwinding that the EH machinery calculated. */
2829 if (current_function_calls_eh_return)
2830 emit_insn (gen_addsi3 (stack_pointer_rtx,
2832 gen_rtx_raw_REG (SImode,
2833 CRIS_STACKADJ_REG)));
2834 cris_expand_return (false);
2837 /* Worker function for generating movem from mem for load_multiple. */
2840 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
2842 int nregs = INTVAL (nregs_rtx);
2846 rtx srcreg = XEXP (src, 0);
2847 unsigned int regno = nregs - 1;
2850 if (GET_CODE (srcreg) == POST_INC)
2851 srcreg = XEXP (srcreg, 0);
2853 CRIS_ASSERT (REG_P (srcreg));
2855 /* Don't use movem for just one insn. The insns are equivalent except
2856 for the pipeline hazard (on v32); movem does not forward the loaded
2857 registers so there's a three cycles penalty for their use. */
2859 return gen_movsi (gen_rtx_REG (SImode, 0), src);
2861 vec = rtvec_alloc (nprefix + nregs
2862 + (GET_CODE (XEXP (src, 0)) == POST_INC));
2864 if (GET_CODE (XEXP (src, 0)) == POST_INC)
2866 RTVEC_ELT (vec, nprefix + 1)
2867 = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
2871 src = replace_equiv_address (src, srcreg);
2872 RTVEC_ELT (vec, nprefix)
2873 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
2876 for (i = 1; i < nregs; i++, eltno++)
2878 RTVEC_ELT (vec, nprefix + eltno)
2879 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
2880 adjust_address_nv (src, SImode, i * 4));
2884 return gen_rtx_PARALLEL (VOIDmode, vec);
2887 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
2888 are added that the dwarf2 machinery understands. */
2891 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
2894 int nregs = INTVAL (nregs_rtx);
2899 rtx destreg = XEXP (dest, 0);
2900 unsigned int regno = nregs - 1;
2903 if (GET_CODE (destreg) == POST_INC)
2904 increment += nregs * 4;
2906 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
2907 destreg = XEXP (destreg, 0);
2909 CRIS_ASSERT (REG_P (destreg));
2911 /* Don't use movem for just one insn. The insns are equivalent except
2912 for the pipeline hazard (on v32); movem does not forward the loaded
2913 registers so there's a three cycles penalty for use. */
2916 rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
2920 insn = emit_insn (mov);
2922 RTX_FRAME_RELATED_P (insn) = 1;
2926 /* If there was a request for a side-effect, create the ordinary
2928 vec = rtvec_alloc (2);
2930 RTVEC_ELT (vec, 0) = mov;
2931 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
2932 plus_constant (destreg, increment));
2935 RTX_FRAME_RELATED_P (mov) = 1;
2936 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
2941 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
2943 = gen_rtx_SET (VOIDmode,
2944 replace_equiv_address (dest,
2945 plus_constant (destreg,
2947 gen_rtx_REG (SImode, regno));
2950 /* The dwarf2 info wants this mark on each component in a parallel
2951 that's part of the prologue (though it's optional on the first
2954 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
2959 = gen_rtx_SET (VOIDmode, destreg,
2960 plus_constant (destreg,
2962 ? increment : nregs * 4));
2966 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
2968 /* Don't call adjust_address_nv on a post-incremented address if
2970 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
2971 dest = replace_equiv_address (dest, destreg);
2974 for (i = 1; i < nregs; i++, eltno++)
2976 RTVEC_ELT (vec, eltno)
2977 = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
2978 gen_rtx_REG (SImode, regno));
2980 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
2985 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
2987 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
2988 we need to keep the stack adjustment separate, after the
2989 MEM-setters. Else the stack-adjustment in the second component of
2990 the parallel would be mishandled; the offsets for the SETs that
2991 follow it would be wrong. We prepare for this by adding a
2992 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
2993 followed by the increment. Note that we have FRAME_RELATED_P on
2994 all the SETs, including the original stack adjustment SET in the
3000 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3001 XVECEXP (seq, 0, 0) = XVECEXP (PATTERN (insn), 0, 0);
3002 for (i = 1; i < nregs; i++)
3003 XVECEXP (seq, 0, i) = XVECEXP (PATTERN (insn), 0, i + 1);
3004 XVECEXP (seq, 0, nregs) = XVECEXP (PATTERN (insn), 0, 1);
3006 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq,
3010 RTX_FRAME_RELATED_P (insn) = 1;
3016 /* Worker function for expanding the address for PIC function calls. */
3019 cris_expand_pic_call_address (rtx *opp)
3023 gcc_assert (MEM_P (op));
3026 /* It might be that code can be generated that jumps to 0 (or to a
3027 specific address). Don't die on that. (There is a
3029 if (CONSTANT_ADDRESS_P (op) && GET_CODE (op) != CONST_INT)
3031 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3033 CRIS_ASSERT (!no_new_pseudos);
3035 /* For local symbols (non-PLT), just get the plain symbol
3036 reference into a register. For symbols that can be PLT, make
3038 if (t == cris_gotrel_symbol)
3039 op = force_reg (Pmode, op);
3040 else if (t == cris_got_symbol)
3042 if (TARGET_AVOID_GOTPLT)
3044 /* Change a "jsr sym" into (allocate register rM, rO)
3045 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT)),rM"
3046 "add.d rPIC,rM,rO", "jsr rO". */
3048 gcc_assert (! no_new_pseudos);
3049 current_function_uses_pic_offset_table = 1;
3050 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), CRIS_UNSPEC_PLT);
3051 rm = gen_reg_rtx (Pmode);
3052 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3053 ro = gen_reg_rtx (Pmode);
3054 if (expand_binop (Pmode, add_optab, rm,
3055 pic_offset_table_rtx,
3056 ro, 0, OPTAB_LIB_WIDEN) != ro)
3057 internal_error ("expand_binop failed in movsi got");
3062 /* Change a "jsr sym" into (allocate register rM, rO)
3063 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOT)),rM"
3064 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3065 marked as not trapping and not aliasing. No "move.d
3066 [rO],rP" as that would invite to re-use of a value
3067 that should not be reused. FIXME: Need a peephole2
3068 for cases when this is cse:d from the call, to change
3069 back to just get the PLT entry address, so we don't
3070 resolve the same symbol over and over (the memory
3071 access of the PLTGOT isn't constant). */
3072 rtx tem, mem, rm, ro;
3074 gcc_assert (! no_new_pseudos);
3075 current_function_uses_pic_offset_table = 1;
3076 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3077 CRIS_UNSPEC_PLTGOTREAD);
3078 rm = gen_reg_rtx (Pmode);
3079 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3080 ro = gen_reg_rtx (Pmode);
3081 if (expand_binop (Pmode, add_optab, rm,
3082 pic_offset_table_rtx,
3083 ro, 0, OPTAB_LIB_WIDEN) != ro)
3084 internal_error ("expand_binop failed in movsi got");
3085 mem = gen_rtx_MEM (Pmode, ro);
3087 /* This MEM doesn't alias anything. Whether it aliases
3088 other same symbols is unimportant. */
3089 set_mem_alias_set (mem, new_alias_set ());
3090 MEM_NOTRAP_P (mem) = 1;
3095 /* Can't possibly get a GOT-needing-fixup for a function-call,
3097 fatal_insn ("Unidentifiable call op", op);
3099 *opp = replace_equiv_address (*opp, op);
3103 /* Use from within code, from e.g. PRINT_OPERAND and
3104 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3105 different things depending on whether code operand or constant is
3109 cris_output_addr_const (FILE *file, rtx x)
3112 output_addr_const (file, x);
3116 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3119 cris_asm_output_symbol_ref (FILE *file, rtx x)
3121 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3123 if (flag_pic && in_code > 0)
3125 const char *origstr = XSTR (x, 0);
3127 str = (* targetm.strip_name_encoding) (origstr);
3128 assemble_name (file, str);
3131 if (! current_function_uses_pic_offset_table)
3132 output_operand_lossage ("PIC register isn't set up");
3135 assemble_name (file, XSTR (x, 0));
3138 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3141 cris_asm_output_label_ref (FILE *file, char *buf)
3143 if (flag_pic && in_code > 0)
3145 assemble_name (file, buf);
3148 if (! current_function_uses_pic_offset_table)
3149 internal_error ("emitting PIC operand, but PIC register isn't set up");
3152 assemble_name (file, buf);
3155 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3158 cris_output_addr_const_extra (FILE *file, rtx xconst)
3160 switch (GET_CODE (xconst))
3165 x = XVECEXP (xconst, 0, 0);
3166 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3167 || GET_CODE (x) == LABEL_REF
3168 || GET_CODE (x) == CONST);
3169 output_addr_const (file, x);
3170 switch (XINT (xconst, 1))
3172 case CRIS_UNSPEC_PLT:
3173 fprintf (file, ":PLTG");
3176 case CRIS_UNSPEC_GOTREL:
3177 fprintf (file, ":GOTOFF");
3180 case CRIS_UNSPEC_GOTREAD:
3182 fprintf (file, ":GOT16");
3184 fprintf (file, ":GOT");
3187 case CRIS_UNSPEC_PLTGOTREAD:
3189 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3191 fprintf (file, CRIS_GOTPLT_SUFFIX);
3204 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3207 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3208 int incoming ATTRIBUTE_UNUSED)
3210 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3213 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3216 cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3217 enum machine_mode mode ATTRIBUTE_UNUSED,
3218 tree type ATTRIBUTE_UNUSED,
3219 int *pretend_arg_size,
3222 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3224 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3225 cfun->machine->stdarg_regs = stdarg_regs;
3226 *pretend_arg_size = stdarg_regs * 4;
3230 fprintf (asm_out_file,
3231 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3232 ca->regs, *pretend_arg_size, second_time);
3235 /* Return true if TYPE must be passed by invisible reference.
3236 For cris, we pass <= 8 bytes by value, others by reference. */
3239 cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3240 enum machine_mode mode, tree type,
3241 bool named ATTRIBUTE_UNUSED)
3243 return (targetm.calls.must_pass_in_stack (mode, type)
3244 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3249 cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3250 tree type, bool named ATTRIBUTE_UNUSED)
3252 if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3253 && !targetm.calls.must_pass_in_stack (mode, type)
3254 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3255 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3256 return UNITS_PER_WORD;
3261 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3264 cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3266 HARD_REG_SET mof_set;
3270 CLEAR_HARD_REG_SET (mof_set);
3271 SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3273 /* For the time being, all asms clobber condition codes. Revisit when
3274 there's a reasonable use for inputs/outputs that mention condition
3277 = tree_cons (NULL_TREE,
3278 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3279 reg_names[CRIS_CC0_REGNUM]),
3282 for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3284 tree val = TREE_VALUE (t);
3286 /* The constraint letter for the singleton register class of MOF
3287 is 'h'. If it's mentioned in the constraints, the asm is
3288 MOF-aware and adding it to the clobbers would cause it to have
3289 impossible constraints. */
3290 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3292 || decl_overlaps_hard_reg_set_p (val, mof_set))
3296 for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3298 tree val = TREE_VALUE (t);
3300 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3302 || decl_overlaps_hard_reg_set_p (val, mof_set))
3306 return tree_cons (NULL_TREE,
3307 build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3308 reg_names[CRIS_MOF_REGNUM]),
3313 /* Various small functions to replace macros. Only called from a
3314 debugger. They might collide with gcc functions or system functions,
3315 so only emit them when '#if 1' above. */
3317 enum rtx_code Get_code (rtx);
3322 return GET_CODE (x);
3325 const char *Get_mode (rtx);
3330 return GET_MODE_NAME (GET_MODE (x));
3333 rtx Xexp (rtx, int);
3341 rtx Xvecexp (rtx, int, int);
3344 Xvecexp (rtx x, int n, int m)
3346 return XVECEXP (x, n, m);
3349 int Get_rtx_len (rtx);
3354 return GET_RTX_LENGTH (GET_CODE (x));
3357 /* Use upper-case to distinguish from local variables that are sometimes
3358 called next_insn and prev_insn. */
3360 rtx Next_insn (rtx);
3363 Next_insn (rtx insn)
3365 return NEXT_INSN (insn);
3368 rtx Prev_insn (rtx);
3371 Prev_insn (rtx insn)
3373 return PREV_INSN (insn);
3377 #include "gt-cris.h"
3381 * eval: (c-set-style "gnu")
3382 * indent-tabs-mode: t