1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
37 #include "diagnostic-core.h"
44 #include "target-def.h"
49 /* Usable when we have an amount to add or subtract, and want the
50 optimal size of the insn. */
51 #define ADDITIVE_SIZE_MODIFIER(size) \
52 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54 #define LOSE_AND_RETURN(msgid, x) \
57 cris_operand_lossage (msgid, x); \
61 enum cris_retinsn_type
62 { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
64 /* Per-function machine data. */
65 struct GTY(()) machine_function
67 int needs_return_address_on_stack;
69 /* This is the number of registers we save in the prologue due to
73 enum cris_retinsn_type return_type;
76 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
78 static char cris_output_insn_is_bound = 0;
80 /* In code for output macros, this is how we know whether e.g. constant
81 goes in code or in a static initializer. */
82 static int in_code = 0;
84 /* Fix for reg_overlap_mentioned_p. */
85 static int cris_reg_overlap_mentioned_p (rtx, rtx);
87 static enum machine_mode cris_promote_function_mode (const_tree, enum machine_mode,
88 int *, const_tree, int);
90 static void cris_print_base (rtx, FILE *);
92 static void cris_print_index (rtx, FILE *);
94 static void cris_output_addr_const (FILE *, rtx);
96 static struct machine_function * cris_init_machine_status (void);
98 static rtx cris_struct_value_rtx (tree, int);
100 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
101 tree type, int *, int);
103 static int cris_initial_frame_pointer_offset (void);
105 static void cris_operand_lossage (const char *, rtx);
107 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
109 static void cris_print_operand (FILE *, rtx, int);
111 static void cris_print_operand_address (FILE *, rtx);
113 static bool cris_print_operand_punct_valid_p (unsigned char code);
115 static void cris_conditional_register_usage (void);
117 static void cris_asm_output_mi_thunk
118 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
120 static void cris_file_start (void);
121 static void cris_init_libfuncs (void);
123 static int cris_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
124 static int cris_memory_move_cost (enum machine_mode, reg_class_t, bool);
125 static bool cris_rtx_costs (rtx, int, int, int *, bool);
126 static int cris_address_cost (rtx, bool);
127 static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
129 static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
131 static rtx cris_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
133 static rtx cris_function_incoming_arg (CUMULATIVE_ARGS *,
134 enum machine_mode, const_tree, bool);
135 static void cris_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
137 static tree cris_md_asm_clobbers (tree, tree, tree);
139 static bool cris_handle_option (size_t, const char *, int);
140 static void cris_option_override (void);
142 static bool cris_frame_pointer_required (void);
144 static void cris_asm_trampoline_template (FILE *);
145 static void cris_trampoline_init (rtx, tree, rtx);
147 static rtx cris_function_value(const_tree, const_tree, bool);
148 static rtx cris_libcall_value (enum machine_mode, const_rtx);
150 /* This is the parsed result of the "-max-stack-stackframe=" option. If
151 it (still) is zero, then there was no such option given. */
152 int cris_max_stackframe = 0;
154 /* This is the parsed result of the "-march=" option, if given. */
155 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
157 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
159 static const struct default_options cris_option_optimization_table[] =
161 { OPT_LEVELS_2_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
162 { OPT_LEVELS_NONE, 0, NULL, 0 }
165 #undef TARGET_ASM_ALIGNED_HI_OP
166 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
167 #undef TARGET_ASM_ALIGNED_SI_OP
168 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
169 #undef TARGET_ASM_ALIGNED_DI_OP
170 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
172 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
173 available in ELF. These "normal" pseudos do not have any alignment
174 constraints or side-effects. */
175 #undef TARGET_ASM_UNALIGNED_HI_OP
176 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
178 #undef TARGET_ASM_UNALIGNED_SI_OP
179 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
181 #undef TARGET_ASM_UNALIGNED_DI_OP
182 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
184 #undef TARGET_PRINT_OPERAND
185 #define TARGET_PRINT_OPERAND cris_print_operand
186 #undef TARGET_PRINT_OPERAND_ADDRESS
187 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
188 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
189 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
191 #undef TARGET_CONDITIONAL_REGISTER_USAGE
192 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
194 #undef TARGET_ASM_OUTPUT_MI_THUNK
195 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
196 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
197 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
199 #undef TARGET_ASM_FILE_START
200 #define TARGET_ASM_FILE_START cris_file_start
202 #undef TARGET_INIT_LIBFUNCS
203 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
205 #undef TARGET_REGISTER_MOVE_COST
206 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
207 #undef TARGET_MEMORY_MOVE_COST
208 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
209 #undef TARGET_RTX_COSTS
210 #define TARGET_RTX_COSTS cris_rtx_costs
211 #undef TARGET_ADDRESS_COST
212 #define TARGET_ADDRESS_COST cris_address_cost
214 #undef TARGET_PROMOTE_FUNCTION_MODE
215 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
217 #undef TARGET_STRUCT_VALUE_RTX
218 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
219 #undef TARGET_SETUP_INCOMING_VARARGS
220 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
221 #undef TARGET_PASS_BY_REFERENCE
222 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
223 #undef TARGET_ARG_PARTIAL_BYTES
224 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
225 #undef TARGET_FUNCTION_ARG
226 #define TARGET_FUNCTION_ARG cris_function_arg
227 #undef TARGET_FUNCTION_INCOMING_ARG
228 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
229 #undef TARGET_FUNCTION_ARG_ADVANCE
230 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
231 #undef TARGET_MD_ASM_CLOBBERS
232 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
233 #undef TARGET_DEFAULT_TARGET_FLAGS
234 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
235 #undef TARGET_HANDLE_OPTION
236 #define TARGET_HANDLE_OPTION cris_handle_option
237 #undef TARGET_FRAME_POINTER_REQUIRED
238 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
240 #undef TARGET_OPTION_OVERRIDE
241 #define TARGET_OPTION_OVERRIDE cris_option_override
242 #undef TARGET_OPTION_OPTIMIZATION_TABLE
243 #define TARGET_OPTION_OPTIMIZATION_TABLE cris_option_optimization_table
245 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
246 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
247 #undef TARGET_TRAMPOLINE_INIT
248 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
250 #undef TARGET_FUNCTION_VALUE
251 #define TARGET_FUNCTION_VALUE cris_function_value
252 #undef TARGET_LIBCALL_VALUE
253 #define TARGET_LIBCALL_VALUE cris_libcall_value
255 struct gcc_target targetm = TARGET_INITIALIZER;
257 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
260 cris_movem_load_rest_p (rtx op, int offs)
262 unsigned int reg_count = XVECLEN (op, 0) - offs;
268 unsigned int regno = 0;
270 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
271 other than (MEM reg). */
273 || GET_CODE (XVECEXP (op, 0, offs)) != SET
274 || !REG_P (SET_DEST (XVECEXP (op, 0, offs)))
275 || !MEM_P (SET_SRC (XVECEXP (op, 0, offs))))
278 /* Check a possible post-inc indicator. */
279 if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
281 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
282 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
288 || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
289 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
290 || !CONST_INT_P (inc)
291 || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
301 regno = reg_count - 1;
304 elt = XVECEXP (op, 0, offs);
305 src_addr = XEXP (SET_SRC (elt), 0);
307 if (GET_CODE (elt) != SET
308 || !REG_P (SET_DEST (elt))
309 || GET_MODE (SET_DEST (elt)) != SImode
310 || REGNO (SET_DEST (elt)) != regno
311 || !MEM_P (SET_SRC (elt))
312 || GET_MODE (SET_SRC (elt)) != SImode
313 || !memory_address_p (SImode, src_addr))
316 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
318 rtx elt = XVECEXP (op, 0, i);
321 if (GET_CODE (elt) != SET
322 || !REG_P (SET_DEST (elt))
323 || GET_MODE (SET_DEST (elt)) != SImode
324 || REGNO (SET_DEST (elt)) != regno
325 || !MEM_P (SET_SRC (elt))
326 || GET_MODE (SET_SRC (elt)) != SImode
327 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
328 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
329 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
330 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
337 /* Worker function for predicate for the parallel contents in a movem
341 cris_store_multiple_op_p (rtx op)
343 int reg_count = XVECLEN (op, 0);
354 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
355 other than (MEM reg) and (MEM (PLUS reg const)). */
359 elt = XVECEXP (op, 0, 0);
361 if (GET_CODE (elt) != SET)
364 dest = SET_DEST (elt);
366 if (!REG_P (SET_SRC (elt)) || !MEM_P (dest))
369 dest_addr = XEXP (dest, 0);
371 /* Check a possible post-inc indicator. */
372 if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
374 rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
375 rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
381 || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
382 || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
383 || !CONST_INT_P (inc)
384 /* Support increment by number of registers, and by the offset
385 of the destination, if it has the form (MEM (PLUS reg
387 || !((REG_P (dest_addr)
388 && REGNO (dest_addr) == REGNO (reg)
389 && INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
390 || (GET_CODE (dest_addr) == PLUS
391 && REG_P (XEXP (dest_addr, 0))
392 && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
393 && CONST_INT_P (XEXP (dest_addr, 1))
394 && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
405 regno = reg_count - 1;
408 if (GET_CODE (elt) != SET
409 || !REG_P (SET_SRC (elt))
410 || GET_MODE (SET_SRC (elt)) != SImode
411 || REGNO (SET_SRC (elt)) != (unsigned int) regno
412 || !MEM_P (SET_DEST (elt))
413 || GET_MODE (SET_DEST (elt)) != SImode)
416 if (REG_P (dest_addr))
418 dest_base = dest_addr;
421 else if (GET_CODE (dest_addr) == PLUS
422 && REG_P (XEXP (dest_addr, 0))
423 && CONST_INT_P (XEXP (dest_addr, 1)))
425 dest_base = XEXP (dest_addr, 0);
426 offset = INTVAL (XEXP (dest_addr, 1));
431 for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
433 rtx elt = XVECEXP (op, 0, i);
436 if (GET_CODE (elt) != SET
437 || !REG_P (SET_SRC (elt))
438 || GET_MODE (SET_SRC (elt)) != SImode
439 || REGNO (SET_SRC (elt)) != (unsigned int) regno
440 || !MEM_P (SET_DEST (elt))
441 || GET_MODE (SET_DEST (elt)) != SImode
442 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
443 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
444 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
445 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
452 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
455 cris_conditional_register_usage (void)
457 /* FIXME: This isn't nice. We should be able to use that register for
458 something else if the PIC table isn't needed. */
460 fixed_regs[PIC_OFFSET_TABLE_REGNUM]
461 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
463 /* Allow use of ACR (PC in pre-V32) and tweak order. */
466 static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32;
469 fixed_regs[CRIS_ACR_REGNUM] = 0;
472 i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]);
474 reg_alloc_order[i] = reg_alloc_order_v32[i];
477 if (TARGET_HAS_MUL_INSNS)
478 fixed_regs[CRIS_MOF_REGNUM] = 0;
480 /* On early versions, we must use the 16-bit condition-code register,
481 which has another name. */
482 if (cris_cpu_version < 8)
483 reg_names[CRIS_CC0_REGNUM] = "ccr";
486 /* Return crtl->uses_pic_offset_table. For use in cris.md,
487 since some generated files do not include function.h. */
490 cris_cfun_uses_pic_table (void)
492 return crtl->uses_pic_offset_table;
495 /* Given an rtx, return the text string corresponding to the CODE of X.
496 Intended for use in the assembly language output section of a
502 cris_output_insn_is_bound = 0;
503 switch (GET_CODE (x))
514 /* This function is for retrieving a part of an instruction name for
515 an operator, for immediate output. If that ever happens for
516 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
518 internal_error ("MULT case in cris_op_str");
554 /* Used to control the sign/zero-extend character for the 'E' modifier.
556 cris_output_insn_is_bound = 1;
561 return "Unknown operator";
566 /* Emit an error message when we're in an asm, and a fatal error for
567 "normal" insns. Formatted output isn't easily implemented, since we
568 use output_operand_lossage to output the actual message and handle the
569 categorization of the error. */
572 cris_operand_lossage (const char *msgid, rtx op)
575 output_operand_lossage ("%s", msgid);
578 /* Print an index part of an address to file. */
581 cris_print_index (rtx index, FILE *file)
583 /* Make the index "additive" unless we'll output a negative number, in
584 which case the sign character is free (as in free beer). */
585 if (!CONST_INT_P (index) || INTVAL (index) >= 0)
589 fprintf (file, "$%s.b", reg_names[REGNO (index)]);
590 else if (CONSTANT_P (index))
591 cris_output_addr_const (file, index);
592 else if (GET_CODE (index) == MULT)
594 fprintf (file, "$%s.",
595 reg_names[REGNO (XEXP (index, 0))]);
597 putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
599 else if (GET_CODE (index) == SIGN_EXTEND && MEM_P (XEXP (index, 0)))
601 rtx inner = XEXP (index, 0);
602 rtx inner_inner = XEXP (inner, 0);
604 if (GET_CODE (inner_inner) == POST_INC)
606 fprintf (file, "[$%s+].",
607 reg_names[REGNO (XEXP (inner_inner, 0))]);
608 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
612 fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
614 putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
617 else if (MEM_P (index))
619 rtx inner = XEXP (index, 0);
620 if (GET_CODE (inner) == POST_INC)
621 fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
623 fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
626 cris_operand_lossage ("unexpected index-type in cris_print_index",
630 /* Print a base rtx of an address to file. */
633 cris_print_base (rtx base, FILE *file)
636 fprintf (file, "$%s", reg_names[REGNO (base)]);
637 else if (GET_CODE (base) == POST_INC)
639 gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM);
640 fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
643 cris_operand_lossage ("unexpected base-type in cris_print_base",
647 /* Usable as a guard in expressions. */
650 cris_fatal (char *arg)
652 internal_error (arg);
654 /* We'll never get here; this is just to appease compilers. */
658 /* Return nonzero if REGNO is an ordinary register that *needs* to be
659 saved together with other registers, possibly by a MOVEM instruction,
660 or is saved for target-independent reasons. There may be
661 target-dependent reasons to save the register anyway; this is just a
662 wrapper for a complicated conditional. */
665 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
668 (((df_regs_ever_live_p (regno)
669 && !call_used_regs[regno])
670 || (regno == PIC_OFFSET_TABLE_REGNUM
672 /* It is saved anyway, if there would be a gap. */
674 && df_regs_ever_live_p (regno + 1)
675 && !call_used_regs[regno + 1]))))
676 && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
677 && regno != CRIS_SRP_REGNUM)
678 || (crtl->calls_eh_return
679 && (regno == EH_RETURN_DATA_REGNO (0)
680 || regno == EH_RETURN_DATA_REGNO (1)
681 || regno == EH_RETURN_DATA_REGNO (2)
682 || regno == EH_RETURN_DATA_REGNO (3)));
685 /* The PRINT_OPERAND worker. */
688 cris_print_operand (FILE *file, rtx x, int code)
692 /* Size-strings corresponding to MULT expressions. */
693 static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
695 /* New code entries should just be added to the switch below. If
696 handling is finished, just return. If handling was just a
697 modification of the operand, the modified operand should be put in
698 "operand", and then do a break to let default handling
699 (zero-modifier) output the operand. */
704 /* Print the unsigned supplied integer as if it were signed
705 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
707 || !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
708 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
709 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
710 INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
714 /* Print assembler code for operator. */
715 fprintf (file, "%s", cris_op_str (operand));
720 /* A movem modifier working on a parallel; output the register
724 if (GET_CODE (x) != PARALLEL)
725 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
727 /* The second item can be (set reg (plus reg const)) to denote a
730 = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
732 : XVECLEN (x, 0) - 1);
734 fprintf (file, "$%s", reg_names [regno]);
740 /* A similar movem modifier; output the memory operand. */
743 if (GET_CODE (x) != PARALLEL)
744 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
746 /* The lowest mem operand is in the first item, but perhaps it
747 needs to be output as postincremented. */
748 addr = MEM_P (SET_SRC (XVECEXP (x, 0, 0)))
749 ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
750 : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
752 /* The second item can be a (set reg (plus reg const)) to denote
754 if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
756 /* It's a post-increment, if the address is a naked (reg). */
758 addr = gen_rtx_POST_INC (SImode, addr);
761 /* Otherwise, it's a side-effect; RN=RN+M. */
762 fprintf (file, "[$%s=$%s%s%d]",
763 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
764 reg_names [REGNO (XEXP (addr, 0))],
765 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
766 (int) INTVAL (XEXP (addr, 1)));
770 output_address (addr);
775 /* Adjust a power of two to its log2. */
776 if (!CONST_INT_P (x) || exact_log2 (INTVAL (x)) < 0 )
777 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
778 fprintf (file, "%d", exact_log2 (INTVAL (x)));
782 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
783 respectively. This modifier also terminates the inhibiting
784 effects of the 'x' modifier. */
785 cris_output_insn_is_bound = 0;
786 if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
790 if (INTVAL (x) <= 255)
792 else if (INTVAL (x) <= 65535)
802 /* For a non-integer, print the size of the operand. */
803 putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
804 ? 'd' : GET_MODE (x) == HImode ? 'w'
805 : GET_MODE (x) == QImode ? 'b'
806 /* If none of the above, emit an erroneous size letter. */
812 /* Const_int: print b for -127 <= x <= 255,
813 w for -32768 <= x <= 65535, else die. */
815 || INTVAL (x) < -32768 || INTVAL (x) > 65535)
816 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
817 putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
821 /* If this is a GOT-symbol, print the size-letter corresponding to
822 -fpic/-fPIC. For everything else, print "d". */
824 && GET_CODE (x) == CONST
825 && GET_CODE (XEXP (x, 0)) == UNSPEC
826 && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD)
831 /* Output a 'nop' if there's nothing for the delay slot.
832 This method stolen from the sparc files. */
833 if (dbr_sequence_length () == 0)
834 fputs ("\n\tnop", file);
838 /* Output directive for alignment padded with "nop" insns.
839 Optimizing for size, it's plain 4-byte alignment, otherwise we
840 align the section to a cache-line (32 bytes) and skip at max 2
841 bytes, i.e. we skip if it's the last insn on a cache-line. The
842 latter is faster by a small amount (for two test-programs 99.6%
843 and 99.9%) and larger by a small amount (ditto 100.1% and
844 100.2%). This is supposed to be the simplest yet performance-
845 wise least intrusive way to make sure the immediately following
846 (supposed) muls/mulu insn isn't located at the end of a
850 ? ".p2alignw 2,0x050f\n\t"
851 : ".p2alignw 5,0x050f,2\n\t", file);
855 /* The PIC register. */
857 internal_error ("invalid use of ':' modifier");
858 fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
862 /* Print high (most significant) part of something. */
863 switch (GET_CODE (operand))
866 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
867 value is kept here, and so may be other than 0 or -1. */
868 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
869 INTVAL (operand_subword (operand, 1, 0, DImode)));
873 /* High part of a long long constant. */
874 if (GET_MODE (operand) == VOIDmode)
876 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
880 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
883 /* Print reg + 1. Check that there's not an attempt to print
884 high-parts of registers like stack-pointer or higher, except
885 for SRP (where the "high part" is MOF). */
886 if (REGNO (operand) > STACK_POINTER_REGNUM - 2
887 && (REGNO (operand) != CRIS_SRP_REGNUM
888 || CRIS_SRP_REGNUM + 1 != CRIS_MOF_REGNUM
889 || fixed_regs[CRIS_MOF_REGNUM] != 0))
890 LOSE_AND_RETURN ("bad register", operand);
891 fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
895 /* Adjust memory address to high part. */
897 rtx adj_mem = operand;
899 = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
901 /* Adjust so we can use two SImode in DImode.
902 Calling adj_offsettable_operand will make sure it is an
903 offsettable address. Don't do this for a postincrement
904 though; it should remain as it was. */
905 if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
907 = adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
909 output_address (XEXP (adj_mem, 0));
914 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
918 /* Strip the MEM expression. */
919 operand = XEXP (operand, 0);
923 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
924 iterators and attributes in cris.md to avoid the need for %x
925 and %E (and %e) and state passed between those modifiers. */
926 cris_output_insn_is_bound = 0;
929 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
930 cris_output_insn_is_bound is nonzero. */
931 if (GET_CODE (operand) != SIGN_EXTEND
932 && GET_CODE (operand) != ZERO_EXTEND
933 && !CONST_INT_P (operand))
934 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
936 if (cris_output_insn_is_bound)
938 cris_output_insn_is_bound = 0;
942 putc (GET_CODE (operand) == SIGN_EXTEND
943 || (CONST_INT_P (operand) && INTVAL (operand) < 0)
948 /* Print the size letter of the inner element. We can do it by
949 calling ourselves with the 's' modifier. */
950 if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
951 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
952 cris_print_operand (file, XEXP (operand, 0), 's');
956 /* Print the least significant part of operand. */
957 if (GET_CODE (operand) == CONST_DOUBLE)
959 fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
962 else if (HOST_BITS_PER_WIDE_INT > 32 && CONST_INT_P (operand))
964 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
965 INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
968 /* Otherwise the least significant part equals the normal part,
969 so handle it normally. */
973 /* When emitting an add for the high part of a DImode constant, we
974 want to use addq for 0 and adds.w for -1. */
975 if (!CONST_INT_P (operand))
976 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
977 fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
981 /* If this is a GOT symbol, force it to be emitted as :GOT and
982 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
983 Avoid making this too much of a special case. */
984 if (flag_pic == 1 && CONSTANT_P (operand))
986 int flag_pic_save = flag_pic;
989 cris_output_addr_const (file, operand);
990 flag_pic = flag_pic_save;
996 /* When emitting an sub for the high part of a DImode constant, we
997 want to use subq for 0 and subs.w for -1. */
998 if (!CONST_INT_P (operand))
999 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
1000 fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
1004 /* Print the operand as the index-part of an address.
1005 Easiest way out is to use cris_print_index. */
1006 cris_print_index (operand, file);
1010 /* Print the size letter for an operand to a MULT, which must be a
1011 const_int with a suitable value. */
1012 if (!CONST_INT_P (operand) || INTVAL (operand) > 4)
1013 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
1014 fprintf (file, "%s", mults[INTVAL (operand)]);
1018 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1020 && GET_CODE (operand) == CONST
1021 && GET_CODE (XEXP (operand, 0)) == UNSPEC
1022 && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD)
1023 fprintf (file, "u.w");
1025 fprintf (file, ".d");
1029 /* No code, print as usual. */
1033 LOSE_AND_RETURN ("invalid operand modifier letter", x);
1036 /* Print an operand as without a modifier letter. */
1037 switch (GET_CODE (operand))
1040 if (REGNO (operand) > 15
1041 && REGNO (operand) != CRIS_MOF_REGNUM
1042 && REGNO (operand) != CRIS_SRP_REGNUM
1043 && REGNO (operand) != CRIS_CC0_REGNUM)
1044 internal_error ("internal error: bad register: %d", REGNO (operand));
1045 fprintf (file, "$%s", reg_names[REGNO (operand)]);
1049 output_address (XEXP (operand, 0));
1053 if (GET_MODE (operand) == VOIDmode)
1054 /* A long long constant. */
1055 output_addr_const (file, operand);
1058 /* Only single precision is allowed as plain operands the
1059 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1064 /* FIXME: Perhaps check overflow of the "single". */
1065 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1066 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1068 fprintf (file, "0x%lx", l);
1075 cris_output_addr_const (file, operand);
1081 /* For a (MULT (reg X) const_int) we output "rX.S". */
1082 int i = CONST_INT_P (XEXP (operand, 1))
1083 ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1084 rtx reg = CONST_INT_P (XEXP (operand, 1))
1085 ? XEXP (operand, 0) : XEXP (operand, 1);
1088 || (!CONST_INT_P (XEXP (operand, 0))
1089 && !CONST_INT_P (XEXP (operand, 1))))
1090 LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1092 cris_print_base (reg, file);
1093 fprintf (file, ".%c",
1094 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1096 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1102 /* No need to handle all strange variants, let output_addr_const
1104 if (CONSTANT_P (operand))
1106 cris_output_addr_const (file, operand);
1110 LOSE_AND_RETURN ("unexpected operand", x);
1115 cris_print_operand_punct_valid_p (unsigned char code)
1117 return (code == '#' || code == '!' || code == ':');
1120 /* The PRINT_OPERAND_ADDRESS worker. */
1123 cris_print_operand_address (FILE *file, rtx x)
1125 /* All these were inside MEM:s so output indirection characters. */
1128 if (CONSTANT_ADDRESS_P (x))
1129 cris_output_addr_const (file, x);
1130 else if (BASE_OR_AUTOINCR_P (x))
1131 cris_print_base (x, file);
1132 else if (GET_CODE (x) == PLUS)
1140 cris_print_base (x1, file);
1141 cris_print_index (x2, file);
1143 else if (BASE_P (x2))
1145 cris_print_base (x2, file);
1146 cris_print_index (x1, file);
1149 LOSE_AND_RETURN ("unrecognized address", x);
1153 /* A DIP. Output more indirection characters. */
1155 cris_print_base (XEXP (x, 0), file);
1159 LOSE_AND_RETURN ("unrecognized address", x);
1164 /* The RETURN_ADDR_RTX worker.
1165 We mark that the return address is used, either by EH or
1166 __builtin_return_address, for use by the function prologue and
1167 epilogue. FIXME: This isn't optimal; we just use the mark in the
1168 prologue and epilogue to say that the return address is to be stored
1169 in the stack frame. We could return SRP for leaf-functions and use the
1170 initial-value machinery. */
1173 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1175 cfun->machine->needs_return_address_on_stack = 1;
1177 /* The return-address is stored just above the saved frame-pointer (if
1178 present). Apparently we can't eliminate from the frame-pointer in
1179 that direction, so use the incoming args (maybe pretended) pointer. */
1181 ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1185 /* Accessor used in cris.md:return because cfun->machine isn't available
1189 cris_return_address_on_stack (void)
1191 return df_regs_ever_live_p (CRIS_SRP_REGNUM)
1192 || cfun->machine->needs_return_address_on_stack;
1195 /* Accessor used in cris.md:return because cfun->machine isn't available
1199 cris_return_address_on_stack_for_return (void)
1201 return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1202 : cris_return_address_on_stack ();
1205 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1206 handles FP -> SP elimination offset. */
1209 cris_initial_frame_pointer_offset (void)
1213 /* Initial offset is 0 if we don't have a frame pointer. */
1215 bool got_really_used = false;
1217 if (crtl->uses_pic_offset_table)
1219 push_topmost_sequence ();
1221 = reg_used_between_p (pic_offset_table_rtx, get_insns (),
1223 pop_topmost_sequence ();
1226 /* And 4 for each register pushed. */
1227 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1228 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1231 /* And then, last, we add the locals allocated. */
1232 offs += get_frame_size ();
1234 /* And more; the accumulated args size. */
1235 offs += crtl->outgoing_args_size;
1237 /* Then round it off, in case we use aligned stack. */
1238 if (TARGET_STACK_ALIGN)
1239 offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1244 /* The INITIAL_ELIMINATION_OFFSET worker.
1245 Calculate the difference between imaginary registers such as frame
1246 pointer and the stack pointer. Used to eliminate the frame pointer
1247 and imaginary arg pointer. */
1250 cris_initial_elimination_offset (int fromreg, int toreg)
1253 = cris_initial_frame_pointer_offset ();
1255 /* We should be able to use regs_ever_live and related prologue
1256 information here, or alpha should not as well. */
1257 bool return_address_on_stack = cris_return_address_on_stack ();
1259 /* Here we act as if the frame-pointer were needed. */
1260 int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1262 if (fromreg == ARG_POINTER_REGNUM
1263 && toreg == FRAME_POINTER_REGNUM)
1264 return ap_fp_offset;
1266 /* Between the frame pointer and the stack are only "normal" stack
1267 variables and saved registers. */
1268 if (fromreg == FRAME_POINTER_REGNUM
1269 && toreg == STACK_POINTER_REGNUM)
1270 return fp_sp_offset;
1272 /* We need to balance out the frame pointer here. */
1273 if (fromreg == ARG_POINTER_REGNUM
1274 && toreg == STACK_POINTER_REGNUM)
1275 return ap_fp_offset + fp_sp_offset - 4;
1280 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1283 cris_reload_address_legitimized (rtx x,
1284 enum machine_mode mode ATTRIBUTE_UNUSED,
1285 int opnum ATTRIBUTE_UNUSED,
1287 int ind_levels ATTRIBUTE_UNUSED)
1289 enum reload_type type = (enum reload_type) itype;
1293 if (GET_CODE (x) != PLUS)
1301 op1p = &XEXP (x, 1);
1306 if (GET_CODE (op0) == SIGN_EXTEND && MEM_P (XEXP (op0, 0)))
1308 rtx op00 = XEXP (op0, 0);
1309 rtx op000 = XEXP (op00, 0);
1310 rtx *op000p = &XEXP (op00, 0);
1312 if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1314 || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1316 bool something_reloaded = false;
1318 if (GET_CODE (op000) == POST_INC
1319 && REG_P (XEXP (op000, 0))
1320 && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1321 /* No, this gets too complicated and is too rare to care
1322 about trying to improve on the general code Here.
1323 As the return-value is an all-or-nothing indicator, we
1324 punt on the other register too. */
1328 && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1330 /* The address of the inner mem is a pseudo or wrong
1331 reg: reload that. */
1332 push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1333 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1334 something_reloaded = true;
1337 if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1339 /* Base register is a pseudo or wrong reg: reload it. */
1340 push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1341 GET_MODE (x), VOIDmode, 0, 0,
1343 something_reloaded = true;
1346 gcc_assert (something_reloaded);
1355 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1358 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1359 reg_class_t from, reg_class_t to)
1363 /* Pretend that classes that we don't support are ALL_REGS, so
1364 we give them the highest cost. */
1365 if (from != SPECIAL_REGS && from != MOF_REGS
1366 && from != GENERAL_REGS && from != GENNONACR_REGS)
1369 if (to != SPECIAL_REGS && to != MOF_REGS
1370 && to != GENERAL_REGS && to != GENNONACR_REGS)
1374 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1375 their move cost within that class is higher. How about 7? That's 3
1376 for a move to a GENERAL_REGS register, 3 for the move from the
1377 GENERAL_REGS register, and 1 for the increased register pressure.
1378 Also, it's higher than the memory move cost, which is in order.
1379 We also do this for ALL_REGS, since we don't want that class to be
1380 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1381 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1382 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1383 used when a GENERAL_REGS should be used, even if there are call-saved
1384 GENERAL_REGS left to allocate. This is because the fall-back when
1385 the most preferred register class isn't available, isn't the next
1386 (or next good) wider register class, but the *most widest* register
1389 if ((reg_classes_intersect_p (from, SPECIAL_REGS)
1390 && reg_classes_intersect_p (to, SPECIAL_REGS))
1391 || from == ALL_REGS || to == ALL_REGS)
1394 if (reg_classes_intersect_p (from, SPECIAL_REGS)
1395 || reg_classes_intersect_p (to, SPECIAL_REGS))
1401 /* Worker function for TARGET_MEMORY_MOVE_COST.
1403 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1407 cris_memory_move_cost (enum machine_mode mode,
1408 reg_class_t rclass ATTRIBUTE_UNUSED,
1409 bool in ATTRIBUTE_UNUSED)
1418 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1419 FIXME: this code is historical; its functionality should be
1420 refactored to look at insn attributes and moved to
1421 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1424 cris_normal_notice_update_cc (rtx exp, rtx insn)
1426 /* "Normal" means, for:
1431 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1432 register or (v32 and (...) is -32..-1), then CC does not change.
1433 CC_NO_OVERFLOW unless (...) is reg or mem.
1442 (set (reg1) (mem (bdap/biap)))
1443 (set (reg2) (bdap/biap))):
1444 CC is (reg1) and (mem (reg2))
1447 (set (mem (bdap/biap)) (reg1)) [or 0]
1448 (set (reg2) (bdap/biap))):
1451 (where reg and mem includes strict_low_parts variants thereof)
1453 For all others, assume CC is clobbered.
1454 Note that we do not have to care about setting CC_NO_OVERFLOW,
1455 since the overflow flag is set to 0 (i.e. right) for
1456 instructions where it does not have any sane sense, but where
1457 other flags have meanings. (This includes shifts; the carry is
1460 Note that there are other parallel constructs we could match,
1461 but we don't do that yet. */
1463 if (GET_CODE (exp) == SET)
1465 /* FIXME: Check when this happens. It looks like we should
1466 actually do a CC_STATUS_INIT here to be safe. */
1467 if (SET_DEST (exp) == pc_rtx)
1470 /* Record CC0 changes, so we do not have to output multiple
1472 if (SET_DEST (exp) == cc0_rtx)
1476 if (GET_CODE (SET_SRC (exp)) == COMPARE
1477 && XEXP (SET_SRC (exp), 1) == const0_rtx)
1478 cc_status.value1 = XEXP (SET_SRC (exp), 0);
1480 cc_status.value1 = SET_SRC (exp);
1482 /* Handle flags for the special btstq on one bit. */
1483 if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
1484 && XEXP (cc_status.value1, 1) == const1_rtx)
1486 if (CONST_INT_P (XEXP (cc_status.value1, 0)))
1488 cc_status.flags = CC_INVERTED;
1490 /* A one-bit btstq. */
1491 cc_status.flags = CC_Z_IN_NOT_N;
1494 else if (GET_CODE (SET_SRC (exp)) == COMPARE)
1496 if (!REG_P (XEXP (SET_SRC (exp), 0))
1497 && XEXP (SET_SRC (exp), 1) != const0_rtx)
1498 /* For some reason gcc will not canonicalize compare
1499 operations, reversing the sign by itself if
1500 operands are in wrong order. */
1501 /* (But NOT inverted; eq is still eq.) */
1502 cc_status.flags = CC_REVERSED;
1504 /* This seems to be overlooked by gcc. FIXME: Check again.
1505 FIXME: Is it really safe? */
1507 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1508 XEXP (SET_SRC (exp), 0),
1509 XEXP (SET_SRC (exp), 1));
1513 else if (REG_P (SET_DEST (exp))
1514 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1515 && REG_P (XEXP (SET_DEST (exp), 0))))
1517 /* A register is set; normally CC is set to show that no
1518 test insn is needed. Catch the exceptions. */
1520 /* If not to cc0, then no "set"s in non-natural mode give
1522 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1523 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1525 /* ... except add:s and sub:s in DImode. */
1526 if (GET_MODE (SET_DEST (exp)) == DImode
1527 && (GET_CODE (SET_SRC (exp)) == PLUS
1528 || GET_CODE (SET_SRC (exp)) == MINUS))
1531 cc_status.value1 = SET_DEST (exp);
1532 cc_status.value2 = SET_SRC (exp);
1534 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1536 cc_status.value2 = 0;
1538 /* Add and sub may set V, which gets us
1539 unoptimizable results in "gt" and "le" condition
1541 cc_status.flags |= CC_NO_OVERFLOW;
1546 else if (SET_SRC (exp) == const0_rtx
1547 || (REG_P (SET_SRC (exp))
1548 && (REGNO (SET_SRC (exp))
1549 > CRIS_LAST_GENERAL_REGISTER))
1551 && GET_CODE (SET_SRC (exp)) == CONST_INT
1552 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (SET_SRC (exp)),
1555 /* There's no CC0 change for this case. Just check
1557 if (cc_status.value1
1558 && modified_in_p (cc_status.value1, insn))
1559 cc_status.value1 = 0;
1561 if (cc_status.value2
1562 && modified_in_p (cc_status.value2, insn))
1563 cc_status.value2 = 0;
1570 cc_status.value1 = SET_DEST (exp);
1571 cc_status.value2 = SET_SRC (exp);
1573 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1575 cc_status.value2 = 0;
1577 /* Some operations may set V, which gets us
1578 unoptimizable results in "gt" and "le" condition
1580 if (GET_CODE (SET_SRC (exp)) == PLUS
1581 || GET_CODE (SET_SRC (exp)) == MINUS
1582 || GET_CODE (SET_SRC (exp)) == NEG)
1583 cc_status.flags |= CC_NO_OVERFLOW;
1585 /* For V32, nothing with a register destination sets
1586 C and V usefully. */
1588 cc_status.flags |= CC_NO_OVERFLOW;
1593 else if (MEM_P (SET_DEST (exp))
1594 || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1595 && MEM_P (XEXP (SET_DEST (exp), 0))))
1597 /* When SET to MEM, then CC is not changed (except for
1599 if (cc_status.value1
1600 && modified_in_p (cc_status.value1, insn))
1601 cc_status.value1 = 0;
1603 if (cc_status.value2
1604 && modified_in_p (cc_status.value2, insn))
1605 cc_status.value2 = 0;
1610 else if (GET_CODE (exp) == PARALLEL)
1612 if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1613 && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1614 && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1616 if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1617 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1)))
1621 /* For "move.S [rx=ry+o],rz", say CC reflects
1622 value1=rz and value2=[rx] */
1623 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1625 = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1626 XEXP (XVECEXP (exp, 0, 1), 0));
1628 /* Huh? A side-effect cannot change the destination
1630 if (cris_reg_overlap_mentioned_p (cc_status.value1,
1632 internal_error ("internal error: sideeffect-insn affecting main effect");
1634 /* For V32, moves to registers don't set C and V. */
1636 cc_status.flags |= CC_NO_OVERFLOW;
1639 else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1640 || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1641 && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0)))
1643 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1644 say flags are not changed, except for overlap. */
1645 if (cc_status.value1
1646 && modified_in_p (cc_status.value1, insn))
1647 cc_status.value1 = 0;
1649 if (cc_status.value2
1650 && modified_in_p (cc_status.value2, insn))
1651 cc_status.value2 = 0;
1658 /* If we got here, the case wasn't covered by the code above. */
1662 /* This function looks into the pattern to see how this insn affects
1665 Used when to eliminate test insns before a condition-code user,
1666 such as a "scc" insn or a conditional branch. This includes
1667 checking if the entities that cc was updated by, are changed by the
1670 Currently a jumble of the old peek-inside-the-insn and the newer
1671 check-cc-attribute methods. */
1674 cris_notice_update_cc (rtx exp, rtx insn)
1676 enum attr_cc attrval = get_attr_cc (insn);
1678 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1679 to still set CC_REVERSED as below, since that's required by some
1680 compare insn alternatives. (FIXME: GCC should do this virtual
1681 operand swap by itself.) A test-case that may otherwise fail is
1682 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1687 if (attrval == CC_REV)
1688 cc_status.flags = CC_REVERSED;
1692 /* Slowly, we're converting to using attributes to control the setting
1693 of condition-code status. */
1697 /* Even if it is "none", a setting may clobber a previous
1698 cc-value, so check. */
1699 if (GET_CODE (exp) == SET)
1701 if (cc_status.value1
1702 && modified_in_p (cc_status.value1, insn))
1703 cc_status.value1 = 0;
1705 if (cc_status.value2
1706 && modified_in_p (cc_status.value2, insn))
1707 cc_status.value2 = 0;
1718 cris_normal_notice_update_cc (exp, insn);
1720 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1721 can change bge => bpl and blt => bmi by passing on to the cc0
1722 user that V should not be considered; bgt and ble are taken
1723 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1724 if (attrval == CC_NOOV32 && TARGET_V32)
1725 cc_status.flags |= CC_NO_OVERFLOW;
1729 internal_error ("unknown cc_attr value");
1735 /* Return != 0 if the return sequence for the current function is short,
1736 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1737 registers must be saved, so return 0 then. */
1740 cris_simple_epilogue (void)
1743 unsigned int reglimit = STACK_POINTER_REGNUM;
1744 bool got_really_used = false;
1746 if (! reload_completed
1747 || frame_pointer_needed
1748 || get_frame_size () != 0
1749 || crtl->args.pretend_args_size
1751 || crtl->outgoing_args_size
1752 || crtl->calls_eh_return
1754 /* If we're not supposed to emit prologue and epilogue, we must
1755 not emit return-type instructions. */
1756 || !TARGET_PROLOGUE_EPILOGUE)
1759 /* Can't return from stacked return address with v32. */
1760 if (TARGET_V32 && cris_return_address_on_stack ())
1763 if (crtl->uses_pic_offset_table)
1765 push_topmost_sequence ();
1767 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1768 pop_topmost_sequence ();
1771 /* No simple epilogue if there are saved registers. */
1772 for (regno = 0; regno < reglimit; regno++)
1773 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1779 /* Expand a return insn (just one insn) marked as using SRP or stack
1780 slot depending on parameter ON_STACK. */
1783 cris_expand_return (bool on_stack)
1785 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1786 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1787 GCC expect just (return) to do the right thing when optimizing, so
1788 we do that until they're fixed. Currently, all return insns in a
1789 function must be the same (not really a limiting factor) so we need
1790 to check that it doesn't change half-way through. */
1791 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1793 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1794 CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1796 cfun->machine->return_type
1797 = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1800 /* Compute a (partial) cost for rtx X. Return true if the complete
1801 cost has been computed, and false if subexpressions should be
1802 scanned. In either case, *TOTAL contains the cost result. */
1805 cris_rtx_costs (rtx x, int code, int outer_code, int *total,
1812 HOST_WIDE_INT val = INTVAL (x);
1815 else if (val < 32 && val >= -32)
1817 /* Eight or 16 bits are a word and cycle more expensive. */
1818 else if (val <= 32767 && val >= -32768)
1820 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1821 another word. FIXME: This isn't linear to 16 bits. */
1837 if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1840 /* Make 0.0 cheap, else test-insns will not be used. */
1845 /* If we have one arm of an ADDI, make sure it gets the cost of
1846 one insn, i.e. zero cost for this operand, and just the cost
1847 of the PLUS, as the insn is created by combine from a PLUS
1848 and an ASHIFT, and the MULT cost below would make the
1849 combined value be larger than the separate insns. The insn
1850 validity is checked elsewhere by combine.
1852 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1853 function should be rewritten. */
1854 if (outer_code == PLUS && BIAP_INDEX_P (x))
1860 /* Identify values that are no powers of two. Powers of 2 are
1861 taken care of already and those values should not be changed. */
1862 if (!CONST_INT_P (XEXP (x, 1))
1863 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1865 /* If we have a multiply insn, then the cost is between
1866 1 and 2 "fast" instructions. */
1867 if (TARGET_HAS_MUL_INSNS)
1869 *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1873 /* Estimate as 4 + 4 * #ofbits. */
1874 *total = COSTS_N_INSNS (132);
1883 if (!CONST_INT_P (XEXP (x, 1))
1884 || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1886 /* Estimate this as 4 + 8 * #of bits. */
1887 *total = COSTS_N_INSNS (260);
1893 if (CONST_INT_P (XEXP (x, 1))
1894 /* Two constants may actually happen before optimization. */
1895 && !CONST_INT_P (XEXP (x, 0))
1896 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1899 = (rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, speed) + 2
1900 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1906 if (outer_code != COMPARE)
1910 case ZERO_EXTEND: case SIGN_EXTEND:
1911 *total = rtx_cost (XEXP (x, 0), (enum rtx_code) outer_code, speed);
1919 /* The ADDRESS_COST worker. */
1922 cris_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
1924 /* The metric to use for the cost-macros is unclear.
1925 The metric used here is (the number of cycles needed) / 2,
1926 where we consider equal a cycle for a word of code and a cycle to
1927 read memory. FIXME: Adding "+ 1" to all values would avoid
1928 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
1929 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
1930 Unfortunately(?) such a hack would expose other pessimizations,
1931 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
1932 loop there, without apparent reason. */
1934 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1935 if (BASE_OR_AUTOINCR_P (x))
1938 /* An indirect mem must be a DIP. This means two bytes extra for code,
1939 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1943 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1944 an extra DIP prefix and 4 bytes of constant in most cases. */
1948 /* Handle BIAP and BDAP prefixes. */
1949 if (GET_CODE (x) == PLUS)
1951 rtx tem1 = XEXP (x, 0);
1952 rtx tem2 = XEXP (x, 1);
1954 /* Local extended canonicalization rule: the first operand must
1955 be REG, unless it's an operation (MULT). */
1956 if (!REG_P (tem1) && GET_CODE (tem1) != MULT)
1957 tem1 = tem2, tem2 = XEXP (x, 0);
1959 /* We'll "assume" we have canonical RTX now. */
1960 gcc_assert (REG_P (tem1) || GET_CODE (tem1) == MULT);
1962 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1963 recognize the typical MULT which is always in tem1 because of
1964 insn canonicalization. */
1965 if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1969 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1970 PLUS is always found in tem2. */
1971 if (CONST_INT_P (tem2) && INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1974 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1976 if (CONST_INT_P (tem2)
1977 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1980 /* A BDAP with some other constant is 2 bytes extra. */
1981 if (CONSTANT_P (tem2))
1982 return (2 + 2 + 2) / 2;
1984 /* BDAP with something indirect should have a higher cost than
1985 BIAP with register. FIXME: Should it cost like a MEM or more? */
1986 return (2 + 2 + 2) / 2;
1989 /* What else? Return a high cost. It matters only for valid
1990 addressing modes. */
1994 /* Check various objections to the side-effect. Used in the test-part
1995 of an anonymous insn describing an insn with a possible side-effect.
1996 Returns nonzero if the implied side-effect is ok.
1999 ops : An array of rtx:es. lreg, rreg, rval,
2000 The variables multop and other_op are indexes into this,
2001 or -1 if they are not applicable.
2002 lreg : The register that gets assigned in the side-effect.
2003 rreg : One register in the side-effect expression
2004 rval : The other register, or an int.
2005 multop : An integer to multiply rval with.
2006 other_op : One of the entities of the main effect,
2007 whose mode we must consider. */
2010 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
2011 int lreg, int rreg, int rval,
2012 int multop, int other_op)
2014 /* Find what value to multiply with, for rx =ry + rz * n. */
2015 int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
2017 rtx reg_rtx = ops[rreg];
2018 rtx val_rtx = ops[rval];
2020 /* The operands may be swapped. Canonicalize them in reg_rtx and
2021 val_rtx, where reg_rtx always is a reg (for this constraint to
2023 if (! BASE_P (reg_rtx))
2024 reg_rtx = val_rtx, val_rtx = ops[rreg];
2026 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2027 we have no business. */
2028 if (! BASE_P (reg_rtx))
2031 /* Don't do this when -mno-split. */
2032 if (!TARGET_SIDE_EFFECT_PREFIXES)
2035 /* The mult expression may be hidden in lreg. FIXME: Add more
2036 commentary about that. */
2037 if (GET_CODE (val_rtx) == MULT)
2039 mult = INTVAL (XEXP (val_rtx, 1));
2040 val_rtx = XEXP (val_rtx, 0);
2044 /* First check the "other operand". */
2047 if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
2050 /* Check if the lvalue register is the same as the "other
2051 operand". If so, the result is undefined and we shouldn't do
2052 this. FIXME: Check again. */
2053 if ((BASE_P (ops[lreg])
2054 && BASE_P (ops[other_op])
2055 && REGNO (ops[lreg]) == REGNO (ops[other_op]))
2056 || rtx_equal_p (ops[other_op], ops[lreg]))
2060 /* Do not accept frame_pointer_rtx as any operand. */
2061 if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
2062 || ops[rval] == frame_pointer_rtx
2063 || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
2067 && ! BASE_P (val_rtx))
2070 /* Do not allow rx = rx + n if a normal add or sub with same size
2072 if (rtx_equal_p (ops[lreg], reg_rtx)
2073 && CONST_INT_P (val_rtx)
2074 && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
2077 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2078 if (CONSTANT_P (val_rtx))
2081 if (MEM_P (val_rtx) && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
2084 if (GET_CODE (val_rtx) == SIGN_EXTEND
2085 && MEM_P (XEXP (val_rtx, 0))
2086 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
2089 /* If we got here, it's not a valid addressing mode. */
2092 else if (code == MULT
2093 || (code == PLUS && BASE_P (val_rtx)))
2095 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2096 if (rtx_equal_p (ops[lreg], reg_rtx)
2097 || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
2100 /* Do not allow bad multiply-values. */
2101 if (mult != 1 && mult != 2 && mult != 4)
2104 /* Only allow r + ... */
2105 if (! BASE_P (reg_rtx))
2108 /* If we got here, all seems ok.
2109 (All checks need to be done above). */
2113 /* If we get here, the caller got its initial tests wrong. */
2114 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2117 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2118 insn for other reasons. */
2121 cris_cc0_user_requires_cmp (rtx insn)
2123 rtx cc0_user = NULL;
2127 gcc_assert (insn != NULL);
2132 cc0_user = next_cc0_user (insn);
2133 if (cc0_user == NULL)
2136 body = PATTERN (cc0_user);
2137 set = single_set (cc0_user);
2139 /* Users can be sCC and bCC. */
2140 if (JUMP_P (cc0_user)
2141 && GET_CODE (body) == SET
2142 && SET_DEST (body) == pc_rtx
2143 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
2144 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
2147 GET_CODE (XEXP (SET_SRC (body), 0)) == GT
2148 || GET_CODE (XEXP (SET_SRC (body), 0)) == LE;
2153 GET_CODE (SET_SRC (body)) == GT
2154 || GET_CODE (SET_SRC (body)) == LE;
2160 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2161 does not handle the case where the IN operand is strict_low_part; it
2162 does handle it for X. Test-case in Axis-20010516. This function takes
2163 care of that for THIS port. FIXME: strict_low_part is going away
2167 cris_reg_overlap_mentioned_p (rtx x, rtx in)
2169 /* The function reg_overlap_mentioned now handles when X is
2170 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2171 if (GET_CODE (in) == STRICT_LOW_PART)
2174 return reg_overlap_mentioned_p (x, in);
2177 /* The TARGET_ASM_NAMED_SECTION worker.
2178 We just dispatch to the functions for ELF and a.out. */
2181 cris_target_asm_named_section (const char *name, unsigned int flags,
2185 default_no_named_section (name, flags, decl);
2187 default_elf_asm_named_section (name, flags, decl);
2190 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2191 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2195 cris_valid_pic_const (rtx x, bool any_operand)
2197 gcc_assert (flag_pic);
2199 switch (GET_CODE (x))
2208 if (GET_CODE (x) != CONST)
2213 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2214 if (GET_CODE (x) == PLUS
2215 && GET_CODE (XEXP (x, 0)) == UNSPEC
2216 && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
2217 || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL)
2218 && CONST_INT_P (XEXP (x, 1)))
2221 if (GET_CODE (x) == UNSPEC)
2222 switch (XINT (x, 1))
2224 /* A PCREL operand is only valid for call and movsi. */
2225 case CRIS_UNSPEC_PLT_PCREL:
2226 case CRIS_UNSPEC_PCREL:
2227 return !any_operand;
2229 case CRIS_UNSPEC_PLT_GOTREL:
2230 case CRIS_UNSPEC_PLTGOTREAD:
2231 case CRIS_UNSPEC_GOTREAD:
2232 case CRIS_UNSPEC_GOTREL:
2238 return cris_pic_symbol_type_of (x) == cris_no_symbol;
2241 /* Helper function to find the right PIC-type symbol to generate,
2242 given the original (non-PIC) representation. */
2244 enum cris_pic_symbol_type
2245 cris_pic_symbol_type_of (rtx x)
2247 switch (GET_CODE (x))
2250 return SYMBOL_REF_LOCAL_P (x)
2251 ? cris_rel_symbol : cris_got_symbol;
2254 return cris_rel_symbol;
2257 return cris_pic_symbol_type_of (XEXP (x, 0));
2262 enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
2263 enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
2265 gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2267 if (t1 == cris_got_symbol || t1 == cris_got_symbol)
2268 return cris_got_symbol_needing_fixup;
2270 return t1 != cris_no_symbol ? t1 : t2;
2275 return cris_no_symbol;
2278 /* Likely an offsettability-test attempting to add a constant to
2279 a GOTREAD symbol, which can't be handled. */
2280 return cris_invalid_pic_symbol;
2283 fatal_insn ("unrecognized supposed constant", x);
2289 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2292 cris_legitimate_pic_operand (rtx x)
2294 /* Symbols are not valid PIC operands as-is; just constants. */
2295 return cris_valid_pic_const (x, true);
2298 /* The ASM_OUTPUT_CASE_END worker. */
2301 cris_asm_output_case_end (FILE *stream, int num, rtx table)
2305 rtx whole_jump_insn = PATTERN (PREV_INSN (PREV_INSN (table)));
2307 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2310 = (GET_CODE (whole_jump_insn) == SEQUENCE
2311 ? PATTERN (XVECEXP (whole_jump_insn, 0, 0)) : whole_jump_insn);
2313 asm_fprintf (stream,
2314 "\t.word %LL%d-.%s\n",
2315 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2316 (parallel_jump, 0, 0),
2318 (TARGET_PDEBUG ? "; default" : ""));
2322 asm_fprintf (stream,
2323 "\t.word %LL%d-%LL%d%s\n",
2324 CODE_LABEL_NUMBER (XEXP
2330 (PREV_INSN (table))), 0, 0), 1),
2333 (TARGET_PDEBUG ? "; default" : ""));
2336 /* TARGET_HANDLE_OPTION worker. We just store the values into local
2337 variables here. Checks for correct semantics are in
2338 cris_option_override. */
2341 cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
2342 int value ATTRIBUTE_UNUSED)
2350 + MASK_ALIGN_BY_32);
2353 case OPT_mno_etrax100:
2357 + MASK_ALIGN_BY_32);
2363 |= (MASK_STACK_ALIGN
2366 + MASK_ALIGN_BY_32);
2372 |= (MASK_STACK_ALIGN
2380 &= ~(MASK_STACK_ALIGN
2389 CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2394 /* The TARGET_OPTION_OVERRIDE worker.
2395 As is the norm, this also parses -mfoo=bar type parameters. */
2398 cris_option_override (void)
2400 if (cris_max_stackframe_str)
2402 cris_max_stackframe = atoi (cris_max_stackframe_str);
2404 /* Do some sanity checking. */
2405 if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2406 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2407 cris_max_stackframe, 0x20000000);
2410 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2411 if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2412 cris_cpu_version = CRIS_CPU_SVINTO;
2413 else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2414 cris_cpu_version = CRIS_CPU_ETRAX4;
2416 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2420 = (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2422 if (strcmp ("etrax4", cris_cpu_str) == 0)
2423 cris_cpu_version = 3;
2425 if (strcmp ("svinto", cris_cpu_str) == 0
2426 || strcmp ("etrax100", cris_cpu_str) == 0)
2427 cris_cpu_version = 8;
2429 if (strcmp ("ng", cris_cpu_str) == 0
2430 || strcmp ("etrax100lx", cris_cpu_str) == 0)
2431 cris_cpu_version = 10;
2433 if (cris_cpu_version < 0 || cris_cpu_version > 32)
2434 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2437 /* Set the target flags. */
2438 if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2439 target_flags |= MASK_ETRAX4_ADD;
2441 /* If this is Svinto or higher, align for 32 bit accesses. */
2442 if (cris_cpu_version >= CRIS_CPU_SVINTO)
2444 |= (MASK_SVINTO | MASK_ALIGN_BY_32
2445 | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2448 /* Note that we do not add new flags when it can be completely
2449 described with a macro that uses -mcpu=X. So
2450 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2456 = (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2458 if (strcmp ("etrax4", cris_tune_str) == 0)
2461 if (strcmp ("svinto", cris_tune_str) == 0
2462 || strcmp ("etrax100", cris_tune_str) == 0)
2465 if (strcmp ("ng", cris_tune_str) == 0
2466 || strcmp ("etrax100lx", cris_tune_str) == 0)
2469 if (cris_tune < 0 || cris_tune > 32)
2470 error ("unknown CRIS cpu version specification in -mtune= : %s",
2473 if (cris_tune >= CRIS_CPU_SVINTO)
2474 /* We have currently nothing more to tune than alignment for
2477 |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2478 | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2481 if (cris_cpu_version >= CRIS_CPU_V32)
2482 target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG);
2486 /* Use error rather than warning, so invalid use is easily
2487 detectable. Still change to the values we expect, to avoid
2491 error ("-fPIC and -fpic are not supported in this configuration");
2495 /* Turn off function CSE. We need to have the addresses reach the
2496 call expanders to get PLT-marked, as they could otherwise be
2497 compared against zero directly or indirectly. After visiting the
2498 call expanders they will then be cse:ed, as the call expanders
2499 force_reg the addresses, effectively forcing flag_no_function_cse
2501 flag_no_function_cse = 1;
2504 if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2506 warning (0, "that particular -g option is invalid with -maout and -melinux");
2507 write_symbols = DBX_DEBUG;
2510 /* Set the per-function-data initializer. */
2511 init_machine_status = cris_init_machine_status;
2514 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2517 cris_asm_output_mi_thunk (FILE *stream,
2518 tree thunkdecl ATTRIBUTE_UNUSED,
2519 HOST_WIDE_INT delta,
2520 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2524 fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2525 ADDITIVE_SIZE_MODIFIER (delta), delta,
2526 reg_names[CRIS_FIRST_ARG_REG]);
2528 fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2529 ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2530 reg_names[CRIS_FIRST_ARG_REG]);
2534 const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2536 name = (* targetm.strip_name_encoding) (name);
2540 fprintf (stream, "\tba ");
2541 assemble_name (stream, name);
2542 fprintf (stream, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX);
2546 fprintf (stream, "add.d ");
2547 assemble_name (stream, name);
2548 fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2553 fprintf (stream, "jump ");
2554 assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2555 fprintf (stream, "\n");
2558 fprintf (stream, "\tnop\n");
2562 /* Boilerplate emitted at start of file.
2564 NO_APP *only at file start* means faster assembly. It also means
2565 comments are not allowed. In some cases comments will be output
2566 for debugging purposes. Make sure they are allowed then.
2568 We want a .file directive only if TARGET_ELF. */
2570 cris_file_start (void)
2572 /* These expressions can vary at run time, so we cannot put
2573 them into TARGET_INITIALIZER. */
2574 targetm.asm_file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2575 targetm.asm_file_start_file_directive = TARGET_ELF;
2577 default_file_start ();
2580 /* Rename the function calls for integer multiply and divide. */
2582 cris_init_libfuncs (void)
2584 set_optab_libfunc (smul_optab, SImode, "__Mul");
2585 set_optab_libfunc (sdiv_optab, SImode, "__Div");
2586 set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2587 set_optab_libfunc (smod_optab, SImode, "__Mod");
2588 set_optab_libfunc (umod_optab, SImode, "__Umod");
2591 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2595 cris_init_expanders (void)
2597 /* Nothing here at the moment. */
2600 /* Zero initialization is OK for all current fields. */
2602 static struct machine_function *
2603 cris_init_machine_status (void)
2605 return ggc_alloc_cleared_machine_function ();
2608 /* Split a 2 word move (DI or presumably DF) into component parts.
2609 Originally a copy of gen_split_move_double in m32r.c. */
2612 cris_split_movdx (rtx *operands)
2614 enum machine_mode mode = GET_MODE (operands[0]);
2615 rtx dest = operands[0];
2616 rtx src = operands[1];
2619 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2620 longer happen; after reload there are no SUBREGs any more, and we're
2621 only called after reload. */
2622 CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2627 int dregno = REGNO (dest);
2629 /* Reg-to-reg copy. */
2632 int sregno = REGNO (src);
2634 int reverse = (dregno == sregno + 1);
2636 /* We normally copy the low-numbered register first. However, if
2637 the first register operand 0 is the same as the second register of
2638 operand 1, we must copy in the opposite order. */
2639 emit_insn (gen_rtx_SET (VOIDmode,
2640 operand_subword (dest, reverse, TRUE, mode),
2641 operand_subword (src, reverse, TRUE, mode)));
2643 emit_insn (gen_rtx_SET (VOIDmode,
2644 operand_subword (dest, !reverse, TRUE, mode),
2645 operand_subword (src, !reverse, TRUE, mode)));
2647 /* Constant-to-reg copy. */
2648 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
2651 split_double (src, &words[0], &words[1]);
2652 emit_insn (gen_rtx_SET (VOIDmode,
2653 operand_subword (dest, 0, TRUE, mode),
2656 emit_insn (gen_rtx_SET (VOIDmode,
2657 operand_subword (dest, 1, TRUE, mode),
2660 /* Mem-to-reg copy. */
2661 else if (MEM_P (src))
2663 /* If the high-address word is used in the address, we must load it
2664 last. Otherwise, load it first. */
2665 rtx addr = XEXP (src, 0);
2667 = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2669 /* The original code implies that we can't do
2670 move.x [rN+],rM move.x [rN],rM+1
2671 when rN is dead, because of REG_NOTES damage. That is
2672 consistent with what I've seen, so don't try it.
2674 We have two different cases here; if the addr is POST_INC,
2675 just pass it through, otherwise add constants. */
2677 if (GET_CODE (addr) == POST_INC)
2682 /* Whenever we emit insns with post-incremented
2683 addresses ourselves, we must add a post-inc note
2685 mem = change_address (src, SImode, addr);
2687 = gen_rtx_SET (VOIDmode,
2688 operand_subword (dest, 0, TRUE, mode), mem);
2689 insn = emit_insn (insn);
2690 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2692 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2695 mem = copy_rtx (mem);
2697 = gen_rtx_SET (VOIDmode,
2698 operand_subword (dest, 1, TRUE, mode), mem);
2699 insn = emit_insn (insn);
2700 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2702 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2707 /* Make sure we don't get any other addresses with
2708 embedded postincrements. They should be stopped in
2709 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2711 if (side_effects_p (addr))
2712 fatal_insn ("unexpected side-effects in address", addr);
2714 emit_insn (gen_rtx_SET
2716 operand_subword (dest, reverse, TRUE, mode),
2719 plus_constant (addr,
2720 reverse * UNITS_PER_WORD))));
2721 emit_insn (gen_rtx_SET
2723 operand_subword (dest, ! reverse, TRUE, mode),
2726 plus_constant (addr,
2732 internal_error ("unknown src");
2734 /* Reg-to-mem copy or clear mem. */
2735 else if (MEM_P (dest)
2737 || src == const0_rtx
2738 || src == CONST0_RTX (DFmode)))
2740 rtx addr = XEXP (dest, 0);
2742 if (GET_CODE (addr) == POST_INC)
2747 /* Whenever we emit insns with post-incremented addresses
2748 ourselves, we must add a post-inc note manually. */
2749 mem = change_address (dest, SImode, addr);
2751 = gen_rtx_SET (VOIDmode,
2752 mem, operand_subword (src, 0, TRUE, mode));
2753 insn = emit_insn (insn);
2754 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2756 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2759 mem = copy_rtx (mem);
2761 = gen_rtx_SET (VOIDmode,
2763 operand_subword (src, 1, TRUE, mode));
2764 insn = emit_insn (insn);
2765 if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2767 = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2772 /* Make sure we don't get any other addresses with embedded
2773 postincrements. They should be stopped in
2774 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2775 if (side_effects_p (addr))
2776 fatal_insn ("unexpected side-effects in address", addr);
2778 emit_insn (gen_rtx_SET
2780 change_address (dest, SImode, addr),
2781 operand_subword (src, 0, TRUE, mode)));
2783 emit_insn (gen_rtx_SET
2785 change_address (dest, SImode,
2786 plus_constant (addr,
2788 operand_subword (src, 1, TRUE, mode)));
2793 internal_error ("unknown dest");
2800 /* The expander for the prologue pattern name. */
2803 cris_expand_prologue (void)
2806 int size = get_frame_size ();
2807 /* Shorten the used name for readability. */
2808 int cfoa_size = crtl->outgoing_args_size;
2809 int last_movem_reg = -1;
2812 int return_address_on_stack = cris_return_address_on_stack ();
2813 int got_really_used = false;
2814 int n_movem_regs = 0;
2815 int pretend = crtl->args.pretend_args_size;
2817 /* Don't do anything if no prologues or epilogues are wanted. */
2818 if (!TARGET_PROLOGUE_EPILOGUE)
2821 CRIS_ASSERT (size >= 0);
2823 if (crtl->uses_pic_offset_table)
2825 /* A reference may have been optimized out (like the abort () in
2826 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2828 push_topmost_sequence ();
2830 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2831 pop_topmost_sequence ();
2834 /* Align the size to what's best for the CPU model. */
2835 if (TARGET_STACK_ALIGN)
2836 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2840 /* See also cris_setup_incoming_varargs where
2841 cfun->machine->stdarg_regs is set. There are other setters of
2842 crtl->args.pretend_args_size than stdarg handling, like
2843 for an argument passed with parts in R13 and stack. We must
2844 not store R13 into the pretend-area for that case, as GCC does
2845 that itself. "Our" store would be marked as redundant and GCC
2846 will attempt to remove it, which will then be flagged as an
2847 internal error; trying to remove a frame-related insn. */
2848 int stdarg_regs = cfun->machine->stdarg_regs;
2850 framesize += pretend;
2852 for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2854 regno--, pretend -= 4, stdarg_regs--)
2856 insn = emit_insn (gen_rtx_SET (VOIDmode,
2858 plus_constant (stack_pointer_rtx,
2860 /* FIXME: When dwarf2 frame output and unless asynchronous
2861 exceptions, make dwarf2 bundle together all stack
2862 adjustments like it does for registers between stack
2864 RTX_FRAME_RELATED_P (insn) = 1;
2866 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2867 set_mem_alias_set (mem, get_varargs_alias_set ());
2868 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2870 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2871 the value isn't restored, so we don't want to tell dwarf2
2872 that it's been stored to stack, else EH handling info would
2876 /* For other setters of crtl->args.pretend_args_size, we
2877 just adjust the stack by leaving the remaining size in
2878 "pretend", handled below. */
2881 /* Save SRP if not a leaf function. */
2882 if (return_address_on_stack)
2884 insn = emit_insn (gen_rtx_SET (VOIDmode,
2886 plus_constant (stack_pointer_rtx,
2889 RTX_FRAME_RELATED_P (insn) = 1;
2891 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2892 set_mem_alias_set (mem, get_frame_alias_set ());
2893 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2894 RTX_FRAME_RELATED_P (insn) = 1;
2898 /* Set up the frame pointer, if needed. */
2899 if (frame_pointer_needed)
2901 insn = emit_insn (gen_rtx_SET (VOIDmode,
2903 plus_constant (stack_pointer_rtx,
2906 RTX_FRAME_RELATED_P (insn) = 1;
2908 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2909 set_mem_alias_set (mem, get_frame_alias_set ());
2910 insn = emit_move_insn (mem, frame_pointer_rtx);
2911 RTX_FRAME_RELATED_P (insn) = 1;
2913 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2914 RTX_FRAME_RELATED_P (insn) = 1;
2919 /* Between frame-pointer and saved registers lie the area for local
2920 variables. If we get here with "pretended" size remaining, count
2921 it into the general stack size. */
2924 /* Get a contiguous sequence of registers, starting with R0, that need
2926 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2928 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2932 /* Check if movem may be used for registers so far. */
2933 if (regno == last_movem_reg + 1)
2934 /* Yes, update next expected register. */
2935 last_movem_reg = regno;
2938 /* We cannot use movem for all registers. We have to flush
2939 any movem:ed registers we got so far. */
2940 if (last_movem_reg != -1)
2943 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2945 /* It is a win to use a side-effect assignment for
2946 64 <= size <= 128. But side-effect on movem was
2947 not usable for CRIS v0..3. Also only do it if
2948 side-effects insns are allowed. */
2949 if ((last_movem_reg + 1) * 4 + size >= 64
2950 && (last_movem_reg + 1) * 4 + size <= 128
2951 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2952 && TARGET_SIDE_EFFECT_PREFIXES)
2955 = gen_rtx_MEM (SImode,
2956 plus_constant (stack_pointer_rtx,
2957 -(n_saved * 4 + size)));
2958 set_mem_alias_set (mem, get_frame_alias_set ());
2960 = cris_emit_movem_store (mem, GEN_INT (n_saved),
2961 -(n_saved * 4 + size),
2967 = gen_rtx_SET (VOIDmode,
2969 plus_constant (stack_pointer_rtx,
2970 -(n_saved * 4 + size)));
2971 insn = emit_insn (insn);
2972 RTX_FRAME_RELATED_P (insn) = 1;
2974 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2975 set_mem_alias_set (mem, get_frame_alias_set ());
2976 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2980 framesize += n_saved * 4 + size;
2981 last_movem_reg = -1;
2985 insn = emit_insn (gen_rtx_SET (VOIDmode,
2987 plus_constant (stack_pointer_rtx,
2989 RTX_FRAME_RELATED_P (insn) = 1;
2991 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2992 set_mem_alias_set (mem, get_frame_alias_set ());
2993 insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2994 RTX_FRAME_RELATED_P (insn) = 1;
2996 framesize += 4 + size;
3002 /* Check after, if we could movem all registers. This is the normal case. */
3003 if (last_movem_reg != -1)
3006 = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
3008 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3009 do it if side-effects insns are allowed. */
3010 if ((last_movem_reg + 1) * 4 + size >= 64
3011 && (last_movem_reg + 1) * 4 + size <= 128
3012 && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
3013 && TARGET_SIDE_EFFECT_PREFIXES)
3016 = gen_rtx_MEM (SImode,
3017 plus_constant (stack_pointer_rtx,
3018 -(n_saved * 4 + size)));
3019 set_mem_alias_set (mem, get_frame_alias_set ());
3020 insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
3021 -(n_saved * 4 + size), true);
3026 = gen_rtx_SET (VOIDmode,
3028 plus_constant (stack_pointer_rtx,
3029 -(n_saved * 4 + size)));
3030 insn = emit_insn (insn);
3031 RTX_FRAME_RELATED_P (insn) = 1;
3033 mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
3034 set_mem_alias_set (mem, get_frame_alias_set ());
3035 insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
3038 framesize += n_saved * 4 + size;
3039 /* We have to put outgoing argument space after regs. */
3042 insn = emit_insn (gen_rtx_SET (VOIDmode,
3044 plus_constant (stack_pointer_rtx,
3046 RTX_FRAME_RELATED_P (insn) = 1;
3047 framesize += cfoa_size;
3050 else if ((size + cfoa_size) > 0)
3052 insn = emit_insn (gen_rtx_SET (VOIDmode,
3054 plus_constant (stack_pointer_rtx,
3055 -(cfoa_size + size))));
3056 RTX_FRAME_RELATED_P (insn) = 1;
3057 framesize += size + cfoa_size;
3060 /* Set up the PIC register, if it is used. */
3061 if (got_really_used)
3064 = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
3065 emit_move_insn (pic_offset_table_rtx, got);
3067 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3068 follow exceptional paths and tries to delete the GOT load as
3069 unused, if it isn't used on the non-exceptional paths. Other
3070 ports have similar or other cover-ups, or plain bugs marking
3071 the GOT register load as maybe-dead. To see this, remove the
3072 line below and try libsupc++/vec.cc or a trivial
3073 "static void y (); void x () {try {y ();} catch (...) {}}". */
3074 emit_use (pic_offset_table_rtx);
3077 if (cris_max_stackframe && framesize > cris_max_stackframe)
3078 warning (0, "stackframe too big: %d bytes", framesize);
3081 /* The expander for the epilogue pattern. */
3084 cris_expand_epilogue (void)
3087 int size = get_frame_size ();
3088 int last_movem_reg = -1;
3089 int argspace_offset = crtl->outgoing_args_size;
3090 int pretend = crtl->args.pretend_args_size;
3092 bool return_address_on_stack = cris_return_address_on_stack ();
3093 /* A reference may have been optimized out
3094 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3095 so check that it's still used. */
3096 int got_really_used = false;
3097 int n_movem_regs = 0;
3099 if (!TARGET_PROLOGUE_EPILOGUE)
3102 if (crtl->uses_pic_offset_table)
3104 /* A reference may have been optimized out (like the abort () in
3105 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3107 push_topmost_sequence ();
3109 = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
3110 pop_topmost_sequence ();
3113 /* Align byte count of stack frame. */
3114 if (TARGET_STACK_ALIGN)
3115 size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
3117 /* Check how many saved regs we can movem. They start at r0 and must
3120 regno < FIRST_PSEUDO_REGISTER;
3122 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3126 if (regno == last_movem_reg + 1)
3127 last_movem_reg = regno;
3132 /* If there was only one register that really needed to be saved
3133 through movem, don't use movem. */
3134 if (n_movem_regs == 1)
3135 last_movem_reg = -1;
3137 /* Now emit "normal" move insns for all regs higher than the movem
3139 for (regno = FIRST_PSEUDO_REGISTER - 1;
3140 regno > last_movem_reg;
3142 if (cris_reg_saved_in_regsave_area (regno, got_really_used))
3146 if (argspace_offset)
3148 /* There is an area for outgoing parameters located before
3149 the saved registers. We have to adjust for that. */
3150 emit_insn (gen_rtx_SET (VOIDmode,
3152 plus_constant (stack_pointer_rtx,
3154 /* Make sure we only do this once. */
3155 argspace_offset = 0;
3158 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3159 stack_pointer_rtx));
3160 set_mem_alias_set (mem, get_frame_alias_set ());
3161 insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
3163 /* Whenever we emit insns with post-incremented addresses
3164 ourselves, we must add a post-inc note manually. */
3166 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3169 /* If we have any movem-restore, do it now. */
3170 if (last_movem_reg != -1)
3174 if (argspace_offset)
3176 emit_insn (gen_rtx_SET (VOIDmode,
3178 plus_constant (stack_pointer_rtx,
3180 argspace_offset = 0;
3183 mem = gen_rtx_MEM (SImode,
3184 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
3185 set_mem_alias_set (mem, get_frame_alias_set ());
3187 = emit_insn (cris_gen_movem_load (mem,
3188 GEN_INT (last_movem_reg + 1), 0));
3189 /* Whenever we emit insns with post-incremented addresses
3190 ourselves, we must add a post-inc note manually. */
3191 if (side_effects_p (PATTERN (insn)))
3193 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3196 /* If we don't clobber all of the allocated stack area (we've already
3197 deallocated saved registers), GCC might want to schedule loads from
3198 the stack to *after* the stack-pointer restore, which introduces an
3199 interrupt race condition. This happened for the initial-value
3200 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3201 other failure for that test). It also happened for the stack slot
3202 for the return value in (one version of)
3203 linux/fs/dcache.c:__d_lookup, at least with "-O2
3204 -fno-omit-frame-pointer". */
3206 /* Restore frame pointer if necessary. */
3207 if (frame_pointer_needed)
3211 emit_insn (gen_cris_frame_deallocated_barrier ());
3213 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
3214 mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
3215 stack_pointer_rtx));
3216 set_mem_alias_set (mem, get_frame_alias_set ());
3217 insn = emit_move_insn (frame_pointer_rtx, mem);
3219 /* Whenever we emit insns with post-incremented addresses
3220 ourselves, we must add a post-inc note manually. */
3222 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3224 else if ((size + argspace_offset) != 0)
3226 emit_insn (gen_cris_frame_deallocated_barrier ());
3228 /* If there was no frame-pointer to restore sp from, we must
3229 explicitly deallocate local variables. */
3231 /* Handle space for outgoing parameters that hasn't been handled
3233 size += argspace_offset;
3235 emit_insn (gen_rtx_SET (VOIDmode,
3237 plus_constant (stack_pointer_rtx, size)));
3240 /* If this function has no pushed register parameters
3241 (stdargs/varargs), and if it is not a leaf function, then we have
3242 the return address on the stack. */
3243 if (return_address_on_stack && pretend == 0)
3245 if (TARGET_V32 || crtl->calls_eh_return)
3249 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3250 mem = gen_rtx_MEM (SImode,
3251 gen_rtx_POST_INC (SImode,
3252 stack_pointer_rtx));
3253 set_mem_alias_set (mem, get_frame_alias_set ());
3254 insn = emit_move_insn (srpreg, mem);
3256 /* Whenever we emit insns with post-incremented addresses
3257 ourselves, we must add a post-inc note manually. */
3259 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3261 if (crtl->calls_eh_return)
3262 emit_insn (gen_addsi3 (stack_pointer_rtx,
3264 gen_rtx_raw_REG (SImode,
3265 CRIS_STACKADJ_REG)));
3266 cris_expand_return (false);
3269 cris_expand_return (true);
3274 /* If we pushed some register parameters, then adjust the stack for
3278 /* If SRP is stored on the way, we need to restore it first. */
3279 if (return_address_on_stack)
3282 rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
3285 mem = gen_rtx_MEM (SImode,
3286 gen_rtx_POST_INC (SImode,
3287 stack_pointer_rtx));
3288 set_mem_alias_set (mem, get_frame_alias_set ());
3289 insn = emit_move_insn (srpreg, mem);
3291 /* Whenever we emit insns with post-incremented addresses
3292 ourselves, we must add a post-inc note manually. */
3294 = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
3297 emit_insn (gen_rtx_SET (VOIDmode,
3299 plus_constant (stack_pointer_rtx, pretend)));
3302 /* Perform the "physical" unwinding that the EH machinery calculated. */
3303 if (crtl->calls_eh_return)
3304 emit_insn (gen_addsi3 (stack_pointer_rtx,
3306 gen_rtx_raw_REG (SImode,
3307 CRIS_STACKADJ_REG)));
3308 cris_expand_return (false);
3311 /* Worker function for generating movem from mem for load_multiple. */
3314 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
3316 int nregs = INTVAL (nregs_rtx);
3320 rtx srcreg = XEXP (src, 0);
3321 unsigned int regno = nregs - 1;
3330 if (GET_CODE (srcreg) == POST_INC)
3331 srcreg = XEXP (srcreg, 0);
3333 CRIS_ASSERT (REG_P (srcreg));
3335 /* Don't use movem for just one insn. The insns are equivalent except
3336 for the pipeline hazard (on v32); movem does not forward the loaded
3337 registers so there's a three cycles penalty for their use. */
3339 return gen_movsi (gen_rtx_REG (SImode, 0), src);
3341 vec = rtvec_alloc (nprefix + nregs
3342 + (GET_CODE (XEXP (src, 0)) == POST_INC));
3344 if (GET_CODE (XEXP (src, 0)) == POST_INC)
3346 RTVEC_ELT (vec, nprefix + 1)
3347 = gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
3351 src = replace_equiv_address (src, srcreg);
3352 RTVEC_ELT (vec, nprefix)
3353 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3356 for (i = 1; i < nregs; i++, eltno++)
3358 RTVEC_ELT (vec, nprefix + eltno)
3359 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3360 adjust_address_nv (src, SImode, i * 4));
3364 return gen_rtx_PARALLEL (VOIDmode, vec);
3367 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3368 are added that the dwarf2 machinery understands. */
3371 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3374 int nregs = INTVAL (nregs_rtx);
3379 rtx destreg = XEXP (dest, 0);
3380 unsigned int regno = nregs - 1;
3389 if (GET_CODE (destreg) == POST_INC)
3390 increment += nregs * 4;
3392 if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3393 destreg = XEXP (destreg, 0);
3395 CRIS_ASSERT (REG_P (destreg));
3397 /* Don't use movem for just one insn. The insns are equivalent except
3398 for the pipeline hazard (on v32); movem does not forward the loaded
3399 registers so there's a three cycles penalty for use. */
3402 rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3406 insn = emit_insn (mov);
3408 RTX_FRAME_RELATED_P (insn) = 1;
3412 /* If there was a request for a side-effect, create the ordinary
3414 vec = rtvec_alloc (2);
3416 RTVEC_ELT (vec, 0) = mov;
3417 RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3418 plus_constant (destreg, increment));
3421 RTX_FRAME_RELATED_P (mov) = 1;
3422 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3427 vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3429 = gen_rtx_SET (VOIDmode,
3430 replace_equiv_address (dest,
3431 plus_constant (destreg,
3433 gen_rtx_REG (SImode, regno));
3436 /* The dwarf2 info wants this mark on each component in a parallel
3437 that's part of the prologue (though it's optional on the first
3440 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3445 = gen_rtx_SET (VOIDmode, destreg,
3446 plus_constant (destreg,
3448 ? increment : nregs * 4));
3452 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3454 /* Don't call adjust_address_nv on a post-incremented address if
3456 if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3457 dest = replace_equiv_address (dest, destreg);
3460 for (i = 1; i < nregs; i++, eltno++)
3462 RTVEC_ELT (vec, eltno)
3463 = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3464 gen_rtx_REG (SImode, regno));
3466 RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3471 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3473 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3474 we need to keep the stack adjustment separate, after the
3475 MEM-setters. Else the stack-adjustment in the second component of
3476 the parallel would be mishandled; the offsets for the SETs that
3477 follow it would be wrong. We prepare for this by adding a
3478 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3479 followed by the increment. Note that we have FRAME_RELATED_P on
3480 all the SETs, including the original stack adjustment SET in the
3486 rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3487 XVECEXP (seq, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn), 0, 0));
3488 for (i = 1; i < nregs; i++)
3490 = copy_rtx (XVECEXP (PATTERN (insn), 0, i + 1));
3491 XVECEXP (seq, 0, nregs) = copy_rtx (XVECEXP (PATTERN (insn), 0, 1));
3492 add_reg_note (insn, REG_FRAME_RELATED_EXPR, seq);
3495 RTX_FRAME_RELATED_P (insn) = 1;
3501 /* Worker function for expanding the address for PIC function calls. */
3504 cris_expand_pic_call_address (rtx *opp)
3508 gcc_assert (MEM_P (op));
3511 /* It might be that code can be generated that jumps to 0 (or to a
3512 specific address). Don't die on that. (There is a
3514 if (CONSTANT_ADDRESS_P (op) && !CONST_INT_P (op))
3516 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3518 CRIS_ASSERT (can_create_pseudo_p ());
3520 /* For local symbols (non-PLT), just get the plain symbol
3521 reference into a register. For symbols that can be PLT, make
3523 if (t == cris_rel_symbol)
3525 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3526 into a register caused performance regression for 3.2.1,
3527 observable in __floatdidf and elsewhere in libgcc. */
3530 rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op);
3531 HOST_WIDE_INT offs = get_integer_term (op);
3533 /* We can't get calls to sym+N, N integer, can we? */
3534 gcc_assert (offs == 0);
3536 op = gen_rtx_CONST (Pmode,
3537 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
3538 CRIS_UNSPEC_PCREL));
3541 op = force_reg (Pmode, op);
3543 else if (t == cris_got_symbol)
3545 if (TARGET_AVOID_GOTPLT)
3547 /* Change a "jsr sym" into (allocate register rM, rO)
3548 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3549 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3550 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3553 gcc_assert (can_create_pseudo_p ());
3554 crtl->uses_pic_offset_table = 1;
3555 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3557 ? CRIS_UNSPEC_PLT_PCREL
3558 : CRIS_UNSPEC_PLT_GOTREL);
3559 tem = gen_rtx_CONST (Pmode, tem);
3564 rm = gen_reg_rtx (Pmode);
3565 emit_move_insn (rm, tem);
3566 ro = gen_reg_rtx (Pmode);
3567 if (expand_binop (Pmode, add_optab, rm,
3568 pic_offset_table_rtx,
3569 ro, 0, OPTAB_LIB_WIDEN) != ro)
3570 internal_error ("expand_binop failed in movsi got");
3576 /* Change a "jsr sym" into (allocate register rM, rO)
3577 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3578 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3579 marked as not trapping and not aliasing. No "move.d
3580 [rO],rP" as that would invite to re-use of a value
3581 that should not be reused. FIXME: Need a peephole2
3582 for cases when this is cse:d from the call, to change
3583 back to just get the PLT entry address, so we don't
3584 resolve the same symbol over and over (the memory
3585 access of the PLTGOT isn't constant). */
3586 rtx tem, mem, rm, ro;
3588 gcc_assert (can_create_pseudo_p ());
3589 crtl->uses_pic_offset_table = 1;
3590 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3591 CRIS_UNSPEC_PLTGOTREAD);
3592 rm = gen_reg_rtx (Pmode);
3593 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3594 ro = gen_reg_rtx (Pmode);
3595 if (expand_binop (Pmode, add_optab, rm,
3596 pic_offset_table_rtx,
3597 ro, 0, OPTAB_LIB_WIDEN) != ro)
3598 internal_error ("expand_binop failed in movsi got");
3599 mem = gen_rtx_MEM (Pmode, ro);
3601 /* This MEM doesn't alias anything. Whether it aliases
3602 other same symbols is unimportant. */
3603 set_mem_alias_set (mem, new_alias_set ());
3604 MEM_NOTRAP_P (mem) = 1;
3609 /* Can't possibly get a GOT-needing-fixup for a function-call,
3611 fatal_insn ("unidentifiable call op", op);
3613 *opp = replace_equiv_address (*opp, op);
3617 /* Make sure operands are in the right order for an addsi3 insn as
3618 generated by a define_split. Nothing but REG_P as the first
3619 operand is recognized by addsi3 after reload. OPERANDS contains
3620 the operands, with the first at OPERANDS[N] and the second at
3624 cris_order_for_addsi3 (rtx *operands, int n)
3626 if (!REG_P (operands[n]))
3628 rtx tem = operands[n];
3629 operands[n] = operands[n + 1];
3630 operands[n + 1] = tem;
3634 /* Use from within code, from e.g. PRINT_OPERAND and
3635 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3636 different things depending on whether code operand or constant is
3640 cris_output_addr_const (FILE *file, rtx x)
3643 output_addr_const (file, x);
3647 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3650 cris_asm_output_symbol_ref (FILE *file, rtx x)
3652 gcc_assert (GET_CODE (x) == SYMBOL_REF);
3654 if (flag_pic && in_code > 0)
3656 const char *origstr = XSTR (x, 0);
3658 str = (* targetm.strip_name_encoding) (origstr);
3659 assemble_name (file, str);
3662 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3663 output_operand_lossage ("PIC register isn't set up");
3666 assemble_name (file, XSTR (x, 0));
3669 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3672 cris_asm_output_label_ref (FILE *file, char *buf)
3674 if (flag_pic && in_code > 0)
3676 assemble_name (file, buf);
3679 if (!TARGET_V32 && !crtl->uses_pic_offset_table)
3680 internal_error ("emitting PIC operand, but PIC register "
3684 assemble_name (file, buf);
3687 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3690 cris_output_addr_const_extra (FILE *file, rtx xconst)
3692 switch (GET_CODE (xconst))
3697 x = XVECEXP (xconst, 0, 0);
3698 CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3699 || GET_CODE (x) == LABEL_REF
3700 || GET_CODE (x) == CONST);
3701 output_addr_const (file, x);
3702 switch (XINT (xconst, 1))
3704 case CRIS_UNSPEC_PCREL:
3705 /* We only get this with -fpic/PIC to tell it apart from an
3706 invalid symbol. We can't tell here, but it should only
3707 be the operand of a call or movsi. */
3708 gcc_assert (TARGET_V32 && flag_pic);
3711 case CRIS_UNSPEC_PLT_PCREL:
3712 gcc_assert (TARGET_V32);
3713 fprintf (file, ":PLT");
3716 case CRIS_UNSPEC_PLT_GOTREL:
3717 gcc_assert (!TARGET_V32);
3718 fprintf (file, ":PLTG");
3721 case CRIS_UNSPEC_GOTREL:
3722 gcc_assert (!TARGET_V32);
3723 fprintf (file, ":GOTOFF");
3726 case CRIS_UNSPEC_GOTREAD:
3728 fprintf (file, ":GOT16");
3730 fprintf (file, ":GOT");
3733 case CRIS_UNSPEC_PLTGOTREAD:
3735 fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3737 fprintf (file, CRIS_GOTPLT_SUFFIX);
3750 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3753 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3754 int incoming ATTRIBUTE_UNUSED)
3756 return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3759 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3762 cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3763 enum machine_mode mode ATTRIBUTE_UNUSED,
3764 tree type ATTRIBUTE_UNUSED,
3765 int *pretend_arg_size,
3768 if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3770 int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3771 cfun->machine->stdarg_regs = stdarg_regs;
3772 *pretend_arg_size = stdarg_regs * 4;
3776 fprintf (asm_out_file,
3777 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3778 ca->regs, *pretend_arg_size, second_time);
3781 /* Return true if TYPE must be passed by invisible reference.
3782 For cris, we pass <= 8 bytes by value, others by reference. */
3785 cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3786 enum machine_mode mode, const_tree type,
3787 bool named ATTRIBUTE_UNUSED)
3789 return (targetm.calls.must_pass_in_stack (mode, type)
3790 || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3793 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3794 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3795 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
3798 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
3799 enum machine_mode mode,
3800 int *punsignedp ATTRIBUTE_UNUSED,
3801 const_tree fntype ATTRIBUTE_UNUSED,
3804 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3805 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3806 Maybe pointless as of now, but let's keep the old behavior. */
3807 if (for_return == 1)
3809 return CRIS_PROMOTED_MODE (mode, *punsignedp, type);
3812 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3816 cris_function_value(const_tree type,
3817 const_tree func ATTRIBUTE_UNUSED,
3818 bool outgoing ATTRIBUTE_UNUSED)
3820 return gen_rtx_REG (TYPE_MODE (type), CRIS_FIRST_ARG_REG);
3823 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3827 cris_libcall_value (enum machine_mode mode,
3828 const_rtx fun ATTRIBUTE_UNUSED)
3830 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG);
3833 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3837 cris_function_value_regno_p (const unsigned int regno)
3839 return (regno == CRIS_FIRST_ARG_REG);
3843 cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3844 tree type, bool named ATTRIBUTE_UNUSED)
3846 if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3847 && !targetm.calls.must_pass_in_stack (mode, type)
3848 && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3849 && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3850 return UNITS_PER_WORD;
3856 cris_function_arg_1 (const CUMULATIVE_ARGS *ca,
3857 enum machine_mode mode ATTRIBUTE_UNUSED,
3858 const_tree type ATTRIBUTE_UNUSED,
3859 bool named, bool incoming)
3861 if ((!incoming || named) && ca->regs < CRIS_MAX_ARGS_IN_REGS)
3862 return gen_rtx_REG (mode, CRIS_FIRST_ARG_REG + ca->regs);
3867 /* Worker function for TARGET_FUNCTION_ARG.
3868 The void_type_node is sent as a "closing" call. */
3871 cris_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3872 const_tree type, bool named)
3874 return cris_function_arg_1 (ca, mode, type, named, false);
3877 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
3879 The differences between this and the previous, is that this one checks
3880 that an argument is named, since incoming stdarg/varargs arguments are
3881 pushed onto the stack, and we don't have to check against the "closing"
3882 void_type_node TYPE parameter. */
3885 cris_function_incoming_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3886 const_tree type, bool named)
3888 return cris_function_arg_1 (ca, mode, type, named, true);
3891 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
3894 cris_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3895 const_tree type, bool named ATTRIBUTE_UNUSED)
3897 ca->regs += (3 + CRIS_FUNCTION_ARG_SIZE (mode, type)) / 4;
3900 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3903 cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3905 HARD_REG_SET mof_set;
3909 CLEAR_HARD_REG_SET (mof_set);
3910 SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3912 /* For the time being, all asms clobber condition codes. Revisit when
3913 there's a reasonable use for inputs/outputs that mention condition
3916 = tree_cons (NULL_TREE,
3917 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3918 reg_names[CRIS_CC0_REGNUM]),
3921 for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3923 tree val = TREE_VALUE (t);
3925 /* The constraint letter for the singleton register class of MOF
3926 is 'h'. If it's mentioned in the constraints, the asm is
3927 MOF-aware and adding it to the clobbers would cause it to have
3928 impossible constraints. */
3929 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3931 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3935 for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3937 tree val = TREE_VALUE (t);
3939 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3941 || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3945 return tree_cons (NULL_TREE,
3946 build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3947 reg_names[CRIS_MOF_REGNUM]),
3951 /* Implement TARGET_FRAME_POINTER_REQUIRED.
3953 Really only needed if the stack frame has variable length (alloca
3954 or variable sized local arguments (GNU C extension). See PR39499 and
3955 PR38609 for the reason this isn't just 0. */
3958 cris_frame_pointer_required (void)
3960 return !current_function_sp_is_unchanging;
3963 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3965 This looks too complicated, and it is. I assigned r7 to be the
3966 static chain register, but it is call-saved, so we have to save it,
3967 and come back to restore it after the call, so we have to save srp...
3968 Anyway, trampolines are rare enough that we can cope with this
3969 somewhat lack of elegance.
3970 (Do not be tempted to "straighten up" whitespace in the asms; the
3971 assembler #NO_APP state mandates strict spacing). */
3972 /* ??? See the i386 regparm=3 implementation that pushes the static
3973 chain value to the stack in the trampoline, and uses a call-saved
3974 register when called directly. */
3977 cris_asm_trampoline_template (FILE *f)
3981 /* This normally-unused nop insn acts as an instruction to
3982 the simulator to flush its instruction cache. None of
3983 the other instructions in the trampoline template suits
3984 as a trigger for V32. The pc-relative addressing mode
3985 works nicely as a trigger for V10.
3986 FIXME: Have specific V32 template (possibly avoiding the
3987 use of a special instruction). */
3988 fprintf (f, "\tclearf x\n");
3989 /* We have to use a register as an intermediate, choosing
3990 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
3991 so we can use it for address indirection and jsr target. */
3992 fprintf (f, "\tmove $r1,$mof\n");
3994 fprintf (f, "\tmove.d 0,$r1\n");
3995 fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]);
3996 fprintf (f, "\taddq 6,$r1\n");
3997 fprintf (f, "\tmove $mof,[$r1]\n");
3998 fprintf (f, "\taddq 6,$r1\n");
3999 fprintf (f, "\tmove $srp,[$r1]\n");
4001 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4003 fprintf (f, "\tmove.d 0,$r1\n");
4004 fprintf (f, "\tjsr $r1\n");
4005 fprintf (f, "\tsetf\n");
4007 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4009 fprintf (f, "\tmove.d 0,$r1\n");
4011 fprintf (f, "\tmove.d 0,$r9\n");
4012 fprintf (f, "\tjump $r9\n");
4013 fprintf (f, "\tsetf\n");
4017 fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]);
4018 fprintf (f, "\tmove $srp,[$pc+22]\n");
4019 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4020 fprintf (f, "\tjsr 0\n");
4021 fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]);
4022 fprintf (f, "\tjump 0\n");
4026 /* Implement TARGET_TRAMPOLINE_INIT. */
4029 cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
4031 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4032 rtx tramp = XEXP (m_tramp, 0);
4035 emit_block_move (m_tramp, assemble_trampoline_template (),
4036 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
4040 mem = adjust_address (m_tramp, SImode, 6);
4041 emit_move_insn (mem, plus_constant (tramp, 38));
4042 mem = adjust_address (m_tramp, SImode, 22);
4043 emit_move_insn (mem, chain_value);
4044 mem = adjust_address (m_tramp, SImode, 28);
4045 emit_move_insn (mem, fnaddr);
4049 mem = adjust_address (m_tramp, SImode, 10);
4050 emit_move_insn (mem, chain_value);
4051 mem = adjust_address (m_tramp, SImode, 16);
4052 emit_move_insn (mem, fnaddr);
4055 /* Note that there is no need to do anything with the cache for
4056 sake of a trampoline. */
4061 /* Various small functions to replace macros. Only called from a
4062 debugger. They might collide with gcc functions or system functions,
4063 so only emit them when '#if 1' above. */
4065 enum rtx_code Get_code (rtx);
4070 return GET_CODE (x);
4073 const char *Get_mode (rtx);
4078 return GET_MODE_NAME (GET_MODE (x));
4081 rtx Xexp (rtx, int);
4089 rtx Xvecexp (rtx, int, int);
4092 Xvecexp (rtx x, int n, int m)
4094 return XVECEXP (x, n, m);
4097 int Get_rtx_len (rtx);
4102 return GET_RTX_LENGTH (GET_CODE (x));
4105 /* Use upper-case to distinguish from local variables that are sometimes
4106 called next_insn and prev_insn. */
4108 rtx Next_insn (rtx);
4111 Next_insn (rtx insn)
4113 return NEXT_INSN (insn);
4116 rtx Prev_insn (rtx);
4119 Prev_insn (rtx insn)
4121 return PREV_INSN (insn);
4125 #include "gt-cris.h"
4129 * eval: (c-set-style "gnu")
4130 * indent-tabs-mode: t