1 ;;- Machine description for GNU compiler, Clipper Version
2 ;; Copyright (C) 1987, 1988, 1991, 1993, 1994, 1997, 1998, 1999, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
24 ;;- Instruction patterns. When multiple patterns apply,
25 ;;- the first one in the file is chosen.
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30 ;;- updates for most instructions.
37 ;; unknown is temporary in order to generate 'cc clobber' until attribute
38 ;; assignment is consistent
40 (define_attr "type" "load,store,arith,fp,branch,unknown"
41 (const_string "unknown"))
43 ;; condition code setting
47 ;; set1 set cc_status.value1, e.g. sub r0,r1
48 ;; set2 set value1 and value2, e.g. mov r0,r1
49 ;; change0 may be side effect, i.e. load mem,r0
51 ;; note: loadi and loadq are 'arith' instructions that set the condition codes
52 ;; mul,div,mod do NOT set the condition codes
54 (define_attr "cc" "clobber,unchanged,set1,set2,change0"
55 (cond [(eq_attr "type" "load") (const_string "change0")
56 (eq_attr "type" "store,branch") (const_string "unchanged")
57 (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "")
59 (const_string "clobber"))
61 (const_string "clobber")))
64 ;; clipper seems to be a traditional risc processor
65 ;; we define a functional unit 'memory'
67 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)
70 ;; We don't want to allow a constant operand for test insns because
71 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
72 ;; be folded while optimizing anyway.
76 (match_operand:SI 0 "int_reg_operand" "r"))]
82 (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n")
83 (match_operand:SI 1 "nonmemory_operand" "r,n,r")))]
89 if (which_alternative == 0)
90 return \"cmpw %1,%0\";
92 if (which_alternative == 1)
94 val = INTVAL (operands[1]);
95 if (0 <= val && val < 16)
96 return \"cmpq %1,%0\";
97 return \"cmpi %1,%0\";
100 cc_status.flags |= CC_REVERSED; /* immediate must be first */
102 val = INTVAL (operands[0]);
104 if (0 <= val && val < 16)
105 return \"cmpq %0,%1\";
107 return \"cmpi %0,%1\";
112 (compare (match_operand:DF 0 "fp_reg_operand" "f")
113 (match_operand:DF 1 "fp_reg_operand" "f")))]
119 (compare (match_operand:SF 0 "fp_reg_operand" "f")
120 (match_operand:SF 1 "fp_reg_operand" "f")))]
126 ;; double and single float move
128 (define_expand "movdf"
129 [(set (match_operand:DF 0 "general_operand" "")
130 (match_operand:DF 1 "general_operand" ""))]
134 if (GET_CODE (operands[0]) == MEM)
136 if (GET_CODE (operands[1]) == CONST_DOUBLE)
137 operands[1] = force_reg (DFmode,
138 force_const_mem (DFmode, operands[1]));
139 else if (GET_CODE (operands[1]) != REG)
140 operands[1] = force_reg (DFmode, operands[1]);
143 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
144 operands[1] = force_const_mem (DFmode, operands[1]);
148 ;; provide two patterns with different predicates as we don't want combine
149 ;; to recombine a mem -> mem move
152 [(set (match_operand:DF 0 "register_operand" "=*rf")
153 (match_operand:DF 1 "nonimmediate_operand" "*rfo"))]
157 #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
159 if (FP_REG_P (operands[0]))
161 if (FP_REG_P (operands[1])) /* f -> f */
162 return \"movd %1,%0\";
164 if (GET_CODE (operands[1]) == REG) /* r -> f */
165 return \"movld %1,%0\";
167 return \"loadd %1,%0\"; /* m -> f */
170 if (FP_REG_P (operands[1]))
172 if (GET_CODE (operands[0]) == REG) /* f -> r */
173 return \"movdl %1,%0\";
178 if (GET_CODE (operands[1]) == MEM) /* m -> r */
181 xops[0] = operands[0];
182 xops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
183 xops[2] = operands[1];
184 xops[3] = adjust_address (operands[1], SImode, 4);
185 output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops);
189 if (GET_CODE (operands[1]) == REG) /* r -> r */
192 xops[0] = operands[0];
193 xops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
194 xops[2] = operands[1];
195 xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
196 output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops);
206 [(set (match_operand:DF 0 "memory_operand" "=o,m")
207 (match_operand:DF 1 "register_operand" "*rf,f"))]
213 if (REGNO (operands[1]) >= 16) /* f -> m */
214 return \"stord %1,%0\";
216 xops[0] = operands[0]; /* r -> o */
217 xops[1] = adjust_address (operands[0], SImode, 4);
218 xops[2] = operands[1];
219 xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
220 output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
223 [(set_attr "type" "store,store")
224 (set_attr "cc" "clobber,unchanged")])
227 (define_expand "movsf"
228 [(set (match_operand:SF 0 "general_operand" "")
229 (match_operand:SF 1 "general_operand" ""))]
233 if (GET_CODE (operands[0]) == MEM)
235 if (GET_CODE (operands[1]) == CONST_DOUBLE)
236 operands[1] = force_reg (SFmode,
237 force_const_mem (SFmode, operands[1]));
238 else if (GET_CODE (operands[1]) != REG)
239 operands[1] = force_reg (SFmode, operands[1]);
242 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
243 operands[1] = force_const_mem (SFmode, operands[1]);
247 ;; provide two patterns with different predicates as we don't want combine
248 ;; to recombine a mem -> mem move
251 [(set (match_operand:SF 0 "register_operand" "=*rf")
252 (match_operand:SF 1 "nonimmediate_operand" "*rfm"))]
256 #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
258 if (FP_REG_P (operands[0]))
260 if (FP_REG_P (operands[1])) /* f -> f */
261 return \"movs %1,%0\";
262 if (GET_CODE (operands[1]) == REG) /* r -> f */
264 \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\";
265 return \"loads %1,%0\"; /* m -> f */
268 if (FP_REG_P (operands[1]))
270 if (GET_CODE (operands[0]) == REG) /* f -> r */
272 \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\";
276 if (GET_CODE (operands[1]) == MEM) /* m -> r */
277 return \"loadw %1,%0\";
279 if (GET_CODE (operands[1]) == REG) /* r -> r */
280 return \"movw %1,%0\";
287 [(set (match_operand:SF 0 "memory_operand" "=m")
288 (match_operand:SF 1 "register_operand" "*rf"))]
292 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16)
293 return \"stors %1,%0\"; /* f-> m */
295 return \"storw %1,%0\"; /* r -> m */
297 [(set_attr "type" "store")])
300 (define_expand "movdi"
301 [(set (match_operand:DI 0 "general_operand" "")
302 (match_operand:DI 1 "general_operand" ""))]
306 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
307 operands[1] = force_reg (DImode, operands[1]);
310 ;; If an operand is a MEM but not offsettable, we can't load it into
311 ;; a register, so we must force the third alternative to be the one
312 ;; reloaded. Hence we show the first as more expensive.
314 [(set (match_operand:DI 0 "register_operand" "=?r,r,r")
315 (match_operand:DI 1 "general_operand" "r,n,o"))]
319 rtx xoperands[2],yoperands[2];
321 xoperands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
323 if (which_alternative == 0) /* r -> r */
325 output_asm_insn (\"movw %1,%0\", operands);
326 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
327 output_asm_insn (\"movw %1,%0\", xoperands);
331 if (which_alternative == 1) /* n -> r */
333 if (GET_CODE (operands[1]) == CONST_INT)
335 output_asm_insn (\"loadi %1,%0\", operands);
336 output_asm_insn (\"loadq $0,%0\", xoperands);
340 if (GET_CODE (operands[1]) != CONST_DOUBLE)
343 yoperands[0] = operands[0];
344 yoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
345 output_asm_insn (\"loadi %1,%0\", yoperands);
347 xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
348 output_asm_insn (\"loadi %1,%0\", xoperands);
352 output_asm_insn (\"loadw %1,%0\", operands);
353 xoperands[1] = adjust_address (operands[1], SImode, 4);
354 output_asm_insn (\"loadw %1,%0\", xoperands);
357 [(set_attr "type" "arith,arith,load")
358 (set_attr "cc" "clobber,clobber,clobber")])
361 [(set (match_operand:DI 0 "memory_operand" "=o")
362 (match_operand:DI 1 "register_operand" "r"))]
367 xops[0] = operands[0];
368 xops[1] = adjust_address (operands[0], SImode, 4);
369 xops[2] = operands[1];
370 xops[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
371 output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
374 [(set_attr "type" "store")
375 (set_attr "cc" "clobber")])
377 (define_expand "movsi"
378 [(set (match_operand:SI 0 "general_operand" "")
379 (match_operand:SI 1 "general_operand" ""))]
383 if (GET_CODE (operands[0]) == MEM &&
384 GET_CODE (operands[1]) != REG)
385 operands[1] = force_reg (SImode, operands[1]);
388 ;; Reject both args with `general_operand' if not reloading because a
389 ;; mem -> mem move that was split by 'movsi' can be recombined to
390 ;; mem -> mem by the combiner.
392 ;; As a pseudo register can end up in a stack slot during reloading we must
393 ;; allow a r->m move for the next pattern.
394 ;; The first predicate must be `general_operand' because a predicate must
395 ;; be true for each constraint.
398 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m")
399 (match_operand:SI 1 "general_operand" "r,m,n,i,r"))]
400 "reload_in_progress || register_operand (operands[0], SImode)"
405 if (which_alternative == 0)
406 return \"movw %1,%0\"; /* reg -> reg */
408 if (which_alternative == 1)
409 return \"loadw %1,%0\"; /* mem -> reg */
411 if (which_alternative == 2)
413 val = INTVAL (operands[1]); /* known const ->reg */
416 return \"notq $0,%0\";
418 if (val < 0 || val >= 16)
419 return \"loadi %1,%0\";
421 return \"loadq %1,%0\";
424 if (which_alternative == 3) /* unknown const */
425 return \"loada %a1,%0\";
427 return \"storw %1,%0\";
429 [(set_attr "type" "arith,load,arith,load,store")
430 (set_attr "cc" "set2,change0,set1,change0,unchanged")])
434 [(set (match_operand:SI 0 "memory_operand" "=m")
435 (match_operand:SI 1 "int_reg_operand" "r"))]
438 [(set_attr "type" "store")])
446 (define_expand "movhi"
447 [(set (match_operand:HI 0 "general_operand" "")
448 (match_operand:HI 1 "general_operand" ""))]
452 if (GET_CODE (operands[0]) == MEM
453 && ! register_operand (operands[1], HImode))
454 operands[1] = force_reg (HImode, operands[1]);
459 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
460 (match_operand:HI 1 "general_operand" "r,m,n"))]
466 [(set_attr "type" "arith,load,arith")])
469 [(set (match_operand:HI 0 "memory_operand" "=m")
470 (match_operand:HI 1 "register_operand" "r"))]
473 [(set_attr "type" "store")])
480 (define_expand "movqi"
481 [(set (match_operand:QI 0 "general_operand" "")
482 (match_operand:QI 1 "general_operand" ""))]
486 if (GET_CODE (operands[0]) == MEM &&
487 ! register_operand (operands[1], QImode))
488 operands[1] = force_reg (QImode, operands[1]);
493 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
494 (match_operand:QI 1 "general_operand" "r,m,n"))]
500 [(set_attr "type" "arith,load,arith")])
503 [(set (match_operand:QI 0 "memory_operand" "=m")
504 (match_operand:QI 1 "register_operand" "r"))]
507 [(set_attr "type" "store")])
513 (define_expand "movstrsi"
515 [(set (match_operand:BLK 0 "memory_operand" "")
516 (match_operand:BLK 1 "memory_operand" ""))
517 (use (match_operand:SI 2 "general_operand" ""))
518 (use (match_operand:SI 3 "const_int_operand" ""))
519 (clobber (match_scratch:SI 4 ""))
520 (clobber (match_scratch:SI 5 ""))
521 (clobber (match_dup 6))
522 (clobber (match_dup 7))])]
528 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
529 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
534 operands[0] = replace_equiv_address (operands[0], addr0);
535 operands[1] = replace_equiv_address (operands[1], addr1);
537 if (GET_CODE (operands[2]) != CONST_INT)
538 operands[2] = force_reg (SImode, operands[2]);
542 ;; there is a problem with this insn in gcc-2.2.3
543 ;; (clobber (match_dup 2)) does not prevent use of this operand later
544 ;; we always use a scratch register and leave operand 2 unchanged
547 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
548 (mem:BLK (match_operand:SI 1 "register_operand" "r")))
549 (use (match_operand:SI 2 "nonmemory_operand" "rn"))
550 (use (match_operand:SI 3 "const_int_operand" "n"))
551 (clobber (match_scratch:SI 4 "=r"))
552 (clobber (match_scratch:SI 5 "=r"))
553 (clobber (match_dup 0))
554 (clobber (match_dup 1))]
558 extern void clipper_movstr ();
559 clipper_movstr (operands);
562 [(set_attr "cc" "clobber")])
566 ;; Extension and truncation insns.
567 (define_insn "extendhisi2"
568 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
569 (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
572 andi $65535,%0\;xori $32768,%0\;subi $32768,%0
574 [(set_attr "type" "arith,load")])
577 (define_insn "extendqihi2"
578 [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
579 (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
582 andi $255,%0\;xori $128,%0\;subi $128,%0
584 [(set_attr "type" "arith,load")
585 (set_attr "cc" "set1,change0")])
588 (define_insn "extendqisi2"
589 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
590 (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
593 andi $255,%0\;xori $128,%0\;subi $128,%0
595 [(set_attr "type" "arith,load")])
598 (define_insn "extendsfdf2"
599 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
600 (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
604 (define_insn "truncdfsf2"
605 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
606 (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
610 (define_insn "zero_extendhisi2"
611 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
612 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
617 [(set_attr "type" "arith,load")])
620 (define_insn "zero_extendqihi2"
621 [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
622 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
627 [(set_attr "type" "arith,load")
628 (set_attr "cc" "clobber,clobber")])
631 (define_insn "zero_extendqisi2"
632 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
633 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
638 [(set_attr "type" "arith,load")])
642 ;; Fix-to-float conversion insns.
644 (define_insn "floatsisf2"
645 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
646 (float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
650 (define_insn "floatsidf2"
651 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
652 (float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
657 ;; Float-to-fix conversion insns.
659 (define_insn "fix_truncsfsi2"
660 [(set (match_operand:SI 0 "int_reg_operand" "=r")
661 (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
665 (define_insn "fix_truncdfsi2"
666 [(set (match_operand:SI 0 "int_reg_operand" "=r")
667 (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
671 ;;- All kinds of add instructions.
673 (define_insn "adddf3"
674 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
675 (plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
676 (match_operand:DF 2 "fp_reg_operand" "f")))]
679 [(set_attr "type" "fp")])
682 (define_insn "addsf3"
683 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
684 (plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
685 (match_operand:SF 2 "fp_reg_operand" "f")))]
688 [(set_attr "type" "fp")])
690 (define_insn "adddi3"
691 [(set (match_operand:DI 0 "int_reg_operand" "=r")
692 (plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
693 (match_operand:DI 2 "int_reg_operand" "r")))]
699 xoperands[0] = operands[0];
700 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
701 xoperands[2] = operands[2];
702 xoperands[3] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
703 output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands);
706 [(set_attr "type" "arith")
707 (set_attr "cc" "clobber")])
709 (define_insn "addsi3"
710 [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
711 (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
712 (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
716 if (which_alternative == 2) /* 3 address version */
718 if (GET_CODE (operands[2]) == CONST_INT)
719 return \"loada %a2(%1),%0\";
720 return \"loada [%2](%1),%0\";
722 /* 2 address version */
723 if (GET_CODE (operands[2]) == CONST_INT)
725 int val = INTVAL (operands[2]);
727 if (val >= 16 || val == 0x80000000)
728 return \"addi %2,%0\";
730 if (val < 0) /* change to sub */
736 xops[0] = operands[0];
737 xops[1] = GEN_INT (val);
740 output_asm_insn (\"subi %1,%0\", xops);
742 output_asm_insn (\"subq %1,%0\", xops);
747 return \"addq %2,%0\";
750 if (which_alternative == 0)
751 return \"addw %2,%0\";
753 return \"addw %1,%0\";
755 [(set_attr "type" "arith,arith,arith")
756 (set_attr "cc" "set1,set1,change0")])
759 ;;- All kinds of subtract instructions.
761 (define_insn "subdi3"
762 [(set (match_operand:DI 0 "int_reg_operand" "=r")
763 (minus:DI (match_operand:DI 1 "int_reg_operand" "0")
764 (match_operand:DI 2 "int_reg_operand" "r")))]
770 xoperands[0] = operands[0];
771 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
772 xoperands[2] = operands[2];
773 xoperands[3] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
774 output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands);
777 [(set_attr "type" "arith")
778 (set_attr "cc" "clobber")])
780 (define_insn "subsi3"
781 [(set (match_operand:SI 0 "int_reg_operand" "=r")
782 (minus:SI (match_operand:SI 1 "int_reg_operand" "0")
783 (match_operand:SI 2 "nonmemory_operand" "rn")))]
787 if (GET_CODE (operands[2]) == CONST_INT)
789 int val = INTVAL (operands[2]);
791 if (val < 0 || val >= 16)
792 return \"subi %2,%0\";
794 return \"subq %2,%0\";
797 return \"subw %2,%0\";
799 [(set_attr "type" "arith")])
801 (define_insn "subdf3"
802 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
803 (minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
804 (match_operand:DF 2 "fp_reg_operand" "f")))]
807 [(set_attr "type" "fp")])
809 (define_insn "subsf3"
810 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
811 (minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
812 (match_operand:SF 2 "fp_reg_operand" "f")))]
815 [(set_attr "type" "fp")])
818 ;;- Multiply instructions.
820 (define_insn "muldf3"
821 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
822 (mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
823 (match_operand:DF 2 "fp_reg_operand" "f")))]
826 [(set_attr "type" "fp")])
828 (define_insn "mulsf3"
829 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
830 (mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
831 (match_operand:SF 2 "fp_reg_operand" "f")))]
834 [(set_attr "type" "fp")])
836 (define_insn "mulsidi3"
837 [(set (match_operand:DI 0 "int_reg_operand" "=r")
838 (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
839 (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
842 [(set_attr "type" "arith")
843 (set_attr "cc" "clobber")])
845 (define_insn "umulsidi3"
846 [(set (match_operand:DI 0 "int_reg_operand" "=r")
847 (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
848 (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
851 [(set_attr "type" "arith")
852 (set_attr "cc" "clobber")])
854 (define_insn "mulsi3"
855 [(set (match_operand:SI 0 "int_reg_operand" "=r")
856 (mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
857 (match_operand:SI 2 "int_reg_operand" "r")))]
860 [(set_attr "type" "arith")
861 (set_attr "cc" "clobber")])
864 ;;- Divide and mod instructions.
866 (define_insn "divdf3"
867 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
868 (div:DF (match_operand:DF 1 "fp_reg_operand" "0")
869 (match_operand:DF 2 "fp_reg_operand" "f")))]
872 [(set_attr "type" "fp")])
874 (define_insn "divsf3"
875 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
876 (div:SF (match_operand:SF 1 "fp_reg_operand" "0")
877 (match_operand:SF 2 "fp_reg_operand" "f")))]
880 [(set_attr "type" "fp")])
882 (define_insn "divsi3"
883 [(set (match_operand:SI 0 "int_reg_operand" "=r")
884 (div:SI (match_operand:SI 1 "int_reg_operand" "0")
885 (match_operand:SI 2 "int_reg_operand" "r")))]
888 [(set_attr "type" "arith")
889 (set_attr "cc" "clobber")])
891 (define_insn "udivsi3"
892 [(set (match_operand:SI 0 "int_reg_operand" "=r")
893 (udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
894 (match_operand:SI 2 "int_reg_operand" "r")))]
897 [(set_attr "type" "arith")
898 (set_attr "cc" "clobber")])
901 (define_insn "modsi3"
902 [(set (match_operand:SI 0 "int_reg_operand" "=r")
903 (mod:SI (match_operand:SI 1 "int_reg_operand" "0")
904 (match_operand:SI 2 "int_reg_operand" "r")))]
907 [(set_attr "type" "arith")
908 (set_attr "cc" "clobber")])
910 (define_insn "umodsi3"
911 [(set (match_operand:SI 0 "int_reg_operand" "=r")
912 (umod:SI (match_operand:SI 1 "int_reg_operand" "0")
913 (match_operand:SI 2 "int_reg_operand" "r")))]
916 [(set_attr "type" "arith")
917 (set_attr "cc" "clobber")])
920 ;; bit and/or instructions
922 (define_insn "andsi3"
923 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
924 (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
925 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
930 [(set_attr "type" "arith")])
932 (define_insn "iorsi3"
933 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
934 (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
935 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
940 [(set_attr "type" "arith")])
942 (define_insn "xorsi3"
943 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
944 (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
945 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
950 [(set_attr "type" "arith")])
952 (define_insn "negdf2"
953 [(set (match_operand:DF 0 "fp_reg_operand" "=f")
954 (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
957 [(set_attr "type" "fp")])
959 (define_insn "negsf2"
960 [(set (match_operand:SF 0 "fp_reg_operand" "=f")
961 (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
964 [(set_attr "type" "fp")])
966 (define_insn "negsi2"
967 [(set (match_operand:SI 0 "int_reg_operand" "=r")
968 (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
971 [(set_attr "type" "arith")])
974 (define_insn "one_cmplsi2"
975 [(set (match_operand:SI 0 "int_reg_operand" "=r")
976 (not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
979 [(set_attr "type" "arith")])
983 ;; Right shift on the clipper works by negating the shift count,
984 ;; then emitting a right shift with the shift count negated. This means
985 ;; that all actual shift counts in the RTL will be positive.
987 (define_expand "ashrdi3"
988 [(set (match_operand:DI 0 "int_reg_operand" "")
989 (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
990 (match_operand:SI 2 "nonmemory_operand" "")))]
994 if (GET_CODE (operands[2]) != CONST_INT)
995 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
999 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1000 (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1001 (match_operand:SI 2 "const_int_operand" "n")))]
1004 [(set_attr "type" "arith")])
1007 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1008 (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1009 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1012 [(set_attr "type" "arith")])
1014 (define_expand "ashrsi3"
1015 [(set (match_operand:SI 0 "int_reg_operand" "")
1016 (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1017 (match_operand:SI 2 "nonmemory_operand" "")))]
1021 if (GET_CODE (operands[2]) != CONST_INT)
1022 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1026 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1027 (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1028 (match_operand:SI 2 "const_int_operand" "n")))]
1031 [(set_attr "type" "arith")])
1034 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1035 (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1036 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1039 [(set_attr "type" "arith")])
1045 (define_insn "ashldi3"
1046 [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1047 (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1048 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1053 [(set_attr "type" "arith")])
1056 (define_insn "ashlsi3"
1057 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1058 (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1059 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1065 if (which_alternative == 0)
1066 return \"shaw %2,%0\";
1068 val = INTVAL (operands[2]);
1071 return \"addw %0,%0\;addw %0,%0\";
1074 return \"addw %0,%0\";
1076 return \"shai %2,%0\";
1078 [(set_attr "type" "arith")])
1084 (define_expand "lshrdi3"
1085 [(set (match_operand:DI 0 "int_reg_operand" "")
1086 (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
1087 (match_operand:SI 2 "nonmemory_operand" "")))]
1091 if (GET_CODE (operands[2]) != CONST_INT)
1092 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1096 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1097 (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1098 (match_operand:SI 2 "const_int_operand" "n")))]
1101 [(set_attr "type" "arith")])
1104 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1105 (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1106 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1109 [(set_attr "type" "arith")])
1111 (define_expand "lshrsi3"
1112 [(set (match_operand:SI 0 "int_reg_operand" "")
1113 (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1114 (match_operand:SI 2 "nonmemory_operand" "")))]
1118 if (GET_CODE (operands[2]) != CONST_INT)
1119 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1123 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1124 (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1125 (match_operand:SI 2 "const_int_operand" "n")))]
1128 [(set_attr "type" "arith")])
1131 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1132 (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1133 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1136 [(set_attr "type" "arith")])
1142 (define_expand "rotrdi3"
1143 [(set (match_operand:DI 0 "int_reg_operand" "")
1144 (rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
1145 (match_operand:SI 2 "nonmemory_operand" "")))]
1149 if (GET_CODE (operands[2]) != CONST_INT)
1150 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1154 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1155 (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1156 (match_operand:SI 2 "const_int_operand" "n")))]
1159 [(set_attr "type" "arith")])
1162 [(set (match_operand:DI 0 "int_reg_operand" "=r")
1163 (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1164 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1167 [(set_attr "type" "arith")])
1169 (define_expand "rotrsi3"
1170 [(set (match_operand:SI 0 "int_reg_operand" "")
1171 (rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
1172 (match_operand:SI 2 "nonmemory_operand" "")))]
1176 if (GET_CODE (operands[2]) != CONST_INT)
1177 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1181 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1182 (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1183 (match_operand:SI 2 "const_int_operand" "n")))]
1186 [(set_attr "type" "arith")])
1189 [(set (match_operand:SI 0 "int_reg_operand" "=r")
1190 (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1191 (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1194 [(set_attr "type" "arith")])
1196 (define_insn "rotldi3"
1197 [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1198 (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1199 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1204 [(set_attr "type" "arith")])
1206 (define_insn "rotlsi3"
1207 [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1208 (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1209 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1214 [(set_attr "type" "arith")])
1218 ;; jump and branch insns
1222 (label_ref (match_operand 0 "" "")))]
1225 [(set_attr "type" "branch")])
1227 (define_insn "tablejump"
1228 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1229 (use (label_ref (match_operand 1 "" "")))]
1232 [(set_attr "type" "branch")])
1236 (if_then_else (eq (cc0)
1238 (label_ref (match_operand 0 "" ""))
1242 [(set_attr "type" "branch")])
1246 (if_then_else (ne (cc0)
1248 (label_ref (match_operand 0 "" ""))
1252 [(set_attr "type" "branch")])
1256 (if_then_else (gt (cc0)
1258 (label_ref (match_operand 0 "" ""))
1262 [(set_attr "type" "branch")])
1266 (if_then_else (gtu (cc0)
1268 (label_ref (match_operand 0 "" ""))
1272 [(set_attr "type" "branch")])
1276 (if_then_else (lt (cc0)
1278 (label_ref (match_operand 0 "" ""))
1282 [(set_attr "type" "branch")])
1286 (if_then_else (ltu (cc0)
1288 (label_ref (match_operand 0 "" ""))
1292 [(set_attr "type" "branch")])
1296 (if_then_else (ge (cc0)
1298 (label_ref (match_operand 0 "" ""))
1302 [(set_attr "type" "branch")])
1306 (if_then_else (geu (cc0)
1308 (label_ref (match_operand 0 "" ""))
1312 [(set_attr "type" "branch")])
1316 (if_then_else (le (cc0)
1318 (label_ref (match_operand 0 "" ""))
1322 [(set_attr "type" "branch")])
1326 (if_then_else (leu (cc0)
1328 (label_ref (match_operand 0 "" ""))
1332 [(set_attr "type" "branch")])
1334 ;; Recognize reversed jumps.
1337 (if_then_else (match_operator 0 "comparison_operator"
1341 (label_ref (match_operand 1 "" ""))))]
1343 "br%C0 %l1" ; %C0 negates condition
1344 [(set_attr "type" "branch")])
1347 ;; call instructions
1350 [(call (match_operand:QI 0 "general_operand" "m")
1351 (match_operand:SI 1 "general_operand" ""))]
1352 ;; Operand 1 not used on the clipper.
1356 (define_insn "call_value"
1357 [(set (match_operand 0 "" "=rf")
1358 (call (match_operand:QI 1 "general_operand" "m")
1359 (match_operand:SI 2 "general_operand" "g")))]
1360 ;; Operand 2 not used on the clipper
1364 ;; Call subroutine returning any type.
1366 (define_expand "untyped_call"
1367 [(parallel [(call (match_operand 0 "" "")
1369 (match_operand 1 "" "")
1370 (match_operand 2 "" "")])]
1376 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
1378 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1380 rtx set = XVECEXP (operands[2], 0, i);
1381 emit_move_insn (SET_DEST (set), SET_SRC (set));
1384 /* The optimizer does not know that the call sets the function value
1385 registers we stored in the result block. We avoid problems by
1386 claiming that all hard registers are used and clobbered at this
1388 emit_insn (gen_blockage ());
1393 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1394 ;; all of memory. This blocks insns from being moved across this point.
1396 (define_insn "blockage"
1397 [(unspec_volatile [(const_int 0)] 0)]
1401 (define_insn "indirect_jump"
1402 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1405 [(set_attr "type" "branch")])
1412 [(set_attr "type" "arith")
1413 (set_attr "cc" "unchanged")])
1417 ;; while (--foo >= 0)
1419 ;; Combiners for 'decrement test and branch' do not work for clipper.
1420 ;; These patters are jump_insns that do not allow output reloads and clipper
1421 ;; can only decrement and test registers.