1 ;; Machine description for the TMS320C[34]x for GNU C compiler
2 ;; Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
4 ;; Contributed by Michael Hayes (m.hayes@elec.canterbury.cri.nz)
5 ;; and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
26 ; Set up addressing macros to handle direct memory references properly
27 ; Try using PQImode again for addresses since C30 only uses
28 ; 24-bit addresses. Ideally GCC would emit different insns
29 ; for QImode and Pmode, whether Pmode was QImode or PQImode.
30 ; For addresses we wouldn't have to have a clobber of the CC
31 ; associated with each insn and we could use MPYI in address
32 ; calculations without having to synthesise a proper 32 bit multiply.
34 ; Additional C30/C40 instructions not coded:
35 ; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
36 ; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI, TRAPcond
38 ; Additional C40 instructions not coded:
39 ; LDEP, LDPE, LWRct, FRIEEE, TOIEEE, LAJcond, LATcond, RETIcondD
44 ; QImode char, short, int, long (32-bits)
45 ; HImode long long (64-bits)
46 ; QFmode float, double (32-bits)
47 ; HFmode long double (40-bits)
54 ; comparison_operator LT, GT, LE, GE, LTU, GTU, LEU, GEU, EQ, NE
55 ; memory_operand memory [m]
56 ; immediate_operand immediate constant [IKN]
57 ; register_operand register [rf]
58 ; general_operand register, memory, constant [rfmI]
60 ; addr_reg_operand AR0-AR7, pseudo reg [a]
61 ; sp_reg_operand SP [b]
62 ; std_reg_operand AR0-AR7, IR0-IR1, RC, RS, RE, SP, pseudo [c]
63 ; ext_reg_operand R0-R11, pseudo reg [f]
64 ; ext_low_reg_operand R0-R7, pseudo reg [q]
65 ; index_reg_operand IR0-IR1, pseudo reg [x]
66 ; st_reg_operand ST [y]
67 ; dp_reg_operand DP [z]
68 ; stik_const_operand 5-bit const [K]
69 ; src_operand general operand [rfmHI]
70 ; par_ind_operand indirect S mode (ARx + 0, 1, IRx) [S<>]
71 ; parallel_operand par_ind_operand or ext_low_reg_operand
73 ; ADDI src2, src1, dst three operand op
74 ; ADDI src, dst two operand op
76 ; Note that the predicates are only used when selecting a pattern
77 ; to determine if an operand is valid.
79 ; The constraints then select which of the possible valid operands
80 ; is present (and guide register selection). The actual assembly
81 ; instruction is then selected on the basis of the constraints.
83 ; The extra constraint (valid_operands) is used to determine if
84 ; the combination of operands is legitimate for the pattern.
89 ; a address reg AR0-AR7
91 ; c other int reg AR0-AR7, IR0-IR1, RC, RS, RE
92 ; d fp reg R0-R11 (sets CC when dst)
93 ; f fp reg R0-R11 (sets CC when dst)
94 ; g general reg, memory, constant
95 ; h fp reg R0-R11 (sets CC when dst)
96 ; i immediate int constant
98 ; q low fp reg R0-R7 (sets CC when dst)
99 ; r general reg R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE
100 ; s immediate int (value not explicit)
103 ; x index reg IR0-IR1
104 ; y status (CC) reg ST
108 ; H fp 16-bit constant
110 ; J signed 8-bit (C4x only)
111 ; K signed 5-bit (C4x only)
113 ; M unsigned 8-bit (C4x only)
114 ; N ones complement of unsigned 16-bit
115 ; O 16 bit high constant
116 ; Q ARx + 9-bit signed disp
117 ; R ARx + 5-bit unsigned disp (C4x only)
118 ; S ARx + 0, 1, IRx disp
119 ; T symbol ref (direct)
120 ; < memory operand with autodecrement addressing
121 ; > memory operand with autoincrement addressing
122 ; { memory operand with pre-modify addressing
123 ; } memory operand with post-modify addressing
125 ; Note that the d, f, and h constraints are equivalent.
126 ; The m constraint is equivalent to QT<>{}
128 ; Note that the constraints are used to select the operands
129 ; for a chosen pattern. The constraint that requires the fewest
130 ; instructions to load an operand is chosen.
132 ; Note that the 'r' constraint is mostly only used for src integer register
133 ; operands, while 'c' and 'd' constraints are generally only used for dst
134 ; integer register operands (the 'r' constraint is the union of the 'c' and
135 ; 'd' constraints). When a register satisfying the 'd' constraint
136 ; is used as a dst operand, the CC gets clobbered (except for LDIcond)---but
139 ; The 'f' constraint is only for float register operands---when
140 ; a register satisying the 'f' constraint is used as a dst operand,
141 ; the CC gets clobbered (except for LDFcond).
143 ; The ! in front of the 'b' constaint says to GCC to disparage the
144 ; use of this constraint. The 'b' constraint applies only to the SP.
146 ; Note that we deal with the condition code CC like some of the RISC
147 ; architectures (arm, sh, sparc) where it is stored in a general register,
148 ; in this case the hard register ST (21). Unlike these other architectures
149 ; that do not set the CC with many instructions, the C[34]x architectures
150 ; sets the CC for many instructions when the destination register is
151 ; an extended precision register. While it would have been easier
152 ; to use the generic cc0 register to store the CC, as with most of
153 ; the other ported architectures, this constrains the setting and testing
154 ; of the CC to be consecutive insns. Thus we would reduce the benefit
155 ; of scheduling instructions to avoid pipeline conflicts and filling of
156 ; delayed branch slots.
158 ; Since the C[34]x has many instructions that set the CC, we pay the
159 ; price of having to explicity define which insns clobber the CC
160 ; (rather than using the macro NOTICE_UPDATE_CC).
162 ; Note that many patterns say that the CC is clobbered when in fact
163 ; that it may not be (depending on the destination register).
164 ; We have to cover ourselves if an extended precision register
165 ; is allocated to the destination register.
166 ; Unfortunately, it is not easy to tell GCC that the clobbering of CC
167 ; is register dependent. If we could tolerate the ST register being
168 ; copied about, then we could store the CC in a pseudo register and
169 ; use constructs such as (clobber (match_scratch:CC N "&y,X")) to
170 ; indicate that the 'y' class (ST register) is clobbered for the
171 ; first combination of operands, but not with the second.
172 ; I tried this approach for a while but reload got unhappy since I
173 ; didn't allow it to move the CC around.
175 ; Note that fundamental operations, such as moves, must not clobber the
176 ; CC. Thus movqi choses a move instruction that doesn't clobber the CC.
177 ; If GCC wants to combine a move with a compare, it is smart enough to
178 ; chose the move instruction that sets the CC.
180 ; Unfortunately, the C[34]x instruction set does not have arithmetic or
181 ; logical operations that never touch the CC. We thus have to assume
182 ; that the CC may be clobbered at all times. If we define patterns
183 ; such as addqi without the clobber of CC, then GCC will be forced
184 ; to use registers such as the auxiliary registers which can cause
185 ; horrible pipeline conflicts. The tradeoff is that GCC can't now
186 ; sneak in an add instruction between setting and testing of the CC.
188 ; Most of the C[34]x instructions require operands of the following formats,
189 ; where imm represents an immediate constant, dir a direct memory reference,
190 ; ind an indirect memory reference, and reg a register:
192 ; src2 (op2) src1 (op1) dst (op0)
193 ; imm dir ind reg | imm dir ind reg | reg Notes
194 ;---------------------+----------------------+------
195 ; ILH T Q<> r | - - - 0 | r 2 operand
196 ; - - S<> r | - - S<> r | r
197 ; J - R - | - - R r | r C4x
199 ; Arithmetic operations use the I, J constraints for immediate constants,
200 ; while logical operations use the L, J constraints. Floating point
201 ; operations use the H constraint for immediate constants.
203 ; With most instructions the src2 and src1 operands are commutative
204 ; (except for SUB, SUBR, ANDN). The assembler considers
205 ; ADDI 10, R0, R1 and ADDI R0, 10, R1 to be equivalent.
206 ; We thus match src2 and src1 with the src_operand predicate and
207 ; use valid_operands as the extra constraint to reject invalid
208 ; operand combinations. For example, ADDI @foo, @bar, R0.
210 ; Note that we use the ? modifier so that reload doesn't preferentially
211 ; try the alternative where three registers are acceptable as
212 ; operands (whenever an operand requires reloading). Instead it will try
213 ; the 2 operand form which will produce better code since it won't require
214 ; a new spill register.
216 ; Note that the floating point representation of 0.0 on the C4x
217 ; is 0x80000000 (-2147483648). This value produces an warning
218 ; message on 32-bit machines about the decimal constant being so large
219 ; that it is unsigned.
221 ; With two operand instructions patterns having two sets,
222 ; the compare set must come first to keep the combiner happy.
223 ; While the combiner seems to cope most of the time with the
224 ; compare set coming second, it's best to have it first.
227 ; C4x CONSTANT attributes
229 (define_attr "cpu" "c4x,c3x"
231 (cond [(symbol_ref "TARGET_C3X") (const_string "c3x")]
232 (const_string "c4x"))))
235 ; C4x INSN ATTRIBUTES:
237 ; lda load address, non-clobber CC
238 ; store memory store, non-clobber CC
239 ; load_load parallel memory loads, non-clobber CC
240 ; load_store parallel memory load and store, non-clobber CC
241 ; store_load parallel memory store and load, non-clobber CC
242 ; store_store parallel memory stores, non-clobber CC
243 ; unary two operand arithmetic, non-clobber CC
244 ; unarycc two operand arithmetic, clobber CC
245 ; binary three operand arithmetic, non-clobber CC
246 ; binarycc three operand arithmetic, clobber CC
247 ; compare compare, clobber CC
249 ; rets return from subroutine
250 ; jump unconditional branch
251 ; jmpc conditional branch
252 ; db decrement and branch (unconditional)
253 ; dbc decrement and branch (conditional)
257 ; repeat block repeat
258 ; repeat_top block repeat top
260 ; multi multiple instruction
263 ; The only real instructions that affect things are the ones that modify
264 ; address registers and ones that call or jump. Note that the number
265 ; of operands refers to the RTL insn pattern, not the number of explicit
266 ; operands in the machine instruction.
268 (define_attr "type" "lda,store,unary,unarycc,binary,binarycc,compare,call,rets,jump,jmpc,db,dbc,misc,ldp,repeat,repeat_top,laj,load_load,load_store,store_load,store_store,push,pop,multi"
269 (const_string "misc"))
272 ; Some instructions operate on unsigned data constants, some on signed data
273 ; constants, or the ones complement of unsigned constants.
274 ; This differentiates them. Default to signed. This attribute
275 ; is used by the macro SMALL_CONST () (defined in c4x.h) to determine
276 ; whether an immediate integer constant will fit within the instruction,
277 ; or will have to be loaded using direct addressing from memory.
278 ; Note that logical operations assume unsigned integers whereas
279 ; arithmetic operations assume signed integers. Note that the C4x
280 ; small immediate constant (J) used as src2 in three operand instructions
281 ; is always signed. not_uint16 refers to a number that fits into 16-bits
282 ; when one's complemented.
284 (define_attr "data" "int16,uint16,high_16,not_uint16" (const_string "int16"))
286 (define_asm_attributes
287 [(set_attr "type" "multi")])
292 ; Define delay slot scheduling for branch and call instructions.
293 ; The C[34]x has three delay slots. Note that none of the three instructions
294 ; that follow a delayed branch can be a Bcond, BcondD, BR, BRD, DBcond,
295 ; DBcondD, CALL, CALLcond, TRAPcond, RETIcond, RETScond, RPTB, RPTS, or IDLE.
297 ; Annulled branches are a bit difficult because the next instructions
299 ; The table below shows what phase of the c4x is executed.
301 ; op1 fetch, decode and read executed
302 ; op2 fetch and decode executed
304 ; This means that we can allow any instruction in the last delay slot
305 ; and only instructions which modify registers in the first two.
306 ; lda can not be executed in the first delay slot
307 ; and ldpk can not be executed in the first two delay slots.
309 (define_attr "onlyreg" "false,true"
310 (cond [(eq_attr "type" "unary,unarycc")
311 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
312 (match_operand 1 "reg_imm_operand" ""))
313 (const_string "true") (const_string "false"))
314 (eq_attr "type" "binary,binarycc")
315 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
316 (and (match_operand 1 "reg_imm_operand" "")
317 (match_operand 2 "reg_imm_operand" "")))
318 (const_string "true") (const_string "false"))]
319 (const_string "false")))
321 (define_attr "onlyreg_nomod" "false,true"
322 (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
323 (if_then_else (and (match_operand 0 "not_modify_reg" "")
324 (match_operand 1 "not_modify_reg" ""))
325 (const_string "true") (const_string "false"))
326 (eq_attr "type" "binary,binarycc")
327 (if_then_else (and (match_operand 0 "not_modify_reg" "")
328 (and (match_operand 1 "not_modify_reg" "")
329 (match_operand 2 "not_modify_reg" "")))
330 (const_string "true") (const_string "false"))]
331 (const_string "false")))
333 (define_attr "not_repeat_reg" "false,true"
334 (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
335 (if_then_else (and (match_operand 0 "not_rc_reg" "")
336 (match_operand 1 "not_rc_reg" ""))
337 (const_string "true") (const_string "false"))
338 (eq_attr "type" "binary,binarycc")
339 (if_then_else (and (match_operand 0 "not_rc_reg" "")
340 (and (match_operand 1 "not_rc_reg" "")
341 (match_operand 2 "not_rc_reg" "")))
342 (const_string "true") (const_string "false"))]
343 (const_string "false")))
345 (define_attr "in_annul_slot_1" "false,true"
346 (if_then_else (and (and (eq_attr "cpu" "c4x")
347 (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi"))
348 (eq_attr "onlyreg" "true"))
349 (const_string "true")
350 (const_string "false")))
352 (define_attr "in_annul_slot_2" "false,true"
353 (if_then_else (and (and (eq_attr "cpu" "c4x")
354 (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
355 (eq_attr "onlyreg_nomod" "true"))
356 (const_string "true")
357 (const_string "false")))
359 (define_attr "in_annul_slot_3" "false,true"
360 (if_then_else (and (eq_attr "cpu" "c4x")
361 (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,push,pop,multi"))
362 (const_string "true")
363 (const_string "false")))
365 (define_attr "in_delay_slot" "false,true"
366 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
367 (const_string "true")
368 (const_string "false")))
370 (define_attr "in_repeat_slot" "false,true"
371 (if_then_else (and (eq_attr "cpu" "c4x")
372 (and (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
373 (eq_attr "not_repeat_reg" "true")))
374 (const_string "true")
375 (const_string "false")))
377 (define_attr "in_dbc_slot" "false,true"
378 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,multi")
379 (const_string "true")
380 (const_string "false")))
382 (define_delay (eq_attr "type" "jmpc")
383 [(eq_attr "in_delay_slot" "true")
384 (eq_attr "in_annul_slot_1" "true")
385 (eq_attr "in_annul_slot_1" "true")
387 (eq_attr "in_delay_slot" "true")
388 (eq_attr "in_annul_slot_2" "true")
389 (eq_attr "in_annul_slot_2" "true")
391 (eq_attr "in_delay_slot" "true")
392 (eq_attr "in_annul_slot_3" "true")
393 (eq_attr "in_annul_slot_3" "true") ])
396 (define_delay (eq_attr "type" "repeat_top")
397 [(eq_attr "in_repeat_slot" "true") (nil) (nil)
398 (eq_attr "in_repeat_slot" "true") (nil) (nil)
399 (eq_attr "in_repeat_slot" "true") (nil) (nil)])
401 (define_delay (eq_attr "type" "jump,db")
402 [(eq_attr "in_delay_slot" "true") (nil) (nil)
403 (eq_attr "in_delay_slot" "true") (nil) (nil)
404 (eq_attr "in_delay_slot" "true") (nil) (nil)])
407 ; Decrement and branch conditional instructions cannot modify the
408 ; condition codes for the cycles in the delay slots.
410 (define_delay (eq_attr "type" "dbc")
411 [(eq_attr "in_dbc_slot" "true") (nil) (nil)
412 (eq_attr "in_dbc_slot" "true") (nil) (nil)
413 (eq_attr "in_dbc_slot" "true") (nil) (nil)])
415 ; The LAJ instruction has three delay slots but the last slot is
416 ; used for pushing the return address. Thus we can only use two slots.
418 (define_delay (eq_attr "type" "laj")
419 [(eq_attr "in_delay_slot" "true") (nil) (nil)
420 (eq_attr "in_delay_slot" "true") (nil) (nil)])
431 ; 7 repeat block filler
438 ; C4x FUNCTIONAL UNITS
440 ; Define functional units for instruction scheduling to minimise
441 ; pipeline conflicts.
443 ; With the C3x, an external memory write (with no wait states) takes
444 ; two cycles and an external memory read (with no wait states) takes
445 ; one cycle. However, an external read following an external write
446 ; takes two cycles. With internal memory, reads and writes take
449 ; When a C4x address register is loaded it will not be available for
450 ; an extra machine cycle. Calculating with a C4x address register
451 ; makes it unavailable for 2 machine cycles. To notify GCC of these
452 ; pipeline delays, each of the auxiliary and index registers are declared
453 ; as separate functional units.
455 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
456 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
458 ; MULTIPLICITY 1 (C4x has no independent identical function units)
459 ; SIMULTANEITY 0 (C4x is pipelined)
460 ; READY_DELAY 1 (Results usually ready after every cyle)
461 ; ISSUE_DELAY 1 (Can issue insns every cycle)
463 ; Just some dummy definitions. The real work is done in c4x_adjust_cost.
464 ; These are needed so the min/max READY_DELAY is known.
466 (define_function_unit "dummy" 1 0 (const_int 0) 1 1)
467 (define_function_unit "dummy" 1 0 (const_int 0) 2 1)
468 (define_function_unit "dummy" 1 0 (const_int 0) 3 1)
470 ;(define_function_unit "ar0" 1 0
471 ; (and (eq_attr "cpu" "c4x")
472 ; (and (eq_attr "setar0" "1")
473 ; (eq_attr "usear0" "1")))
476 ;(define_function_unit "ar0" 1 0
477 ; (and (eq_attr "cpu" "c4x")
478 ; (and (eq_attr "setlda_ar0" "1")
479 ; (eq_attr "usear0" "1")))
482 ;(define_function_unit "ar0" 1 0
483 ; (and (eq_attr "cpu" "c4x")
484 ; (and (eq_attr "usear0" "1")
485 ; (eq_attr "readar0" "1")))
488 ; The attribute setar0 is set to 1 for insns where ar0 is a dst operand.
489 ; Note that the attributes unarycc and binarycc do not apply
490 ; if ar0 is a dst operand (only loading an ext. prec. reg. sets CC)
491 (define_attr "setar0" ""
492 (cond [(eq_attr "type" "unary,binary")
493 (if_then_else (match_operand 0 "ar0_reg_operand" "")
494 (const_int 1) (const_int 0))]
497 (define_attr "setlda_ar0" ""
498 (cond [(eq_attr "type" "lda")
499 (if_then_else (match_operand 0 "ar0_reg_operand" "")
500 (const_int 1) (const_int 0))]
503 ; The attribute usear0 is set to 1 for insns where ar0 is used
504 ; for addressing, as a src operand, or as a dst operand.
505 (define_attr "usear0" ""
506 (cond [(eq_attr "type" "compare,store")
507 (if_then_else (match_operand 0 "ar0_mem_operand" "")
508 (const_int 1) (const_int 0))
509 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
510 (if_then_else (match_operand 1 "ar0_mem_operand" "")
511 (const_int 1) (const_int 0))
512 (eq_attr "type" "binary,binarycc")
513 (if_then_else (match_operand 2 "ar0_mem_operand" "")
514 (const_int 1) (const_int 0))
515 (eq_attr "type" "db,dbc")
516 (if_then_else (match_operand 0 "ar0_reg_operand" "")
517 (const_int 1) (const_int 0))]
520 ; The attribute readar0 is set to 1 for insns where ar0 is a src operand.
521 (define_attr "readar0" ""
522 (cond [(eq_attr "type" "compare")
523 (if_then_else (match_operand 0 "ar0_reg_operand" "")
524 (const_int 1) (const_int 0))
525 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
526 (if_then_else (match_operand 1 "ar0_reg_operand" "")
527 (const_int 1) (const_int 0))
528 (eq_attr "type" "binary,binarycc")
529 (if_then_else (match_operand 2 "ar0_reg_operand" "")
530 (const_int 1) (const_int 0))]
533 ;(define_function_unit "ar1" 1 0
534 ; (and (eq_attr "cpu" "c4x")
535 ; (and (eq_attr "setar1" "1")
536 ; (eq_attr "usear1" "1")))
539 ;(define_function_unit "ar1" 1 0
540 ; (and (eq_attr "cpu" "c4x")
541 ; (and (eq_attr "setlda_ar1" "1")
542 ; (eq_attr "usear1" "1")))
545 ;(define_function_unit "ar1" 1 0
546 ; (and (eq_attr "cpu" "c4x")
547 ; (and (eq_attr "usear1" "1")
548 ; (eq_attr "readar1" "1")))
551 (define_attr "setar1" ""
552 (cond [(eq_attr "type" "unary,binary")
553 (if_then_else (match_operand 0 "ar1_reg_operand" "")
554 (const_int 1) (const_int 0))]
557 (define_attr "setlda_ar1" ""
558 (cond [(eq_attr "type" "lda")
559 (if_then_else (match_operand 0 "ar1_reg_operand" "")
560 (const_int 1) (const_int 0))]
563 (define_attr "usear1" ""
564 (cond [(eq_attr "type" "compare,store")
565 (if_then_else (match_operand 0 "ar1_mem_operand" "")
566 (const_int 1) (const_int 0))
567 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
568 (if_then_else (match_operand 1 "ar1_mem_operand" "")
569 (const_int 1) (const_int 0))
570 (eq_attr "type" "binary,binarycc")
571 (if_then_else (match_operand 2 "ar1_mem_operand" "")
572 (const_int 1) (const_int 0))
573 (eq_attr "type" "db,dbc")
574 (if_then_else (match_operand 0 "ar1_reg_operand" "")
575 (const_int 1) (const_int 0))]
578 (define_attr "readar1" ""
579 (cond [(eq_attr "type" "compare")
580 (if_then_else (match_operand 0 "ar1_reg_operand" "")
581 (const_int 1) (const_int 0))
582 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
583 (if_then_else (match_operand 1 "ar1_reg_operand" "")
584 (const_int 1) (const_int 0))
585 (eq_attr "type" "binary,binarycc")
586 (if_then_else (match_operand 2 "ar1_reg_operand" "")
587 (const_int 1) (const_int 0))]
590 ;(define_function_unit "ar2" 1 0
591 ; (and (eq_attr "cpu" "c4x")
592 ; (and (eq_attr "setar2" "1")
593 ; (eq_attr "usear2" "1")))
596 ;(define_function_unit "ar2" 1 0
597 ; (and (eq_attr "cpu" "c4x")
598 ; (and (eq_attr "setlda_ar2" "1")
599 ; (eq_attr "usear2" "1")))
602 ;(define_function_unit "ar2" 1 0
603 ; (and (eq_attr "cpu" "c4x")
604 ; (and (eq_attr "usear2" "1")
605 ; (eq_attr "readar2" "1")))
608 (define_attr "setar2" ""
609 (cond [(eq_attr "type" "unary,binary")
610 (if_then_else (match_operand 0 "ar2_reg_operand" "")
611 (const_int 1) (const_int 0))]
614 (define_attr "setlda_ar2" ""
615 (cond [(eq_attr "type" "lda")
616 (if_then_else (match_operand 0 "ar2_reg_operand" "")
617 (const_int 1) (const_int 0))]
620 (define_attr "usear2" ""
621 (cond [(eq_attr "type" "compare,store")
622 (if_then_else (match_operand 0 "ar2_mem_operand" "")
623 (const_int 1) (const_int 0))
624 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
625 (if_then_else (match_operand 1 "ar2_mem_operand" "")
626 (const_int 1) (const_int 0))
627 (eq_attr "type" "binary,binarycc")
628 (if_then_else (match_operand 2 "ar2_mem_operand" "")
629 (const_int 1) (const_int 0))
630 (eq_attr "type" "db,dbc")
631 (if_then_else (match_operand 0 "ar2_reg_operand" "")
632 (const_int 1) (const_int 0))]
635 (define_attr "readar2" ""
636 (cond [(eq_attr "type" "compare")
637 (if_then_else (match_operand 0 "ar2_reg_operand" "")
638 (const_int 1) (const_int 0))
639 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
640 (if_then_else (match_operand 1 "ar2_reg_operand" "")
641 (const_int 1) (const_int 0))
642 (eq_attr "type" "binary,binarycc")
643 (if_then_else (match_operand 2 "ar2_reg_operand" "")
644 (const_int 1) (const_int 0))]
647 ;(define_function_unit "ar3" 1 0
648 ; (and (eq_attr "cpu" "c4x")
649 ; (and (eq_attr "setar3" "1")
650 ; (eq_attr "usear3" "1")))
653 ;(define_function_unit "ar3" 1 0
654 ; (and (eq_attr "cpu" "c4x")
655 ; (and (eq_attr "setlda_ar3" "1")
656 ; (eq_attr "usear3" "1")))
659 ;(define_function_unit "ar3" 1 0
660 ; (and (eq_attr "cpu" "c4x")
661 ; (and (eq_attr "usear3" "1")
662 ; (eq_attr "readar3" "1")))
665 (define_attr "setar3" ""
666 (cond [(eq_attr "type" "unary,binary")
667 (if_then_else (match_operand 0 "ar3_reg_operand" "")
668 (const_int 1) (const_int 0))]
671 (define_attr "setlda_ar3" ""
672 (cond [(eq_attr "type" "lda")
673 (if_then_else (match_operand 0 "ar3_reg_operand" "")
674 (const_int 1) (const_int 0))]
677 (define_attr "usear3" ""
678 (cond [(eq_attr "type" "compare,store")
679 (if_then_else (match_operand 0 "ar3_mem_operand" "")
680 (const_int 1) (const_int 0))
681 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
682 (if_then_else (match_operand 1 "ar3_mem_operand" "")
683 (const_int 1) (const_int 0))
684 (eq_attr "type" "binary,binarycc")
685 (if_then_else (match_operand 2 "ar3_mem_operand" "")
686 (const_int 1) (const_int 0))
687 (eq_attr "type" "db,dbc")
688 (if_then_else (match_operand 0 "ar3_reg_operand" "")
689 (const_int 1) (const_int 0))]
692 (define_attr "readar3" ""
693 (cond [(eq_attr "type" "compare")
694 (if_then_else (match_operand 0 "ar3_reg_operand" "")
695 (const_int 1) (const_int 0))
696 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
697 (if_then_else (match_operand 1 "ar3_reg_operand" "")
698 (const_int 1) (const_int 0))
699 (eq_attr "type" "binary,binarycc")
700 (if_then_else (match_operand 2 "ar3_reg_operand" "")
701 (const_int 1) (const_int 0))]
704 ;(define_function_unit "ar4" 1 0
705 ; (and (eq_attr "cpu" "c4x")
706 ; (and (eq_attr "setar4" "1")
707 ; (eq_attr "usear4" "1")))
710 ;(define_function_unit "ar4" 1 0
711 ; (and (eq_attr "cpu" "c4x")
712 ; (and (eq_attr "setlda_ar4" "1")
713 ; (eq_attr "usear4" "1")))
716 ;(define_function_unit "ar4" 1 0
717 ; (and (eq_attr "cpu" "c4x")
718 ; (and (eq_attr "usear4" "1")
719 ; (eq_attr "readar4" "1")))
722 (define_attr "setar4" ""
723 (cond [(eq_attr "type" "unary,binary")
724 (if_then_else (match_operand 0 "ar4_reg_operand" "")
725 (const_int 1) (const_int 0))]
728 (define_attr "setlda_ar4" ""
729 (cond [(eq_attr "type" "lda")
730 (if_then_else (match_operand 0 "ar4_reg_operand" "")
731 (const_int 1) (const_int 0))]
734 (define_attr "usear4" ""
735 (cond [(eq_attr "type" "compare,store")
736 (if_then_else (match_operand 0 "ar4_mem_operand" "")
737 (const_int 1) (const_int 0))
738 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
739 (if_then_else (match_operand 1 "ar4_mem_operand" "")
740 (const_int 1) (const_int 0))
741 (eq_attr "type" "binary,binarycc")
742 (if_then_else (match_operand 2 "ar4_mem_operand" "")
743 (const_int 1) (const_int 0))
744 (eq_attr "type" "db,dbc")
745 (if_then_else (match_operand 0 "ar4_reg_operand" "")
746 (const_int 1) (const_int 0))]
749 (define_attr "readar4" ""
750 (cond [(eq_attr "type" "compare")
751 (if_then_else (match_operand 0 "ar4_reg_operand" "")
752 (const_int 1) (const_int 0))
753 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
754 (if_then_else (match_operand 1 "ar4_reg_operand" "")
755 (const_int 1) (const_int 0))
756 (eq_attr "type" "binary,binarycc")
757 (if_then_else (match_operand 2 "ar4_reg_operand" "")
758 (const_int 1) (const_int 0))]
761 ;(define_function_unit "ar5" 1 0
762 ; (and (eq_attr "cpu" "c4x")
763 ; (and (eq_attr "setar5" "1")
764 ; (eq_attr "usear5" "1")))
767 ;(define_function_unit "ar5" 1 0
768 ; (and (eq_attr "cpu" "c4x")
769 ; (and (eq_attr "setlda_ar5" "1")
770 ; (eq_attr "usear5" "1")))
773 ;(define_function_unit "ar5" 1 0
774 ; (and (eq_attr "cpu" "c4x")
775 ; (and (eq_attr "usear5" "1")
776 ; (eq_attr "readar5" "1")))
779 (define_attr "setar5" ""
780 (cond [(eq_attr "type" "unary,binary")
781 (if_then_else (match_operand 0 "ar5_reg_operand" "")
782 (const_int 1) (const_int 0))]
785 (define_attr "setlda_ar5" ""
786 (cond [(eq_attr "type" "lda")
787 (if_then_else (match_operand 0 "ar5_reg_operand" "")
788 (const_int 1) (const_int 0))]
791 (define_attr "usear5" ""
792 (cond [(eq_attr "type" "compare,store")
793 (if_then_else (match_operand 0 "ar5_mem_operand" "")
794 (const_int 1) (const_int 0))
795 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
796 (if_then_else (match_operand 1 "ar5_mem_operand" "")
797 (const_int 1) (const_int 0))
798 (eq_attr "type" "binary,binarycc")
799 (if_then_else (match_operand 2 "ar5_mem_operand" "")
800 (const_int 1) (const_int 0))
801 (eq_attr "type" "db,dbc")
802 (if_then_else (match_operand 0 "ar5_reg_operand" "")
803 (const_int 1) (const_int 0))]
806 (define_attr "readar5" ""
807 (cond [(eq_attr "type" "compare")
808 (if_then_else (match_operand 0 "ar5_reg_operand" "")
809 (const_int 1) (const_int 0))
810 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
811 (if_then_else (match_operand 1 "ar5_reg_operand" "")
812 (const_int 1) (const_int 0))
813 (eq_attr "type" "binary,binarycc")
814 (if_then_else (match_operand 2 "ar5_reg_operand" "")
815 (const_int 1) (const_int 0))]
818 ;(define_function_unit "ar6" 1 0
819 ; (and (eq_attr "cpu" "c4x")
820 ; (and (eq_attr "setar6" "1")
821 ; (eq_attr "usear6" "1")))
824 ;(define_function_unit "ar6" 1 0
825 ; (and (eq_attr "cpu" "c4x")
826 ; (and (eq_attr "setlda_ar6" "1")
827 ; (eq_attr "usear6" "1")))
830 ;(define_function_unit "ar6" 1 0
831 ; (and (eq_attr "cpu" "c4x")
832 ; (and (eq_attr "usear6" "1")
833 ; (eq_attr "readar6" "1")))
836 (define_attr "setar6" ""
837 (cond [(eq_attr "type" "unary,binary")
838 (if_then_else (match_operand 0 "ar6_reg_operand" "")
839 (const_int 1) (const_int 0))]
842 (define_attr "setlda_ar6" ""
843 (cond [(eq_attr "type" "lda")
844 (if_then_else (match_operand 0 "ar6_reg_operand" "")
845 (const_int 1) (const_int 0))]
848 (define_attr "usear6" ""
849 (cond [(eq_attr "type" "compare,store")
850 (if_then_else (match_operand 0 "ar6_mem_operand" "")
851 (const_int 1) (const_int 0))
852 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
853 (if_then_else (match_operand 1 "ar6_mem_operand" "")
854 (const_int 1) (const_int 0))
855 (eq_attr "type" "binary,binarycc")
856 (if_then_else (match_operand 2 "ar6_mem_operand" "")
857 (const_int 1) (const_int 0))
858 (eq_attr "type" "db,dbc")
859 (if_then_else (match_operand 0 "ar6_reg_operand" "")
860 (const_int 1) (const_int 0))]
863 (define_attr "readar6" ""
864 (cond [(eq_attr "type" "compare")
865 (if_then_else (match_operand 0 "ar6_reg_operand" "")
866 (const_int 1) (const_int 0))
867 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
868 (if_then_else (match_operand 1 "ar6_reg_operand" "")
869 (const_int 1) (const_int 0))
870 (eq_attr "type" "binary,binarycc")
871 (if_then_else (match_operand 2 "ar6_reg_operand" "")
872 (const_int 1) (const_int 0))]
875 ;(define_function_unit "ar7" 1 0
876 ; (and (eq_attr "cpu" "c4x")
877 ; (and (eq_attr "setar7" "1")
878 ; (eq_attr "usear7" "1")))
881 ;(define_function_unit "ar7" 1 0
882 ; (and (eq_attr "cpu" "c4x")
883 ; (and (eq_attr "setlda_ar7" "1")
884 ; (eq_attr "usear7" "1")))
887 ;(define_function_unit "ar7" 1 0
888 ; (and (eq_attr "cpu" "c4x")
889 ; (and (eq_attr "usear7" "1")
890 ; (eq_attr "readar7" "1")))
893 (define_attr "setar7" ""
894 (cond [(eq_attr "type" "unary,binary")
895 (if_then_else (match_operand 0 "ar7_reg_operand" "")
896 (const_int 1) (const_int 0))]
899 (define_attr "setlda_ar7" ""
900 (cond [(eq_attr "type" "lda")
901 (if_then_else (match_operand 0 "ar7_reg_operand" "")
902 (const_int 1) (const_int 0))]
905 (define_attr "usear7" ""
906 (cond [(eq_attr "type" "compare,store")
907 (if_then_else (match_operand 0 "ar7_mem_operand" "")
908 (const_int 1) (const_int 0))
909 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
910 (if_then_else (match_operand 1 "ar7_mem_operand" "")
911 (const_int 1) (const_int 0))
912 (eq_attr "type" "binary,binarycc")
913 (if_then_else (match_operand 2 "ar7_mem_operand" "")
914 (const_int 1) (const_int 0))
915 (eq_attr "type" "db,dbc")
916 (if_then_else (match_operand 0 "ar7_reg_operand" "")
917 (const_int 1) (const_int 0))]
920 (define_attr "readar7" ""
921 (cond [(eq_attr "type" "compare")
922 (if_then_else (match_operand 0 "ar7_reg_operand" "")
923 (const_int 1) (const_int 0))
924 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
925 (if_then_else (match_operand 1 "ar7_reg_operand" "")
926 (const_int 1) (const_int 0))
927 (eq_attr "type" "binary,binarycc")
928 (if_then_else (match_operand 2 "ar7_reg_operand" "")
929 (const_int 1) (const_int 0))]
932 ;(define_function_unit "ir0" 1 0
933 ; (and (eq_attr "cpu" "c4x")
934 ; (and (eq_attr "setir0" "1")
935 ; (eq_attr "useir0" "1")))
938 ;(define_function_unit "ir0" 1 0
939 ; (and (eq_attr "cpu" "c4x")
940 ; (and (eq_attr "setlda_ir0" "1")
941 ; (eq_attr "useir0" "1")))
944 (define_attr "setir0" ""
945 (cond [(eq_attr "type" "unary,binary")
946 (if_then_else (match_operand 0 "ir0_reg_operand" "")
947 (const_int 1) (const_int 0))]
950 (define_attr "setlda_ir0" ""
951 (cond [(eq_attr "type" "lda")
952 (if_then_else (match_operand 0 "ir0_reg_operand" "")
953 (const_int 1) (const_int 0))]
956 (define_attr "useir0" ""
957 (cond [(eq_attr "type" "compare,store")
958 (if_then_else (match_operand 0 "ir0_mem_operand" "")
959 (const_int 1) (const_int 0))
960 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
961 (if_then_else (match_operand 1 "ir0_mem_operand" "")
962 (const_int 1) (const_int 0))
963 (eq_attr "type" "binary,binarycc")
964 (if_then_else (match_operand 2 "ir0_mem_operand" "")
965 (const_int 1) (const_int 0))]
968 ;(define_function_unit "ir1" 1 0
969 ; (and (eq_attr "cpu" "c4x")
970 ; (and (eq_attr "setir1" "1")
971 ; (eq_attr "useir1" "1")))
974 ;(define_function_unit "ir1" 1 0
975 ; (and (eq_attr "cpu" "c4x")
976 ; (and (eq_attr "setlda_ir1" "1")
977 ; (eq_attr "useir1" "1")))
980 (define_attr "setir1" ""
981 (cond [(eq_attr "type" "unary,binary")
982 (if_then_else (match_operand 0 "ir1_reg_operand" "")
983 (const_int 1) (const_int 0))]
986 (define_attr "setlda_ir1" ""
987 (cond [(eq_attr "type" "lda")
988 (if_then_else (match_operand 0 "ir1_reg_operand" "")
989 (const_int 1) (const_int 0))]
992 (define_attr "useir1" ""
993 (cond [(eq_attr "type" "compare,store")
994 (if_then_else (match_operand 0 "ir1_mem_operand" "")
995 (const_int 1) (const_int 0))
996 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
997 (if_then_else (match_operand 1 "ir1_mem_operand" "")
998 (const_int 1) (const_int 0))
999 (eq_attr "type" "binary,binarycc")
1000 (if_then_else (match_operand 2 "ir1_mem_operand" "")
1001 (const_int 1) (const_int 0))]
1004 ; With the C3x, things are simpler, but slower, i.e. more pipeline conflicts :(
1005 ; There are three functional groups:
1006 ; (1) AR0-AR7, IR0-IR1, BK
1010 ; When a register in one of these functional groups is loaded,
1011 ; the contents of that or any other register in its group
1012 ; will not be available to the next instruction for 2 machine cycles.
1013 ; Similarly, when a register in one of the functional groups is read
1014 ; excepting (IR0-IR1, BK, DP) the contents of that or any other register
1015 ; in its group will not be available to the next instruction for
1018 ; Let's ignore functional groups 2 and 3 for now, since they are not
1021 ;(define_function_unit "group1" 1 0
1022 ; (and (eq_attr "cpu" "c3x")
1023 ; (and (eq_attr "setgroup1" "1")
1024 ; (eq_attr "usegroup1" "1")))
1027 ;(define_function_unit "group1" 1 0
1028 ; (and (eq_attr "cpu" "c3x")
1029 ; (and (eq_attr "usegroup1" "1")
1030 ; (eq_attr "readarx" "1")))
1033 (define_attr "setgroup1" ""
1034 (cond [(eq_attr "type" "lda,unary,binary")
1035 (if_then_else (match_operand 0 "group1_reg_operand" "")
1036 (const_int 1) (const_int 0))]
1039 (define_attr "usegroup1" ""
1040 (cond [(eq_attr "type" "compare,store,store_store,store_load")
1041 (if_then_else (match_operand 0 "group1_mem_operand" "")
1042 (const_int 1) (const_int 0))
1043 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc,load_load,load_store")
1044 (if_then_else (match_operand 1 "group1_mem_operand" "")
1045 (const_int 1) (const_int 0))
1046 (eq_attr "type" "store_store,load_store")
1047 (if_then_else (match_operand 2 "group1_mem_operand" "")
1048 (const_int 1) (const_int 0))
1049 (eq_attr "type" "load_load,store_load")
1050 (if_then_else (match_operand 3 "group1_mem_operand" "")
1051 (const_int 1) (const_int 0))]
1054 (define_attr "readarx" ""
1055 (cond [(eq_attr "type" "compare")
1056 (if_then_else (match_operand 0 "arx_reg_operand" "")
1057 (const_int 1) (const_int 0))
1058 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
1059 (if_then_else (match_operand 1 "arx_reg_operand" "")
1060 (const_int 1) (const_int 0))
1061 (eq_attr "type" "binary,binarycc")
1062 (if_then_else (match_operand 2 "arx_reg_operand" "")
1063 (const_int 1) (const_int 0))]
1067 ; TWO OPERAND INTEGER INSTRUCTIONS
1073 (define_insn "set_ldp"
1074 [(set (match_operand:QI 0 "dp_reg_operand" "=z")
1075 (high:QI (match_operand:QI 1 "" "")))]
1077 "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
1078 [(set_attr "type" "ldp")])
1081 ; Used when moving a constant label reference to an external
1082 ; location, this will make sure the original label is still
1083 ; used so the optimizer will not optimize it away.
1085 (define_insn "set_ldp_use"
1086 [(parallel [(set (match_operand:QI 0 "dp_reg_operand" "=z")
1087 (high:QI (match_operand:QI 1 "" "")))
1088 (use (match_operand 2 "" ""))])]
1090 "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
1091 [(set_attr "type" "ldp")])
1093 (define_insn "set_high_use"
1094 [(parallel [(set (match_operand:QI 0 "std_reg_operand" "=c")
1095 (high:QI (match_operand:QI 1 "" "")))
1096 (use (match_operand 2 "" ""))])]
1097 "!TARGET_C3X && !TARGET_SMALL"
1099 [(set_attr "type" "unary")])
1101 (define_insn "set_ior_lo_use"
1102 [(parallel [(set (match_operand:QI 0 "std_reg_operand" "=c")
1103 (ior:QI (match_dup 0)
1104 (and:QI (match_operand:QI 1 "" "")
1105 (const_int 65535))))
1106 (use (match_operand 2 "" ""))])]
1107 "!TARGET_C3X && !TARGET_SMALL"
1109 [(set_attr "type" "unary")])
1113 ; The following moves will not set the condition codes register.
1116 ; This must come before the general case
1117 (define_insn "*movqi_stik"
1118 [(set (match_operand:QI 0 "memory_operand" "=m")
1119 (match_operand:QI 1 "stik_const_operand" "K"))]
1122 [(set_attr "type" "store")])
1124 ; We must provide an alternative to store to memory in case we have to
1126 (define_insn "movqi_noclobber"
1127 [(set (match_operand:QI 0 "src_operand" "=d,*c,m,r")
1128 (match_operand:QI 1 "src_hi_operand" "rmI,rmI,r,O"))]
1129 "reg_operand (operands[0], QImode)
1130 || reg_operand (operands[1], QImode)"
1132 if (which_alternative == 2)
1133 return \"sti\\t%1,%0\";
1135 if (!TARGET_C3X && which_alternative == 3)
1137 operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
1138 return \"ldhi\\t%1,%0\";
1141 /* The lda instruction cannot use the same register as source
1143 if (!TARGET_C3X && which_alternative == 1
1144 && ( IS_ADDR_REG (REGNO (operands[0]))
1145 || IS_INDEX_REG (REGNO (operands[0]))
1146 || IS_SP_REG (REGNO (operands[0])))
1147 && (REGNO (operands[0]) != REGNO (operands[1])))
1148 return \"lda\\t%1,%0\";
1149 return \"ldiu\\t%1,%0\";
1151 [(set_attr "type" "unary,lda,store,unary")
1152 (set_attr "data" "int16,int16,int16,high_16")])
1158 ; We shouldn't need these peepholes, but the combiner seems to miss them...
1160 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1161 (match_operand:QI 1 "src_operand" "g"))
1163 (compare:CC (match_dup 0) (const_int 0)))]
1167 [(set_attr "type" "unarycc")
1168 (set_attr "data" "int16")])
1170 (define_insn "*movqi_set"
1172 (compare:CC (match_operand:QI 1 "src_operand" "g")
1174 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1179 [(set_attr "type" "unarycc")
1180 (set_attr "data" "int16")])
1182 ; This pattern probably gets in the way and requires a scratch register
1183 ; when a simple compare with zero will suffice.
1184 ;(define_insn "*movqi_test"
1186 ; (compare:CC (match_operand:QI 1 "src_operand" "g")
1188 ; (clobber (match_scratch:QI 0 "=d"))]
1192 ; [(set_attr "type" "unarycc")
1193 ; (set_attr "data" "int16")])
1195 ; If one of the operands is not a register, then we should
1196 ; emit two insns, using a scratch register. This will produce
1197 ; better code in loops if the source operand is invariant, since
1198 ; the source reload can be optimised out. During reload we cannot
1199 ; use change_address or force_reg which will allocate new pseudo regs.
1201 ; Unlike most other insns, the move insns can't be split with
1202 ; different predicates, because register spilling and other parts of
1203 ; the compiler, have memoized the insn number already.
1205 (define_expand "movqi"
1206 [(set (match_operand:QI 0 "src_operand" "")
1207 (match_operand:QI 1 "src_operand" ""))]
1210 /* We shouldn't have to do this, since reload is supposed to
1211 be able to do this if we have a memory constraint. */
1212 if (CONSTANT_P (operands[1])
1213 && !const_operand (operands[1], QImode))
1215 operands[1] = force_const_mem (QImode, operands[1]);
1216 if (!memory_address_p (QImode, XEXP (operands[1], 0))
1217 && !reload_in_progress)
1218 operands[1] = change_address (operands[1], QImode,
1219 XEXP (operands[1], 0));
1222 if (!reload_in_progress
1223 && !reg_operand (operands[0], QImode)
1224 && !reg_operand (operands[1], QImode)
1225 && !(stik_const_operand (operands[1], QImode)
1226 && !push_operand (operands[0], QImode)))
1227 operands[1] = force_reg (QImode, operands[1]);")
1229 (define_insn "*movqi_update"
1230 [(set (match_operand:QI 0 "reg_operand" "=r")
1231 (mem:QI (plus:QI (match_operand:QI 1 "addr_reg_operand" "a")
1232 (match_operand:QI 2 "index_reg_operand" "x"))))
1234 (plus:QI (match_dup 1) (match_dup 2)))]
1236 "ldiu\\t*%1++(%2),%0"
1237 [(set_attr "type" "unary")
1238 (set_attr "data" "int16")])
1240 (define_insn "movqi_parallel"
1241 [(set (match_operand:QI 0 "parallel_operand" "=q,S<>,q,S<>")
1242 (match_operand:QI 1 "parallel_operand" "S<>,q,S<>,q"))
1243 (set (match_operand:QI 2 "parallel_operand" "=q,S<>,S<>,q")
1244 (match_operand:QI 3 "parallel_operand" "S<>,q,q,S<>"))]
1245 "valid_parallel_operands_4 (operands, QImode)"
1247 ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
1248 sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
1249 ldi\\t%1,%0\\n||\\tsti\\t%3,%2
1250 ldi\\t%3,%2\\n||\\tsti\\t%1,%0"
1251 [(set_attr "type" "load_load,store_store,load_store,store_load")])
1256 (define_insn "*pushqi"
1257 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
1258 (match_operand:QI 0 "reg_operand" "r"))]
1261 [(set_attr "type" "push")])
1263 (define_insn "*popqi"
1264 [(set (match_operand:QI 0 "reg_operand" "=r")
1265 (mem:QI (post_dec:QI (reg:QI 20))))
1266 (clobber (reg:CC 21))]
1269 [(set_attr "type" "pop")])
1274 (define_expand "absqi2"
1275 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1276 (abs:QI (match_operand:QI 1 "src_operand" "")))
1277 (clobber (reg:CC_NOOV 21))])]
1281 (define_insn "*absqi2_clobber"
1282 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1283 (abs:QI (match_operand:QI 1 "src_operand" "g,g")))
1284 (clobber (reg:CC_NOOV 21))]
1287 [(set_attr "type" "unarycc,unary")
1288 (set_attr "data" "int16,int16")])
1290 (define_insn "*absqi2_test"
1291 [(set (reg:CC_NOOV 21)
1292 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "g"))
1294 (clobber (match_scratch:QI 0 "=d"))]
1297 [(set_attr "type" "unarycc")
1298 (set_attr "data" "int16")])
1300 (define_insn "*absqi2_set"
1301 [(set (reg:CC_NOOV 21)
1302 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "g"))
1304 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1305 (abs:QI (match_dup 1)))]
1308 [(set_attr "type" "unarycc")
1309 (set_attr "data" "int16")])
1314 (define_expand "negqi2"
1315 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1316 (neg:QI (match_operand:QI 1 "src_operand" "")))
1317 (clobber (reg:CC_NOOV 21))])]
1321 (define_insn "*negqi2_clobber"
1322 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1323 (neg:QI (match_operand:QI 1 "src_operand" "g,g")))
1324 (clobber (reg:CC_NOOV 21))]
1327 [(set_attr "type" "unarycc,unary")
1328 (set_attr "data" "int16,int16")])
1330 (define_insn "*negqi2_test"
1331 [(set (reg:CC_NOOV 21)
1332 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "g"))
1334 (clobber (match_scratch:QI 0 "=d"))]
1337 [(set_attr "type" "unarycc")
1338 (set_attr "data" "int16")])
1340 (define_insn "*negqi2_set"
1341 [(set (reg:CC_NOOV 21)
1342 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "g"))
1344 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1345 (neg:QI (match_dup 1)))]
1348 [(set_attr "type" "unarycc")
1349 (set_attr "data" "int16")])
1351 (define_insn "*negbqi2_clobber"
1352 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1353 (neg:QI (match_operand:QI 1 "src_operand" "g")))
1354 (use (reg:CC_NOOV 21))
1355 (clobber (reg:CC_NOOV 21))]
1358 [(set_attr "type" "unarycc")
1359 (set_attr "data" "int16")])
1364 (define_expand "one_cmplqi2"
1365 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1366 (not:QI (match_operand:QI 1 "lsrc_operand" "")))
1367 (clobber (reg:CC 21))])]
1371 (define_insn "*one_cmplqi2_clobber"
1372 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1373 (not:QI (match_operand:QI 1 "lsrc_operand" "g,g")))
1374 (clobber (reg:CC 21))]
1377 [(set_attr "type" "unarycc,unary")
1378 (set_attr "data" "uint16,uint16")])
1380 (define_insn "*one_cmplqi2_test"
1382 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "g"))
1384 (clobber (match_scratch:QI 0 "=d"))]
1387 [(set_attr "type" "unarycc")
1388 (set_attr "data" "uint16")])
1390 (define_insn "*one_cmplqi2_set"
1392 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "g"))
1394 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1395 (not:QI (match_dup 1)))]
1398 [(set_attr "type" "unarycc")
1399 (set_attr "data" "uint16")])
1401 (define_insn "*one_cmplqi2_const_clobber"
1402 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1403 (match_operand:QI 1 "not_const_operand" "N,N"))
1404 (clobber (reg:CC 21))]
1409 [(set_attr "type" "unarycc,unary")
1410 (set_attr "data" "not_uint16,not_uint16")])
1412 ; movqi can use this for loading an integer that can't normally
1413 ; fit into a 16-bit signed integer. The drawback is that it cannot
1414 ; go into R0-R11 since that will clobber the CC and movqi shouldn't
1415 ; do that. This can cause additional reloading but in most cases
1416 ; this will cause only an additional register move. With the large
1417 ; memory model we require an extra instruction to load DP anyway,
1418 ; if we're loading the constant from memory. The big advantage of
1419 ; allowing constants that satisfy not_const_operand in movqi, is that
1420 ; it allows andn to be generated more often.
1421 ; However, there is a problem if GCC has decided that it wants
1422 ; to use R0-R11, since we won't have a matching pattern...
1423 ; In interim, we prevent immed_const allowing `N' constants.
1424 (define_insn "*one_cmplqi2_const_noclobber"
1425 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1426 (match_operand:QI 1 "not_const_operand" "N"))]
1429 [(set_attr "type" "unary")
1430 (set_attr "data" "not_uint16")])
1435 (define_expand "rotlqi3"
1436 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1437 (rotate:QI (match_operand:QI 1 "reg_operand" "")
1438 (match_operand:QI 2 "const_int_operand" "")))
1439 (clobber (reg:CC 21))])]
1441 "if (INTVAL (operands[2]) >= 4)
1442 FAIL; /* Open code as two shifts and an or */
1443 if (INTVAL (operands[2]) > 1)
1447 /* If we have 4 or fewer shifts, then it is probably faster
1448 to emit separate ROL instructions. A C3x requires
1449 at least 4 instructions (a C4x requires at least 3), to
1450 perform a rotation by shifts. */
1452 for (i = 0; i < INTVAL (operands[2]); i++)
1453 emit_insn (gen_rotl_1_clobber (operands[0], operands[1]));
1457 (define_insn "rotl_1_clobber"
1458 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1459 (rotate:QI (match_operand:QI 1 "reg_operand" "0,0")
1461 (clobber (reg:CC 21))]
1464 [(set_attr "type" "unarycc,unary")])
1465 ; Default to int16 data attr.
1470 (define_expand "rotrqi3"
1471 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1472 (rotatert:QI (match_operand:QI 1 "reg_operand" "")
1473 (match_operand:QI 2 "const_int_operand" "")))
1474 (clobber (reg:CC 21))])]
1476 "if (INTVAL (operands[2]) >= 4)
1477 FAIL; /* Open code as two shifts and an or */
1478 if (INTVAL (operands[2]) > 1)
1482 /* If we have 4 or fewer shifts, then it is probably faster
1483 to emit separate ROL instructions. A C3x requires
1484 at least 4 instructions (a C4x requires at least 3), to
1485 perform a rotation by shifts. */
1487 for (i = 0; i < INTVAL (operands[2]); i++)
1488 emit_insn (gen_rotr_1_clobber (operands[0], operands[1]));
1492 (define_insn "rotr_1_clobber"
1493 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1494 (rotatert:QI (match_operand:QI 1 "reg_operand" "0,0")
1496 (clobber (reg:CC 21))]
1499 [(set_attr "type" "unarycc,unary")])
1500 ; Default to int16 data attr.
1504 ; THREE OPERAND INTEGER INSTRUCTIONS
1510 ; This is used by reload when it calls gen_add2_insn for address arithmetic
1511 ; so we must emit the pattern that doesn't clobber CC.
1513 (define_expand "addqi3"
1514 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1515 (plus:QI (match_operand:QI 1 "src_operand" "")
1516 (match_operand:QI 2 "src_operand" "")))
1517 (clobber (reg:CC_NOOV 21))])]
1519 "legitimize_operands (PLUS, operands, QImode);
1520 if (reload_in_progress)
1522 emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
1526 (define_insn "*addqi3_clobber"
1527 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
1528 (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
1529 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
1530 (clobber (reg:CC_NOOV 21))]
1531 "valid_operands (PLUS, operands, QImode)"
1539 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1540 ; Default to int16 data attr.
1542 (define_insn "*addqi3_test"
1543 [(set (reg:CC_NOOV 21)
1544 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1545 (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
1547 (clobber (match_scratch:QI 0 "=d,?d,d"))]
1548 "valid_operands (PLUS, operands, QImode)"
1553 [(set_attr "type" "binarycc,binarycc,binarycc")])
1554 ; Default to int16 data attr.
1556 ; gcc does this in combine.c we just reverse it here
1557 (define_insn "*cmp_neg"
1558 [(set (reg:CC_NOOV 21)
1559 (compare:CC_NOOV (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1560 (neg: QI (match_operand:QI 2 "src_operand" "JR,rS<>,g"))))
1561 (clobber (match_scratch:QI 0 "=d,?d,d"))]
1562 "valid_operands (PLUS, operands, QImode)"
1567 [(set_attr "type" "binarycc,binarycc,binarycc")])
1570 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
1571 (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1572 (match_operand:QI 2 "src_operand" "JR,rS<>,g")))
1573 (clobber (reg:CC_NOOV 21))])
1574 (set (reg:CC_NOOV 21)
1575 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1576 "valid_operands (PLUS, operands, QImode)"
1581 [(set_attr "type" "binarycc,binarycc,binarycc")])
1583 (define_insn "*addqi3_set"
1584 [(set (reg:CC_NOOV 21)
1585 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1586 (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
1588 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
1589 (plus:QI (match_dup 1) (match_dup 2)))]
1590 "valid_operands (PLUS, operands, QImode)"
1595 [(set_attr "type" "binarycc,binarycc,binarycc")])
1596 ; Default to int16 data attr.
1598 ; This pattern is required primarily for manipulating the stack pointer
1599 ; where GCC doesn't expect CC to be clobbered.
1600 (define_insn "addqi3_noclobber"
1601 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c,c")
1602 (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1603 (match_operand:QI 2 "src_operand" "JR,rS<>,g")))]
1604 "valid_operands (PLUS, operands, QImode)"
1609 [(set_attr "type" "binary,binary,binary")])
1610 ; Default to int16 data attr.
1613 (define_insn "*addqi3_carry_clobber"
1614 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
1615 (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
1616 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
1617 (use (reg:CC_NOOV 21))
1618 (clobber (reg:CC_NOOV 21))]
1619 "valid_operands (PLUS, operands, QImode)"
1627 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1628 ; Default to int16 data attr.
1634 (define_expand "subqi3"
1635 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1636 (minus:QI (match_operand:QI 1 "src_operand" "")
1637 (match_operand:QI 2 "src_operand" "")))
1638 (clobber (reg:CC_NOOV 21))])]
1640 "legitimize_operands (MINUS, operands, QImode);")
1642 (define_insn "*subqi3_clobber"
1643 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
1644 (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g,rR,rS<>,0,g")
1645 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0,JR,rS<>,g,0")))
1646 (clobber (reg:CC_NOOV 21))]
1647 "valid_operands (MINUS, operands, QImode)"
1657 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
1658 ; Default to int16 data attr.
1660 (define_insn "*subqi3_test"
1661 [(set (reg:CC_NOOV 21)
1662 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
1663 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
1665 (clobber (match_scratch:QI 0 "=d,?d,d,d"))]
1666 "valid_operands (MINUS, operands, QImode)"
1672 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1673 ; Default to int16 data attr.
1676 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
1677 (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
1678 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0")))
1679 (clobber (reg:CC_NOOV 21))])
1680 (set (reg:CC_NOOV 21)
1681 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1682 "valid_operands (MINUS, operands, QImode)"
1688 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1690 (define_insn "*subqi3_set"
1691 [(set (reg:CC_NOOV 21)
1692 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
1693 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
1695 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
1696 (minus:QI (match_dup 1)
1698 "valid_operands (MINUS, operands, QImode)"
1704 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1705 ; Default to int16 data attr.
1707 (define_insn "*subqi3_carry_clobber"
1708 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
1709 (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g,rR,rS<>,0,g")
1710 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0,JR,rS<>,g,0")))
1711 (use (reg:CC_NOOV 21))
1712 (clobber (reg:CC_NOOV 21))]
1713 "valid_operands (MINUS, operands, QImode)"
1723 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
1724 ; Default to int16 data attr.
1726 (define_insn "*subqi3_carry_set"
1727 [(set (reg:CC_NOOV 21)
1728 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
1729 (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
1731 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
1732 (minus:QI (match_dup 1)
1734 (use (reg:CC_NOOV 21))]
1735 "valid_operands (MINUS, operands, QImode)"
1741 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1742 ; Default to int16 data attr.
1747 (define_expand "mulqi3"
1748 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1749 (mult:QI (match_operand:QI 1 "src_operand" "")
1750 (match_operand:QI 2 "src_operand" "")))
1751 (clobber (reg:CC_NOOV 21))])]
1753 "if (TARGET_MPYI || (GET_CODE (operands[2]) == CONST_INT
1754 && exact_log2 (INTVAL (operands[2])) >= 0))
1755 legitimize_operands (MULT, operands, QImode);
1758 if (GET_CODE (operands[2]) == CONST_INT)
1760 /* Let GCC try to synthesise the multiplication using shifts
1761 and adds. In most cases this will be more profitable than
1762 using the C3x MPYI. */
1765 if (operands[1] == operands[2])
1767 /* Do the squaring operation in-line. */
1768 emit_insn (gen_sqrqi2_inline(operands[0], operands[1]));
1773 emit_insn (gen_mulqi3_inline(operands[0], operands[1],
1777 c4x_emit_libcall3 (MULQI3_LIBCALL, MULT, QImode, operands);
1782 (define_insn "*mulqi3_clobber"
1783 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
1784 (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
1785 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
1786 (clobber (reg:CC_NOOV 21))]
1787 "valid_operands (MULT, operands, QImode)"
1789 if (which_alternative == 2 || which_alternative == 5)
1792 && GET_CODE (operands[2]) == CONST_INT
1793 && exact_log2 (INTVAL (operands[2])) >= 0)
1794 return \"ash\\t%L2,%0\";
1796 return \"mpyi\\t%2,%0\";
1799 return \"mpyi3\\t%2,%1,%0\";"
1800 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1801 ; Default to int16 data attr.
1803 (define_insn "*mulqi3_test"
1804 [(set (reg:CC_NOOV 21)
1805 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1806 (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
1808 (clobber (match_scratch:QI 0 "=d,?d,d"))]
1809 "valid_operands (MULT, operands, QImode)"
1811 if (which_alternative == 2)
1814 && GET_CODE (operands[2]) == CONST_INT
1815 && exact_log2 (INTVAL (operands[2])) >= 0)
1816 return \"ash\\t%L2,%0\";
1818 return \"mpyi\\t%2,%0\";
1821 return \"mpyi3\\t%2,%1,%0\";"
1822 [(set_attr "type" "binarycc,binarycc,binarycc")])
1823 ; Default to int16 data attr.
1825 (define_insn "*mulqi3_set"
1826 [(set (reg:CC_NOOV 21)
1827 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
1828 (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
1830 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
1831 (mult:QI (match_dup 1)
1833 "valid_operands (MULT, operands, QImode)"
1835 if (which_alternative == 2)
1838 && GET_CODE (operands[2]) == CONST_INT
1839 && exact_log2 (INTVAL (operands[2])) >= 0)
1840 return \"ash\\t%L2,%0\";
1842 return \"mpyi\\t%2,%0\";
1845 return \"mpyi3\\t%2,%1,%0\";"
1846 [(set_attr "type" "binarycc,binarycc,binarycc")])
1847 ; Default to int16 data attr.
1849 ; The C3x multiply instruction assumes 24-bit signed integer operands
1850 ; and the 48-bit result is truncated to 32-bits.
1851 (define_insn "*mulqi3_24_clobber"
1852 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
1855 (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
1856 (const_int 16777215)))
1858 (and:QI (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")
1859 (const_int 16777215)))))
1860 (clobber (reg:CC_NOOV 21))]
1861 "TARGET_C3X && valid_operands (MULT, operands, QImode)"
1869 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1870 ; Default to int16 data attr.
1873 ; Fast square function for C3x where TARGET_MPYI not asserted
1874 (define_expand "sqrqi2_inline"
1875 [(set (match_dup 7) (match_operand:QI 1 "src_operand" ""))
1876 (parallel [(set (match_dup 3)
1877 (lshiftrt:QI (match_dup 7) (const_int 16)))
1878 (clobber (reg:CC 21))])
1879 (parallel [(set (match_dup 2)
1880 (and:QI (match_dup 7) (const_int 65535)))
1881 (clobber (reg:CC 21))])
1882 (parallel [(set (match_dup 4)
1883 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
1884 (const_int 16777215)))
1885 (sign_extend:QI (and:QI (match_dup 2)
1886 (const_int 16777215)))))
1887 (clobber (reg:CC_NOOV 21))])
1888 (parallel [(set (match_dup 5)
1889 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
1890 (const_int 16777215)))
1891 (sign_extend:QI (and:QI (match_dup 3)
1892 (const_int 16777215)))))
1893 (clobber (reg:CC_NOOV 21))])
1894 (parallel [(set (match_dup 6)
1895 (ashift:QI (match_dup 5) (const_int 17)))
1896 (clobber (reg:CC 21))])
1897 (parallel [(set (match_operand:QI 0 "reg_operand" "")
1898 (plus:QI (match_dup 4) (match_dup 6)))
1899 (clobber (reg:CC_NOOV 21))])]
1902 operands[2] = gen_reg_rtx (QImode); /* a = val & 0xffff */
1903 operands[3] = gen_reg_rtx (QImode); /* b = val >> 16 */
1904 operands[4] = gen_reg_rtx (QImode); /* a * a */
1905 operands[5] = gen_reg_rtx (QImode); /* a * b */
1906 operands[6] = gen_reg_rtx (QImode); /* (a * b) << 17 */
1907 operands[7] = gen_reg_rtx (QImode); /* val */
1910 ; Inlined integer multiply for C3x
1911 (define_expand "mulqi3_inline"
1912 [(set (match_dup 12) (const_int -16))
1913 (set (match_dup 13) (match_operand:QI 1 "src_operand" ""))
1914 (set (match_dup 14) (match_operand:QI 2 "src_operand" ""))
1915 (parallel [(set (match_dup 4)
1916 (lshiftrt:QI (match_dup 13) (neg:QI (match_dup 12))))
1917 (clobber (reg:CC 21))])
1918 (parallel [(set (match_dup 6)
1919 (lshiftrt:QI (match_dup 14) (neg:QI (match_dup 12))))
1920 (clobber (reg:CC 21))])
1921 (parallel [(set (match_dup 3)
1922 (and:QI (match_dup 13)
1924 (clobber (reg:CC 21))])
1925 (parallel [(set (match_dup 5)
1926 (and:QI (match_dup 14)
1928 (clobber (reg:CC 21))])
1929 (parallel [(set (match_dup 7)
1930 (mult:QI (sign_extend:QI (and:QI (match_dup 4)
1931 (const_int 16777215)))
1932 (sign_extend:QI (and:QI (match_dup 5)
1933 (const_int 16777215)))))
1934 (clobber (reg:CC_NOOV 21))])
1935 (parallel [(set (match_dup 8)
1936 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
1937 (const_int 16777215)))
1938 (sign_extend:QI (and:QI (match_dup 5)
1939 (const_int 16777215)))))
1940 (clobber (reg:CC_NOOV 21))])
1941 (parallel [(set (match_dup 9)
1942 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
1943 (const_int 16777215)))
1944 (sign_extend:QI (and:QI (match_dup 6)
1945 (const_int 16777215)))))
1946 (clobber (reg:CC_NOOV 21))])
1947 (parallel [(set (match_dup 10)
1948 (plus:QI (match_dup 7) (match_dup 9)))
1949 (clobber (reg:CC_NOOV 21))])
1950 (parallel [(set (match_dup 11)
1951 (ashift:QI (match_dup 10) (const_int 16)))
1952 (clobber (reg:CC 21))])
1953 (parallel [(set (match_operand:QI 0 "reg_operand" "")
1954 (plus:QI (match_dup 8) (match_dup 11)))
1955 (clobber (reg:CC_NOOV 21))])]
1958 operands[3] = gen_reg_rtx (QImode); /* a = arg1 & 0xffff */
1959 operands[4] = gen_reg_rtx (QImode); /* b = arg1 >> 16 */
1960 operands[5] = gen_reg_rtx (QImode); /* a = arg2 & 0xffff */
1961 operands[6] = gen_reg_rtx (QImode); /* b = arg2 >> 16 */
1962 operands[7] = gen_reg_rtx (QImode); /* b * c */
1963 operands[8] = gen_reg_rtx (QImode); /* a * c */
1964 operands[9] = gen_reg_rtx (QImode); /* a * d */
1965 operands[10] = gen_reg_rtx (QImode); /* b * c + a * d */
1966 operands[11] = gen_reg_rtx (QImode); /* (b *c + a * d) << 16 */
1967 operands[12] = gen_reg_rtx (QImode); /* -16 */
1968 operands[13] = gen_reg_rtx (QImode); /* arg1 */
1969 operands[14] = gen_reg_rtx (QImode); /* arg2 */
1975 (define_expand "smulqi3_highpart"
1976 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1980 (sign_extend:HI (match_operand:QI 1 "src_operand" ""))
1981 (sign_extend:HI (match_operand:QI 2 "src_operand" "")))
1983 (clobber (reg:CC_NOOV 21))])]
1985 "legitimize_operands (MULT, operands, QImode);
1988 c4x_emit_libcall_mulhi (SMULHI3_LIBCALL, SIGN_EXTEND, QImode, operands);
1993 (define_insn "*smulqi3_highpart_clobber"
1994 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
1998 (sign_extend:HI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0"))
1999 (sign_extend:HI (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
2001 (clobber (reg:CC_NOOV 21))]
2002 "!TARGET_C3X && valid_operands (MULT, operands, QImode)"
2010 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2011 (set_attr "data" "int16,int16,int16,int16,int16,int16")])
2016 (define_expand "umulqi3_highpart"
2017 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2021 (zero_extend:HI (match_operand:QI 1 "src_operand" ""))
2022 (zero_extend:HI (match_operand:QI 2 "lsrc_operand" "")))
2024 (clobber (reg:CC_NOOV 21))])]
2026 "legitimize_operands (MULT, operands, QImode);
2029 c4x_emit_libcall_mulhi (UMULHI3_LIBCALL, ZERO_EXTEND, QImode, operands);
2034 (define_insn "*umulqi3_highpart_clobber"
2035 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2039 (zero_extend:HI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0"))
2040 (zero_extend:HI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,g,JR,rS<>,g")))
2042 (clobber (reg:CC_NOOV 21))]
2043 "!TARGET_C3X && valid_operands (MULT, operands, QImode)"
2051 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2052 (set_attr "data" "uint16,uint16,uint16,uint16,uint16,uint16")])
2057 (define_expand "andqi3"
2058 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2059 (and:QI (match_operand:QI 1 "src_operand" "")
2060 (match_operand:QI 2 "tsrc_operand" "")))
2061 (clobber (reg:CC 21))])]
2063 "legitimize_operands (AND, operands, QImode);")
2065 (define_insn "*andqi3_clobber"
2066 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
2067 (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0,rR,rS<>,0,0")
2068 (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm,JR,rS<>,N,rLm")))
2069 (clobber (reg:CC 21))]
2070 "valid_operands (AND, operands, QImode)"
2080 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")
2081 (set_attr "data" "int16,uint16,not_uint16,uint16,int16,uint16,not_uint16,uint16")])
2083 (define_insn "*andqi3_test"
2085 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,r")
2086 (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm"))
2088 (clobber (match_scratch:QI 0 "=X,X,d,X"))]
2089 "valid_operands (AND, operands, QImode)"
2095 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2096 (set_attr "data" "int16,uint16,not_uint16,uint16")])
2099 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
2100 (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0")
2101 (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm")))
2102 (clobber (reg:CC 21))])
2104 (compare:CC (match_dup 0) (const_int 0)))]
2105 "valid_operands (AND, operands, QImode)"
2111 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2112 (set_attr "data" "int16,uint16,not_uint16,uint16")])
2114 (define_insn "*andqi3_set"
2116 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0")
2117 (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm"))
2119 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
2120 (and:QI (match_dup 1)
2122 "valid_operands (AND, operands, QImode)"
2128 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2129 (set_attr "data" "int16,uint16,not_uint16,uint16")])
2134 ; NB, this insn doesn't have commutative operands, but valid_operands
2135 ; assumes that the code AND does. We might have to kludge this if
2136 ; we make valid_operands stricter.
2137 (define_insn "*andnqi3_clobber"
2138 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2139 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm"))
2140 (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")))
2141 (clobber (reg:CC 21))]
2142 "valid_operands (AND, operands, QImode)"
2150 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2151 (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
2153 (define_insn "*andnqi3_test"
2155 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2156 (match_operand:QI 1 "src_operand" "rR,rS<>,0"))
2158 (clobber (match_scratch:QI 0 "=d,?d,d"))]
2159 "valid_operands (AND, operands, QImode)"
2164 [(set_attr "type" "binarycc,binarycc,binarycc")
2165 (set_attr "data" "int16,uint16,uint16")])
2167 (define_insn "*andnqi3_set"
2169 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2170 (match_operand:QI 1 "src_operand" "rR,rS<>,0"))
2172 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
2173 (and:QI (not:QI (match_dup 2))
2175 "valid_operands (AND, operands, QImode)"
2180 [(set_attr "type" "binarycc,binarycc,binarycc")
2181 (set_attr "data" "int16,uint16,uint16")])
2186 (define_expand "iorqi3"
2187 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2188 (ior:QI (match_operand:QI 1 "src_operand" "")
2189 (match_operand:QI 2 "lsrc_operand" "")))
2190 (clobber (reg:CC 21))])]
2192 "legitimize_operands (IOR, operands, QImode);")
2194 (define_insn "*iorqi3_clobber"
2195 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2196 (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
2197 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm")))
2198 (clobber (reg:CC 21))]
2199 "valid_operands (IOR, operands, QImode)"
2207 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2208 (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
2210 (define_insn "*iorqi3_test"
2212 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2213 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2215 (clobber (match_scratch:QI 0 "=d,?d,d"))]
2216 "valid_operands (IOR, operands, QImode)"
2221 [(set_attr "type" "binarycc,binarycc,binarycc")
2222 (set_attr "data" "int16,uint16,uint16")])
2225 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
2226 (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2227 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm")))
2228 (clobber (reg:CC 21))])
2230 (compare:CC (match_dup 0) (const_int 0)))]
2231 "valid_operands (IOR, operands, QImode)"
2236 [(set_attr "type" "binarycc,binarycc,binarycc")
2237 (set_attr "data" "int16,uint16,uint16")])
2239 (define_insn "*iorqi3_set"
2241 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2242 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2244 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
2245 (ior:QI (match_dup 1)
2247 "valid_operands (IOR, operands, QImode)"
2252 [(set_attr "type" "binarycc,binarycc,binarycc")
2253 (set_attr "data" "int16,uint16,uint16")])
2255 ; This pattern is used for loading symbol references in several parts.
2256 (define_insn "iorqi3_noclobber"
2257 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c,c")
2258 (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2259 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm")))]
2260 "valid_operands (IOR, operands, QImode)"
2265 [(set_attr "type" "binary,binary,binary")
2266 (set_attr "data" "int16,uint16,uint16")])
2271 (define_expand "xorqi3"
2272 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2273 (xor:QI (match_operand:QI 1 "src_operand" "")
2274 (match_operand:QI 2 "lsrc_operand" "")))
2275 (clobber (reg:CC 21))])]
2277 "legitimize_operands (XOR, operands, QImode);")
2279 (define_insn "*xorqi3_clobber"
2280 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2281 (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
2282 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm")))
2283 (clobber (reg:CC 21))]
2284 "valid_operands (XOR, operands, QImode)"
2292 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2293 (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
2295 (define_insn "*xorqi3_test"
2297 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2298 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2300 (clobber (match_scratch:QI 0 "=d,?d,d"))]
2301 "valid_operands (XOR, operands, QImode)"
2306 [(set_attr "type" "binarycc,binarycc,binarycc")
2307 (set_attr "data" "int16,uint16,uint16")])
2309 (define_insn "*xorqi3_set"
2311 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
2312 (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
2314 (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
2315 (xor:QI (match_dup 1)
2317 "valid_operands (XOR, operands, QImode)"
2322 [(set_attr "type" "binarycc,binarycc,binarycc")
2323 (set_attr "data" "int16,uint16,uint16")])
2328 ; The C3x and C4x have two shift instructions ASH and LSH
2329 ; If the shift count is positive, a left shift is performed
2330 ; otherwise a right shift is performed. The number of bits
2331 ; shifted is determined by the seven LSBs of the shift count.
2332 ; If the absolute value of the count is 32 or greater, the result
2333 ; using the LSH instruction is zero; with the ASH insn the result
2334 ; is zero or negative 1. Note that the ISO C standard allows
2335 ; the result to be machine dependent whenever the shift count
2336 ; exceeds the size of the object.
2337 (define_expand "ashlqi3"
2338 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2339 (ashift:QI (match_operand:QI 1 "src_operand" "")
2340 (match_operand:QI 2 "src_operand" "")))
2341 (clobber (reg:CC 21))])]
2343 "legitimize_operands (ASHIFT, operands, QImode);")
2345 (define_insn "*ashlqi3_clobber"
2346 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2347 (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
2348 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
2349 (clobber (reg:CC 21))]
2350 "valid_operands (ASHIFT, operands, QImode)"
2358 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2359 ; Default to int16 data attr.
2361 (define_insn "*ashlqi3_set"
2364 (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0")
2365 (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
2367 (set (match_operand:QI 0 "reg_operand" "=d,?d,d")
2368 (ashift:QI (match_dup 1)
2370 "valid_operands (ASHIFT, operands, QImode)"
2375 [(set_attr "type" "binarycc,binarycc,binarycc")])
2376 ; Default to int16 data attr.
2378 ; This is only used by lshrhi3_reg where we need a LSH insn that will
2380 (define_insn "*lshlqi3_clobber"
2381 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2382 (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
2383 (unspec [(match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")] 3)))
2384 (clobber (reg:CC 21))]
2385 "valid_operands (ASHIFT, operands, QImode)"
2393 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2394 ; Default to int16 data attr.
2399 ; Logical right shift on the C[34]x works by negating the shift count,
2400 ; then emitting a right shift with the shift count negated. This means
2401 ; that all actual shift counts in the RTL will be positive.
2403 (define_expand "lshrqi3"
2404 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2405 (lshiftrt:QI (match_operand:QI 1 "src_operand" "")
2406 (match_operand:QI 2 "src_operand" "")))
2407 (clobber (reg:CC 21))])]
2409 "legitimize_operands (LSHIFTRT, operands, QImode);")
2411 ; When the shift count is greater than the size of the word
2412 ; the result can be implementation specific
2413 (define_insn "*lshrqi3_const_clobber"
2414 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
2415 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
2416 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
2417 (clobber (reg:CC 21))]
2418 "valid_operands (LSHIFTRT, operands, QImode)"
2424 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2426 ; When the shift count is greater than the size of the word
2427 ; the result can be implementation specific
2428 (define_insn "*lshrqi3_const_set"
2431 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
2432 (match_operand:QI 2 "const_int_operand" "n,n,J,J"))
2434 (set (match_operand:QI 0 "reg_operand" "=?d,?c,d,c")
2435 (lshiftrt:QI (match_dup 1)
2437 "valid_operands (LSHIFTRT, operands, QImode)"
2443 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2445 (define_insn "*lshrqi3_nonconst_clobber"
2446 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2447 (lshiftrt:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
2448 (neg:QI (match_operand:QI 2 "src_operand" "R,rS<>,rm,R,rS<>,rm"))))
2449 (clobber (reg:CC 21))]
2450 "valid_operands (LSHIFTRT, operands, QImode)"
2458 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2459 ; Default to int16 data attr.
2464 ; Arithmetic right shift on the C[34]x works by negating the shift count,
2465 ; then emitting a right shift with the shift count negated. This means
2466 ; that all actual shift counts in the RTL will be positive.
2468 (define_expand "ashrqi3"
2469 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2470 (ashiftrt:QI (match_operand:QI 1 "src_operand" "")
2471 (match_operand:QI 2 "src_operand" "")))
2472 (clobber (reg:CC 21))])]
2474 "legitimize_operands (ASHIFTRT, operands, QImode);")
2476 ; When the shift count is greater than the size of the word
2477 ; the result can be implementation specific
2478 (define_insn "*ashrqi3_const_clobber"
2479 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
2480 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
2481 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
2482 (clobber (reg:CC 21))]
2483 "valid_operands (ASHIFTRT, operands, QImode)"
2489 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2491 ; When the shift count is greater than the size of the word
2492 ; the result can be implementation specific
2493 (define_insn "*ashrqi3_const_set"
2496 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
2497 (match_operand:QI 2 "const_int_operand" "n,J"))
2499 (set (match_operand:QI 0 "reg_operand" "=?d,d")
2500 (ashiftrt:QI (match_dup 1)
2502 "valid_operands (ASHIFTRT, operands, QImode)"
2506 [(set_attr "type" "binarycc,binarycc")])
2508 (define_insn "*ashrqi3_nonconst_clobber"
2509 [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
2510 (ashiftrt:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
2511 (neg:QI (match_operand:QI 2 "src_operand" "R,rS<>,rm,R,rS<>,rm"))))
2512 (clobber (reg:CC 21))]
2513 "valid_operands (ASHIFTRT, operands, QImode)"
2521 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2522 ; Default to int16 data attr.
2527 ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
2528 ; thing would be to get the small constant loaded into a register (say r0)
2529 ; so that it could be hoisted out of the loop so that we only
2530 ; would need to do cmpi3 *ar0++, r0. Now the loop optimisation pass
2531 ; comes before the flow pass (which finds autoincrements) so we're stuck.
2532 ; Ideally, GCC requires another loop optimisation pass (preferably after
2533 ; reload) so that it can hoist invariants out of loops.
2534 ; The current solution modifies legitimize_operands () so that small
2535 ; constants are forced into a pseudo register.
2537 (define_expand "cmpqi"
2539 (compare:CC (match_operand:QI 0 "src_operand" "")
2540 (match_operand:QI 1 "src_operand" "")))]
2542 "legitimize_operands (COMPARE, operands, QImode);
2543 c4x_compare_op0 = operands[0];
2544 c4x_compare_op1 = operands[1];
2547 (define_insn "*cmpqi_test"
2549 (compare:CC (match_operand:QI 0 "src_operand" "rR,?rS<>,r")
2550 (match_operand:QI 1 "src_operand" "JR,rS<>,g")))]
2551 "valid_operands (COMPARE, operands, QImode)"
2556 [(set_attr "type" "compare,compare,compare")])
2558 (define_insn "*cmpqi_test_noov"
2559 [(set (reg:CC_NOOV 21)
2560 (compare:CC_NOOV (match_operand:QI 0 "src_operand" "rR,?rS<>,r")
2561 (match_operand:QI 1 "src_operand" "JR,rS<>,g")))]
2562 "valid_operands (COMPARE, operands, QImode)"
2567 [(set_attr "type" "compare,compare,compare")])
2569 (define_expand "udivqi3"
2570 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2571 (udiv:QI (match_operand:QI 1 "src_operand" "")
2572 (match_operand:QI 2 "src_operand" "")))
2573 (clobber (reg:CC 21))])]
2575 "c4x_emit_libcall3 (UDIVQI3_LIBCALL, UDIV, QImode, operands);
2578 (define_expand "divqi3"
2579 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2580 (div:QI (match_operand:QI 1 "src_operand" "")
2581 (match_operand:QI 2 "src_operand" "")))
2582 (clobber (reg:CC 21))])]
2584 "c4x_emit_libcall3 (DIVQI3_LIBCALL, DIV, QImode, operands);
2587 (define_expand "umodqi3"
2588 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2589 (umod:QI (match_operand:QI 1 "src_operand" "")
2590 (match_operand:QI 2 "src_operand" "")))
2591 (clobber (reg:CC 21))])]
2593 "c4x_emit_libcall3 (UMODQI3_LIBCALL, UMOD, QImode, operands);
2596 (define_expand "modqi3"
2597 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2598 (mod:QI (match_operand:QI 1 "src_operand" "")
2599 (match_operand:QI 2 "src_operand" "")))
2600 (clobber (reg:CC 21))])]
2602 "c4x_emit_libcall3 (MODQI3_LIBCALL, MOD, QImode, operands);
2605 (define_expand "ffsqi2"
2606 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2607 (ffs:QI (match_operand:QI 1 "src_operand" "")))
2608 (clobber (reg:CC 21))])]
2610 "c4x_emit_libcall (FFS_LIBCALL, FFS, QImode, QImode, 2, operands);
2614 ; BIT-FIELD INSTRUCTIONS
2618 ; LBx/LHw (C4x only)
2620 (define_expand "extv"
2621 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2622 (sign_extract:QI (match_operand:QI 1 "src_operand" "")
2623 (match_operand:QI 2 "const_int_operand" "")
2624 (match_operand:QI 3 "const_int_operand" "")))
2625 (clobber (reg:CC 21))])]
2627 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
2628 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
2632 (define_insn "*extv_clobber"
2633 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2634 (sign_extract:QI (match_operand:QI 1 "src_operand" "g,g")
2635 (match_operand:QI 2 "const_int_operand" "n,n")
2636 (match_operand:QI 3 "const_int_operand" "n,n")))
2637 (clobber (reg:CC 21))]
2639 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2640 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2642 if (INTVAL (operands[2]) == 8)
2644 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2645 return \"lb%3\\t%1,%0\";
2647 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2648 return \"lh%3\\t%1,%0\";
2650 [(set_attr "type" "binarycc,binary")
2651 (set_attr "data" "int16,int16")])
2653 (define_insn "*extv_clobber_test"
2655 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "g")
2656 (match_operand:QI 2 "const_int_operand" "n")
2657 (match_operand:QI 3 "const_int_operand" "n"))
2659 (clobber (match_scratch:QI 0 "=d"))]
2661 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2662 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2664 if (INTVAL (operands[2]) == 8)
2666 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2667 return \"lb%3\\t%1,%0\";
2669 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2670 return \"lh%3\\t%1,%0\";
2672 [(set_attr "type" "binarycc")
2673 (set_attr "data" "int16")])
2675 (define_insn "*extv_clobber_set"
2677 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "g")
2678 (match_operand:QI 2 "const_int_operand" "n")
2679 (match_operand:QI 3 "const_int_operand" "n"))
2681 (set (match_operand:QI 0 "reg_operand" "=d")
2682 (sign_extract:QI (match_dup 1)
2686 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2687 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2689 if (INTVAL (operands[2]) == 8)
2691 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2692 return \"lb%3\\t%1,%0\";
2694 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2695 return \"lh%3\\t%1,%0\";
2697 [(set_attr "type" "binarycc")
2698 (set_attr "data" "int16")])
2701 ; LBUx/LHUw (C4x only)
2703 (define_expand "extzv"
2704 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2705 (zero_extract:QI (match_operand:QI 1 "src_operand" "")
2706 (match_operand:QI 2 "const_int_operand" "")
2707 (match_operand:QI 3 "const_int_operand" "")))
2708 (clobber (reg:CC 21))])]
2710 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
2711 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
2715 (define_insn "*extzv_clobber"
2716 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2717 (zero_extract:QI (match_operand:QI 1 "src_operand" "g,g")
2718 (match_operand:QI 2 "const_int_operand" "n,n")
2719 (match_operand:QI 3 "const_int_operand" "n,n")))
2720 (clobber (reg:CC 21))]
2722 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2723 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2725 if (INTVAL (operands[2]) == 8)
2727 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2728 return \"lbu%3\\t%1,%0\";
2730 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2731 return \"lhu%3\\t%1,%0\";
2733 [(set_attr "type" "binarycc,binary")
2734 (set_attr "data" "uint16,uint16")])
2736 (define_insn "*extzv_test"
2738 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "g")
2739 (match_operand:QI 2 "const_int_operand" "n")
2740 (match_operand:QI 3 "const_int_operand" "n"))
2742 (clobber (match_scratch:QI 0 "=d"))]
2744 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2745 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2747 if (INTVAL (operands[2]) == 8)
2749 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2750 return \"lbu%3\\t%1,%0\";
2752 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2753 return \"lhu%3\\t%1,%0\";
2755 [(set_attr "type" "binarycc")
2756 (set_attr "data" "uint16")])
2758 (define_insn "*extzv_set"
2760 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "g")
2761 (match_operand:QI 2 "const_int_operand" "n")
2762 (match_operand:QI 3 "const_int_operand" "n"))
2764 (set (match_operand:QI 0 "reg_operand" "=d")
2765 (zero_extract:QI (match_dup 1)
2769 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2770 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
2772 if (INTVAL (operands[2]) == 8)
2774 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
2775 return \"lbu%3\\t%1,%0\";
2777 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
2778 return \"lhu%3\\t%1,%0\";
2780 [(set_attr "type" "binarycc")
2781 (set_attr "data" "uint16")])
2784 ; MBx/MHw (C4x only)
2786 (define_expand "insv"
2787 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "")
2788 (match_operand:QI 1 "const_int_operand" "")
2789 (match_operand:QI 2 "const_int_operand" ""))
2790 (match_operand:QI 3 "src_operand" ""))
2791 (clobber (reg:CC 21))])]
2793 "if (!(((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2794 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
2795 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)))
2799 (define_insn "*insv_clobber"
2800 [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "=d,c")
2801 (match_operand:QI 1 "const_int_operand" "n,n")
2802 (match_operand:QI 2 "const_int_operand" "n,n"))
2803 (match_operand:QI 3 "src_operand" "g,g"))
2804 (clobber (reg:CC 21))]
2806 && (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2807 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
2808 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8))"
2810 if (INTVAL (operands[1]) == 8)
2812 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
2813 return \"mb%2\\t%3,%0\";
2815 else if (INTVAL (operands[1]) == 16)
2817 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
2818 return \"mh%2\\t%3,%0\";
2820 return \"lwl1\\t%3,%0\";
2822 [(set_attr "type" "binarycc,binary")
2823 (set_attr "data" "uint16,uint16")])
2826 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "=d")
2827 (match_operand:QI 1 "const_int_operand" "n")
2828 (match_operand:QI 2 "const_int_operand" "n"))
2829 (match_operand:QI 3 "src_operand" "g"))
2830 (clobber (reg:CC 21))])
2832 (compare:CC (match_dup 0) (const_int 0)))]
2834 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2835 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0)"
2837 if (INTVAL (operands[1]) == 8)
2839 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
2840 return \"mb%2\\t%3,%0\";
2842 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
2843 return \"mh%2\\t%3,%0\";
2845 [(set_attr "type" "binarycc")
2846 (set_attr "data" "uint16")])
2849 ; TWO OPERAND FLOAT INSTRUCTIONS
2855 ; If one of the operands is not a register, then we should
2856 ; emit two insns, using a scratch register. This will produce
2857 ; better code in loops if the source operand is invariant, since
2858 ; the source reload can be optimised out. During reload we cannot
2859 ; use change_address or force_reg.
2860 (define_expand "movqf"
2861 [(set (match_operand:QF 0 "src_operand" "")
2862 (match_operand:QF 1 "src_operand" ""))]
2865 if (CONSTANT_P (operands[1]) && !const_operand (operands[1], QFmode))
2867 operands[1] = force_const_mem (QFmode, operands[1]);
2868 if (!memory_address_p (QFmode, XEXP (operands[1], 0))
2869 && !reload_in_progress)
2870 operands[1] = change_address (operands[1], QFmode,
2871 XEXP (operands[1], 0));
2874 if (!reload_in_progress
2875 && !reg_operand (operands[0], QFmode)
2876 && !reg_operand (operands[1], QFmode))
2877 operands[1] = force_reg (QFmode, operands[1]);
2880 ; We must provide an alternative to store to memory in case we have to
2882 (define_insn "*movqf_noclobber"
2883 [(set (match_operand:QF 0 "src_operand" "=f,m")
2884 (match_operand:QF 1 "src_operand" "fmH,f"))]
2885 "reg_operand (operands[0], QFmode)
2886 || reg_operand (operands[1], QFmode)"
2890 [(set_attr "type" "unary,store")])
2892 ;(define_insn "*movqf_clobber"
2893 ; [(set (match_operand:QF 0 "reg_operand" "=f")
2894 ; (match_operand:QF 1 "src_operand" "fmH"))
2895 ; (clobber (reg:CC 21))]
2898 ; [(set_attr "type" "unarycc")])
2900 (define_insn "*movqf_test"
2902 (compare:CC (match_operand:QF 1 "src_operand" "fmH")
2904 (clobber (match_scratch:QF 0 "=f"))]
2907 [(set_attr "type" "unarycc")])
2909 (define_insn "*movqf_set"
2911 (compare:CC (match_operand:QF 1 "src_operand" "fmH")
2912 (match_operand:QF 2 "fp_zero_operand" "G")))
2913 (set (match_operand:QF 0 "reg_operand" "=f")
2917 [(set_attr "type" "unarycc")])
2919 (define_insn "*movqf_update"
2920 [(set (match_operand:QF 0 "reg_operand" "=r")
2921 (mem:QF (plus:QI (match_operand:QI 1 "addr_reg_operand" "a")
2922 (match_operand:QI 2 "index_reg_operand" "x"))))
2924 (plus:QI (match_dup 1) (match_dup 2)))]
2926 "ldfu\\t*%1++(%2),%0"
2927 [(set_attr "type" "unary")])
2929 (define_insn "*movqf_parallel"
2930 [(set (match_operand:QF 0 "parallel_operand" "=q,S<>,q,S<>")
2931 (match_operand:QF 1 "parallel_operand" "S<>,q,S<>,q"))
2932 (set (match_operand:QF 2 "parallel_operand" "=q,S<>,S<>,q")
2933 (match_operand:QF 3 "parallel_operand" "S<>,q,q,S<>"))]
2934 "valid_parallel_operands_4 (operands, QFmode)"
2936 ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
2937 stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
2938 ldf\\t%1,%0\\n||\\tstf\\t%3,%2
2939 ldf\\t%3,%2\\n||\\tstf\\t%1,%0"
2940 [(set_attr "type" "load_load,store_store,load_store,store_load")])
2946 (define_insn "*pushqf"
2947 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
2948 (match_operand:QF 0 "reg_operand" "f"))]
2951 [(set_attr "type" "push")])
2953 (define_insn "*popqf"
2954 [(set (match_operand:QF 0 "reg_operand" "=f")
2955 (mem:QF (post_dec:QI (reg:QI 20))))
2956 (clobber (reg:CC 21))]
2959 [(set_attr "type" "pop")])
2965 (define_expand "absqf2"
2966 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
2967 (abs:QF (match_operand:QF 1 "src_operand" "")))
2968 (clobber (reg:CC_NOOV 21))])]
2972 (define_insn "*absqf2_clobber"
2973 [(set (match_operand:QF 0 "reg_operand" "=f")
2974 (abs:QF (match_operand:QF 1 "src_operand" "fmH")))
2975 (clobber (reg:CC_NOOV 21))]
2978 [(set_attr "type" "unarycc")])
2980 (define_insn "*absqf2_test"
2981 [(set (reg:CC_NOOV 21)
2982 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fmH"))
2983 (match_operand:QF 2 "fp_zero_operand" "G")))
2984 (clobber (match_scratch:QF 0 "=f"))]
2987 [(set_attr "type" "unarycc")])
2989 (define_insn "*absqf2_set"
2990 [(set (reg:CC_NOOV 21)
2991 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fmH"))
2992 (match_operand:QF 2 "fp_zero_operand" "G")))
2993 (set (match_operand:QF 0 "reg_operand" "=f")
2994 (abs:QF (match_dup 1)))]
2998 [(set_attr "type" "unarycc")])
3003 (define_expand "negqf2"
3004 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3005 (neg:QF (match_operand:QF 1 "src_operand" "")))
3006 (clobber (reg:CC_NOOV 21))])]
3010 (define_insn "*negqf2_clobber"
3011 [(set (match_operand:QF 0 "reg_operand" "=f")
3012 (neg:QF (match_operand:QF 1 "src_operand" "fmH")))
3013 (clobber (reg:CC_NOOV 21))]
3016 [(set_attr "type" "unarycc")])
3018 (define_insn "*negqf2_test"
3019 [(set (reg:CC_NOOV 21)
3020 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fmH"))
3021 (match_operand:QF 2 "fp_zero_operand" "G")))
3022 (clobber (match_scratch:QF 0 "=f"))]
3025 [(set_attr "type" "unarycc")])
3027 (define_insn "*negqf2_set"
3028 [(set (reg:CC_NOOV 21)
3029 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fmH"))
3030 (match_operand:QF 2 "fp_zero_operand" "G")))
3031 (set (match_operand:QF 0 "reg_operand" "=f")
3032 (neg:QF (match_dup 1)))]
3035 [(set_attr "type" "unarycc")])
3040 (define_insn "floatqiqf2"
3041 [(set (match_operand:QF 0 "reg_operand" "=f")
3042 (float:QF (match_operand:QI 1 "src_operand" "g")))
3043 (clobber (reg:CC 21))]
3046 [(set_attr "type" "unarycc")])
3048 (define_insn "*floatqiqf2_set"
3050 (compare:CC (float:QF (match_operand:QI 1 "src_operand" "g"))
3051 (match_operand:QF 2 "fp_zero_operand" "G")))
3052 (set (match_operand:QF 0 "reg_operand" "=f")
3053 (float:QF (match_dup 1)))]
3057 [(set_attr "type" "unarycc")])
3059 ; Unsigned conversions are a little tricky because we need to
3060 ; add the value for the high bit if necessary.
3062 (define_expand "floatunsqiqf2"
3063 [(set (match_dup 2) (match_dup 3))
3064 (parallel [(set (reg:CC 21)
3065 (compare:CC (float:QF (match_operand:QI 1 "src_operand" ""))
3068 (float:QF (match_dup 1)))])
3070 (if_then_else:QF (lt (reg:CC 21) (const_int 0))
3071 (mem:QF (symbol_ref:QF "*___unsfltconst"))
3073 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3074 (plus:QF (match_dup 2) (match_dup 4)))
3075 (clobber (reg:CC_NOOV 21))])]
3077 "operands[2] = gen_reg_rtx (QFmode);
3078 operands[3] = CONST0_RTX (QFmode);
3079 operands[4] = gen_reg_rtx (QFmode);
3082 (define_insn "floatqihf2"
3083 [(set (match_operand:HF 0 "reg_operand" "=h")
3084 (float:HF (match_operand:QI 1 "src_operand" "g")))
3085 (clobber (reg:CC 21))]
3088 [(set_attr "type" "unarycc")])
3093 (define_insn "fixqfqi_clobber"
3094 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3095 (fix:QI (match_operand:QF 1 "src_operand" "fmH,fmH")))
3096 (clobber (reg:CC 21))]
3099 [(set_attr "type" "unarycc")])
3101 (define_insn "*fixqfqi_set"
3103 (compare:CC (fix:QI (match_operand:QF 1 "src_operand" "fmH"))
3105 (set (match_operand:QI 0 "reg_operand" "=d")
3106 (fix:QI (match_dup 1)))]
3109 [(set_attr "type" "unarycc")])
3112 ; The C[34]x fix instruction implements a floor, not a straight trunc,
3113 ; so we have to invert the number, fix it, and reinvert it if negative
3115 (define_expand "fix_truncqfqi2"
3116 [(parallel [(set (match_dup 2)
3117 (fix:QI (match_operand:QF 1 "src_operand" "")))
3118 (clobber (reg:CC 21))])
3119 (parallel [(set (match_dup 3) (neg:QF (match_dup 1)))
3120 (clobber (reg:CC_NOOV 21))])
3121 (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
3122 (clobber (reg:CC 21))])
3123 (parallel [(set (reg:CC_NOOV 21)
3124 (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
3125 (set (match_dup 5) (neg:QI (match_dup 4)))])
3127 (if_then_else:QI (le (reg:CC 21) (const_int 0))
3130 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
3132 "if (TARGET_FAST_FIX)
3134 emit_insn (gen_fixqfqi_clobber (operands[0], operands[1]));
3137 operands[2] = gen_reg_rtx (QImode);
3138 operands[3] = gen_reg_rtx (QFmode);
3139 operands[4] = gen_reg_rtx (QImode);
3140 operands[5] = gen_reg_rtx (QImode);
3143 (define_expand "fix_truncqfhi2"
3144 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3145 (fix:HI (match_operand:QF 1 "src_operand" "")))
3146 (clobber (reg:CC 21))])]
3148 "c4x_emit_libcall (FIX_TRUNCQFHI2_LIBCALL, FIX, HImode, QFmode, 2, operands);
3151 (define_expand "fixuns_truncqfqi2"
3152 [(set (match_dup 2) (match_dup 4))
3154 (compare:CC (match_operand:QF 1 "reg_operand" "")
3155 (mem:QF (symbol_ref "*___unsfltcompare"))))
3157 (if_then_else:QF (ge (reg:CC 21) (const_int 0))
3158 (mem:QF (symbol_ref "*___unsfltconst"))
3160 (parallel [(set (match_dup 3)
3161 (minus:QF (match_dup 1) (match_dup 2)))
3162 (clobber (reg:CC_NOOV 21))])
3163 (parallel [(set (match_operand:QI 0 "reg_operand" "")
3164 (fix:QI (match_dup 3)))
3165 (clobber (reg:CC 21))])]
3167 "operands[2] = gen_reg_rtx (QFmode);
3168 operands[3] = gen_reg_rtx (QFmode);
3169 operands[4] = CONST0_RTX (QFmode);
3172 (define_expand "fixuns_truncqfhi2"
3173 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3174 (unsigned_fix:HI (match_operand:QF 1 "src_operand" "")))
3175 (clobber (reg:CC 21))])]
3177 "c4x_emit_libcall (FIXUNS_TRUNCQFHI2_LIBCALL, UNSIGNED_FIX,
3178 HImode, QFmode, 2, operands);
3184 (define_insn "*rcpfqf_clobber"
3185 [(set (match_operand:QF 0 "reg_operand" "=f")
3186 (unspec [(match_operand:QF 1 "src_operand" "fmH")] 5))
3187 (clobber (reg:CC_NOOV 21))]
3190 [(set_attr "type" "unarycc")])
3195 (define_insn "*rsqrfqf_clobber"
3196 [(set (match_operand:QF 0 "reg_operand" "=f")
3197 (unspec [(match_operand:QF 1 "src_operand" "fmH")] 10))
3198 (clobber (reg:CC_NOOV 21))]
3201 [(set_attr "type" "unarycc")])
3206 (define_insn "*rndqf_clobber"
3207 [(set (match_operand:QF 0 "reg_operand" "=f")
3208 (unspec [(match_operand:QF 1 "src_operand" "fmH")] 6))
3209 (clobber (reg:CC_NOOV 21))]
3212 [(set_attr "type" "unarycc")])
3215 ; Inlined float square root for C4x
3216 (define_expand "sqrtqf2_inline"
3217 [(parallel [(set (match_dup 2)
3218 (unspec [(match_operand:QF 1 "src_operand" "")] 10))
3219 (clobber (reg:CC_NOOV 21))])
3220 (parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1)))
3221 (clobber (reg:CC_NOOV 21))])
3222 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3223 (clobber (reg:CC_NOOV 21))])
3224 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3225 (clobber (reg:CC_NOOV 21))])
3226 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3227 (clobber (reg:CC_NOOV 21))])
3228 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3229 (clobber (reg:CC_NOOV 21))])
3230 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3231 (clobber (reg:CC_NOOV 21))])
3232 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3233 (clobber (reg:CC_NOOV 21))])
3234 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3235 (clobber (reg:CC_NOOV 21))])
3236 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3237 (clobber (reg:CC_NOOV 21))])
3238 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1)))
3239 (clobber (reg:CC_NOOV 21))])
3240 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3241 (unspec [(match_dup 4)] 6))
3242 (clobber (reg:CC_NOOV 21))])]
3244 "if (!reload_in_progress
3245 && !reg_operand (operands[1], QFmode))
3246 operands[1] = force_reg (QFmode, operands[1]);
3247 operands[2] = gen_reg_rtx (QFmode);
3248 operands[3] = gen_reg_rtx (QFmode);
3249 operands[4] = gen_reg_rtx (QFmode);
3250 operands[5] = immed_real_const_1 (REAL_VALUE_ATOF (\"0.5\", QFmode),
3252 operands[6] = immed_real_const_1 (REAL_VALUE_ATOF (\"1.5\", QFmode),
3255 (define_expand "sqrtqf2"
3256 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3257 (sqrt:QF (match_operand:QF 1 "src_operand" "")))
3258 (clobber (reg:CC 21))])]
3260 "if (TARGET_C3X || !TARGET_INLINE)
3264 emit_insn (gen_sqrtqf2_inline( operands[0], operands[1]));
3270 ; THREE OPERAND FLOAT INSTRUCTIONS
3276 (define_expand "addqf3"
3277 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3278 (plus:QF (match_operand:QF 1 "src_operand" "")
3279 (match_operand:QF 2 "src_operand" "")))
3280 (clobber (reg:CC_NOOV 21))])]
3282 "legitimize_operands (PLUS, operands, QFmode);")
3284 (define_insn "*addqf3_clobber"
3285 [(set (match_operand:QF 0 "reg_operand" "=f,?f,f")
3286 (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3287 (match_operand:QF 2 "src_operand" "R,fS<>,fmH")))
3288 (clobber (reg:CC_NOOV 21))]
3289 "valid_operands (PLUS, operands, QFmode)"
3294 [(set_attr "type" "binarycc,binarycc,binarycc")])
3296 (define_insn "*addqf3_test"
3297 [(set (reg:CC_NOOV 21)
3298 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3299 (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
3300 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3301 (clobber (match_scratch:QF 0 "=f,?f,f"))]
3302 "valid_operands (PLUS, operands, QFmode)"
3307 [(set_attr "type" "binarycc,binarycc,binarycc")])
3309 (define_insn "*addqf3_set"
3310 [(set (reg:CC_NOOV 21)
3311 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3312 (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
3313 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3314 (set (match_operand:QF 0 "reg_operand" "=f,?f,f")
3315 (plus:QF (match_dup 1)
3317 "valid_operands (PLUS, operands, QFmode)"
3322 [(set_attr "type" "binarycc,binarycc,binarycc")])
3327 (define_expand "subqf3"
3328 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3329 (minus:QF (match_operand:QF 1 "src_operand" "")
3330 (match_operand:QF 2 "src_operand" "")))
3331 (clobber (reg:CC_NOOV 21))])]
3333 "legitimize_operands (MINUS, operands, QFmode);")
3335 (define_insn "*subqf3_clobber"
3336 [(set (match_operand:QF 0 "reg_operand" "=f,?f,f,f")
3337 (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
3338 (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0")))
3339 (clobber (reg:CC_NOOV 21))]
3340 "valid_operands (MINUS, operands, QFmode)"
3346 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
3348 (define_insn "*subqf3_test"
3349 [(set (reg:CC_NOOV 21)
3350 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
3351 (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0"))
3352 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
3353 (clobber (match_scratch:QF 0 "=f,?f,f,f"))]
3354 "valid_operands (MINUS, operands, QFmode)"
3360 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
3362 (define_insn "*subqf3_set"
3363 [(set (reg:CC_NOOV 21)
3364 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
3365 (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0"))
3366 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
3367 (set (match_operand:QF 0 "reg_operand" "=f,?f,f,f")
3368 (minus:QF (match_dup 1)
3370 "valid_operands (MINUS, operands, QFmode)"
3376 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
3381 (define_expand "mulqf3"
3382 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3383 (mult:QF (match_operand:QF 1 "src_operand" "")
3384 (match_operand:QF 2 "src_operand" "")))
3385 (clobber (reg:CC_NOOV 21))])]
3387 "legitimize_operands (MULT, operands, QFmode);")
3389 (define_insn "*mulqf3_clobber"
3390 [(set (match_operand:QF 0 "reg_operand" "=f,?f,f")
3391 (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3392 (match_operand:QF 2 "src_operand" "R,fS<>,fmH")))
3393 (clobber (reg:CC_NOOV 21))]
3394 "valid_operands (MULT, operands, QFmode)"
3399 [(set_attr "type" "binarycc,binarycc,binarycc")])
3401 (define_insn "*mulqf3_test"
3402 [(set (reg:CC_NOOV 21)
3403 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3404 (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
3405 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3406 (clobber (match_scratch:QF 0 "=f,?f,f"))]
3407 "valid_operands (MULT, operands, QFmode)"
3412 [(set_attr "type" "binarycc,binarycc,binarycc")])
3414 (define_insn "*mulqf3_set"
3415 [(set (reg:CC_NOOV 21)
3416 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
3417 (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
3418 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3419 (set (match_operand:QF 0 "reg_operand" "=f,?f,f")
3420 (mult:QF (match_dup 1)
3422 "valid_operands (MULT, operands, QFmode)"
3427 [(set_attr "type" "binarycc,binarycc,binarycc")])
3432 (define_expand "cmpqf"
3434 (compare:CC (match_operand:QF 0 "src_operand" "")
3435 (match_operand:QF 1 "src_operand" "")))]
3437 "legitimize_operands (COMPARE, operands, QFmode);
3438 c4x_compare_op0 = operands[0];
3439 c4x_compare_op1 = operands[1];
3442 (define_insn "*cmpqf"
3444 (compare:CC (match_operand:QF 0 "src_operand" "fR,?fS<>,f")
3445 (match_operand:QF 1 "src_operand" "R,fS<>,fmH")))]
3446 "valid_operands (COMPARE, operands, QFmode)"
3451 [(set_attr "type" "compare,compare,compare")])
3453 (define_insn "*cmpqf_noov"
3454 [(set (reg:CC_NOOV 21)
3455 (compare:CC_NOOV (match_operand:QF 0 "src_operand" "fR,?fS<>,f")
3456 (match_operand:QF 1 "src_operand" "R,fS<>,fmH")))]
3457 "valid_operands (COMPARE, operands, QFmode)"
3462 [(set_attr "type" "compare,compare,compare")])
3464 ; Inlined float divide for C4x
3465 (define_expand "divqf3_inline"
3466 [(parallel [(set (match_dup 3)
3467 (unspec [(match_operand:QF 2 "src_operand" "")] 5))
3468 (clobber (reg:CC_NOOV 21))])
3469 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3470 (clobber (reg:CC_NOOV 21))])
3471 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
3472 (clobber (reg:CC_NOOV 21))])
3473 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
3474 (clobber (reg:CC_NOOV 21))])
3475 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3476 (clobber (reg:CC_NOOV 21))])
3477 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
3478 (clobber (reg:CC_NOOV 21))])
3479 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
3480 (clobber (reg:CC_NOOV 21))])
3481 (parallel [(set (match_dup 3)
3482 (mult:QF (match_operand:QF 1 "src_operand" "")
3484 (clobber (reg:CC_NOOV 21))])
3485 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3486 (unspec [(match_dup 3)] 6))
3487 (clobber (reg:CC_NOOV 21))])]
3489 "if (!reload_in_progress
3490 && !reg_operand (operands[2], QFmode))
3491 operands[2] = force_reg (QFmode, operands[2]);
3492 operands[3] = gen_reg_rtx (QFmode);
3493 operands[4] = gen_reg_rtx (QFmode);
3494 operands[5] = CONST2_RTX (QFmode);")
3496 (define_expand "divqf3"
3497 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3498 (div:QF (match_operand:QF 1 "src_operand" "")
3499 (match_operand:QF 2 "src_operand" "")))
3500 (clobber (reg:CC 21))])]
3502 "if (TARGET_C3X || !TARGET_INLINE)
3504 c4x_emit_libcall3 (DIVQF3_LIBCALL, DIV, QFmode, operands);
3509 emit_insn (gen_divqf3_inline( operands[0], operands[1], operands[2]));
3518 (define_insn "*ldi_conditional"
3519 [(set (match_operand:QI 0 "reg_operand" "=r,r")
3520 (if_then_else:QI (match_operator 1 "comparison_operator"
3521 [(reg:CC 21) (const_int 0)])
3522 (match_operand:QI 2 "src_operand" "g,0")
3523 (match_operand:QI 3 "src_operand" "0,g")))]
3528 [(set_attr "type" "binary")])
3530 (define_insn "*ldi_conditional_noov"
3531 [(set (match_operand:QI 0 "reg_operand" "=r,r")
3532 (if_then_else:QI (match_operator 1 "comparison_operator"
3533 [(reg:CC_NOOV 21) (const_int 0)])
3534 (match_operand:QI 2 "src_operand" "g,0")
3535 (match_operand:QI 3 "src_operand" "0,g")))]
3536 "GET_CODE(operands[1]) != LE
3537 && GET_CODE(operands[1]) != GE
3538 && GET_CODE(operands[1]) != LT
3539 && GET_CODE(operands[1]) != GT"
3543 [(set_attr "type" "binary")])
3545 ; Move operand 2 to operand 0 if condition (operand 1) is true
3546 ; else move operand 3 to operand 0.
3547 ; The temporary register is required below because some of the operands
3548 ; might be identical (namely 0 and 2).
3550 (define_expand "movqicc"
3551 [(set (match_operand:QI 0 "reg_operand" "")
3552 (if_then_else:QI (match_operand 1 "comparison_operator" "")
3553 (match_operand:QI 2 "src_operand" "")
3554 (match_operand:QI 3 "src_operand" "")))]
3557 enum rtx_code code = GET_CODE (operands[1]);
3558 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
3559 if (ccreg == NULL_RTX) FAIL;
3560 emit_insn (gen_rtx_SET (QImode, operands[0],
3561 gen_rtx_IF_THEN_ELSE (QImode,
3562 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
3563 operands[2], operands[3])));
3566 (define_insn "*ldf_conditional"
3567 [(set (match_operand:QF 0 "reg_operand" "=f,f")
3568 (if_then_else:QF (match_operator 1 "comparison_operator"
3569 [(reg:CC 21) (const_int 0)])
3570 (match_operand:QF 2 "src_operand" "fmH,0")
3571 (match_operand:QF 3 "src_operand" "0,fmH")))]
3576 [(set_attr "type" "binary")])
3578 (define_insn "*ldf_conditional_noov"
3579 [(set (match_operand:QF 0 "reg_operand" "=f,f")
3580 (if_then_else:QF (match_operator 1 "comparison_operator"
3581 [(reg:CC_NOOV 21) (const_int 0)])
3582 (match_operand:QF 2 "src_operand" "fmH,0")
3583 (match_operand:QF 3 "src_operand" "0,fmH")))]
3584 "GET_CODE(operands[1]) != LE
3585 && GET_CODE(operands[1]) != GE
3586 && GET_CODE(operands[1]) != LT
3587 && GET_CODE(operands[1]) != GT"
3591 [(set_attr "type" "binary")])
3593 (define_expand "movqfcc"
3594 [(set (match_operand:QF 0 "reg_operand" "")
3595 (if_then_else:QF (match_operand 1 "comparison_operator" "")
3596 (match_operand:QF 2 "src_operand" "")
3597 (match_operand:QF 3 "src_operand" "")))]
3600 enum rtx_code code = GET_CODE (operands[1]);
3601 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
3602 if (ccreg == NULL_RTX) FAIL;
3603 emit_insn (gen_rtx_SET (QFmode, operands[0],
3604 gen_rtx_IF_THEN_ELSE (QFmode,
3605 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
3606 operands[2], operands[3])));
3609 (define_expand "seq"
3610 [(set (match_operand:QI 0 "reg_operand" "")
3613 (if_then_else:QI (eq (match_dup 1) (const_int 0))
3617 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
3619 (define_expand "sne"
3620 [(set (match_operand:QI 0 "reg_operand" "")
3623 (if_then_else:QI (ne (match_dup 1) (const_int 0))
3627 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
3629 (define_expand "slt"
3630 [(set (match_operand:QI 0 "reg_operand" "")
3633 (if_then_else:QI (lt (match_dup 1) (const_int 0))
3637 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
3638 if (operands[1] == NULL_RTX) FAIL;")
3640 (define_expand "sltu"
3641 [(set (match_operand:QI 0 "reg_operand" "")
3644 (if_then_else:QI (ltu (match_dup 1) (const_int 0))
3648 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
3650 (define_expand "sgt"
3651 [(set (match_operand:QI 0 "reg_operand" "")
3654 (if_then_else:QI (gt (match_dup 1) (const_int 0))
3658 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
3659 if (operands[1] == NULL_RTX) FAIL;")
3661 (define_expand "sgtu"
3662 [(set (match_operand:QI 0 "reg_operand" "")
3665 (if_then_else:QI (gtu (match_dup 1) (const_int 0))
3669 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
3671 (define_expand "sle"
3672 [(set (match_operand:QI 0 "reg_operand" "")
3675 (if_then_else:QI (le (match_dup 1) (const_int 0))
3679 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
3680 if (operands[1] == NULL_RTX) FAIL;")
3682 (define_expand "sleu"
3683 [(set (match_operand:QI 0 "reg_operand" "")
3686 (if_then_else:QI (leu (match_dup 1) (const_int 0))
3690 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
3692 (define_expand "sge"
3693 [(set (match_operand:QI 0 "reg_operand" "")
3696 (if_then_else:QI (ge (match_dup 1) (const_int 0))
3700 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
3701 if (operands[1] == NULL_RTX) FAIL;")
3703 (define_expand "sgeu"
3704 [(set (match_operand:QI 0 "reg_operand" "")
3707 (if_then_else:QI (geu (match_dup 1) (const_int 0))
3711 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
3714 [(set (match_operand:QI 0 "reg_operand" "")
3715 (match_operator 1 "comparison_operator" [(reg:CC 21) (const_int 0)]))]
3717 [(set (match_dup 0) (const_int 0))
3719 (if_then_else:QI (match_op_dup 1 [(reg:CC 21) (const_int 0)])
3725 [(set (match_operand:QI 0 "reg_operand" "")
3726 (match_operator 1 "comparison_operator" [(reg:CC_NOOV 21) (const_int 0)]))]
3728 [(set (match_dup 0) (const_int 0))
3730 (if_then_else:QI (match_op_dup 1 [(reg:CC_NOOV 21) (const_int 0)])
3737 (unspec [(match_operand:QI 0 "reg_operand" "r")] 1))]
3740 [(set_attr "type" "jump")])
3742 (define_expand "caseqi"
3743 [(parallel [(set (match_dup 5)
3744 (minus:QI (match_operand:QI 0 "reg_operand" "")
3745 (match_operand:QI 1 "src_operand" "")))
3746 (clobber (reg:CC_NOOV 21))])
3748 (compare:CC (match_dup 5)
3749 (match_operand:QI 2 "src_operand" "")))
3751 (if_then_else (gtu (reg:CC 21)
3753 (label_ref (match_operand 4 "" ""))
3755 (parallel [(set (match_dup 6)
3756 (plus:QI (match_dup 5)
3757 (label_ref:QI (match_operand 3 "" ""))))
3758 (clobber (reg:CC_NOOV 21))])
3760 (mem:QI (match_dup 6)))
3761 (set (pc) (match_dup 7))]
3763 "operands[5] = gen_reg_rtx (QImode);
3764 operands[6] = gen_reg_rtx (QImode);
3765 operands[7] = gen_reg_rtx (QImode);")
3768 ; PARALLEL FLOAT INSTRUCTIONS
3770 ; This patterns are under development
3776 (define_insn "*absqf2_movqf_clobber"
3777 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3778 (abs:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
3779 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
3780 (match_operand:QF 3 "ext_low_reg_operand" "q"))
3781 (clobber (reg:CC_NOOV 21))]
3783 "absf\\t%1,%0\\n||\\tstf\\t%3,%2"
3784 [(set_attr "type" "binarycc")])
3790 (define_insn "*addqf3_movqf_clobber"
3791 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3792 (plus:QF (match_operand:QF 1 "parallel_operand" "%q")
3793 (match_operand:QF 2 "parallel_operand" "S<>")))
3794 (set (match_operand:QF 3 "par_ind_operand" "=S<>")
3795 (match_operand:QF 4 "ext_low_reg_operand" "q"))
3796 (clobber (reg:CC 21))]
3797 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
3798 "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
3799 [(set_attr "type" "binarycc")])
3805 (define_insn "*floatqiqf_movqf_clobber"
3806 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3807 (float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
3808 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
3809 (match_operand:QF 3 "ext_low_reg_operand" "q"))
3810 (clobber (reg:CC 21))]
3812 "float\\t%1,%0\\n||\\tstf\\t%3,%2"
3813 [(set_attr "type" "binarycc")])
3819 (define_insn "*mulqf3_addqf3_clobber"
3820 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
3821 (mult:QF (match_operand:QF 1 "parallel_operand" "S<>q")
3822 (match_operand:QF 2 "parallel_operand" "S<>q")))
3823 (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
3824 (plus:QF (match_operand:QF 4 "parallel_operand" "S<>q")
3825 (match_operand:QF 5 "parallel_operand" "S<>q")))
3826 (clobber (reg:CC 21))]
3827 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
3828 "mpyf3\\t%2,%1,%0\\n||\\taddf3\\t%5,%4,%3"
3829 [(set_attr "type" "binarycc")])
3836 (define_insn "*mulqf3_movqf_clobber"
3837 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3838 (mult:QF (match_operand:QF 1 "parallel_operand" "%q")
3839 (match_operand:QF 2 "parallel_operand" "S<>")))
3840 (set (match_operand:QF 3 "par_ind_operand" "=S<>")
3841 (match_operand:QF 4 "ext_low_reg_operand" "q"))
3842 (clobber (reg:CC 21))]
3843 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
3844 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
3845 [(set_attr "type" "binarycc")])
3851 (define_insn "*mulqf3_subqf3_clobber"
3852 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
3853 (mult:QF (match_operand:QF 1 "parallel_operand" "S<>q")
3854 (match_operand:QF 2 "parallel_operand" "S<>q")))
3855 (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
3856 (minus:QF (match_operand:QF 4 "parallel_operand" "S<>q")
3857 (match_operand:QF 5 "parallel_operand" "S<>q")))
3858 (clobber (reg:CC 21))]
3859 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
3860 "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%5,%4,%3"
3861 [(set_attr "type" "binarycc")])
3867 (define_insn "*negqf2_movqf_clobber"
3868 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3869 (neg:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
3870 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
3871 (match_operand:QF 3 "ext_low_reg_operand" "q"))
3872 (clobber (reg:CC 21))]
3874 "negf\\t%1,%0\\n||\\tstf\\t%3,%2"
3875 [(set_attr "type" "binarycc")])
3881 (define_insn "*subqf3_movqf_clobber"
3882 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
3883 (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
3884 (match_operand:QF 2 "par_ind_operand" "S<>")))
3885 (set (match_operand:QF 3 "par_ind_operand" "=S<>")
3886 (match_operand:QF 4 "ext_low_reg_operand" "q"))
3887 (clobber (reg:CC 21))]
3889 "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
3890 [(set_attr "type" "binarycc")])
3893 ; PARALLEL INTEGER INSTRUCTIONS
3895 ; These patterns are under development
3901 (define_insn "*absqi2_movqi_clobber"
3902 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3903 (abs:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
3904 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
3905 (match_operand:QI 3 "ext_low_reg_operand" "q"))
3906 (clobber (reg:CC_NOOV 21))]
3908 "absi\\t%1,%0\\n||\\tsti\\t%3,%2"
3909 [(set_attr "type" "binarycc")])
3915 (define_insn "*addqi3_movqi_clobber"
3916 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3917 (plus:QI (match_operand:QI 1 "parallel_operand" "%q")
3918 (match_operand:QI 2 "parallel_operand" "S<>")))
3919 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
3920 (match_operand:QI 4 "ext_low_reg_operand" "q"))
3921 (clobber (reg:CC 21))]
3922 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
3923 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
3924 [(set_attr "type" "binarycc")])
3930 (define_insn "*andqi3_movqi_clobber"
3931 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3932 (and:QI (match_operand:QI 1 "parallel_operand" "%q")
3933 (match_operand:QI 2 "parallel_operand" "S<>")))
3934 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
3935 (match_operand:QI 4 "ext_low_reg_operand" "q"))
3936 (clobber (reg:CC 21))]
3937 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
3938 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
3939 [(set_attr "type" "binarycc")])
3945 (define_insn "*ashlqi3_movqi_clobber"
3946 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3947 (ashift:QI (match_operand:QI 1 "par_ind_operand" "S<>")
3948 (match_operand:QI 2 "ext_low_reg_operand" "q")))
3949 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
3950 (match_operand:QI 4 "ext_low_reg_operand" "q"))
3951 (clobber (reg:CC 21))]
3953 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
3954 [(set_attr "type" "binarycc")])
3960 (define_insn "*ashlqi3_movqi_clobber"
3961 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3962 (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
3963 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
3964 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
3965 (match_operand:QI 4 "ext_low_reg_operand" "q"))
3966 (clobber (reg:CC 21))]
3968 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
3969 [(set_attr "type" "binarycc")])
3975 (define_insn "*fixqfqi2_movqi_clobber"
3976 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3977 (fix:QI (match_operand:QF 1 "par_ind_operand" "S<>")))
3978 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
3979 (match_operand:QI 3 "ext_low_reg_operand" "q"))
3980 (clobber (reg:CC 21))]
3982 "fix\\t%1,%0\\n||\\tsti\\t%3,%2"
3983 [(set_attr "type" "binarycc")])
3989 (define_insn "*lshrqi3_movqi_clobber"
3990 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
3991 (lshiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
3992 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
3993 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
3994 (match_operand:QI 4 "ext_low_reg_operand" "q"))
3995 (clobber (reg:CC 21))]
3997 "lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
3998 [(set_attr "type" "binarycc")])
4004 (define_insn "*mulqi3_addqi3_clobber"
4005 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
4006 (mult:QI (match_operand:QI 1 "parallel_operand" "S<>q")
4007 (match_operand:QI 2 "parallel_operand" "S<>q")))
4008 (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
4009 (plus:QI (match_operand:QI 4 "parallel_operand" "S<>q")
4010 (match_operand:QI 5 "parallel_operand" "S<>q")))
4011 (clobber (reg:CC 21))]
4012 "TARGET_PARALLEL_MPY && TARGET_MPYI
4013 && valid_parallel_operands_6 (operands, QImode)"
4014 "mpyi3\\t%2,%1,%0\\n||\\taddi3\\t%5,%4,%3"
4015 [(set_attr "type" "binarycc")])
4021 (define_insn "*mulqi3_movqi_clobber"
4022 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4023 (mult:QI (match_operand:QI 1 "parallel_operand" "%q")
4024 (match_operand:QI 2 "parallel_operand" "S<>")))
4025 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4026 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4027 (clobber (reg:CC 21))]
4028 "TARGET_PARALLEL && TARGET_MPYI
4029 && valid_parallel_operands_5 (operands, QImode)"
4030 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4031 [(set_attr "type" "binarycc")])
4037 (define_insn "*mulqi3_subqi3_clobber"
4038 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
4039 (mult:QI (match_operand:QI 1 "parallel_operand" "S<>q")
4040 (match_operand:QI 2 "parallel_operand" "S<>q")))
4041 (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
4042 (minus:QI (match_operand:QI 4 "parallel_operand" "S<>q")
4043 (match_operand:QI 5 "parallel_operand" "S<>q")))
4044 (clobber (reg:CC 21))]
4045 "TARGET_PARALLEL_MPY && TARGET_MPYI
4046 && valid_parallel_operands_6 (operands, QImode)"
4047 "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%5,%4,%3"
4048 [(set_attr "type" "binarycc")])
4054 (define_insn "*negqi2_movqi_clobber"
4055 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4056 (neg:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4057 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4058 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4059 (clobber (reg:CC 21))]
4061 "negi\\t%1,%0\\n||\\tsti\\t%3,%2"
4062 [(set_attr "type" "binarycc")])
4068 (define_insn "*notqi2_movqi_clobber"
4069 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4070 (not:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4071 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4072 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4073 (clobber (reg:CC 21))]
4075 "not\\t%1,%0\\n||\\tsti\\t%3,%2"
4076 [(set_attr "type" "binarycc")])
4082 (define_insn "*iorqi3_movqi_clobber"
4083 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4084 (ior:QI (match_operand:QI 1 "parallel_operand" "%q")
4085 (match_operand:QI 2 "parallel_operand" "S<>")))
4086 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4087 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4088 (clobber (reg:CC 21))]
4089 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4090 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4091 [(set_attr "type" "binarycc")])
4097 (define_insn "*subqi3_movqi_clobber"
4098 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4099 (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "q")
4100 (match_operand:QI 2 "par_ind_operand" "S<>")))
4101 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4102 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4103 (clobber (reg:CC 21))]
4105 "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4106 [(set_attr "type" "binarycc")])
4112 (define_insn "*xorqi3_movqi_clobber"
4113 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4114 (xor:QI (match_operand:QI 1 "parallel_operand" "%q")
4115 (match_operand:QI 2 "parallel_operand" "S<>")))
4116 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4117 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4118 (clobber (reg:CC 21))]
4119 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4120 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4121 [(set_attr "type" "binarycc")])
4124 ; BRANCH/CALL INSTRUCTIONS
4128 ; Branch instructions
4131 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4132 [(reg:CC 21) (const_int 0)])
4133 (label_ref (match_operand 1 "" ""))
4137 return c4x_output_cbranch (0, insn);"
4138 [(set_attr "type" "jmpc")])
4140 (define_insn "*b_rev"
4141 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4142 [(reg:CC 21) (const_int 0)])
4144 (label_ref (match_operand 1 "" ""))))]
4147 return c4x_output_cbranch (1, insn);"
4148 [(set_attr "type" "jmpc")])
4150 (define_insn "*b_noov"
4151 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4152 [(reg:CC_NOOV 21) (const_int 0)])
4153 (label_ref (match_operand 1 "" ""))
4155 "GET_CODE(operands[0]) != LE
4156 && GET_CODE(operands[0]) != GE
4157 && GET_CODE(operands[0]) != LT
4158 && GET_CODE(operands[0]) != GT"
4160 return c4x_output_cbranch (0, insn);"
4161 [(set_attr "type" "jmpc")])
4163 (define_insn "*b_noov_rev"
4164 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4165 [(reg:CC_NOOV 21) (const_int 0)])
4167 (label_ref (match_operand 1 "" ""))))]
4168 "GET_CODE(operands[0]) != LE
4169 && GET_CODE(operands[0]) != GE
4170 && GET_CODE(operands[0]) != LT
4171 && GET_CODE(operands[0]) != GT"
4173 return c4x_output_cbranch (1, insn);"
4174 [(set_attr "type" "jmpc")])
4176 (define_expand "beq"
4177 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
4178 (label_ref (match_operand 0 "" ""))
4181 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
4183 (define_expand "bne"
4184 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
4185 (label_ref (match_operand 0 "" ""))
4188 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
4190 (define_expand "blt"
4191 [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0))
4192 (label_ref (match_operand 0 "" ""))
4195 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
4196 if (operands[1] == NULL_RTX) FAIL;")
4198 (define_expand "bltu"
4199 [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0))
4200 (label_ref (match_operand 0 "" ""))
4203 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
4205 (define_expand "bgt"
4206 [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0))
4207 (label_ref (match_operand 0 "" ""))
4210 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
4211 if (operands[1] == NULL_RTX) FAIL;")
4213 (define_expand "bgtu"
4214 [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0))
4215 (label_ref (match_operand 0 "" ""))
4218 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
4220 (define_expand "ble"
4221 [(set (pc) (if_then_else (le (match_dup 1) (const_int 0))
4222 (label_ref (match_operand 0 "" ""))
4225 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
4226 if (operands[1] == NULL_RTX) FAIL;")
4228 (define_expand "bleu"
4229 [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0))
4230 (label_ref (match_operand 0 "" ""))
4233 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
4235 (define_expand "bge"
4236 [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0))
4237 (label_ref (match_operand 0 "" ""))
4240 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
4241 if (operands[1] == NULL_RTX) FAIL;")
4243 (define_expand "bgeu"
4244 [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0))
4245 (label_ref (match_operand 0 "" ""))
4248 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
4250 (define_insn "*b_reg"
4251 [(set (pc) (match_operand:QI 0 "reg_operand" "r"))]
4254 [(set_attr "type" "jump")])
4256 (define_expand "indirect_jump"
4257 [(set (pc) (match_operand:QI 0 "reg_operand" ""))]
4261 (define_insn "tablejump"
4262 [(set (pc) (match_operand:QI 0 "src_operand" "r"))
4263 (use (label_ref (match_operand 1 "" "")))]
4266 [(set_attr "type" "jump")])
4271 (define_insn "*call_c3x"
4272 [(call (match_operand:QI 0 "call_operand" "T,!o")
4273 (match_operand:QI 1 "general_operand" ""))
4274 (clobber (reg:QI 31))]
4275 ;; Operand 1 not really used on the C4x. The C30 doesn't have reg 31.
4281 [(set_attr "type" "call,call")])
4283 ; LAJ requires R11 (31) for the return address
4285 [(call (match_operand:QI 0 "call_operand" "T,!o")
4286 (match_operand:QI 1 "general_operand" ""))
4287 (clobber (reg:QI 31))]
4288 ;; Operand 1 not really used on the C4x.
4292 if (which_alternative == 0)
4295 return \"laj\\t%C0\";
4297 return \"call\\t%C0\";
4302 return \"laju\\t%R0\";
4304 return \"callu\\t%R0\";
4306 [(set_attr "type" "laj,laj")])
4308 (define_expand "call"
4309 [(parallel [(call (match_operand:QI 0 "call_operand" "")
4310 (match_operand:QI 1 "general_operand" ""))
4311 (clobber (reg:QI 31))])]
4315 (define_insn "*callv_c3x"
4316 [(set (match_operand 0 "" "=r,r")
4317 (call (match_operand:QI 1 "call_operand" "T,!o")
4318 (match_operand:QI 2 "general_operand" "")))
4319 (clobber (reg:QI 31))]
4320 ;; Operand 0 and 2 not really used for the C4x.
4321 ;; The C30 doesn't have reg 31.
4327 [(set_attr "type" "call,call")])
4329 ; LAJ requires R11 (31) for the return address
4330 (define_insn "*lajv"
4331 [(set (match_operand 0 "" "=r,r")
4332 (call (match_operand:QI 1 "call_operand" "T,!o")
4333 (match_operand:QI 2 "general_operand" "")))
4334 (clobber (reg:QI 31))]
4335 ;; Operand 0 and 2 not really used in the C30 instruction.
4339 if (which_alternative == 0)
4342 return \"laj\\t%C1\";
4344 return \"call\\t%C1\";
4349 return \"laju\\t%R1\";
4351 return \"callu\\t%R1\";
4353 [(set_attr "type" "laj,laj")])
4355 (define_expand "call_value"
4356 [(parallel [(set (match_operand 0 "" "")
4357 (call (match_operand:QI 1 "call_operand" "")
4358 (match_operand:QI 2 "general_operand" "")))
4359 (clobber (reg:QI 31))])]
4363 (define_insn "return"
4365 "c4x_null_epilogue_p ()"
4367 [(set_attr "type" "rets")])
4369 (define_insn "*return_cc"
4371 (if_then_else (match_operator 0 "comparison_operator"
4372 [(reg:CC 21) (const_int 0)])
4375 "c4x_null_epilogue_p ()"
4377 [(set_attr "type" "rets")])
4379 (define_insn "*return_cc_noov"
4381 (if_then_else (match_operator 0 "comparison_operator"
4382 [(reg:CC_NOOV 21) (const_int 0)])
4385 "GET_CODE(operands[0]) != LE
4386 && GET_CODE(operands[0]) != GE
4387 && GET_CODE(operands[0]) != LT
4388 && GET_CODE(operands[0]) != GT
4389 && c4x_null_epilogue_p ()"
4391 [(set_attr "type" "rets")])
4393 (define_insn "*return_cc_inverse"
4395 (if_then_else (match_operator 0 "comparison_operator"
4396 [(reg:CC 21) (const_int 0)])
4399 "c4x_null_epilogue_p ()"
4401 [(set_attr "type" "rets")])
4403 (define_insn "*return_cc_noov_inverse"
4405 (if_then_else (match_operator 0 "comparison_operator"
4406 [(reg:CC_NOOV 21) (const_int 0)])
4409 "GET_CODE(operands[0]) != LE
4410 && GET_CODE(operands[0]) != GE
4411 && GET_CODE(operands[0]) != LT
4412 && GET_CODE(operands[0]) != GT
4413 && c4x_null_epilogue_p ()"
4415 [(set_attr "type" "rets")])
4418 [(set (pc) (label_ref (match_operand 0 "" "")))]
4421 [(set_attr "type" "jump")])
4426 ; Note we have to emit a dbu instruction if there are no delay slots
4428 ; Also note that GCC will try to reverse a loop to see if it can
4429 ; utilise this instruction. However, if there are more than one
4430 ; memory reference in the loop, it cannot guarantee that reversing
4431 ; the loop will work :( (see check_dbra_loop() in loop.c)
4432 ; Note that the C3x only decrements the 24 LSBs of the address register
4433 ; and the 8 MSBs are untouched. The C4x uses all 32-bits. We thus
4434 ; have an option to disable this instruction.
4437 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,!d,!m")
4439 (label_ref (match_operand 1 "" ""))
4442 (plus:QI (match_dup 0)
4444 "TARGET_DB && TARGET_LOOP_UNSIGNED"
4446 if (IS_ADDR_REG (REGNO (operands[0])))
4448 return \"dbu%#\\t%0,%l1\";
4450 else if (IS_EXT_REG (REGNO (operands[0])))
4452 return \"subi\\t1,%0\\n\\tbge%#\\t%l1\";
4456 return \"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs%#\\t%l1\";
4459 [(set_attr "type" "db")])
4461 (define_insn "decrement_and_branch_until_zero"
4463 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,!d,!m")
4464 (const_int -1)) (const_int 0))
4465 (label_ref (match_operand 1 "" ""))
4468 (plus:QI (match_dup 0)
4470 "TARGET_DB && find_reg_note (insn, REG_NONNEG, 0)"
4472 if (IS_ADDR_REG (REGNO (operands[0])))
4474 return \"dbu%#\\t%0,%l1\";
4476 else if (IS_EXT_REG (REGNO (operands[0])))
4478 return \"subi\\t1,%0\\n\\tbge%#\\t%l1\";
4482 return \"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\t\\tpop\\tr0\\n\\tbhs%#\\t%l1\";
4485 [(set_attr "type" "db")])
4498 ; Default to misc type attr.
4503 ; Should we disallow RPTS if we get a silly number of shifts?
4506 (unspec [(match_operand:QI 0 "src_operand" "g")] 2))
4507 (clobber (reg:QI 25))
4508 (clobber (reg:QI 26))]
4511 [(set_attr "type" "repeat")])
4516 (define_insn "rptb_top"
4517 [(set (reg:QI 25) (label_ref (match_operand 0 "" "")))
4518 (set (reg:QI 26) (label_ref (match_operand 1 "" "")))]
4521 return !final_sequence && c4x_rptb_rpts_p (insn, operands[0])
4522 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
4524 [(set_attr "type" "repeat_top")])
4527 (define_insn "rptb_end"
4529 (if_then_else (ge (match_operand:QI 0 "rc_reg_operand" "v")
4531 (label_ref (match_operand 1 "" ""))
4534 (plus:QI (match_dup 0)
4536 (clobber (reg:QI 25))
4537 (clobber (reg:QI 26))]
4540 return c4x_rptb_nop_p(insn) ? \"nop\" : \"\";"
4541 [(set_attr "type" "repeat")])
4544 (define_expand "decrement_and_branch_on_count"
4545 [(parallel [(set (pc)
4546 (if_then_else (ge (match_operand:QI 0 "rc_reg_operand" "")
4548 (label_ref (match_operand 1 "" ""))
4550 (set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))
4551 (clobber (reg:QI 25))
4552 (clobber (reg:QI 26))])]
4557 (define_expand "movstrqi_small2"
4558 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
4559 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
4560 (use (match_operand:QI 2 "immediate_operand" ""))
4561 (use (match_operand:QI 3 "immediate_operand" ""))
4562 (clobber (match_operand:QI 4 "ext_low_reg_operand" ""))])]
4567 rtx src_mem, dst_mem;
4573 len = INTVAL (operands[2]);
4576 src_mem = gen_rtx_MEM (QImode, src);
4577 dst_mem = gen_rtx_MEM (QImode, dst);
4579 emit_insn (gen_movqi (tmp, src_mem));
4580 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
4581 for (i = 1; i < len; i++)
4583 emit_insn (gen_movqi_parallel (tmp, src_mem, dst_mem, tmp));
4584 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
4585 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
4587 emit_insn (gen_movqi (dst_mem, tmp));
4588 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
4596 ; We should probably get RC loaded when using RPTB automagically...
4597 ; There's probably no need to call _memcpy() if we don't get
4598 ; a immediate operand for the size. We could do a better job here
4599 ; than most memcpy() implementations.
4600 ; operand 2 is the number of bytes
4601 ; operand 3 is the shared alignment
4602 ; operand 4 is a scratch register
4604 (define_insn "movstrqi_small"
4605 [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
4606 (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
4607 (use (match_operand:QI 2 "immediate_operand" "i"))
4608 (use (match_operand:QI 3 "immediate_operand" ""))
4609 (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
4610 (clobber (match_dup 0))
4611 (clobber (match_dup 1))]
4616 int len = INTVAL (operands[2]);
4619 for (i = 0; i < len; i++)
4622 output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
4624 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
4625 output_asm_insn (\"sti\\t%4,*%0++\", operands);
4631 [(set_attr "type" "multi")])
4633 (define_insn "movstrqi_large"
4634 [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
4635 (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
4636 (use (match_operand:QI 2 "immediate_operand" "i"))
4637 (use (match_operand:QI 3 "immediate_operand" ""))
4638 (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
4639 (clobber (match_dup 0))
4640 (clobber (match_dup 1))
4641 (clobber (reg:QI 25))
4642 (clobber (reg:QI 26))
4643 (clobber (reg:QI 27))]
4647 int len = INTVAL (operands[2]);
4649 output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
4650 if (TARGET_RPTS_CYCLES(len))
4652 output_asm_insn (\"rpts\\t%2-2\", operands);
4653 output_asm_insn (\"sti\\t%4,*%0++\", operands);
4654 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
4655 return \"sti\\t%4,*%0++\";
4659 output_asm_insn (\"ldiu\\t%2-2,rc\", operands);
4660 output_asm_insn (\"rptb\\t$+1\", operands);
4661 output_asm_insn (\"sti\\t%4,*%0++\", operands);
4662 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
4664 return \"sti\\t%4,*%0++\";
4668 [(set_attr "type" "repeat")])
4670 ; Operand 2 is the count, operand 3 is the alignment.
4671 (define_expand "movstrqi"
4672 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
4673 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
4674 (use (match_operand:QI 2 "immediate_operand" ""))
4675 (use (match_operand:QI 3 "immediate_operand" ""))])]
4680 if (GET_CODE (operands[2]) != CONST_INT
4681 || INTVAL (operands[2]) > 32767
4682 || INTVAL (operands[2]) <= 0)
4684 FAIL; /* Try to call _memcpy */
4687 operands[0] = copy_to_mode_reg (Pmode, XEXP(operands[0], 0));
4688 operands[1] = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
4689 tmp = gen_reg_rtx (QImode);
4690 if (INTVAL (operands[2]) < 8)
4691 emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2],
4695 emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2],
4702 (define_insn "*cmpstrqi"
4703 [(set (match_operand:QI 0 "reg_operand" "=d")
4704 (compare:QI (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a"))
4705 (mem:BLK (match_operand:QI 2 "addr_reg_operand" "a"))))
4706 (use (match_operand:QI 3 "immediate_operand" "i"))
4707 (use (match_operand:QI 4 "immediate_operand" ""))
4708 (clobber (match_operand:QI 5 "std_reg_operand" "=&c"))
4709 (clobber (reg:QI 21))]
4713 output_asm_insn (\"ldi\\t%3-1,%5\", operands);
4714 output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
4715 output_asm_insn (\"dbeq\\t%5,$1\", operands);
4719 (define_expand "cmpstrqi"
4720 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
4721 (compare:QI (match_operand:BLK 1 "general_operand" "")
4722 (match_operand:BLK 2 "general_operand" "")))
4723 (use (match_operand:QI 3 "immediate_operand" ""))
4724 (use (match_operand:QI 4 "immediate_operand" ""))
4725 (clobber (match_dup 5))
4726 (clobber (reg:QI 21))])]
4730 if (GET_CODE (operands[3]) != CONST_INT
4731 || INTVAL (operands[3]) > 32767
4732 || INTVAL (operands[3]) <= 0)
4736 operands[1] = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
4737 operands[2] = copy_to_mode_reg (Pmode, XEXP(operands[2], 0));
4738 operands[5] = gen_reg_rtx (QImode);
4742 ; TWO OPERAND LONG DOUBLE INSTRUCTIONS
4745 (define_expand "movhf"
4746 [(set (match_operand:HF 0 "src_operand" "")
4747 (match_operand:HF 1 "src_operand" ""))]
4749 "if (CONSTANT_P (operands[1]))
4751 operands[1] = force_const_mem (HFmode, operands[1]);
4752 if (!memory_address_p (HFmode, XEXP (operands[1], 0))
4753 && !reload_in_progress)
4754 operands[1] = change_address (operands[1], HFmode,
4755 XEXP (operands[1], 0));
4758 /* Memory to memory copies must go through a register. */
4759 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
4760 && !reload_in_progress)
4761 operands[1] = force_reg (HFmode, operands[1]);
4764 (define_insn "*movhf_noclobber_reg"
4765 [(set (match_operand:HF 0 "reg_operand" "=h")
4766 (match_operand:HF 1 "reg_operand" "h"))]
4769 [(set_attr "type" "unary")])
4771 ; The predicates could be tightened to disallow constants
4772 (define_insn "*movhf_noclobber"
4773 [(set (match_operand:HF 0 "src_operand" "=h,m")
4774 (match_operand:HF 1 "src_operand" "m,h"))]
4775 "reg_operand (operands[0], HFmode) ^ reg_operand (operands[1], HFmode)"
4777 [(set_attr "type" "multi,multi")])
4779 (define_insn "*movhf_test"
4781 (compare:CC (match_operand:HF 1 "reg_operand" "h")
4783 (clobber (match_scratch:HF 0 "=h"))]
4786 [(set_attr "type" "unarycc")])
4788 (define_insn "*movhf_set"
4790 (compare:CC (match_operand:HF 1 "reg_operand" "h")
4791 (match_operand:HF 2 "fp_zero_operand" "G")))
4792 (set (match_operand:HF 0 "reg_operand" "=h")
4796 [(set_attr "type" "unarycc")])
4799 [(set (match_operand:HF 0 "reg_operand" "")
4800 (match_operand:HF 1 "memory_operand" ""))]
4802 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
4803 (set (match_dup 0) (unspec[(subreg:QI (match_dup 0) 0) (match_dup 3)] 8))]
4804 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
4805 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
4806 PUT_MODE (operands[2], QFmode);
4807 PUT_MODE (operands[3], QImode);")
4810 [(set (match_operand:HF 0 "reg_operand" "")
4811 (match_operand:HF 1 "const_operand" ""))]
4812 "reload_completed && 0"
4813 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
4814 (set (match_dup 0) (unspec[(subreg:QI (match_dup 0) 0) (match_dup 3)] 8))]
4815 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
4816 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
4817 PUT_MODE (operands[2], QFmode);
4818 PUT_MODE (operands[3], QImode);")
4821 [(set (match_operand:HF 0 "memory_operand" "")
4822 (match_operand:HF 1 "reg_operand" ""))]
4824 [(set (match_dup 2) (float_truncate:QF (match_dup 1)))
4825 (set (match_dup 3) (unspec [(match_dup 1)] 9))]
4826 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode);
4827 operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode);
4828 PUT_MODE (operands[2], QFmode);
4829 PUT_MODE (operands[3], QImode);")
4831 (define_insn "*loadhf_float"
4832 [(set (match_operand:HF 0 "reg_operand" "=h")
4833 (float_extend:HF (match_operand:QF 1 "src_operand" "fmH")))]
4837 [(set_attr "type" "unary")])
4839 (define_insn "*loadhf_int"
4840 [(set (match_operand:HF 0 "reg_operand" "=h")
4841 (unspec[(subreg:QI (match_dup 0) 0)
4842 (match_operand:QI 1 "src_operand" "g")] 8))]
4846 [(set_attr "type" "unary")])
4848 (define_insn "*storehf_float"
4849 [(set (match_operand:QF 0 "memory_operand" "=m")
4850 (float_truncate:QF (match_operand:HF 1 "reg_operand" "h")))]
4853 [(set_attr "type" "store")])
4855 (define_insn "*storehf_int"
4856 [(set (match_operand:QI 0 "memory_operand" "=m")
4857 (unspec [(match_operand:HF 1 "reg_operand" "h")] 9))]
4861 [(set_attr "type" "store")])
4863 (define_insn "extendqfhf2"
4864 [(set (match_operand:HF 0 "reg_operand" "=h")
4865 (float_extend:HF (match_operand:QF 1 "reg_operand" "h")))]
4868 [(set_attr "type" "unarycc")])
4870 (define_insn "trunchfqf2"
4871 [(set (match_operand:QF 0 "reg_operand" "=h")
4872 (float_truncate:QF (match_operand:HF 1 "reg_operand" "0")))
4873 (clobber (reg:CC 21))]
4876 [(set_attr "type" "unarycc")])
4881 (define_insn "*pushhf"
4882 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
4883 (match_operand:HF 0 "reg_operand" "h"))]
4886 [(set_attr "type" "multi")])
4889 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
4890 (match_operand:HF 0 "reg_operand" ""))]
4892 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
4893 (float_truncate:QF (match_dup 0)))
4894 (set (mem:QI (pre_inc:QI (reg:QI 20)))
4895 (unspec [(match_dup 0)] 9))]
4898 (define_insn "pushhf_trunc"
4899 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
4900 (float_truncate:QF (match_operand:HF 0 "reg_operand" "h")))]
4903 [(set_attr "type" "push")])
4905 (define_insn "pushhf_int"
4906 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
4907 (unspec [(match_operand:HF 0 "reg_operand" "h")] 9))]
4910 [(set_attr "type" "push")])
4912 ; we can not use this because the popf will destroy the low 8 bits
4913 ;(define_insn "*pophf"
4914 ; [(set (match_operand:HF 0 "reg_operand" "=h")
4915 ; (mem:HF (post_dec:QI (reg:QI 20))))
4916 ; (clobber (reg:CC 21))]
4919 ; [(set_attr "type" "multi")])
4922 [(set (match_operand:HF 0 "reg_operand" "")
4923 (mem:HF (post_dec:QI (reg:QI 20))))
4924 (clobber (reg:CC 21))]
4926 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
4927 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
4928 (clobber (reg:CC 21))])
4929 (parallel [(set (match_dup 0)
4930 (unspec[(subreg:QI (match_dup 0) 0)
4931 (mem:QI (post_dec:QI (reg:QI 20)))] 8))
4932 (clobber (reg:CC 21))])]
4935 (define_insn "*pophf_int"
4936 [(set (match_operand:HF 0 "reg_operand" "=h")
4937 (unspec[(subreg:QI (match_dup 0) 0)
4938 (mem:QI (post_dec:QI (reg:QI 20)))] 8))
4939 (clobber (reg:CC 21))]
4943 [(set_attr "type" "pop")])
4945 (define_insn "*pophf_float"
4946 [(set (match_operand:HF 0 "reg_operand" "=h")
4947 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
4948 (clobber (reg:CC 21))]
4952 [(set_attr "type" "unary")])
4957 (define_insn "fixhfqi_clobber"
4958 [(set (match_operand:QI 0 "reg_operand" "=dc")
4959 (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")))
4960 (clobber (reg:CC 21))]
4963 [(set_attr "type" "unarycc")])
4968 (define_expand "abshf2"
4969 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
4970 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "")))
4971 (clobber (reg:CC_NOOV 21))])]
4975 (define_insn "*abshf2_clobber"
4976 [(set (match_operand:HF 0 "reg_operand" "=h")
4977 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
4978 (clobber (reg:CC_NOOV 21))]
4981 [(set_attr "type" "unarycc")])
4983 (define_insn "*abshf2_test"
4984 [(set (reg:CC_NOOV 21)
4985 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_operand" "h"))
4986 (match_operand:HF 2 "fp_zero_operand" "G")))
4987 (clobber (match_scratch:HF 0 "=h"))]
4990 [(set_attr "type" "unarycc")])
4992 (define_insn "*abshf2_set"
4993 [(set (reg:CC_NOOV 21)
4994 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
4995 (match_operand:HF 2 "fp_zero_operand" "G")))
4996 (set (match_operand:HF 0 "reg_operand" "=h")
4997 (abs:HF (match_dup 1)))]
5001 [(set_attr "type" "unarycc")])
5006 (define_expand "neghf2"
5007 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
5008 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "")))
5009 (clobber (reg:CC 21))])]
5013 (define_insn "*neghf2_clobber"
5014 [(set (match_operand:HF 0 "reg_operand" "=h")
5015 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
5016 (clobber (reg:CC 21))]
5019 [(set_attr "type" "unarycc")])
5021 (define_insn "*neghf2_test"
5023 (compare:CC (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
5024 (match_operand:HF 2 "fp_zero_operand" "G")))
5025 (clobber (match_scratch:HF 0 "=h"))]
5028 [(set_attr "type" "unarycc")])
5030 (define_insn "*neghf2_set"
5032 (compare:CC (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
5033 (match_operand:HF 2 "fp_zero_operand" "G")))
5034 (set (match_operand:HF 0 "reg_operand" "=h")
5035 (neg:HF (match_dup 1)))]
5038 [(set_attr "type" "unarycc")])
5043 (define_insn "*rcpfhf_clobber"
5044 [(set (match_operand:HF 0 "reg_operand" "=h")
5045 (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 5))
5046 (clobber (reg:CC_NOOV 21))]
5049 [(set_attr "type" "unarycc")])
5054 (define_insn "*rsqrfhf_clobber"
5055 [(set (match_operand:HF 0 "reg_operand" "=h")
5056 (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 10))
5057 (clobber (reg:CC_NOOV 21))]
5060 [(set_attr "type" "unarycc")])
5065 (define_insn "*rndhf_clobber"
5066 [(set (match_operand:HF 0 "reg_operand" "=h")
5067 (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 6))
5068 (clobber (reg:CC_NOOV 21))]
5071 [(set_attr "type" "unarycc")])
5074 ; Inlined float square root for C4x
5075 (define_expand "sqrthf2_inline"
5076 [(parallel [(set (match_dup 2)
5077 (unspec [(match_operand:HF 1 "reg_operand" "")] 10))
5078 (clobber (reg:CC_NOOV 21))])
5079 (parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1)))
5080 (clobber (reg:CC_NOOV 21))])
5081 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
5082 (clobber (reg:CC_NOOV 21))])
5083 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
5084 (clobber (reg:CC_NOOV 21))])
5085 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
5086 (clobber (reg:CC_NOOV 21))])
5087 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
5088 (clobber (reg:CC_NOOV 21))])
5089 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
5090 (clobber (reg:CC_NOOV 21))])
5091 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
5092 (clobber (reg:CC_NOOV 21))])
5093 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
5094 (clobber (reg:CC_NOOV 21))])
5095 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
5096 (clobber (reg:CC_NOOV 21))])
5097 (parallel [(set (match_operand:HF 0 "reg_operand" "")
5098 (mult:HF (match_dup 2) (match_dup 1)))
5099 (clobber (reg:CC_NOOV 21))])]
5102 operands[2] = gen_reg_rtx (HFmode);
5103 operands[3] = gen_reg_rtx (HFmode);
5104 operands[4] = gen_reg_rtx (HFmode);
5105 operands[5] = immed_real_const_1 (REAL_VALUE_ATOF (\"0.5\", HFmode), HFmode);
5106 operands[6] = immed_real_const_1 (REAL_VALUE_ATOF (\"1.5\", HFmode), HFmode);
5110 (define_expand "sqrthf2"
5111 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
5112 (sqrt:HF (match_operand:HF 1 "reg_operand" "")))
5113 (clobber (reg:CC 21))])]
5115 "if (TARGET_C3X || !TARGET_INLINE)
5119 emit_insn (gen_sqrthf2_inline( operands[0], operands[1]));
5124 (define_expand "fix_trunchfhi2"
5125 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5126 (fix:HI (match_operand:HF 1 "reg_operand" "")))
5127 (clobber (reg:CC 21))])]
5129 "c4x_emit_libcall (FIX_TRUNCHFHI2_LIBCALL, FIX, HImode, HFmode, 2, operands);
5132 (define_expand "fixuns_trunchfhi2"
5133 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5134 (unsigned_fix:HI (match_operand:HF 1 "reg_operand" "")))
5135 (clobber (reg:CC 21))])]
5137 "c4x_emit_libcall (FIXUNS_TRUNCHFHI2_LIBCALL, UNSIGNED_FIX,
5138 HImode, HFmode, 2, operands);
5142 ; THREE OPERAND LONG DOUBLE INSTRUCTIONS
5148 (define_insn "addhf3"
5149 [(set (match_operand:HF 0 "reg_operand" "=?h,h")
5150 (plus:HF (match_operand:HF 1 "reg_operand" "%h,0")
5151 (match_operand:HF 2 "reg_or_const_operand" "h,H")))
5152 (clobber (reg:CC_NOOV 21))]
5157 [(set_attr "type" "binarycc,binarycc")])
5162 (define_insn "subhf3"
5163 [(set (match_operand:HF 0 "reg_operand" "=?h,h,h")
5164 (minus:HF (match_operand:HF 1 "reg_or_const_operand" "h,0,H")
5165 (match_operand:HF 2 "reg_or_const_operand" "h,H,0")))
5166 (clobber (reg:CC_NOOV 21))]
5172 [(set_attr "type" "binarycc,binarycc,binarycc")])
5177 ; The C3x MPYF only uses 24 bit precision while the C4x uses 32 bit precison.
5179 (define_expand "mulhf3"
5180 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
5181 (mult:HF (match_operand:HF 1 "reg_operand" "h")
5182 (match_operand:HF 2 "reg_operand" "h")))
5183 (clobber (reg:CC_NOOV 21))])]
5187 c4x_emit_libcall3 (MULHF3_LIBCALL, MULT, HFmode, operands);
5192 (define_insn "*mulhf3_c40"
5193 [(set (match_operand:HF 0 "reg_operand" "=?h,h")
5194 (mult:HF (match_operand:HF 1 "reg_operand" "%h,0")
5195 (match_operand:HF 2 "reg_or_const_operand" "h,hH")))
5196 (clobber (reg:CC_NOOV 21))]
5201 [(set_attr "type" "binarycc,binarycc")])
5206 (define_expand "cmphf"
5208 (compare:CC (match_operand:HF 0 "reg_operand" "")
5209 (match_operand:HF 1 "reg_or_const_operand" "")))]
5211 "c4x_compare_op0 = operands[0];
5212 c4x_compare_op1 = operands[1];
5215 (define_insn "*cmphf"
5217 (compare:CC (match_operand:HF 0 "reg_operand" "h")
5218 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
5221 [(set_attr "type" "compare")])
5223 (define_insn "*cmphf_noov"
5224 [(set (reg:CC_NOOV 21)
5225 (compare:CC_NOOV (match_operand:HF 0 "reg_operand" "h")
5226 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
5229 [(set_attr "type" "compare")])
5231 ; Inlined float divide for C4x
5232 (define_expand "divhf3_inline"
5233 [(parallel [(set (match_dup 3)
5234 (unspec [(match_operand:HF 2 "reg_operand" "")] 5))
5235 (clobber (reg:CC_NOOV 21))])
5236 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
5237 (clobber (reg:CC_NOOV 21))])
5238 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
5239 (clobber (reg:CC_NOOV 21))])
5240 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
5241 (clobber (reg:CC_NOOV 21))])
5242 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
5243 (clobber (reg:CC_NOOV 21))])
5244 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
5245 (clobber (reg:CC_NOOV 21))])
5246 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
5247 (clobber (reg:CC_NOOV 21))])
5248 (parallel [(set (match_operand:HF 0 "reg_operand" "")
5249 (mult:HF (match_operand:HF 1 "reg_operand" "")
5251 (clobber (reg:CC_NOOV 21))])]
5254 operands[3] = gen_reg_rtx (HFmode);
5255 operands[4] = gen_reg_rtx (HFmode);
5256 operands[5] = CONST2_RTX (HFmode);
5259 (define_expand "divhf3"
5260 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
5261 (div:HF (match_operand:HF 1 "reg_operand" "")
5262 (match_operand:HF 2 "reg_operand" "")))
5263 (clobber (reg:CC 21))])]
5265 "if (TARGET_C3X || !TARGET_INLINE)
5267 c4x_emit_libcall3 (DIVHF3_LIBCALL, DIV, HFmode, operands);
5272 emit_insn (gen_divhf3_inline( operands[0], operands[1], operands[2]));
5279 ; TWO OPERAND LONG LONG INSTRUCTIONS
5282 ; We could load some constants using define_splits for the C30
5283 ; in the large memory model---these would emit shift and or insns.
5284 (define_expand "movhi"
5285 [(set (match_operand:HI 0 "src_operand" "")
5286 (match_operand:HI 1 "src_operand" ""))]
5288 "if (CONSTANT_P (operands[1]))
5290 /* We don't need to force all constants into memory.
5291 This could be improved.... */
5292 operands[1] = force_const_mem (HImode, operands[1]);
5293 if (!memory_address_p (HImode, XEXP (operands[1], 0))
5294 && !reload_in_progress)
5295 operands[1] = change_address (operands[1], HImode,
5296 XEXP (operands[1], 0));
5299 /* Memory to memory copies must go through a register. */
5300 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
5301 && !reload_in_progress)
5302 operands[1] = force_reg (HImode, operands[1]);
5305 ; The constraints for movhi must include 'r' if we don't
5306 ; restrict HImode regnos to start on an even number, since
5307 ; we can get RC, R8 allocated as a pair. We want more
5308 ; votes for FP_REGS so we use dr as the constraints.
5309 (define_insn "*movhi_noclobber"
5310 [(set (match_operand:HI 0 "src_operand" "=dr,m")
5311 (match_operand:HI 1 "src_operand" "drm,r"))]
5312 "reg_operand (operands[0], HImode)
5313 || reg_operand (operands[1], HImode)"
5315 [(set_attr "type" "multi,multi")])
5318 [(set (match_operand:HI 0 "src_operand" "")
5319 (match_operand:HI 1 "src_operand" ""))]
5321 && (reg_operand (operands[0], HImode) || reg_operand (operands[1], HImode))"
5322 [(set (match_dup 2) (match_dup 3))
5323 (set (match_dup 4) (match_dup 5))]
5324 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
5325 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
5326 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
5327 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
5330 (define_insn "extendqihi2"
5331 [(set (match_operand:HI 0 "reg_operand" "=dc")
5332 (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
5333 (clobber (reg:CC 21))]
5336 [(set_attr "type" "multi")])
5339 [(set (match_operand:HI 0 "reg_operand" "=?dc")
5340 (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
5341 (clobber (reg:CC 21))]
5342 "reload_completed && TARGET_C3X"
5343 [(set (match_dup 2) (match_dup 1))
5344 (set (match_dup 3) (match_dup 2))
5345 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 3) (const_int 31)))
5346 (clobber (reg:CC 21))])]
5347 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
5348 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
5351 [(set (match_operand:HI 0 "reg_operand" "=?dc")
5352 (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
5353 (clobber (reg:CC 21))]
5354 "reload_completed && !TARGET_C3X"
5355 [(set (match_dup 2) (match_dup 1))
5356 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 2) (const_int 31)))
5357 (clobber (reg:CC 21))])]
5358 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
5359 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
5361 (define_insn "zero_extendqihi2"
5362 [(set (match_operand:HI 0 "reg_operand" "=?dc")
5363 (zero_extend:HI (match_operand:QI 1 "src_operand" "g")))
5364 (clobber (reg:CC 21))]
5367 [(set_attr "type" "multi")])
5369 ; If operand0 and operand1 are the same register we don't need
5372 [(set (match_operand:HI 0 "reg_operand" "=?dc")
5373 (zero_extend:HI (match_operand:QI 1 "src_operand" "g")))
5374 (clobber (reg:CC 21))]
5376 [(set (match_dup 2) (match_dup 1))
5377 (set (match_dup 3) (const_int 0))]
5378 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
5379 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
5384 (define_insn "*pushhi"
5385 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
5386 (match_operand:HI 0 "reg_operand" "r"))]
5389 [(set_attr "type" "multi")])
5392 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
5393 (match_operand:HI 0 "reg_operand" ""))]
5395 [(set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 2))
5396 (set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 3))]
5397 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
5398 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
5400 (define_insn "*pophi"
5401 [(set (match_operand:HI 0 "reg_operand" "=r")
5402 (mem:HI (post_dec:QI (reg:QI 20))))
5403 (clobber (reg:CC 21))]
5406 [(set_attr "type" "multi")])
5409 [(set (match_operand:HI 0 "reg_operand" "")
5410 (mem:HI (pre_inc:QI (reg:QI 20))))]
5412 [(set (match_dup 2) (mem:QI (pre_inc:QI (reg:QI 20))))
5413 (set (match_dup 3) (mem:QI (pre_inc:QI (reg:QI 20))))]
5414 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
5415 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
5420 (define_insn "neghi2"
5421 [(set (match_operand:HI 0 "ext_reg_operand" "=d")
5422 (neg:HI (match_operand:HI 1 "src_operand" "rm")))
5423 (clobber (reg:CC_NOOV 21))]
5426 [(set_attr "type" "multi")])
5429 [(set (match_operand:HI 0 "ext_reg_operand" "")
5430 (neg:HI (match_operand:HI 1 "src_operand" "")))
5431 (clobber (reg:CC_NOOV 21))]
5433 [(parallel [(set (reg:CC_NOOV 21)
5434 (compare:CC_NOOV (neg:QI (match_dup 3))
5436 (set (match_dup 2) (neg:QI (match_dup 3)))])
5437 (parallel [(set (match_dup 4) (neg:QI (match_dup 5)))
5438 (use (reg:CC_NOOV 21))
5439 (clobber (reg:CC_NOOV 21))])]
5440 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
5441 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
5442 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
5443 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
5445 (define_insn "one_cmplhi2"
5446 [(set (match_operand:HI 0 "reg_operand" "=r")
5447 (not:HI (match_operand:HI 1 "src_operand" "rm")))
5448 (clobber (reg:CC 21))]
5451 [(set_attr "type" "multi")])
5454 [(set (match_operand:HI 0 "reg_operand" "")
5455 (not:HI (match_operand:HI 1 "src_operand" "")))
5456 (clobber (reg:CC 21))]
5458 [(parallel [(set (match_dup 2) (not:QI (match_dup 3)))
5459 (clobber (reg:CC 21))])
5460 (parallel [(set (match_dup 4) (not:QI (match_dup 5)))
5461 (clobber (reg:CC 21))])]
5462 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
5463 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
5464 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
5465 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
5467 (define_expand "floathiqf2"
5468 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
5469 (float:QF (match_operand:HI 1 "src_operand" "")))
5470 (clobber (reg:CC 21))])]
5472 "c4x_emit_libcall (FLOATHIQF2_LIBCALL, FLOAT, QFmode, HImode, 2, operands);
5475 (define_expand "floatunshiqf2"
5476 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
5477 (unsigned_float:QF (match_operand:HI 1 "src_operand" "")))
5478 (clobber (reg:CC 21))])]
5480 "c4x_emit_libcall (FLOATUNSHIQF2_LIBCALL, UNSIGNED_FLOAT,
5481 QFmode, HImode, 2, operands);
5484 (define_expand "floathihf2"
5485 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
5486 (float:HF (match_operand:HI 1 "src_operand" "")))
5487 (clobber (reg:CC 21))])]
5489 "c4x_emit_libcall (FLOATHIHF2_LIBCALL, FLOAT, HFmode, HImode, 2, operands);
5492 (define_expand "floatunshihf2"
5493 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
5494 (unsigned_float:HF (match_operand:HI 1 "src_operand" "")))
5495 (clobber (reg:CC 21))])]
5497 "c4x_emit_libcall (FLOATUNSHIHF2_LIBCALL, UNSIGNED_FLOAT,
5498 HFmode, HImode, 2, operands);
5503 ; THREE OPERAND LONG LONG INSTRUCTIONS
5506 (define_expand "addhi3"
5507 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
5508 (plus:HI (match_operand:HI 1 "src_operand" "")
5509 (match_operand:HI 2 "src_operand" "")))
5510 (clobber (reg:CC_NOOV 21))])]
5512 "legitimize_operands (PLUS, operands, HImode);")
5514 (define_insn "*addhi3_clobber"
5515 [(set (match_operand:HI 0 "ext_reg_operand" "=d,?d,d")
5516 (plus:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
5517 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
5518 (clobber (reg:CC_NOOV 21))]
5519 "valid_operands (PLUS, operands, HImode)"
5521 [(set_attr "type" "multi,multi,multi")])
5524 [(set (match_operand:HI 0 "ext_reg_operand" "")
5525 (plus:HI (match_operand:HI 1 "src_operand" "")
5526 (match_operand:HI 2 "src_operand" "")))
5527 (clobber (reg:CC_NOOV 21))]
5529 [(parallel [(set (reg:CC_NOOV 21)
5530 (compare:CC_NOOV (plus:QI (match_dup 4) (match_dup 5))
5532 (set (match_dup 3) (plus:QI (match_dup 4) (match_dup 5)))])
5533 (parallel [(set (match_dup 6) (plus:QI (match_dup 7) (match_dup 8)))
5534 (use (reg:CC_NOOV 21))
5535 (clobber (reg:CC_NOOV 21))])]
5536 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
5537 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
5538 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
5539 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
5540 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
5541 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
5543 (define_expand "subhi3"
5544 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
5545 (minus:HI (match_operand:HI 1 "src_operand" "")
5546 (match_operand:HI 2 "src_operand" "")))
5547 (clobber (reg:CC_NOOV 21))])]
5549 "legitimize_operands (MINUS, operands, HImode);")
5552 (define_insn "*subhi3_clobber"
5553 [(set (match_operand:HI 0 "ext_reg_operand" "=d,?d,d")
5554 (minus:HI (match_operand:HI 1 "src_operand" "rR,rS<>,0")
5555 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
5556 (clobber (reg:CC_NOOV 21))]
5557 "valid_operands (MINUS, operands, HImode)"
5559 [(set_attr "type" "multi,multi,multi")])
5562 [(set (match_operand:HI 0 "ext_reg_operand" "")
5563 (minus:HI (match_operand:HI 1 "src_operand" "")
5564 (match_operand:HI 2 "src_operand" "")))
5565 (clobber (reg:CC_NOOV 21))]
5567 [(parallel [(set (reg:CC_NOOV 21)
5568 (compare:CC_NOOV (minus:QI (match_dup 4) (match_dup 5))
5570 (set (match_dup 3) (minus:QI (match_dup 4) (match_dup 5)))])
5571 (parallel [(set (match_dup 6) (minus:QI (match_dup 7) (match_dup 8)))
5572 (use (reg:CC_NOOV 21))
5573 (clobber (reg:CC_NOOV 21))])]
5574 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
5575 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
5576 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
5577 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
5578 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
5579 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
5581 (define_expand "iorhi3"
5582 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5583 (ior:HI (match_operand:HI 1 "src_operand" "")
5584 (match_operand:HI 2 "src_operand" "")))
5585 (clobber (reg:CC 21))])]
5587 "legitimize_operands (IOR, operands, HImode);")
5589 (define_insn "*iorhi3_clobber"
5590 [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
5591 (ior:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
5592 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
5593 (clobber (reg:CC 21))]
5594 "valid_operands (IOR, operands, HImode)"
5596 [(set_attr "type" "multi,multi,multi")])
5599 [(set (match_operand:HI 0 "reg_operand" "")
5600 (ior:HI (match_operand:HI 1 "src_operand" "")
5601 (match_operand:HI 2 "src_operand" "")))
5602 (clobber (reg:CC 21))]
5604 [(parallel [(set (match_dup 3) (ior:QI (match_dup 4) (match_dup 5)))
5605 (clobber (reg:CC 21))])
5606 (parallel [(set (match_dup 6) (ior:QI (match_dup 7) (match_dup 8)))
5607 (clobber (reg:CC 21))])]
5608 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
5609 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
5610 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
5611 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
5612 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
5613 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
5615 (define_expand "andhi3"
5616 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5617 (and:HI (match_operand:HI 1 "src_operand" "")
5618 (match_operand:HI 2 "src_operand" "")))
5619 (clobber (reg:CC 21))])]
5621 "legitimize_operands (AND, operands, HImode);")
5623 (define_insn "*andhi3_clobber"
5624 [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
5625 (and:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
5626 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
5627 (clobber (reg:CC 21))]
5628 "valid_operands (AND, operands, HImode)"
5630 [(set_attr "type" "multi,multi,multi")])
5633 [(set (match_operand:HI 0 "reg_operand" "")
5634 (and:HI (match_operand:HI 1 "src_operand" "")
5635 (match_operand:HI 2 "src_operand" "")))
5636 (clobber (reg:CC 21))]
5638 [(parallel [(set (match_dup 3) (and:QI (match_dup 4) (match_dup 5)))
5639 (clobber (reg:CC 21))])
5640 (parallel [(set (match_dup 6) (and:QI (match_dup 7) (match_dup 8)))
5641 (clobber (reg:CC 21))])]
5642 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
5643 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
5644 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
5645 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
5646 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
5647 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
5649 (define_expand "xorhi3"
5650 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5651 (xor:HI (match_operand:HI 1 "src_operand" "")
5652 (match_operand:HI 2 "src_operand" "")))
5653 (clobber (reg:CC 21))])]
5655 "legitimize_operands (AND, operands, HImode);")
5658 (define_insn "*xorhi3_clobber"
5659 [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
5660 (xor:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
5661 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
5662 (clobber (reg:CC 21))]
5663 "valid_operands (XOR, operands, HImode)"
5665 [(set_attr "type" "multi,multi,multi")])
5668 [(set (match_operand:HI 0 "reg_operand" "")
5669 (xor:HI (match_operand:HI 1 "src_operand" "")
5670 (match_operand:HI 2 "src_operand" "")))
5671 (clobber (reg:CC 21))]
5673 [(parallel [(set (match_dup 3) (xor:QI (match_dup 4) (match_dup 5)))
5674 (clobber (reg:CC 21))])
5675 (parallel [(set (match_dup 6) (xor:QI (match_dup 7) (match_dup 8)))
5676 (clobber (reg:CC 21))])]
5677 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
5678 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
5679 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
5680 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
5681 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
5682 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
5684 ; This should do all the dirty work with define_split
5685 (define_expand "ashlhi3"
5686 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5687 (ashift:HI (match_operand:HI 1 "src_operand" "")
5688 (match_operand:QI 2 "src_operand" "")))
5689 (clobber (reg:CC 21))])]
5691 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
5693 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
5694 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
5695 rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
5696 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
5699 emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
5701 emit_insn (gen_movqi (op0hi, op1lo));
5702 emit_insn (gen_movqi (op0lo, const0_rtx));
5705 emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
5708 ; %0.lo = %1.lo << %2
5709 ; %0.hi = (%1.hi << %2 ) | (%1.lo >> (32 - %2))
5710 ; This algorithm should work for shift counts greater than 32
5711 (define_expand "ashlhi3_reg"
5712 [(use (match_operand:HI 1 "src_operand" ""))
5713 (use (match_operand:HI 0 "reg_operand" ""))
5714 /* If the shift count is greater than 32 this will give zero. */
5715 (parallel [(set (match_dup 7)
5716 (ashift:QI (match_dup 3)
5717 (match_operand:QI 2 "reg_operand" "")))
5718 (clobber (reg:CC 21))])
5719 /* If the shift count is greater than 32 this will give zero. */
5720 (parallel [(set (match_dup 8)
5721 (ashift:QI (match_dup 4) (match_dup 2)))
5722 (clobber (reg:CC 21))])
5723 (parallel [(set (match_dup 10)
5724 (plus:QI (match_dup 2) (const_int -32)))
5725 (clobber (reg:CC_NOOV 21))])
5726 /* If the shift count is greater than 32 this will do a left shift. */
5727 (parallel [(set (match_dup 9)
5728 (lshiftrt:QI (match_dup 3) (neg:QI (match_dup 10))))
5729 (clobber (reg:CC 21))])
5730 (set (match_dup 5) (match_dup 7))
5731 (parallel [(set (match_dup 6)
5732 (ior:QI (match_dup 8) (match_dup 9)))
5733 (clobber (reg:CC 21))])]
5736 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
5737 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
5738 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
5739 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
5740 operands[7] = gen_reg_rtx (QImode); /* lo << count */
5741 operands[8] = gen_reg_rtx (QImode); /* hi << count */
5742 operands[9] = gen_reg_rtx (QImode); /* lo >> (32 - count) */
5743 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
5746 ; This should do all the dirty work with define_split
5747 (define_expand "lshrhi3"
5748 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5749 (lshiftrt:HI (match_operand:HI 1 "src_operand" "")
5750 (match_operand:QI 2 "src_operand" "")))
5751 (clobber (reg:CC 21))])]
5753 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
5755 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
5756 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
5757 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
5758 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
5761 emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
5763 emit_insn (gen_movqi (op0lo, op1hi));
5764 emit_insn (gen_movqi (op0hi, const0_rtx));
5767 emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
5770 ; %0.hi = %1.hi >> %2
5771 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
5772 ; This algorithm should work for shift counts greater than 32
5773 (define_expand "lshrhi3_reg"
5774 [(use (match_operand:HI 1 "src_operand" ""))
5775 (use (match_operand:HI 0 "reg_operand" ""))
5776 (parallel [(set (match_dup 11)
5777 (neg:QI (match_operand:QI 2 "reg_operand" "")))
5778 (clobber (reg:CC_NOOV 21))])
5779 /* If the shift count is greater than 32 this will give zero. */
5780 (parallel [(set (match_dup 7)
5781 (lshiftrt:QI (match_dup 3)
5782 (neg:QI (match_dup 11))))
5783 (clobber (reg:CC 21))])
5784 /* If the shift count is greater than 32 this will give zero. */
5785 (parallel [(set (match_dup 8)
5786 (lshiftrt:QI (match_dup 4)
5787 (neg:QI (match_dup 11))))
5788 (clobber (reg:CC 21))])
5789 (parallel [(set (match_dup 10)
5790 (plus:QI (match_dup 11) (const_int 32)))
5791 (clobber (reg:CC_NOOV 21))])
5792 /* If the shift count is greater than 32 this will do an arithmetic
5793 right shift. However, we need a logical right shift. */
5794 (parallel [(set (match_dup 9)
5795 (ashift:QI (match_dup 4) (unspec [(match_dup 10)] 3)))
5796 (clobber (reg:CC 21))])
5797 (set (match_dup 6) (match_dup 8))
5798 (parallel [(set (match_dup 5)
5799 (ior:QI (match_dup 7) (match_dup 9)))
5800 (clobber (reg:CC 21))])]
5803 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
5804 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
5805 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
5806 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
5807 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
5808 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
5809 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
5810 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
5811 operands[11] = gen_reg_rtx (QImode); /* -count */
5814 ; This should do all the dirty work with define_split
5815 (define_expand "ashrhi3"
5816 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
5817 (ashiftrt:HI (match_operand:HI 1 "src_operand" "")
5818 (match_operand:QI 2 "src_operand" "")))
5819 (clobber (reg:CC 21))])]
5821 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
5823 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
5824 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
5825 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
5826 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
5829 emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
5831 emit_insn (gen_movqi (op0lo, op1hi));
5832 emit_insn (gen_ashrqi3 (op0hi, op1hi, GEN_INT (31)));
5835 emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
5838 ; %0.hi = %1.hi >> %2
5839 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
5840 ; This algorithm should work for shift counts greater than 32
5841 (define_expand "ashrhi3_reg"
5842 [(use (match_operand:HI 1 "src_operand" ""))
5843 (use (match_operand:HI 0 "reg_operand" ""))
5844 (parallel [(set (match_dup 11)
5845 (neg:QI (match_operand:QI 2 "reg_operand" "")))
5846 (clobber (reg:CC_NOOV 21))])
5847 /* If the shift count is greater than 32 this will give zero. */
5848 (parallel [(set (match_dup 7)
5849 (lshiftrt:QI (match_dup 3)
5850 (neg:QI (match_dup 11))))
5851 (clobber (reg:CC 21))])
5852 /* If the shift count is greater than 32 this will give zero. */
5853 (parallel [(set (match_dup 8)
5854 (ashiftrt:QI (match_dup 4)
5855 (neg:QI (match_dup 11))))
5856 (clobber (reg:CC 21))])
5857 (parallel [(set (match_dup 10)
5858 (plus:QI (match_dup 11) (const_int 32)))
5859 (clobber (reg:CC_NOOV 21))])
5860 /* If the shift count is greater than 32 this will do an arithmetic
5862 (parallel [(set (match_dup 9)
5863 (ashift:QI (match_dup 4) (match_dup 10)))
5864 (clobber (reg:CC 21))])
5865 (set (match_dup 6) (match_dup 8))
5866 (parallel [(set (match_dup 5)
5867 (ior:QI (match_dup 7) (match_dup 9)))
5868 (clobber (reg:CC 21))])]
5871 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
5872 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
5873 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
5874 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
5875 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
5876 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
5877 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
5878 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
5879 operands[11] = gen_reg_rtx (QImode); /* -count */
5882 (define_expand "cmphi"
5884 (compare:CC (match_operand:HI 0 "src_operand" "")
5885 (match_operand:HI 1 "src_operand" "")))]
5887 "legitimize_operands (COMPARE, operands, HImode);
5888 c4x_compare_op0 = operands[0];
5889 c4x_compare_op1 = operands[1];
5892 ; This works only before reload because we need 2 extra registers.
5893 ; Use unspec to avoid recursive split.
5896 (compare:CC (match_operand:HI 0 "src_operand" "")
5897 (match_operand:HI 1 "src_operand" "")))]
5899 [(parallel [(set (reg:CC 21)
5900 (unspec [(compare:CC (match_dup 0)
5902 (clobber (match_scratch:QI 2 ""))
5903 (clobber (match_scratch:QI 3 ""))])]
5907 [(set (reg:CC_NOOV 21)
5908 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
5909 (match_operand:HI 1 "src_operand" "")))]
5911 [(parallel [(set (reg:CC_NOOV 21)
5912 (unspec [(compare:CC_NOOV (match_dup 0)
5914 (clobber (match_scratch:QI 2 ""))
5915 (clobber (match_scratch:QI 3 ""))])]
5918 ; This is normally not used. The define splits above are used first.
5919 (define_insn "*cmphi"
5921 (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
5922 (match_operand:HI 1 "src_operand" "R,rS<>")))]
5923 "valid_operands (COMPARE, operands, HImode)"
5926 int use_ir1 = (reg_operand (operands[0], HImode)
5927 && REG_P (operands[0])
5928 && REGNO (operands[0]) == IR1_REGNO)
5929 || (reg_operand (operands[1], HImode)
5930 && REG_P (operands[1])
5931 && REGNO (operands[1]) == IR1_REGNO);
5934 output_asm_insn (\"push\\tir1\", operands);
5936 output_asm_insn (\"push\\tbk\", operands);
5937 output_asm_insn (\"push\\tr0\", operands);
5938 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
5941 output_asm_insn (\"ldiu\\tst,ir1\", operands);
5942 output_asm_insn (\"or\\t07bh,ir1\", operands);
5946 output_asm_insn (\"ldiu\\tst,bk\", operands);
5947 output_asm_insn (\"or\\t07bh,bk\", operands);
5949 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
5951 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
5953 output_asm_insn (\"and3\\tbk,st,bk\", operands);
5954 output_asm_insn (\"pop\\tr0\", operands);
5957 output_asm_insn (\"ldiu\\tir1,st\", operands);
5958 output_asm_insn (\"pop\\tir1\", operands);
5962 output_asm_insn (\"ldiu\\tbk,st\", operands);
5963 output_asm_insn (\"pop\\tbk\", operands);
5967 [(set_attr "type" "multi")])
5969 (define_insn "*cmphi_noov"
5970 [(set (reg:CC_NOOV 21)
5971 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
5972 (match_operand:HI 1 "src_operand" "R,rS<>")))]
5973 "valid_operands (COMPARE, operands, HImode)"
5976 int use_ir1 = (reg_operand (operands[0], HImode)
5977 && REG_P (operands[0])
5978 && REGNO (operands[0]) == IR1_REGNO)
5979 || (reg_operand (operands[1], HImode)
5980 && REG_P (operands[1])
5981 && REGNO (operands[1]) == IR1_REGNO);
5984 output_asm_insn (\"push\\tir1\", operands);
5986 output_asm_insn (\"push\\tbk\", operands);
5987 output_asm_insn (\"push\\tr0\", operands);
5988 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
5991 output_asm_insn (\"ldiu\\tst,ir1\", operands);
5992 output_asm_insn (\"or\\t07bh,ir1\", operands);
5996 output_asm_insn (\"ldiu\\tst,bk\", operands);
5997 output_asm_insn (\"or\\t07bh,bk\", operands);
5999 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
6001 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
6003 output_asm_insn (\"and3\\tbk,st,bk\", operands);
6004 output_asm_insn (\"pop\\tr0\", operands);
6007 output_asm_insn (\"ldiu\\tir1,st\", operands);
6008 output_asm_insn (\"pop\\tir1\", operands);
6012 output_asm_insn (\"ldiu\\tbk,st\", operands);
6013 output_asm_insn (\"pop\\tbk\", operands);
6017 [(set_attr "type" "multi")])
6020 (define_insn "cmphi_cc"
6022 (unspec [(compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
6023 (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
6024 (clobber (match_scratch:QI 2 "=&d,&d"))
6025 (clobber (match_scratch:QI 3 "=&c,&c"))]
6026 "valid_operands (COMPARE, operands, HImode)"
6028 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
6029 output_asm_insn (\"ldiu\\tst,%3\", operands);
6030 output_asm_insn (\"or\\t07bh,%3\", operands);
6031 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
6032 output_asm_insn (\"and\\t%3,st\", operands);
6034 [(set_attr "type" "multi")])
6036 (define_insn "cmphi_cc_noov"
6037 [(set (reg:CC_NOOV 21)
6038 (unspec [(compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
6039 (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
6040 (clobber (match_scratch:QI 2 "=&d,&d"))
6041 (clobber (match_scratch:QI 3 "=&c,&c"))]
6042 "valid_operands (COMPARE, operands, HImode)"
6044 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
6045 output_asm_insn (\"ldiu\\tst,%3\", operands);
6046 output_asm_insn (\"or\\t07bh,%3\", operands);
6047 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
6048 output_asm_insn (\"and\\t%3,st\", operands);
6050 [(set_attr "type" "multi")])
6052 (define_expand "mulhi3"
6053 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6054 (mult:HI (match_operand:HI 1 "src_operand" "")
6055 (match_operand:HI 2 "src_operand" "")))
6056 (clobber (reg:CC 21))])]
6058 "c4x_emit_libcall3 (MULHI3_LIBCALL, MULT, HImode, operands);
6061 (define_expand "udivhi3"
6062 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6063 (udiv:HI (match_operand:HI 1 "src_operand" "")
6064 (match_operand:HI 2 "src_operand" "")))
6065 (clobber (reg:CC 21))])]
6067 "c4x_emit_libcall3 (UDIVHI3_LIBCALL, UDIV, HImode, operands);
6070 (define_expand "divhi3"
6071 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6072 (div:HI (match_operand:HI 1 "src_operand" "")
6073 (match_operand:HI 2 "src_operand" "")))
6074 (clobber (reg:CC 21))])]
6076 "c4x_emit_libcall3 (DIVHI3_LIBCALL, DIV, HImode, operands);
6079 (define_expand "umodhi3"
6080 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6081 (umod:HI (match_operand:HI 1 "src_operand" "")
6082 (match_operand:HI 2 "src_operand" "")))
6083 (clobber (reg:CC 21))])]
6085 "c4x_emit_libcall3 (UMODHI3_LIBCALL, UMOD, HImode, operands);
6088 (define_expand "modhi3"
6089 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6090 (mod:HI (match_operand:HI 1 "src_operand" "")
6091 (match_operand:HI 2 "src_operand" "")))
6092 (clobber (reg:CC 21))])]
6094 "c4x_emit_libcall3 (MODHI3_LIBCALL, MOD, HImode, operands);
6106 ; bCC label ; abnormal loop termination
6107 ; dbu aN, loop ; normal loop termination
6115 ; Which moves the bCC condition outside the inner loop for free.
6118 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
6119 [(reg:CC 21) (const_int 0)])
6120 (label_ref (match_operand 2 "" ""))
6125 (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
6128 (label_ref (match_operand 1 "" ""))
6131 (plus:QI (match_dup 0)
6133 "!c4x_label_conflict (insn, operands[2], operands[1])"
6134 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
6137 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
6138 [(reg:CC 21) (const_int 0)])
6139 (label_ref (match_operand 2 "" ""))
6144 (ne (match_operand:QI 0 "addr_reg_operand" "+a")
6146 (label_ref (match_operand 1 "" ""))
6149 (plus:QI (match_dup 0)
6151 "!c4x_label_conflict (insn, operands[2], operands[1])"
6152 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
6155 ; Peepholes to convert 'call label; rets' into jump label
6158 [(parallel [(call (match_operand:QI 0 "call_operand" "T,!o")
6159 (match_operand:QI 1 "general_operand" ""))
6160 (clobber (reg:QI 31))])
6162 "c4x_null_epilogue_p ()"
6166 [(set_attr "type" "jump,jump")])
6169 [(parallel [(set (match_operand 0 "" "")
6170 (call (match_operand:QI 1 "call_operand" "T,!o")
6171 (match_operand:QI 2 "general_operand" "")))
6172 (clobber (reg:QI 31))])
6174 "c4x_null_epilogue_p ()"
6178 [(set_attr "type" "jump,jump")])
6181 ; Peepholes for parallel instructions
6184 [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6185 (match_operand:QI 1 "par_ind_operand" ""))
6186 (set (match_operand:QI 2 "ext_low_reg_operand" "")
6187 (match_operand:QI 3 "par_ind_operand" ""))]
6188 "(REGNO (operands[0]) != REGNO (operands[2]))
6189 && !c4x_address_conflict (operands[1], operands[3], 0, 0)"
6190 "ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2")
6192 ; load occurs before store if 1 and 2 point to same address
6194 [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6195 (match_operand:QI 1 "par_ind_operand" ""))
6196 (set (match_operand:QI 2 "par_ind_operand" "")
6197 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6198 "(REGNO (operands[0]) != REGNO (operands[3]))
6199 && !c4x_address_conflict (operands[1], operands[2], 0, 1)"
6200 "ldi\\t%1,%0\\n||\\tsti\\t%3,%2")
6202 ; load occurs before store if 0 and 3 point to same address
6204 [(set (match_operand:QI 0 "par_ind_operand" "")
6205 (match_operand:QI 1 "ext_low_reg_operand" ""))
6206 (set (match_operand:QI 2 "ext_low_reg_operand" "")
6207 (match_operand:QI 3 "par_ind_operand" ""))]
6208 "(REGNO (operands[1]) != REGNO (operands[2]))
6209 && !c4x_address_conflict (operands[0], operands[3], 1, 0)"
6210 "ldi\\t%3,%2\\n||\\tsti\\t%1,%0")
6213 [(set (match_operand:QI 0 "par_ind_operand" "")
6214 (match_operand:QI 1 "ext_low_reg_operand" ""))
6215 (set (match_operand:QI 2 "par_ind_operand" "")
6216 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6217 "!c4x_address_conflict (operands[0], operands[2], 1, 1)"
6218 "sti\\t%1,%0\\n||\\tsti\\t%3,%2")
6220 ; This peephole should be unnecessary with my patches to flow.c
6221 ; for better autoincrement detection
6223 [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6224 (mem:QF (match_operand:QI 1 "addr_reg_operand" "")))
6225 (set (match_operand:QF 2 "ext_low_reg_operand" "")
6226 (mem:QF (plus:QI (match_dup 1) (const_int 1))))
6227 (parallel [(set (match_dup 1) (plus:QI (match_dup 1) (const_int 2)))
6228 (clobber (reg:CC_NOOV 21))])]
6230 "ldf\\t*%1++,%0\\n\\tldf\\t*%1++,%2")
6233 [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6234 (match_operand:QF 1 "par_ind_operand" ""))
6235 (set (match_operand:QF 2 "ext_low_reg_operand" "")
6236 (match_operand:QF 3 "par_ind_operand" ""))]
6237 "(REGNO (operands[0]) != REGNO (operands[2]))
6238 && !c4x_address_conflict (operands[1], operands[3], 0, 1)"
6239 "ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2")
6241 ; This peephole should be unnecessary with my patches to flow.c
6242 ; for better autoincrement detection
6244 [(set (mem:QF (match_operand:QI 0 "addr_reg_operand" ""))
6245 (match_operand:QF 1 "ext_low_reg_operand" ""))
6246 (set (mem:QF (plus:QI (match_dup 0) (const_int 1)))
6247 (match_operand:QF 2 "ext_low_reg_operand" ""))
6248 (parallel [(set (match_dup 0) (plus:QI (match_dup 0) (const_int 2)))
6249 (clobber (reg:CC_NOOV 21))])]
6251 "stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
6254 [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6255 (match_operand:QF 1 "par_ind_operand" ""))
6256 (set (match_operand:QF 2 "par_ind_operand" "")
6257 (match_operand:QF 3 "ext_low_reg_operand" ""))]
6258 "(REGNO (operands[0]) != REGNO (operands[3]))"
6259 "ldf\\t%1,%0\\n||\\tstf\\t%3,%2")
6262 [(set (match_operand:QF 0 "par_ind_operand" "")
6263 (match_operand:QF 1 "ext_low_reg_operand" ""))
6264 (set (match_operand:QF 2 "ext_low_reg_operand" "")
6265 (match_operand:QF 3 "par_ind_operand" ""))]
6266 "!c4x_address_conflict (operands[0], operands[3], 1, 1)"
6267 "ldf\\t%3,%2\\n||\\tstf\\t%1,%0")
6270 [(set (match_operand:QF 0 "par_ind_operand" "")
6271 (match_operand:QF 1 "ext_low_reg_operand" ""))
6272 (set (match_operand:QF 2 "par_ind_operand" "")
6273 (match_operand:QF 3 "ext_low_reg_operand" ""))]
6274 "!c4x_address_conflict (operands[0], operands[2], 1, 1)"
6275 "stf1\\t%1,%0\\n||\\tstf2\\t%3,%2")
6278 [(parallel [(set (reg:CC_NOOV 21)
6279 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "par_ind_operand" ""))
6280 (match_operand:QF 2 "fp_zero_operand" "")))
6281 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6282 (abs:QF (match_dup 1)))])
6283 (set (match_operand:QF 3 "par_ind_operand" "")
6284 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6285 "(REGNO (operands[0]) != REGNO (operands[4]))"
6286 "absf\\t%1,%0\\n||\\tstf\\t%4,%3")
6289 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6290 (abs:QF (match_operand:QF 1 "par_ind_operand" "")))
6291 (clobber (reg:CC_NOOV 21))])
6292 (set (match_operand:QF 2 "par_ind_operand" "")
6293 (match_operand:QF 3 "ext_low_reg_operand" ""))]
6294 "(REGNO (operands[0]) != REGNO (operands[3]))"
6295 "absf\\t%1,%0\\n||\\tstf\\t%3,%2")
6298 [(parallel [(set (reg:CC_NOOV 21)
6299 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "par_ind_operand" ""))
6301 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6302 (abs:QI (match_dup 1)))])
6303 (set (match_operand:QI 2 "par_ind_operand" "")
6304 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6305 "(REGNO (operands[0]) != REGNO (operands[3]))"
6306 "absi\\t%1,%0\\n||\\tsti\\t%3,%2")
6309 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6310 (abs:QI (match_operand:QI 1 "par_ind_operand" "")))
6311 (clobber (reg:CC_NOOV 21))])
6312 (set (match_operand:QI 2 "par_ind_operand" "")
6313 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6314 "(REGNO (operands[0]) != REGNO (operands[3]))"
6315 "absi\\t%1,%0\\n||\\tsti\\t%3,%2")
6318 [(parallel [(set (reg:CC_NOOV 21)
6319 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6320 (match_operand:QI 2 "par_ind_operand" ""))
6322 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6323 (plus:QI (match_dup 1) (match_dup 2)))])
6324 (set (match_operand:QI 3 "par_ind_operand" "")
6325 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6326 "(REGNO (operands[0]) != REGNO (operands[4]))"
6327 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6330 [(parallel [(set (reg:CC_NOOV 21)
6331 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "par_ind_operand" "")
6332 (match_operand:QI 2 "ext_low_reg_operand" ""))
6334 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6335 (plus:QI (match_dup 1) (match_dup 2)))])
6336 (set (match_operand:QI 3 "par_ind_operand" "")
6337 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6338 "(REGNO (operands[0]) != REGNO (operands[4]))"
6339 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6342 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6343 (plus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6344 (match_operand:QI 2 "par_ind_operand" "")))
6345 (clobber (reg:CC_NOOV 21))])
6346 (set (match_operand:QI 3 "par_ind_operand" "")
6347 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6348 "(REGNO (operands[0]) != REGNO (operands[4]))"
6349 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6352 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6353 (plus:QI (match_operand:QI 1 "par_ind_operand" "")
6354 (match_operand:QI 2 "ext_low_reg_operand" "")))
6355 (clobber (reg:CC_NOOV 21))])
6356 (set (match_operand:QI 3 "par_ind_operand" "")
6357 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6358 "(REGNO (operands[0]) != REGNO (operands[4]))"
6359 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6362 [(parallel [(set (reg:CC_NOOV 21)
6363 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6364 (match_operand:QF 2 "par_ind_operand" ""))
6365 (match_operand:QF 3 "fp_zero_operand" "")))
6366 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6367 (plus:QF (match_dup 1) (match_dup 2)))])
6368 (set (match_operand:QF 4 "par_ind_operand" "")
6369 (match_operand:QF 5 "ext_low_reg_operand" ""))]
6370 "(REGNO (operands[0]) != REGNO (operands[5]))"
6371 "addf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
6374 [(parallel [(set (reg:CC_NOOV 21)
6375 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "par_ind_operand" "")
6376 (match_operand:QF 2 "ext_low_reg_operand" ""))
6377 (match_operand:QF 3 "fp_zero_operand" "")))
6378 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6379 (plus:QF (match_dup 1) (match_dup 2)))])
6380 (set (match_operand:QF 4 "par_ind_operand" "")
6381 (match_operand:QF 5 "ext_low_reg_operand" ""))]
6382 "(REGNO (operands[0]) != REGNO (operands[5]))"
6383 "addf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
6386 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6387 (plus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6388 (match_operand:QF 2 "par_ind_operand" "")))
6389 (clobber (reg:CC_NOOV 21))])
6390 (set (match_operand:QF 3 "par_ind_operand" "")
6391 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6392 "(REGNO (operands[0]) != REGNO (operands[4]))"
6393 "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
6396 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6397 (plus:QF (match_operand:QF 1 "par_ind_operand" "")
6398 (match_operand:QF 2 "ext_low_reg_operand" "")))
6399 (clobber (reg:CC_NOOV 21))])
6400 (set (match_operand:QF 3 "par_ind_operand" "")
6401 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6402 "(REGNO (operands[0]) != REGNO (operands[4]))"
6403 "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
6406 [(parallel [(set (reg:CC 21)
6407 (compare:CC (and:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6408 (match_operand:QI 2 "par_ind_operand" ""))
6410 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6411 (and:QI (match_dup 1) (match_dup 2)))])
6412 (set (match_operand:QI 3 "par_ind_operand" "")
6413 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6414 "(REGNO (operands[0]) != REGNO (operands[4]))"
6415 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6418 [(parallel [(set (reg:CC 21)
6419 (compare:CC (and:QI (match_operand:QI 1 "par_ind_operand" "")
6420 (match_operand:QI 2 "ext_low_reg_operand" ""))
6422 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6423 (and:QI (match_dup 1) (match_dup 2)))])
6424 (set (match_operand:QI 3 "par_ind_operand" "")
6425 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6426 "(REGNO (operands[0]) != REGNO (operands[4]))"
6427 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6430 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6431 (and:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6432 (match_operand:QI 2 "par_ind_operand" "")))
6433 (clobber (reg:CC 21))])
6434 (set (match_operand:QI 3 "par_ind_operand" "")
6435 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6436 "(REGNO (operands[0]) != REGNO (operands[4]))"
6437 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6440 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6441 (and:QI (match_operand:QI 1 "par_ind_operand" "")
6442 (match_operand:QI 2 "ext_low_reg_operand" "")))
6443 (clobber (reg:CC 21))])
6444 (set (match_operand:QI 3 "par_ind_operand" "")
6445 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6446 "(REGNO (operands[0]) != REGNO (operands[4]))"
6447 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6450 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6451 (ashift:QI (match_operand:QI 1 "par_ind_operand" "")
6452 (match_operand:QI 2 "ext_low_reg_operand" "")))
6453 (clobber (reg:CC 21))])
6454 (set (match_operand:QI 3 "par_ind_operand" "")
6455 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6456 "(REGNO (operands[0]) != REGNO (operands[4]))"
6457 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6460 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6461 (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "")
6462 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" ""))))
6463 (clobber (reg:CC 21))])
6464 (set (match_operand:QI 3 "par_ind_operand" "")
6465 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6466 "(REGNO (operands[0]) != REGNO (operands[4]))"
6467 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6470 [(parallel [(set (reg:CC 21)
6471 (compare:CC (fix:QI (match_operand:QF 1 "par_ind_operand" ""))
6473 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6474 (fix:QI (match_dup 1)))])
6475 (set (match_operand:QI 2 "par_ind_operand" "")
6476 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6477 "(REGNO (operands[0]) != REGNO (operands[3]))"
6478 "fix\\t%1,%0\\n||\\tsti\\t%3,%2")
6481 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6482 (fix:QI (match_operand:QF 1 "par_ind_operand" "")))
6483 (clobber (reg:CC 21))])
6484 (set (match_operand:QI 2 "par_ind_operand" "")
6485 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6486 "(REGNO (operands[0]) != REGNO (operands[3]))"
6487 "fix\\t%1,%0\\n||\\tsti\\t%3,%2")
6490 [(parallel [(set (reg:CC 21)
6491 (compare:CC (float:QF (match_operand:QI 1 "par_ind_operand" ""))
6492 (match_operand:QF 2 "fp_zero_operand" "")))
6493 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6494 (float:QF (match_dup 1)))])
6495 (set (match_operand:QF 3 "par_ind_operand" "")
6496 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6497 "(REGNO (operands[0]) != REGNO (operands[4]))"
6498 "float\\t%1,%0\\n||\\tstf\\t%4,%3")
6501 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6502 (float:QF (match_operand:QI 1 "par_ind_operand" "")))
6503 (clobber (reg:CC 21))])
6504 (set (match_operand:QF 2 "par_ind_operand" "")
6505 (match_operand:QF 3 "ext_low_reg_operand" ""))]
6506 "(REGNO (operands[0]) != REGNO (operands[3]))"
6507 "float\\t%1,%0\\n||\\tstf\\t%3,%2")
6510 [(parallel [(set (reg:CC_NOOV 21)
6511 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6512 (match_operand:QI 2 "par_ind_operand" ""))
6514 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6515 (mult:QI (match_dup 1) (match_dup 2)))])
6516 (set (match_operand:QI 3 "par_ind_operand" "")
6517 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6518 "(REGNO (operands[0]) != REGNO (operands[4]))"
6519 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6522 [(parallel [(set (reg:CC_NOOV 21)
6523 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "par_ind_operand" "")
6524 (match_operand:QI 2 "ext_low_reg_operand" ""))
6526 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6527 (mult:QI (match_dup 1) (match_dup 2)))])
6528 (set (match_operand:QI 3 "par_ind_operand" "")
6529 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6530 "(REGNO (operands[0]) != REGNO (operands[4]))"
6531 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6534 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6535 (mult:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6536 (match_operand:QI 2 "par_ind_operand" "")))
6537 (clobber (reg:CC 21))])
6538 (set (match_operand:QI 3 "par_ind_operand" "")
6539 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6540 "(REGNO (operands[0]) != REGNO (operands[4]))"
6541 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6544 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6545 (mult:QI (match_operand:QI 1 "par_ind_operand" "")
6546 (match_operand:QI 2 "ext_low_reg_operand" "")))
6547 (clobber (reg:CC 21))])
6548 (set (match_operand:QI 3 "par_ind_operand" "")
6549 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6550 "(REGNO (operands[0]) != REGNO (operands[4]))"
6551 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6554 [(parallel [(set (reg:CC_NOOV 21)
6555 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6556 (match_operand:QF 2 "par_ind_operand" ""))
6557 (match_operand:QF 3 "fp_zero_operand" "")))
6558 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6559 (mult:QF (match_dup 1) (match_dup 2)))])
6560 (set (match_operand:QF 4 "par_ind_operand" "")
6561 (match_operand:QF 5 "ext_low_reg_operand" ""))]
6562 "(REGNO (operands[0]) != REGNO (operands[5]))"
6563 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
6566 [(parallel [(set (reg:CC_NOOV 21)
6567 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "par_ind_operand" "")
6568 (match_operand:QF 2 "ext_low_reg_operand" ""))
6569 (match_operand:QF 3 "fp_zero_operand" "")))
6570 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6571 (mult:QF (match_dup 1) (match_dup 2)))])
6572 (set (match_operand:QF 4 "par_ind_operand" "")
6573 (match_operand:QF 5 "ext_low_reg_operand" ""))]
6574 "(REGNO (operands[0]) != REGNO (operands[5]))"
6575 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
6578 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6579 (mult:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6580 (match_operand:QF 2 "par_ind_operand" "")))
6581 (clobber (reg:CC 21))])
6582 (set (match_operand:QF 3 "par_ind_operand" "")
6583 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6584 "(REGNO (operands[0]) != REGNO (operands[4]))"
6585 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
6588 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6589 (mult:QF (match_operand:QF 1 "par_ind_operand" "")
6590 (match_operand:QF 2 "ext_low_reg_operand" "")))
6591 (clobber (reg:CC 21))])
6592 (set (match_operand:QF 3 "par_ind_operand" "")
6593 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6594 "(REGNO (operands[0]) != REGNO (operands[4]))"
6595 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
6598 [(parallel [(set (reg:CC_NOOV 21)
6599 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "par_ind_operand" ""))
6600 (match_operand:QF 2 "fp_zero_operand" "")))
6601 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6602 (neg:QF (match_dup 1)))])
6603 (set (match_operand:QF 3 "par_ind_operand" "")
6604 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6605 "(REGNO (operands[0]) != REGNO (operands[4]))"
6606 "negf\\t%1,%0\\n||\\tstf\\t%4,%3")
6609 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6610 (neg:QF (match_operand:QF 1 "par_ind_operand" "")))
6611 (clobber (reg:CC_NOOV 21))])
6612 (set (match_operand:QF 2 "par_ind_operand" "")
6613 (match_operand:QF 3 "ext_low_reg_operand" ""))]
6614 "(REGNO (operands[0]) != REGNO (operands[3]))"
6615 "negf\\t%1,%0\\n||\\tstf\\t%3,%2")
6618 [(parallel [(set (reg:CC_NOOV 21)
6619 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "par_ind_operand" ""))
6621 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6622 (neg:QI (match_dup 1)))])
6623 (set (match_operand:QI 2 "par_ind_operand" "")
6624 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6625 "(REGNO (operands[0]) != REGNO (operands[3]))"
6626 "negi\\t%1,%0\\n||\\tsti\\t%3,%2")
6629 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6630 (neg:QI (match_operand:QI 1 "par_ind_operand" "")))
6631 (clobber (reg:CC_NOOV 21))])
6632 (set (match_operand:QI 2 "par_ind_operand" "")
6633 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6634 "(REGNO (operands[0]) != REGNO (operands[3]))"
6635 "negi\\t%1,%0\\n||\\tsti\\t%3,%2")
6638 [(parallel [(set (reg:CC 21)
6639 (compare:CC (not:QI (match_operand:QI 1 "par_ind_operand" ""))
6641 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6642 (not:QI (match_dup 1)))])
6643 (set (match_operand:QI 2 "par_ind_operand" "")
6644 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6645 "(REGNO (operands[0]) != REGNO (operands[3]))"
6646 "not\\t%1,%0\\n||\\tsti\\t%3,%2")
6649 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6650 (not:QI (match_operand:QI 1 "par_ind_operand" "")))
6651 (clobber (reg:CC 21))])
6652 (set (match_operand:QI 2 "par_ind_operand" "")
6653 (match_operand:QI 3 "ext_low_reg_operand" ""))]
6654 "(REGNO (operands[0]) != REGNO (operands[3]))"
6655 "not\\t%1,%0\\n||\\tsti\\t%3,%2")
6658 [(parallel [(set (reg:CC 21)
6659 (compare:CC (ior:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6660 (match_operand:QI 2 "par_ind_operand" ""))
6662 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6663 (ior:QI (match_dup 1) (match_dup 2)))])
6664 (set (match_operand:QI 3 "par_ind_operand" "")
6665 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6666 "(REGNO (operands[0]) != REGNO (operands[4]))"
6667 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6670 [(parallel [(set (reg:CC 21)
6671 (compare:CC (ior:QI (match_operand:QI 1 "par_ind_operand" "")
6672 (match_operand:QI 2 "ext_low_reg_operand" ""))
6674 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6675 (ior:QI (match_dup 1) (match_dup 2)))])
6676 (set (match_operand:QI 3 "par_ind_operand" "")
6677 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6678 "(REGNO (operands[0]) != REGNO (operands[4]))"
6679 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6682 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6683 (ior:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6684 (match_operand:QI 2 "par_ind_operand" "")))
6685 (clobber (reg:CC 21))])
6686 (set (match_operand:QI 3 "par_ind_operand" "")
6687 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6688 "(REGNO (operands[0]) != REGNO (operands[4]))"
6689 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6692 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6693 (ior:QI (match_operand:QI 1 "par_ind_operand" "")
6694 (match_operand:QI 2 "ext_low_reg_operand" "")))
6695 (clobber (reg:CC 21))])
6696 (set (match_operand:QI 3 "par_ind_operand" "")
6697 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6698 "(REGNO (operands[0]) != REGNO (operands[4]))"
6699 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6702 [(parallel [(set (reg:CC_NOOV 21)
6703 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6704 (match_operand:QI 2 "par_ind_operand" ""))
6706 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6707 (minus:QI (match_dup 1) (match_dup 2)))])
6708 (set (match_operand:QI 3 "par_ind_operand" "")
6709 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6710 "(REGNO (operands[0]) != REGNO (operands[4]))"
6711 "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6714 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6715 (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6716 (match_operand:QI 2 "par_ind_operand" "")))
6717 (clobber (reg:CC_NOOV 21))])
6718 (set (match_operand:QI 3 "par_ind_operand" "")
6719 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6720 "(REGNO (operands[0]) != REGNO (operands[4]))"
6721 "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6724 [(parallel [(set (reg:CC_NOOV 21)
6725 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6726 (match_operand:QF 2 "par_ind_operand" ""))
6727 (match_operand:QF 3 "fp_zero_operand" "")))
6728 (set (match_operand:QF 0 "ext_low_reg_operand" "")
6729 (minus:QF (match_dup 1) (match_dup 2)))])
6730 (set (match_operand:QF 4 "par_ind_operand" "")
6731 (match_operand:QF 5 "ext_low_reg_operand" ""))]
6732 "(REGNO (operands[0]) != REGNO (operands[5]))"
6733 "subf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
6736 [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
6737 (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
6738 (match_operand:QF 2 "par_ind_operand" "")))
6739 (clobber (reg:CC_NOOV 21))])
6740 (set (match_operand:QF 3 "par_ind_operand" "")
6741 (match_operand:QF 4 "ext_low_reg_operand" ""))]
6742 "(REGNO (operands[0]) != REGNO (operands[4]))"
6743 "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
6746 [(parallel [(set (reg:CC 21)
6747 (compare:CC (xor:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6748 (match_operand:QI 2 "par_ind_operand" ""))
6750 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6751 (xor:QI (match_dup 1) (match_dup 2)))])
6752 (set (match_operand:QI 3 "par_ind_operand" "")
6753 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6754 "(REGNO (operands[0]) != REGNO (operands[4]))"
6755 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6758 [(parallel [(set (reg:CC 21)
6759 (compare:CC (xor:QI (match_operand:QI 1 "par_ind_operand" "")
6760 (match_operand:QI 2 "ext_low_reg_operand" ""))
6762 (set (match_operand:QI 0 "ext_low_reg_operand" "")
6763 (xor:QI (match_dup 1) (match_dup 2)))])
6764 (set (match_operand:QI 3 "par_ind_operand" "")
6765 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6766 "(REGNO (operands[0]) != REGNO (operands[4]))"
6767 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6770 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6771 (xor:QI (match_operand:QI 1 "ext_low_reg_operand" "")
6772 (match_operand:QI 2 "par_ind_operand" "")))
6773 (clobber (reg:CC 21))])
6774 (set (match_operand:QI 3 "par_ind_operand" "")
6775 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6776 "(REGNO (operands[0]) != REGNO (operands[4]))"
6777 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
6780 [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
6781 (xor:QI (match_operand:QI 1 "par_ind_operand" "")
6782 (match_operand:QI 2 "ext_low_reg_operand" "")))
6783 (clobber (reg:CC 21))])
6784 (set (match_operand:QI 3 "par_ind_operand" "")
6785 (match_operand:QI 4 "ext_low_reg_operand" ""))]
6786 "(REGNO (operands[0]) != REGNO (operands[4]))"
6787 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")