1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
4 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
5 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Set the following so that some of the macros expand to function
25 calls to simplify debugging. */
28 /* RUN-TIME TARGET SPECIFICATION */
32 /* Name of the c4x assembler */
34 #define ASM_PROG "c4x-as"
36 /* Name of the c4x linker */
38 #define LD_PROG "c4x-ld"
40 /* Define assembler options. */
43 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
44 %{!m30:%{!m40:-m40}}}}}}} \
55 %{mmemparm:-p} %{mregparm:-r} \
56 %{!mmemparm:%{!mregparm:-r}} \
57 %{mbig:-b} %{msmall:-s} \
58 %{!msmall:%{!mbig:-b}}"
60 /* Define linker options. */
63 %{m30:--architecture c3x} \
64 %{m31:--architecture c3x} \
65 %{m32:--architecture c3x} \
66 %{mcpu=30:--architecture c3x} \
67 %{mcpu=31:--architecture c3x} \
68 %{mcpu=32:--architecture c3x}"
70 /* Define C preprocessor options. */
73 %{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
74 %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
75 %{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
76 %{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
77 %{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
78 %{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
79 %{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
80 %{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
81 %{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
82 %{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
83 %{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
84 %{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
85 %{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
86 %{!mmemparm:%{!mregparm:-D_REGPARM }} \
87 %{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
88 %{!msmall:%{!mbig:-D_BIGMODEL }} \
89 %{finline-functions:-D_INLINE }"
91 /* Specify the end file to link with. */
93 #define ENDFILE_SPEC ""
95 /* Target compilation option flags. */
97 #define SMALL_MEMORY_FLAG 0x0000001 /* small memory model */
98 #define MPYI_FLAG 0x0000002 /* use 24-bit MPYI for C3x */
99 #define FAST_FIX_FLAG 0x0000004 /* fast fixing of floats */
100 #define RPTS_FLAG 0x0000008 /* allow use of RPTS */
101 #define C3X_FLAG 0x0000010 /* emit C3x code */
102 #define TI_FLAG 0x0000020 /* be compatible with TI assembler */
103 #define PARANOID_FLAG 0x0000040 /* be paranoid about DP reg. in ISRs */
104 #define MEMPARM_FLAG 0x0000080 /* pass arguments on stack */
105 #define DEVEL_FLAG 0x0000100 /* enable features under development */
106 #define RPTB_FLAG 0x0000200 /* enable repeat block */
107 #define BK_FLAG 0x0000400 /* use BK as general register */
108 #define DB_FLAG 0x0000800 /* use decrement and branch for C3x */
109 #define DEBUG_FLAG 0x0001000 /* enable debugging of GCC */
110 #define HOIST_FLAG 0x0002000 /* force constants into registers */
111 #define LOOP_UNSIGNED_FLAG 0x0004000 /* allow unsigned loop counters */
112 #define FORCE_FLAG 0x0008000 /* force op0 and op1 to be same */
113 #define PRESERVE_FLOAT_FLAG 0x0010000 /* save all 40 bits for floats */
114 #define PARALLEL_PACK_FLAG 0x0020000 /* allow parallel insn packing */
115 #define PARALLEL_MPY_FLAG 0x0040000 /* allow MPY||ADD, MPY||SUB insns */
116 #define ALIASES_FLAG 0x0080000 /* assume mem refs possibly aliased */
118 #define C30_FLAG 0x0100000 /* emit C30 code */
119 #define C31_FLAG 0x0200000 /* emit C31 code */
120 #define C32_FLAG 0x0400000 /* emit C32 code */
121 #define C40_FLAG 0x1000000 /* emit C40 code */
122 #define C44_FLAG 0x2000000 /* emit C44 code */
124 /* Run-time compilation parameters selecting different hardware subsets.
126 Macro to define tables used to set the flags.
127 This is a list in braces of triplets in braces,
128 each pair being { "NAME", VALUE, "DESCRIPTION" }
129 where VALUE is the bits to set or minus the bits to clear.
130 An empty string NAME is used to identify the default VALUE. */
132 #define TARGET_SWITCHES \
133 { { "small", SMALL_MEMORY_FLAG, \
134 "Small memory model" }, \
135 { "big", -SMALL_MEMORY_FLAG, \
136 "Big memory model" }, \
137 { "mpyi", MPYI_FLAG, \
138 "Use MPYI instruction for C3x" }, \
139 { "no-mpyi", -MPYI_FLAG, \
140 "Do not use MPYI instruction for C3x" }, \
141 { "fast-fix", FAST_FIX_FLAG, \
142 "Use fast but approximate float to integer conversion" }, \
143 { "no-fast-fix", -FAST_FIX_FLAG, \
144 "Use slow but accurate float to integer conversion" }, \
145 { "rpts", RPTS_FLAG, \
146 "Enable use of RTPS instruction" }, \
147 { "no-rpts", -RPTS_FLAG, \
148 "Disable use of RTPS instruction" }, \
149 { "rptb", RPTB_FLAG, \
150 "Enable use of RTPB instruction" }, \
151 { "no-rptb", -RPTB_FLAG, \
152 "Disable use of RTPB instruction" }, \
154 "Generate code for C30 CPU"}, \
156 "Generate code for C31 CPU"}, \
158 "Generate code for C32 CPU"}, \
160 "Generate code for C40 CPU"}, \
162 "Generate code for C44 CPU"}, \
164 "Emit code compatible with TI tools"}, \
165 { "no-ti", -TI_FLAG, \
166 "Emit code to use GAS extensions"}, \
167 { "paranoid", PARANOID_FLAG, \
168 "Save DP across ISR in small memory model" }, \
169 { "no-paranoid", -PARANOID_FLAG, \
170 "Don't save DP across ISR in small memory model" }, \
171 { "isr-dp-reload", PARANOID_FLAG, \
172 "Save DP across ISR in small memory model" }, \
173 { "no-isr-dp-reload", -PARANOID_FLAG, \
174 "Don't save DP across ISR in small memory model" }, \
175 { "memparm", MEMPARM_FLAG, \
176 "Pass arguments on the stack" }, \
177 { "regparm", -MEMPARM_FLAG, \
178 "Pass arguments in registers" }, \
179 { "devel", DEVEL_FLAG, \
180 "Enable new features under development" }, \
181 { "no-devel", -DEVEL_FLAG, \
182 "Disable new features under development" }, \
184 "Use the BK register as a general purpose register" }, \
185 { "no-bk", -BK_FLAG, \
186 "Do not allocate BK register" }, \
188 "Enable use of DB instruction" }, \
189 { "no-db", -DB_FLAG, \
190 "Disable use of DB instruction" }, \
191 { "debug", DEBUG_FLAG, \
192 "Enable debugging" }, \
193 { "no-debug", -DEBUG_FLAG, \
194 "Disable debugging" }, \
195 { "hoist", HOIST_FLAG, \
196 "Force constants into registers to improve hoisting" }, \
197 { "no-hoist", -HOIST_FLAG, \
198 "Don't force constants into registers" }, \
199 { "force", FORCE_FLAG, \
200 "Force RTL generation to emit valid 3 operand insns" }, \
201 { "no-force", -FORCE_FLAG, \
202 "Allow RTL generation to emit invalid 3 operand insns" }, \
203 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
204 "Allow unsigned interation counts for RPTB/DB" }, \
205 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
206 "Disallow unsigned iteration counts for RPTB/DB" }, \
207 { "preserve-float", PRESERVE_FLOAT_FLAG, \
208 "Preserve all 40 bits of FP reg across call" }, \
209 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
210 "Only preserve 32 bits of FP reg across call" }, \
211 { "parallel-insns", PARALLEL_PACK_FLAG, \
212 "Enable parallel instructions" }, \
213 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
214 "Disable parallel instructions" }, \
215 { "parallel-mpy", PARALLEL_MPY_FLAG, \
216 "Enable MPY||ADD and MPY||SUB instructions" }, \
217 { "no-parallel-insns", -PARALLEL_PACK_FLAG, \
218 "Disable MPY||ADD and MPY||SUB instructions" }, \
219 { "aliases", ALIASES_FLAG, \
220 "Assume that pointers may be aliased" }, \
221 { "no-aliases", -ALIASES_FLAG, \
222 "Assume that pointers not aliased" }, \
223 { "", TARGET_DEFAULT, ""} }
225 /* Default target switches */
227 /* Play safe, not the fastest code. */
228 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_PACK_FLAG \
229 | PARALLEL_MPY_FLAG | RPTB_FLAG
232 Max iteration count for RPTB/RPTS is 2^31 + 1.
233 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
234 RPTS blocks interrupts. */
237 extern int target_flags;
239 #define TARGET_INLINE 1 /* Inline MPYI */
240 #define TARGET_PARALLEL 1 /* Enable parallel insns in MD */
241 #define TARGET_SMALL_REG_CLASS 0
243 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
244 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
245 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
246 #define TARGET_RPTS (target_flags & RPTS_FLAG)
247 #define TARGET_TI (target_flags & TI_FLAG)
248 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
249 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
250 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
251 #define TARGET_RPTB (target_flags & RPTB_FLAG \
253 #define TARGET_BK (target_flags & BK_FLAG)
254 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
255 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
256 #define TARGET_HOIST (target_flags & HOIST_FLAG)
257 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
258 #define TARGET_FORCE (target_flags & FORCE_FLAG)
259 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
260 #define TARGET_PARALLEL_PACK (TARGET_RPTB \
261 && (target_flags & PARALLEL_PACK_FLAG) \
263 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL_PACK \
264 && (target_flags & PARALLEL_MPY_FLAG))
265 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
267 #define TARGET_C3X (target_flags & C3X_FLAG)
268 #define TARGET_C30 (target_flags & C30_FLAG)
269 #define TARGET_C31 (target_flags & C31_FLAG)
270 #define TARGET_C32 (target_flags & C32_FLAG)
271 #define TARGET_C40 (target_flags & C40_FLAG)
272 #define TARGET_C44 (target_flags & C44_FLAG)
274 /* Define some options to control code generation. */
275 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
276 #define TARGET_EXPOSE_LDP 0
278 /* -mrpts allows the use of the RPTS instruction irregardless.
279 -mrpts=max-cycles will use RPTS if the number of cycles is constant
280 and less than max-cycles. */
282 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
284 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
286 /* -mcpu=XX with XX = target DSP version number */
288 /* This macro is similar to `TARGET_SWITCHES' but defines names of
289 command options that have values. Its definition is an
290 initializer with a subgrouping for each command option.
292 Each subgrouping contains a string constant, that defines the
293 fixed part of the option name, and the address of a variable.
294 The variable, type `char *', is set to the variable part of the
295 given option if the fixed part matches. The actual option name
296 is made by appending `-m' to the specified name.
298 Here is an example which defines `-mshort-data-NUMBER'. If the
299 given option is `-mshort-data-512', the variable `m88k_short_data'
300 will be set to the string `"512"'.
302 extern char *m88k_short_data;
303 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
305 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
307 #define TARGET_OPTIONS \
308 { {"rpts=", &c4x_rpts_cycles_string, \
309 "Specify maximum number of iterations for RPTS" }, \
310 {"cpu=", &c4x_cpu_version_string, \
311 "Select CPU to generate code for" } }
313 /* Sometimes certain combinations of command options do not make sense
314 on a particular target machine. You can define a macro
315 `OVERRIDE_OPTIONS' to take account of this. This macro, if
316 defined, is executed once just after all the command options have
319 extern void c4x_override_options ();
320 #define OVERRIDE_OPTIONS c4x_override_options ()
322 /* Define this to change the optimizations performed by default. */
323 extern void c4x_optimization_options ();
324 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL,SIZE)
326 /* Run Time Target Specification */
328 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)" );
332 #define BITS_BIG_ENDIAN 0
333 #define BYTES_BIG_ENDIAN 0
334 #define WORDS_BIG_ENDIAN 0
336 /* Technically, we are little endian, but we put the floats out as
337 whole longs and this makes GCC put them out in the right order. */
339 #define FLOAT_WORDS_BIG_ENDIAN 1
341 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
342 all integral and floating point data types are stored in memory as
343 32-bits (floating point types can be stored as 40-bits in the
344 extended precision registers), so sizeof(char) = sizeof(short) =
345 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
347 #define BITS_PER_UNIT 32
348 #define BITS_PER_WORD 32
349 #define UNITS_PER_WORD 1
350 #define POINTER_SIZE 32
351 #define PARM_BOUNDARY 32
352 #define STACK_BOUNDARY 32
353 #define FUNCTION_BOUNDARY 32
354 #define BIGGEST_ALIGNMENT 32
355 #define EMPTY_FIELD_BOUNDARY 32
356 #define STRICT_ALIGNMENT 0
357 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
358 #define MAX_FIXED_MODE_SIZE 64 /* HImode */
360 /* Number of bits in the high and low parts of a two stage
361 load of an immediate constant. */
362 #define BITS_PER_HIGH 16
363 #define BITS_PER_LO_SUM 16
365 /* Use the internal floating point stuff in the compiler and not the
366 host floating point stuff. */
368 #define REAL_ARITHMETIC
370 /* Define register numbers */
372 /* Extended-precision registers */
383 /* Auxiliary (address) registers */
394 /* Data page register */
398 /* Index registers */
403 /* Block size register */
411 /* Status register */
415 /* Misc. interrupt registers */
417 #define DIE_REGNO 22 /* C4x only */
418 #define IE_REGNO 22 /* C3x only */
419 #define IIE_REGNO 23 /* C4x only */
420 #define IF_REGNO 23 /* C3x only */
421 #define IIF_REGNO 24 /* C4x only */
422 #define IOF_REGNO 24 /* C3x only */
424 /* Repeat block registers */
430 /* Additional extended-precision registers */
432 #define R8_REGNO 28 /* C4x only */
433 #define R9_REGNO 29 /* C4x only */
434 #define R10_REGNO 30 /* C4x only */
435 #define R11_REGNO 31 /* C4x only */
437 #define FIRST_PSEUDO_REGISTER 32
439 /* Extended precision registers (low set) */
441 #define IS_R0R1_REG(r) ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
442 #define IS_R2R3_REG(r) ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
443 #define IS_EXT_LOW_REG(r) ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
445 /* Extended precision registers (high set) */
447 #define IS_EXT_HIGH_REG(r) (! TARGET_C3X \
448 && ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
449 /* Address registers */
451 #define IS_AUX_REG(r) (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
452 #define IS_ADDR_REG(r) IS_AUX_REG(r)
453 #define IS_DP_REG(r) ((r) == DP_REGNO)
454 #define IS_INDEX_REG(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
455 #define IS_SP_REG(r) ((r) == SP_REGNO)
456 #define IS_BK_REG(r) (TARGET_BK && (r) == BK_REGNO)
460 #define IS_ST_REG(r) ((r) == ST_REGNO)
461 #define IS_RC_REG(r) ((r) == RC_REGNO)
462 #define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
464 /* Composite register sets */
466 #define IS_ADDR_OR_INDEX_REG(r) (IS_ADDR_REG(r) || IS_INDEX_REG(r))
467 #define IS_EXT_REG(r) (IS_EXT_LOW_REG(r) || IS_EXT_HIGH_REG(r))
468 #define IS_STD_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_REPEAT_REG(r) \
469 || IS_SP_REG(r) || IS_BK_REG(r))
470 #define IS_INT_REG(r) (IS_EXT_REG(r) || IS_STD_REG(r))
471 #define IS_GROUP1_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_BK_REG(r))
474 #define IS_PSEUDO_REG(r) ((r) >= FIRST_PSEUDO_REGISTER)
475 #define IS_R0R1_OR_PSEUDO_REG(r) (IS_R0R1_REG(r) || IS_PSEUDO_REG(r))
476 #define IS_R2R3_OR_PSEUDO_REG(r) (IS_R2R3_REG(r) || IS_PSEUDO_REG(r))
477 #define IS_EXT_OR_PSEUDO_REG(r) (IS_EXT_REG(r) || IS_PSEUDO_REG(r))
478 #define IS_STD_OR_PSEUDO_REG(r) (IS_STD_REG(r) || IS_PSEUDO_REG(r))
479 #define IS_INT_OR_PSEUDO_REG(r) (IS_INT_REG(r) || IS_PSEUDO_REG(r))
480 #define IS_ADDR_OR_PSEUDO_REG(r) (IS_ADDR_REG(r) || IS_PSEUDO_REG(r))
481 #define IS_INDEX_OR_PSEUDO_REG(r) (IS_INDEX_REG(r) || IS_PSEUDO_REG(r))
482 #define IS_EXT_LOW_OR_PSEUDO_REG(r) (IS_EXT_LOW_REG(r) || IS_PSEUDO_REG(r))
483 #define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r))
484 #define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r))
485 #define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r))
486 #define IS_RC_OR_PSEUDO_REG(r) (IS_RC_REG(r) || IS_PSEUDO_REG(r))
488 #define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op)))
489 #define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op)))
490 #define IS_INDEX_REGNO(op) (IS_INDEX_REG(REGNO(op)))
491 #define IS_GROUP1_REGNO(r) (IS_GROUP1_REG(REGNO(op)))
493 #define IS_R0R1_OR_PSEUDO_REGNO(op) (IS_R0R1_OR_PSEUDO_REG(REGNO(op)))
494 #define IS_R2R3_OR_PSEUDO_REGNO(op) (IS_R2R3_OR_PSEUDO_REG(REGNO(op)))
495 #define IS_EXT_OR_PSEUDO_REGNO(op) (IS_EXT_OR_PSEUDO_REG(REGNO(op)))
496 #define IS_STD_OR_PSEUDO_REGNO(op) (IS_STD_OR_PSEUDO_REG(REGNO(op)))
497 #define IS_EXT_LOW_OR_PSEUDO_REGNO(op) (IS_EXT_LOW_OR_PSEUDO_REG(REGNO(op)))
498 #define IS_INT_OR_PSEUDO_REGNO(op) (IS_INT_OR_PSEUDO_REG(REGNO(op)))
500 #define IS_ADDR_OR_PSEUDO_REGNO(op) (IS_ADDR_OR_PSEUDO_REG(REGNO(op)))
501 #define IS_INDEX_OR_PSEUDO_REGNO(op) (IS_INDEX_OR_PSEUDO_REG(REGNO(op)))
502 #define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op)))
503 #define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op)))
504 #define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op)))
505 #define IS_RC_OR_PSEUDO_REGNO(op) (IS_RC_OR_PSEUDO_REG(REGNO(op)))
507 /* 1 for registers that have pervasive standard uses
508 and are not available for the register allocator. */
510 #define FIXED_REGISTERS \
512 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
514 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
515 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
518 /* 1 for registers not available across function calls.
519 These must include the FIXED_REGISTERS and also any
520 registers that can be used without being saved.
521 The latter must include the registers where values are returned
522 and the register where structure-value addresses are passed.
523 Aside from that, you can include as many other registers as you like.
525 Note that the extended precision registers are only saved in some
526 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
527 get clobbered for a given regno. */
529 #define CALL_USED_REGISTERS \
531 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
532 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
533 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
537 /* Macro to conditionally modify fixed_regs/call_used_regs. */
539 #define CONDITIONAL_REGISTER_USAGE \
543 fixed_regs[BK_REGNO] = 1; \
544 call_used_regs[BK_REGNO] = 1; \
545 c4x_regclass_map[BK_REGNO] = NO_REGS; \
551 reg_names[DIE_REGNO] = "ie"; /* clobber die */ \
552 reg_names[IF_REGNO] = "if"; /* clobber iie */ \
553 reg_names[IOF_REGNO] = "iof"; /* clobber iif */ \
555 for (i = R8_REGNO; i <= R11_REGNO; i++) \
557 fixed_regs[i] = call_used_regs[i] = 1; \
558 c4x_regclass_map[i] = NO_REGS; \
561 if (TARGET_PRESERVE_FLOAT) \
563 c4x_caller_save_map[R6_REGNO] = HFmode; \
564 c4x_caller_save_map[R7_REGNO] = HFmode; \
568 /* Order of Allocation of Registers */
570 /* List the order in which to allocate registers. Each register must be
571 listed once, even those in FIXED_REGISTERS.
573 First allocate registers that don't need preservation across calls,
574 except index and address registers. Then allocate data registers
575 that require preservation across calls (even though this invokes an
576 extra overhead of having to save/restore these registers). Next
577 allocate the address and index registers, since using these
578 registers for arithmetic can cause pipeline stalls. Finally
579 allocated the fixed registers which won't be allocated anyhow. */
581 #define REG_ALLOC_ORDER \
582 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
583 R9_REGNO, R10_REGNO, R11_REGNO, \
584 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
585 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
586 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
587 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
588 IR0_REGNO, IR1_REGNO, \
589 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
592 /* Determine which register classes are very likely used by spill registers.
593 local-alloc.c won't allocate pseudos that have these classes as their
594 preferred class unless they are "preferred or nothing". */
596 #define CLASS_LIKELY_SPILLED_P(CLASS) \
597 ((CLASS) == INDEX_REGS)
599 /* CCmode is wrongly defined in machmode.def It should have a size
600 of UNITS_PER_WORD. */
602 #define HARD_REGNO_NREGS(REGNO, MODE) \
603 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
604 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
607 /* A C expression that is nonzero if the hard register REGNO is preserved
608 across a call in mode MODE. This does not have to include the call used
611 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
612 ((((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) && ! ((MODE) == QFmode)) \
613 || (((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO)) \
614 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
616 /* Specify the modes required to caller save a given hard regno. */
618 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) (c4x_caller_save_map[REGNO])
620 int c4x_hard_regno_mode_ok ();
621 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
624 /* A C expression that is nonzero if it is desirable to choose
625 register allocation so as to avoid move instructions between a
626 value of mode MODE1 and a value of mode MODE2.
628 Value is 1 if it is a good idea to tie two pseudo registers
629 when one has mode MODE1 and one has mode MODE2.
630 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
631 for any hard reg, then this must be 0 for correct output. */
633 #define MODES_TIEABLE_P(MODE1, MODE2) 0
636 /* Define the classes of registers for register constraints in the
637 machine description. Also define ranges of constants.
639 One of the classes must always be named ALL_REGS and include all hard regs.
640 If there is more than one class, another class must be named NO_REGS
641 and contain no registers.
643 The name GENERAL_REGS must be the name of a class (or an alias for
644 another name such as ALL_REGS). This is the class of registers
645 that is allowed by "g" or "r" in a register constraint.
646 Also, registers outside this class are allocated only when
647 instructions express preferences for them.
649 The classes must be numbered in nondecreasing order; that is,
650 a larger-numbered class must never be contained completely
651 in a smaller-numbered class.
653 For any two classes, it is very desirable that there be another
654 class that represents their union. */
661 EXT_LOW_REGS, /* 'q' */
664 INDEX_REGS, /* 'x' */
670 GENERAL_REGS, /* 'r' */
677 #define N_REG_CLASSES (int) LIM_REG_CLASSES
679 #define REG_CLASS_NAMES \
699 /* Define which registers fit in which classes.
700 This is an initializer for a vector of HARD_REG_SET
701 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
702 since the register allocator will often choose a general register
703 in preference to RC for the decrement_and_branch_on_count pattern. */
705 #define REG_CLASS_CONTENTS \
707 {0x00000000}, /* No registers */ \
708 {0x00000003}, /* 't' R0-R1 */ \
709 {0x0000000c}, /* 'u' R2-R3 */ \
710 {0x000000ff}, /* 'q' R0-R7 */ \
711 {0xf00000ff}, /* 'f' R0-R11 */ \
712 {0x0000ff00}, /* 'a' AR0-AR7 */ \
713 {0x00060000}, /* 'x' IR0-IR1 */ \
714 {0x00080000}, /* 'k' BK */ \
715 {0x00100000}, /* 'b' SP */ \
716 {0x08000000}, /* 'v' RC */ \
717 {0x0800ff00}, /* RC,AR0-AR7 */ \
718 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */ \
719 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */\
720 {0x00010000}, /* 'z' DP */ \
721 {0x00200000}, /* 'y' ST */ \
722 {0xffffffff}, /* All registers */ \
725 /* The same information, inverted:
726 Return the class number of the smallest class containing
727 reg number REGNO. This could be a conditional expression
728 or could index an array. */
730 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
732 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
733 explicitly used in the rtl is kept as short as possible.
735 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
736 is defined since the MPY|ADD insns require the classes R0R1_REGS and
737 R2R3_REGS which are used by the function return registers (R0,R1) and
738 the register arguments (R2,R3), respectively. I'm reluctant to define
739 this macro since it stomps on many potential optimisations. Ideally
740 it should have a register class argument so that not all the register
741 classes gets penalised for the sake of a naughty few... For long
742 double arithmetic we need two additional registers that we can use as
745 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
747 #define BASE_REG_CLASS ADDR_REGS
748 #define INDEX_REG_CLASS INDEX_REGS
751 Register constraints for the C4x
753 a - address reg (ar0-ar7)
755 c - other gp int-only reg
756 d - data/int reg (equiv. to f)
758 h - data/long double reg (equiv. to f)
763 v - repeat count (rc)
764 x - index register (ir0-ir1)
765 y - status register (st)
768 Memory/constant constraints for the C4x
770 G - short float 16-bit
771 I - signed 16-bit constant (sign extended)
772 J - signed 8-bit constant (sign extended) (C4x only)
773 K - signed 5-bit constant (sign extended) (C4x only for stik)
774 L - unsigned 16-bit constant
775 M - unsigned 8-bit constant (C4x only)
776 N - ones complement of unsigned 16-bit constant
777 Q - indirect arx + 9-bit signed displacement
778 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
779 R - indirect arx + 5-bit unsigned displacement (C4x only)
780 S - indirect arx + 0, 1, or irn displacement
781 T - direct symbol ref
782 > - indirect with autoincrement
783 < - indirect with autodecrement
784 } - indirect with post-modify
785 { - indirect with pre-modify
788 #define REG_CLASS_FROM_LETTER(CC) \
789 ( ((CC) == 'a') ? ADDR_REGS \
790 : ((CC) == 'b') ? SP_REG \
791 : ((CC) == 'c') ? INT_REGS \
792 : ((CC) == 'd') ? EXT_REGS \
793 : ((CC) == 'f') ? EXT_REGS \
794 : ((CC) == 'h') ? EXT_REGS \
795 : ((CC) == 'k') ? BK_REG \
796 : ((CC) == 'q') ? EXT_LOW_REGS \
797 : ((CC) == 't') ? R0R1_REGS \
798 : ((CC) == 'u') ? R2R3_REGS \
799 : ((CC) == 'v') ? RC_REG \
800 : ((CC) == 'x') ? INDEX_REGS \
801 : ((CC) == 'y') ? ST_REG \
802 : ((CC) == 'z') ? DP_REG \
805 /* These assume that REGNO is a hard or pseudo reg number.
806 They give nonzero only if REGNO is a hard reg of the suitable class
807 or a pseudo reg currently allocated to a suitable hard reg.
808 Since they use reg_renumber, they are safe only once reg_renumber
809 has been allocated, which happens in local-alloc.c. */
811 #define REGNO_OK_FOR_BASE_P(REGNO) \
812 (IS_ADDR_REG(REGNO) || IS_ADDR_REG((unsigned)reg_renumber[REGNO]))
814 #define REGNO_OK_FOR_INDEX_P(REGNO) \
815 (IS_INDEX_REG(REGNO) || IS_INDEX_REG((unsigned)reg_renumber[REGNO]))
817 extern enum reg_class c4x_preferred_reload_class ();
818 #define PREFERRED_RELOAD_CLASS(X, CLASS) c4x_preferred_reload_class(X, CLASS)
820 extern enum reg_class c4x_limit_reload_class ();
821 #define LIMIT_RELOAD_CLASS(X, CLASS) c4x_limit_reload_class(X, CLASS)
823 extern enum reg_class c4x_secondary_memory_needed ();
824 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
825 c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
827 #define CLASS_MAX_NREGS(CLASS, MODE) \
828 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
829 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
831 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K' */
833 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R' */
835 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J' */
837 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M' */
839 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I' */
841 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L' */
843 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N' */
845 #define IS_HIGH_CONST(VAL) (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
848 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S' */
850 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q' */
852 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
853 && IS_DISP1_CONST (VAL + 1))
855 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
856 && IS_DISP8_CONST (VAL + 1))
858 #define CONST_OK_FOR_LETTER_P(VAL, C) \
859 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
860 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
861 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
862 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
863 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
864 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
865 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
868 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
869 ( ((C) == 'G') ? (fp_zero_operand (OP)) \
870 : ((C) == 'H') ? (c4x_H_constant (OP)) \
873 #define EXTRA_CONSTRAINT(OP, C) \
874 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
875 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
876 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
877 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
878 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
881 #define SMALL_CONST(VAL, insn) \
882 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
883 ? IS_INT16_CONST (VAL) \
884 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
885 ? IS_NOT_UINT16_CONST (VAL) \
886 : ( (get_attr_data (insn) == DATA_HIGH_16) \
887 ? IS_HIGH_CONST (VAL) \
888 : IS_UINT16_CONST (VAL) \
894 I. Routine calling with arguments in registers
895 ----------------------------------------------
897 The TI C3x compiler has a rather unusual register passing algorithm.
898 Data is passed in the following registers (in order):
900 AR2, R2, R3, RC, RS, RE
902 However, the first and second floating point values are always in R2
903 and R3 (and all other floats are on the stack). Structs are always
904 passed on the stack. If the last argument is an ellipsis, the
905 previous argument is passed on the stack so that its address can be
906 taken for the stdargs macros.
908 Because of this, we have to pre-scan the list of arguments to figure
909 out what goes where in the list.
911 II. Routine calling with arguments on stack
912 -------------------------------------------
914 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
915 variables loc0, loc1, and loc2. After the function prologue has
916 been executed, the stack frame will look like:
918 [stack grows towards increasing addresses]
920 5 I saved reg1 I <= SP points here
930 0 I old FP I <= FP (AR3) points here
941 All local variables (locn) are accessible by means of +FP(n+1)
942 addressing, where n is the local variable number.
944 All stack arguments (argn) are accessible by means of -FP(n-2).
946 The stack pointer (SP) points to the last register saved in the
949 Note that a push instruction performs a preincrement of the stack
950 pointer. (STACK_PUSH_CODE == PRE_INC)
952 III. Registers used in function calling convention
953 --------------------------------------------------
955 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
956 R6...R7 (only by PUSHF, i.e. upper 32 bits)
959 (Because of this model, we only assign FP values in R6, R7 and
960 only assign integer values in R4, R5.)
962 These registers are saved at each function entry and restored at
963 the exit. Also it is expected any of these not affected by any
964 call to user-defined (not service) functions.
966 Not preserved across calls: R0...R3
967 R4...R5 (upper 8 bits)
968 R6...R7 (lower 8 bits)
969 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
971 These registers are used arbitrary in a function without being preserved.
972 It is also expected that any of these can be clobbered by any call.
974 Not used by GCC (except for in user "asm" statements):
975 IE (DIE), IF (IIE), IOF (IIF)
977 These registers are never used by GCC for any data, but can be used
978 with "asm" statements. */
983 /* Basic Stack Layout */
985 /* The stack grows upward, stack frame grows upward, and args grow
988 #define STARTING_FRAME_OFFSET C4X_LOC0
989 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
990 #define ARGS_GROW_DOWNWARD
991 #define STACK_POINTER_OFFSET 1
993 /* Define this if pushing a word on the stack
994 makes the stack pointer a smaller address. */
996 /* #define STACK_GROWS_DOWNWARD */
997 /* Like the dsp16xx, i370, i960, and we32k ports */
999 /* Define this if the nominal address of the stack frame
1000 is at the high-address end of the local variables;
1001 that is, each additional local variable allocated
1002 goes at a more negative offset in the frame. */
1004 /* #define FRAME_GROWS_DOWNWARD */
1007 /* Registers That Address the Stack Frame */
1009 #define STACK_POINTER_REGNUM SP_REGNO /* SP */
1010 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3 */
1011 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3 */
1012 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0 */
1014 /* Eliminating Frame Pointer and Arg Pointer */
1016 #define FRAME_POINTER_REQUIRED 0
1018 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1022 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1023 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1024 offset += TARGET_PRESERVE_FLOAT \
1025 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1027 (DEPTH) = -(offset + get_frame_size ()); \
1030 /* This is a hack... We need to specify a register. */
1031 #define ELIMINABLE_REGS \
1032 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1034 #define CAN_ELIMINATE(FROM, TO) \
1035 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1036 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1038 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1042 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1043 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1044 offset += TARGET_PRESERVE_FLOAT \
1045 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1047 (OFFSET) = -(offset + get_frame_size ()); \
1051 /* Passing Function Arguments on the Stack */
1054 #define PUSH_ROUNDING(BYTES) (BYTES)
1056 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1058 /* The following structure is used by calls.c, function.c, c4x.c */
1060 typedef struct c4x_args
1073 extern void c4x_init_cumulative_args();
1075 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1076 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1078 extern void c4x_function_arg_advance();
1080 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1081 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1083 extern struct rtx_def *c4x_function_arg();
1085 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1086 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1088 /* Define the profitability of saving registers around calls.
1089 We disable caller save to avoid a bug in flow.c (this also affects
1090 other targets such as m68k). Since we must use stf/sti,
1091 the profitability is marginal anyway. */
1093 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1095 /* Never pass data by reference. */
1097 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1099 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1101 /* 1 if N is a possible register number for function argument passing. */
1103 #define FUNCTION_ARG_REGNO_P(REGNO) \
1104 ( ( ((REGNO) == AR2_REGNO) /* AR2 */ \
1105 || ((REGNO) == R2_REGNO) /* R2 */ \
1106 || ((REGNO) == R3_REGNO) /* R3 */ \
1107 || ((REGNO) == RC_REGNO) /* RC */ \
1108 || ((REGNO) == RS_REGNO) /* RS */ \
1109 || ((REGNO) == RE_REGNO)) /* RE */ \
1113 /* How Scalar Function Values Are Returned */
1115 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1116 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0 */
1118 #define LIBCALL_VALUE(MODE) \
1119 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0 */
1121 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1123 /* How Large Values Are Returned */
1125 #define DEFAULT_PCC_STRUCT_RETURN 0
1126 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0 */
1128 /* Varargs handling. */
1130 extern void c4x_va_start ();
1131 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1132 c4x_va_start (stdarg, valist, nextarg)
1134 extern struct rtx_def *c4x_va_arg ();
1135 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1136 c4x_va_arg (valist, type)
1138 /* Function Entry and Exit */
1140 #define FUNCTION_PROLOGUE(FILE, SIZE) c4x_function_prologue(FILE, SIZE)
1141 #define FUNCTION_EPILOGUE(FILE, SIZE) c4x_function_epilogue(FILE, SIZE)
1144 /* Generating Code for Profiling */
1146 /* Note that the generated assembly uses the ^ operator to load the 16
1147 MSBs of the address. This is not supported by the TI assembler.
1148 The FUNCTION profiler needs a function mcount which gets passed
1149 a pointer to the LABELNO. */
1151 #define FUNCTION_PROFILER(FILE, LABELNO) \
1154 fprintf (FILE, "\tpush\tar2\n"); \
1155 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1156 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1157 fprintf (FILE, "\tcall\tmcount\n"); \
1158 fprintf (FILE, "\tpop\tar2\n"); \
1162 fprintf (FILE, "\tpush\tar2\n"); \
1163 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1164 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1165 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1166 fprintf (FILE, "\tcall\tmcount\n"); \
1167 fprintf (FILE, "\tpop\tar2\n"); \
1170 /* There are three profiling modes for basic blocks available.
1171 The modes are selected at compile time by using the options
1172 -a or -ax of the gnu compiler.
1173 The variable `profile_block_flag' will be set according to the
1176 profile_block_flag == 0, no option used:
1180 profile_block_flag == 1, -a option used.
1182 Count frequency of execution of every basic block.
1184 profile_block_flag == 2, -ax option used.
1186 Generate code to allow several different profiling modes at run time.
1187 Available modes are:
1188 Produce a trace of all basic blocks.
1189 Count frequency of jump instructions executed.
1190 In every mode it is possible to start profiling upon entering
1191 certain functions and to disable profiling of some other functions.
1193 The result of basic-block profiling will be written to a file `bb.out'.
1194 If the -ax option is used parameters for the profiling will be read
1199 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) \
1200 if (profile_block_flag == 2) \
1204 fprintf (FILE, "\tpush\tst\n"); \
1205 fprintf (FILE, "\tpush\tar2\n"); \
1206 fprintf (FILE, "\tpush\tr2\n"); \
1207 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1208 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1209 if (BLOCKNO > 32767) \
1211 fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16); \
1212 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1216 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1218 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1219 fprintf (FILE, "\tpop\tr2\n"); \
1220 fprintf (FILE, "\tpop\tar2\n"); \
1221 fprintf (FILE, "\tpop\tst\n"); \
1225 fprintf (FILE, "\tpush\tst\n"); \
1226 fprintf (FILE, "\tpush\tar2\n"); \
1227 fprintf (FILE, "\tpush\tr2\n"); \
1228 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1229 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1230 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1231 if (BLOCKNO > 32767) \
1233 fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16); \
1234 fprintf (FILE, "\tlsh\t16,r2\n"); \
1235 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1239 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1241 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1242 fprintf (FILE, "\tpop\tr2\n"); \
1243 fprintf (FILE, "\tpop\tar2\n"); \
1244 fprintf (FILE, "\tpop\tst\n"); \
1251 fprintf (FILE, "\tpush\tst\n"); \
1252 fprintf (FILE, "\tpush\tar2\n"); \
1253 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1254 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1255 fprintf (FILE, "\tcmpi\t0,*ar2\n"); \
1256 fprintf (FILE, "\tbne\t$+2\n"); \
1257 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1258 fprintf (FILE, "\tpop\tar2\n"); \
1259 fprintf (FILE, "\tpop\tst\n"); \
1263 fprintf (FILE, "\tpush\tst\n"); \
1264 fprintf (FILE, "\tpush\tar2\n"); \
1265 fprintf (FILE, "\tpush\tr2\n"); \
1266 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1267 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1268 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1269 fprintf (FILE, "\tldi\t*ar2,r2\n"); \
1270 fprintf (FILE, "\tbne\t$+2\n"); \
1271 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1272 fprintf (FILE, "\tpop\tr2\n"); \
1273 fprintf (FILE, "\tpop\tar2\n"); \
1274 fprintf (FILE, "\tpop\tst\n"); \
1278 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1279 if (profile_block_flag == 2) \
1283 fprintf (FILE, "\tpush\tst\n"); \
1284 fprintf (FILE, "\tpush\tar2\n"); \
1285 fprintf (FILE, "\tpush\tar0\n"); \
1286 fprintf (FILE, "\tldhi\t^___bb,ar2\n"); \
1287 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1288 if (BLOCKNO > 32767) \
1290 fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
1291 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1295 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1297 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1298 fprintf (FILE, "\tldhi\t^LPBX0,ar0\n"); \
1299 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1300 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1301 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1302 fprintf (FILE, "\tpop\tar0\n"); \
1303 fprintf (FILE, "\tpop\tar2\n"); \
1304 fprintf (FILE, "\tpop\tst\n"); \
1308 fprintf (FILE, "\tpush\tst\n"); \
1309 fprintf (FILE, "\tpush\tar2\n"); \
1310 fprintf (FILE, "\tpush\tar0\n"); \
1311 fprintf (FILE, "\tldiu\t^___bb,ar2\n"); \
1312 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1313 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1314 if (BLOCKNO > 32767) \
1316 fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16); \
1317 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1318 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1322 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1324 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1325 fprintf (FILE, "\tldiu\t^LPBX0,ar0\n"); \
1326 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1327 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1328 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1329 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1330 fprintf (FILE, "\tpop\tar0\n"); \
1331 fprintf (FILE, "\tpop\tar2\n"); \
1332 fprintf (FILE, "\tpop\tst\n"); \
1339 fprintf (FILE, "\tpush\tar2\n"); \
1340 fprintf (FILE, "\tpush\tar0\n"); \
1341 fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1342 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1343 fprintf (FILE, "\taddi3\t1,*ar2,ar0\n"); \
1344 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1345 fprintf (FILE, "\tpop\tar0\n"); \
1346 fprintf (FILE, "\tpop\tar2\n"); \
1350 fprintf (FILE, "\tpush\tar2\n"); \
1351 fprintf (FILE, "\tpush\tar0\n"); \
1352 fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1353 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1354 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1355 fprintf (FILE, "\tldiu\t*ar2,ar0\n"); \
1356 fprintf (FILE, "\taddi\t1,ar0\n"); \
1357 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1358 fprintf (FILE, "\tpop\tar0\n"); \
1359 fprintf (FILE, "\tpop\tar2\n"); \
1363 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1365 fprintf (FILE, "\tpush\tst\n"); \
1366 fprintf (FILE, "\tpush\tar2\n"); \
1367 fprintf (FILE, "\tcall\t___bb_trace_ret\n"); \
1368 fprintf (FILE, "\tpop\tar2\n"); \
1369 fprintf (FILE, "\tpop\tst\n"); \
1372 #define MACHINE_STATE_SAVE(ID) \
1383 asm(" .if .BIGMODEL"); \
1392 asm(" .if .tms320C40"); \
1396 asm(" pushf r10"); \
1398 asm(" pushf r11"); \
1401 #define MACHINE_STATE_RESTORE(ID) \
1402 asm(" .if .tms320C40"); \
1416 asm(" .if .BIGMODEL"); \
1430 /* Implicit Calls to Library Routines */
1432 #define MULQI3_LIBCALL "__mulqi3"
1433 #define DIVQI3_LIBCALL "__divqi3"
1434 #define UDIVQI3_LIBCALL "__udivqi3"
1435 #define MODQI3_LIBCALL "__modqi3"
1436 #define UMODQI3_LIBCALL "__umodqi3"
1438 #define DIVQF3_LIBCALL "__divqf3"
1440 #define MULHF3_LIBCALL "__mulhf3"
1441 #define DIVHF3_LIBCALL "__divhf3"
1443 #define MULHI3_LIBCALL "__mulhi3"
1444 #define SMULHI3_LIBCALL "__smulhi3_high"
1445 #define UMULHI3_LIBCALL "__umulhi3_high"
1446 #define DIVHI3_LIBCALL "__divhi3"
1447 #define UDIVHI3_LIBCALL "__udivhi3"
1448 #define MODHI3_LIBCALL "__modhi3"
1449 #define UMODHI3_LIBCALL "__umodhi3"
1451 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1452 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1453 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1454 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1456 #define FLOATHIHF2_LIBCALL "__floathihf2"
1457 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1458 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1459 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1461 #define FFS_LIBCALL "__ffs"
1463 #define TARGET_MEM_FUNCTIONS
1465 /* Add any extra modes needed to represent the condition code.
1467 On the C4x, we have a "no-overflow" mode which is used when an ADD,
1468 SUB, NEG, or MPY insn is used to set the condition code. This is
1469 to prevent the combiner from optimising away a following CMP of the
1470 result with zero when a signed conditional branch or load insn
1473 The problem is a subtle one and deals with the manner in which the
1474 negative condition (N) flag is used on the C4x. This flag does not
1475 reflect the status of the actual result but of the ideal result had
1476 no overflow occured (when considering signed operands).
1478 For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
1479 the flags reflect the untruncated result, not the actual result.
1480 While the actual result is less than zero, the N flag is not set
1481 since the ideal result of the addition without truncation would
1484 Note that the while the N flag is handled differently to most other
1485 architectures, the use of it is self consistent and is not the
1486 cause of the problem.
1488 Logical operations set the N flag to the MSB of the result so if
1489 the result is negative, N is 1. However, integer and floating
1490 point operations set the N flag to be the MSB of the result
1491 exclusive ored with the overflow (V) flag. Thus if an overflow
1492 occurs and the result does not have the MSB set (i.e., the result
1493 looks like a positive number), the N flag is set. Conversely, if
1494 an overflow occurs and the MSB of the result is set, N is set to 0.
1495 Thus the N flag represents the sign of the result if it could have
1496 been stored without overflow but does not represent the apparent
1497 sign of the result. Note that most architectures set the N flag to
1498 be the MSB of the result.
1500 The C4x approach to setting the N flag simplifies signed
1501 conditional branches and loads which only have to test the state of
1502 the N flag, whereas most architectures have to look at both the N
1503 and V flags. The disadvantage is that there is no flag giving the
1504 status of the sign bit of the operation. However, there are no
1505 conditional load or branch instructions that make use of this
1506 feature (e.g., BMI---branch minus) instruction. Note that BN and
1507 BLT are identical in the C4x.
1509 To handle the problem where the N flag is set differently whenever
1510 there is an overflow we use a different CC mode, CC_NOOVmode which
1511 says that the CC reflects the comparison of the result against zero
1512 if no overflow occured.
1516 [(set (reg:CC_NOOV 21)
1517 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
1518 (match_operand:QI 2 "src_operand" ""))
1520 (set (match_operand:QI 0 "ext_reg_operand" "")
1521 (minus:QI (match_dup 1)
1524 Note that there is no problem for insns that don't return a result
1525 like CMP, since the CC reflects the effect of operation.
1527 An example of a potential problem is when GCC
1528 converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
1529 to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
1530 to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
1532 Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
1533 C4x sets the N flag since the result without overflow would have
1534 been 0xffffffff when treating the operands as signed integers.
1535 Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
1536 flag but (GE (0x00000001)) does not set the N flag.
1538 The upshot is that we can not use signed branch and conditional
1539 load instructions after an add, subtract, neg, abs or multiply.
1540 We must emit a compare insn to check the result against 0. */
1542 #define EXTRA_CC_MODES CC(CC_NOOVmode, "CC_NOOV")
1544 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1546 CCmode should be used when no special processing is needed. */
1547 #define SELECT_CC_MODE(OP,X,Y) \
1548 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1549 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1550 || GET_MODE (X) == ABS \
1551 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1552 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1553 || GET_MODE (Y) == ABS) \
1554 ? CC_NOOVmode : CCmode)
1556 extern struct rtx_def *c4x_gen_compare_reg ();
1558 /* Addressing Modes */
1560 #define HAVE_POST_INCREMENT 1
1561 #define HAVE_PRE_INCREMENT 1
1562 #define HAVE_POST_DECREMENT 1
1563 #define HAVE_PRE_DECREMENT 1
1564 #define HAVE_PRE_MODIFY_REG 1
1565 #define HAVE_POST_MODIFY_REG 1
1566 #define HAVE_PRE_MODIFY_DISP 1
1567 #define HAVE_POST_MODIFY_DISP 1
1569 /* The number of insns that can be packed into a single opcode. */
1570 #define PACK_INSNS 2
1572 /* Recognize any constant value that is a valid address.
1573 We could allow arbitrary constant addresses in the large memory
1574 model but for the small memory model we can only accept addresses
1575 within the data page. I suppose we could also allow
1576 CONST PLUS SYMBOL_REF. */
1577 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1579 /* Maximum number of registers that can appear in a valid memory
1581 #define MAX_REGS_PER_ADDRESS 2
1583 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1584 and check its validity for a certain class.
1585 We have two alternate definitions for each of them.
1586 The usual definition accepts all pseudo regs; the other rejects
1587 them unless they have been allocated suitable hard regs.
1588 The symbol REG_OK_STRICT causes the latter definition to be used.
1590 Most source files want to accept pseudo regs in the hope that
1591 they will get allocated to the class that the insn wants them to be in.
1592 Source files for reload pass need to be strict.
1593 After reload, it makes no difference, since pseudo regs have
1594 been eliminated by then. */
1596 extern int c4x_check_legit_addr ();
1598 #ifndef REG_OK_STRICT
1600 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1602 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(REGNO(X))
1604 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1606 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(REGNO(X))
1608 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1610 if (c4x_check_legit_addr (MODE, X, 0)) \
1616 /* Nonzero if X is a hard reg that can be used as an index. */
1618 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1620 /* Nonzero if X is a hard reg that can be used as a base reg. */
1622 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1624 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1626 if (c4x_check_legit_addr (MODE, X, 1)) \
1632 extern struct rtx_def *c4x_legitimize_address ();
1633 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1636 new = c4x_legitimize_address (X, MODE); \
1637 if (new != NULL_RTX) \
1644 extern struct rtx_def *c4x_legitimize_reload_address ();
1645 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1648 new = c4x_legitimize_reload_address (X, MODE, insn); \
1649 if (new != NULL_RTX) \
1652 /* We do not have to call push_reload because we do not require \
1653 any more reloads. */ \
1659 /* No mode-dependent addresses on the C4x are autoincrements. */
1661 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1662 if (GET_CODE (ADDR) == PRE_DEC \
1663 || GET_CODE (ADDR) == POST_DEC \
1664 || GET_CODE (ADDR) == PRE_INC \
1665 || GET_CODE (ADDR) == POST_INC \
1666 || GET_CODE (ADDR) == POST_MODIFY \
1667 || GET_CODE (ADDR) == PRE_MODIFY) \
1671 /* Nonzero if the constant value X is a legitimate general operand.
1672 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1674 The C4x can only load 16-bit immediate values, so we only allow a
1675 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1676 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1677 model) so that the symbols will be forced into the constant pool.
1678 On second thoughts, let's do this with the move expanders since
1679 the alias analysis has trouble if we force constant addresses
1683 #define LEGITIMATE_CONSTANT_P(X) \
1684 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1685 || (GET_CODE (X) == CONST_INT) \
1686 || (GET_CODE (X) == SYMBOL_REF) \
1687 || (GET_CODE (X) == LABEL_REF) \
1688 || (GET_CODE (X) == CONST) \
1689 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1690 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1692 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1694 /* Define this macro if references to a symbol must be treated
1695 differently depending on something about the variable or
1696 function named by the symbol (such as what section it is in).
1698 The macro definition, if any, is executed immediately after the
1699 rtl for DECL or other node is created.
1700 The value of the rtl will be a `mem' whose address is a
1703 The usual thing for this macro to do is to a flag in the
1704 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1705 name string in the `symbol_ref' (if one bit is not enough
1708 On the C4x we use this to indicate if a symbol is in text or
1711 extern void c4x_encode_section_info ();
1712 #define ENCODE_SECTION_INFO(DECL) c4x_encode_section_info (DECL);
1714 /* Descripting Relative Cost of Operations */
1716 /* Provide the costs of a rtl expression. This is in the body of a
1719 Note that we return, rather than break so that rtx_cost doesn't
1720 include CONST_COSTS otherwise expand_mult will think that it is
1721 cheaper to synthesise a multiply rather than to use a multiply
1722 instruction. I think this is because the algorithm synth_mult
1723 doesn't take into account the loading of the operands, whereas the
1724 calculation of mult_cost does.
1728 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1737 return COSTS_N_INSNS (1); \
1739 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1740 || TARGET_MPYI ? 1 : 14); \
1745 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1748 /* Compute the cost of computing a constant rtl expression RTX
1749 whose rtx-code is CODE. The body of this macro is a portion
1750 of a switch statement. If the code is computed here,
1751 return it with a return statement. Otherwise, break from the switch.
1753 An insn is assumed to cost 4 units.
1754 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1756 Some small integers are effectively free for the C40. We should
1757 also consider if we are using the small memory model. With
1758 the big memory model we require an extra insn for a constant
1761 This is used by expand_binop to decide whether to force a constant
1762 into a register. If the cost is greater than 2 and the constant
1763 is used within a short loop, it gets forced into a register.
1764 Ideally, there should be some weighting as to how mnay times it is used
1767 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1769 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1770 || (C) == IOR || (C) == XOR)
1772 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1774 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1776 if (c4x_J_constant (RTX)) \
1779 && OUTER_CODE == AND \
1780 && GET_CODE (RTX) == CONST_INT \
1781 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1784 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1785 && GET_CODE (RTX) == CONST_INT \
1786 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1788 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1790 if (LOGICAL_CODE_P (OUTER_CODE) \
1791 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1797 case CONST_DOUBLE: \
1798 if (c4x_H_constant (RTX)) \
1800 if (GET_MODE (RTX) == QFmode) \
1805 /* Compute the cost of an address. This is meant to approximate the size
1806 and/or execution delay of an insn using that address. If the cost is
1807 approximated by the RTL complexity, including CONST_COSTS above, as
1808 is usually the case for CISC machines, this macro should not be defined.
1809 For aggressively RISCy machines, only one insn format is allowed, so
1810 this macro should be a constant. The value of this macro only matters
1811 for valid addresses. We handle the most common address without
1812 a call to c4x_address_cost. */
1814 extern int c4x_address_cost ();
1816 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1818 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1819 if (REG_P (OP1) && ! REG_P (OP0)) \
1821 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1822 CODE = swap_condition (CODE); \
1825 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1826 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1827 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1828 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1829 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1831 /* Compute extra cost of moving data between one register class
1834 #define REGISTER_MOVE_COST(FROM, TO) 2
1836 /* Memory move cost is same as fast register move. Maybe this should
1839 #define MEMORY_MOVE_COST(M,C,I) 4
1841 /* Branches are kind of expensive (even with delayed branching) so
1842 make their cost higher. */
1844 #define BRANCH_COST 8
1846 /* Adjust the cost of dependencies. */
1848 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1849 (COST) = c4x_adjust_cost (INSN, LINK, DEP, COST)
1851 #define WORD_REGISTER_OPERATIONS
1853 /* Dividing the Output into Sections. */
1855 #define TEXT_SECTION_ASM_OP "\t.text"
1857 #define DATA_SECTION_ASM_OP "\t.data"
1859 #define USE_CONST_SECTION 1
1861 #define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
1863 /* Do not use .init section so __main will be called on startup. This will
1864 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1867 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1870 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1872 /* Support const sections and the ctors and dtors sections for g++.
1873 Note that there appears to be two different ways to support const
1874 sections at the moment. You can either #define the symbol
1875 READONLY_DATA_SECTION (giving it some code which switches to the
1876 readonly data section) or else you can #define the symbols
1877 EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
1878 SELECT_RTX_SECTION. We do both here just to be on the safe side. */
1880 /* Define a few machine-specific details of the implementation of
1883 The __CTORS_LIST__ goes in the .ctors section. Define CTOR_LIST_BEGIN
1884 and CTOR_LIST_END to contribute to the .ctors section an instruction to
1885 push a word containing 0 (or some equivalent of that).
1887 Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */
1889 #define CTORS_SECTION_ASM_OP "\t.sect\t\".ctors\""
1890 #define DTORS_SECTION_ASM_OP "\t.sect\t\".dtors\""
1892 /* Constructor list on stack is in reverse order. Go to the end of the
1893 list and go backwards to call constructors in the right order. */
1895 #define DO_GLOBAL_CTORS_BODY \
1897 extern func_ptr __CTOR_LIST__[]; \
1898 func_ptr *p, *beg = __CTOR_LIST__ + 1; \
1899 for (p = beg; *p ; p++) ; \
1904 #undef EXTRA_SECTIONS
1905 #define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
1907 #undef EXTRA_SECTION_FUNCTIONS
1908 #define EXTRA_SECTION_FUNCTIONS \
1909 CONST_SECTION_FUNCTION \
1910 INIT_SECTION_FUNCTION \
1911 FINI_SECTION_FUNCTION \
1912 CTORS_SECTION_FUNCTION \
1913 DTORS_SECTION_FUNCTION
1915 #define INIT_SECTION_FUNCTION \
1919 if (in_section != in_init) \
1921 fprintf (asm_out_file, ";\t.init\n"); \
1922 in_section = in_init; \
1926 #define FINI_SECTION_FUNCTION \
1930 if (in_section != in_fini) \
1932 fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \
1933 in_section = in_fini; \
1937 #define READONLY_DATA_SECTION() const_section ()
1939 #define CONST_SECTION_FUNCTION \
1943 extern void text_section(); \
1944 if (! USE_CONST_SECTION) \
1946 else if (in_section != in_const) \
1948 fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
1949 in_section = in_const; \
1953 #define ASM_STABS_OP "\t.stabs"
1955 /* The ctors and dtors sections are not normally put into use
1956 by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
1957 but it can't hurt to define these macros for whatever systems use them. */
1959 #define CTORS_SECTION_FUNCTION \
1963 if (in_section != in_ctors) \
1965 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1966 in_section = in_ctors; \
1970 #define DTORS_SECTION_FUNCTION \
1974 if (in_section != in_dtors) \
1976 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1977 in_section = in_dtors; \
1981 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1982 fprintf (FILE, "\t.sect\t\"%s\"\n", NAME);
1984 /* This is machine-dependent because it needs to push something
1987 /* A C statement (sans semicolon) to output an element in the table of
1988 global constructors. */
1989 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1992 fprintf (FILE, "\t.word\t "); \
1993 assemble_name (FILE, NAME); \
1994 fprintf (FILE, "\n"); \
1997 /* A C statement (sans semicolon) to output an element in the table of
1998 global destructors. */
1999 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
2002 fprintf (FILE, "\t.word\t "); \
2003 assemble_name (FILE, NAME); \
2004 fprintf (FILE, "\n"); \
2007 /* A C statement or statements to switch to the appropriate
2008 section for output of DECL. DECL is either a `VAR_DECL' node
2009 or a constant of some sort. RELOC indicates whether forming
2010 the initial value of DECL requires link-time relocations. */
2012 #define SELECT_SECTION(DECL, RELOC) \
2014 if (TREE_CODE (DECL) == STRING_CST) \
2016 if (! flag_writable_strings) \
2021 else if (TREE_CODE (DECL) == VAR_DECL) \
2023 if ((0 && RELOC) /* should be (flag_pic && RELOC) */ \
2024 || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
2025 || ! DECL_INITIAL (DECL) \
2026 || (DECL_INITIAL (DECL) != error_mark_node \
2027 && ! TREE_CONSTANT (DECL_INITIAL (DECL)))) \
2036 /* A C statement or statements to switch to the appropriate
2037 section for output of RTX in mode MODE. RTX is some kind
2038 of constant in RTL. The argument MODE is redundant except
2039 in the case of a `const_int' rtx. Currently, these always
2040 go into the const section. */
2042 #define SELECT_RTX_SECTION(MODE, RTX) const_section()
2045 /* Overall Framework of an Assembler File */
2047 #define ASM_FILE_START(FILE) \
2049 int dspversion = 0; \
2050 if (TARGET_C30) dspversion = 30; \
2051 if (TARGET_C31) dspversion = 31; \
2052 if (TARGET_C32) dspversion = 32; \
2053 if (TARGET_C40) dspversion = 40; \
2054 if (TARGET_C44) dspversion = 44; \
2055 fprintf (FILE, "\t.version\t%d\n", dspversion); \
2056 fprintf (FILE, "\t.file\t"); \
2060 char *after_dir = main_input_filename; \
2061 for (p = main_input_filename; *p; p++) \
2063 after_dir = p + 1; \
2064 output_quoted_string (FILE, after_dir); \
2067 output_quoted_string (FILE, main_input_filename); \
2068 fprintf (FILE, "\n"); \
2071 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n")
2073 /* We need to have a data section we can identify so that we can set
2074 the DP register back to a data pointer in the small memory model.
2075 This is only required for ISRs if we are paranoid that someone
2076 may have quietly changed this register on the sly. */
2078 #define ASM_IDENTIFY_GCC(FILE) \
2079 if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE); \
2080 fputs ("\t.data\ndata_sec:\n", FILE);
2082 #define ASM_COMMENT_START ";"
2084 #define ASM_APP_ON ""
2085 #define ASM_APP_OFF ""
2087 /* Output float/double constants QFmode. */
2089 #define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE) \
2092 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2093 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2094 if (sizeof (int) == sizeof (long)) \
2095 fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
2097 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
2100 /* Output long double constants HFmode.
2101 The first word contains the exponent and first part of the mantissa
2102 in the same manner as QFmode. The second word contains the full
2103 mantissa. We should ensure that the two words are allocated within
2104 the same page for the large memory model since we only output a single
2105 LDP instruction. FIXME. The simplest solution probably is to output
2106 a LDP for each load. */
2108 #define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE) \
2111 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2112 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2113 l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
2114 if (sizeof (int) == sizeof (long)) \
2115 fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
2118 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
2122 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
2123 { fprintf (FILE, "\t.word\t"); \
2124 output_addr_const (FILE, VALUE); \
2125 if (GET_CODE (VALUE) != SYMBOL_REF) \
2126 fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE)); \
2128 fputc ('\n', FILE); \
2131 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
2132 fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
2134 extern void c4x_output_ascii ();
2135 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
2137 #define ASM_OPEN_PAREN "("
2138 #define ASM_CLOSE_PAREN ")"
2141 /* Output and Generation of Labels */
2143 #define NO_DOT_IN_LABEL /* Only required for TI format */
2145 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2146 { assemble_name (FILE, NAME); fputs (":\n", FILE); }
2148 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
2150 fprintf (FILE, "\t.global\t"); \
2151 assemble_name (FILE, NAME); \
2152 fputs ("\n", FILE); \
2155 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2157 fprintf (FILE, "\t.ref\t"); \
2158 assemble_name (FILE, NAME); \
2159 fputc ('\n', FILE); \
2162 /* A C statement to output on FILE an assembler pseudo-op to
2163 declare a library function named external.
2164 (Only needed to keep asm30 happy for ___divqf3 etc.) */
2166 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
2168 fprintf (FILE, "\t.ref\t"); \
2169 assemble_name (FILE, XSTR (FUN, 0)); \
2170 fprintf (FILE, "\n"); \
2173 /* The prefix to add to user-visible assembler symbols. */
2175 #define USER_LABEL_PREFIX "_"
2177 /* This is how to output an internal numbered label where
2178 PREFIX is the class of label and NUM is the number within the class. */
2180 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
2181 asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2183 /* This is how to store into the string LABEL
2184 the symbol_ref name of an internal numbered label where
2185 PREFIX is the class of label and NUM is the number within the class.
2186 This is suitable for output with `assemble_name'. */
2188 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
2189 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
2191 /* Store in OUTPUT a string (made with alloca) containing
2192 an assembler-name for a local static variable named NAME.
2193 LABELNO is an integer which is different for each call. */
2195 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2196 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2197 sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO)))
2200 /* Output of Dispatch Tables */
2202 /* This is how to output an element of a case-vector that is absolute. */
2204 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2205 fprintf (FILE, "\t.long\tL%d\n", VALUE);
2207 /* This is how to output an element of a case-vector that is relative. */
2209 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2210 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
2213 #define SIZE_TYPE "unsigned int"
2216 #define PTRDIFF_TYPE "int"
2219 #define WCHAR_TYPE "long int"
2221 #undef WCHAR_TYPE_SIZE
2222 #define WCHAR_TYPE_SIZE 32
2224 #define INT_TYPE_SIZE 32
2225 #define LONG_LONG_TYPE_SIZE 64
2226 #define FLOAT_TYPE_SIZE 32
2227 #define DOUBLE_TYPE_SIZE 32
2228 #define LONG_DOUBLE_TYPE_SIZE 64 /* actually only 40 */
2230 /* Allow #sccs in preprocessor. */
2232 #define SCCS_DIRECTIVE
2234 /* Output #ident as a .ident. */
2236 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2237 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
2239 #define CPP_PREDEFINES ""
2241 /* Output of Uninitialized Variables */
2243 /* This says how to output an assembler line to define a local
2244 uninitialized variable. */
2246 #undef ASM_OUTPUT_LOCAL
2247 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2248 ( fputs ("\t.bss\t", FILE), \
2249 assemble_name (FILE, (NAME)), \
2250 fprintf (FILE, ",%u\n", (ROUNDED)))
2252 /* This says how to output an assembler line to define a global
2253 uninitialized variable. */
2255 #undef ASM_OUTPUT_COMMON
2256 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2257 ( fputs ("\t.globl\t", FILE), \
2258 assemble_name (FILE, (NAME)), \
2259 fputs ("\n\t.bss\t", FILE), \
2260 assemble_name (FILE, (NAME)), \
2261 fprintf (FILE, ",%u\n", (ROUNDED)))
2263 /* Macros Controlling Initialization Routines */
2265 #define OBJECT_FORMAT_COFF
2266 #define REAL_NM_FILE_NAME "c4x-nm"
2268 /* Output of Assembler Instructions */
2270 /* Register names when used for integer modes. */
2272 #define REGISTER_NAMES \
2274 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2275 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2276 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2277 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
2280 /* Alternate register names when used for floating point modes. */
2282 #define FLOAT_REGISTER_NAMES \
2284 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2285 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2286 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2287 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
2291 extern void c4x_print_operand ();
2292 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
2294 /* Determine which codes are valid without a following integer. These must
2295 not be alphabetic. */
2297 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
2299 extern void c4x_print_operand_address ();
2300 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
2302 /* Define this macro if you want to implement any pragmas. If defined, it
2303 should be a C expression to be executed when #pragma is seen. The
2304 argument STREAM is the stdio input stream from which the source
2305 text can be read. CH is the first character after the #pragma. The
2306 result of the expression is the terminating character found
2307 (newline or EOF). */
2308 extern int c4x_handle_pragma ();
2309 #define HANDLE_PRAGMA(GETC, UNGETC, NAME) \
2310 c4x_handle_pragma (GETC, UNGETC, NAME)
2312 extern void c4x_set_default_attributes ();
2313 #define SET_DEFAULT_DECL_ATTRIBUTES(DECL, ATTRIBUTES) \
2314 c4x_set_default_attributes (DECL, &ATTRIBUTES)
2316 extern int c4x_valid_type_attribute_p ();
2317 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2318 (c4x_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2320 /* Assembler Commands for Alignment */
2322 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
2324 for (; c > 0; --c) \
2325 fprintf (FILE,"\t.word\t0\n"); \
2328 #define ASM_NO_SKIP_IN_TEXT 1
2330 /* I'm not sure about this one. FIXME. */
2332 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
2334 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
2337 /* Macros for SDB and DWARF Output (use .sdef instead of .def
2338 to avoid conflict with TI's use of .def) */
2340 #define SDB_DELIM "\n"
2341 #define SDB_DEBUGGING_INFO
2343 #define PUT_SDB_DEF(A) \
2344 do { fprintf (asm_out_file, "\t.sdef\t"); \
2345 ASM_OUTPUT_LABELREF (asm_out_file, A); \
2346 fprintf (asm_out_file, SDB_DELIM); } while (0)
2348 #define PUT_SDB_PLAIN_DEF(A) \
2349 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
2351 #define PUT_SDB_BLOCK_START(LINE) \
2352 fprintf (asm_out_file, \
2353 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2354 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2356 #define PUT_SDB_BLOCK_END(LINE) \
2357 fprintf (asm_out_file, \
2358 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2359 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2361 #define PUT_SDB_FUNCTION_START(LINE) \
2362 fprintf (asm_out_file, \
2363 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2364 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2366 #define PUT_SDB_FUNCTION_END(LINE) \
2367 fprintf (asm_out_file, \
2368 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2369 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2371 #define PUT_SDB_EPILOGUE_END(NAME) \
2372 do { fprintf (asm_out_file, "\t.sdef\t"); \
2373 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
2374 fprintf (asm_out_file, \
2375 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
2376 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
2379 /* Define results of standard character escape sequences. */
2381 #define TARGET_BELL 007
2382 #define TARGET_BS 010
2383 #define TARGET_TAB 011
2384 #define TARGET_NEWLINE 012
2385 #define TARGET_VT 013
2386 #define TARGET_FF 014
2387 #define TARGET_CR 015
2389 /* This is the kind of divide that is easiest to do in the general case. */
2391 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2393 /* Define this as 1 if `char' should by default be signed; else as 0. */
2395 #define DEFAULT_SIGNED_CHAR 1
2397 /* A function address in a call instruction is a byte address (for
2398 indexing purposes) so give the MEM rtx a byte's mode. */
2400 #define FUNCTION_MODE QImode
2402 #define SLOW_BYTE_ACCESS 0
2404 /* Specify the machine mode that pointers have. After generation of
2405 RTL, the compiler makes no further distinction between pointers and
2406 any other objects of this machine mode. */
2408 #define Pmode QImode
2410 /* On the C4x we can write the following code. We have to clear the cache
2411 every time we execute it because the data in the stack could change.
2424 On the c3x this is a bit more difficult. We have to write self
2425 modifying code here. So we have to clear the cache every time
2426 we execute it because the data in the stack could change.
2428 ldiu TOP_OF_FUNCTION,ar1
2430 or BOTTOM_OF_FUNCTION,ar1
2431 ldiu TOP_OF_STATIC,ar0
2434 or BOTTOM_OF_STATIC,ar0
2439 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
2441 #define TRAMPOLINE_TEMPLATE(FILE) \
2445 asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
2446 asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
2447 asm_fprintf (FILE, "\tor\t0,ar1\n"); \
2448 asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
2449 asm_fprintf (FILE, "\tbud\tar1\n"); \
2450 asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
2451 asm_fprintf (FILE, "\tor\t0,ar0\n"); \
2452 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2456 asm_fprintf (FILE, "\tlaj\t$+4\n"); \
2457 asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2458 asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2459 asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2460 asm_fprintf (FILE, "\tbud\tar1\n"); \
2461 asm_fprintf (FILE, "\tnop\n"); \
2462 asm_fprintf (FILE, "\tnop\n"); \
2463 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2464 asm_fprintf (FILE, "\t.word\t0\n"); \
2465 asm_fprintf (FILE, "\t.word\t0\n"); \
2469 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2474 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2475 size_int (16), 0, 1); \
2476 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2477 gen_rtx (CONST_INT, VOIDmode, 0x5069), \
2478 size_int (16), 0, 1); \
2479 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2480 emit_move_insn (gen_rtx (MEM, QImode, \
2481 plus_constant (tramp, 0)), tmp1); \
2482 tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
2484 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2485 gen_rtx (CONST_INT, VOIDmode, 0x1069), \
2486 size_int (16), 0, 1); \
2487 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2488 emit_move_insn (gen_rtx (MEM, QImode, \
2489 plus_constant (tramp, 2)), tmp1); \
2490 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2491 size_int (16), 0, 1); \
2492 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2493 gen_rtx (CONST_INT, VOIDmode, 0x5068), \
2494 size_int (16), 0, 1); \
2495 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2496 emit_move_insn (gen_rtx (MEM, QImode, \
2497 plus_constant (tramp, 3)), tmp1); \
2498 tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
2500 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2501 gen_rtx (CONST_INT, VOIDmode, 0x1068), \
2502 size_int (16), 0, 1); \
2503 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2504 emit_move_insn (gen_rtx (MEM, QImode, \
2505 plus_constant (tramp, 6)), tmp1); \
2509 emit_move_insn (gen_rtx (MEM, QImode, \
2510 plus_constant (TRAMP, 8)), FNADDR); \
2511 emit_move_insn (gen_rtx (MEM, QImode, \
2512 plus_constant (TRAMP, 9)), CXT); \
2516 /* Specify the machine mode that this machine uses for the index in
2517 the tablejump instruction. */
2519 #define CASE_VECTOR_MODE Pmode
2521 /* Max number of (32-bit) bytes we can move from memory to memory
2522 in one reasonably fast instruction. */
2526 /* MOVE_RATIO is the number of move instructions that is better than a
2529 #define MOVE_RATIO 2 /* Default value */
2531 #define BSS_SECTION_ASM_OP ".bss"
2533 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2534 asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2536 /* This is how to output an insn to pop a register from the stack.
2537 It need not be very fast code. */
2539 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2540 asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2542 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2543 is done just by pretending it is already truncated. */
2545 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2547 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2549 /* We need to use direct addressing for large constants and addresses
2550 that cannot fit within an instruction. We must check for these
2551 after after the final jump optimisation pass, since this may
2552 introduce a local_move insn for a SYMBOL_REF. This pass
2553 must come before delayed branch slot filling since it can generate
2554 additional instructions. */
2556 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2558 #define DBR_OUTPUT_SEQEND(FILE) \
2559 if (final_sequence != NULL_RTX) \
2562 int laj = GET_CODE (XVECEXP (final_sequence, 0, 0)) == CALL_INSN; \
2564 count = dbr_sequence_length(); \
2565 while (count < (laj ? 2 : 3)) \
2567 fputs("\tnop\n", FILE); \
2571 fputs("\tpush\tr11\n", FILE); \
2574 #define NO_FUNCTION_CSE
2576 /* We don't want a leading tab. */
2578 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2580 /* Define the codes that are matched by predicates in c4x.c. */
2582 #define PREDICATE_CODES \
2583 {"fp_zero_operand", {CONST_DOUBLE}}, \
2584 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2585 {"stik_const_operand", {CONST_INT}}, \
2586 {"not_const_operand", {CONST_INT}}, \
2587 {"reg_operand", {REG, SUBREG}}, \
2588 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2589 {"r0r1_reg_operand", {REG, SUBREG}}, \
2590 {"r2r3_reg_operand", {REG, SUBREG}}, \
2591 {"ext_low_reg_operand", {REG, SUBREG}}, \
2592 {"ext_reg_operand", {REG, SUBREG}}, \
2593 {"std_reg_operand", {REG, SUBREG}}, \
2594 {"addr_reg_operand", {REG, SUBREG}}, \
2595 {"index_reg_operand", {REG, SUBREG}}, \
2596 {"dp_reg_operand", {REG}}, \
2597 {"sp_reg_operand", {REG}}, \
2598 {"st_reg_operand", {REG}}, \
2599 {"rc_reg_operand", {REG}}, \
2600 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2601 {"dst_operand", {SUBREG, REG, MEM}}, \
2602 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2603 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2604 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2605 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2606 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2607 {"par_ind_operand", {MEM}}, \
2608 {"parallel_operand", {SUBREG, REG, MEM}}, \
2609 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2610 {"mem_operand", {MEM}},
2613 /* Variables in c4x.c */
2615 extern enum reg_class c4x_regclass_map[];/* smallest class containing REGNO */
2616 extern enum machine_mode c4x_caller_save_map[];
2618 extern struct rtx_def *c4x_compare_op0; /* operand 0 for comparisons */
2619 extern struct rtx_def *c4x_compare_op1; /* operand 1 for comparisons */
2621 extern int c4x_rpts_cycles; /* max cycles for RPTS */
2622 extern int c4x_cpu_version; /* cpu version C30/31/32/40/44 */
2624 /* Functions in c4x.c */
2626 extern void c4x_function_prologue ();
2628 extern void c4x_function_epilogue ();
2630 extern struct rtx_def *c4x_operand_subword ();
2632 extern struct rtx_def *c4x_adj_offsettable_operand ();
2634 extern char *c4x_output_cbranch ();
2636 extern int c4x_null_epilogue_p ();
2638 extern int c4x_autoinc_operand ();
2640 extern int c4x_label_conflict ();
2642 extern int c4x_address_conflict ();
2644 extern int c4x_adjust_cost ();
2646 extern void c4x_process_after_reload ();
2648 extern void c4x_combine_parallel ();
2650 extern int c4x_rptb_nop_p ();
2652 extern int c4x_rptb_rpts_p ();
2654 extern int fp_zero_operand ();
2656 extern int const_operand ();
2658 extern int stik_const_operand ();
2660 extern int not_const_operand ();
2662 extern int parallel_operand ();
2664 extern int reg_or_const_operand ();
2666 extern int reg_operand ();
2668 extern int mixed_subreg_operand ();
2670 extern int reg_imm_operand ();
2672 extern int r0r1_reg_operand ();
2674 extern int r2r3_reg_operand ();
2676 extern int ext_low_reg_operand ();
2678 extern int ext_reg_operand ();
2680 extern int std_reg_operand ();
2682 extern int dst_operand ();
2684 extern int src_operand ();
2686 extern int src_hi_operand ();
2688 extern int lsrc_operand ();
2690 extern int tsrc_operand ();
2692 extern int addr_reg_operand ();
2694 extern int index_reg_operand ();
2696 extern int dp_reg_operand ();
2698 extern int sp_reg_operand ();
2700 extern int rc_reg_operand ();
2702 extern int st_reg_operand ();
2704 extern int symbolic_address_operand ();
2706 extern int ar0_reg_operand ();
2708 extern int ar0_mem_operand ();
2710 extern int ar1_reg_operand ();
2712 extern int ar1_mem_operand ();
2714 extern int ar2_reg_operand ();
2716 extern int ar2_mem_operand ();
2718 extern int ar3_reg_operand ();
2720 extern int ar3_mem_operand ();
2722 extern int ar4_reg_operand ();
2724 extern int ar4_mem_operand ();
2726 extern int ar5_reg_operand ();
2728 extern int ar5_mem_operand ();
2730 extern int ar6_reg_operand ();
2732 extern int ar6_mem_operand ();
2734 extern int ar7_reg_operand ();
2736 extern int ar7_mem_operand ();
2738 extern int ir0_reg_operand ();
2740 extern int ir0_mem_operand ();
2742 extern int ir1_reg_operand ();
2744 extern int ir1_mem_operand ();
2746 extern int group1_reg_operand ();
2748 extern int group1_mem_operand ();
2750 extern int arx_reg_operand ();
2752 extern int call_address_operand ();
2754 extern int par_ind_operand ();
2756 extern int not_rc_reg ();
2758 extern int not_modify_reg ();
2760 extern int c4x_shiftable_constant ();
2762 extern int c4x_H_constant ();
2764 extern int c4x_I_constant ();
2766 extern int c4x_J_constant ();
2768 extern int c4x_L_constant ();
2770 extern int c4x_Q_constraint ();
2772 extern int c4x_R_constraint ();
2774 extern int c4x_S_constraint ();
2776 extern int c4x_T_constraint ();
2778 extern int c4x_U_constraint ();
2780 extern void c4x_emit_libcall ();
2782 extern void c4x_emit_libcall3 ();
2784 extern void c4x_emit_libcall_mulhi ();
2786 extern int c4x_emit_move_sequence ();
2788 extern int legitimize_operands ();
2790 extern int valid_operands ();
2792 extern int valid_parallel_load_store ();
2794 extern int valid_parallel_operands_4 ();
2796 extern int valid_parallel_operands_5 ();
2798 extern int valid_parallel_operands_6 ();
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