1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
4 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
5 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 1, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Set the following so that some of the macros expand to function
25 calls to simplify debugging. */
28 /* RUN-TIME TARGET SPECIFICATION */
32 /* Name of the c4x assembler */
34 #define ASM_PROG "c4x-as"
36 /* Name of the c4x linker */
38 #define LD_PROG "c4x-ld"
40 /* Define assembler options */
43 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
44 %{!m30:%{!m40:-m40}}}}}}} \
55 %{mmemparm:-p} %{mregparm:-r} \
56 %{!mmemparm:%{!mregparm:-r}} \
57 %{mbig:-b} %{msmall:-s} \
58 %{!msmall:%{!mbig:-b}}"
60 /* Define linker options */
63 %{m30:--architecture c3x} \
64 %{m31:--architecture c3x} \
65 %{m32:--architecture c3x} \
66 %{mcpu=30:--architecture c3x} \
67 %{mcpu=31:--architecture c3x} \
68 %{mcpu=32:--architecture c3x}"
70 /* Define C preprocessor options. */
73 %{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
74 %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
75 %{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
76 %{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
77 %{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
78 %{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
79 %{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
80 %{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
81 %{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
82 %{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
83 %{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
84 %{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
85 %{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
86 %{!mmemparm:%{!mregparm:-D_REGPARM }} \
87 %{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
88 %{!msmall:%{!mbig:-D_BIGMODEL }} \
89 %{finline-functions:-D_INLINE }"
91 /* Specify the startup file to link with. */
93 #define STARTFILE_SPEC "\
94 %{!mmemparm:%{m30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
95 %{mmemparm:%{m30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
96 %{!mmemparm:%{m31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
97 %{mmemparm:%{m31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
98 %{!mmemparm:%{m32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
99 %{mmemparm:%{m32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
100 %{!mmemparm:%{mcpu=30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
101 %{mmemparm:%{mcpu=30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
102 %{!mmemparm:%{mcpu=31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
103 %{mmemparm:%{mcpu=31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
104 %{!mmemparm:%{mcpu=32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
105 %{mmemparm:%{mcpu=32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
106 %{!mmemparm:%{m40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
107 %{mmemparm:%{m40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
108 %{!mmemparm:%{m44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
109 %{mmemparm:%{m44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
110 %{!mmemparm:%{mcpu=40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
111 %{mmemparm:%{mcpu=40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
112 %{!mmemparm:%{mcpu=44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
113 %{mmemparm:%{mcpu=44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
114 %{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
115 %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sr%O%s}}}}}}}}}}}} \
116 %{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
117 %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sm%O%s}}}}}}}}}}}} \
118 %{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
119 %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4br%O%s}}}}}}}}}}}} \
120 %{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
121 %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4bm%O%s}}}}}}}}}}}}"
123 /* Specify the end file to link with */
125 #define ENDFILE_SPEC ""
127 /* Target compilation option flags */
129 #define SMALL_MEMORY_FLAG 0x0000001 /* small memory model */
130 #define MPYI_FLAG 0x0000002 /* use 24-bit MPYI for C3x */
131 #define FAST_FIX_FLAG 0x0000004 /* fast fixing of floats */
132 #define RPTS_FLAG 0x0000008 /* allow use of RPTS */
133 #define C3X_FLAG 0x0000010 /* emit C3x code */
134 #define TI_FLAG 0x0000020 /* be compatible with TI assembler */
135 #define PARANOID_FLAG 0x0000040 /* be paranoid about DP reg. in ISRs */
136 #define MEMPARM_FLAG 0x0000080 /* pass arguments on stack */
137 #define DEVEL_FLAG 0x0000100 /* enable features under development */
138 #define RPTB_FLAG 0x0000200 /* enable repeat block */
139 #define BK_FLAG 0x0000400 /* use BK as general register */
140 #define DB_FLAG 0x0000800 /* use decrement and branch for C3x */
141 #define DEBUG_FLAG 0x0001000 /* enable debugging of GCC */
142 #define HOIST_FLAG 0x0002000 /* force constants into registers */
143 #define LOOP_UNSIGNED_FLAG 0x0004000 /* allow unsigned loop counters */
144 #define FORCE_FLAG 0x0008000 /* force op0 and op1 to be same */
145 #define PRESERVE_FLOAT_FLAG 0x0010000 /* save all 40 bits for floats */
146 #define PARALLEL_PACK_FLAG 0x0020000 /* allow parallel insn packing */
147 #define PARALLEL_MPY_FLAG 0x0040000 /* allow MPY||ADD, MPY||SUB insns */
148 #define ALIASES_FLAG 0x0080000 /* assume mem refs possibly aliased */
150 #define C30_FLAG 0x0100000 /* emit C30 code */
151 #define C31_FLAG 0x0200000 /* emit C31 code */
152 #define C32_FLAG 0x0400000 /* emit C32 code */
153 #define C40_FLAG 0x1000000 /* emit C40 code */
154 #define C44_FLAG 0x2000000 /* emit C44 code */
156 /* Run-time compilation parameters selecting different hardware subsets.
158 Macro to define tables used to set the flags.
159 This is a list in braces of pairs in braces,
160 each pair being { "NAME", VALUE }
161 where VALUE is the bits to set or minus the bits to clear.
162 An empty string NAME is used to identify the default VALUE. */
164 #define TARGET_SWITCHES \
165 { { "small", SMALL_MEMORY_FLAG }, \
166 { "big", -SMALL_MEMORY_FLAG }, \
167 { "mpyi", MPYI_FLAG}, \
168 { "no-mpyi", -MPYI_FLAG}, \
169 { "fast-fix", FAST_FIX_FLAG}, \
170 { "no-fast-fix", -FAST_FIX_FLAG}, \
171 { "rpts", RPTS_FLAG}, \
172 { "no-rpts", -RPTS_FLAG}, \
173 { "rptb", RPTB_FLAG}, \
174 { "no-rptb", -RPTB_FLAG}, \
181 { "no-ti", -TI_FLAG}, \
182 { "paranoid", PARANOID_FLAG}, \
183 { "no-paranoid", -PARANOID_FLAG}, \
184 { "isr-dp-reload", PARANOID_FLAG}, \
185 { "no-isr-dp-reload", -PARANOID_FLAG}, \
186 { "memparm", MEMPARM_FLAG}, \
187 { "regparm", -MEMPARM_FLAG}, \
188 { "devel", DEVEL_FLAG}, \
189 { "no-devel", -DEVEL_FLAG}, \
191 { "no-bk", -BK_FLAG}, \
193 { "no-db", -DB_FLAG}, \
194 { "debug", DEBUG_FLAG}, \
195 { "no-debug", -DEBUG_FLAG}, \
196 { "hoist", HOIST_FLAG}, \
197 { "no-hoist", -HOIST_FLAG}, \
198 { "no-force", -FORCE_FLAG}, \
199 { "force", FORCE_FLAG}, \
200 { "loop-unsigned", LOOP_UNSIGNED_FLAG}, \
201 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG}, \
202 { "preserve-float", PRESERVE_FLOAT_FLAG}, \
203 { "no-preserve-float", -PRESERVE_FLOAT_FLAG}, \
204 { "parallel-insns", PARALLEL_PACK_FLAG}, \
205 { "no-parallel-mpy", -PARALLEL_MPY_FLAG}, \
206 { "parallel-mpy", PARALLEL_MPY_FLAG}, \
207 { "no-parallel-insns", -PARALLEL_PACK_FLAG}, \
208 { "aliases", ALIASES_FLAG}, \
209 { "no-aliases", -ALIASES_FLAG}, \
210 { "", TARGET_DEFAULT} }
212 /* Default target switches */
214 /* Play safe, not the fastest code. Note that setting PARALLEL_MPY
215 flag will set SMALL_REGISTER_CLASSES which can be a price to pay,
216 especially when MPY||ADD instructions are only generated very
218 #define TARGET_DEFAULT ALIASES_FLAG | RPTB_FLAG | PARALLEL_PACK_FLAG
221 Max iteration count for RPTB/RPTS is 2^31 + 1.
222 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
223 RPTS blocks interrupts. */
226 extern int target_flags;
228 #define TARGET_INLINE 1 /* Inline MPYI */
229 #define TARGET_PARALLEL 1 /* Enable parallel insns in MD */
230 #define TARGET_SMALL_REG_CLASS 1
232 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
233 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
234 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
235 #define TARGET_RPTS (target_flags & RPTS_FLAG)
236 #define TARGET_TI (target_flags & TI_FLAG)
237 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
238 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
239 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
240 #define TARGET_RPTB (target_flags & RPTB_FLAG \
242 #define TARGET_BK (target_flags & BK_FLAG)
243 #define TARGET_DB (!TARGET_C3X || (target_flags & DB_FLAG))
244 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
245 #define TARGET_HOIST (target_flags & HOIST_FLAG)
246 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
247 #define TARGET_FORCE (target_flags & FORCE_FLAG)
248 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
249 #define TARGET_PARALLEL_PACK (TARGET_RPTB \
250 && (target_flags & PARALLEL_PACK_FLAG) \
252 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL_PACK \
253 && (target_flags & PARALLEL_MPY_FLAG))
254 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
256 #define TARGET_C3X (target_flags & C3X_FLAG)
257 #define TARGET_C30 (target_flags & C30_FLAG)
258 #define TARGET_C31 (target_flags & C31_FLAG)
259 #define TARGET_C32 (target_flags & C32_FLAG)
260 #define TARGET_C40 (target_flags & C40_FLAG)
261 #define TARGET_C44 (target_flags & C44_FLAG)
263 /* -mrpts allows the use of the RPTS instruction irregardless.
264 -mrpts=max-cycles will use RPTS if the number of cycles is constant
265 and less than max-cycles. */
267 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
269 /* -mcpu=XX with XX = target DSP version number */
271 /* This macro is similar to `TARGET_SWITCHES' but defines names of
272 command options that have values. Its definition is an
273 initializer with a subgrouping for each command option.
275 Each subgrouping contains a string constant, that defines the
276 fixed part of the option name, and the address of a variable.
277 The variable, type `char *', is set to the variable part of the
278 given option if the fixed part matches. The actual option name
279 is made by appending `-m' to the specified name.
281 Here is an example which defines `-mshort-data-NUMBER'. If the
282 given option is `-mshort-data-512', the variable `m88k_short_data'
283 will be set to the string `"512"'.
285 extern char *m88k_short_data;
286 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
288 extern char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
290 #define TARGET_OPTIONS \
291 { {"rpts=", &c4x_rpts_cycles_string},\
292 {"cpu=", &c4x_cpu_version_string} }
294 /* Sometimes certain combinations of command options do not make sense
295 on a particular target machine. You can define a macro
296 `OVERRIDE_OPTIONS' to take account of this. This macro, if
297 defined, is executed once just after all the command options have
300 extern void c4x_override_options ();
301 #define OVERRIDE_OPTIONS c4x_override_options ()
304 /* Run Time Target Specification */
306 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)" );
310 #define BITS_BIG_ENDIAN 0
311 #define BYTES_BIG_ENDIAN 0
312 #define WORDS_BIG_ENDIAN 0
314 /* Technically, we are little endian, but we put the floats out as
315 whole longs and this makes GCC put them out in the right order. */
317 #define FLOAT_WORDS_BIG_ENDIAN 1
319 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
320 all integral and floating point data types are stored in memory as
321 32-bits (floating point types can be stored as 40-bits in the
322 extended precision registers), so sizeof(char) = sizeof(short) =
323 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
325 #define BITS_PER_UNIT 32
326 #define BITS_PER_WORD 32
327 #define UNITS_PER_WORD 1
328 #define POINTER_SIZE 32
329 #define PARM_BOUNDARY 32
330 #define STACK_BOUNDARY 32
331 #define FUNCTION_BOUNDARY 32
332 #define BIGGEST_ALIGNMENT 32
333 #define EMPTY_FIELD_BOUNDARY 32
334 #define STRICT_ALIGNMENT 0
335 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
336 #define MAX_FIXED_MODE_SIZE 64 /* HImode */
338 /* Use the internal floating point stuff in the compiler and not the
339 host floating point stuff. */
341 #define REAL_ARITHMETIC
343 /* Define register numbers */
345 /* Extended-precision registers */
356 /* Auxiliary (address) registers */
367 /* Data page register */
371 /* Index registers */
376 /* Block size register */
384 /* Status register */
388 /* Misc. interrupt registers */
390 #define DIE_REGNO 22 /* C4x only */
391 #define IE_REGNO 22 /* C3x only */
392 #define IIE_REGNO 23 /* C4x only */
393 #define IF_REGNO 23 /* C3x only */
394 #define IIF_REGNO 24 /* C4x only */
395 #define IOF_REGNO 24 /* C3x only */
397 /* Repeat block registers */
403 /* Additional extended-precision registers */
405 #define R8_REGNO 28 /* C4x only */
406 #define R9_REGNO 29 /* C4x only */
407 #define R10_REGNO 30 /* C4x only */
408 #define R11_REGNO 31 /* C4x only */
410 #define FIRST_PSEUDO_REGISTER 32
412 /* Extended precision registers (low set) */
414 #define IS_R0R1_REG(r) ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
415 #define IS_R2R3_REG(r) ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
416 #define IS_EXT_LOW_REG(r) ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
418 /* Extended precision registers (high set) */
420 #define IS_EXT_HIGH_REG(r) (!TARGET_C3X \
421 && ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
422 /* Address registers */
424 #define IS_AUX_REG(r) (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
425 #define IS_ADDR_REG(r) IS_AUX_REG(r)
426 #define IS_DP_REG(r) ((r) == DP_REGNO)
427 #define IS_INDEX_REG(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
428 #define IS_SP_REG(r) ((r) == SP_REGNO)
429 #define IS_BK_REG(r) (TARGET_BK && (r) == BK_REGNO)
433 #define IS_ST_REG(r) ((r) == ST_REGNO)
434 #define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
436 /* Composite register sets */
438 #define IS_ADDR_OR_INDEX_REG(r) (IS_ADDR_REG(r) || IS_INDEX_REG(r))
439 #define IS_EXT_REG(r) (IS_EXT_LOW_REG(r) || IS_EXT_HIGH_REG(r))
440 #define IS_STD_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_REPEAT_REG(r) \
441 || IS_SP_REG(r) || IS_BK_REG(r))
442 #define IS_INT_REG(r) (IS_EXT_REG(r) || IS_STD_REG(r))
443 #define IS_GROUP1_REG(r) (IS_ADDR_OR_INDEX_REG(r) || IS_BK_REG(r))
446 #define IS_PSEUDO_REG(r) ((r) >= FIRST_PSEUDO_REGISTER)
447 #define IS_R0R1_OR_PSEUDO_REG(r) (IS_R0R1_REG(r) || IS_PSEUDO_REG(r))
448 #define IS_R2R3_OR_PSEUDO_REG(r) (IS_R2R3_REG(r) || IS_PSEUDO_REG(r))
449 #define IS_EXT_OR_PSEUDO_REG(r) (IS_EXT_REG(r) || IS_PSEUDO_REG(r))
450 #define IS_STD_OR_PSEUDO_REG(r) (IS_STD_REG(r) || IS_PSEUDO_REG(r))
451 #define IS_INT_OR_PSEUDO_REG(r) (IS_INT_REG(r) || IS_PSEUDO_REG(r))
452 #define IS_ADDR_OR_PSEUDO_REG(r) (IS_ADDR_REG(r) || IS_PSEUDO_REG(r))
453 #define IS_INDEX_OR_PSEUDO_REG(r) (IS_INDEX_REG(r) || IS_PSEUDO_REG(r))
454 #define IS_EXT_LOW_OR_PSEUDO_REG(r) (IS_EXT_LOW_REG(r) || IS_PSEUDO_REG(r))
455 #define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r))
456 #define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r))
457 #define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r))
459 #define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op)))
460 #define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op)))
461 #define IS_INDEX_REGNO(op) (IS_INDEX_REG(REGNO(op)))
462 #define IS_GROUP1_REGNO(r) (IS_GROUP1_REG(REGNO(op)))
464 #define IS_R0R1_OR_PSEUDO_REGNO(op) (IS_R0R1_OR_PSEUDO_REG(REGNO(op)))
465 #define IS_R2R3_OR_PSEUDO_REGNO(op) (IS_R2R3_OR_PSEUDO_REG(REGNO(op)))
466 #define IS_EXT_OR_PSEUDO_REGNO(op) (IS_EXT_OR_PSEUDO_REG(REGNO(op)))
467 #define IS_STD_OR_PSEUDO_REGNO(op) (IS_STD_OR_PSEUDO_REG(REGNO(op)))
468 #define IS_EXT_LOW_OR_PSEUDO_REGNO(op) (IS_EXT_LOW_OR_PSEUDO_REG(REGNO(op)))
469 #define IS_INT_OR_PSEUDO_REGNO(op) (IS_INT_OR_PSEUDO_REG(REGNO(op)))
471 #define IS_ADDR_OR_PSEUDO_REGNO(op) (IS_ADDR_OR_PSEUDO_REG(REGNO(op)))
472 #define IS_INDEX_OR_PSEUDO_REGNO(op) (IS_INDEX_OR_PSEUDO_REG(REGNO(op)))
473 #define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op)))
474 #define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op)))
475 #define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op)))
477 /* 1 for registers that have pervasive standard uses
478 and are not available for the register allocator. */
480 #define FIXED_REGISTERS \
482 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
484 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
485 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
488 /* 1 for registers not available across function calls.
489 These must include the FIXED_REGISTERS and also any
490 registers that can be used without being saved.
491 The latter must include the registers where values are returned
492 and the register where structure-value addresses are passed.
493 Aside from that, you can include as many other registers as you like.
495 Note that the extended precision registers are only saved in some
496 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
497 get clobbered for a given regno. */
499 #define CALL_USED_REGISTERS \
501 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
502 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
503 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
504 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
507 /* Macro to conditionally modify fixed_regs/call_used_regs. */
509 #define CONDITIONAL_REGISTER_USAGE \
513 fixed_regs[BK_REGNO] = 1; \
514 call_used_regs[BK_REGNO] = 1; \
515 c4x_regclass_map[BK_REGNO] = NO_REGS; \
521 reg_names[DIE_REGNO] = "ie"; /* clobber die */ \
522 reg_names[IF_REGNO] = "if"; /* clobber iie */ \
523 reg_names[IOF_REGNO] = "iof"; /* clobber iif */ \
525 for (i = R8_REGNO; i <= R11_REGNO; i++) \
527 fixed_regs[i] = call_used_regs[i] = 1; \
528 c4x_regclass_map[i] = NO_REGS; \
533 /* Order of Allocation of Registers */
535 /* List the order in which to allocate registers. Each register must be
536 listed once, even those in FIXED_REGISTERS.
538 First allocate registers that don't need preservation across calls,
539 except index and address registers. Then allocate data registers
540 that require preservation across calls (even though this invokes an
541 extra overhead of having to save/restore these registers). Next
542 allocate the address and index registers, since using these
543 registers for arithmetic can cause pipeline stalls. Finally
544 allocated the fixed registers which won't be allocated anyhow. */
546 #define REG_ALLOC_ORDER \
547 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
548 R9_REGNO, R10_REGNO, R11_REGNO, \
549 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
550 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
551 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
552 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
553 IR0_REGNO, IR1_REGNO, \
554 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
557 /* Determine which register classes are very likely used by spill registers.
558 local-alloc.c won't allocate pseudos that have these classes as their
559 preferred class unless they are "preferred or nothing". */
561 #define CLASS_LIKELY_SPILLED_P(CLASS) \
562 ((CLASS) == INDEX_REGS)
564 /* CCmode is wrongly defined in machmode.def It should have a size
565 of UNITS_PER_WORD. */
567 #define HARD_REGNO_NREGS(REGNO, MODE) \
568 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
569 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
572 /* A C expression that is nonzero if the hard register REGNO is preserved
573 across a call in mode MODE. This does not have to include the call used
576 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
577 (((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) \
578 && (MODE) != QFmode \
579 || ((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO) \
580 && ((MODE) != QImode || (MODE) != HImode || (MODE) != Pmode)))
582 /* Specify the modes required to caller save a given hard regno. */
584 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) (c4x_caller_save_map[REGNO])
586 int c4x_hard_regno_mode_ok ();
587 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
590 /* A C expression that is nonzero if it is desirable to choose
591 register allocation so as to avoid move instructions between a
592 value of mode MODE1 and a value of mode MODE2.
594 Value is 1 if it is a good idea to tie two pseudo registers
595 when one has mode MODE1 and one has mode MODE2.
596 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
597 for any hard reg, then this must be 0 for correct output. */
599 #define MODES_TIEABLE_P(MODE1, MODE2) 0
602 /* Define the classes of registers for register constraints in the
603 machine description. Also define ranges of constants.
605 One of the classes must always be named ALL_REGS and include all hard regs.
606 If there is more than one class, another class must be named NO_REGS
607 and contain no registers.
609 The name GENERAL_REGS must be the name of a class (or an alias for
610 another name such as ALL_REGS). This is the class of registers
611 that is allowed by "g" or "r" in a register constraint.
612 Also, registers outside this class are allocated only when
613 instructions express preferences for them.
615 The classes must be numbered in nondecreasing order; that is,
616 a larger-numbered class must never be contained completely
617 in a smaller-numbered class.
619 For any two classes, it is very desirable that there be another
620 class that represents their union. */
627 EXT_LOW_REGS, /* 'q' */
630 INDEX_REGS, /* 'x' */
634 GENERAL_REGS, /* 'r' */
641 #define N_REG_CLASSES (int) LIM_REG_CLASSES
643 #define REG_CLASS_NAMES \
661 /* Define which registers fit in which classes.
662 This is an initializer for a vector of HARD_REG_SET
663 of length N_REG_CLASSES. */
666 #define REG_CLASS_CONTENTS \
668 0x00000000, /* No registers */ \
669 0x00000003, /* 't' R0-R1 */ \
670 0x0000000c, /* 'u' R2-R3 */ \
671 0x000000ff, /* 'q' R0-R7 */ \
672 0xf00000ff, /* 'f' R0-R11 */ \
673 0x0000ff00, /* 'a' AR0-AR7 */ \
674 0x00060000, /* 'x' IR0-IR1 */ \
675 0x00100000, /* 'b' SP */ \
676 0x00080000, /* 'k' BK */ \
677 0x0e1eff00, /* 'c' AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */ \
678 0xfe1effff, /* 'r' R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */\
679 0x00010000, /* 'z' DP */ \
680 0x00200000, /* 'y' ST */ \
681 0xffffffff, /* All registers */ \
684 /* The same information, inverted:
685 Return the class number of the smallest class containing
686 reg number REGNO. This could be a conditional expression
687 or could index an array. */
689 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
691 /* When SMALL_REGISTER_CLASSES is defined, the compiler allows
692 registers explicitly used in the rtl to be used as spill registers but
693 prevents the compiler from extending the lifetime of these registers.
694 Problems can occur if reload has to spill a register used explicitly
695 in the RTL if it has a long lifetime. This is only likely to be a problem
696 with a function having many variables and thus lots of spilling.
698 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
699 is defined since the MPY|ADD insns require the classes R0R1_REGS and
700 R2R3_REGS which are used by the function return registers (R0,R1) and
701 the register arguments (R2,R3), respectively. I'm reluctant to define
702 this macro since it stomps on many potential optimisations. Ideally
703 it should have a register class argument so that not all the register
704 classes gets penalised for the sake of a naughty few... For long
705 double arithmetic we need two additional registers that we can use as
708 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
710 #define BASE_REG_CLASS ADDR_REGS
711 #define INDEX_REG_CLASS INDEX_REGS
714 Constraints for the C4x
716 a - address reg (ar0-ar7)
718 c - other gp int-only reg
719 d - data/int reg (equiv. to f)
721 h - data/long double reg (equiv. to f)
726 x - index register (ir0-ir1)
727 y - status register (st)
730 G - short float 16-bit
731 I - signed 16-bit constant (sign extended)
732 J - signed 8-bit constant (sign extended) (C4x only)
733 K - signed 5-bit constant (sign extended) (C4x only for stik)
734 L - unsigned 16-bit constant
735 M - unsigned 8-bit constant (C4x only)
736 N - ones complement of unsigned 16-bit constant
737 Q - indirect arx + 9-bit signed displacement
738 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
739 R - indirect arx + 5-bit unsigned displacement (C4x only)
740 S - indirect arx + 0, 1, or irn displacement
741 T - direct symbol ref
742 > - indirect with autoincrement
743 < - indirect with autodecrement
744 } - indirect with post-modify
745 { - indirect with pre-modify
748 #define REG_CLASS_FROM_LETTER(CC) \
749 ( ((CC) == 'a') ? ADDR_REGS \
750 : ((CC) == 'b') ? SP_REG \
751 : ((CC) == 'c') ? INT_REGS \
752 : ((CC) == 'd') ? EXT_REGS \
753 : ((CC) == 'f') ? EXT_REGS \
754 : ((CC) == 'h') ? EXT_REGS \
755 : ((CC) == 'k') ? BK_REG \
756 : ((CC) == 'q') ? EXT_LOW_REGS \
757 : ((CC) == 't') ? R0R1_REGS \
758 : ((CC) == 'u') ? R2R3_REGS \
759 : ((CC) == 'x') ? INDEX_REGS \
760 : ((CC) == 'y') ? ST_REG \
761 : ((CC) == 'z') ? DP_REG \
764 /* These assume that REGNO is a hard or pseudo reg number.
765 They give nonzero only if REGNO is a hard reg of the suitable class
766 or a pseudo reg currently allocated to a suitable hard reg.
767 Since they use reg_renumber, they are safe only once reg_renumber
768 has been allocated, which happens in local-alloc.c. */
770 #define REGNO_OK_FOR_BASE_P(REGNO) \
771 (IS_ADDR_REG(REGNO) || IS_ADDR_REG((unsigned)reg_renumber[REGNO]))
773 #define REGNO_OK_FOR_INDEX_P(REGNO) \
774 (IS_INDEX_REG(REGNO) || IS_INDEX_REG((unsigned)reg_renumber[REGNO]))
776 extern enum reg_class c4x_preferred_reload_class ();
777 #define PREFERRED_RELOAD_CLASS(X, CLASS) c4x_preferred_reload_class(X, CLASS)
779 extern enum reg_class c4x_limit_reload_class ();
780 #define LIMIT_RELOAD_CLASS(X, CLASS) c4x_limit_reload_class(X, CLASS)
782 extern enum reg_class c4x_secondary_memory_needed ();
783 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
784 c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
786 #define CLASS_MAX_NREGS(CLASS, MODE) \
787 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
788 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
790 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K' */
792 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R' */
794 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J' */
796 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M' */
798 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I' */
800 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L' */
802 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N' */
804 #define IS_HIGH_CONST(VAL) (!TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
807 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S' */
809 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q' */
811 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
812 && IS_DISP1_CONST (VAL + 1))
814 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
815 && IS_DISP8_CONST (VAL + 1))
817 #define CONST_OK_FOR_LETTER_P(VAL, C) \
818 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
819 : ((C) == 'J') ? (!TARGET_C3X && IS_INT8_CONST (VAL)) \
820 : ((C) == 'K') ? (!TARGET_C3X && IS_INT5_CONST (VAL)) \
821 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
822 : ((C) == 'M') ? (!TARGET_C3X && IS_UINT8_CONST (VAL)) \
823 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
824 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
827 #define CONST_DOUBLE_OK_FOR_LETTER_P(VAL, C) \
828 ( ((C) == 'G') ? (fp_zero_operand (VAL)) \
829 : ((C) == 'H') ? (c4x_H_constant (VAL)) \
832 #define EXTRA_CONSTRAINT(VAL, C) \
833 ( ((C) == 'Q') ? (c4x_Q_constraint (VAL)) \
834 : ((C) == 'R') ? (c4x_R_constraint (VAL)) \
835 : ((C) == 'S') ? (c4x_S_constraint (VAL)) \
836 : ((C) == 'T') ? (c4x_T_constraint (VAL)) \
839 #define SMALL_CONST(VAL, insn) \
840 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
841 ? IS_INT16_CONST (VAL) \
842 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
843 ? IS_NOT_UINT16_CONST (VAL) \
844 : ( (get_attr_data (insn) == DATA_HIGH_16) \
845 ? IS_HIGH_CONST (VAL) \
846 : IS_UINT16_CONST (VAL) \
852 I. Routine calling with arguments in registers
853 ----------------------------------------------
855 The TI C3x compiler has a rather unusual register passing algorithm.
856 Data is passed in the following registers (in order):
858 AR2, R2, R3, RC, RS, RE
860 However, the first and second floating point values are always in R2
861 and R3 (and all other floats are on the stack). Structs are always
862 passed on the stack. If the last argument is an ellipsis, the
863 previous argument is passed on the stack so that its address can be
864 taken for the stdargs macros.
866 Because of this, we have to pre-scan the list of arguments to figure
867 out what goes where in the list.
869 II. Routine calling with arguments on stack
870 -------------------------------------------
872 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
873 variables loc0, loc1, and loc2. After the function prologue has
874 been executed, the stack frame will look like:
876 [stack grows towards increasing addresses]
878 5 I saved reg1 I <= SP points here
888 0 I old FP I <= FP (AR3) points here
899 All local variables (locn) are accessible by means of +FP(n+1)
900 addressing, where n is the local variable number.
902 All stack arguments (argn) are accessible by means of -FP(n-2).
904 The stack pointer (SP) points to the last register saved in the
907 Note that a push instruction performs a preincrement of the stack
908 pointer. (STACK_PUSH_CODE == PRE_INC)
910 III. Registers used in function calling convention
911 --------------------------------------------------
913 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
914 R6...R7 (only by PUSHF, i.e. upper 32 bits)
917 (Because of this model, we only assign FP values in R6, R7 and
918 only assign integer values in R4, R5.)
920 These registers are saved at each function entry and restored at
921 the exit. Also it is expected any of these not affected by any
922 call to user-defined (not service) functions.
924 Not preserved across calls: R0...R3
925 R4...R5 (upper 8 bits)
926 R6...R7 (lower 8 bits)
927 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
929 These registers are used arbitrary in a function without being preserved.
930 It is also expected that any of these can be clobbered by any call.
932 Not used by GCC (except for in user "asm" statements):
933 IE (DIE), IF (IIE), IOF (IIF)
935 These registers are never used by GCC for any data, but can be used
936 with "asm" statements. */
941 /* Basic Stack Layout */
943 /* The stack grows upward, stack frame grows upward, and args grow
946 #define STARTING_FRAME_OFFSET C4X_LOC0
947 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
948 #define ARGS_GROW_DOWNWARD
949 #define STACK_POINTER_OFFSET 1
951 /* Define this if pushing a word on the stack
952 makes the stack pointer a smaller address. */
954 /* #define STACK_GROWS_DOWNWARD */
955 /* Like the dsp16xx, i370, i960, and we32k ports */
957 /* Define this if the nominal address of the stack frame
958 is at the high-address end of the local variables;
959 that is, each additional local variable allocated
960 goes at a more negative offset in the frame. */
962 /* #define FRAME_GROWS_DOWNWARD */
965 /* Registers That Address the Stack Frame */
967 #define STACK_POINTER_REGNUM SP_REGNO /* SP */
968 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3 */
969 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3 */
970 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0 */
972 /* Eliminating Frame Pointer and Arg Pointer */
974 #define FRAME_POINTER_REQUIRED 0
976 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
980 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
981 if (regs_ever_live[regno] && !call_used_regs[regno]) \
982 offset += TARGET_PRESERVE_FLOAT \
983 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
985 (DEPTH) = -(offset + get_frame_size ()); \
988 /* This is a hack... We need to specify a register. */
989 #define ELIMINABLE_REGS \
990 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
992 #define CAN_ELIMINATE(FROM, TO) \
993 (!(((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
994 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
996 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1000 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1001 if (regs_ever_live[regno] && !call_used_regs[regno]) \
1002 offset += TARGET_PRESERVE_FLOAT \
1003 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1005 (OFFSET) = -(offset + get_frame_size ()); \
1009 /* Passing Function Arguments on the Stack */
1012 #define PUSH_ROUNDING(BYTES) (BYTES)
1014 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1016 /* The following structure is used by calls.c, function.c, c4x.c */
1018 typedef struct c4x_args
1031 extern void c4x_init_cumulative_args();
1033 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1034 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1036 extern void c4x_function_arg_advance();
1038 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1039 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1041 extern struct rtx_def *c4x_function_arg();
1043 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1044 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1046 /* Define the profitability of saving registers around calls.
1047 NOTE: For now we turn this off because caller-save assumes
1048 that a register with a QFmode quantity can be saved/restored
1051 /* #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 */
1053 /* Never pass data by reference. */
1055 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1057 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1059 /* 1 if N is a possible register number for function argument passing. */
1061 #define FUNCTION_ARG_REGNO_P(REGNO) \
1062 ( ( ((REGNO) == AR2_REGNO) /* AR2 */ \
1063 || ((REGNO) == R2_REGNO) /* R2 */ \
1064 || ((REGNO) == R3_REGNO) /* R3 */ \
1065 || ((REGNO) == RC_REGNO) /* RC */ \
1066 || ((REGNO) == RS_REGNO) /* RS */ \
1067 || ((REGNO) == RE_REGNO)) /* RE */ \
1071 /* How Scalar Function Values Are Returned */
1073 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1074 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0 */
1076 #define LIBCALL_VALUE(MODE) \
1077 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0 */
1079 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1081 /* How Large Values Are Returned */
1083 #define DEFAULT_PCC_STRUCT_RETURN 0
1084 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0 */
1087 /* Function Entry and Exit */
1089 #define FUNCTION_PROLOGUE(FILE, SIZE) c4x_function_prologue(FILE, SIZE)
1090 #define FUNCTION_EPILOGUE(FILE, SIZE) c4x_function_epilogue(FILE, SIZE)
1093 /* Generating Code for Profiling */
1095 /* Note that the generated assembly uses the ^ operator to load the 16
1096 MSBs of the address. This is not supported by the TI assembler. */
1098 #define FUNCTION_PROFILER(FILE, LABELNO) \
1101 fprintf (FILE, "\tpush\tar2\n"); \
1102 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1103 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1104 fprintf (FILE, "\tcall\tmcount\n"); \
1105 fprintf (FILE, "\tpop\tar2\n"); \
1109 fprintf (FILE, "\tpush\tar2\n"); \
1110 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1111 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1112 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1113 fprintf (FILE, "\tcall\tmcount\n"); \
1114 fprintf (FILE, "\tpop\tar2\n"); \
1117 /* There are three profiling modes for basic blocks available.
1118 The modes are selected at compile time by using the options
1119 -a or -ax of the gnu compiler.
1120 The variable `profile_block_flag' will be set according to the
1123 profile_block_flag == 0, no option used:
1127 profile_block_flag == 1, -a option used.
1129 Count frequency of execution of every basic block.
1131 profile_block_flag == 2, -ax option used.
1133 Generate code to allow several different profiling modes at run time.
1134 Available modes are:
1135 Produce a trace of all basic blocks.
1136 Count frequency of jump instructions executed.
1137 In every mode it is possible to start profiling upon entering
1138 certain functions and to disable profiling of some other functions.
1140 The result of basic-block profiling will be written to a file `bb.out'.
1141 If the -ax option is used parameters for the profiling will be read
1146 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) \
1147 if (profile_block_flag == 2) \
1151 fprintf (FILE, "\tpush\tst\n"); \
1152 fprintf (FILE, "\tpush\tar2\n"); \
1153 fprintf (FILE, "\tpush\tr2\n"); \
1154 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1155 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1156 if (BLOCKNO > 32767) \
1158 fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16); \
1159 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1163 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1165 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1166 fprintf (FILE, "\tpop\tr2\n"); \
1167 fprintf (FILE, "\tpop\tar2\n"); \
1168 fprintf (FILE, "\tpop\tst\n"); \
1172 fprintf (FILE, "\tpush\tst\n"); \
1173 fprintf (FILE, "\tpush\tar2\n"); \
1174 fprintf (FILE, "\tpush\tr2\n"); \
1175 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1176 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1177 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1178 if (BLOCKNO > 32767) \
1180 fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16); \
1181 fprintf (FILE, "\tlsh\t16,r2\n"); \
1182 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1186 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1188 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1189 fprintf (FILE, "\tpop\tr2\n"); \
1190 fprintf (FILE, "\tpop\tar2\n"); \
1191 fprintf (FILE, "\tpop\tst\n"); \
1198 fprintf (FILE, "\tpush\tst\n"); \
1199 fprintf (FILE, "\tpush\tar2\n"); \
1200 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1201 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1202 fprintf (FILE, "\tcmpi\t0,*ar2\n"); \
1203 fprintf (FILE, "\tbne\t$+2\n"); \
1204 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1205 fprintf (FILE, "\tpop\tar2\n"); \
1206 fprintf (FILE, "\tpop\tst\n"); \
1210 fprintf (FILE, "\tpush\tst\n"); \
1211 fprintf (FILE, "\tpush\tar2\n"); \
1212 fprintf (FILE, "\tpush\tr2\n"); \
1213 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1214 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1215 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1216 fprintf (FILE, "\tldi\t*ar2,r2\n"); \
1217 fprintf (FILE, "\tbne\t$+2\n"); \
1218 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1219 fprintf (FILE, "\tpop\tr2\n"); \
1220 fprintf (FILE, "\tpop\tar2\n"); \
1221 fprintf (FILE, "\tpop\tst\n"); \
1225 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1226 if (profile_block_flag == 2) \
1230 fprintf (FILE, "\tpush\tst\n"); \
1231 fprintf (FILE, "\tpush\tar2\n"); \
1232 fprintf (FILE, "\tpush\tar0\n"); \
1233 fprintf (FILE, "\tldhi\t^___bb,ar2\n"); \
1234 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1235 if (BLOCKNO > 32767) \
1237 fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
1238 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1242 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1244 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1245 fprintf (FILE, "\tldhi\t^LPBX0,ar0\n"); \
1246 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1247 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1248 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1249 fprintf (FILE, "\tpop\tar0\n"); \
1250 fprintf (FILE, "\tpop\tar2\n"); \
1251 fprintf (FILE, "\tpop\tst\n"); \
1255 fprintf (FILE, "\tpush\tst\n"); \
1256 fprintf (FILE, "\tpush\tar2\n"); \
1257 fprintf (FILE, "\tpush\tar0\n"); \
1258 fprintf (FILE, "\tldiu\t^___bb,ar2\n"); \
1259 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1260 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1261 if (BLOCKNO > 32767) \
1263 fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16); \
1264 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1265 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1269 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1271 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1272 fprintf (FILE, "\tldiu\t^LPBX0,ar0\n"); \
1273 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1274 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1275 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1276 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1277 fprintf (FILE, "\tpop\tar0\n"); \
1278 fprintf (FILE, "\tpop\tar2\n"); \
1279 fprintf (FILE, "\tpop\tst\n"); \
1286 fprintf (FILE, "\tpush\tar2\n"); \
1287 fprintf (FILE, "\tpush\tar0\n"); \
1288 fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1289 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1290 fprintf (FILE, "\taddi3\t1,*ar2,ar0\n"); \
1291 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1292 fprintf (FILE, "\tpop\tar0\n"); \
1293 fprintf (FILE, "\tpop\tar2\n"); \
1297 fprintf (FILE, "\tpush\tar2\n"); \
1298 fprintf (FILE, "\tpush\tar0\n"); \
1299 fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1300 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1301 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1302 fprintf (FILE, "\tldiu\t*ar2,ar0\n"); \
1303 fprintf (FILE, "\taddi\t1,ar0\n"); \
1304 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1305 fprintf (FILE, "\tpop\tar0\n"); \
1306 fprintf (FILE, "\tpop\tar2\n"); \
1310 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1312 fprintf (FILE, "\tpush\tst\n"); \
1313 fprintf (FILE, "\tpush\tar2\n"); \
1314 fprintf (FILE, "\tcall\t___bb_trace_ret\n"); \
1315 fprintf (FILE, "\tpop\tar2\n"); \
1316 fprintf (FILE, "\tpop\tst\n"); \
1319 #define MACHINE_STATE_SAVE(ID) \
1330 asm(" .if .BIGMODEL"); \
1339 asm(" .if .tms320C40"); \
1343 asm(" pushf r10"); \
1345 asm(" pushf r11"); \
1348 #define MACHINE_STATE_RESTORE(ID) \
1349 asm(" .if .tms320C40"); \
1363 asm(" .if .BIGMODEL"); \
1377 /* Implicit Calls to Library Routines */
1379 #define MULQI3_LIBCALL "__mulqi3"
1380 #define DIVQI3_LIBCALL "__divqi3"
1381 #define UDIVQI3_LIBCALL "__udivqi3"
1382 #define MODQI3_LIBCALL "__modqi3"
1383 #define UMODQI3_LIBCALL "__umodqi3"
1385 #define DIVQF3_LIBCALL "__divqf3"
1387 #define MULHF3_LIBCALL "__mulhf3"
1388 #define DIVHF3_LIBCALL "__divhf3"
1390 #define MULHI3_LIBCALL "__mulhi3"
1391 #define SMULHI3_LIBCALL "__smulhi3_high"
1392 #define UMULHI3_LIBCALL "__umulhi3_high"
1393 #define DIVHI3_LIBCALL "__divhi3"
1394 #define UDIVHI3_LIBCALL "__udivhi3"
1395 #define MODHI3_LIBCALL "__modhi3"
1396 #define UMODHI3_LIBCALL "__umodhi3"
1398 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1399 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1400 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1401 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1403 #define FLOATHIHF2_LIBCALL "__floathihf2"
1404 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1405 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1406 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1408 #define FFS_LIBCALL "__ffs"
1410 #define TARGET_MEM_FUNCTIONS
1412 /* Add any extra modes needed to represent the condition code.
1414 On the C4x, we have a "no-overflow" mode which is used when an ADD,
1415 SUB, NEG, or MPY insn is used to set the condition code. This is
1416 to prevent the combiner from optimising away a following CMP of the
1417 result with zero when a signed conditional branch or load insn
1420 The problem is a subtle one and deals with the manner in which the
1421 negative condition (N) flag is used on the C4x. This flag does not
1422 reflect the status of the actual result but of the ideal result had
1423 no overflow occured (when considering signed operands).
1425 For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
1426 the flags reflect the untruncated result, not the actual result.
1427 While the actual result is less than zero, the N flag is not set
1428 since the ideal result of the addition without truncation would
1431 Note that the while the N flag is handled differently to most other
1432 architectures, the use of it is self consistent and is not the
1433 cause of the problem.
1435 Logical operations set the N flag to the MSB of the result so if
1436 the result is negative, N is 1. However, integer and floating
1437 point operations set the N flag to be the MSB of the result
1438 exclusive ored with the overflow (V) flag. Thus if an overflow
1439 occurs and the result does not have the MSB set (i.e., the result
1440 looks like a positive number), the N flag is set. Conversely, if
1441 an overflow occurs and the MSB of the result is set, N is set to 0.
1442 Thus the N flag represents the sign of the result if it could have
1443 been stored without overflow but does not represent the apparent
1444 sign of the result. Note that most architectures set the N flag to
1445 be the MSB of the result.
1447 The C4x approach to setting the N flag simplifies signed
1448 conditional branches and loads which only have to test the state of
1449 the N flag, whereas most architectures have to look at both the N
1450 and V flags. The disadvantage is that there is no flag giving the
1451 status of the sign bit of the operation. However, there are no
1452 conditional load or branch instructions that make use of this
1453 feature (e.g., BMI---branch minus) instruction. Note that BN and
1454 BLT are identical in the C4x.
1456 To handle the problem where the N flag is set differently whenever
1457 there is an overflow we use a different CC mode, CC_NOOVmode which
1458 says that the CC reflects the comparison of the result against zero
1459 if no overflow occured.
1463 [(set (reg:CC_NOOV 21)
1464 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
1465 (match_operand:QI 2 "src_operand" ""))
1467 (set (match_operand:QI 0 "ext_reg_operand" "")
1468 (minus:QI (match_dup 1)
1471 Note that there is no problem for insns that don't return a result
1472 like CMP, since the CC reflects the effect of operation.
1474 An example of a potential problem is when GCC
1475 converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
1476 to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
1477 to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
1479 Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
1480 C4x sets the N flag since the result without overflow would have
1481 been 0xffffffff when treating the operands as signed integers.
1482 Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
1483 flag but (GE (0x00000001)) does not set the N flag.
1485 The upshot is that we can not use signed branch and conditional
1486 load instructions after an add, subtract, neg, abs or multiply.
1487 We must emit a compare insn to check the result against 0. */
1489 #define EXTRA_CC_MODES CC_NOOVmode
1491 /* Define the names for the modes specified above. */
1493 #define EXTRA_CC_NAMES "CC_NOOV"
1495 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1497 CCmode should be used when no special processing is needed. */
1498 #define SELECT_CC_MODE(OP,X,Y) \
1499 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1500 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1501 || GET_MODE (X) == ABS \
1502 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1503 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1504 || GET_MODE (Y) == ABS) \
1505 ? CC_NOOVmode : CCmode)
1507 extern struct rtx_def *c4x_gen_compare_reg ();
1509 /* Addressing Modes */
1511 #define HAVE_POST_INCREMENT
1512 #define HAVE_PRE_INCREMENT
1513 #define HAVE_POST_DECREMENT
1514 #define HAVE_PRE_DECREMENT
1515 #define HAVE_PRE_MODIFY_REG
1516 #define HAVE_POST_MODIFY_REG
1517 #define HAVE_PRE_MODIFY_DISP
1518 #define HAVE_POST_MODIFY_DISP
1520 /* What about LABEL_REF? */
1521 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1523 #define MAX_REGS_PER_ADDRESS 2
1525 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1526 and check its validity for a certain class.
1527 We have two alternate definitions for each of them.
1528 The usual definition accepts all pseudo regs; the other rejects
1529 them unless they have been allocated suitable hard regs.
1530 The symbol REG_OK_STRICT causes the latter definition to be used.
1532 Most source files want to accept pseudo regs in the hope that
1533 they will get allocated to the class that the insn wants them to be in.
1534 Source files for reload pass need to be strict.
1535 After reload, it makes no difference, since pseudo regs have
1536 been eliminated by then. */
1538 extern int c4x_check_legit_addr ();
1540 #ifndef REG_OK_STRICT
1542 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1544 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(REGNO(X))
1546 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1548 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(REGNO(X))
1550 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1552 if (c4x_check_legit_addr (MODE, X, 0)) \
1558 /* Nonzero if X is a hard reg that can be used as an index. */
1560 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1562 /* Nonzero if X is a hard reg that can be used as a base reg. */
1564 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1566 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1568 if (c4x_check_legit_addr (MODE, X, 1)) \
1574 extern struct rtx_def *c4x_legitimize_address ();
1575 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1578 new = c4x_legitimize_address (X, MODE); \
1579 if (new != NULL_RTX) \
1587 /* No mode-dependent addresses on the C4x are autoincrements. */
1589 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1590 if (GET_CODE (ADDR) == PRE_DEC \
1591 || GET_CODE (ADDR) == POST_DEC \
1592 || GET_CODE (ADDR) == PRE_INC \
1593 || GET_CODE (ADDR) == POST_INC \
1594 || GET_CODE (ADDR) == POST_MODIFY \
1595 || GET_CODE (ADDR) == PRE_MODIFY) \
1599 /* Nonzero if the constant value X is a legitimate general operand.
1600 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1602 The C4x can only load 16-bit immediate values, so we only allow
1603 a restricted subset of CONST_INT and CONST_DOUBLE and reject
1604 LABEL_REF, SYMBOL_REF, CONST, and HIGH codes. */
1606 #define LEGITIMATE_CONSTANT_P(X) \
1607 (GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X) \
1608 || GET_CODE (X) == CONST_INT && c4x_I_constant (X))
1611 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1613 /* Descripting Relative Cost of Operations */
1615 /* Provide the costs of a rtl expression. This is in the body of a
1618 Note that we return, rather than break so that rtx_cost doesn't
1619 include CONST_COSTS otherwise expand_mult will think that it is
1620 cheaper to synthesise a multiply rather than to use a multiply
1621 instruction. I think this is because the algorithm synth_mult
1622 doesn't take into account the loading of the operands, whereas the
1623 calculation of mult_cost does.
1627 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1629 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1630 || TARGET_MPYI ? 1 : 14); \
1631 case DIV: case UDIV: case MOD: case UMOD: \
1632 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1635 /* Compute the cost of computing a constant rtl expression RTX
1636 whose rtx-code is CODE. The body of this macro is a portion
1637 of a switch statement. If the code is computed here,
1638 return it with a return statement. Otherwise, break from the switch.
1640 An insn is assumed to cost 4 units.
1641 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1643 Some small integers are effectively free for the C40. We should
1644 also consider if we are using the small memory model. With
1645 the big memory model we require an extra insn for a constant
1646 loaded from memory. */
1648 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1650 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1651 || (C) == IOR || (C) == XOR)
1653 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1655 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1657 if (c4x_J_constant (RTX)) \
1659 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1661 if (LOGICAL_CODE_P (OUTER_CODE) \
1662 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1668 case CONST_DOUBLE: \
1669 if (c4x_H_constant (RTX)) \
1671 if (GET_MODE (RTX) == QFmode) \
1676 /* Compute the cost of an address. This is meant to approximate the size
1677 and/or execution delay of an insn using that address. If the cost is
1678 approximated by the RTL complexity, including CONST_COSTS above, as
1679 is usually the case for CISC machines, this macro should not be defined.
1680 For aggressively RISCy machines, only one insn format is allowed, so
1681 this macro should be a constant. The value of this macro only matters
1682 for valid addresses. We handle the most common address without
1683 a call to c4x_address_cost. */
1685 extern int c4x_address_cost ();
1687 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1689 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1690 if (REG_P (OP1) && ! REG_P (OP0)) \
1692 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1693 CODE = swap_condition (CODE); \
1696 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1697 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1698 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1699 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1700 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1702 /* Make the Rx register a little easier to use so they are used for
1703 calculations and the ARx registers are used for addressing. */
1705 #define REGISTER_MOVE_COST(FROM, TO) \
1706 (EXPENSIVE_CLASS_P(TO) ? 5 : EXPENSIVE_CLASS_P(FROM) ? 4 : 3)
1708 /* Memory move cost is same as fast register move. Maybe this should
1711 #define MEMORY_MOVE_COST(M,C,I) 4
1713 /* Branches are kind of expensive (even with delayed branching) so
1714 make their cost higher. */
1716 #define BRANCH_COST 8
1718 /* Adjust the cost of dependencies. */
1720 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1721 (COST) = c4x_adjust_cost (INSN, LINK, DEP, COST)
1723 #define WORD_REGISTER_OPERATIONS
1725 /* Dividing the Output into Sections */
1727 #define TEXT_SECTION_ASM_OP "\t.text"
1729 #define DATA_SECTION_ASM_OP "\t.data"
1731 #define USE_CONST_SECTION 1
1733 #define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
1735 /* Do not use .init section so __main will be called on startup. This will
1736 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1739 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1742 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1744 /* Support const sections and the ctors and dtors sections for g++.
1745 Note that there appears to be two different ways to support const
1746 sections at the moment. You can either #define the symbol
1747 READONLY_DATA_SECTION (giving it some code which switches to the
1748 readonly data section) or else you can #define the symbols
1749 EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
1750 SELECT_RTX_SECTION. We do both here just to be on the safe side. */
1752 /* Define a few machine-specific details of the implementation of
1755 The __CTORS_LIST__ goes in the .ctors section. Define CTOR_LIST_BEGIN
1756 and CTOR_LIST_END to contribute to the .ctors section an instruction to
1757 push a word containing 0 (or some equivalent of that).
1759 Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */
1761 #define CTORS_SECTION_ASM_OP "\t.sect\t\".ctors\""
1762 #define DTORS_SECTION_ASM_OP "\t.sect\t\".dtors\""
1764 /* Constructor list on stack is in reverse order. Go to the end of the
1765 list and go backwards to call constructors in the right order. */
1767 #define DO_GLOBAL_CTORS_BODY \
1769 extern func_ptr __CTOR_LIST__[]; \
1770 func_ptr *p, *beg = __CTOR_LIST__ + 1; \
1771 for (p = beg; *p ; p++) ; \
1776 /* The TI tooling uses atexit. */
1777 #define ON_EXIT(FUNC,ARG) atexit (FUNC)
1779 #undef EXTRA_SECTIONS
1780 #define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
1782 #undef EXTRA_SECTION_FUNCTIONS
1783 #define EXTRA_SECTION_FUNCTIONS \
1784 CONST_SECTION_FUNCTION \
1785 INIT_SECTION_FUNCTION \
1786 FINI_SECTION_FUNCTION \
1787 CTORS_SECTION_FUNCTION \
1788 DTORS_SECTION_FUNCTION
1790 #define INIT_SECTION_FUNCTION \
1794 if (in_section != in_init) \
1796 fprintf (asm_out_file, ";\t.init\n"); \
1797 in_section = in_init; \
1801 #define FINI_SECTION_FUNCTION \
1805 if (in_section != in_fini) \
1807 fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \
1808 in_section = in_fini; \
1812 #define READONLY_DATA_SECTION() const_section ()
1814 #define CONST_SECTION_FUNCTION \
1818 extern void text_section(); \
1819 if (!USE_CONST_SECTION) \
1821 else if (in_section != in_const) \
1823 fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
1824 in_section = in_const; \
1828 #define ASM_STABS_OP "\t.stabs"
1830 /* The ctors and dtors sections are not normally put into use
1831 by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
1832 but it can't hurt to define these macros for whatever systems use them. */
1834 #define CTORS_SECTION_FUNCTION \
1838 if (in_section != in_ctors) \
1840 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1841 in_section = in_ctors; \
1845 #define DTORS_SECTION_FUNCTION \
1849 if (in_section != in_dtors) \
1851 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1852 in_section = in_dtors; \
1856 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1857 fprintf (FILE, "\t.sect\t\"%s\"\n", NAME);
1859 /* This is machine-dependent because it needs to push something
1862 /* A C statement (sans semicolon) to output an element in the table of
1863 global constructors. */
1864 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1867 fprintf (FILE, "\t.word\t "); \
1868 assemble_name (FILE, NAME); \
1869 fprintf (FILE, "\n"); \
1872 /* A C statement (sans semicolon) to output an element in the table of
1873 global destructors. */
1874 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1877 fprintf (FILE, "\t.word\t "); \
1878 assemble_name (FILE, NAME); \
1879 fprintf (FILE, "\n"); \
1882 /* A C statement or statements to switch to the appropriate
1883 section for output of DECL. DECL is either a `VAR_DECL' node
1884 or a constant of some sort. RELOC indicates whether forming
1885 the initial value of DECL requires link-time relocations. */
1887 #define SELECT_SECTION(DECL, RELOC) \
1889 if (TREE_CODE (DECL) == STRING_CST) \
1891 if (! flag_writable_strings) \
1896 else if (TREE_CODE (DECL) == VAR_DECL) \
1898 if ((0 && RELOC) /* should be (flag_pic && RELOC) */ \
1899 || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
1900 || !DECL_INITIAL (DECL) \
1901 || (DECL_INITIAL (DECL) != error_mark_node \
1902 && !TREE_CONSTANT (DECL_INITIAL (DECL)))) \
1911 /* A C statement or statements to switch to the appropriate
1912 section for output of RTX in mode MODE. RTX is some kind
1913 of constant in RTL. The argument MODE is redundant except
1914 in the case of a `const_int' rtx. Currently, these always
1915 go into the const section. */
1917 #define SELECT_RTX_SECTION(MODE, RTX) const_section()
1920 /* Overall Framework of an Assembler File */
1922 #define ASM_FILE_START(FILE) \
1924 int dspversion = 0; \
1925 if (TARGET_C30) dspversion = 30; \
1926 if (TARGET_C31) dspversion = 31; \
1927 if (TARGET_C32) dspversion = 32; \
1928 if (TARGET_C40) dspversion = 40; \
1929 if (TARGET_C44) dspversion = 44; \
1930 fprintf (FILE, "\t.version\t%d\n", dspversion); \
1931 fprintf (FILE, "\t.file\t"); \
1935 char *after_dir = main_input_filename; \
1936 for (p = main_input_filename; *p; p++) \
1938 after_dir = p + 1; \
1939 output_quoted_string (FILE, after_dir); \
1942 output_quoted_string (FILE, main_input_filename); \
1943 fprintf (FILE, "\n"); \
1946 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n")
1948 /* We need to have a data section we can identify so that we can set
1949 the DP register back to a data pointer in the small memory model.
1950 This is only required for ISRs if we are paranoid that someone
1951 may have quietly changed this register on the sly. */
1953 #define ASM_IDENTIFY_GCC(FILE) \
1954 if (!TARGET_TI) fputs ("gcc2_compiled.:\n", FILE); \
1955 fputs ("\t.data\ndata_sec:\n", FILE);
1957 #define ASM_COMMENT_START ";"
1959 #define ASM_APP_ON ""
1960 #define ASM_APP_OFF ""
1962 /* Output float/double constants QFmode. */
1964 #define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE) \
1967 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1968 REAL_VALUE_TO_DECIMAL (VALUE, "%20f", str); \
1969 if (sizeof (int) == sizeof (long)) \
1970 fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
1972 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
1975 /* Output long double constants HFmode.
1976 The first word contains the exponent and first part of the mantissa
1977 in the same manner as QFmode. The second word contains the full
1978 mantissa. We should ensure that the two words are allocated within
1979 the same page for the large memory model since we only output a single
1980 LDP instruction. FIXME. The simplest solution probably is to output
1981 a LDP for each load. */
1983 #define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE) \
1986 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1987 REAL_VALUE_TO_DECIMAL (VALUE, "%20f", str); \
1988 l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
1989 if (sizeof (int) == sizeof (long)) \
1990 fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
1993 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
1997 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1998 { fprintf (FILE, "\t.word\t"); \
1999 output_addr_const (FILE, VALUE); \
2000 if (GET_CODE (VALUE) != SYMBOL_REF) \
2001 fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE)); \
2003 fputc ('\n', FILE); \
2006 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
2007 fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
2009 extern void c4x_output_ascii ();
2010 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
2012 #define ASM_OPEN_PAREN "("
2013 #define ASM_CLOSE_PAREN ")"
2016 /* Output and Generation of Labels */
2018 #define NO_DOT_IN_LABEL /* Only required for TI format */
2020 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2021 { assemble_name (FILE, NAME); fputs (":\n", FILE); }
2023 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
2025 fprintf (FILE, "\t.global\t"); \
2026 assemble_name (FILE, NAME); \
2027 fputs ("\n", FILE); \
2030 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2032 fprintf (FILE, "\t.ref\t"); \
2033 assemble_name (FILE, NAME); \
2034 fputc ('\n', FILE); \
2037 /* A C statement to output on FILE an assembler pseudo-op to
2038 declare a library function named external.
2039 (Only needed to keep asm30 happy for ___divqf3 etc.) */
2041 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
2043 fprintf (FILE, "\t.ref\t"); \
2044 assemble_name (FILE, XSTR (FUN, 0)); \
2045 fprintf (FILE, "\n"); \
2048 /* The prefix to add to user-visible assembler symbols. */
2050 #define USER_LABEL_PREFIX "_"
2052 /* This is how to output an internal numbered label where
2053 PREFIX is the class of label and NUM is the number within the class. */
2055 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
2056 asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2058 /* This is how to store into the string LABEL
2059 the symbol_ref name of an internal numbered label where
2060 PREFIX is the class of label and NUM is the number within the class.
2061 This is suitable for output with `assemble_name'. */
2063 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
2064 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
2066 /* Store in OUTPUT a string (made with alloca) containing
2067 an assembler-name for a local static variable named NAME.
2068 LABELNO is an integer which is different for each call. */
2070 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2071 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2072 sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO)))
2075 /* Output of Dispatch Tables */
2077 /* This is how to output an element of a case-vector that is absolute. */
2079 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2080 fprintf (FILE, "\t.long\tL%d\n", VALUE);
2082 /* This is how to output an element of a case-vector that is relative. */
2084 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2085 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
2088 #define SIZE_TYPE "unsigned int"
2091 #define PTRDIFF_TYPE "int"
2094 #define WCHAR_TYPE "long int"
2096 #undef WCHAR_TYPE_SIZE
2097 #define WCHAR_TYPE_SIZE 32
2099 #define INT_TYPE_SIZE 32
2100 #define LONG_LONG_TYPE_SIZE 64
2101 #define FLOAT_TYPE_SIZE 32
2102 #define DOUBLE_TYPE_SIZE 32
2103 #define LONG_DOUBLE_TYPE_SIZE 64 /* actually only 40 */
2105 /* Allow #sccs in preprocessor. */
2107 #define SCCS_DIRECTIVE
2109 /* Output #ident as a .ident. */
2111 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2112 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
2114 #define CPP_PREDEFINES ""
2116 /* This says how to output an assembler line
2117 to define a local common symbol. */
2119 #undef ASM_OUTPUT_LOCAL
2120 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2121 ( fputs ("\t.bss\t", FILE), \
2122 assemble_name (FILE, (NAME)), \
2123 fprintf (FILE, ",%u\n", (ROUNDED)))
2125 /* Output of Uninitialized Variables */
2127 #undef ASM_OUTPUT_COMMON
2128 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2129 ( fputs ("\t.globl\t", FILE), \
2130 assemble_name (FILE, (NAME)), \
2131 fputs ("\n\t.bss\t", FILE), \
2132 assemble_name (FILE, (NAME)), \
2133 fprintf (FILE, ",%u\n", (ROUNDED)))
2135 /* Macros Controlling Initialization Routines */
2137 #define OBJECT_FORMAT_COFF
2138 #define REAL_NM_FILE_NAME "c4x-nm"
2140 /* Output of Assembler Instructions */
2142 /* Register names when used for integer modes. */
2144 #define REGISTER_NAMES \
2146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2147 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2148 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2149 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
2152 /* Alternate register names when used for floating point modes. */
2154 #define FLOAT_REGISTER_NAMES \
2156 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2157 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2158 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2159 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
2163 extern void c4x_print_operand ();
2164 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
2166 /* Determine which codes are valid without a following integer. These must
2167 not be alphabetic. */
2169 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
2171 extern void c4x_print_operand_address ();
2172 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
2174 /* Define this macro if you want to implement any pragmas. If defined, it
2175 should be a C expression to be executed when #pragma is seen. The
2176 argument STREAM is the stdio input stream from which the source
2177 text can be read. CH is the first character after the #pragma. The
2178 result of the expression is the terminating character found
2179 (newline or EOF). */
2180 extern int c4x_handle_pragma ();
2181 #define HANDLE_PRAGMA(GETC, UNGETC, NAME) \
2182 c4x_handle_pragma (GETC, UNGETC, NAME)
2184 extern void c4x_set_default_attributes ();
2185 #define SET_DEFAULT_DECL_ATTRIBUTES(DECL, ATTRIBUTES) \
2186 c4x_set_default_attributes (DECL, &ATTRIBUTES)
2188 extern int c4x_valid_type_attribute_p ();
2189 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2190 (c4x_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2192 /* Assembler Commands for Alignment */
2194 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
2196 for (; c > 0; --c) \
2197 fprintf (FILE,"\t.word\t0\n"); \
2200 #define ASM_NO_SKIP_IN_TEXT 1
2202 /* I'm not sure about this one. FIXME. */
2204 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
2206 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
2209 /* Macros for SDB and DWARF Output (use .sdef instead of .def
2210 to avoid conflict with TI's use of .def) */
2212 #define SDB_DELIM "\n"
2213 #define SDB_DEBUGGING_INFO
2215 #define PUT_SDB_DEF(A) \
2216 do { fprintf (asm_out_file, "\t.sdef\t"); \
2217 ASM_OUTPUT_LABELREF (asm_out_file, A); \
2218 fprintf (asm_out_file, SDB_DELIM); } while (0)
2220 #define PUT_SDB_PLAIN_DEF(A) \
2221 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
2223 #define PUT_SDB_BLOCK_START(LINE) \
2224 fprintf (asm_out_file, \
2225 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2226 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2228 #define PUT_SDB_BLOCK_END(LINE) \
2229 fprintf (asm_out_file, \
2230 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2231 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2233 #define PUT_SDB_FUNCTION_START(LINE) \
2234 fprintf (asm_out_file, \
2235 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2236 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2238 #define PUT_SDB_FUNCTION_END(LINE) \
2239 fprintf (asm_out_file, \
2240 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2241 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2243 #define PUT_SDB_EPILOGUE_END(NAME) \
2244 do { fprintf (asm_out_file, "\t.sdef\t"); \
2245 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
2246 fprintf (asm_out_file, \
2247 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
2248 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
2251 /* Define results of standard character escape sequences. */
2253 #define TARGET_BELL 007
2254 #define TARGET_BS 010
2255 #define TARGET_TAB 011
2256 #define TARGET_NEWLINE 012
2257 #define TARGET_VT 013
2258 #define TARGET_FF 014
2259 #define TARGET_CR 015
2261 /* This is the kind of divide that is easiest to do in the general case. */
2263 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2265 /* Define this as 1 if `char' should by default be signed; else as 0. */
2267 #define DEFAULT_SIGNED_CHAR 1
2269 /* A function address in a call instruction is a byte address (for
2270 indexing purposes) so give the MEM rtx a byte's mode. */
2272 #define FUNCTION_MODE QImode
2274 #define SLOW_BYTE_ACCESS 0
2276 /* Specify the machine mode that pointers have. After generation of
2277 RTL, the compiler makes no further distinction between pointers and
2278 any other objects of this machine mode. */
2280 #define Pmode QImode
2282 /* On the C4x we can write the following code. We have to clear the cache
2283 every time we execute it because the data in the stack could change.
2296 On the c3x this is a bit more difficult. We have to write self
2297 modifying code here. So we have to clear the cache every time
2298 we execute it because the data in the stack could change.
2300 ldiu TOP_OF_FUNCTION,ar1
2302 or BOTTOM_OF_FUNCTION,ar1
2303 ldiu TOP_OF_STATIC,ar0
2306 or BOTTOM_OF_STATIC,ar0
2311 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
2313 #define TRAMPOLINE_TEMPLATE(FILE) \
2317 asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
2318 asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
2319 asm_fprintf (FILE, "\tor\t0,ar1\n"); \
2320 asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
2321 asm_fprintf (FILE, "\tbud\tar1\n"); \
2322 asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
2323 asm_fprintf (FILE, "\tor\t0,ar0\n"); \
2324 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2328 asm_fprintf (FILE, "\tlaj\t$+4\n"); \
2329 asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2330 asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2331 asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2332 asm_fprintf (FILE, "\tbud\tar1\n"); \
2333 asm_fprintf (FILE, "\tnop\n"); \
2334 asm_fprintf (FILE, "\tnop\n"); \
2335 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2336 asm_fprintf (FILE, "\t.word\t0\n"); \
2337 asm_fprintf (FILE, "\t.word\t0\n"); \
2341 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2346 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2347 size_int (16), 0, 1); \
2348 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2349 gen_rtx (CONST_INT, VOIDmode, 0x5069), \
2350 size_int (16), 0, 1); \
2351 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2352 emit_move_insn (gen_rtx (MEM, QImode, \
2353 plus_constant (tramp, 0)), tmp1); \
2354 tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
2356 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2357 gen_rtx (CONST_INT, VOIDmode, 0x1069), \
2358 size_int (16), 0, 1); \
2359 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2360 emit_move_insn (gen_rtx (MEM, QImode, \
2361 plus_constant (tramp, 2)), tmp1); \
2362 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2363 size_int (16), 0, 1); \
2364 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2365 gen_rtx (CONST_INT, VOIDmode, 0x5068), \
2366 size_int (16), 0, 1); \
2367 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2368 emit_move_insn (gen_rtx (MEM, QImode, \
2369 plus_constant (tramp, 3)), tmp1); \
2370 tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
2372 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2373 gen_rtx (CONST_INT, VOIDmode, 0x1068), \
2374 size_int (16), 0, 1); \
2375 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2376 emit_move_insn (gen_rtx (MEM, QImode, \
2377 plus_constant (tramp, 6)), tmp1); \
2381 emit_move_insn (gen_rtx (MEM, QImode, \
2382 plus_constant (TRAMP, 8)), FNADDR); \
2383 emit_move_insn (gen_rtx (MEM, QImode, \
2384 plus_constant (TRAMP, 9)), CXT); \
2388 /* Specify the machine mode that this machine uses for the index in
2389 the tablejump instruction. */
2391 #define CASE_VECTOR_MODE Pmode
2393 /* Max number of (32-bit) bytes we can move from memory to memory
2394 in one reasonably fast instruction. */
2398 /* MOVE_RATIO is the number of move instructions that is better than a
2401 #define MOVE_RATIO 2 /* Default value */
2403 #define BSS_SECTION_ASM_OP ".bss"
2405 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2406 asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2408 /* This is how to output an insn to pop a register from the stack.
2409 It need not be very fast code. */
2411 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2412 asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2414 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2415 is done just by pretending it is already truncated. */
2417 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2419 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2421 /* We need to use direct addressing for large constants and addresses
2422 that cannot fit within an instruction. We must check for these
2423 after after the final jump optimisation pass, since this may
2424 introduce a local_move insn for a SYMBOL_REF. This pass
2425 must come before delayed branch slot filling since it can generate
2426 additional instructions. */
2428 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2430 #define MACHINE_DEPENDENT_COMBINE(INSNS) c4x_combine_parallel(INSNS)
2432 #define DBR_OUTPUT_SEQEND(FILE) \
2433 if (final_sequence != NULL_RTX) \
2436 int laj = GET_CODE (XEXP (XEXP (final_sequence, 0), 0)) == CALL_INSN; \
2438 count = dbr_sequence_length(); \
2439 while (count < (laj ? 2 : 3)) \
2441 fputs("\tnop\n", FILE); \
2445 fputs("\tpush\tr11\n", FILE); \
2448 #define NO_FUNCTION_CSE
2450 /* Repeat block stuff (hook into strength_reduce() in loop.c). */
2452 extern void c4x_rptb_process ();
2453 #define REPEAT_BLOCK_PROCESS(START, END) c4x_rptb_process(START, END)
2455 /* We don't want a leading tab. */
2457 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2459 /* Define the codes that are matched by predicates in c4x.c. */
2461 #define PREDICATE_CODES \
2462 {"fp_zero_operand", {CONST_DOUBLE}}, \
2463 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2464 {"stik_const_operand", {CONST_INT}}, \
2465 {"not_const_operand", {CONST_INT}}, \
2466 {"reg_operand", {REG, SUBREG}}, \
2467 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2468 {"r0r1_reg_operand", {REG, SUBREG}}, \
2469 {"r2r3_reg_operand", {REG, SUBREG}}, \
2470 {"ext_low_reg_operand", {REG, SUBREG}}, \
2471 {"ext_reg_operand", {REG, SUBREG}}, \
2472 {"std_reg_operand", {REG, SUBREG}}, \
2473 {"addr_reg_operand", {REG, SUBREG}}, \
2474 {"index_reg_operand", {REG, SUBREG}}, \
2475 {"dp_reg_operand", {REG}}, \
2476 {"sp_reg_operand", {REG}}, \
2477 {"st_reg_operand", {REG}}, \
2478 {"call_operand", {REG, SYMBOL_REF}}, \
2479 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2480 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2481 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2482 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2483 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2484 {"par_ind_operand", {MEM}}, \
2485 {"parallel_operand", {SUBREG, REG, MEM}}, \
2486 {"mem_operand", {MEM}}, \
2489 /* Variables in c4x.c */
2491 extern enum reg_class c4x_regclass_map[];/* smallest class containing REGNO */
2492 extern enum machine_mode c4x_caller_save_map[];
2494 extern struct rtx_def *c4x_compare_op0; /* operand 0 for comparisons */
2495 extern struct rtx_def *c4x_compare_op1; /* operand 1 for comparisons */
2497 extern int c4x_rpts_cycles; /* max cycles for RPTS */
2498 extern int c4x_cpu_version; /* cpu version C30/31/32/40/44 */
2500 /* Functions in c4x.c */
2502 extern void c4x_function_prologue ();
2504 extern void c4x_function_epilogue ();
2506 extern struct rtx_def *c4x_operand_subword ();
2508 extern struct rtx_def *c4x_adj_offsettable_operand ();
2510 extern char *c4x_output_cbranch ();
2512 extern int c4x_null_epilogue_p ();
2514 extern int c4x_autoinc_operand ();
2516 extern int c4x_label_conflict ();
2518 extern int c4x_address_conflict ();
2520 extern int c4x_adjust_cost ();
2522 extern void c4x_process_after_reload ();
2524 extern void c4x_combine_parallel ();
2526 extern int c4x_rptb_nop_p ();
2528 extern int c4x_rptb_rpts_p ();
2530 extern int fp_zero_operand ();
2532 extern int const_operand ();
2534 extern int stik_const_operand ();
2536 extern int not_const_operand ();
2538 extern int reg_operand ();
2540 extern int reg_imm_operand ();
2542 extern int r0r1_reg_operand ();
2544 extern int r2r3_reg_operand ();
2546 extern int ext_low_reg_operand ();
2548 extern int ext_reg_operand ();
2550 extern int std_reg_operand ();
2552 extern int src_operand ();
2554 extern int lsrc_operand ();
2556 extern int tsrc_operand ();
2558 extern int addr_reg_operand ();
2560 extern int index_reg_operand ();
2562 extern int dp_reg_operand ();
2564 extern int sp_reg_operand ();
2566 extern int st_reg_operand ();
2568 extern int call_operand ();
2570 extern int par_ind_operand ();
2572 extern int c4x_H_constant ();
2574 extern int c4x_I_constant ();
2576 extern int c4x_J_constant ();
2578 extern int c4x_L_constant ();
2580 extern int c4x_Q_constraint ();
2582 extern int c4x_R_constraint ();
2584 extern int c4x_S_constraint ();
2586 extern int c4x_T_constraint ();
2588 extern void c4x_emit_libcall ();
2590 extern void c4x_emit_libcall3 ();
2592 extern void c4x_emit_libcall_mulhi ();
2594 extern int c4x_group1_reg_operand ();
2596 extern int c4x_group1_mem_operand ();
2598 extern int c4x_arx_reg_operand ();
2600 extern int legitimize_operands ();
2602 extern int valid_operands ();
2604 extern int valid_parallel_operands_4 ();
2606 extern int valid_parallel_operands_5 ();
2608 extern int valid_parallel_operands_6 ();
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