1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 /* RUN-TIME TARGET SPECIFICATION. */
31 /* Name of the c4x assembler. */
33 #define ASM_PROG "c4x-as"
35 /* Name of the c4x linker. */
37 #define LD_PROG "c4x-ld"
39 /* Define assembler options. */
42 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
43 %{!m30:%{!m40:-m40}}}}}}}} \
56 %{mmemparm:-p} %{mregparm:-r} \
57 %{!mmemparm:%{!mregparm:-r}} \
58 %{mbig:-b} %{msmall:-s} \
59 %{!msmall:%{!mbig:-b}}"
61 /* Define linker options. */
64 %{m30:--architecture c3x} \
65 %{m31:--architecture c3x} \
66 %{m32:--architecture c3x} \
67 %{m33:--architecture c3x} \
68 %{mcpu=30:--architecture c3x} \
69 %{mcpu=31:--architecture c3x} \
70 %{mcpu=32:--architecture c3x} \
71 %{mcpu=33:--architecture c3x}"
73 /* Define C preprocessor options. */
76 %{!m30:%{!m31:%{!m32:%{!m33:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:\
77 %{!mcpu=40:%{!mcpu=44:%{\
78 !m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40}}}}}}}}}}}} \
79 %{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
80 %{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
81 %{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
82 %{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
83 %{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
84 %{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
85 %{mcpu=33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
86 %{m33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
87 %{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
88 %{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
89 %{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
90 %{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
91 %{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
92 %{!mmemparm:%{!mregparm:-D_REGPARM }} \
93 %{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
94 %{!msmall:%{!mbig:-D_BIGMODEL }} \
95 %{finline-functions:-D_INLINE }"
97 /* Specify the end file to link with. */
99 #define ENDFILE_SPEC ""
101 /* Target compilation option flags. */
103 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
104 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
105 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
106 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
107 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
108 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
109 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
110 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
111 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
112 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
113 #define BK_FLAG 0x0000400 /* Use BK as general register. */
114 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
115 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
116 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
117 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
118 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
119 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
120 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
121 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
122 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
124 #define C30_FLAG 0x0100000 /* Emit C30 code. */
125 #define C31_FLAG 0x0200000 /* Emit C31 code. */
126 #define C32_FLAG 0x0400000 /* Emit C32 code. */
127 #define C33_FLAG 0x0400000 /* Emit C33 code. */
128 #define C40_FLAG 0x1000000 /* Emit C40 code. */
129 #define C44_FLAG 0x2000000 /* Emit C44 code. */
131 /* Run-time compilation parameters selecting different hardware subsets.
133 Macro to define tables used to set the flags.
134 This is a list in braces of triplets in braces,
135 each pair being { "NAME", VALUE, "DESCRIPTION" }
136 where VALUE is the bits to set or minus the bits to clear.
137 An empty string NAME is used to identify the default VALUE. */
139 #define TARGET_SWITCHES \
140 { { "small", SMALL_MEMORY_FLAG, \
141 N_("Small memory model") }, \
142 { "big", -SMALL_MEMORY_FLAG, \
143 N_("Big memory model") }, \
144 { "mpyi", MPYI_FLAG, \
145 N_("Use MPYI instruction for C3x") }, \
146 { "no-mpyi", -MPYI_FLAG, \
147 N_("Do not use MPYI instruction for C3x") }, \
148 { "fast-fix", FAST_FIX_FLAG, \
149 N_("Use fast but approximate float to integer conversion") }, \
150 { "no-fast-fix", -FAST_FIX_FLAG, \
151 N_("Use slow but accurate float to integer conversion") }, \
152 { "rpts", RPTS_FLAG, \
153 N_("Enable use of RTPS instruction") }, \
154 { "no-rpts", -RPTS_FLAG, \
155 N_("Disable use of RTPS instruction") }, \
156 { "rptb", RPTB_FLAG, \
157 N_("Enable use of RTPB instruction") }, \
158 { "no-rptb", -RPTB_FLAG, \
159 N_("Disable use of RTPB instruction") }, \
161 N_("Generate code for C30 CPU")}, \
163 N_("Generate code for C31 CPU")}, \
165 N_("Generate code for C32 CPU")}, \
167 N_("Generate code for C33 CPU")}, \
169 N_("Generate code for C40 CPU")}, \
171 N_("Generate code for C44 CPU")}, \
173 N_("Emit code compatible with TI tools")}, \
174 { "no-ti", -TI_FLAG, \
175 N_("Emit code to use GAS extensions")}, \
176 { "paranoid", PARANOID_FLAG, \
177 N_("Save DP across ISR in small memory model") }, \
178 { "no-paranoid", -PARANOID_FLAG, \
179 N_("Don't save DP across ISR in small memory model") }, \
180 { "isr-dp-reload", PARANOID_FLAG, \
181 N_("Save DP across ISR in small memory model") }, \
182 { "no-isr-dp-reload", -PARANOID_FLAG, \
183 N_("Don't save DP across ISR in small memory model") }, \
184 { "memparm", MEMPARM_FLAG, \
185 N_("Pass arguments on the stack") }, \
186 { "regparm", -MEMPARM_FLAG, \
187 N_("Pass arguments in registers") }, \
188 { "devel", DEVEL_FLAG, \
189 N_("Enable new features under development") }, \
190 { "no-devel", -DEVEL_FLAG, \
191 N_("Disable new features under development") }, \
193 N_("Use the BK register as a general purpose register") }, \
194 { "no-bk", -BK_FLAG, \
195 N_("Do not allocate BK register") }, \
197 N_("Enable use of DB instruction") }, \
198 { "no-db", -DB_FLAG, \
199 N_("Disable use of DB instruction") }, \
200 { "debug", DEBUG_FLAG, \
201 N_("Enable debugging") }, \
202 { "no-debug", -DEBUG_FLAG, \
203 N_("Disable debugging") }, \
204 { "hoist", HOIST_FLAG, \
205 N_("Force constants into registers to improve hoisting") }, \
206 { "no-hoist", -HOIST_FLAG, \
207 N_("Don't force constants into registers") }, \
208 { "force", FORCE_FLAG, \
209 N_("Force RTL generation to emit valid 3 operand insns") }, \
210 { "no-force", -FORCE_FLAG, \
211 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
212 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
213 N_("Allow unsigned interation counts for RPTB/DB") }, \
214 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
215 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
216 { "preserve-float", PRESERVE_FLOAT_FLAG, \
217 N_("Preserve all 40 bits of FP reg across call") }, \
218 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
219 N_("Only preserve 32 bits of FP reg across call") }, \
220 { "parallel-insns", PARALLEL_INSN_FLAG, \
221 N_("Enable parallel instructions") }, \
222 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
223 N_("Disable parallel instructions") }, \
224 { "parallel-mpy", PARALLEL_MPY_FLAG, \
225 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
226 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
227 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
228 { "aliases", ALIASES_FLAG, \
229 N_("Assume that pointers may be aliased") }, \
230 { "no-aliases", -ALIASES_FLAG, \
231 N_("Assume that pointers not aliased") }, \
232 { "", TARGET_DEFAULT, ""} }
234 /* Default target switches. */
236 /* Play safe, not the fastest code. */
237 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
238 | PARALLEL_MPY_FLAG | RPTB_FLAG
241 Max iteration count for RPTB/RPTS is 2^31 + 1.
242 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
243 RPTS blocks interrupts. */
246 extern int target_flags;
248 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
249 #define TARGET_SMALL_REG_CLASS 0
251 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
252 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
253 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
254 #define TARGET_RPTS (target_flags & RPTS_FLAG)
255 #define TARGET_TI (target_flags & TI_FLAG)
256 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
257 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
258 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
259 #define TARGET_RPTB (target_flags & RPTB_FLAG \
261 #define TARGET_BK (target_flags & BK_FLAG)
262 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
263 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
264 #define TARGET_HOIST (target_flags & HOIST_FLAG)
265 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
266 #define TARGET_FORCE (target_flags & FORCE_FLAG)
267 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
268 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
270 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
271 && (target_flags & PARALLEL_MPY_FLAG))
272 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
274 #define TARGET_C3X (target_flags & C3X_FLAG)
275 #define TARGET_C30 (target_flags & C30_FLAG)
276 #define TARGET_C31 (target_flags & C31_FLAG)
277 #define TARGET_C32 (target_flags & C32_FLAG)
278 #define TARGET_C33 (target_flags & C33_FLAG)
279 #define TARGET_C40 (target_flags & C40_FLAG)
280 #define TARGET_C44 (target_flags & C44_FLAG)
282 /* Define some options to control code generation. */
283 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
284 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
285 during RTL generation. */
286 #define TARGET_EXPOSE_LDP 0
287 /* Nonzero to force loading of direct memory references into a register. */
288 #define TARGET_LOAD_DIRECT_MEMS 0
290 /* -mrpts allows the use of the RPTS instruction irregardless.
291 -mrpts=max-cycles will use RPTS if the number of cycles is constant
292 and less than max-cycles. */
294 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
296 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
298 /* -mcpu=XX with XX = target DSP version number. */
300 /* This macro is similar to `TARGET_SWITCHES' but defines names of
301 command options that have values. Its definition is an
302 initializer with a subgrouping for each command option.
304 Each subgrouping contains a string constant, that defines the
305 fixed part of the option name, and the address of a variable.
306 The variable, type `char *', is set to the variable part of the
307 given option if the fixed part matches. The actual option name
308 is made by appending `-m' to the specified name.
310 Here is an example which defines `-mshort-data-NUMBER'. If the
311 given option is `-mshort-data-512', the variable `m88k_short_data'
312 will be set to the string `"512"'.
314 extern char *m88k_short_data;
315 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
317 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
319 #define TARGET_OPTIONS \
320 { {"rpts=", &c4x_rpts_cycles_string, \
321 N_("Specify maximum number of iterations for RPTS") }, \
322 {"cpu=", &c4x_cpu_version_string, \
323 N_("Select CPU to generate code for") } }
325 /* Sometimes certain combinations of command options do not make sense
326 on a particular target machine. You can define a macro
327 `OVERRIDE_OPTIONS' to take account of this. This macro, if
328 defined, is executed once just after all the command options have
331 #define OVERRIDE_OPTIONS c4x_override_options ()
333 /* Define this to change the optimizations performed by default. */
335 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
337 /* Run Time Target Specification. */
339 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
341 /* Storage Layout. */
343 #define BITS_BIG_ENDIAN 0
344 #define BYTES_BIG_ENDIAN 0
345 #define WORDS_BIG_ENDIAN 0
347 /* Technically, we are little endian, but we put the floats out as
348 whole longs and this makes GCC put them out in the right order. */
350 #define FLOAT_WORDS_BIG_ENDIAN 1
352 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
353 all integral and floating point data types are stored in memory as
354 32-bits (floating point types can be stored as 40-bits in the
355 extended precision registers), so sizeof(char) = sizeof(short) =
356 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
358 #define BITS_PER_UNIT 32
359 #define BITS_PER_WORD 32
360 #define UNITS_PER_WORD 1
361 #define POINTER_SIZE 32
362 #define PARM_BOUNDARY 32
363 #define STACK_BOUNDARY 32
364 #define FUNCTION_BOUNDARY 32
365 #define BIGGEST_ALIGNMENT 32
366 #define EMPTY_FIELD_BOUNDARY 32
367 #define STRICT_ALIGNMENT 0
368 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
369 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
371 /* If a structure has a floating point field then force structure
373 #define MEMBER_TYPE_FORCES_BLK(FIELD) \
374 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE)
376 /* Number of bits in the high and low parts of a two stage
377 load of an immediate constant. */
378 #define BITS_PER_HIGH 16
379 #define BITS_PER_LO_SUM 16
381 /* Use the internal floating point stuff in the compiler and not the
382 host floating point stuff. */
384 #define REAL_ARITHMETIC
386 /* Define register numbers. */
388 /* Extended-precision registers. */
399 /* Auxiliary (address) registers. */
410 /* Data page register. */
414 /* Index registers. */
419 /* Block size register. */
427 /* Status register. */
431 /* Misc. interrupt registers. */
433 #define DIE_REGNO 22 /* C4x only. */
434 #define IE_REGNO 22 /* C3x only. */
435 #define IIE_REGNO 23 /* C4x only. */
436 #define IF_REGNO 23 /* C3x only. */
437 #define IIF_REGNO 24 /* C4x only. */
438 #define IOF_REGNO 24 /* C3x only. */
440 /* Repeat block registers. */
446 /* Additional extended-precision registers. */
448 #define R8_REGNO 28 /* C4x only. */
449 #define R9_REGNO 29 /* C4x only. */
450 #define R10_REGNO 30 /* C4x only. */
451 #define R11_REGNO 31 /* C4x only. */
453 #define FIRST_PSEUDO_REGISTER 32
455 /* Extended precision registers (low set). */
457 #define IS_R0R1_REGNO(r) \
458 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
459 #define IS_R2R3_REGNO(r) \
460 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
461 #define IS_EXT_LOW_REGNO(r) \
462 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
464 /* Extended precision registers (high set). */
466 #define IS_EXT_HIGH_REGNO(r) \
468 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
470 /* Address registers. */
472 #define IS_AUX_REGNO(r) \
473 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
474 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
475 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
476 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
477 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
478 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
480 /* Misc registers. */
482 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
483 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
484 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
486 /* Composite register sets. */
488 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
489 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
490 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
491 || IS_REPEAT_REGNO(r) \
494 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
495 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
496 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
497 || ((r) == R8_REGNO))
498 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
500 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
501 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
502 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
503 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
504 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
505 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
506 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
509 || IS_PSEUDO_REGNO(r))
510 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
511 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
512 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
513 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
515 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
516 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
517 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
518 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
519 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
520 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
521 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
523 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
524 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
525 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
526 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
527 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
528 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
530 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
531 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
532 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
533 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
534 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
535 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
537 /* 1 for registers that have pervasive standard uses
538 and are not available for the register allocator. */
540 #define FIXED_REGISTERS \
542 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
544 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
545 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
548 /* 1 for registers not available across function calls.
549 These must include the FIXED_REGISTERS and also any
550 registers that can be used without being saved.
551 The latter must include the registers where values are returned
552 and the register where structure-value addresses are passed.
553 Aside from that, you can include as many other registers as you like.
555 Note that the extended precision registers are only saved in some
556 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
557 get clobbered for a given regno. */
559 #define CALL_USED_REGISTERS \
561 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
562 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
563 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
567 /* Macro to conditionally modify fixed_regs/call_used_regs. */
569 #define CONDITIONAL_REGISTER_USAGE \
573 fixed_regs[BK_REGNO] = 1; \
574 call_used_regs[BK_REGNO] = 1; \
575 c4x_regclass_map[BK_REGNO] = NO_REGS; \
581 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
582 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
583 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
585 for (i = R8_REGNO; i <= R11_REGNO; i++) \
587 fixed_regs[i] = call_used_regs[i] = 1; \
588 c4x_regclass_map[i] = NO_REGS; \
591 if (TARGET_PRESERVE_FLOAT) \
593 c4x_caller_save_map[R6_REGNO] = HFmode; \
594 c4x_caller_save_map[R7_REGNO] = HFmode; \
598 /* Order of Allocation of Registers. */
600 /* List the order in which to allocate registers. Each register must be
601 listed once, even those in FIXED_REGISTERS.
603 First allocate registers that don't need preservation across calls,
604 except index and address registers. Then allocate data registers
605 that require preservation across calls (even though this invokes an
606 extra overhead of having to save/restore these registers). Next
607 allocate the address and index registers, since using these
608 registers for arithmetic can cause pipeline stalls. Finally
609 allocated the fixed registers which won't be allocated anyhow. */
611 #define REG_ALLOC_ORDER \
612 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
613 R9_REGNO, R10_REGNO, R11_REGNO, \
614 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
615 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
616 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
617 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
618 IR0_REGNO, IR1_REGNO, \
619 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
621 /* A C expression that is nonzero if hard register number REGNO2 can be
622 considered for use as a rename register for REGNO1 */
624 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
625 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
627 /* Determine which register classes are very likely used by spill registers.
628 local-alloc.c won't allocate pseudos that have these classes as their
629 preferred class unless they are "preferred or nothing". */
631 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
633 /* CCmode is wrongly defined in machmode.def. It should have a size
634 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
635 extended precision register. Similarly, HCmode fits within two
636 extended precision registers. */
638 #define HARD_REGNO_NREGS(REGNO, MODE) \
639 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
640 ((MODE) == HFmode) ? 1 : \
641 ((MODE) == HCmode) ? 2 : \
642 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
645 /* A C expression that is nonzero if the hard register REGNO is preserved
646 across a call in mode MODE. This does not have to include the call used
649 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
650 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
651 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
652 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
654 /* Specify the modes required to caller save a given hard regno. */
656 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
658 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
660 /* A C expression that is nonzero if it is desirable to choose
661 register allocation so as to avoid move instructions between a
662 value of mode MODE1 and a value of mode MODE2.
664 Value is 1 if it is a good idea to tie two pseudo registers
665 when one has mode MODE1 and one has mode MODE2.
666 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
667 for any hard reg, then this must be 0 for correct output. */
669 #define MODES_TIEABLE_P(MODE1, MODE2) 0
672 /* Define the classes of registers for register constraints in the
673 machine description. Also define ranges of constants.
675 One of the classes must always be named ALL_REGS and include all hard regs.
676 If there is more than one class, another class must be named NO_REGS
677 and contain no registers.
679 The name GENERAL_REGS must be the name of a class (or an alias for
680 another name such as ALL_REGS). This is the class of registers
681 that is allowed by "g" or "r" in a register constraint.
682 Also, registers outside this class are allocated only when
683 instructions express preferences for them.
685 The classes must be numbered in nondecreasing order; that is,
686 a larger-numbered class must never be contained completely
687 in a smaller-numbered class.
689 For any two classes, it is very desirable that there be another
690 class that represents their union. */
695 R0R1_REGS, /* 't'. */
696 R2R3_REGS, /* 'u'. */
697 EXT_LOW_REGS, /* 'q'. */
699 ADDR_REGS, /* 'a'. */
700 INDEX_REGS, /* 'x'. */
706 GENERAL_REGS, /* 'r'. */
713 #define N_REG_CLASSES (int) LIM_REG_CLASSES
715 #define REG_CLASS_NAMES \
735 /* Define which registers fit in which classes.
736 This is an initializer for a vector of HARD_REG_SET
737 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
738 since the register allocator will often choose a general register
739 in preference to RC for the decrement_and_branch_on_count pattern. */
741 #define REG_CLASS_CONTENTS \
743 {0x00000000}, /* No registers. */ \
744 {0x00000003}, /* 't' R0-R1 . */ \
745 {0x0000000c}, /* 'u' R2-R3 . */ \
746 {0x000000ff}, /* 'q' R0-R7 . */ \
747 {0xf00000ff}, /* 'f' R0-R11 */ \
748 {0x0000ff00}, /* 'a' AR0-AR7. */ \
749 {0x00060000}, /* 'x' IR0-IR1. */ \
750 {0x00080000}, /* 'k' BK. */ \
751 {0x00100000}, /* 'b' SP. */ \
752 {0x08000000}, /* 'v' RC. */ \
753 {0x0800ff00}, /* RC,AR0-AR7. */ \
754 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
755 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
756 {0x00010000}, /* 'z' DP. */ \
757 {0x00200000}, /* 'y' ST. */ \
758 {0xffffffff}, /* All registers. */ \
761 /* The same information, inverted:
762 Return the class number of the smallest class containing
763 reg number REGNO. This could be a conditional expression
764 or could index an array. */
766 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
768 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
769 explicitly used in the rtl is kept as short as possible.
771 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
772 is defined since the MPY|ADD insns require the classes R0R1_REGS and
773 R2R3_REGS which are used by the function return registers (R0,R1) and
774 the register arguments (R2,R3), respectively. I'm reluctant to define
775 this macro since it stomps on many potential optimisations. Ideally
776 it should have a register class argument so that not all the register
777 classes gets penalised for the sake of a naughty few... For long
778 double arithmetic we need two additional registers that we can use as
781 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
783 #define BASE_REG_CLASS ADDR_REGS
784 #define INDEX_REG_CLASS INDEX_REGS
787 Register constraints for the C4x
789 a - address reg (ar0-ar7)
791 c - other gp int-only reg
792 d - data/int reg (equiv. to f)
794 h - data/long double reg (equiv. to f)
799 v - repeat count (rc)
800 x - index register (ir0-ir1)
801 y - status register (st)
804 Memory/constant constraints for the C4x
806 G - short float 16-bit
807 I - signed 16-bit constant (sign extended)
808 J - signed 8-bit constant (sign extended) (C4x only)
809 K - signed 5-bit constant (sign extended) (C4x only for stik)
810 L - unsigned 16-bit constant
811 M - unsigned 8-bit constant (C4x only)
812 N - ones complement of unsigned 16-bit constant
813 Q - indirect arx + 9-bit signed displacement
814 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
815 R - indirect arx + 5-bit unsigned displacement (C4x only)
816 S - indirect arx + 0, 1, or irn displacement
817 T - direct symbol ref
818 > - indirect with autoincrement
819 < - indirect with autodecrement
820 } - indirect with post-modify
821 { - indirect with pre-modify
824 #define REG_CLASS_FROM_LETTER(CC) \
825 ( ((CC) == 'a') ? ADDR_REGS \
826 : ((CC) == 'b') ? SP_REG \
827 : ((CC) == 'c') ? INT_REGS \
828 : ((CC) == 'd') ? EXT_REGS \
829 : ((CC) == 'f') ? EXT_REGS \
830 : ((CC) == 'h') ? EXT_REGS \
831 : ((CC) == 'k') ? BK_REG \
832 : ((CC) == 'q') ? EXT_LOW_REGS \
833 : ((CC) == 't') ? R0R1_REGS \
834 : ((CC) == 'u') ? R2R3_REGS \
835 : ((CC) == 'v') ? RC_REG \
836 : ((CC) == 'x') ? INDEX_REGS \
837 : ((CC) == 'y') ? ST_REG \
838 : ((CC) == 'z') ? DP_REG \
841 /* These assume that REGNO is a hard or pseudo reg number.
842 They give nonzero only if REGNO is a hard reg of the suitable class
843 or a pseudo reg currently allocated to a suitable hard reg.
844 Since they use reg_renumber, they are safe only once reg_renumber
845 has been allocated, which happens in local-alloc.c. */
847 #define REGNO_OK_FOR_BASE_P(REGNO) \
848 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
850 #define REGNO_OK_FOR_INDEX_P(REGNO) \
851 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
853 /* If we have to generate framepointer + constant prefer an ADDR_REGS
854 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
856 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
857 (GET_CODE (X) == PLUS \
858 && GET_MODE (X) == Pmode \
859 && GET_CODE (XEXP ((X), 0)) == REG \
860 && GET_MODE (XEXP ((X), 0)) == Pmode \
861 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
862 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
863 ? ADDR_REGS : (CLASS))
865 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
867 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
869 #define CLASS_MAX_NREGS(CLASS, MODE) \
870 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
871 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
873 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
875 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
877 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
879 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
881 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
883 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
885 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
887 #define IS_HIGH_CONST(VAL) \
888 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
891 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
893 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
895 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
896 && IS_DISP1_CONST (VAL + 1))
898 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
899 && IS_DISP8_CONST (VAL + 1))
901 #define CONST_OK_FOR_LETTER_P(VAL, C) \
902 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
903 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
904 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
905 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
906 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
907 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
908 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
911 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
912 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
913 : ((C) == 'H') ? (c4x_H_constant (OP)) \
916 #define EXTRA_CONSTRAINT(OP, C) \
917 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
918 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
919 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
920 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
921 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
924 #define SMALL_CONST(VAL, insn) \
925 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
926 ? IS_INT16_CONST (VAL) \
927 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
928 ? IS_NOT_UINT16_CONST (VAL) \
929 : ( (get_attr_data (insn) == DATA_HIGH_16) \
930 ? IS_HIGH_CONST (VAL) \
931 : IS_UINT16_CONST (VAL) \
937 I. Routine calling with arguments in registers
938 ----------------------------------------------
940 The TI C3x compiler has a rather unusual register passing algorithm.
941 Data is passed in the following registers (in order):
943 AR2, R2, R3, RC, RS, RE
945 However, the first and second floating point values are always in R2
946 and R3 (and all other floats are on the stack). Structs are always
947 passed on the stack. If the last argument is an ellipsis, the
948 previous argument is passed on the stack so that its address can be
949 taken for the stdargs macros.
951 Because of this, we have to pre-scan the list of arguments to figure
952 out what goes where in the list.
954 II. Routine calling with arguments on stack
955 -------------------------------------------
957 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
958 variables loc0, loc1, and loc2. After the function prologue has
959 been executed, the stack frame will look like:
961 [stack grows towards increasing addresses]
963 5 I saved reg1 I <= SP points here
973 0 I old FP I <= FP (AR3) points here
984 All local variables (locn) are accessible by means of +FP(n+1)
985 addressing, where n is the local variable number.
987 All stack arguments (argn) are accessible by means of -FP(n-2).
989 The stack pointer (SP) points to the last register saved in the
992 Note that a push instruction performs a preincrement of the stack
993 pointer. (STACK_PUSH_CODE == PRE_INC)
995 III. Registers used in function calling convention
996 --------------------------------------------------
998 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
999 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1002 (Because of this model, we only assign FP values in R6, R7 and
1003 only assign integer values in R4, R5.)
1005 These registers are saved at each function entry and restored at
1006 the exit. Also it is expected any of these not affected by any
1007 call to user-defined (not service) functions.
1009 Not preserved across calls: R0...R3
1010 R4...R5 (upper 8 bits)
1011 R6...R7 (lower 8 bits)
1012 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1014 These registers are used arbitrary in a function without being preserved.
1015 It is also expected that any of these can be clobbered by any call.
1017 Not used by GCC (except for in user "asm" statements):
1018 IE (DIE), IF (IIE), IOF (IIF)
1020 These registers are never used by GCC for any data, but can be used
1021 with "asm" statements. */
1026 /* Basic Stack Layout. */
1028 /* The stack grows upward, stack frame grows upward, and args grow
1031 #define STARTING_FRAME_OFFSET C4X_LOC0
1032 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1033 #define ARGS_GROW_DOWNWARD
1034 #define STACK_POINTER_OFFSET 1
1036 /* Define this if pushing a word on the stack
1037 makes the stack pointer a smaller address. */
1039 /* #define STACK_GROWS_DOWNWARD. */
1040 /* Like the dsp16xx, i370, i960, and we32k ports. */
1042 /* Define this if the nominal address of the stack frame
1043 is at the high-address end of the local variables;
1044 that is, each additional local variable allocated
1045 goes at a more negative offset in the frame. */
1047 /* #define FRAME_GROWS_DOWNWARD. */
1050 /* Registers That Address the Stack Frame. */
1052 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1053 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1054 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1055 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1057 /* Eliminating Frame Pointer and Arg Pointer. */
1059 #define FRAME_POINTER_REQUIRED 0
1061 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1065 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1066 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1067 offset += TARGET_PRESERVE_FLOAT \
1068 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1069 (DEPTH) = -(offset + get_frame_size ()); \
1072 /* This is a hack... We need to specify a register. */
1073 #define ELIMINABLE_REGS \
1074 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1076 #define CAN_ELIMINATE(FROM, TO) \
1077 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1078 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1080 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1084 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1085 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1086 offset += TARGET_PRESERVE_FLOAT \
1087 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1088 (OFFSET) = -(offset + get_frame_size ()); \
1092 /* Passing Function Arguments on the Stack. */
1095 #define PUSH_ROUNDING(BYTES) (BYTES)
1097 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1099 /* The following structure is used by calls.c, function.c, c4x.c. */
1101 typedef struct c4x_args
1114 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1115 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1117 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1118 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1120 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1121 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1123 /* Define the profitability of saving registers around calls.
1124 We disable caller save to avoid a bug in flow.c (this also affects
1125 other targets such as m68k). Since we must use stf/sti,
1126 the profitability is marginal anyway. */
1128 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1130 /* Never pass data by reference. */
1132 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1134 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1136 /* 1 if N is a possible register number for function argument passing. */
1138 #define FUNCTION_ARG_REGNO_P(REGNO) \
1139 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1140 || ((REGNO) == R2_REGNO) /* R2. */ \
1141 || ((REGNO) == R3_REGNO) /* R3. */ \
1142 || ((REGNO) == RC_REGNO) /* RC. */ \
1143 || ((REGNO) == RS_REGNO) /* RS. */ \
1144 || ((REGNO) == RE_REGNO)) /* RE. */ \
1148 /* How Scalar Function Values Are Returned. */
1150 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1151 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1153 #define LIBCALL_VALUE(MODE) \
1154 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1156 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1158 /* How Large Values Are Returned. */
1160 #define DEFAULT_PCC_STRUCT_RETURN 0
1161 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1163 /* Varargs handling. */
1165 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1166 c4x_va_start (stdarg, valist, nextarg)
1168 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1169 c4x_va_arg (valist, type)
1171 /* Generating Code for Profiling. */
1173 /* Note that the generated assembly uses the ^ operator to load the 16
1174 MSBs of the address. This is not supported by the TI assembler.
1175 The FUNCTION profiler needs a function mcount which gets passed
1176 a pointer to the LABELNO. */
1178 #define FUNCTION_PROFILER(FILE, LABELNO) \
1181 fprintf (FILE, "\tpush\tar2\n"); \
1182 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1183 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1184 fprintf (FILE, "\tcall\tmcount\n"); \
1185 fprintf (FILE, "\tpop\tar2\n"); \
1189 fprintf (FILE, "\tpush\tar2\n"); \
1190 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1191 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1192 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1193 fprintf (FILE, "\tcall\tmcount\n"); \
1194 fprintf (FILE, "\tpop\tar2\n"); \
1197 /* There are three profiling modes for basic blocks available.
1198 The modes are selected at compile time by using the options
1199 -a or -ax of the gnu compiler.
1200 The variable `profile_block_flag' will be set according to the
1203 profile_block_flag == 0, no option used:
1207 profile_block_flag == 1, -a option used.
1209 Count frequency of execution of every basic block.
1211 profile_block_flag == 2, -ax option used.
1213 Generate code to allow several different profiling modes at run time.
1214 Available modes are:
1215 Produce a trace of all basic blocks.
1216 Count frequency of jump instructions executed.
1217 In every mode it is possible to start profiling upon entering
1218 certain functions and to disable profiling of some other functions.
1220 The result of basic-block profiling will be written to a file `bb.out'.
1221 If the -ax option is used parameters for the profiling will be read
1226 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) \
1227 if (profile_block_flag == 2) \
1231 fprintf (FILE, "\tpush\tst\n"); \
1232 fprintf (FILE, "\tpush\tar2\n"); \
1233 fprintf (FILE, "\tpush\tr2\n"); \
1234 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1235 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1236 if (BLOCKNO > 32767) \
1238 fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16); \
1239 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1243 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1245 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1246 fprintf (FILE, "\tpop\tr2\n"); \
1247 fprintf (FILE, "\tpop\tar2\n"); \
1248 fprintf (FILE, "\tpop\tst\n"); \
1252 fprintf (FILE, "\tpush\tst\n"); \
1253 fprintf (FILE, "\tpush\tar2\n"); \
1254 fprintf (FILE, "\tpush\tr2\n"); \
1255 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1256 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1257 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1258 if (BLOCKNO > 32767) \
1260 fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16); \
1261 fprintf (FILE, "\tlsh\t16,r2\n"); \
1262 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1266 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1268 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1269 fprintf (FILE, "\tpop\tr2\n"); \
1270 fprintf (FILE, "\tpop\tar2\n"); \
1271 fprintf (FILE, "\tpop\tst\n"); \
1278 fprintf (FILE, "\tpush\tst\n"); \
1279 fprintf (FILE, "\tpush\tar2\n"); \
1280 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1281 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1282 fprintf (FILE, "\tcmpi\t0,*ar2\n"); \
1283 fprintf (FILE, "\tbne\t$+2\n"); \
1284 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1285 fprintf (FILE, "\tpop\tar2\n"); \
1286 fprintf (FILE, "\tpop\tst\n"); \
1290 fprintf (FILE, "\tpush\tst\n"); \
1291 fprintf (FILE, "\tpush\tar2\n"); \
1292 fprintf (FILE, "\tpush\tr2\n"); \
1293 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1294 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1295 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1296 fprintf (FILE, "\tldi\t*ar2,r2\n"); \
1297 fprintf (FILE, "\tbne\t$+2\n"); \
1298 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1299 fprintf (FILE, "\tpop\tr2\n"); \
1300 fprintf (FILE, "\tpop\tar2\n"); \
1301 fprintf (FILE, "\tpop\tst\n"); \
1305 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1306 if (profile_block_flag == 2) \
1310 fprintf (FILE, "\tpush\tst\n"); \
1311 fprintf (FILE, "\tpush\tar2\n"); \
1312 fprintf (FILE, "\tpush\tar0\n"); \
1313 fprintf (FILE, "\tldhi\t^___bb,ar2\n"); \
1314 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1315 if (BLOCKNO > 32767) \
1317 fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
1318 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1322 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1324 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1325 fprintf (FILE, "\tldhi\t^LPBX0,ar0\n"); \
1326 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1327 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1328 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1329 fprintf (FILE, "\tpop\tar0\n"); \
1330 fprintf (FILE, "\tpop\tar2\n"); \
1331 fprintf (FILE, "\tpop\tst\n"); \
1335 fprintf (FILE, "\tpush\tst\n"); \
1336 fprintf (FILE, "\tpush\tar2\n"); \
1337 fprintf (FILE, "\tpush\tar0\n"); \
1338 fprintf (FILE, "\tldiu\t^___bb,ar2\n"); \
1339 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1340 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1341 if (BLOCKNO > 32767) \
1343 fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16); \
1344 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1345 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1349 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1351 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1352 fprintf (FILE, "\tldiu\t^LPBX0,ar0\n"); \
1353 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1354 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1355 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1356 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1357 fprintf (FILE, "\tpop\tar0\n"); \
1358 fprintf (FILE, "\tpop\tar2\n"); \
1359 fprintf (FILE, "\tpop\tst\n"); \
1366 fprintf (FILE, "\tpush\tar2\n"); \
1367 fprintf (FILE, "\tpush\tar0\n"); \
1368 fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1369 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1370 fprintf (FILE, "\taddi3\t1,*ar2,ar0\n"); \
1371 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1372 fprintf (FILE, "\tpop\tar0\n"); \
1373 fprintf (FILE, "\tpop\tar2\n"); \
1377 fprintf (FILE, "\tpush\tar2\n"); \
1378 fprintf (FILE, "\tpush\tar0\n"); \
1379 fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1380 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1381 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1382 fprintf (FILE, "\tldiu\t*ar2,ar0\n"); \
1383 fprintf (FILE, "\taddi\t1,ar0\n"); \
1384 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1385 fprintf (FILE, "\tpop\tar0\n"); \
1386 fprintf (FILE, "\tpop\tar2\n"); \
1390 #define FUNCTION_BLOCK_PROFILER_EXIT \
1392 emit_insn (gen_push_st ()); \
1393 emit_insn (gen_pushqi ( \
1394 gen_rtx_REG (QImode, AR2_REGNO))); \
1395 emit_call_insn (gen_nodb_call ( \
1396 gen_rtx_SYMBOL_REF (QImode, "__bb_trace_ret")));\
1397 emit_insn (gen_popqi_unspec ( \
1398 gen_rtx_REG (QImode, AR2_REGNO))); \
1399 emit_insn (gen_pop_st ()); \
1402 #define MACHINE_STATE_SAVE(ID) \
1413 asm(" .if .BIGMODEL"); \
1422 asm(" .if .tms320C40"); \
1426 asm(" pushf r10"); \
1428 asm(" pushf r11"); \
1431 #define MACHINE_STATE_RESTORE(ID) \
1432 asm(" .if .tms320C40"); \
1446 asm(" .if .BIGMODEL"); \
1460 /* Implicit Calls to Library Routines. */
1462 #define MULQI3_LIBCALL "__mulqi3"
1463 #define DIVQI3_LIBCALL "__divqi3"
1464 #define UDIVQI3_LIBCALL "__udivqi3"
1465 #define MODQI3_LIBCALL "__modqi3"
1466 #define UMODQI3_LIBCALL "__umodqi3"
1468 #define DIVQF3_LIBCALL "__divqf3"
1470 #define MULHF3_LIBCALL "__mulhf3"
1471 #define DIVHF3_LIBCALL "__divhf3"
1473 #define MULHI3_LIBCALL "__mulhi3"
1474 #define SMULHI3_LIBCALL "__smulhi3_high"
1475 #define UMULHI3_LIBCALL "__umulhi3_high"
1476 #define DIVHI3_LIBCALL "__divhi3"
1477 #define UDIVHI3_LIBCALL "__udivhi3"
1478 #define MODHI3_LIBCALL "__modhi3"
1479 #define UMODHI3_LIBCALL "__umodhi3"
1481 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1482 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1483 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1484 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1486 #define FLOATHIHF2_LIBCALL "__floathihf2"
1487 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1488 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1489 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1491 #define FFS_LIBCALL "__ffs"
1493 #define INIT_TARGET_OPTABS \
1495 smul_optab->handlers[(int) QImode].libfunc \
1496 = init_one_libfunc (MULQI3_LIBCALL); \
1497 sdiv_optab->handlers[(int) QImode].libfunc \
1498 = init_one_libfunc (DIVQI3_LIBCALL); \
1499 udiv_optab->handlers[(int) QImode].libfunc \
1500 = init_one_libfunc (UDIVQI3_LIBCALL); \
1501 smod_optab->handlers[(int) QImode].libfunc \
1502 = init_one_libfunc (MODQI3_LIBCALL); \
1503 umod_optab->handlers[(int) QImode].libfunc \
1504 = init_one_libfunc (UMODQI3_LIBCALL); \
1505 sdiv_optab->handlers[(int) QFmode].libfunc \
1506 = init_one_libfunc (DIVQF3_LIBCALL); \
1507 smul_optab->handlers[(int) HFmode].libfunc \
1508 = init_one_libfunc (MULHF3_LIBCALL); \
1509 sdiv_optab->handlers[(int) HFmode].libfunc \
1510 = init_one_libfunc (DIVHF3_LIBCALL); \
1511 smul_optab->handlers[(int) HImode].libfunc \
1512 = init_one_libfunc (MULHI3_LIBCALL); \
1513 sdiv_optab->handlers[(int) HImode].libfunc \
1514 = init_one_libfunc (DIVHI3_LIBCALL); \
1515 udiv_optab->handlers[(int) HImode].libfunc \
1516 = init_one_libfunc (UDIVHI3_LIBCALL); \
1517 smod_optab->handlers[(int) HImode].libfunc \
1518 = init_one_libfunc (MODHI3_LIBCALL); \
1519 umod_optab->handlers[(int) HImode].libfunc \
1520 = init_one_libfunc (UMODHI3_LIBCALL); \
1521 ffs_optab->handlers[(int) QImode].libfunc \
1522 = init_one_libfunc (FFS_LIBCALL); \
1524 = init_one_libfunc(SMULHI3_LIBCALL); \
1526 = init_one_libfunc(UMULHI3_LIBCALL); \
1527 fix_truncqfhi2_libfunc \
1528 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
1529 fixuns_truncqfhi2_libfunc \
1530 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
1531 fix_trunchfhi2_libfunc \
1532 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
1533 fixuns_trunchfhi2_libfunc \
1534 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
1535 floathiqf2_libfunc \
1536 = init_one_libfunc(FLOATHIQF2_LIBCALL); \
1537 floatunshiqf2_libfunc \
1538 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
1539 floathihf2_libfunc \
1540 = init_one_libfunc(FLOATHIHF2_LIBCALL); \
1541 floatunshihf2_libfunc \
1542 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
1545 #define TARGET_MEM_FUNCTIONS
1547 /* Add any extra modes needed to represent the condition code.
1549 On the C4x, we have a "no-overflow" mode which is used when an ADD,
1550 SUB, NEG, or MPY insn is used to set the condition code. This is
1551 to prevent the combiner from optimising away a following CMP of the
1552 result with zero when a signed conditional branch or load insn
1555 The problem is a subtle one and deals with the manner in which the
1556 negative condition (N) flag is used on the C4x. This flag does not
1557 reflect the status of the actual result but of the ideal result had
1558 no overflow occurred (when considering signed operands).
1560 For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
1561 the flags reflect the untruncated result, not the actual result.
1562 While the actual result is less than zero, the N flag is not set
1563 since the ideal result of the addition without truncation would
1566 Note that the while the N flag is handled differently to most other
1567 architectures, the use of it is self consistent and is not the
1568 cause of the problem.
1570 Logical operations set the N flag to the MSB of the result so if
1571 the result is negative, N is 1. However, integer and floating
1572 point operations set the N flag to be the MSB of the result
1573 exclusive ored with the overflow (V) flag. Thus if an overflow
1574 occurs and the result does not have the MSB set (i.e., the result
1575 looks like a positive number), the N flag is set. Conversely, if
1576 an overflow occurs and the MSB of the result is set, N is set to 0.
1577 Thus the N flag represents the sign of the result if it could have
1578 been stored without overflow but does not represent the apparent
1579 sign of the result. Note that most architectures set the N flag to
1580 be the MSB of the result.
1582 The C4x approach to setting the N flag simplifies signed
1583 conditional branches and loads which only have to test the state of
1584 the N flag, whereas most architectures have to look at both the N
1585 and V flags. The disadvantage is that there is no flag giving the
1586 status of the sign bit of the operation. However, there are no
1587 conditional load or branch instructions that make use of this
1588 feature (e.g., BMI---branch minus) instruction. Note that BN and
1589 BLT are identical in the C4x.
1591 To handle the problem where the N flag is set differently whenever
1592 there is an overflow we use a different CC mode, CC_NOOVmode which
1593 says that the CC reflects the comparison of the result against zero
1594 if no overflow occurred.
1598 [(set (reg:CC_NOOV 21)
1599 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
1600 (match_operand:QI 2 "src_operand" ""))
1602 (set (match_operand:QI 0 "ext_reg_operand" "")
1603 (minus:QI (match_dup 1)
1606 Note that there is no problem for insns that don't return a result
1607 like CMP, since the CC reflects the effect of operation.
1609 An example of a potential problem is when GCC
1610 converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
1611 to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
1612 to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
1614 Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
1615 C4x sets the N flag since the result without overflow would have
1616 been 0xffffffff when treating the operands as signed integers.
1617 Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
1618 flag but (GE (0x00000001)) does not set the N flag.
1620 The upshot is that we can not use signed branch and conditional
1621 load instructions after an add, subtract, neg, abs or multiply.
1622 We must emit a compare insn to check the result against 0. */
1624 #define EXTRA_CC_MODES CC(CC_NOOVmode, "CC_NOOV")
1626 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1628 CCmode should be used when no special processing is needed. */
1629 #define SELECT_CC_MODE(OP,X,Y) \
1630 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1631 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1632 || GET_MODE (X) == ABS \
1633 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1634 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1635 || GET_MODE (Y) == ABS) \
1636 ? CC_NOOVmode : CCmode)
1638 /* Addressing Modes. */
1640 #define HAVE_POST_INCREMENT 1
1641 #define HAVE_PRE_INCREMENT 1
1642 #define HAVE_POST_DECREMENT 1
1643 #define HAVE_PRE_DECREMENT 1
1644 #define HAVE_PRE_MODIFY_REG 1
1645 #define HAVE_POST_MODIFY_REG 1
1646 #define HAVE_PRE_MODIFY_DISP 1
1647 #define HAVE_POST_MODIFY_DISP 1
1649 /* The number of insns that can be packed into a single opcode. */
1650 #define PACK_INSNS 2
1652 /* Recognize any constant value that is a valid address.
1653 We could allow arbitrary constant addresses in the large memory
1654 model but for the small memory model we can only accept addresses
1655 within the data page. I suppose we could also allow
1656 CONST PLUS SYMBOL_REF. */
1657 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1659 /* Maximum number of registers that can appear in a valid memory
1661 #define MAX_REGS_PER_ADDRESS 2
1663 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1664 and check its validity for a certain class.
1665 We have two alternate definitions for each of them.
1666 The usual definition accepts all pseudo regs; the other rejects
1667 them unless they have been allocated suitable hard regs.
1668 The symbol REG_OK_STRICT causes the latter definition to be used.
1670 Most source files want to accept pseudo regs in the hope that
1671 they will get allocated to the class that the insn wants them to be in.
1672 Source files for reload pass need to be strict.
1673 After reload, it makes no difference, since pseudo regs have
1674 been eliminated by then. */
1676 #ifndef REG_OK_STRICT
1678 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1680 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1682 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1684 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1686 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1688 if (c4x_check_legit_addr (MODE, X, 0)) \
1694 /* Nonzero if X is a hard reg that can be used as an index. */
1696 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1698 /* Nonzero if X is a hard reg that can be used as a base reg. */
1700 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1702 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1704 if (c4x_check_legit_addr (MODE, X, 1)) \
1710 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1713 new = c4x_legitimize_address (X, MODE); \
1714 if (new != NULL_RTX) \
1721 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1723 if (MODE != HImode \
1725 && GET_MODE (X) != HImode \
1726 && GET_MODE (X) != HFmode \
1727 && (GET_CODE (X) == CONST \
1728 || GET_CODE (X) == SYMBOL_REF \
1729 || GET_CODE (X) == LABEL_REF)) \
1731 if (! TARGET_SMALL) \
1734 X = gen_rtx_LO_SUM (GET_MODE (X), \
1735 gen_rtx_HIGH (GET_MODE (X), X), X); \
1736 i = push_reload (XEXP (X, 0), NULL_RTX, \
1737 &XEXP (X, 0), NULL, \
1738 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1740 /* The only valid reg is DP. This is a fixed reg and will \
1741 normally not be used so force it. */ \
1742 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1743 rld[i].nocombine = 1; \
1747 else if (MODE != HImode \
1749 && GET_MODE (X) != HImode \
1750 && GET_MODE (X) != HFmode \
1751 && GET_CODE (X) == LO_SUM \
1752 && GET_CODE (XEXP (X,0)) == HIGH \
1753 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1754 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1755 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1757 if (! TARGET_SMALL) \
1759 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1760 &XEXP (X, 0), NULL, \
1761 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1763 /* The only valid reg is DP. This is a fixed reg and will \
1764 normally not be used so force it. */ \
1765 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1766 rld[i].nocombine = 1; \
1772 /* No mode-dependent addresses on the C4x are autoincrements. */
1774 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1775 if (GET_CODE (ADDR) == PRE_DEC \
1776 || GET_CODE (ADDR) == POST_DEC \
1777 || GET_CODE (ADDR) == PRE_INC \
1778 || GET_CODE (ADDR) == POST_INC \
1779 || GET_CODE (ADDR) == POST_MODIFY \
1780 || GET_CODE (ADDR) == PRE_MODIFY) \
1784 /* Nonzero if the constant value X is a legitimate general operand.
1785 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1787 The C4x can only load 16-bit immediate values, so we only allow a
1788 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1789 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1790 model) so that the symbols will be forced into the constant pool.
1791 On second thoughts, let's do this with the move expanders since
1792 the alias analysis has trouble if we force constant addresses
1796 #define LEGITIMATE_CONSTANT_P(X) \
1797 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1798 || (GET_CODE (X) == CONST_INT) \
1799 || (GET_CODE (X) == SYMBOL_REF) \
1800 || (GET_CODE (X) == LABEL_REF) \
1801 || (GET_CODE (X) == CONST) \
1802 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1803 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1805 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1807 /* Define this macro if references to a symbol must be treated
1808 differently depending on something about the variable or
1809 function named by the symbol (such as what section it is in).
1811 The macro definition, if any, is executed immediately after the
1812 rtl for DECL or other node is created.
1813 The value of the rtl will be a `mem' whose address is a
1816 The usual thing for this macro to do is to a flag in the
1817 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1818 name string in the `symbol_ref' (if one bit is not enough
1821 On the C4x we use this to indicate if a symbol is in text or
1824 #define ENCODE_SECTION_INFO(DECL) c4x_encode_section_info (DECL);
1826 /* Descripting Relative Cost of Operations. */
1828 /* Provide the costs of a rtl expression. This is in the body of a
1831 Note that we return, rather than break so that rtx_cost doesn't
1832 include CONST_COSTS otherwise expand_mult will think that it is
1833 cheaper to synthesise a multiply rather than to use a multiply
1834 instruction. I think this is because the algorithm synth_mult
1835 doesn't take into account the loading of the operands, whereas the
1836 calculation of mult_cost does.
1840 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1849 return COSTS_N_INSNS (1); \
1851 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1852 || TARGET_MPYI ? 1 : 14); \
1857 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1860 /* Compute the cost of computing a constant rtl expression RTX
1861 whose rtx-code is CODE. The body of this macro is a portion
1862 of a switch statement. If the code is computed here,
1863 return it with a return statement. Otherwise, break from the switch.
1865 An insn is assumed to cost 4 units.
1866 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1868 Some small integers are effectively free for the C40. We should
1869 also consider if we are using the small memory model. With
1870 the big memory model we require an extra insn for a constant
1873 This is used by expand_binop to decide whether to force a constant
1874 into a register. If the cost is greater than 2 and the constant
1875 is used within a short loop, it gets forced into a register.
1876 Ideally, there should be some weighting as to how mnay times it is used
1879 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1881 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1882 || (C) == IOR || (C) == XOR)
1884 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1886 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1888 if (c4x_J_constant (RTX)) \
1891 && OUTER_CODE == AND \
1892 && GET_CODE (RTX) == CONST_INT \
1893 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1896 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1897 && GET_CODE (RTX) == CONST_INT \
1898 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1900 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1902 if (LOGICAL_CODE_P (OUTER_CODE) \
1903 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1909 case CONST_DOUBLE: \
1910 if (c4x_H_constant (RTX)) \
1912 if (GET_MODE (RTX) == QFmode) \
1917 /* Compute the cost of an address. This is meant to approximate the size
1918 and/or execution delay of an insn using that address. If the cost is
1919 approximated by the RTL complexity, including CONST_COSTS above, as
1920 is usually the case for CISC machines, this macro should not be defined.
1921 For aggressively RISCy machines, only one insn format is allowed, so
1922 this macro should be a constant. The value of this macro only matters
1923 for valid addresses. We handle the most common address without
1924 a call to c4x_address_cost. */
1926 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1928 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1929 if (REG_P (OP1) && ! REG_P (OP0)) \
1931 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1932 CODE = swap_condition (CODE); \
1935 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1936 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1937 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1938 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1939 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1941 /* Compute extra cost of moving data between one register class
1944 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1946 /* Memory move cost is same as fast register move. Maybe this should
1949 #define MEMORY_MOVE_COST(M,C,I) 4
1951 /* Branches are kind of expensive (even with delayed branching) so
1952 make their cost higher. */
1954 #define BRANCH_COST 8
1956 #define WORD_REGISTER_OPERATIONS
1958 /* Dividing the Output into Sections. */
1960 #define TEXT_SECTION_ASM_OP "\t.text"
1962 #define DATA_SECTION_ASM_OP "\t.data"
1964 #define USE_CONST_SECTION 1
1966 #define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
1968 /* Do not use .init section so __main will be called on startup. This will
1969 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1972 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1975 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1977 #undef EXTRA_SECTIONS
1978 #define EXTRA_SECTIONS in_const, in_init, in_fini
1980 #undef EXTRA_SECTION_FUNCTIONS
1981 #define EXTRA_SECTION_FUNCTIONS \
1982 CONST_SECTION_FUNCTION \
1983 INIT_SECTION_FUNCTION \
1984 FINI_SECTION_FUNCTION
1986 #define INIT_SECTION_FUNCTION \
1987 extern void init_section PARAMS ((void)); \
1991 if (in_section != in_init) \
1993 fprintf (asm_out_file, ";\t.init\n"); \
1994 in_section = in_init; \
1998 #define FINI_SECTION_FUNCTION \
2002 if (in_section != in_fini) \
2004 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
2005 in_section = in_fini; \
2009 #define READONLY_DATA_SECTION() const_section ()
2011 #define CONST_SECTION_FUNCTION \
2015 if (! USE_CONST_SECTION) \
2017 else if (in_section != in_const) \
2019 fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
2020 in_section = in_const; \
2024 #define ASM_STABS_OP "\t.stabs\t"
2026 /* Switch into a generic section. */
2027 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
2029 /* A C statement or statements to switch to the appropriate
2030 section for output of DECL. DECL is either a `VAR_DECL' node
2031 or a constant of some sort. RELOC indicates whether forming
2032 the initial value of DECL requires link-time relocations. */
2034 #define SELECT_SECTION(DECL, RELOC, ALIGN) \
2036 if (TREE_CODE (DECL) == STRING_CST) \
2038 if (! flag_writable_strings) \
2043 else if (TREE_CODE (DECL) == VAR_DECL) \
2045 if ((0 && RELOC) /* Should be (flag_pic && RELOC). */ \
2046 || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
2047 || ! DECL_INITIAL (DECL) \
2048 || (DECL_INITIAL (DECL) != error_mark_node \
2049 && ! TREE_CONSTANT (DECL_INITIAL (DECL)))) \
2058 /* The TI assembler wants to have hex numbers this way. */
2060 #undef HOST_WIDE_INT_PRINT_HEX
2061 #ifndef HOST_WIDE_INT_PRINT_HEX
2062 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2063 # define HOST_WIDE_INT_PRINT_HEX "0%xh"
2065 # if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
2066 # define HOST_WIDE_INT_PRINT_HEX "0%lxh"
2068 # define HOST_WIDE_INT_PRINT_HEX "0%llxh"
2071 #endif /* ! HOST_WIDE_INT_PRINT_HEX */
2073 /* A C statement or statements to switch to the appropriate
2074 section for output of RTX in mode MODE. RTX is some kind
2075 of constant in RTL. The argument MODE is redundant except
2076 in the case of a `const_int' rtx. Currently, these always
2077 go into the const section. */
2079 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) const_section()
2082 /* Overall Framework of an Assembler File. */
2083 /* We need to have a data section we can identify so that we can set
2084 the DP register back to a data pointer in the small memory model.
2085 This is only required for ISRs if we are paranoid that someone
2086 may have quietly changed this register on the sly. */
2088 #define ASM_FILE_START(FILE) \
2090 int dspversion = 0; \
2091 if (TARGET_C30) dspversion = 30; \
2092 if (TARGET_C31) dspversion = 31; \
2093 if (TARGET_C32) dspversion = 32; \
2094 if (TARGET_C40) dspversion = 40; \
2095 if (TARGET_C44) dspversion = 44; \
2096 fprintf (FILE, "\t.version\t%d\n", dspversion); \
2097 fprintf (FILE, "\t.file\t"); \
2101 const char *after_dir = main_input_filename; \
2102 for (p = main_input_filename; *p; p++) \
2104 after_dir = p + 1; \
2105 output_quoted_string (FILE, after_dir); \
2108 output_quoted_string (FILE, main_input_filename); \
2109 fputs ("\n\t.data\ndata_sec:\n", FILE); \
2112 #define ASM_COMMENT_START ";"
2114 #define ASM_APP_ON ""
2115 #define ASM_APP_OFF ""
2117 /* Output float/double constants QFmode. */
2119 #define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE) \
2123 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2124 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2125 if (sizeof (int) == sizeof (long)) \
2126 fprintf (FILE, "\t.word\t0%08xh\t; %s\n", (int) l, str);\
2128 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
2131 /* Output long double constants HFmode.
2132 The first word contains the exponent and first part of the mantissa
2133 in the same manner as QFmode. The second word contains the full
2134 mantissa. We should ensure that the two words are allocated within
2135 the same page for the large memory model since we only output a single
2136 LDP instruction. FIXME. The simplest solution probably is to output
2137 a LDP for each load. */
2139 #define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE) \
2143 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2144 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2145 l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
2146 if (sizeof (int) == sizeof (long)) \
2147 fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
2148 (int) l[0], str, (int) l[1]); \
2150 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
2154 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
2156 fprintf (FILE, "\t.word\t"); \
2157 output_addr_const (FILE, VALUE); \
2158 if (GET_CODE (VALUE) != SYMBOL_REF) \
2159 fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE)); \
2161 fputc ('\n', FILE); \
2164 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
2165 fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
2167 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
2169 /* Output and Generation of Labels. */
2171 #define NO_DOT_IN_LABEL /* Only required for TI format. */
2173 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2174 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0);
2176 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
2178 fprintf (FILE, "\t.global\t"); \
2179 assemble_name (FILE, NAME); \
2180 fputs ("\n", FILE); \
2181 c4x_global_label (NAME); \
2184 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2185 c4x_external_ref (NAME)
2187 /* A C statement to output on FILE an assembler pseudo-op to
2188 declare a library function named external.
2189 (Only needed to keep asm30 happy for ___divqf3 etc.) */
2191 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
2192 c4x_external_ref (XSTR (FUN, 0))
2194 #define ASM_FILE_END(FILE) \
2197 /* The prefix to add to user-visible assembler symbols. */
2199 #define USER_LABEL_PREFIX "_"
2201 /* This is how to output an internal numbered label where
2202 PREFIX is the class of label and NUM is the number within the class. */
2204 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
2205 asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2207 /* This is how to store into the string LABEL
2208 the symbol_ref name of an internal numbered label where
2209 PREFIX is the class of label and NUM is the number within the class.
2210 This is suitable for output with `assemble_name'. */
2212 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
2213 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
2215 /* Store in OUTPUT a string (made with alloca) containing
2216 an assembler-name for a local static variable named NAME.
2217 LABELNO is an integer which is different for each call. */
2219 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2220 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2221 sprintf ((OUTPUT), "%s$%d", (NAME), (LABELNO)))
2223 /* A C statement to output to the stdio stream STREAM assembler code which
2224 defines (equates) the symbol NAME to have the value VALUE. */
2226 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
2228 assemble_name (STREAM, NAME); \
2229 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
2232 /* Output of Dispatch Tables. */
2234 /* This is how to output an element of a case-vector that is absolute. */
2236 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2237 fprintf (FILE, "\t.long\tL%d\n", VALUE);
2239 /* This is how to output an element of a case-vector that is relative. */
2241 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2242 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
2245 #define SIZE_TYPE "unsigned int"
2248 #define PTRDIFF_TYPE "int"
2251 #define WCHAR_TYPE "long int"
2253 #undef WCHAR_TYPE_SIZE
2254 #define WCHAR_TYPE_SIZE 32
2256 #define INT_TYPE_SIZE 32
2257 #define LONG_LONG_TYPE_SIZE 64
2258 #define FLOAT_TYPE_SIZE 32
2259 #define DOUBLE_TYPE_SIZE 32
2260 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
2262 /* Allow #sccs in preprocessor. */
2264 #define SCCS_DIRECTIVE
2266 /* Output #ident as a .ident. */
2268 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2269 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
2271 #define CPP_PREDEFINES ""
2273 /* Output of Uninitialized Variables. */
2275 /* This says how to output an assembler line to define a local
2276 uninitialized variable. */
2278 #undef ASM_OUTPUT_LOCAL
2279 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2280 ( fputs ("\t.bss\t", FILE), \
2281 assemble_name (FILE, (NAME)), \
2282 fprintf (FILE, ",%u\n", (ROUNDED)))
2284 /* This says how to output an assembler line to define a global
2285 uninitialized variable. */
2287 #undef ASM_OUTPUT_COMMON
2288 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2289 ( fputs ("\t.globl\t", FILE), \
2290 assemble_name (FILE, (NAME)), \
2291 fputs ("\n\t.bss\t", FILE), \
2292 assemble_name (FILE, (NAME)), \
2293 fprintf (FILE, ",%u\n", (ROUNDED)))
2295 #undef ASM_OUTPUT_BSS
2296 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2297 ( fputs ("\t.globl\t", FILE), \
2298 assemble_name (FILE, (NAME)), \
2299 fputs ("\n\t.bss\t", FILE), \
2300 assemble_name (FILE, (NAME)), \
2301 fprintf (FILE, ",%u\n", (SIZE)))
2303 /* Macros Controlling Initialization Routines. */
2305 #define OBJECT_FORMAT_COFF
2306 #define REAL_NM_FILE_NAME "c4x-nm"
2308 /* Output of Assembler Instructions. */
2310 /* Register names when used for integer modes. */
2312 #define REGISTER_NAMES \
2314 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2315 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2316 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2317 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
2320 /* Alternate register names when used for floating point modes. */
2322 #define FLOAT_REGISTER_NAMES \
2324 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2325 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2326 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2327 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
2330 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
2332 /* Determine which codes are valid without a following integer. These must
2333 not be alphabetic. */
2335 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
2337 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
2339 /* C4x specific pragmas. */
2340 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2341 cpp_register_pragma (PFILE, 0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
2342 cpp_register_pragma (PFILE, 0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
2343 cpp_register_pragma (PFILE, 0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
2344 cpp_register_pragma (PFILE, 0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
2345 cpp_register_pragma (PFILE, 0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
2346 cpp_register_pragma (PFILE, 0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
2347 cpp_register_pragma (PFILE, 0, "FUNC_NEVER_RETURNS", \
2348 c4x_pr_FUNC_NEVER_RETURNS); \
2349 cpp_register_pragma (PFILE, 0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
2350 cpp_register_pragma (PFILE, 0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
2351 cpp_register_pragma (PFILE, 0, "INTERRUPT", c4x_pr_INTERRUPT); \
2354 /* Assembler Commands for Alignment. */
2356 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
2358 for (; c > 0; --c) \
2359 fprintf (FILE,"\t.word\t0\n"); \
2362 #define ASM_NO_SKIP_IN_TEXT 1
2364 /* I'm not sure about this one. FIXME. */
2366 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
2368 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
2371 /* Macros for SDB and DWARF Output (use .sdef instead of .def
2372 to avoid conflict with TI's use of .def). */
2374 #define SDB_DELIM "\n"
2375 #define SDB_DEBUGGING_INFO
2377 /* Don't use octal since this can confuse gas for the c4x. */
2378 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
2380 #define PUT_SDB_DEF(A) \
2381 do { fprintf (asm_out_file, "\t.sdef\t"); \
2382 ASM_OUTPUT_LABELREF (asm_out_file, A); \
2383 fprintf (asm_out_file, SDB_DELIM); } while (0)
2385 #define PUT_SDB_PLAIN_DEF(A) \
2386 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
2388 #define PUT_SDB_BLOCK_START(LINE) \
2389 fprintf (asm_out_file, \
2390 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2391 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2393 #define PUT_SDB_BLOCK_END(LINE) \
2394 fprintf (asm_out_file, \
2395 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2396 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2398 #define PUT_SDB_FUNCTION_START(LINE) \
2399 fprintf (asm_out_file, \
2400 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2401 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2403 /* Note we output relative line numbers for .ef which gas converts
2404 to absolute line numbers. The TI compiler outputs absolute line numbers
2405 in the .sym directive which gas does not support. */
2406 #define PUT_SDB_FUNCTION_END(LINE) \
2407 fprintf (asm_out_file, \
2408 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2409 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
2412 #define PUT_SDB_EPILOGUE_END(NAME) \
2413 do { fprintf (asm_out_file, "\t.sdef\t"); \
2414 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
2415 fprintf (asm_out_file, \
2416 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
2417 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
2419 /* This is the kind of divide that is easiest to do in the general case. */
2421 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2423 /* Define this as 1 if `char' should by default be signed; else as 0. */
2425 #define DEFAULT_SIGNED_CHAR 1
2427 /* A function address in a call instruction is a byte address (for
2428 indexing purposes) so give the MEM rtx a byte's mode. */
2430 #define FUNCTION_MODE QImode
2432 #define SLOW_BYTE_ACCESS 0
2434 /* Specify the machine mode that pointers have. After generation of
2435 RTL, the compiler makes no further distinction between pointers and
2436 any other objects of this machine mode. */
2438 #define Pmode QImode
2440 /* On the C4x we can write the following code. We have to clear the cache
2441 every time we execute it because the data in the stack could change.
2454 On the c3x this is a bit more difficult. We have to write self
2455 modifying code here. So we have to clear the cache every time
2456 we execute it because the data in the stack could change.
2458 ldiu TOP_OF_FUNCTION,ar1
2460 or BOTTOM_OF_FUNCTION,ar1
2461 ldiu TOP_OF_STATIC,ar0
2464 or BOTTOM_OF_STATIC,ar0
2469 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
2471 #define TRAMPOLINE_TEMPLATE(FILE) \
2475 asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
2476 asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
2477 asm_fprintf (FILE, "\tor\t0,ar1\n"); \
2478 asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
2479 asm_fprintf (FILE, "\tbud\tar1\n"); \
2480 asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
2481 asm_fprintf (FILE, "\tor\t0,ar0\n"); \
2482 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2486 asm_fprintf (FILE, "\tlaj\t$+4\n"); \
2487 asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2488 asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2489 asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2490 asm_fprintf (FILE, "\tbud\tar1\n"); \
2491 asm_fprintf (FILE, "\tnop\n"); \
2492 asm_fprintf (FILE, "\tnop\n"); \
2493 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2494 asm_fprintf (FILE, "\t.word\t0\n"); \
2495 asm_fprintf (FILE, "\t.word\t0\n"); \
2499 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2504 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2505 size_int (16), 0, 1); \
2506 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2507 gen_rtx (CONST_INT, VOIDmode, 0x5069), \
2508 size_int (16), 0, 1); \
2509 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2510 emit_move_insn (gen_rtx (MEM, QImode, \
2511 plus_constant (tramp, 0)), tmp1); \
2512 tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
2514 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2515 gen_rtx (CONST_INT, VOIDmode, 0x1069), \
2516 size_int (16), 0, 1); \
2517 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2518 emit_move_insn (gen_rtx (MEM, QImode, \
2519 plus_constant (tramp, 2)), tmp1); \
2520 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2521 size_int (16), 0, 1); \
2522 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2523 gen_rtx (CONST_INT, VOIDmode, 0x5068), \
2524 size_int (16), 0, 1); \
2525 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2526 emit_move_insn (gen_rtx (MEM, QImode, \
2527 plus_constant (tramp, 3)), tmp1); \
2528 tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
2530 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2531 gen_rtx (CONST_INT, VOIDmode, 0x1068), \
2532 size_int (16), 0, 1); \
2533 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2534 emit_move_insn (gen_rtx (MEM, QImode, \
2535 plus_constant (tramp, 6)), tmp1); \
2539 emit_move_insn (gen_rtx (MEM, QImode, \
2540 plus_constant (TRAMP, 8)), FNADDR); \
2541 emit_move_insn (gen_rtx (MEM, QImode, \
2542 plus_constant (TRAMP, 9)), CXT); \
2546 /* Specify the machine mode that this machine uses for the index in
2547 the tablejump instruction. */
2549 #define CASE_VECTOR_MODE Pmode
2551 /* Max number of (32-bit) bytes we can move from memory to memory
2552 in one reasonably fast instruction. */
2556 /* MOVE_RATIO is the number of move instructions that is better than a
2559 #define MOVE_RATIO 3
2561 #define BSS_SECTION_ASM_OP "\t.bss"
2563 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2564 asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2566 /* This is how to output an insn to pop a register from the stack.
2567 It need not be very fast code. */
2569 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2570 asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2572 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2573 is done just by pretending it is already truncated. */
2575 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2577 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2579 /* We need to use direct addressing for large constants and addresses
2580 that cannot fit within an instruction. We must check for these
2581 after after the final jump optimisation pass, since this may
2582 introduce a local_move insn for a SYMBOL_REF. This pass
2583 must come before delayed branch slot filling since it can generate
2584 additional instructions. */
2586 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2588 #define DBR_OUTPUT_SEQEND(FILE) \
2589 if (final_sequence != NULL_RTX) \
2592 rtx insn = XVECEXP (final_sequence, 0, 0); \
2593 int laj = GET_CODE (insn) == CALL_INSN \
2594 || (GET_CODE (insn) == INSN \
2595 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
2597 count = dbr_sequence_length(); \
2598 while (count < (laj ? 2 : 3)) \
2600 fputs("\tnop\n", FILE); \
2604 fputs("\tpush\tr11\n", FILE); \
2607 #define NO_FUNCTION_CSE
2609 /* We don't want a leading tab. */
2611 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2613 /* Define the codes that are matched by predicates in c4x.c. */
2615 #define PREDICATE_CODES \
2616 {"fp_zero_operand", {CONST_DOUBLE}}, \
2617 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2618 {"stik_const_operand", {CONST_INT}}, \
2619 {"not_const_operand", {CONST_INT}}, \
2620 {"reg_operand", {REG, SUBREG}}, \
2621 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2622 {"r0r1_reg_operand", {REG, SUBREG}}, \
2623 {"r2r3_reg_operand", {REG, SUBREG}}, \
2624 {"ext_low_reg_operand", {REG, SUBREG}}, \
2625 {"ext_reg_operand", {REG, SUBREG}}, \
2626 {"std_reg_operand", {REG, SUBREG}}, \
2627 {"std_or_reg_operand", {REG, SUBREG}}, \
2628 {"addr_reg_operand", {REG, SUBREG}}, \
2629 {"index_reg_operand", {REG, SUBREG}}, \
2630 {"dp_reg_operand", {REG}}, \
2631 {"sp_reg_operand", {REG}}, \
2632 {"st_reg_operand", {REG}}, \
2633 {"rc_reg_operand", {REG}}, \
2634 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2635 {"dst_operand", {SUBREG, REG, MEM}}, \
2636 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2637 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2638 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2639 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2640 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2641 {"par_ind_operand", {MEM}}, \
2642 {"parallel_operand", {SUBREG, REG, MEM}}, \
2643 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2644 {"mem_operand", {MEM}},
2647 /* Define the intrinsic functions for the c3x/c4x. */
2651 /* intrinsic name */
2652 C4X_BUILTIN_FIX, /* fast_ftoi */
2653 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
2654 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
2655 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
2656 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
2657 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
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