1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994-99, 2000 Free Software Foundation, Inc.
4 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
5 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* RUN-TIME TARGET SPECIFICATION */
28 /* Name of the c4x assembler */
30 #define ASM_PROG "c4x-as"
32 /* Name of the c4x linker */
34 #define LD_PROG "c4x-ld"
36 /* Define assembler options. */
39 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
40 %{!m30:%{!m40:-m40}}}}}}} \
51 %{mmemparm:-p} %{mregparm:-r} \
52 %{!mmemparm:%{!mregparm:-r}} \
53 %{mbig:-b} %{msmall:-s} \
54 %{!msmall:%{!mbig:-b}}"
56 /* Define linker options. */
59 %{m30:--architecture c3x} \
60 %{m31:--architecture c3x} \
61 %{m32:--architecture c3x} \
62 %{mcpu=30:--architecture c3x} \
63 %{mcpu=31:--architecture c3x} \
64 %{mcpu=32:--architecture c3x}"
66 /* Define C preprocessor options. */
69 %{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
70 %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
71 %{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
72 %{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
73 %{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
74 %{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
75 %{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
76 %{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
77 %{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
78 %{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
79 %{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
80 %{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
81 %{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
82 %{!mmemparm:%{!mregparm:-D_REGPARM }} \
83 %{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
84 %{!msmall:%{!mbig:-D_BIGMODEL }} \
85 %{finline-functions:-D_INLINE }"
87 /* Specify the end file to link with. */
89 #define ENDFILE_SPEC ""
91 /* Target compilation option flags. */
93 #define SMALL_MEMORY_FLAG 0x0000001 /* small memory model */
94 #define MPYI_FLAG 0x0000002 /* use 24-bit MPYI for C3x */
95 #define FAST_FIX_FLAG 0x0000004 /* fast fixing of floats */
96 #define RPTS_FLAG 0x0000008 /* allow use of RPTS */
97 #define C3X_FLAG 0x0000010 /* emit C3x code */
98 #define TI_FLAG 0x0000020 /* be compatible with TI assembler */
99 #define PARANOID_FLAG 0x0000040 /* be paranoid about DP reg. in ISRs */
100 #define MEMPARM_FLAG 0x0000080 /* pass arguments on stack */
101 #define DEVEL_FLAG 0x0000100 /* enable features under development */
102 #define RPTB_FLAG 0x0000200 /* enable repeat block */
103 #define BK_FLAG 0x0000400 /* use BK as general register */
104 #define DB_FLAG 0x0000800 /* use decrement and branch for C3x */
105 #define DEBUG_FLAG 0x0001000 /* enable debugging of GCC */
106 #define HOIST_FLAG 0x0002000 /* force constants into registers */
107 #define LOOP_UNSIGNED_FLAG 0x0004000 /* allow unsigned loop counters */
108 #define FORCE_FLAG 0x0008000 /* force op0 and op1 to be same */
109 #define PRESERVE_FLOAT_FLAG 0x0010000 /* save all 40 bits for floats */
110 #define PARALLEL_PACK_FLAG 0x0020000 /* allow parallel insn packing */
111 #define PARALLEL_MPY_FLAG 0x0040000 /* allow MPY||ADD, MPY||SUB insns */
112 #define ALIASES_FLAG 0x0080000 /* assume mem refs possibly aliased */
114 #define C30_FLAG 0x0100000 /* emit C30 code */
115 #define C31_FLAG 0x0200000 /* emit C31 code */
116 #define C32_FLAG 0x0400000 /* emit C32 code */
117 #define C40_FLAG 0x1000000 /* emit C40 code */
118 #define C44_FLAG 0x2000000 /* emit C44 code */
120 /* Run-time compilation parameters selecting different hardware subsets.
122 Macro to define tables used to set the flags.
123 This is a list in braces of triplets in braces,
124 each pair being { "NAME", VALUE, "DESCRIPTION" }
125 where VALUE is the bits to set or minus the bits to clear.
126 An empty string NAME is used to identify the default VALUE. */
128 #define TARGET_SWITCHES \
129 { { "small", SMALL_MEMORY_FLAG, \
130 "Small memory model" }, \
131 { "big", -SMALL_MEMORY_FLAG, \
132 "Big memory model" }, \
133 { "mpyi", MPYI_FLAG, \
134 "Use MPYI instruction for C3x" }, \
135 { "no-mpyi", -MPYI_FLAG, \
136 "Do not use MPYI instruction for C3x" }, \
137 { "fast-fix", FAST_FIX_FLAG, \
138 "Use fast but approximate float to integer conversion" }, \
139 { "no-fast-fix", -FAST_FIX_FLAG, \
140 "Use slow but accurate float to integer conversion" }, \
141 { "rpts", RPTS_FLAG, \
142 "Enable use of RTPS instruction" }, \
143 { "no-rpts", -RPTS_FLAG, \
144 "Disable use of RTPS instruction" }, \
145 { "rptb", RPTB_FLAG, \
146 "Enable use of RTPB instruction" }, \
147 { "no-rptb", -RPTB_FLAG, \
148 "Disable use of RTPB instruction" }, \
150 "Generate code for C30 CPU"}, \
152 "Generate code for C31 CPU"}, \
154 "Generate code for C32 CPU"}, \
156 "Generate code for C40 CPU"}, \
158 "Generate code for C44 CPU"}, \
160 "Emit code compatible with TI tools"}, \
161 { "no-ti", -TI_FLAG, \
162 "Emit code to use GAS extensions"}, \
163 { "paranoid", PARANOID_FLAG, \
164 "Save DP across ISR in small memory model" }, \
165 { "no-paranoid", -PARANOID_FLAG, \
166 "Don't save DP across ISR in small memory model" }, \
167 { "isr-dp-reload", PARANOID_FLAG, \
168 "Save DP across ISR in small memory model" }, \
169 { "no-isr-dp-reload", -PARANOID_FLAG, \
170 "Don't save DP across ISR in small memory model" }, \
171 { "memparm", MEMPARM_FLAG, \
172 "Pass arguments on the stack" }, \
173 { "regparm", -MEMPARM_FLAG, \
174 "Pass arguments in registers" }, \
175 { "devel", DEVEL_FLAG, \
176 "Enable new features under development" }, \
177 { "no-devel", -DEVEL_FLAG, \
178 "Disable new features under development" }, \
180 "Use the BK register as a general purpose register" }, \
181 { "no-bk", -BK_FLAG, \
182 "Do not allocate BK register" }, \
184 "Enable use of DB instruction" }, \
185 { "no-db", -DB_FLAG, \
186 "Disable use of DB instruction" }, \
187 { "debug", DEBUG_FLAG, \
188 "Enable debugging" }, \
189 { "no-debug", -DEBUG_FLAG, \
190 "Disable debugging" }, \
191 { "hoist", HOIST_FLAG, \
192 "Force constants into registers to improve hoisting" }, \
193 { "no-hoist", -HOIST_FLAG, \
194 "Don't force constants into registers" }, \
195 { "force", FORCE_FLAG, \
196 "Force RTL generation to emit valid 3 operand insns" }, \
197 { "no-force", -FORCE_FLAG, \
198 "Allow RTL generation to emit invalid 3 operand insns" }, \
199 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
200 "Allow unsigned interation counts for RPTB/DB" }, \
201 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
202 "Disallow unsigned iteration counts for RPTB/DB" }, \
203 { "preserve-float", PRESERVE_FLOAT_FLAG, \
204 "Preserve all 40 bits of FP reg across call" }, \
205 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
206 "Only preserve 32 bits of FP reg across call" }, \
207 { "parallel-insns", PARALLEL_PACK_FLAG, \
208 "Enable parallel instructions" }, \
209 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
210 "Disable parallel instructions" }, \
211 { "parallel-mpy", PARALLEL_MPY_FLAG, \
212 "Enable MPY||ADD and MPY||SUB instructions" }, \
213 { "no-parallel-insns", -PARALLEL_PACK_FLAG, \
214 "Disable MPY||ADD and MPY||SUB instructions" }, \
215 { "aliases", ALIASES_FLAG, \
216 "Assume that pointers may be aliased" }, \
217 { "no-aliases", -ALIASES_FLAG, \
218 "Assume that pointers not aliased" }, \
219 { "", TARGET_DEFAULT, ""} }
221 /* Default target switches */
223 /* Play safe, not the fastest code. */
224 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_PACK_FLAG \
225 | PARALLEL_MPY_FLAG | RPTB_FLAG
228 Max iteration count for RPTB/RPTS is 2^31 + 1.
229 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
230 RPTS blocks interrupts. */
233 extern int target_flags;
235 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
236 #define TARGET_PARALLEL 1 /* Enable parallel insns in MD. */
237 #define TARGET_SMALL_REG_CLASS 0
239 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
240 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
241 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
242 #define TARGET_RPTS (target_flags & RPTS_FLAG)
243 #define TARGET_TI (target_flags & TI_FLAG)
244 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
245 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
246 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
247 #define TARGET_RPTB (target_flags & RPTB_FLAG \
249 #define TARGET_BK (target_flags & BK_FLAG)
250 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
251 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
252 #define TARGET_HOIST (target_flags & HOIST_FLAG)
253 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
254 #define TARGET_FORCE (target_flags & FORCE_FLAG)
255 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
256 #define TARGET_PARALLEL_PACK (TARGET_RPTB \
257 && (target_flags & PARALLEL_PACK_FLAG) \
259 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL_PACK \
260 && (target_flags & PARALLEL_MPY_FLAG))
261 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
263 #define TARGET_C3X (target_flags & C3X_FLAG)
264 #define TARGET_C30 (target_flags & C30_FLAG)
265 #define TARGET_C31 (target_flags & C31_FLAG)
266 #define TARGET_C32 (target_flags & C32_FLAG)
267 #define TARGET_C40 (target_flags & C40_FLAG)
268 #define TARGET_C44 (target_flags & C44_FLAG)
270 /* Define some options to control code generation. */
271 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
272 #define TARGET_EXPOSE_LDP 0
274 /* -mrpts allows the use of the RPTS instruction irregardless.
275 -mrpts=max-cycles will use RPTS if the number of cycles is constant
276 and less than max-cycles. */
278 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
280 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
282 /* -mcpu=XX with XX = target DSP version number */
284 /* This macro is similar to `TARGET_SWITCHES' but defines names of
285 command options that have values. Its definition is an
286 initializer with a subgrouping for each command option.
288 Each subgrouping contains a string constant, that defines the
289 fixed part of the option name, and the address of a variable.
290 The variable, type `char *', is set to the variable part of the
291 given option if the fixed part matches. The actual option name
292 is made by appending `-m' to the specified name.
294 Here is an example which defines `-mshort-data-NUMBER'. If the
295 given option is `-mshort-data-512', the variable `m88k_short_data'
296 will be set to the string `"512"'.
298 extern char *m88k_short_data;
299 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
301 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
303 #define TARGET_OPTIONS \
304 { {"rpts=", &c4x_rpts_cycles_string, \
305 "Specify maximum number of iterations for RPTS" }, \
306 {"cpu=", &c4x_cpu_version_string, \
307 "Select CPU to generate code for" } }
309 /* Sometimes certain combinations of command options do not make sense
310 on a particular target machine. You can define a macro
311 `OVERRIDE_OPTIONS' to take account of this. This macro, if
312 defined, is executed once just after all the command options have
315 #define OVERRIDE_OPTIONS c4x_override_options ()
317 /* Define this to change the optimizations performed by default. */
319 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
321 /* Run Time Target Specification */
323 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
327 #define BITS_BIG_ENDIAN 0
328 #define BYTES_BIG_ENDIAN 0
329 #define WORDS_BIG_ENDIAN 0
331 /* Technically, we are little endian, but we put the floats out as
332 whole longs and this makes GCC put them out in the right order. */
334 #define FLOAT_WORDS_BIG_ENDIAN 1
336 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
337 all integral and floating point data types are stored in memory as
338 32-bits (floating point types can be stored as 40-bits in the
339 extended precision registers), so sizeof(char) = sizeof(short) =
340 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
342 #define BITS_PER_UNIT 32
343 #define BITS_PER_WORD 32
344 #define UNITS_PER_WORD 1
345 #define POINTER_SIZE 32
346 #define PARM_BOUNDARY 32
347 #define STACK_BOUNDARY 32
348 #define FUNCTION_BOUNDARY 32
349 #define BIGGEST_ALIGNMENT 32
350 #define EMPTY_FIELD_BOUNDARY 32
351 #define STRICT_ALIGNMENT 0
352 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
353 #define MAX_FIXED_MODE_SIZE 64 /* HImode */
355 /* Number of bits in the high and low parts of a two stage
356 load of an immediate constant. */
357 #define BITS_PER_HIGH 16
358 #define BITS_PER_LO_SUM 16
360 /* Use the internal floating point stuff in the compiler and not the
361 host floating point stuff. */
363 #define REAL_ARITHMETIC
365 /* Define register numbers. */
367 /* Extended-precision registers. */
378 /* Auxiliary (address) registers. */
389 /* Data page register. */
393 /* Index registers. */
398 /* Block size register. */
406 /* Status register. */
410 /* Misc. interrupt registers. */
412 #define DIE_REGNO 22 /* C4x only. */
413 #define IE_REGNO 22 /* C3x only. */
414 #define IIE_REGNO 23 /* C4x only. */
415 #define IF_REGNO 23 /* C3x only. */
416 #define IIF_REGNO 24 /* C4x only. */
417 #define IOF_REGNO 24 /* C3x only. */
419 /* Repeat block registers. */
425 /* Additional extended-precision registers. */
427 #define R8_REGNO 28 /* C4x only. */
428 #define R9_REGNO 29 /* C4x only. */
429 #define R10_REGNO 30 /* C4x only. */
430 #define R11_REGNO 31 /* C4x only. */
432 #define FIRST_PSEUDO_REGISTER 32
434 /* Extended precision registers (low set). */
436 #define IS_R0R1_REGNO(r) ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
437 #define IS_R2R3_REGNO(r) ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
438 #define IS_EXT_LOW_REGNO(r) ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
440 /* Extended precision registers (high set). */
442 #define IS_EXT_HIGH_REGNO(r) (! TARGET_C3X \
443 && ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
444 /* Address registers. */
446 #define IS_AUX_REGNO(r) (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
447 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
448 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
449 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
450 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
451 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
453 /* Misc registers. */
455 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
456 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
457 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
459 /* Composite register sets. */
461 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
462 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
463 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
464 || IS_REPEAT_REGNO(r) \
467 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
468 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
470 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
471 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
472 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
473 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
474 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
475 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
476 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
477 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
478 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
479 || IS_PSEUDO_REGNO(r))
480 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
481 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
482 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
483 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
485 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
486 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
487 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
488 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
489 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
490 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
491 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
493 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
494 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
495 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
496 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
497 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
498 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
500 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
501 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
502 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
503 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
504 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
505 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
507 /* 1 for registers that have pervasive standard uses
508 and are not available for the register allocator. */
510 #define FIXED_REGISTERS \
512 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
514 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
515 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
518 /* 1 for registers not available across function calls.
519 These must include the FIXED_REGISTERS and also any
520 registers that can be used without being saved.
521 The latter must include the registers where values are returned
522 and the register where structure-value addresses are passed.
523 Aside from that, you can include as many other registers as you like.
525 Note that the extended precision registers are only saved in some
526 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
527 get clobbered for a given regno. */
529 #define CALL_USED_REGISTERS \
531 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */ \
532 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
533 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11 */ \
534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
537 /* Macro to conditionally modify fixed_regs/call_used_regs. */
539 #define CONDITIONAL_REGISTER_USAGE \
543 fixed_regs[BK_REGNO] = 1; \
544 call_used_regs[BK_REGNO] = 1; \
545 c4x_regclass_map[BK_REGNO] = NO_REGS; \
551 reg_names[DIE_REGNO] = "ie"; /* clobber die */ \
552 reg_names[IF_REGNO] = "if"; /* clobber iie */ \
553 reg_names[IOF_REGNO] = "iof"; /* clobber iif */ \
555 for (i = R8_REGNO; i <= R11_REGNO; i++) \
557 fixed_regs[i] = call_used_regs[i] = 1; \
558 c4x_regclass_map[i] = NO_REGS; \
561 if (TARGET_PRESERVE_FLOAT) \
563 c4x_caller_save_map[R6_REGNO] = HFmode; \
564 c4x_caller_save_map[R7_REGNO] = HFmode; \
568 /* Order of Allocation of Registers */
570 /* List the order in which to allocate registers. Each register must be
571 listed once, even those in FIXED_REGISTERS.
573 First allocate registers that don't need preservation across calls,
574 except index and address registers. Then allocate data registers
575 that require preservation across calls (even though this invokes an
576 extra overhead of having to save/restore these registers). Next
577 allocate the address and index registers, since using these
578 registers for arithmetic can cause pipeline stalls. Finally
579 allocated the fixed registers which won't be allocated anyhow. */
581 #define REG_ALLOC_ORDER \
582 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
583 R9_REGNO, R10_REGNO, R11_REGNO, \
584 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
585 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
586 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
587 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
588 IR0_REGNO, IR1_REGNO, \
589 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
592 /* Determine which register classes are very likely used by spill registers.
593 local-alloc.c won't allocate pseudos that have these classes as their
594 preferred class unless they are "preferred or nothing". */
596 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
598 /* CCmode is wrongly defined in machmode.def It should have a size
599 of UNITS_PER_WORD. */
601 #define HARD_REGNO_NREGS(REGNO, MODE) \
602 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
603 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
606 /* A C expression that is nonzero if the hard register REGNO is preserved
607 across a call in mode MODE. This does not have to include the call used
610 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
611 ((((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) && ! ((MODE) == QFmode)) \
612 || (((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO)) \
613 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
615 /* Specify the modes required to caller save a given hard regno. */
617 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) (c4x_caller_save_map[REGNO])
619 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
621 /* A C expression that is nonzero if it is desirable to choose
622 register allocation so as to avoid move instructions between a
623 value of mode MODE1 and a value of mode MODE2.
625 Value is 1 if it is a good idea to tie two pseudo registers
626 when one has mode MODE1 and one has mode MODE2.
627 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
628 for any hard reg, then this must be 0 for correct output. */
630 #define MODES_TIEABLE_P(MODE1, MODE2) 0
633 /* Define the classes of registers for register constraints in the
634 machine description. Also define ranges of constants.
636 One of the classes must always be named ALL_REGS and include all hard regs.
637 If there is more than one class, another class must be named NO_REGS
638 and contain no registers.
640 The name GENERAL_REGS must be the name of a class (or an alias for
641 another name such as ALL_REGS). This is the class of registers
642 that is allowed by "g" or "r" in a register constraint.
643 Also, registers outside this class are allocated only when
644 instructions express preferences for them.
646 The classes must be numbered in nondecreasing order; that is,
647 a larger-numbered class must never be contained completely
648 in a smaller-numbered class.
650 For any two classes, it is very desirable that there be another
651 class that represents their union. */
658 EXT_LOW_REGS, /* 'q' */
661 INDEX_REGS, /* 'x' */
667 GENERAL_REGS, /* 'r' */
674 #define N_REG_CLASSES (int) LIM_REG_CLASSES
676 #define REG_CLASS_NAMES \
696 /* Define which registers fit in which classes.
697 This is an initializer for a vector of HARD_REG_SET
698 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
699 since the register allocator will often choose a general register
700 in preference to RC for the decrement_and_branch_on_count pattern. */
702 #define REG_CLASS_CONTENTS \
704 {0x00000000}, /* No registers */ \
705 {0x00000003}, /* 't' R0-R1 */ \
706 {0x0000000c}, /* 'u' R2-R3 */ \
707 {0x000000ff}, /* 'q' R0-R7 */ \
708 {0xf00000ff}, /* 'f' R0-R11 */ \
709 {0x0000ff00}, /* 'a' AR0-AR7 */ \
710 {0x00060000}, /* 'x' IR0-IR1 */ \
711 {0x00080000}, /* 'k' BK */ \
712 {0x00100000}, /* 'b' SP */ \
713 {0x08000000}, /* 'v' RC */ \
714 {0x0800ff00}, /* RC,AR0-AR7 */ \
715 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */ \
716 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */\
717 {0x00010000}, /* 'z' DP */ \
718 {0x00200000}, /* 'y' ST */ \
719 {0xffffffff}, /* All registers */ \
722 /* The same information, inverted:
723 Return the class number of the smallest class containing
724 reg number REGNO. This could be a conditional expression
725 or could index an array. */
727 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
729 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
730 explicitly used in the rtl is kept as short as possible.
732 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
733 is defined since the MPY|ADD insns require the classes R0R1_REGS and
734 R2R3_REGS which are used by the function return registers (R0,R1) and
735 the register arguments (R2,R3), respectively. I'm reluctant to define
736 this macro since it stomps on many potential optimisations. Ideally
737 it should have a register class argument so that not all the register
738 classes gets penalised for the sake of a naughty few... For long
739 double arithmetic we need two additional registers that we can use as
742 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
744 #define BASE_REG_CLASS ADDR_REGS
745 #define INDEX_REG_CLASS INDEX_REGS
748 Register constraints for the C4x
750 a - address reg (ar0-ar7)
752 c - other gp int-only reg
753 d - data/int reg (equiv. to f)
755 h - data/long double reg (equiv. to f)
760 v - repeat count (rc)
761 x - index register (ir0-ir1)
762 y - status register (st)
765 Memory/constant constraints for the C4x
767 G - short float 16-bit
768 I - signed 16-bit constant (sign extended)
769 J - signed 8-bit constant (sign extended) (C4x only)
770 K - signed 5-bit constant (sign extended) (C4x only for stik)
771 L - unsigned 16-bit constant
772 M - unsigned 8-bit constant (C4x only)
773 N - ones complement of unsigned 16-bit constant
774 Q - indirect arx + 9-bit signed displacement
775 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
776 R - indirect arx + 5-bit unsigned displacement (C4x only)
777 S - indirect arx + 0, 1, or irn displacement
778 T - direct symbol ref
779 > - indirect with autoincrement
780 < - indirect with autodecrement
781 } - indirect with post-modify
782 { - indirect with pre-modify
785 #define REG_CLASS_FROM_LETTER(CC) \
786 ( ((CC) == 'a') ? ADDR_REGS \
787 : ((CC) == 'b') ? SP_REG \
788 : ((CC) == 'c') ? INT_REGS \
789 : ((CC) == 'd') ? EXT_REGS \
790 : ((CC) == 'f') ? EXT_REGS \
791 : ((CC) == 'h') ? EXT_REGS \
792 : ((CC) == 'k') ? BK_REG \
793 : ((CC) == 'q') ? EXT_LOW_REGS \
794 : ((CC) == 't') ? R0R1_REGS \
795 : ((CC) == 'u') ? R2R3_REGS \
796 : ((CC) == 'v') ? RC_REG \
797 : ((CC) == 'x') ? INDEX_REGS \
798 : ((CC) == 'y') ? ST_REG \
799 : ((CC) == 'z') ? DP_REG \
802 /* These assume that REGNO is a hard or pseudo reg number.
803 They give nonzero only if REGNO is a hard reg of the suitable class
804 or a pseudo reg currently allocated to a suitable hard reg.
805 Since they use reg_renumber, they are safe only once reg_renumber
806 has been allocated, which happens in local-alloc.c. */
808 #define REGNO_OK_FOR_BASE_P(REGNO) \
809 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
811 #define REGNO_OK_FOR_INDEX_P(REGNO) \
812 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
814 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
816 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
818 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
820 #define CLASS_MAX_NREGS(CLASS, MODE) \
821 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
822 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
824 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K' */
826 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R' */
828 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J' */
830 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M' */
832 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I' */
834 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L' */
836 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N' */
838 #define IS_HIGH_CONST(VAL) (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
841 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S' */
843 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q' */
845 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
846 && IS_DISP1_CONST (VAL + 1))
848 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
849 && IS_DISP8_CONST (VAL + 1))
851 #define CONST_OK_FOR_LETTER_P(VAL, C) \
852 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
853 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
854 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
855 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
856 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
857 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
858 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
861 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
862 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
863 : ((C) == 'H') ? (c4x_H_constant (OP)) \
866 #define EXTRA_CONSTRAINT(OP, C) \
867 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
868 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
869 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
870 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
871 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
874 #define SMALL_CONST(VAL, insn) \
875 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
876 ? IS_INT16_CONST (VAL) \
877 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
878 ? IS_NOT_UINT16_CONST (VAL) \
879 : ( (get_attr_data (insn) == DATA_HIGH_16) \
880 ? IS_HIGH_CONST (VAL) \
881 : IS_UINT16_CONST (VAL) \
887 I. Routine calling with arguments in registers
888 ----------------------------------------------
890 The TI C3x compiler has a rather unusual register passing algorithm.
891 Data is passed in the following registers (in order):
893 AR2, R2, R3, RC, RS, RE
895 However, the first and second floating point values are always in R2
896 and R3 (and all other floats are on the stack). Structs are always
897 passed on the stack. If the last argument is an ellipsis, the
898 previous argument is passed on the stack so that its address can be
899 taken for the stdargs macros.
901 Because of this, we have to pre-scan the list of arguments to figure
902 out what goes where in the list.
904 II. Routine calling with arguments on stack
905 -------------------------------------------
907 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
908 variables loc0, loc1, and loc2. After the function prologue has
909 been executed, the stack frame will look like:
911 [stack grows towards increasing addresses]
913 5 I saved reg1 I <= SP points here
923 0 I old FP I <= FP (AR3) points here
934 All local variables (locn) are accessible by means of +FP(n+1)
935 addressing, where n is the local variable number.
937 All stack arguments (argn) are accessible by means of -FP(n-2).
939 The stack pointer (SP) points to the last register saved in the
942 Note that a push instruction performs a preincrement of the stack
943 pointer. (STACK_PUSH_CODE == PRE_INC)
945 III. Registers used in function calling convention
946 --------------------------------------------------
948 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
949 R6...R7 (only by PUSHF, i.e. upper 32 bits)
952 (Because of this model, we only assign FP values in R6, R7 and
953 only assign integer values in R4, R5.)
955 These registers are saved at each function entry and restored at
956 the exit. Also it is expected any of these not affected by any
957 call to user-defined (not service) functions.
959 Not preserved across calls: R0...R3
960 R4...R5 (upper 8 bits)
961 R6...R7 (lower 8 bits)
962 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
964 These registers are used arbitrary in a function without being preserved.
965 It is also expected that any of these can be clobbered by any call.
967 Not used by GCC (except for in user "asm" statements):
968 IE (DIE), IF (IIE), IOF (IIF)
970 These registers are never used by GCC for any data, but can be used
971 with "asm" statements. */
976 /* Basic Stack Layout */
978 /* The stack grows upward, stack frame grows upward, and args grow
981 #define STARTING_FRAME_OFFSET C4X_LOC0
982 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
983 #define ARGS_GROW_DOWNWARD
984 #define STACK_POINTER_OFFSET 1
986 /* Define this if pushing a word on the stack
987 makes the stack pointer a smaller address. */
989 /* #define STACK_GROWS_DOWNWARD */
990 /* Like the dsp16xx, i370, i960, and we32k ports */
992 /* Define this if the nominal address of the stack frame
993 is at the high-address end of the local variables;
994 that is, each additional local variable allocated
995 goes at a more negative offset in the frame. */
997 /* #define FRAME_GROWS_DOWNWARD */
1000 /* Registers That Address the Stack Frame */
1002 #define STACK_POINTER_REGNUM SP_REGNO /* SP */
1003 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3 */
1004 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3 */
1005 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0 */
1007 /* Eliminating Frame Pointer and Arg Pointer */
1009 #define FRAME_POINTER_REQUIRED 0
1011 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1015 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1016 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1017 offset += TARGET_PRESERVE_FLOAT \
1018 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1020 (DEPTH) = -(offset + get_frame_size ()); \
1023 /* This is a hack... We need to specify a register. */
1024 #define ELIMINABLE_REGS \
1025 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1027 #define CAN_ELIMINATE(FROM, TO) \
1028 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1029 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1031 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1035 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1036 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1037 offset += TARGET_PRESERVE_FLOAT \
1038 && ((regno == R6_REGNO) || (regno == R7_REGNO)) \
1040 (OFFSET) = -(offset + get_frame_size ()); \
1044 /* Passing Function Arguments on the Stack */
1047 #define PUSH_ROUNDING(BYTES) (BYTES)
1049 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1051 /* The following structure is used by calls.c, function.c, c4x.c */
1053 typedef struct c4x_args
1066 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1067 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1069 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1070 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1072 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1073 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1075 /* Define the profitability of saving registers around calls.
1076 We disable caller save to avoid a bug in flow.c (this also affects
1077 other targets such as m68k). Since we must use stf/sti,
1078 the profitability is marginal anyway. */
1080 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1082 /* Never pass data by reference. */
1084 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1086 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1088 /* 1 if N is a possible register number for function argument passing. */
1090 #define FUNCTION_ARG_REGNO_P(REGNO) \
1091 ( ( ((REGNO) == AR2_REGNO) /* AR2 */ \
1092 || ((REGNO) == R2_REGNO) /* R2 */ \
1093 || ((REGNO) == R3_REGNO) /* R3 */ \
1094 || ((REGNO) == RC_REGNO) /* RC */ \
1095 || ((REGNO) == RS_REGNO) /* RS */ \
1096 || ((REGNO) == RE_REGNO)) /* RE */ \
1100 /* How Scalar Function Values Are Returned */
1102 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1103 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0 */
1105 #define LIBCALL_VALUE(MODE) \
1106 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0 */
1108 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1110 /* How Large Values Are Returned */
1112 #define DEFAULT_PCC_STRUCT_RETURN 0
1113 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0 */
1115 /* Varargs handling. */
1117 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1118 c4x_va_start (stdarg, valist, nextarg)
1120 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1121 c4x_va_arg (valist, type)
1123 /* Function Entry and Exit */
1125 #define FUNCTION_PROLOGUE(FILE, SIZE) c4x_function_prologue(FILE, SIZE)
1126 #define FUNCTION_EPILOGUE(FILE, SIZE) c4x_function_epilogue(FILE, SIZE)
1129 /* Generating Code for Profiling */
1131 /* Note that the generated assembly uses the ^ operator to load the 16
1132 MSBs of the address. This is not supported by the TI assembler.
1133 The FUNCTION profiler needs a function mcount which gets passed
1134 a pointer to the LABELNO. */
1136 #define FUNCTION_PROFILER(FILE, LABELNO) \
1139 fprintf (FILE, "\tpush\tar2\n"); \
1140 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1141 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1142 fprintf (FILE, "\tcall\tmcount\n"); \
1143 fprintf (FILE, "\tpop\tar2\n"); \
1147 fprintf (FILE, "\tpush\tar2\n"); \
1148 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1149 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1150 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1151 fprintf (FILE, "\tcall\tmcount\n"); \
1152 fprintf (FILE, "\tpop\tar2\n"); \
1155 /* There are three profiling modes for basic blocks available.
1156 The modes are selected at compile time by using the options
1157 -a or -ax of the gnu compiler.
1158 The variable `profile_block_flag' will be set according to the
1161 profile_block_flag == 0, no option used:
1165 profile_block_flag == 1, -a option used.
1167 Count frequency of execution of every basic block.
1169 profile_block_flag == 2, -ax option used.
1171 Generate code to allow several different profiling modes at run time.
1172 Available modes are:
1173 Produce a trace of all basic blocks.
1174 Count frequency of jump instructions executed.
1175 In every mode it is possible to start profiling upon entering
1176 certain functions and to disable profiling of some other functions.
1178 The result of basic-block profiling will be written to a file `bb.out'.
1179 If the -ax option is used parameters for the profiling will be read
1184 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) \
1185 if (profile_block_flag == 2) \
1189 fprintf (FILE, "\tpush\tst\n"); \
1190 fprintf (FILE, "\tpush\tar2\n"); \
1191 fprintf (FILE, "\tpush\tr2\n"); \
1192 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1193 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1194 if (BLOCKNO > 32767) \
1196 fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16); \
1197 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1201 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1203 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1204 fprintf (FILE, "\tpop\tr2\n"); \
1205 fprintf (FILE, "\tpop\tar2\n"); \
1206 fprintf (FILE, "\tpop\tst\n"); \
1210 fprintf (FILE, "\tpush\tst\n"); \
1211 fprintf (FILE, "\tpush\tar2\n"); \
1212 fprintf (FILE, "\tpush\tr2\n"); \
1213 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1214 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1215 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1216 if (BLOCKNO > 32767) \
1218 fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16); \
1219 fprintf (FILE, "\tlsh\t16,r2\n"); \
1220 fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO)); \
1224 fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO)); \
1226 fprintf (FILE, "\tcall\t___bb_init_trace_func\n"); \
1227 fprintf (FILE, "\tpop\tr2\n"); \
1228 fprintf (FILE, "\tpop\tar2\n"); \
1229 fprintf (FILE, "\tpop\tst\n"); \
1236 fprintf (FILE, "\tpush\tst\n"); \
1237 fprintf (FILE, "\tpush\tar2\n"); \
1238 fprintf (FILE, "\tldhi\t^LPBX0,ar2\n"); \
1239 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1240 fprintf (FILE, "\tcmpi\t0,*ar2\n"); \
1241 fprintf (FILE, "\tbne\t$+2\n"); \
1242 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1243 fprintf (FILE, "\tpop\tar2\n"); \
1244 fprintf (FILE, "\tpop\tst\n"); \
1248 fprintf (FILE, "\tpush\tst\n"); \
1249 fprintf (FILE, "\tpush\tar2\n"); \
1250 fprintf (FILE, "\tpush\tr2\n"); \
1251 fprintf (FILE, "\tldiu\t^LPBX0,ar2\n"); \
1252 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1253 fprintf (FILE, "\tor\t#LPBX0,ar2\n"); \
1254 fprintf (FILE, "\tldi\t*ar2,r2\n"); \
1255 fprintf (FILE, "\tbne\t$+2\n"); \
1256 fprintf (FILE, "\tcall\t___bb_init_func\n"); \
1257 fprintf (FILE, "\tpop\tr2\n"); \
1258 fprintf (FILE, "\tpop\tar2\n"); \
1259 fprintf (FILE, "\tpop\tst\n"); \
1263 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1264 if (profile_block_flag == 2) \
1268 fprintf (FILE, "\tpush\tst\n"); \
1269 fprintf (FILE, "\tpush\tar2\n"); \
1270 fprintf (FILE, "\tpush\tar0\n"); \
1271 fprintf (FILE, "\tldhi\t^___bb,ar2\n"); \
1272 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1273 if (BLOCKNO > 32767) \
1275 fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
1276 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1280 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1282 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1283 fprintf (FILE, "\tldhi\t^LPBX0,ar0\n"); \
1284 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1285 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1286 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1287 fprintf (FILE, "\tpop\tar0\n"); \
1288 fprintf (FILE, "\tpop\tar2\n"); \
1289 fprintf (FILE, "\tpop\tst\n"); \
1293 fprintf (FILE, "\tpush\tst\n"); \
1294 fprintf (FILE, "\tpush\tar2\n"); \
1295 fprintf (FILE, "\tpush\tar0\n"); \
1296 fprintf (FILE, "\tldiu\t^___bb,ar2\n"); \
1297 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1298 fprintf (FILE, "\tor\t#___bb,ar2\n"); \
1299 if (BLOCKNO > 32767) \
1301 fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16); \
1302 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1303 fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO)); \
1307 fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO)); \
1309 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1310 fprintf (FILE, "\tldiu\t^LPBX0,ar0\n"); \
1311 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1312 fprintf (FILE, "\tor\t#LPBX0,ar0\n"); \
1313 fprintf (FILE, "\tsti\tar0,*+ar2(1)\n"); \
1314 fprintf (FILE, "\tcall\t___bb_trace_func\n"); \
1315 fprintf (FILE, "\tpop\tar0\n"); \
1316 fprintf (FILE, "\tpop\tar2\n"); \
1317 fprintf (FILE, "\tpop\tst\n"); \
1324 fprintf (FILE, "\tpush\tar2\n"); \
1325 fprintf (FILE, "\tpush\tar0\n"); \
1326 fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1327 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1328 fprintf (FILE, "\taddi3\t1,*ar2,ar0\n"); \
1329 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1330 fprintf (FILE, "\tpop\tar0\n"); \
1331 fprintf (FILE, "\tpop\tar2\n"); \
1335 fprintf (FILE, "\tpush\tar2\n"); \
1336 fprintf (FILE, "\tpush\tar0\n"); \
1337 fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO)); \
1338 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1339 fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO)); \
1340 fprintf (FILE, "\tldiu\t*ar2,ar0\n"); \
1341 fprintf (FILE, "\taddi\t1,ar0\n"); \
1342 fprintf (FILE, "\tsti\tar0,*ar2\n"); \
1343 fprintf (FILE, "\tpop\tar0\n"); \
1344 fprintf (FILE, "\tpop\tar2\n"); \
1348 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1350 fprintf (FILE, "\tpush\tst\n"); \
1351 fprintf (FILE, "\tpush\tar2\n"); \
1352 fprintf (FILE, "\tcall\t___bb_trace_ret\n"); \
1353 fprintf (FILE, "\tpop\tar2\n"); \
1354 fprintf (FILE, "\tpop\tst\n"); \
1357 #define MACHINE_STATE_SAVE(ID) \
1368 asm(" .if .BIGMODEL"); \
1377 asm(" .if .tms320C40"); \
1381 asm(" pushf r10"); \
1383 asm(" pushf r11"); \
1386 #define MACHINE_STATE_RESTORE(ID) \
1387 asm(" .if .tms320C40"); \
1401 asm(" .if .BIGMODEL"); \
1415 /* Implicit Calls to Library Routines */
1417 #define MULQI3_LIBCALL "__mulqi3"
1418 #define DIVQI3_LIBCALL "__divqi3"
1419 #define UDIVQI3_LIBCALL "__udivqi3"
1420 #define MODQI3_LIBCALL "__modqi3"
1421 #define UMODQI3_LIBCALL "__umodqi3"
1423 #define DIVQF3_LIBCALL "__divqf3"
1425 #define MULHF3_LIBCALL "__mulhf3"
1426 #define DIVHF3_LIBCALL "__divhf3"
1428 #define MULHI3_LIBCALL "__mulhi3"
1429 #define SMULHI3_LIBCALL "__smulhi3_high"
1430 #define UMULHI3_LIBCALL "__umulhi3_high"
1431 #define DIVHI3_LIBCALL "__divhi3"
1432 #define UDIVHI3_LIBCALL "__udivhi3"
1433 #define MODHI3_LIBCALL "__modhi3"
1434 #define UMODHI3_LIBCALL "__umodhi3"
1436 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1437 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1438 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1439 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1441 #define FLOATHIHF2_LIBCALL "__floathihf2"
1442 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1443 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1444 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1446 #define FFS_LIBCALL "__ffs"
1449 #define INIT_TARGET_OPTABS \
1451 smul_optab->handlers[(int) QImode].libfunc \
1452 = init_one_libfunc (MULQI3_LIBCALL); \
1453 sdiv_optab->handlers[(int) QImode].libfunc \
1454 = init_one_libfunc (DIVQI3_LIBCALL); \
1455 udiv_optab->handlers[(int) QImode].libfunc \
1456 = init_one_libfunc (UDIVQI3_LIBCALL); \
1457 smod_optab->handlers[(int) QImode].libfunc \
1458 = init_one_libfunc (MODQI3_LIBCALL); \
1459 umod_optab->handlers[(int) QImode].libfunc \
1460 = init_one_libfunc (UMODQI3_LIBCALL); \
1461 flodiv_optab->handlers[(int) QFmode].libfunc \
1462 = init_one_libfunc (DIVQF3_LIBCALL); \
1463 smul_optab->handlers[(int) HFmode].libfunc \
1464 = init_one_libfunc (MULHF3_LIBCALL); \
1465 flodiv_optab->handlers[(int) HFmode].libfunc \
1466 = init_one_libfunc (DIVHF3_LIBCALL); \
1467 smul_optab->handlers[(int) HImode].libfunc \
1468 = init_one_libfunc (MULHI3_LIBCALL); \
1469 sdiv_optab->handlers[(int) HImode].libfunc \
1470 = init_one_libfunc (DIVHI3_LIBCALL); \
1471 udiv_optab->handlers[(int) HImode].libfunc \
1472 = init_one_libfunc (UDIVHI3_LIBCALL); \
1473 smod_optab->handlers[(int) HImode].libfunc \
1474 = init_one_libfunc (MODHI3_LIBCALL); \
1475 umod_optab->handlers[(int) HImode].libfunc \
1476 = init_one_libfunc (UMODHI3_LIBCALL); \
1477 ffs_optab->handlers[(int) QImode].libfunc \
1478 = init_one_libfunc (FFS_LIBCALL); \
1481 #define TARGET_MEM_FUNCTIONS
1483 /* Add any extra modes needed to represent the condition code.
1485 On the C4x, we have a "no-overflow" mode which is used when an ADD,
1486 SUB, NEG, or MPY insn is used to set the condition code. This is
1487 to prevent the combiner from optimising away a following CMP of the
1488 result with zero when a signed conditional branch or load insn
1491 The problem is a subtle one and deals with the manner in which the
1492 negative condition (N) flag is used on the C4x. This flag does not
1493 reflect the status of the actual result but of the ideal result had
1494 no overflow occured (when considering signed operands).
1496 For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
1497 the flags reflect the untruncated result, not the actual result.
1498 While the actual result is less than zero, the N flag is not set
1499 since the ideal result of the addition without truncation would
1502 Note that the while the N flag is handled differently to most other
1503 architectures, the use of it is self consistent and is not the
1504 cause of the problem.
1506 Logical operations set the N flag to the MSB of the result so if
1507 the result is negative, N is 1. However, integer and floating
1508 point operations set the N flag to be the MSB of the result
1509 exclusive ored with the overflow (V) flag. Thus if an overflow
1510 occurs and the result does not have the MSB set (i.e., the result
1511 looks like a positive number), the N flag is set. Conversely, if
1512 an overflow occurs and the MSB of the result is set, N is set to 0.
1513 Thus the N flag represents the sign of the result if it could have
1514 been stored without overflow but does not represent the apparent
1515 sign of the result. Note that most architectures set the N flag to
1516 be the MSB of the result.
1518 The C4x approach to setting the N flag simplifies signed
1519 conditional branches and loads which only have to test the state of
1520 the N flag, whereas most architectures have to look at both the N
1521 and V flags. The disadvantage is that there is no flag giving the
1522 status of the sign bit of the operation. However, there are no
1523 conditional load or branch instructions that make use of this
1524 feature (e.g., BMI---branch minus) instruction. Note that BN and
1525 BLT are identical in the C4x.
1527 To handle the problem where the N flag is set differently whenever
1528 there is an overflow we use a different CC mode, CC_NOOVmode which
1529 says that the CC reflects the comparison of the result against zero
1530 if no overflow occured.
1534 [(set (reg:CC_NOOV 21)
1535 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
1536 (match_operand:QI 2 "src_operand" ""))
1538 (set (match_operand:QI 0 "ext_reg_operand" "")
1539 (minus:QI (match_dup 1)
1542 Note that there is no problem for insns that don't return a result
1543 like CMP, since the CC reflects the effect of operation.
1545 An example of a potential problem is when GCC
1546 converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
1547 to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
1548 to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
1550 Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
1551 C4x sets the N flag since the result without overflow would have
1552 been 0xffffffff when treating the operands as signed integers.
1553 Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
1554 flag but (GE (0x00000001)) does not set the N flag.
1556 The upshot is that we can not use signed branch and conditional
1557 load instructions after an add, subtract, neg, abs or multiply.
1558 We must emit a compare insn to check the result against 0. */
1560 #define EXTRA_CC_MODES CC(CC_NOOVmode, "CC_NOOV")
1562 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1564 CCmode should be used when no special processing is needed. */
1565 #define SELECT_CC_MODE(OP,X,Y) \
1566 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1567 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1568 || GET_MODE (X) == ABS \
1569 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1570 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1571 || GET_MODE (Y) == ABS) \
1572 ? CC_NOOVmode : CCmode)
1574 /* Addressing Modes */
1576 #define HAVE_POST_INCREMENT 1
1577 #define HAVE_PRE_INCREMENT 1
1578 #define HAVE_POST_DECREMENT 1
1579 #define HAVE_PRE_DECREMENT 1
1580 #define HAVE_PRE_MODIFY_REG 1
1581 #define HAVE_POST_MODIFY_REG 1
1582 #define HAVE_PRE_MODIFY_DISP 1
1583 #define HAVE_POST_MODIFY_DISP 1
1585 /* The number of insns that can be packed into a single opcode. */
1586 #define PACK_INSNS 2
1588 /* Recognize any constant value that is a valid address.
1589 We could allow arbitrary constant addresses in the large memory
1590 model but for the small memory model we can only accept addresses
1591 within the data page. I suppose we could also allow
1592 CONST PLUS SYMBOL_REF. */
1593 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1595 /* Maximum number of registers that can appear in a valid memory
1597 #define MAX_REGS_PER_ADDRESS 2
1599 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1600 and check its validity for a certain class.
1601 We have two alternate definitions for each of them.
1602 The usual definition accepts all pseudo regs; the other rejects
1603 them unless they have been allocated suitable hard regs.
1604 The symbol REG_OK_STRICT causes the latter definition to be used.
1606 Most source files want to accept pseudo regs in the hope that
1607 they will get allocated to the class that the insn wants them to be in.
1608 Source files for reload pass need to be strict.
1609 After reload, it makes no difference, since pseudo regs have
1610 been eliminated by then. */
1612 #ifndef REG_OK_STRICT
1614 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1616 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1618 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1620 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1622 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1624 if (c4x_check_legit_addr (MODE, X, 0)) \
1630 /* Nonzero if X is a hard reg that can be used as an index. */
1632 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1634 /* Nonzero if X is a hard reg that can be used as a base reg. */
1636 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1638 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1640 if (c4x_check_legit_addr (MODE, X, 1)) \
1646 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1649 new = c4x_legitimize_address (X, MODE); \
1650 if (new != NULL_RTX) \
1657 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1660 new = c4x_legitimize_reload_address (X, MODE, insn); \
1661 if (new != NULL_RTX) \
1664 /* We do not have to call push_reload because we do not require \
1665 any more reloads. */ \
1671 /* No mode-dependent addresses on the C4x are autoincrements. */
1673 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1674 if (GET_CODE (ADDR) == PRE_DEC \
1675 || GET_CODE (ADDR) == POST_DEC \
1676 || GET_CODE (ADDR) == PRE_INC \
1677 || GET_CODE (ADDR) == POST_INC \
1678 || GET_CODE (ADDR) == POST_MODIFY \
1679 || GET_CODE (ADDR) == PRE_MODIFY) \
1683 /* Nonzero if the constant value X is a legitimate general operand.
1684 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1686 The C4x can only load 16-bit immediate values, so we only allow a
1687 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1688 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1689 model) so that the symbols will be forced into the constant pool.
1690 On second thoughts, let's do this with the move expanders since
1691 the alias analysis has trouble if we force constant addresses
1695 #define LEGITIMATE_CONSTANT_P(X) \
1696 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1697 || (GET_CODE (X) == CONST_INT) \
1698 || (GET_CODE (X) == SYMBOL_REF) \
1699 || (GET_CODE (X) == LABEL_REF) \
1700 || (GET_CODE (X) == CONST) \
1701 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1702 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1704 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1706 /* Define this macro if references to a symbol must be treated
1707 differently depending on something about the variable or
1708 function named by the symbol (such as what section it is in).
1710 The macro definition, if any, is executed immediately after the
1711 rtl for DECL or other node is created.
1712 The value of the rtl will be a `mem' whose address is a
1715 The usual thing for this macro to do is to a flag in the
1716 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1717 name string in the `symbol_ref' (if one bit is not enough
1720 On the C4x we use this to indicate if a symbol is in text or
1723 #define ENCODE_SECTION_INFO(DECL) c4x_encode_section_info (DECL);
1725 /* Descripting Relative Cost of Operations */
1727 /* Provide the costs of a rtl expression. This is in the body of a
1730 Note that we return, rather than break so that rtx_cost doesn't
1731 include CONST_COSTS otherwise expand_mult will think that it is
1732 cheaper to synthesise a multiply rather than to use a multiply
1733 instruction. I think this is because the algorithm synth_mult
1734 doesn't take into account the loading of the operands, whereas the
1735 calculation of mult_cost does.
1739 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1748 return COSTS_N_INSNS (1); \
1750 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1751 || TARGET_MPYI ? 1 : 14); \
1756 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1759 /* Compute the cost of computing a constant rtl expression RTX
1760 whose rtx-code is CODE. The body of this macro is a portion
1761 of a switch statement. If the code is computed here,
1762 return it with a return statement. Otherwise, break from the switch.
1764 An insn is assumed to cost 4 units.
1765 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1767 Some small integers are effectively free for the C40. We should
1768 also consider if we are using the small memory model. With
1769 the big memory model we require an extra insn for a constant
1772 This is used by expand_binop to decide whether to force a constant
1773 into a register. If the cost is greater than 2 and the constant
1774 is used within a short loop, it gets forced into a register.
1775 Ideally, there should be some weighting as to how mnay times it is used
1778 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1780 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1781 || (C) == IOR || (C) == XOR)
1783 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1785 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1787 if (c4x_J_constant (RTX)) \
1790 && OUTER_CODE == AND \
1791 && GET_CODE (RTX) == CONST_INT \
1792 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1795 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1796 && GET_CODE (RTX) == CONST_INT \
1797 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1799 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1801 if (LOGICAL_CODE_P (OUTER_CODE) \
1802 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1808 case CONST_DOUBLE: \
1809 if (c4x_H_constant (RTX)) \
1811 if (GET_MODE (RTX) == QFmode) \
1816 /* Compute the cost of an address. This is meant to approximate the size
1817 and/or execution delay of an insn using that address. If the cost is
1818 approximated by the RTL complexity, including CONST_COSTS above, as
1819 is usually the case for CISC machines, this macro should not be defined.
1820 For aggressively RISCy machines, only one insn format is allowed, so
1821 this macro should be a constant. The value of this macro only matters
1822 for valid addresses. We handle the most common address without
1823 a call to c4x_address_cost. */
1825 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1827 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1828 if (REG_P (OP1) && ! REG_P (OP0)) \
1830 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1831 CODE = swap_condition (CODE); \
1834 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1835 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1836 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1837 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1838 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1840 /* Compute extra cost of moving data between one register class
1843 #define REGISTER_MOVE_COST(FROM, TO) 2
1845 /* Memory move cost is same as fast register move. Maybe this should
1848 #define MEMORY_MOVE_COST(M,C,I) 4
1850 /* Branches are kind of expensive (even with delayed branching) so
1851 make their cost higher. */
1853 #define BRANCH_COST 8
1855 /* Adjust the cost of dependencies. */
1857 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1858 (COST) = c4x_adjust_cost (INSN, LINK, DEP, COST)
1860 #define WORD_REGISTER_OPERATIONS
1862 /* Dividing the Output into Sections. */
1864 #define TEXT_SECTION_ASM_OP "\t.text"
1866 #define DATA_SECTION_ASM_OP "\t.data"
1868 #define USE_CONST_SECTION 1
1870 #define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
1872 /* Do not use .init section so __main will be called on startup. This will
1873 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1876 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1879 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1881 /* Support const sections and the ctors and dtors sections for g++.
1882 Note that there appears to be two different ways to support const
1883 sections at the moment. You can either #define the symbol
1884 READONLY_DATA_SECTION (giving it some code which switches to the
1885 readonly data section) or else you can #define the symbols
1886 EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
1887 SELECT_RTX_SECTION. We do both here just to be on the safe side. */
1889 /* Define a few machine-specific details of the implementation of
1892 The __CTORS_LIST__ goes in the .ctors section. Define CTOR_LIST_BEGIN
1893 and CTOR_LIST_END to contribute to the .ctors section an instruction to
1894 push a word containing 0 (or some equivalent of that).
1896 Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */
1898 #define CTORS_SECTION_ASM_OP "\t.sect\t\".ctors\""
1899 #define DTORS_SECTION_ASM_OP "\t.sect\t\".dtors\""
1901 /* Constructor list on stack is in reverse order. Go to the end of the
1902 list and go backwards to call constructors in the right order. */
1904 #define DO_GLOBAL_CTORS_BODY \
1906 extern func_ptr __CTOR_LIST__[]; \
1907 func_ptr *p, *beg = __CTOR_LIST__ + 1; \
1908 for (p = beg; *p ; p++) ; \
1913 #undef EXTRA_SECTIONS
1914 #define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
1916 #undef EXTRA_SECTION_FUNCTIONS
1917 #define EXTRA_SECTION_FUNCTIONS \
1918 CONST_SECTION_FUNCTION \
1919 INIT_SECTION_FUNCTION \
1920 FINI_SECTION_FUNCTION \
1921 CTORS_SECTION_FUNCTION \
1922 DTORS_SECTION_FUNCTION
1924 #define INIT_SECTION_FUNCTION \
1928 if (in_section != in_init) \
1930 fprintf (asm_out_file, ";\t.init\n"); \
1931 in_section = in_init; \
1935 #define FINI_SECTION_FUNCTION \
1939 if (in_section != in_fini) \
1941 fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \
1942 in_section = in_fini; \
1946 #define READONLY_DATA_SECTION() const_section ()
1948 #define CONST_SECTION_FUNCTION \
1952 if (! USE_CONST_SECTION) \
1954 else if (in_section != in_const) \
1956 fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
1957 in_section = in_const; \
1961 #define ASM_STABS_OP "\t.stabs"
1963 /* The ctors and dtors sections are not normally put into use
1964 by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
1965 but it can't hurt to define these macros for whatever systems use them. */
1967 #define CTORS_SECTION_FUNCTION \
1971 if (in_section != in_ctors) \
1973 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1974 in_section = in_ctors; \
1978 #define DTORS_SECTION_FUNCTION \
1982 if (in_section != in_dtors) \
1984 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1985 in_section = in_dtors; \
1989 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1990 fprintf (FILE, "\t.sect\t\"%s\"\n", NAME);
1992 /* This is machine-dependent because it needs to push something
1995 /* A C statement (sans semicolon) to output an element in the table of
1996 global constructors. */
1997 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
2000 fprintf (FILE, "\t.word\t "); \
2001 assemble_name (FILE, NAME); \
2002 fprintf (FILE, "\n"); \
2005 /* A C statement (sans semicolon) to output an element in the table of
2006 global destructors. */
2007 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
2010 fprintf (FILE, "\t.word\t "); \
2011 assemble_name (FILE, NAME); \
2012 fprintf (FILE, "\n"); \
2015 /* A C statement or statements to switch to the appropriate
2016 section for output of DECL. DECL is either a `VAR_DECL' node
2017 or a constant of some sort. RELOC indicates whether forming
2018 the initial value of DECL requires link-time relocations. */
2020 #define SELECT_SECTION(DECL, RELOC) \
2022 if (TREE_CODE (DECL) == STRING_CST) \
2024 if (! flag_writable_strings) \
2029 else if (TREE_CODE (DECL) == VAR_DECL) \
2031 if ((0 && RELOC) /* should be (flag_pic && RELOC) */ \
2032 || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
2033 || ! DECL_INITIAL (DECL) \
2034 || (DECL_INITIAL (DECL) != error_mark_node \
2035 && ! TREE_CONSTANT (DECL_INITIAL (DECL)))) \
2044 /* A C statement or statements to switch to the appropriate
2045 section for output of RTX in mode MODE. RTX is some kind
2046 of constant in RTL. The argument MODE is redundant except
2047 in the case of a `const_int' rtx. Currently, these always
2048 go into the const section. */
2050 #define SELECT_RTX_SECTION(MODE, RTX) const_section()
2053 /* Overall Framework of an Assembler File */
2055 #define ASM_FILE_START(FILE) \
2057 int dspversion = 0; \
2058 if (TARGET_C30) dspversion = 30; \
2059 if (TARGET_C31) dspversion = 31; \
2060 if (TARGET_C32) dspversion = 32; \
2061 if (TARGET_C40) dspversion = 40; \
2062 if (TARGET_C44) dspversion = 44; \
2063 fprintf (FILE, "\t.version\t%d\n", dspversion); \
2064 fprintf (FILE, "\t.file\t"); \
2068 char *after_dir = main_input_filename; \
2069 for (p = main_input_filename; *p; p++) \
2071 after_dir = p + 1; \
2072 output_quoted_string (FILE, after_dir); \
2075 output_quoted_string (FILE, main_input_filename); \
2076 fprintf (FILE, "\n"); \
2079 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n")
2081 /* We need to have a data section we can identify so that we can set
2082 the DP register back to a data pointer in the small memory model.
2083 This is only required for ISRs if we are paranoid that someone
2084 may have quietly changed this register on the sly. */
2086 #define ASM_IDENTIFY_GCC(FILE) \
2087 if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE); \
2088 fputs ("\t.data\ndata_sec:\n", FILE);
2090 #define ASM_COMMENT_START ";"
2092 #define ASM_APP_ON ""
2093 #define ASM_APP_OFF ""
2095 /* Output float/double constants QFmode. */
2097 #define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE) \
2101 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2102 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2103 if (sizeof (int) == sizeof (long)) \
2104 fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
2106 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
2109 /* Output long double constants HFmode.
2110 The first word contains the exponent and first part of the mantissa
2111 in the same manner as QFmode. The second word contains the full
2112 mantissa. We should ensure that the two words are allocated within
2113 the same page for the large memory model since we only output a single
2114 LDP instruction. FIXME. The simplest solution probably is to output
2115 a LDP for each load. */
2117 #define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE) \
2121 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2122 REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str); \
2123 l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff); \
2124 if (sizeof (int) == sizeof (long)) \
2125 fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
2128 fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
2132 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
2134 fprintf (FILE, "\t.word\t"); \
2135 output_addr_const (FILE, VALUE); \
2136 if (GET_CODE (VALUE) != SYMBOL_REF) \
2137 fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE)); \
2139 fputc ('\n', FILE); \
2142 #define ASM_OUTPUT_BYTE(FILE, VALUE) \
2143 fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
2145 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
2147 #define ASM_OPEN_PAREN "("
2148 #define ASM_CLOSE_PAREN ")"
2151 /* Output and Generation of Labels */
2153 #define NO_DOT_IN_LABEL /* Only required for TI format */
2155 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2156 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0);
2158 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
2160 fprintf (FILE, "\t.global\t"); \
2161 assemble_name (FILE, NAME); \
2162 fputs ("\n", FILE); \
2165 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2167 fprintf (FILE, "\t.ref\t"); \
2168 assemble_name (FILE, NAME); \
2169 fputc ('\n', FILE); \
2172 /* A C statement to output on FILE an assembler pseudo-op to
2173 declare a library function named external.
2174 (Only needed to keep asm30 happy for ___divqf3 etc.) */
2176 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
2178 fprintf (FILE, "\t.ref\t"); \
2179 assemble_name (FILE, XSTR (FUN, 0)); \
2180 fprintf (FILE, "\n"); \
2183 /* The prefix to add to user-visible assembler symbols. */
2185 #define USER_LABEL_PREFIX "_"
2187 /* This is how to output an internal numbered label where
2188 PREFIX is the class of label and NUM is the number within the class. */
2190 #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
2191 asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2193 /* This is how to store into the string LABEL
2194 the symbol_ref name of an internal numbered label where
2195 PREFIX is the class of label and NUM is the number within the class.
2196 This is suitable for output with `assemble_name'. */
2198 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
2199 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
2201 /* Store in OUTPUT a string (made with alloca) containing
2202 an assembler-name for a local static variable named NAME.
2203 LABELNO is an integer which is different for each call. */
2205 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2206 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2207 sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO)))
2210 /* Output of Dispatch Tables */
2212 /* This is how to output an element of a case-vector that is absolute. */
2214 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2215 fprintf (FILE, "\t.long\tL%d\n", VALUE);
2217 /* This is how to output an element of a case-vector that is relative. */
2219 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2220 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
2223 #define SIZE_TYPE "unsigned int"
2226 #define PTRDIFF_TYPE "int"
2229 #define WCHAR_TYPE "long int"
2231 #undef WCHAR_TYPE_SIZE
2232 #define WCHAR_TYPE_SIZE 32
2234 #define INT_TYPE_SIZE 32
2235 #define LONG_LONG_TYPE_SIZE 64
2236 #define FLOAT_TYPE_SIZE 32
2237 #define DOUBLE_TYPE_SIZE 32
2238 #define LONG_DOUBLE_TYPE_SIZE 64 /* actually only 40 */
2240 /* Allow #sccs in preprocessor. */
2242 #define SCCS_DIRECTIVE
2244 /* Output #ident as a .ident. */
2246 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2247 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
2249 #define CPP_PREDEFINES ""
2251 /* Output of Uninitialized Variables */
2253 /* This says how to output an assembler line to define a local
2254 uninitialized variable. */
2256 #undef ASM_OUTPUT_LOCAL
2257 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2258 ( fputs ("\t.bss\t", FILE), \
2259 assemble_name (FILE, (NAME)), \
2260 fprintf (FILE, ",%u\n", (ROUNDED)))
2262 /* This says how to output an assembler line to define a global
2263 uninitialized variable. */
2265 #undef ASM_OUTPUT_COMMON
2266 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2267 ( fputs ("\t.globl\t", FILE), \
2268 assemble_name (FILE, (NAME)), \
2269 fputs ("\n\t.bss\t", FILE), \
2270 assemble_name (FILE, (NAME)), \
2271 fprintf (FILE, ",%u\n", (ROUNDED)))
2273 /* Macros Controlling Initialization Routines */
2275 #define OBJECT_FORMAT_COFF
2276 #define REAL_NM_FILE_NAME "c4x-nm"
2278 /* Output of Assembler Instructions */
2280 /* Register names when used for integer modes. */
2282 #define REGISTER_NAMES \
2284 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2285 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2286 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2287 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
2290 /* Alternate register names when used for floating point modes. */
2292 #define FLOAT_REGISTER_NAMES \
2294 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2295 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
2296 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
2297 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
2300 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
2302 /* Determine which codes are valid without a following integer. These must
2303 not be alphabetic. */
2305 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
2307 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
2309 /* Define this macro if you want to implement any pragmas. If defined, it
2310 should be a C expression to be executed when #pragma is seen. The
2311 argument STREAM is the stdio input stream from which the source
2312 text can be read. CH is the first character after the #pragma. The
2313 result of the expression is the terminating character found
2314 (newline or EOF). */
2315 #define HANDLE_PRAGMA(GETC, UNGETC, NAME) \
2316 c4x_handle_pragma (GETC, UNGETC, NAME)
2318 #define SET_DEFAULT_DECL_ATTRIBUTES(DECL, ATTRIBUTES) \
2319 c4x_set_default_attributes (DECL, &ATTRIBUTES)
2321 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2322 (c4x_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2324 /* Assembler Commands for Alignment */
2326 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
2328 for (; c > 0; --c) \
2329 fprintf (FILE,"\t.word\t0\n"); \
2332 #define ASM_NO_SKIP_IN_TEXT 1
2334 /* I'm not sure about this one. FIXME. */
2336 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
2338 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
2341 /* Macros for SDB and DWARF Output (use .sdef instead of .def
2342 to avoid conflict with TI's use of .def) */
2344 #define SDB_DELIM "\n"
2345 #define SDB_DEBUGGING_INFO
2347 #define PUT_SDB_DEF(A) \
2348 do { fprintf (asm_out_file, "\t.sdef\t"); \
2349 ASM_OUTPUT_LABELREF (asm_out_file, A); \
2350 fprintf (asm_out_file, SDB_DELIM); } while (0)
2352 #define PUT_SDB_PLAIN_DEF(A) \
2353 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
2355 #define PUT_SDB_BLOCK_START(LINE) \
2356 fprintf (asm_out_file, \
2357 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2358 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2360 #define PUT_SDB_BLOCK_END(LINE) \
2361 fprintf (asm_out_file, \
2362 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
2363 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2365 #define PUT_SDB_FUNCTION_START(LINE) \
2366 fprintf (asm_out_file, \
2367 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2368 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2370 #define PUT_SDB_FUNCTION_END(LINE) \
2371 fprintf (asm_out_file, \
2372 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
2373 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
2375 #define PUT_SDB_EPILOGUE_END(NAME) \
2376 do { fprintf (asm_out_file, "\t.sdef\t"); \
2377 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
2378 fprintf (asm_out_file, \
2379 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
2380 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
2383 /* Define results of standard character escape sequences. */
2385 #define TARGET_BELL 007
2386 #define TARGET_BS 010
2387 #define TARGET_TAB 011
2388 #define TARGET_NEWLINE 012
2389 #define TARGET_VT 013
2390 #define TARGET_FF 014
2391 #define TARGET_CR 015
2393 /* This is the kind of divide that is easiest to do in the general case. */
2395 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2397 /* Define this as 1 if `char' should by default be signed; else as 0. */
2399 #define DEFAULT_SIGNED_CHAR 1
2401 /* A function address in a call instruction is a byte address (for
2402 indexing purposes) so give the MEM rtx a byte's mode. */
2404 #define FUNCTION_MODE QImode
2406 #define SLOW_BYTE_ACCESS 0
2408 /* Specify the machine mode that pointers have. After generation of
2409 RTL, the compiler makes no further distinction between pointers and
2410 any other objects of this machine mode. */
2412 #define Pmode QImode
2414 /* On the C4x we can write the following code. We have to clear the cache
2415 every time we execute it because the data in the stack could change.
2428 On the c3x this is a bit more difficult. We have to write self
2429 modifying code here. So we have to clear the cache every time
2430 we execute it because the data in the stack could change.
2432 ldiu TOP_OF_FUNCTION,ar1
2434 or BOTTOM_OF_FUNCTION,ar1
2435 ldiu TOP_OF_STATIC,ar0
2438 or BOTTOM_OF_STATIC,ar0
2443 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
2445 #define TRAMPOLINE_TEMPLATE(FILE) \
2449 asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
2450 asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
2451 asm_fprintf (FILE, "\tor\t0,ar1\n"); \
2452 asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
2453 asm_fprintf (FILE, "\tbud\tar1\n"); \
2454 asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
2455 asm_fprintf (FILE, "\tor\t0,ar0\n"); \
2456 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2460 asm_fprintf (FILE, "\tlaj\t$+4\n"); \
2461 asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
2462 asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
2463 asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
2464 asm_fprintf (FILE, "\tbud\tar1\n"); \
2465 asm_fprintf (FILE, "\tnop\n"); \
2466 asm_fprintf (FILE, "\tnop\n"); \
2467 asm_fprintf (FILE, "\tor\t1000h,st\n"); \
2468 asm_fprintf (FILE, "\t.word\t0\n"); \
2469 asm_fprintf (FILE, "\t.word\t0\n"); \
2473 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2478 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2479 size_int (16), 0, 1); \
2480 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2481 gen_rtx (CONST_INT, VOIDmode, 0x5069), \
2482 size_int (16), 0, 1); \
2483 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2484 emit_move_insn (gen_rtx (MEM, QImode, \
2485 plus_constant (tramp, 0)), tmp1); \
2486 tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
2488 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2489 gen_rtx (CONST_INT, VOIDmode, 0x1069), \
2490 size_int (16), 0, 1); \
2491 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2492 emit_move_insn (gen_rtx (MEM, QImode, \
2493 plus_constant (tramp, 2)), tmp1); \
2494 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2495 size_int (16), 0, 1); \
2496 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2497 gen_rtx (CONST_INT, VOIDmode, 0x5068), \
2498 size_int (16), 0, 1); \
2499 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2500 emit_move_insn (gen_rtx (MEM, QImode, \
2501 plus_constant (tramp, 3)), tmp1); \
2502 tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
2504 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2505 gen_rtx (CONST_INT, VOIDmode, 0x1068), \
2506 size_int (16), 0, 1); \
2507 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2508 emit_move_insn (gen_rtx (MEM, QImode, \
2509 plus_constant (tramp, 6)), tmp1); \
2513 emit_move_insn (gen_rtx (MEM, QImode, \
2514 plus_constant (TRAMP, 8)), FNADDR); \
2515 emit_move_insn (gen_rtx (MEM, QImode, \
2516 plus_constant (TRAMP, 9)), CXT); \
2520 /* Specify the machine mode that this machine uses for the index in
2521 the tablejump instruction. */
2523 #define CASE_VECTOR_MODE Pmode
2525 /* Max number of (32-bit) bytes we can move from memory to memory
2526 in one reasonably fast instruction. */
2530 /* MOVE_RATIO is the number of move instructions that is better than a
2533 #define MOVE_RATIO 2 /* Default value */
2535 #define BSS_SECTION_ASM_OP ".bss"
2537 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2538 asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2540 /* This is how to output an insn to pop a register from the stack.
2541 It need not be very fast code. */
2543 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2544 asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2546 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2547 is done just by pretending it is already truncated. */
2549 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2551 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2553 /* We need to use direct addressing for large constants and addresses
2554 that cannot fit within an instruction. We must check for these
2555 after after the final jump optimisation pass, since this may
2556 introduce a local_move insn for a SYMBOL_REF. This pass
2557 must come before delayed branch slot filling since it can generate
2558 additional instructions. */
2560 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2562 #define DBR_OUTPUT_SEQEND(FILE) \
2563 if (final_sequence != NULL_RTX) \
2566 int laj = GET_CODE (XVECEXP (final_sequence, 0, 0)) == CALL_INSN; \
2568 count = dbr_sequence_length(); \
2569 while (count < (laj ? 2 : 3)) \
2571 fputs("\tnop\n", FILE); \
2575 fputs("\tpush\tr11\n", FILE); \
2578 #define NO_FUNCTION_CSE
2580 /* We don't want a leading tab. */
2582 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2584 /* Define the codes that are matched by predicates in c4x.c. */
2586 #define PREDICATE_CODES \
2587 {"fp_zero_operand", {CONST_DOUBLE}}, \
2588 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2589 {"stik_const_operand", {CONST_INT}}, \
2590 {"not_const_operand", {CONST_INT}}, \
2591 {"reg_operand", {REG, SUBREG}}, \
2592 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2593 {"r0r1_reg_operand", {REG, SUBREG}}, \
2594 {"r2r3_reg_operand", {REG, SUBREG}}, \
2595 {"ext_low_reg_operand", {REG, SUBREG}}, \
2596 {"ext_reg_operand", {REG, SUBREG}}, \
2597 {"std_reg_operand", {REG, SUBREG}}, \
2598 {"addr_reg_operand", {REG, SUBREG}}, \
2599 {"index_reg_operand", {REG, SUBREG}}, \
2600 {"dp_reg_operand", {REG}}, \
2601 {"sp_reg_operand", {REG}}, \
2602 {"st_reg_operand", {REG}}, \
2603 {"rc_reg_operand", {REG}}, \
2604 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2605 {"dst_operand", {SUBREG, REG, MEM}}, \
2606 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2607 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2608 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2609 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2610 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2611 {"par_ind_operand", {MEM}}, \
2612 {"parallel_operand", {SUBREG, REG, MEM}}, \
2613 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2614 {"mem_operand", {MEM}},
2617 /* Variables in c4x.c */
2619 extern enum reg_class c4x_regclass_map[];/* smallest class containing REGNO */
2620 extern enum machine_mode c4x_caller_save_map[];
2622 extern struct rtx_def *c4x_compare_op0; /* operand 0 for comparisons */
2623 extern struct rtx_def *c4x_compare_op1; /* operand 1 for comparisons */
2625 extern int c4x_rpts_cycles; /* max cycles for RPTS */
2626 extern int c4x_cpu_version; /* cpu version C30/31/32/40/44 */
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