1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-codes.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
41 #include "target-def.h"
47 #include "integrate.h"
49 #include "langhooks.h"
50 #include "bfin-protos.h"
52 #include "tm-constrs.h"
54 #include "basic-block.h"
55 #include "cfglayout.h"
59 /* A C structure for machine-specific, per-function data.
60 This is added to the cfun structure. */
61 struct machine_function GTY(())
63 int has_hardware_loops;
66 /* Test and compare insns in bfin.md store the information needed to
67 generate branch and scc insns here. */
68 rtx bfin_compare_op0, bfin_compare_op1;
70 /* RTX for condition code flag register and RETS register */
71 extern GTY(()) rtx bfin_cc_rtx;
72 extern GTY(()) rtx bfin_rets_rtx;
73 rtx bfin_cc_rtx, bfin_rets_rtx;
75 int max_arg_registers = 0;
77 /* Arrays used when emitting register names. */
78 const char *short_reg_names[] = SHORT_REGISTER_NAMES;
79 const char *high_reg_names[] = HIGH_REGISTER_NAMES;
80 const char *dregs_pair_names[] = DREGS_PAIR_NAMES;
81 const char *byte_reg_names[] = BYTE_REGISTER_NAMES;
83 static int arg_regs[] = FUNCTION_ARG_REGISTERS;
85 /* Nonzero if -mshared-library-id was given. */
86 static int bfin_lib_id_given;
88 /* Nonzero if -fschedule-insns2 was given. We override it and
89 call the scheduler ourselves during reorg. */
90 static int bfin_flag_schedule_insns2;
92 /* Determines whether we run variable tracking in machine dependent
94 static int bfin_flag_var_tracking;
97 bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
99 /* -msi-revision support. There are three special values:
100 -1 -msi-revision=none.
101 0xffff -msi-revision=any. */
102 int bfin_si_revision;
104 /* The workarounds enabled */
105 unsigned int bfin_workarounds = 0;
112 unsigned int workarounds;
115 struct bfin_cpu bfin_cpus[] =
117 {"bf522", BFIN_CPU_BF522, 0x0001,
118 WA_SPECULATIVE_LOADS | WA_RETS},
119 {"bf522", BFIN_CPU_BF522, 0x0000,
120 WA_SPECULATIVE_LOADS | WA_RETS},
122 {"bf523", BFIN_CPU_BF523, 0x0001,
123 WA_SPECULATIVE_LOADS | WA_RETS},
124 {"bf523", BFIN_CPU_BF523, 0x0000,
125 WA_SPECULATIVE_LOADS | WA_RETS},
127 {"bf524", BFIN_CPU_BF524, 0x0001,
128 WA_SPECULATIVE_LOADS | WA_RETS},
129 {"bf524", BFIN_CPU_BF524, 0x0000,
130 WA_SPECULATIVE_LOADS | WA_RETS},
132 {"bf525", BFIN_CPU_BF525, 0x0001,
133 WA_SPECULATIVE_LOADS | WA_RETS},
134 {"bf525", BFIN_CPU_BF525, 0x0000,
135 WA_SPECULATIVE_LOADS | WA_RETS},
137 {"bf526", BFIN_CPU_BF526, 0x0001,
138 WA_SPECULATIVE_LOADS | WA_RETS},
139 {"bf526", BFIN_CPU_BF526, 0x0000,
140 WA_SPECULATIVE_LOADS | WA_RETS},
142 {"bf527", BFIN_CPU_BF527, 0x0001,
143 WA_SPECULATIVE_LOADS | WA_RETS},
144 {"bf527", BFIN_CPU_BF527, 0x0000,
145 WA_SPECULATIVE_LOADS | WA_RETS},
147 {"bf531", BFIN_CPU_BF531, 0x0005,
148 WA_SPECULATIVE_LOADS | WA_RETS},
149 {"bf531", BFIN_CPU_BF531, 0x0004,
150 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
151 {"bf531", BFIN_CPU_BF531, 0x0003,
152 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
154 {"bf532", BFIN_CPU_BF532, 0x0005,
155 WA_SPECULATIVE_LOADS | WA_RETS},
156 {"bf532", BFIN_CPU_BF532, 0x0004,
157 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
158 {"bf532", BFIN_CPU_BF532, 0x0003,
159 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
161 {"bf533", BFIN_CPU_BF533, 0x0005,
162 WA_SPECULATIVE_LOADS | WA_RETS},
163 {"bf533", BFIN_CPU_BF533, 0x0004,
164 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
165 {"bf533", BFIN_CPU_BF533, 0x0003,
166 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
168 {"bf534", BFIN_CPU_BF534, 0x0003,
169 WA_SPECULATIVE_LOADS | WA_RETS},
170 {"bf534", BFIN_CPU_BF534, 0x0002,
171 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
172 {"bf534", BFIN_CPU_BF534, 0x0001,
173 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
175 {"bf536", BFIN_CPU_BF536, 0x0003,
176 WA_SPECULATIVE_LOADS | WA_RETS},
177 {"bf536", BFIN_CPU_BF536, 0x0002,
178 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
179 {"bf536", BFIN_CPU_BF536, 0x0001,
180 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
182 {"bf537", BFIN_CPU_BF537, 0x0003,
183 WA_SPECULATIVE_LOADS | WA_RETS},
184 {"bf537", BFIN_CPU_BF537, 0x0002,
185 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
186 {"bf537", BFIN_CPU_BF537, 0x0001,
187 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
189 {"bf538", BFIN_CPU_BF538, 0x0004,
190 WA_SPECULATIVE_LOADS | WA_RETS},
191 {"bf538", BFIN_CPU_BF538, 0x0003,
192 WA_SPECULATIVE_LOADS | WA_RETS},
193 {"bf538", BFIN_CPU_BF538, 0x0002,
194 WA_SPECULATIVE_LOADS | WA_RETS},
196 {"bf539", BFIN_CPU_BF539, 0x0004,
197 WA_SPECULATIVE_LOADS | WA_RETS},
198 {"bf539", BFIN_CPU_BF539, 0x0003,
199 WA_SPECULATIVE_LOADS | WA_RETS},
200 {"bf539", BFIN_CPU_BF539, 0x0002,
201 WA_SPECULATIVE_LOADS | WA_RETS},
203 {"bf542", BFIN_CPU_BF542, 0x0001,
204 WA_SPECULATIVE_LOADS | WA_RETS},
205 {"bf542", BFIN_CPU_BF542, 0x0000,
206 WA_SPECULATIVE_LOADS | WA_RETS},
208 {"bf544", BFIN_CPU_BF544, 0x0001,
209 WA_SPECULATIVE_LOADS | WA_RETS},
210 {"bf544", BFIN_CPU_BF544, 0x0000,
211 WA_SPECULATIVE_LOADS | WA_RETS},
213 {"bf547", BFIN_CPU_BF547, 0x0001,
214 WA_SPECULATIVE_LOADS | WA_RETS},
215 {"bf547", BFIN_CPU_BF547, 0x0000,
216 WA_SPECULATIVE_LOADS | WA_RETS},
218 {"bf548", BFIN_CPU_BF548, 0x0001,
219 WA_SPECULATIVE_LOADS | WA_RETS},
220 {"bf548", BFIN_CPU_BF548, 0x0000,
221 WA_SPECULATIVE_LOADS | WA_RETS},
223 {"bf549", BFIN_CPU_BF549, 0x0001,
224 WA_SPECULATIVE_LOADS | WA_RETS},
225 {"bf549", BFIN_CPU_BF549, 0x0000,
226 WA_SPECULATIVE_LOADS | WA_RETS},
228 {"bf561", BFIN_CPU_BF561, 0x0005, WA_RETS},
229 {"bf561", BFIN_CPU_BF561, 0x0003,
230 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
231 {"bf561", BFIN_CPU_BF561, 0x0002,
232 WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
237 int splitting_for_sched;
240 bfin_globalize_label (FILE *stream, const char *name)
242 fputs (".global ", stream);
243 assemble_name (stream, name);
249 output_file_start (void)
251 FILE *file = asm_out_file;
254 /* Variable tracking should be run after all optimizations which change order
255 of insns. It also needs a valid CFG. This can't be done in
256 override_options, because flag_var_tracking is finalized after
258 bfin_flag_var_tracking = flag_var_tracking;
259 flag_var_tracking = 0;
261 fprintf (file, ".file \"%s\";\n", input_filename);
263 for (i = 0; arg_regs[i] >= 0; i++)
265 max_arg_registers = i; /* how many arg reg used */
268 /* Called early in the compilation to conditionally modify
269 fixed_regs/call_used_regs. */
272 conditional_register_usage (void)
274 /* initialize condition code flag register rtx */
275 bfin_cc_rtx = gen_rtx_REG (BImode, REG_CC);
276 bfin_rets_rtx = gen_rtx_REG (Pmode, REG_RETS);
279 /* Examine machine-dependent attributes of function type FUNTYPE and return its
280 type. See the definition of E_FUNKIND. */
283 funkind (const_tree funtype)
285 tree attrs = TYPE_ATTRIBUTES (funtype);
286 if (lookup_attribute ("interrupt_handler", attrs))
287 return INTERRUPT_HANDLER;
288 else if (lookup_attribute ("exception_handler", attrs))
289 return EXCPT_HANDLER;
290 else if (lookup_attribute ("nmi_handler", attrs))
296 /* Legitimize PIC addresses. If the address is already position-independent,
297 we return ORIG. Newly generated position-independent addresses go into a
298 reg. This is REG if nonzero, otherwise we allocate register(s) as
299 necessary. PICREG is the register holding the pointer to the PIC offset
303 legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
308 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
313 if (TARGET_ID_SHARED_LIBRARY)
314 unspec = UNSPEC_MOVE_PIC;
315 else if (GET_CODE (addr) == SYMBOL_REF
316 && SYMBOL_REF_FUNCTION_P (addr))
317 unspec = UNSPEC_FUNCDESC_GOT17M4;
319 unspec = UNSPEC_MOVE_FDPIC;
323 gcc_assert (can_create_pseudo_p ());
324 reg = gen_reg_rtx (Pmode);
327 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), unspec);
328 new_rtx = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp));
330 emit_move_insn (reg, new_rtx);
331 if (picreg == pic_offset_table_rtx)
332 crtl->uses_pic_offset_table = 1;
336 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
340 if (GET_CODE (addr) == CONST)
342 addr = XEXP (addr, 0);
343 gcc_assert (GET_CODE (addr) == PLUS);
346 if (XEXP (addr, 0) == picreg)
351 gcc_assert (can_create_pseudo_p ());
352 reg = gen_reg_rtx (Pmode);
355 base = legitimize_pic_address (XEXP (addr, 0), reg, picreg);
356 addr = legitimize_pic_address (XEXP (addr, 1),
357 base == reg ? NULL_RTX : reg,
360 if (GET_CODE (addr) == CONST_INT)
362 gcc_assert (! reload_in_progress && ! reload_completed);
363 addr = force_reg (Pmode, addr);
366 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
368 base = gen_rtx_PLUS (Pmode, base, XEXP (addr, 0));
369 addr = XEXP (addr, 1);
372 return gen_rtx_PLUS (Pmode, base, addr);
378 /* Stack frame layout. */
380 /* For a given REGNO, determine whether it must be saved in the function
381 prologue. IS_INTHANDLER specifies whether we're generating a normal
382 prologue or an interrupt/exception one. */
384 must_save_p (bool is_inthandler, unsigned regno)
386 if (D_REGNO_P (regno))
388 bool is_eh_return_reg = false;
389 if (crtl->calls_eh_return)
394 unsigned test = EH_RETURN_DATA_REGNO (j);
395 if (test == INVALID_REGNUM)
398 is_eh_return_reg = true;
402 return (is_eh_return_reg
403 || (df_regs_ever_live_p (regno)
404 && !fixed_regs[regno]
405 && (is_inthandler || !call_used_regs[regno])));
407 else if (P_REGNO_P (regno))
409 return ((df_regs_ever_live_p (regno)
410 && !fixed_regs[regno]
411 && (is_inthandler || !call_used_regs[regno]))
413 && regno == PIC_OFFSET_TABLE_REGNUM
414 && (crtl->uses_pic_offset_table
415 || (TARGET_ID_SHARED_LIBRARY && !current_function_is_leaf))));
418 return ((is_inthandler || !call_used_regs[regno])
419 && (df_regs_ever_live_p (regno)
420 || (!leaf_function_p () && call_used_regs[regno])));
424 /* Compute the number of DREGS to save with a push_multiple operation.
425 This could include registers that aren't modified in the function,
426 since push_multiple only takes a range of registers.
427 If IS_INTHANDLER, then everything that is live must be saved, even
428 if normally call-clobbered.
429 If CONSECUTIVE, return the number of registers we can save in one
430 instruction with a push/pop multiple instruction. */
433 n_dregs_to_save (bool is_inthandler, bool consecutive)
438 for (i = REG_R7 + 1; i-- != REG_R0;)
440 if (must_save_p (is_inthandler, i))
442 else if (consecutive)
448 /* Like n_dregs_to_save, but compute number of PREGS to save. */
451 n_pregs_to_save (bool is_inthandler, bool consecutive)
456 for (i = REG_P5 + 1; i-- != REG_P0;)
457 if (must_save_p (is_inthandler, i))
459 else if (consecutive)
464 /* Determine if we are going to save the frame pointer in the prologue. */
467 must_save_fp_p (void)
469 return frame_pointer_needed || df_regs_ever_live_p (REG_FP);
473 stack_frame_needed_p (void)
475 /* EH return puts a new return address into the frame using an
476 address relative to the frame pointer. */
477 if (crtl->calls_eh_return)
479 return frame_pointer_needed;
482 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
483 must save all registers; this is used for interrupt handlers.
484 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
485 this for an interrupt (or exception) handler. */
488 expand_prologue_reg_save (rtx spreg, int saveall, bool is_inthandler)
490 rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg);
491 rtx predec = gen_rtx_MEM (SImode, predec1);
492 int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false);
493 int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false);
494 int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true);
495 int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true);
497 int total_consec = ndregs_consec + npregs_consec;
500 if (saveall || is_inthandler)
502 rtx insn = emit_move_insn (predec, gen_rtx_REG (SImode, REG_ASTAT));
503 RTX_FRAME_RELATED_P (insn) = 1;
506 if (total_consec != 0)
509 rtx val = GEN_INT (-total_consec * 4);
510 rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 2));
512 XVECEXP (pat, 0, 0) = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, val),
513 UNSPEC_PUSH_MULTIPLE);
514 XVECEXP (pat, 0, total_consec + 1) = gen_rtx_SET (VOIDmode, spreg,
518 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, total_consec + 1)) = 1;
519 d_to_save = ndregs_consec;
520 dregno = REG_R7 + 1 - ndregs_consec;
521 pregno = REG_P5 + 1 - npregs_consec;
522 for (i = 0; i < total_consec; i++)
524 rtx memref = gen_rtx_MEM (word_mode,
525 gen_rtx_PLUS (Pmode, spreg,
526 GEN_INT (- i * 4 - 4)));
530 subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode,
536 subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode,
539 XVECEXP (pat, 0, i + 1) = subpat;
540 RTX_FRAME_RELATED_P (subpat) = 1;
542 insn = emit_insn (pat);
543 RTX_FRAME_RELATED_P (insn) = 1;
546 for (dregno = REG_R0; ndregs != ndregs_consec; dregno++)
548 if (must_save_p (is_inthandler, dregno))
550 rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, dregno));
551 RTX_FRAME_RELATED_P (insn) = 1;
555 for (pregno = REG_P0; npregs != npregs_consec; pregno++)
557 if (must_save_p (is_inthandler, pregno))
559 rtx insn = emit_move_insn (predec, gen_rtx_REG (word_mode, pregno));
560 RTX_FRAME_RELATED_P (insn) = 1;
564 for (i = REG_P7 + 1; i < REG_CC; i++)
567 && (df_regs_ever_live_p (i)
568 || (!leaf_function_p () && call_used_regs[i]))))
571 if (i == REG_A0 || i == REG_A1)
572 insn = emit_move_insn (gen_rtx_MEM (PDImode, predec1),
573 gen_rtx_REG (PDImode, i));
575 insn = emit_move_insn (predec, gen_rtx_REG (SImode, i));
576 RTX_FRAME_RELATED_P (insn) = 1;
580 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
581 must save all registers; this is used for interrupt handlers.
582 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
583 this for an interrupt (or exception) handler. */
586 expand_epilogue_reg_restore (rtx spreg, bool saveall, bool is_inthandler)
588 rtx postinc1 = gen_rtx_POST_INC (SImode, spreg);
589 rtx postinc = gen_rtx_MEM (SImode, postinc1);
591 int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler, false);
592 int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler, false);
593 int ndregs_consec = saveall ? 8 : n_dregs_to_save (is_inthandler, true);
594 int npregs_consec = saveall ? 6 : n_pregs_to_save (is_inthandler, true);
595 int total_consec = ndregs_consec + npregs_consec;
599 /* A slightly crude technique to stop flow from trying to delete "dead"
601 MEM_VOLATILE_P (postinc) = 1;
603 for (i = REG_CC - 1; i > REG_P7; i--)
606 && (df_regs_ever_live_p (i)
607 || (!leaf_function_p () && call_used_regs[i]))))
609 if (i == REG_A0 || i == REG_A1)
611 rtx mem = gen_rtx_MEM (PDImode, postinc1);
612 MEM_VOLATILE_P (mem) = 1;
613 emit_move_insn (gen_rtx_REG (PDImode, i), mem);
616 emit_move_insn (gen_rtx_REG (SImode, i), postinc);
619 regno = REG_P5 - npregs_consec;
620 for (; npregs != npregs_consec; regno--)
622 if (must_save_p (is_inthandler, regno))
624 emit_move_insn (gen_rtx_REG (word_mode, regno), postinc);
628 regno = REG_R7 - ndregs_consec;
629 for (; ndregs != ndregs_consec; regno--)
631 if (must_save_p (is_inthandler, regno))
633 emit_move_insn (gen_rtx_REG (word_mode, regno), postinc);
638 if (total_consec != 0)
640 rtx pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_consec + 1));
642 = gen_rtx_SET (VOIDmode, spreg,
643 gen_rtx_PLUS (Pmode, spreg,
644 GEN_INT (total_consec * 4)));
646 if (npregs_consec > 0)
651 for (i = 0; i < total_consec; i++)
654 ? gen_rtx_PLUS (Pmode, spreg, GEN_INT (i * 4))
656 rtx memref = gen_rtx_MEM (word_mode, addr);
659 XVECEXP (pat, 0, i + 1)
660 = gen_rtx_SET (VOIDmode, gen_rtx_REG (word_mode, regno), memref);
662 if (npregs_consec > 0)
664 if (--npregs_consec == 0)
669 insn = emit_insn (pat);
670 RTX_FRAME_RELATED_P (insn) = 1;
672 if (saveall || is_inthandler)
673 emit_move_insn (gen_rtx_REG (SImode, REG_ASTAT), postinc);
676 /* Perform any needed actions needed for a function that is receiving a
677 variable number of arguments.
681 MODE and TYPE are the mode and type of the current parameter.
683 PRETEND_SIZE is a variable that should be set to the amount of stack
684 that must be pushed by the prolog to pretend that our caller pushed
687 Normally, this macro will push all remaining incoming registers on the
688 stack and set PRETEND_SIZE to the length of the registers pushed.
691 - VDSP C compiler manual (our ABI) says that a variable args function
692 should save the R0, R1 and R2 registers in the stack.
693 - The caller will always leave space on the stack for the
694 arguments that are passed in registers, so we dont have
695 to leave any extra space.
696 - now, the vastart pointer can access all arguments from the stack. */
699 setup_incoming_varargs (CUMULATIVE_ARGS *cum,
700 enum machine_mode mode ATTRIBUTE_UNUSED,
701 tree type ATTRIBUTE_UNUSED, int *pretend_size,
710 /* The move for named arguments will be generated automatically by the
711 compiler. We need to generate the move rtx for the unnamed arguments
712 if they are in the first 3 words. We assume at least 1 named argument
713 exists, so we never generate [ARGP] = R0 here. */
715 for (i = cum->words + 1; i < max_arg_registers; i++)
717 mem = gen_rtx_MEM (Pmode,
718 plus_constant (arg_pointer_rtx, (i * UNITS_PER_WORD)));
719 emit_move_insn (mem, gen_rtx_REG (Pmode, i));
725 /* Value should be nonzero if functions must have frame pointers.
726 Zero means the frame pointer need not be set up (and parms may
727 be accessed via the stack pointer) in functions that seem suitable. */
730 bfin_frame_pointer_required (void)
732 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
734 if (fkind != SUBROUTINE)
737 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
738 so we have to override it for non-leaf functions. */
739 if (TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf)
745 /* Return the number of registers pushed during the prologue. */
748 n_regs_saved_by_prologue (void)
750 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
751 bool is_inthandler = fkind != SUBROUTINE;
752 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
753 bool all = (lookup_attribute ("saveall", attrs) != NULL_TREE
754 || (is_inthandler && !current_function_is_leaf));
755 int ndregs = all ? 8 : n_dregs_to_save (is_inthandler, false);
756 int npregs = all ? 6 : n_pregs_to_save (is_inthandler, false);
757 int n = ndregs + npregs;
760 if (all || stack_frame_needed_p ())
761 /* We use a LINK instruction in this case. */
765 if (must_save_fp_p ())
767 if (! current_function_is_leaf)
771 if (fkind != SUBROUTINE || all)
772 /* Increment once for ASTAT. */
775 if (fkind != SUBROUTINE)
778 if (lookup_attribute ("nesting", attrs))
782 for (i = REG_P7 + 1; i < REG_CC; i++)
784 || (fkind != SUBROUTINE
785 && (df_regs_ever_live_p (i)
786 || (!leaf_function_p () && call_used_regs[i]))))
787 n += i == REG_A0 || i == REG_A1 ? 2 : 1;
792 /* Return the offset between two registers, one to be eliminated, and the other
793 its replacement, at the start of a routine. */
796 bfin_initial_elimination_offset (int from, int to)
798 HOST_WIDE_INT offset = 0;
800 if (from == ARG_POINTER_REGNUM)
801 offset = n_regs_saved_by_prologue () * 4;
803 if (to == STACK_POINTER_REGNUM)
805 if (crtl->outgoing_args_size >= FIXED_STACK_AREA)
806 offset += crtl->outgoing_args_size;
807 else if (crtl->outgoing_args_size)
808 offset += FIXED_STACK_AREA;
810 offset += get_frame_size ();
816 /* Emit code to load a constant CONSTANT into register REG; setting
817 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
818 Make sure that the insns we generate need not be split. */
821 frame_related_constant_load (rtx reg, HOST_WIDE_INT constant, bool related)
824 rtx cst = GEN_INT (constant);
826 if (constant >= -32768 && constant < 65536)
827 insn = emit_move_insn (reg, cst);
830 /* We don't call split_load_immediate here, since dwarf2out.c can get
831 confused about some of the more clever sequences it can generate. */
832 insn = emit_insn (gen_movsi_high (reg, cst));
834 RTX_FRAME_RELATED_P (insn) = 1;
835 insn = emit_insn (gen_movsi_low (reg, reg, cst));
838 RTX_FRAME_RELATED_P (insn) = 1;
841 /* Generate efficient code to add a value to a P register.
842 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
843 EPILOGUE_P is zero if this function is called for prologue,
844 otherwise it's nonzero. And it's less than zero if this is for
848 add_to_reg (rtx reg, HOST_WIDE_INT value, int frame, int epilogue_p)
853 /* Choose whether to use a sequence using a temporary register, or
854 a sequence with multiple adds. We can add a signed 7-bit value
855 in one instruction. */
856 if (value > 120 || value < -120)
864 /* For prologue or normal epilogue, P1 can be safely used
865 as the temporary register. For sibcall epilogue, we try to find
866 a call used P register, which will be restored in epilogue.
867 If we cannot find such a P register, we have to use one I register
871 tmpreg = gen_rtx_REG (SImode, REG_P1);
875 for (i = REG_P0; i <= REG_P5; i++)
876 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
878 && i == PIC_OFFSET_TABLE_REGNUM
879 && (crtl->uses_pic_offset_table
880 || (TARGET_ID_SHARED_LIBRARY
881 && ! current_function_is_leaf))))
884 tmpreg = gen_rtx_REG (SImode, i);
887 tmpreg = gen_rtx_REG (SImode, REG_P1);
888 tmpreg2 = gen_rtx_REG (SImode, REG_I0);
889 emit_move_insn (tmpreg2, tmpreg);
894 frame_related_constant_load (tmpreg, value, TRUE);
896 insn = emit_move_insn (tmpreg, GEN_INT (value));
898 insn = emit_insn (gen_addsi3 (reg, reg, tmpreg));
900 RTX_FRAME_RELATED_P (insn) = 1;
902 if (tmpreg2 != NULL_RTX)
903 emit_move_insn (tmpreg, tmpreg2);
914 /* We could use -62, but that would leave the stack unaligned, so
918 insn = emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
920 RTX_FRAME_RELATED_P (insn) = 1;
926 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
927 is too large, generate a sequence of insns that has the same effect.
928 SPREG contains (reg:SI REG_SP). */
931 emit_link_insn (rtx spreg, HOST_WIDE_INT frame_size)
933 HOST_WIDE_INT link_size = frame_size;
937 if (link_size > 262140)
940 /* Use a LINK insn with as big a constant as possible, then subtract
941 any remaining size from the SP. */
942 insn = emit_insn (gen_link (GEN_INT (-8 - link_size)));
943 RTX_FRAME_RELATED_P (insn) = 1;
945 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
947 rtx set = XVECEXP (PATTERN (insn), 0, i);
948 gcc_assert (GET_CODE (set) == SET);
949 RTX_FRAME_RELATED_P (set) = 1;
952 frame_size -= link_size;
956 /* Must use a call-clobbered PREG that isn't the static chain. */
957 rtx tmpreg = gen_rtx_REG (Pmode, REG_P1);
959 frame_related_constant_load (tmpreg, -frame_size, TRUE);
960 insn = emit_insn (gen_addsi3 (spreg, spreg, tmpreg));
961 RTX_FRAME_RELATED_P (insn) = 1;
965 /* Return the number of bytes we must reserve for outgoing arguments
966 in the current function's stack frame. */
971 if (crtl->outgoing_args_size)
973 if (crtl->outgoing_args_size >= FIXED_STACK_AREA)
974 return crtl->outgoing_args_size;
976 return FIXED_STACK_AREA;
981 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
982 function must save all its registers (true only for certain interrupt
986 do_link (rtx spreg, HOST_WIDE_INT frame_size, bool all)
988 frame_size += arg_area_size ();
990 if (all || stack_frame_needed_p ()
991 || (must_save_fp_p () && ! current_function_is_leaf))
992 emit_link_insn (spreg, frame_size);
995 if (! current_function_is_leaf)
997 rtx pat = gen_movsi (gen_rtx_MEM (Pmode,
998 gen_rtx_PRE_DEC (Pmode, spreg)),
1000 rtx insn = emit_insn (pat);
1001 RTX_FRAME_RELATED_P (insn) = 1;
1003 if (must_save_fp_p ())
1005 rtx pat = gen_movsi (gen_rtx_MEM (Pmode,
1006 gen_rtx_PRE_DEC (Pmode, spreg)),
1007 gen_rtx_REG (Pmode, REG_FP));
1008 rtx insn = emit_insn (pat);
1009 RTX_FRAME_RELATED_P (insn) = 1;
1011 add_to_reg (spreg, -frame_size, 1, 0);
1015 /* Like do_link, but used for epilogues to deallocate the stack frame.
1016 EPILOGUE_P is zero if this function is called for prologue,
1017 otherwise it's nonzero. And it's less than zero if this is for
1018 sibcall epilogue. */
1021 do_unlink (rtx spreg, HOST_WIDE_INT frame_size, bool all, int epilogue_p)
1023 frame_size += arg_area_size ();
1025 if (all || stack_frame_needed_p ())
1026 emit_insn (gen_unlink ());
1029 rtx postinc = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, spreg));
1031 add_to_reg (spreg, frame_size, 0, epilogue_p);
1032 if (must_save_fp_p ())
1034 rtx fpreg = gen_rtx_REG (Pmode, REG_FP);
1035 emit_move_insn (fpreg, postinc);
1038 if (! current_function_is_leaf)
1040 emit_move_insn (bfin_rets_rtx, postinc);
1041 emit_use (bfin_rets_rtx);
1046 /* Generate a prologue suitable for a function of kind FKIND. This is
1047 called for interrupt and exception handler prologues.
1048 SPREG contains (reg:SI REG_SP). */
1051 expand_interrupt_handler_prologue (rtx spreg, e_funkind fkind, bool all)
1053 HOST_WIDE_INT frame_size = get_frame_size ();
1054 rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg);
1055 rtx predec = gen_rtx_MEM (SImode, predec1);
1057 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
1058 tree kspisusp = lookup_attribute ("kspisusp", attrs);
1062 insn = emit_move_insn (spreg, gen_rtx_REG (Pmode, REG_USP));
1063 RTX_FRAME_RELATED_P (insn) = 1;
1066 /* We need space on the stack in case we need to save the argument
1068 if (fkind == EXCPT_HANDLER)
1070 insn = emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (-12)));
1071 RTX_FRAME_RELATED_P (insn) = 1;
1074 /* If we're calling other functions, they won't save their call-clobbered
1075 registers, so we must save everything here. */
1076 if (!current_function_is_leaf)
1078 expand_prologue_reg_save (spreg, all, true);
1080 if (lookup_attribute ("nesting", attrs))
1082 rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX
1083 : fkind == NMI_HANDLER ? REG_RETN
1085 insn = emit_move_insn (predec, srcreg);
1086 RTX_FRAME_RELATED_P (insn) = 1;
1089 do_link (spreg, frame_size, all);
1091 if (fkind == EXCPT_HANDLER)
1093 rtx r0reg = gen_rtx_REG (SImode, REG_R0);
1094 rtx r1reg = gen_rtx_REG (SImode, REG_R1);
1095 rtx r2reg = gen_rtx_REG (SImode, REG_R2);
1098 insn = emit_move_insn (r0reg, gen_rtx_REG (SImode, REG_SEQSTAT));
1099 insn = emit_insn (gen_ashrsi3 (r0reg, r0reg, GEN_INT (26)));
1100 insn = emit_insn (gen_ashlsi3 (r0reg, r0reg, GEN_INT (26)));
1101 insn = emit_move_insn (r1reg, spreg);
1102 insn = emit_move_insn (r2reg, gen_rtx_REG (Pmode, REG_FP));
1103 insn = emit_insn (gen_addsi3 (r2reg, r2reg, GEN_INT (8)));
1107 /* Generate an epilogue suitable for a function of kind FKIND. This is
1108 called for interrupt and exception handler epilogues.
1109 SPREG contains (reg:SI REG_SP). */
1112 expand_interrupt_handler_epilogue (rtx spreg, e_funkind fkind, bool all)
1114 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
1115 rtx postinc1 = gen_rtx_POST_INC (SImode, spreg);
1116 rtx postinc = gen_rtx_MEM (SImode, postinc1);
1118 /* A slightly crude technique to stop flow from trying to delete "dead"
1120 MEM_VOLATILE_P (postinc) = 1;
1122 do_unlink (spreg, get_frame_size (), all, 1);
1124 if (lookup_attribute ("nesting", attrs))
1126 rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX
1127 : fkind == NMI_HANDLER ? REG_RETN
1129 emit_move_insn (srcreg, postinc);
1132 /* If we're calling other functions, they won't save their call-clobbered
1133 registers, so we must save (and restore) everything here. */
1134 if (!current_function_is_leaf)
1137 expand_epilogue_reg_restore (spreg, all, true);
1139 /* Deallocate any space we left on the stack in case we needed to save the
1140 argument registers. */
1141 if (fkind == EXCPT_HANDLER)
1142 emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (12)));
1144 emit_jump_insn (gen_return_internal (GEN_INT (fkind)));
1147 /* Used while emitting the prologue to generate code to load the correct value
1148 into the PIC register, which is passed in DEST. */
1151 bfin_load_pic_reg (rtx dest)
1153 struct cgraph_local_info *i = NULL;
1156 i = cgraph_local_info (current_function_decl);
1158 /* Functions local to the translation unit don't need to reload the
1159 pic reg, since the caller always passes a usable one. */
1161 return pic_offset_table_rtx;
1163 if (bfin_lib_id_given)
1164 addr = plus_constant (pic_offset_table_rtx, -4 - bfin_library_id * 4);
1166 addr = gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1167 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1168 UNSPEC_LIBRARY_OFFSET));
1169 insn = emit_insn (gen_movsi (dest, gen_rtx_MEM (Pmode, addr)));
1173 /* Generate RTL for the prologue of the current function. */
1176 bfin_expand_prologue (void)
1178 HOST_WIDE_INT frame_size = get_frame_size ();
1179 rtx spreg = gen_rtx_REG (Pmode, REG_SP);
1180 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
1181 rtx pic_reg_loaded = NULL_RTX;
1182 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
1183 bool all = lookup_attribute ("saveall", attrs) != NULL_TREE;
1185 if (fkind != SUBROUTINE)
1187 expand_interrupt_handler_prologue (spreg, fkind, all);
1191 if (crtl->limit_stack
1192 || (TARGET_STACK_CHECK_L1
1193 && !DECL_NO_LIMIT_STACK (current_function_decl)))
1195 HOST_WIDE_INT offset
1196 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM,
1197 STACK_POINTER_REGNUM);
1198 rtx lim = crtl->limit_stack ? stack_limit_rtx : NULL_RTX;
1199 rtx p2reg = gen_rtx_REG (Pmode, REG_P2);
1203 emit_move_insn (p2reg, gen_int_mode (0xFFB00000, SImode));
1204 emit_move_insn (p2reg, gen_rtx_MEM (Pmode, p2reg));
1207 if (GET_CODE (lim) == SYMBOL_REF)
1209 if (TARGET_ID_SHARED_LIBRARY)
1211 rtx p1reg = gen_rtx_REG (Pmode, REG_P1);
1213 pic_reg_loaded = bfin_load_pic_reg (p2reg);
1214 val = legitimize_pic_address (stack_limit_rtx, p1reg,
1216 emit_move_insn (p1reg, val);
1217 frame_related_constant_load (p2reg, offset, FALSE);
1218 emit_insn (gen_addsi3 (p2reg, p2reg, p1reg));
1223 rtx limit = plus_constant (lim, offset);
1224 emit_move_insn (p2reg, limit);
1231 emit_move_insn (p2reg, lim);
1232 add_to_reg (p2reg, offset, 0, 0);
1235 emit_insn (gen_compare_lt (bfin_cc_rtx, spreg, lim));
1236 emit_insn (gen_trapifcc ());
1238 expand_prologue_reg_save (spreg, all, false);
1240 do_link (spreg, frame_size, false);
1242 if (TARGET_ID_SHARED_LIBRARY
1244 && (crtl->uses_pic_offset_table
1245 || !current_function_is_leaf))
1246 bfin_load_pic_reg (pic_offset_table_rtx);
1249 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1250 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1251 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1255 bfin_expand_epilogue (int need_return, int eh_return, bool sibcall_p)
1257 rtx spreg = gen_rtx_REG (Pmode, REG_SP);
1258 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
1259 int e = sibcall_p ? -1 : 1;
1260 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
1261 bool all = lookup_attribute ("saveall", attrs) != NULL_TREE;
1263 if (fkind != SUBROUTINE)
1265 expand_interrupt_handler_epilogue (spreg, fkind, all);
1269 do_unlink (spreg, get_frame_size (), false, e);
1271 expand_epilogue_reg_restore (spreg, all, false);
1273 /* Omit the return insn if this is for a sibcall. */
1278 emit_insn (gen_addsi3 (spreg, spreg, gen_rtx_REG (Pmode, REG_P2)));
1280 emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE)));
1283 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1286 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
1287 unsigned int new_reg)
1289 /* Interrupt functions can only use registers that have already been
1290 saved by the prologue, even if they would normally be
1293 if (funkind (TREE_TYPE (current_function_decl)) != SUBROUTINE
1294 && !df_regs_ever_live_p (new_reg))
1300 /* Return the value of the return address for the frame COUNT steps up
1301 from the current frame, after the prologue.
1302 We punt for everything but the current frame by returning const0_rtx. */
1305 bfin_return_addr_rtx (int count)
1310 return get_hard_reg_initial_val (Pmode, REG_RETS);
1313 /* Try machine-dependent ways of modifying an illegitimate address X
1314 to be legitimate. If we find one, return the new, valid address,
1315 otherwise return NULL_RTX.
1317 OLDX is the address as it was before break_out_memory_refs was called.
1318 In some cases it is useful to look at this to decide what needs to be done.
1320 MODE is the mode of the memory reference. */
1323 legitimize_address (rtx x ATTRIBUTE_UNUSED, rtx oldx ATTRIBUTE_UNUSED,
1324 enum machine_mode mode ATTRIBUTE_UNUSED)
1330 bfin_delegitimize_address (rtx orig_x)
1334 if (GET_CODE (x) != MEM)
1338 if (GET_CODE (x) == PLUS
1339 && GET_CODE (XEXP (x, 1)) == UNSPEC
1340 && XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC
1341 && GET_CODE (XEXP (x, 0)) == REG
1342 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
1343 return XVECEXP (XEXP (x, 1), 0, 0);
1348 /* This predicate is used to compute the length of a load/store insn.
1349 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1350 32-bit instruction. */
1353 effective_address_32bit_p (rtx op, enum machine_mode mode)
1355 HOST_WIDE_INT offset;
1357 mode = GET_MODE (op);
1360 if (GET_CODE (op) != PLUS)
1362 gcc_assert (REG_P (op) || GET_CODE (op) == POST_INC
1363 || GET_CODE (op) == PRE_DEC || GET_CODE (op) == POST_DEC);
1367 if (GET_CODE (XEXP (op, 1)) == UNSPEC)
1370 offset = INTVAL (XEXP (op, 1));
1372 /* All byte loads use a 16-bit offset. */
1373 if (GET_MODE_SIZE (mode) == 1)
1376 if (GET_MODE_SIZE (mode) == 4)
1378 /* Frame pointer relative loads can use a negative offset, all others
1379 are restricted to a small positive one. */
1380 if (XEXP (op, 0) == frame_pointer_rtx)
1381 return offset < -128 || offset > 60;
1382 return offset < 0 || offset > 60;
1385 /* Must be HImode now. */
1386 return offset < 0 || offset > 30;
1389 /* Returns true if X is a memory reference using an I register. */
1391 bfin_dsp_memref_p (rtx x)
1396 if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_INC
1397 || GET_CODE (x) == POST_DEC || GET_CODE (x) == PRE_DEC)
1402 /* Return cost of the memory address ADDR.
1403 All addressing modes are equally cheap on the Blackfin. */
1406 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
1411 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1414 print_address_operand (FILE *file, rtx x)
1416 switch (GET_CODE (x))
1419 output_address (XEXP (x, 0));
1420 fprintf (file, "+");
1421 output_address (XEXP (x, 1));
1425 fprintf (file, "--");
1426 output_address (XEXP (x, 0));
1429 output_address (XEXP (x, 0));
1430 fprintf (file, "++");
1433 output_address (XEXP (x, 0));
1434 fprintf (file, "--");
1438 gcc_assert (GET_CODE (x) != MEM);
1439 print_operand (file, x, 0);
1444 /* Adding intp DImode support by Tony
1450 print_operand (FILE *file, rtx x, char code)
1452 enum machine_mode mode;
1456 if (GET_MODE (current_output_insn) == SImode)
1457 fprintf (file, " ||");
1459 fprintf (file, ";");
1463 mode = GET_MODE (x);
1468 switch (GET_CODE (x))
1471 fprintf (file, "e");
1474 fprintf (file, "ne");
1477 fprintf (file, "g");
1480 fprintf (file, "l");
1483 fprintf (file, "ge");
1486 fprintf (file, "le");
1489 fprintf (file, "g");
1492 fprintf (file, "l");
1495 fprintf (file, "ge");
1498 fprintf (file, "le");
1501 output_operand_lossage ("invalid %%j value");
1505 case 'J': /* reverse logic */
1506 switch (GET_CODE(x))
1509 fprintf (file, "ne");
1512 fprintf (file, "e");
1515 fprintf (file, "le");
1518 fprintf (file, "ge");
1521 fprintf (file, "l");
1524 fprintf (file, "g");
1527 fprintf (file, "le");
1530 fprintf (file, "ge");
1533 fprintf (file, "l");
1536 fprintf (file, "g");
1539 output_operand_lossage ("invalid %%J value");
1544 switch (GET_CODE (x))
1550 fprintf (file, "%s", short_reg_names[REGNO (x)]);
1552 output_operand_lossage ("invalid operand for code '%c'", code);
1554 else if (code == 'd')
1557 fprintf (file, "%s", high_reg_names[REGNO (x)]);
1559 output_operand_lossage ("invalid operand for code '%c'", code);
1561 else if (code == 'w')
1563 if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1)
1564 fprintf (file, "%s.w", reg_names[REGNO (x)]);
1566 output_operand_lossage ("invalid operand for code '%c'", code);
1568 else if (code == 'x')
1570 if (REGNO (x) == REG_A0 || REGNO (x) == REG_A1)
1571 fprintf (file, "%s.x", reg_names[REGNO (x)]);
1573 output_operand_lossage ("invalid operand for code '%c'", code);
1575 else if (code == 'v')
1577 if (REGNO (x) == REG_A0)
1578 fprintf (file, "AV0");
1579 else if (REGNO (x) == REG_A1)
1580 fprintf (file, "AV1");
1582 output_operand_lossage ("invalid operand for code '%c'", code);
1584 else if (code == 'D')
1586 if (D_REGNO_P (REGNO (x)))
1587 fprintf (file, "%s", dregs_pair_names[REGNO (x)]);
1589 output_operand_lossage ("invalid operand for code '%c'", code);
1591 else if (code == 'H')
1593 if ((mode == DImode || mode == DFmode) && REG_P (x))
1594 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
1596 output_operand_lossage ("invalid operand for code '%c'", code);
1598 else if (code == 'T')
1600 if (D_REGNO_P (REGNO (x)))
1601 fprintf (file, "%s", byte_reg_names[REGNO (x)]);
1603 output_operand_lossage ("invalid operand for code '%c'", code);
1606 fprintf (file, "%s", reg_names[REGNO (x)]);
1612 print_address_operand (file, x);
1624 fputs ("(FU)", file);
1627 fputs ("(T)", file);
1630 fputs ("(TFU)", file);
1633 fputs ("(W32)", file);
1636 fputs ("(IS)", file);
1639 fputs ("(IU)", file);
1642 fputs ("(IH)", file);
1645 fputs ("(M)", file);
1648 fputs ("(IS,M)", file);
1651 fputs ("(ISS2)", file);
1654 fputs ("(S2RND)", file);
1661 else if (code == 'b')
1663 if (INTVAL (x) == 0)
1665 else if (INTVAL (x) == 1)
1671 /* Moves to half registers with d or h modifiers always use unsigned
1673 else if (code == 'd')
1674 x = GEN_INT ((INTVAL (x) >> 16) & 0xffff);
1675 else if (code == 'h')
1676 x = GEN_INT (INTVAL (x) & 0xffff);
1677 else if (code == 'N')
1678 x = GEN_INT (-INTVAL (x));
1679 else if (code == 'X')
1680 x = GEN_INT (exact_log2 (0xffffffff & INTVAL (x)));
1681 else if (code == 'Y')
1682 x = GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x)));
1683 else if (code == 'Z')
1684 /* Used for LINK insns. */
1685 x = GEN_INT (-8 - INTVAL (x));
1690 output_addr_const (file, x);
1694 output_operand_lossage ("invalid const_double operand");
1698 switch (XINT (x, 1))
1700 case UNSPEC_MOVE_PIC:
1701 output_addr_const (file, XVECEXP (x, 0, 0));
1702 fprintf (file, "@GOT");
1705 case UNSPEC_MOVE_FDPIC:
1706 output_addr_const (file, XVECEXP (x, 0, 0));
1707 fprintf (file, "@GOT17M4");
1710 case UNSPEC_FUNCDESC_GOT17M4:
1711 output_addr_const (file, XVECEXP (x, 0, 0));
1712 fprintf (file, "@FUNCDESC_GOT17M4");
1715 case UNSPEC_LIBRARY_OFFSET:
1716 fprintf (file, "_current_shared_library_p5_offset_");
1725 output_addr_const (file, x);
1730 /* Argument support functions. */
1732 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1733 for a call to a function whose data type is FNTYPE.
1734 For a library call, FNTYPE is 0.
1735 VDSP C Compiler manual, our ABI says that
1736 first 3 words of arguments will use R0, R1 and R2.
1740 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
1741 rtx libname ATTRIBUTE_UNUSED)
1743 static CUMULATIVE_ARGS zero_cum;
1747 /* Set up the number of registers to use for passing arguments. */
1749 cum->nregs = max_arg_registers;
1750 cum->arg_regs = arg_regs;
1752 cum->call_cookie = CALL_NORMAL;
1753 /* Check for a longcall attribute. */
1754 if (fntype && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
1755 cum->call_cookie |= CALL_SHORT;
1756 else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
1757 cum->call_cookie |= CALL_LONG;
1762 /* Update the data in CUM to advance over an argument
1763 of mode MODE and data type TYPE.
1764 (TYPE is null for libcalls where that information may not be available.) */
1767 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1768 int named ATTRIBUTE_UNUSED)
1770 int count, bytes, words;
1772 bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1773 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1775 cum->words += words;
1776 cum->nregs -= words;
1778 if (cum->nregs <= 0)
1781 cum->arg_regs = NULL;
1785 for (count = 1; count <= words; count++)
1792 /* Define where to put the arguments to a function.
1793 Value is zero to push the argument on the stack,
1794 or a hard register in which to store the argument.
1796 MODE is the argument's machine mode.
1797 TYPE is the data type of the argument (as a tree).
1798 This is null for libcalls where that information may
1800 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1801 the preceding args and about the function being called.
1802 NAMED is nonzero if this argument is a named parameter
1803 (otherwise it is an extra parameter matching an ellipsis). */
1806 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1807 int named ATTRIBUTE_UNUSED)
1810 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1812 if (mode == VOIDmode)
1813 /* Compute operand 2 of the call insn. */
1814 return GEN_INT (cum->call_cookie);
1820 return gen_rtx_REG (mode, *(cum->arg_regs));
1825 /* For an arg passed partly in registers and partly in memory,
1826 this is the number of bytes passed in registers.
1827 For args passed entirely in registers or entirely in memory, zero.
1829 Refer VDSP C Compiler manual, our ABI.
1830 First 3 words are in registers. So, if an argument is larger
1831 than the registers available, it will span the register and
1835 bfin_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1836 tree type ATTRIBUTE_UNUSED,
1837 bool named ATTRIBUTE_UNUSED)
1840 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1841 int bytes_left = cum->nregs * UNITS_PER_WORD;
1846 if (bytes_left == 0)
1848 if (bytes > bytes_left)
1853 /* Variable sized types are passed by reference. */
1856 bfin_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1857 enum machine_mode mode ATTRIBUTE_UNUSED,
1858 const_tree type, bool named ATTRIBUTE_UNUSED)
1860 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
1863 /* Decide whether a type should be returned in memory (true)
1864 or in a register (false). This is called by the macro
1865 TARGET_RETURN_IN_MEMORY. */
1868 bfin_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1870 int size = int_size_in_bytes (type);
1871 return size > 2 * UNITS_PER_WORD || size == -1;
1874 /* Register in which address to store a structure value
1875 is passed to a function. */
1877 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
1878 int incoming ATTRIBUTE_UNUSED)
1880 return gen_rtx_REG (Pmode, REG_P0);
1883 /* Return true when register may be used to pass function parameters. */
1886 function_arg_regno_p (int n)
1889 for (i = 0; arg_regs[i] != -1; i++)
1890 if (n == arg_regs[i])
1895 /* Returns 1 if OP contains a symbol reference */
1898 symbolic_reference_mentioned_p (rtx op)
1900 register const char *fmt;
1903 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1906 fmt = GET_RTX_FORMAT (GET_CODE (op));
1907 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1913 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1914 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1918 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1925 /* Decide whether we can make a sibling call to a function. DECL is the
1926 declaration of the function being targeted by the call and EXP is the
1927 CALL_EXPR representing the call. */
1930 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
1931 tree exp ATTRIBUTE_UNUSED)
1933 struct cgraph_local_info *this_func, *called_func;
1934 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
1935 if (fkind != SUBROUTINE)
1937 if (!TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA)
1940 /* When compiling for ID shared libraries, can't sibcall a local function
1941 from a non-local function, because the local function thinks it does
1942 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1943 sibcall epilogue, and we end up with the wrong value in P5. */
1946 this_func = cgraph_local_info (current_function_decl);
1947 called_func = cgraph_local_info (decl);
1948 return !called_func->local || this_func->local;
1951 /* Emit RTL insns to initialize the variable parts of a trampoline at
1952 TRAMP. FNADDR is an RTX for the address of the function's pure
1953 code. CXT is an RTX for the static chain value for the function. */
1956 initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
1958 rtx t1 = copy_to_reg (fnaddr);
1959 rtx t2 = copy_to_reg (cxt);
1965 rtx a = memory_address (Pmode, plus_constant (tramp, 8));
1966 addr = memory_address (Pmode, tramp);
1967 emit_move_insn (gen_rtx_MEM (SImode, addr), a);
1971 addr = memory_address (Pmode, plus_constant (tramp, i + 2));
1972 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1));
1973 emit_insn (gen_ashrsi3 (t1, t1, GEN_INT (16)));
1974 addr = memory_address (Pmode, plus_constant (tramp, i + 6));
1975 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1));
1977 addr = memory_address (Pmode, plus_constant (tramp, i + 10));
1978 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2));
1979 emit_insn (gen_ashrsi3 (t2, t2, GEN_INT (16)));
1980 addr = memory_address (Pmode, plus_constant (tramp, i + 14));
1981 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2));
1984 /* Emit insns to move operands[1] into operands[0]. */
1987 emit_pic_move (rtx *operands, enum machine_mode mode ATTRIBUTE_UNUSED)
1989 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
1991 gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed));
1992 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
1993 operands[1] = force_reg (SImode, operands[1]);
1995 operands[1] = legitimize_pic_address (operands[1], temp,
1996 TARGET_FDPIC ? OUR_FDPIC_REG
1997 : pic_offset_table_rtx);
2000 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
2001 Returns true if no further code must be generated, false if the caller
2002 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
2005 expand_move (rtx *operands, enum machine_mode mode)
2007 rtx op = operands[1];
2008 if ((TARGET_ID_SHARED_LIBRARY || TARGET_FDPIC)
2009 && SYMBOLIC_CONST (op))
2010 emit_pic_move (operands, mode);
2011 else if (mode == SImode && GET_CODE (op) == CONST
2012 && GET_CODE (XEXP (op, 0)) == PLUS
2013 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
2014 && !bfin_legitimate_constant_p (op))
2016 rtx dest = operands[0];
2018 gcc_assert (!reload_in_progress && !reload_completed);
2020 op0 = force_reg (mode, XEXP (op, 0));
2022 if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode))
2023 op1 = force_reg (mode, op1);
2024 if (GET_CODE (dest) == MEM)
2025 dest = gen_reg_rtx (mode);
2026 emit_insn (gen_addsi3 (dest, op0, op1));
2027 if (dest == operands[0])
2031 /* Don't generate memory->memory or constant->memory moves, go through a
2033 else if ((reload_in_progress | reload_completed) == 0
2034 && GET_CODE (operands[0]) == MEM
2035 && GET_CODE (operands[1]) != REG)
2036 operands[1] = force_reg (mode, operands[1]);
2040 /* Split one or more DImode RTL references into pairs of SImode
2041 references. The RTL can be REG, offsettable MEM, integer constant, or
2042 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2043 split and "num" is its length. lo_half and hi_half are output arrays
2044 that parallel "operands". */
2047 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
2051 rtx op = operands[num];
2053 /* simplify_subreg refuse to split volatile memory addresses,
2054 but we still have to handle it. */
2055 if (GET_CODE (op) == MEM)
2057 lo_half[num] = adjust_address (op, SImode, 0);
2058 hi_half[num] = adjust_address (op, SImode, 4);
2062 lo_half[num] = simplify_gen_subreg (SImode, op,
2063 GET_MODE (op) == VOIDmode
2064 ? DImode : GET_MODE (op), 0);
2065 hi_half[num] = simplify_gen_subreg (SImode, op,
2066 GET_MODE (op) == VOIDmode
2067 ? DImode : GET_MODE (op), 4);
2073 bfin_longcall_p (rtx op, int call_cookie)
2075 gcc_assert (GET_CODE (op) == SYMBOL_REF);
2076 if (call_cookie & CALL_SHORT)
2078 if (call_cookie & CALL_LONG)
2080 if (TARGET_LONG_CALLS)
2085 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
2086 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
2087 SIBCALL is nonzero if this is a sibling call. */
2090 bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
2092 rtx use = NULL, call;
2093 rtx callee = XEXP (fnaddr, 0);
2094 int nelts = 2 + !!sibcall;
2096 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REGNO);
2099 /* In an untyped call, we can get NULL for operand 2. */
2100 if (cookie == NULL_RTX)
2101 cookie = const0_rtx;
2103 /* Static functions and indirect calls don't need the pic register. */
2104 if (!TARGET_FDPIC && flag_pic
2105 && GET_CODE (callee) == SYMBOL_REF
2106 && !SYMBOL_REF_LOCAL_P (callee))
2107 use_reg (&use, pic_offset_table_rtx);
2111 int caller_has_l1_text, callee_has_l1_text;
2113 caller_has_l1_text = callee_has_l1_text = 0;
2115 if (lookup_attribute ("l1_text",
2116 DECL_ATTRIBUTES (cfun->decl)) != NULL_TREE)
2117 caller_has_l1_text = 1;
2119 if (GET_CODE (callee) == SYMBOL_REF
2120 && SYMBOL_REF_DECL (callee) && DECL_P (SYMBOL_REF_DECL (callee))
2123 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee))) != NULL_TREE)
2124 callee_has_l1_text = 1;
2126 if (GET_CODE (callee) != SYMBOL_REF
2127 || bfin_longcall_p (callee, INTVAL (cookie))
2128 || (GET_CODE (callee) == SYMBOL_REF
2129 && !SYMBOL_REF_LOCAL_P (callee)
2130 && TARGET_INLINE_PLT)
2131 || caller_has_l1_text != callee_has_l1_text
2132 || (caller_has_l1_text && callee_has_l1_text
2133 && (GET_CODE (callee) != SYMBOL_REF
2134 || !SYMBOL_REF_LOCAL_P (callee))))
2137 if (! address_operand (addr, Pmode))
2138 addr = force_reg (Pmode, addr);
2140 fnaddr = gen_reg_rtx (SImode);
2141 emit_insn (gen_load_funcdescsi (fnaddr, addr));
2142 fnaddr = gen_rtx_MEM (Pmode, fnaddr);
2144 picreg = gen_reg_rtx (SImode);
2145 emit_insn (gen_load_funcdescsi (picreg,
2146 plus_constant (addr, 4)));
2151 else if ((!register_no_elim_operand (callee, Pmode)
2152 && GET_CODE (callee) != SYMBOL_REF)
2153 || (GET_CODE (callee) == SYMBOL_REF
2154 && ((TARGET_ID_SHARED_LIBRARY && !TARGET_LEAF_ID_SHARED_LIBRARY)
2155 || bfin_longcall_p (callee, INTVAL (cookie)))))
2157 callee = copy_to_mode_reg (Pmode, callee);
2158 fnaddr = gen_rtx_MEM (Pmode, callee);
2160 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
2163 call = gen_rtx_SET (VOIDmode, retval, call);
2165 pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nelts));
2167 XVECEXP (pat, 0, n++) = call;
2169 XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg);
2170 XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie);
2172 XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode);
2173 call = emit_call_insn (pat);
2175 CALL_INSN_FUNCTION_USAGE (call) = use;
2178 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
2181 hard_regno_mode_ok (int regno, enum machine_mode mode)
2183 /* Allow only dregs to store value of mode HI or QI */
2184 enum reg_class rclass = REGNO_REG_CLASS (regno);
2189 if (mode == V2HImode)
2190 return D_REGNO_P (regno);
2191 if (rclass == CCREGS)
2192 return mode == BImode;
2193 if (mode == PDImode || mode == V2PDImode)
2194 return regno == REG_A0 || regno == REG_A1;
2196 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
2197 up with a bad register class (such as ALL_REGS) for DImode. */
2199 return regno < REG_M3;
2202 && TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
2205 return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
2208 /* Implements target hook vector_mode_supported_p. */
2211 bfin_vector_mode_supported_p (enum machine_mode mode)
2213 return mode == V2HImode;
2216 /* Return the cost of moving data from a register in class CLASS1 to
2217 one in class CLASS2. A cost of 2 is the default. */
2220 bfin_register_move_cost (enum machine_mode mode,
2221 enum reg_class class1, enum reg_class class2)
2223 /* These need secondary reloads, so they're more expensive. */
2224 if ((class1 == CCREGS && class2 != DREGS)
2225 || (class1 != DREGS && class2 == CCREGS))
2228 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
2232 /* There are some stalls involved when moving from a DREG to a different
2233 class reg, and using the value in one of the following instructions.
2234 Attempt to model this by slightly discouraging such moves. */
2235 if (class1 == DREGS && class2 != DREGS)
2238 if (GET_MODE_CLASS (mode) == MODE_INT)
2240 /* Discourage trying to use the accumulators. */
2241 if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0)
2242 || TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1)
2243 || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0)
2244 || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1))
2250 /* Return the cost of moving data of mode M between a
2251 register and memory. A value of 2 is the default; this cost is
2252 relative to those in `REGISTER_MOVE_COST'.
2254 ??? In theory L1 memory has single-cycle latency. We should add a switch
2255 that tells the compiler whether we expect to use only L1 memory for the
2256 program; it'll make the costs more accurate. */
2259 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2260 enum reg_class rclass,
2261 int in ATTRIBUTE_UNUSED)
2263 /* Make memory accesses slightly more expensive than any register-register
2264 move. Also, penalize non-DP registers, since they need secondary
2265 reloads to load and store. */
2266 if (! reg_class_subset_p (rclass, DPREGS))
2272 /* Inform reload about cases where moving X with a mode MODE to a register in
2273 RCLASS requires an extra scratch register. Return the class needed for the
2274 scratch register. */
2276 static enum reg_class
2277 bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2278 enum machine_mode mode, secondary_reload_info *sri)
2280 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2281 in most other cases we can also use PREGS. */
2282 enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS;
2283 enum reg_class x_class = NO_REGS;
2284 enum rtx_code code = GET_CODE (x);
2287 x = SUBREG_REG (x), code = GET_CODE (x);
2290 int regno = REGNO (x);
2291 if (regno >= FIRST_PSEUDO_REGISTER)
2292 regno = reg_renumber[regno];
2297 x_class = REGNO_REG_CLASS (regno);
2300 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2301 This happens as a side effect of register elimination, and we need
2302 a scratch register to do it. */
2303 if (fp_plus_const_operand (x, mode))
2305 rtx op2 = XEXP (x, 1);
2306 int large_constant_p = ! satisfies_constraint_Ks7 (op2);
2308 if (rclass == PREGS || rclass == PREGS_CLOBBERED)
2310 /* If destination is a DREG, we can do this without a scratch register
2311 if the constant is valid for an add instruction. */
2312 if ((rclass == DREGS || rclass == DPREGS)
2313 && ! large_constant_p)
2315 /* Reloading to anything other than a DREG? Use a PREG scratch
2317 sri->icode = CODE_FOR_reload_insi;
2321 /* Data can usually be moved freely between registers of most classes.
2322 AREGS are an exception; they can only move to or from another register
2323 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2324 if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS)
2325 return (rclass == DREGS || rclass == AREGS || rclass == EVEN_AREGS
2326 || rclass == ODD_AREGS
2329 if (rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS)
2333 sri->icode = in_p ? CODE_FOR_reload_inpdi : CODE_FOR_reload_outpdi;
2337 if (x != const0_rtx && x_class != DREGS)
2345 /* CCREGS can only be moved from/to DREGS. */
2346 if (rclass == CCREGS && x_class != DREGS)
2348 if (x_class == CCREGS && rclass != DREGS)
2351 /* All registers other than AREGS can load arbitrary constants. The only
2352 case that remains is MEM. */
2354 if (! reg_class_subset_p (rclass, default_class))
2355 return default_class;
2360 /* Implement TARGET_HANDLE_OPTION. */
2363 bfin_handle_option (size_t code, const char *arg, int value)
2367 case OPT_mshared_library_id_:
2368 if (value > MAX_LIBRARY_ID)
2369 error ("-mshared-library-id=%s is not between 0 and %d",
2370 arg, MAX_LIBRARY_ID);
2371 bfin_lib_id_given = 1;
2380 while ((p = bfin_cpus[i].name) != NULL)
2382 if (strncmp (arg, p, strlen (p)) == 0)
2389 error ("-mcpu=%s is not valid", arg);
2393 bfin_cpu_type = bfin_cpus[i].type;
2395 q = arg + strlen (p);
2399 bfin_si_revision = bfin_cpus[i].si_revision;
2400 bfin_workarounds |= bfin_cpus[i].workarounds;
2402 else if (strcmp (q, "-none") == 0)
2403 bfin_si_revision = -1;
2404 else if (strcmp (q, "-any") == 0)
2406 bfin_si_revision = 0xffff;
2407 while (bfin_cpus[i].type == bfin_cpu_type)
2409 bfin_workarounds |= bfin_cpus[i].workarounds;
2415 unsigned int si_major, si_minor;
2418 rev_len = strlen (q);
2420 if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
2422 || si_major > 0xff || si_minor > 0xff)
2424 invalid_silicon_revision:
2425 error ("-mcpu=%s has invalid silicon revision", arg);
2429 bfin_si_revision = (si_major << 8) | si_minor;
2431 while (bfin_cpus[i].type == bfin_cpu_type
2432 && bfin_cpus[i].si_revision != bfin_si_revision)
2435 if (bfin_cpus[i].type != bfin_cpu_type)
2436 goto invalid_silicon_revision;
2438 bfin_workarounds |= bfin_cpus[i].workarounds;
2449 static struct machine_function *
2450 bfin_init_machine_status (void)
2452 struct machine_function *f;
2454 f = GGC_CNEW (struct machine_function);
2459 /* Implement the macro OVERRIDE_OPTIONS. */
2462 override_options (void)
2464 /* If processor type is not specified, enable all workarounds. */
2465 if (bfin_cpu_type == BFIN_CPU_UNKNOWN)
2469 for (i = 0; bfin_cpus[i].name != NULL; i++)
2470 bfin_workarounds |= bfin_cpus[i].workarounds;
2472 bfin_si_revision = 0xffff;
2475 if (bfin_csync_anomaly == 1)
2476 bfin_workarounds |= WA_SPECULATIVE_SYNCS;
2477 else if (bfin_csync_anomaly == 0)
2478 bfin_workarounds &= ~WA_SPECULATIVE_SYNCS;
2480 if (bfin_specld_anomaly == 1)
2481 bfin_workarounds |= WA_SPECULATIVE_LOADS;
2482 else if (bfin_specld_anomaly == 0)
2483 bfin_workarounds &= ~WA_SPECULATIVE_LOADS;
2485 if (TARGET_OMIT_LEAF_FRAME_POINTER)
2486 flag_omit_frame_pointer = 1;
2488 /* Library identification */
2489 if (bfin_lib_id_given && ! TARGET_ID_SHARED_LIBRARY)
2490 error ("-mshared-library-id= specified without -mid-shared-library");
2492 if (stack_limit_rtx && TARGET_STACK_CHECK_L1)
2493 error ("Can't use multiple stack checking methods together.");
2495 if (TARGET_ID_SHARED_LIBRARY && TARGET_FDPIC)
2496 error ("ID shared libraries and FD-PIC mode can't be used together.");
2498 /* Don't allow the user to specify -mid-shared-library and -msep-data
2499 together, as it makes little sense from a user's point of view... */
2500 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
2501 error ("cannot specify both -msep-data and -mid-shared-library");
2502 /* ... internally, however, it's nearly the same. */
2503 if (TARGET_SEP_DATA)
2504 target_flags |= MASK_ID_SHARED_LIBRARY | MASK_LEAF_ID_SHARED_LIBRARY;
2506 if (TARGET_ID_SHARED_LIBRARY && flag_pic == 0)
2509 /* There is no single unaligned SI op for PIC code. Sometimes we
2510 need to use ".4byte" and sometimes we need to use ".picptr".
2511 See bfin_assemble_integer for details. */
2513 targetm.asm_out.unaligned_op.si = 0;
2515 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2516 since we don't support it and it'll just break. */
2517 if (flag_pic && !TARGET_FDPIC && !TARGET_ID_SHARED_LIBRARY)
2520 if (TARGET_MULTICORE && bfin_cpu_type != BFIN_CPU_BF561)
2521 error ("-mmulticore can only be used with BF561");
2523 if (TARGET_COREA && !TARGET_MULTICORE)
2524 error ("-mcorea should be used with -mmulticore");
2526 if (TARGET_COREB && !TARGET_MULTICORE)
2527 error ("-mcoreb should be used with -mmulticore");
2529 if (TARGET_COREA && TARGET_COREB)
2530 error ("-mcorea and -mcoreb can't be used together");
2532 flag_schedule_insns = 0;
2534 /* Passes after sched2 can break the helpful TImode annotations that
2535 haifa-sched puts on every insn. Just do scheduling in reorg. */
2536 bfin_flag_schedule_insns2 = flag_schedule_insns_after_reload;
2537 flag_schedule_insns_after_reload = 0;
2539 init_machine_status = bfin_init_machine_status;
2542 /* Return the destination address of BRANCH.
2543 We need to use this instead of get_attr_length, because the
2544 cbranch_with_nops pattern conservatively sets its length to 6, and
2545 we still prefer to use shorter sequences. */
2548 branch_dest (rtx branch)
2552 rtx pat = PATTERN (branch);
2553 if (GET_CODE (pat) == PARALLEL)
2554 pat = XVECEXP (pat, 0, 0);
2555 dest = SET_SRC (pat);
2556 if (GET_CODE (dest) == IF_THEN_ELSE)
2557 dest = XEXP (dest, 1);
2558 dest = XEXP (dest, 0);
2559 dest_uid = INSN_UID (dest);
2560 return INSN_ADDRESSES (dest_uid);
2563 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2564 it's a branch that's predicted taken. */
2567 cbranch_predicted_taken_p (rtx insn)
2569 rtx x = find_reg_note (insn, REG_BR_PROB, 0);
2573 int pred_val = INTVAL (XEXP (x, 0));
2575 return pred_val >= REG_BR_PROB_BASE / 2;
2581 /* Templates for use by asm_conditional_branch. */
2583 static const char *ccbranch_templates[][3] = {
2584 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2585 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2586 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2587 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2590 /* Output INSN, which is a conditional branch instruction with operands
2593 We deal with the various forms of conditional branches that can be generated
2594 by bfin_reorg to prevent the hardware from doing speculative loads, by
2595 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2596 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2597 Either of these is only necessary if the branch is short, otherwise the
2598 template we use ends in an unconditional jump which flushes the pipeline
2602 asm_conditional_branch (rtx insn, rtx *operands, int n_nops, int predict_taken)
2604 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2605 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2606 is to be taken from start of if cc rather than jump.
2607 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2609 int len = (offset >= -1024 && offset <= 1022 ? 0
2610 : offset >= -4094 && offset <= 4096 ? 1
2612 int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p (insn);
2613 int idx = (bp << 1) | (GET_CODE (operands[0]) == EQ ? BRF : BRT);
2614 output_asm_insn (ccbranch_templates[idx][len], operands);
2615 gcc_assert (n_nops == 0 || !bp);
2617 while (n_nops-- > 0)
2618 output_asm_insn ("nop;", NULL);
2621 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2622 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2625 bfin_gen_compare (rtx cmp, enum machine_mode mode ATTRIBUTE_UNUSED)
2627 enum rtx_code code1, code2;
2628 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2629 rtx tem = bfin_cc_rtx;
2630 enum rtx_code code = GET_CODE (cmp);
2632 /* If we have a BImode input, then we already have a compare result, and
2633 do not need to emit another comparison. */
2634 if (GET_MODE (op0) == BImode)
2636 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
2637 tem = op0, code2 = code;
2642 /* bfin has these conditions */
2652 code1 = reverse_condition (code);
2656 emit_insn (gen_rtx_SET (BImode, tem,
2657 gen_rtx_fmt_ee (code1, BImode, op0, op1)));
2660 return gen_rtx_fmt_ee (code2, BImode, tem, CONST0_RTX (BImode));
2663 /* Return nonzero iff C has exactly one bit set if it is interpreted
2664 as a 32-bit constant. */
2667 log2constp (unsigned HOST_WIDE_INT c)
2670 return c != 0 && (c & (c-1)) == 0;
2673 /* Returns the number of consecutive least significant zeros in the binary
2674 representation of *V.
2675 We modify *V to contain the original value arithmetically shifted right by
2676 the number of zeroes. */
2679 shiftr_zero (HOST_WIDE_INT *v)
2681 unsigned HOST_WIDE_INT tmp = *v;
2682 unsigned HOST_WIDE_INT sgn;
2688 sgn = tmp & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1));
2689 while ((tmp & 0x1) == 0 && n <= 32)
2691 tmp = (tmp >> 1) | sgn;
2698 /* After reload, split the load of an immediate constant. OPERANDS are the
2699 operands of the movsi_insn pattern which we are splitting. We return
2700 nonzero if we emitted a sequence to load the constant, zero if we emitted
2701 nothing because we want to use the splitter's default sequence. */
2704 split_load_immediate (rtx operands[])
2706 HOST_WIDE_INT val = INTVAL (operands[1]);
2708 HOST_WIDE_INT shifted = val;
2709 HOST_WIDE_INT shifted_compl = ~val;
2710 int num_zero = shiftr_zero (&shifted);
2711 int num_compl_zero = shiftr_zero (&shifted_compl);
2712 unsigned int regno = REGNO (operands[0]);
2714 /* This case takes care of single-bit set/clear constants, which we could
2715 also implement with BITSET/BITCLR. */
2717 && shifted >= -32768 && shifted < 65536
2718 && (D_REGNO_P (regno)
2719 || (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2)))
2721 emit_insn (gen_movsi (operands[0], GEN_INT (shifted)));
2722 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero)));
2727 tmp |= -(tmp & 0x8000);
2729 /* If high word has one bit set or clear, try to use a bit operation. */
2730 if (D_REGNO_P (regno))
2732 if (log2constp (val & 0xFFFF0000))
2734 emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF)));
2735 emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000)));
2738 else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0)
2740 emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
2741 emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF)));
2745 if (D_REGNO_P (regno))
2747 if (tmp >= -64 && tmp <= 63)
2749 emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
2750 emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536)));
2754 if ((val & 0xFFFF0000) == 0)
2756 emit_insn (gen_movsi (operands[0], const0_rtx));
2757 emit_insn (gen_movsi_low (operands[0], operands[0], operands[1]));
2761 if ((val & 0xFFFF0000) == 0xFFFF0000)
2763 emit_insn (gen_movsi (operands[0], constm1_rtx));
2764 emit_insn (gen_movsi_low (operands[0], operands[0], operands[1]));
2769 /* Need DREGs for the remaining case. */
2774 && num_compl_zero && shifted_compl >= -64 && shifted_compl <= 63)
2776 /* If optimizing for size, generate a sequence that has more instructions
2778 emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl)));
2779 emit_insn (gen_ashlsi3 (operands[0], operands[0],
2780 GEN_INT (num_compl_zero)));
2781 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
2787 /* Return true if the legitimate memory address for a memory operand of mode
2788 MODE. Return false if not. */
2791 bfin_valid_add (enum machine_mode mode, HOST_WIDE_INT value)
2793 unsigned HOST_WIDE_INT v = value > 0 ? value : -value;
2794 int sz = GET_MODE_SIZE (mode);
2795 int shift = sz == 1 ? 0 : sz == 2 ? 1 : 2;
2796 /* The usual offsettable_memref machinery doesn't work so well for this
2797 port, so we deal with the problem here. */
2798 if (value > 0 && sz == 8)
2800 return (v & ~(0x7fff << shift)) == 0;
2804 bfin_valid_reg_p (unsigned int regno, int strict, enum machine_mode mode,
2805 enum rtx_code outer_code)
2808 return REGNO_OK_FOR_BASE_STRICT_P (regno, mode, outer_code, SCRATCH);
2810 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno, mode, outer_code, SCRATCH);
2814 bfin_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2816 switch (GET_CODE (x)) {
2818 if (bfin_valid_reg_p (REGNO (x), strict, mode, MEM))
2822 if (REG_P (XEXP (x, 0))
2823 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS)
2824 && ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode)
2825 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2826 && bfin_valid_add (mode, INTVAL (XEXP (x, 1))))))
2831 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode)
2832 && REG_P (XEXP (x, 0))
2833 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, POST_INC))
2836 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode)
2837 && XEXP (x, 0) == stack_pointer_rtx
2838 && REG_P (XEXP (x, 0))
2839 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PRE_DEC))
2848 /* Decide whether we can force certain constants to memory. If we
2849 decide we can't, the caller should be able to cope with it in
2853 bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
2855 /* We have only one class of non-legitimate constants, and our movsi
2856 expander knows how to handle them. Dropping these constants into the
2857 data section would only shift the problem - we'd still get relocs
2858 outside the object, in the data section rather than the text section. */
2862 /* Ensure that for any constant of the form symbol + offset, the offset
2863 remains within the object. Any other constants are ok.
2864 This ensures that flat binaries never have to deal with relocations
2865 crossing section boundaries. */
2868 bfin_legitimate_constant_p (rtx x)
2871 HOST_WIDE_INT offset;
2873 if (GET_CODE (x) != CONST)
2877 gcc_assert (GET_CODE (x) == PLUS);
2881 if (GET_CODE (sym) != SYMBOL_REF
2882 || GET_CODE (x) != CONST_INT)
2884 offset = INTVAL (x);
2886 if (SYMBOL_REF_DECL (sym) == 0)
2889 || offset >= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym))))
2896 bfin_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
2898 int cost2 = COSTS_N_INSNS (1);
2904 if (outer_code == SET || outer_code == PLUS)
2905 *total = satisfies_constraint_Ks7 (x) ? 0 : cost2;
2906 else if (outer_code == AND)
2907 *total = log2constp (~INTVAL (x)) ? 0 : cost2;
2908 else if (outer_code == LE || outer_code == LT || outer_code == EQ)
2909 *total = (INTVAL (x) >= -4 && INTVAL (x) <= 3) ? 0 : cost2;
2910 else if (outer_code == LEU || outer_code == LTU)
2911 *total = (INTVAL (x) >= 0 && INTVAL (x) <= 7) ? 0 : cost2;
2912 else if (outer_code == MULT)
2913 *total = (INTVAL (x) == 2 || INTVAL (x) == 4) ? 0 : cost2;
2914 else if (outer_code == ASHIFT && (INTVAL (x) == 1 || INTVAL (x) == 2))
2916 else if (outer_code == ASHIFT || outer_code == ASHIFTRT
2917 || outer_code == LSHIFTRT)
2918 *total = (INTVAL (x) >= 0 && INTVAL (x) <= 31) ? 0 : cost2;
2919 else if (outer_code == IOR || outer_code == XOR)
2920 *total = (INTVAL (x) & (INTVAL (x) - 1)) == 0 ? 0 : cost2;
2929 *total = COSTS_N_INSNS (2);
2935 if (GET_MODE (x) == SImode)
2937 if (GET_CODE (op0) == MULT
2938 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
2940 HOST_WIDE_INT val = INTVAL (XEXP (op0, 1));
2941 if (val == 2 || val == 4)
2944 *total += rtx_cost (XEXP (op0, 0), outer_code, speed);
2945 *total += rtx_cost (op1, outer_code, speed);
2950 if (GET_CODE (op0) != REG
2951 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2952 *total += rtx_cost (op0, SET, speed);
2953 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2954 towards creating too many induction variables. */
2955 if (!reg_or_7bit_operand (op1, SImode))
2956 *total += rtx_cost (op1, SET, speed);
2959 else if (GET_MODE (x) == DImode)
2962 if (GET_CODE (op1) != CONST_INT
2963 || !satisfies_constraint_Ks7 (op1))
2964 *total += rtx_cost (op1, PLUS, speed);
2965 if (GET_CODE (op0) != REG
2966 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2967 *total += rtx_cost (op0, PLUS, speed);
2972 if (GET_MODE (x) == DImode)
2981 if (GET_MODE (x) == DImode)
2988 if (GET_CODE (op0) != REG
2989 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2990 *total += rtx_cost (op0, code, speed);
3000 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
3003 if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT)
3004 || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND)
3005 || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
3006 || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT))
3013 if (GET_CODE (op0) != REG
3014 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
3015 *total += rtx_cost (op0, code, speed);
3017 if (GET_MODE (x) == DImode)
3023 if (GET_MODE (x) != SImode)
3028 if (! rhs_andsi3_operand (XEXP (x, 1), SImode))
3029 *total += rtx_cost (XEXP (x, 1), code, speed);
3033 if (! regorlog2_operand (XEXP (x, 1), SImode))
3034 *total += rtx_cost (XEXP (x, 1), code, speed);
3041 if (outer_code == SET
3042 && XEXP (x, 1) == const1_rtx
3043 && GET_CODE (XEXP (x, 2)) == CONST_INT)
3059 if (GET_CODE (op0) == GET_CODE (op1)
3060 && (GET_CODE (op0) == ZERO_EXTEND
3061 || GET_CODE (op0) == SIGN_EXTEND))
3063 *total = COSTS_N_INSNS (1);
3064 op0 = XEXP (op0, 0);
3065 op1 = XEXP (op1, 0);
3068 *total = COSTS_N_INSNS (1);
3070 *total = COSTS_N_INSNS (3);
3072 if (GET_CODE (op0) != REG
3073 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
3074 *total += rtx_cost (op0, MULT, speed);
3075 if (GET_CODE (op1) != REG
3076 && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
3077 *total += rtx_cost (op1, MULT, speed);
3083 *total = COSTS_N_INSNS (32);
3088 if (outer_code == SET)
3097 /* Used for communication between {push,pop}_multiple_operation (which
3098 we use not only as a predicate) and the corresponding output functions. */
3099 static int first_preg_to_save, first_dreg_to_save;
3102 push_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3104 int lastdreg = 8, lastpreg = 6;
3107 first_preg_to_save = lastpreg;
3108 first_dreg_to_save = lastdreg;
3109 for (i = 1, group = 0; i < XVECLEN (op, 0) - 1; i++)
3111 rtx t = XVECEXP (op, 0, i);
3115 if (GET_CODE (t) != SET)
3119 dest = SET_DEST (t);
3120 if (GET_CODE (dest) != MEM || ! REG_P (src))
3122 dest = XEXP (dest, 0);
3123 if (GET_CODE (dest) != PLUS
3124 || ! REG_P (XEXP (dest, 0))
3125 || REGNO (XEXP (dest, 0)) != REG_SP
3126 || GET_CODE (XEXP (dest, 1)) != CONST_INT
3127 || INTVAL (XEXP (dest, 1)) != -i * 4)
3130 regno = REGNO (src);
3133 if (D_REGNO_P (regno))
3136 first_dreg_to_save = lastdreg = regno - REG_R0;
3138 else if (regno >= REG_P0 && regno <= REG_P7)
3141 first_preg_to_save = lastpreg = regno - REG_P0;
3151 if (regno >= REG_P0 && regno <= REG_P7)
3154 first_preg_to_save = lastpreg = regno - REG_P0;
3156 else if (regno != REG_R0 + lastdreg + 1)
3161 else if (group == 2)
3163 if (regno != REG_P0 + lastpreg + 1)
3172 pop_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3174 int lastdreg = 8, lastpreg = 6;
3177 for (i = 1, group = 0; i < XVECLEN (op, 0); i++)
3179 rtx t = XVECEXP (op, 0, i);
3183 if (GET_CODE (t) != SET)
3187 dest = SET_DEST (t);
3188 if (GET_CODE (src) != MEM || ! REG_P (dest))
3190 src = XEXP (src, 0);
3194 if (! REG_P (src) || REGNO (src) != REG_SP)
3197 else if (GET_CODE (src) != PLUS
3198 || ! REG_P (XEXP (src, 0))
3199 || REGNO (XEXP (src, 0)) != REG_SP
3200 || GET_CODE (XEXP (src, 1)) != CONST_INT
3201 || INTVAL (XEXP (src, 1)) != (i - 1) * 4)
3204 regno = REGNO (dest);
3207 if (regno == REG_R7)
3212 else if (regno != REG_P0 + lastpreg - 1)
3217 else if (group == 1)
3219 if (regno != REG_R0 + lastdreg - 1)
3225 first_dreg_to_save = lastdreg;
3226 first_preg_to_save = lastpreg;
3230 /* Emit assembly code for one multi-register push described by INSN, with
3231 operands in OPERANDS. */
3234 output_push_multiple (rtx insn, rtx *operands)
3239 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3240 ok = push_multiple_operation (PATTERN (insn), VOIDmode);
3243 if (first_dreg_to_save == 8)
3244 sprintf (buf, "[--sp] = ( p5:%d );\n", first_preg_to_save);
3245 else if (first_preg_to_save == 6)
3246 sprintf (buf, "[--sp] = ( r7:%d );\n", first_dreg_to_save);
3248 sprintf (buf, "[--sp] = ( r7:%d, p5:%d );\n",
3249 first_dreg_to_save, first_preg_to_save);
3251 output_asm_insn (buf, operands);
3254 /* Emit assembly code for one multi-register pop described by INSN, with
3255 operands in OPERANDS. */
3258 output_pop_multiple (rtx insn, rtx *operands)
3263 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3264 ok = pop_multiple_operation (PATTERN (insn), VOIDmode);
3267 if (first_dreg_to_save == 8)
3268 sprintf (buf, "( p5:%d ) = [sp++];\n", first_preg_to_save);
3269 else if (first_preg_to_save == 6)
3270 sprintf (buf, "( r7:%d ) = [sp++];\n", first_dreg_to_save);
3272 sprintf (buf, "( r7:%d, p5:%d ) = [sp++];\n",
3273 first_dreg_to_save, first_preg_to_save);
3275 output_asm_insn (buf, operands);
3278 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
3281 single_move_for_movmem (rtx dst, rtx src, enum machine_mode mode, HOST_WIDE_INT offset)
3283 rtx scratch = gen_reg_rtx (mode);
3286 srcmem = adjust_address_nv (src, mode, offset);
3287 dstmem = adjust_address_nv (dst, mode, offset);
3288 emit_move_insn (scratch, srcmem);
3289 emit_move_insn (dstmem, scratch);
3292 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
3293 alignment ALIGN_EXP. Return true if successful, false if we should fall
3294 back on a different method. */
3297 bfin_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
3299 rtx srcreg, destreg, countreg;
3300 HOST_WIDE_INT align = 0;
3301 unsigned HOST_WIDE_INT count = 0;
3303 if (GET_CODE (align_exp) == CONST_INT)
3304 align = INTVAL (align_exp);
3305 if (GET_CODE (count_exp) == CONST_INT)
3307 count = INTVAL (count_exp);
3309 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
3314 /* If optimizing for size, only do single copies inline. */
3317 if (count == 2 && align < 2)
3319 if (count == 4 && align < 4)
3321 if (count != 1 && count != 2 && count != 4)
3324 if (align < 2 && count != 1)
3327 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
3328 if (destreg != XEXP (dst, 0))
3329 dst = replace_equiv_address_nv (dst, destreg);
3330 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
3331 if (srcreg != XEXP (src, 0))
3332 src = replace_equiv_address_nv (src, srcreg);
3334 if (count != 0 && align >= 2)
3336 unsigned HOST_WIDE_INT offset = 0;
3340 if ((count & ~3) == 4)
3342 single_move_for_movmem (dst, src, SImode, offset);
3345 else if (count & ~3)
3347 HOST_WIDE_INT new_count = ((count >> 2) & 0x3fffffff) - 1;
3348 countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count));
3350 emit_insn (gen_rep_movsi (destreg, srcreg, countreg, destreg, srcreg));
3354 single_move_for_movmem (dst, src, HImode, offset);
3360 if ((count & ~1) == 2)
3362 single_move_for_movmem (dst, src, HImode, offset);
3365 else if (count & ~1)
3367 HOST_WIDE_INT new_count = ((count >> 1) & 0x7fffffff) - 1;
3368 countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count));
3370 emit_insn (gen_rep_movhi (destreg, srcreg, countreg, destreg, srcreg));
3375 single_move_for_movmem (dst, src, QImode, offset);
3382 /* Compute the alignment for a local variable.
3383 TYPE is the data type, and ALIGN is the alignment that
3384 the object would ordinarily have. The value of this macro is used
3385 instead of that alignment to align the object. */
3388 bfin_local_alignment (tree type, int align)
3390 /* Increasing alignment for (relatively) big types allows the builtin
3391 memcpy can use 32 bit loads/stores. */
3392 if (TYPE_SIZE (type)
3393 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3394 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) > 8
3395 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 32)
3400 /* Implement TARGET_SCHED_ISSUE_RATE. */
3403 bfin_issue_rate (void)
3409 bfin_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3411 enum attr_type insn_type, dep_insn_type;
3412 int dep_insn_code_number;
3414 /* Anti and output dependencies have zero cost. */
3415 if (REG_NOTE_KIND (link) != 0)
3418 dep_insn_code_number = recog_memoized (dep_insn);
3420 /* If we can't recognize the insns, we can't really do anything. */
3421 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
3424 insn_type = get_attr_type (insn);
3425 dep_insn_type = get_attr_type (dep_insn);
3427 if (dep_insn_type == TYPE_MOVE || dep_insn_type == TYPE_MCLD)
3429 rtx pat = PATTERN (dep_insn);
3430 if (GET_CODE (pat) == PARALLEL)
3431 pat = XVECEXP (pat, 0, 0);
3432 rtx dest = SET_DEST (pat);
3433 rtx src = SET_SRC (pat);
3434 if (! ADDRESS_REGNO_P (REGNO (dest))
3435 || ! (MEM_P (src) || D_REGNO_P (REGNO (src))))
3437 return cost + (dep_insn_type == TYPE_MOVE ? 4 : 3);
3444 /* Increment the counter for the number of loop instructions in the
3445 current function. */
3448 bfin_hardware_loop (void)
3450 cfun->machine->has_hardware_loops++;
3453 /* Maximum loop nesting depth. */
3454 #define MAX_LOOP_DEPTH 2
3456 /* Maximum size of a loop. */
3457 #define MAX_LOOP_LENGTH 2042
3459 /* Maximum distance of the LSETUP instruction from the loop start. */
3460 #define MAX_LSETUP_DISTANCE 30
3462 /* We need to keep a vector of loops */
3463 typedef struct loop_info *loop_info;
3464 DEF_VEC_P (loop_info);
3465 DEF_VEC_ALLOC_P (loop_info,heap);
3467 /* Information about a loop we have found (or are in the process of
3469 struct loop_info GTY (())
3471 /* loop number, for dumps */
3474 /* All edges that jump into and out of the loop. */
3475 VEC(edge,gc) *incoming;
3477 /* We can handle two cases: all incoming edges have the same destination
3478 block, or all incoming edges have the same source block. These two
3479 members are set to the common source or destination we found, or NULL
3480 if different blocks were found. If both are NULL the loop can't be
3482 basic_block incoming_src;
3483 basic_block incoming_dest;
3485 /* First block in the loop. This is the one branched to by the loop_end
3489 /* Last block in the loop (the one with the loop_end insn). */
3492 /* The successor block of the loop. This is the one the loop_end insn
3494 basic_block successor;
3496 /* The last instruction in the tail. */
3499 /* The loop_end insn. */
3502 /* The iteration register. */
3505 /* The new initialization insn. */
3508 /* The new initialization instruction. */
3511 /* The new label placed at the beginning of the loop. */
3514 /* The new label placed at the end of the loop. */
3517 /* The length of the loop. */
3520 /* The nesting depth of the loop. */
3523 /* Nonzero if we can't optimize this loop. */
3526 /* True if we have visited this loop. */
3529 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3532 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3535 /* Next loop in the graph. */
3536 struct loop_info *next;
3538 /* Immediate outer loop of this loop. */
3539 struct loop_info *outer;
3541 /* Vector of blocks only within the loop, including those within
3543 VEC (basic_block,heap) *blocks;
3545 /* Same information in a bitmap. */
3546 bitmap block_bitmap;
3548 /* Vector of inner loops within this loop */
3549 VEC (loop_info,heap) *loops;
3553 bfin_dump_loops (loop_info loops)
3557 for (loop = loops; loop; loop = loop->next)
3563 fprintf (dump_file, ";; loop %d: ", loop->loop_no);
3565 fprintf (dump_file, "(bad) ");
3566 fprintf (dump_file, "{head:%d, depth:%d}", loop->head->index, loop->depth);
3568 fprintf (dump_file, " blocks: [ ");
3569 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, b); ix++)
3570 fprintf (dump_file, "%d ", b->index);
3571 fprintf (dump_file, "] ");
3573 fprintf (dump_file, " inner loops: [ ");
3574 for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, i); ix++)
3575 fprintf (dump_file, "%d ", i->loop_no);
3576 fprintf (dump_file, "]\n");
3578 fprintf (dump_file, "\n");
3581 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3582 BB. Return true, if we find it. */
3585 bfin_bb_in_loop (loop_info loop, basic_block bb)
3587 return bitmap_bit_p (loop->block_bitmap, bb->index);
3590 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3591 REG. Return true, if we find any. Don't count the loop's loop_end
3592 insn if it matches LOOP_END. */
3595 bfin_scan_loop (loop_info loop, rtx reg, rtx loop_end)
3600 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++)
3604 for (insn = BB_HEAD (bb);
3605 insn != NEXT_INSN (BB_END (bb));
3606 insn = NEXT_INSN (insn))
3610 if (insn == loop_end)
3612 if (reg_mentioned_p (reg, PATTERN (insn)))
3619 /* Estimate the length of INSN conservatively. */
3622 length_for_loop (rtx insn)
3625 if (JUMP_P (insn) && any_condjump_p (insn) && !optimize_size)
3627 if (ENABLE_WA_SPECULATIVE_SYNCS)
3629 else if (ENABLE_WA_SPECULATIVE_LOADS)
3632 else if (LABEL_P (insn))
3634 if (ENABLE_WA_SPECULATIVE_SYNCS)
3639 length += get_attr_length (insn);
3644 /* Optimize LOOP. */
3647 bfin_optimize_loop (loop_info loop)
3651 rtx insn, init_insn, last_insn, nop_insn;
3652 rtx loop_init, start_label, end_label;
3653 rtx reg_lc0, reg_lc1, reg_lt0, reg_lt1, reg_lb0, reg_lb1;
3655 rtx lc_reg, lt_reg, lb_reg;
3659 int inner_depth = 0;
3669 fprintf (dump_file, ";; loop %d bad when found\n", loop->loop_no);
3673 /* Every loop contains in its list of inner loops every loop nested inside
3674 it, even if there are intermediate loops. This works because we're doing
3675 a depth-first search here and never visit a loop more than once. */
3676 for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, inner); ix++)
3678 bfin_optimize_loop (inner);
3680 if (!inner->bad && inner_depth < inner->depth)
3682 inner_depth = inner->depth;
3684 loop->clobber_loop0 |= inner->clobber_loop0;
3685 loop->clobber_loop1 |= inner->clobber_loop1;
3689 loop->depth = inner_depth + 1;
3690 if (loop->depth > MAX_LOOP_DEPTH)
3693 fprintf (dump_file, ";; loop %d too deep\n", loop->loop_no);
3697 /* Get the loop iteration register. */
3698 iter_reg = loop->iter_reg;
3700 if (!DPREG_P (iter_reg))
3703 fprintf (dump_file, ";; loop %d iteration count NOT in PREG or DREG\n",
3708 if (loop->incoming_src)
3710 /* Make sure the predecessor is before the loop start label, as required by
3711 the LSETUP instruction. */
3713 for (insn = BB_END (loop->incoming_src);
3714 insn && insn != loop->start_label;
3715 insn = NEXT_INSN (insn))
3716 length += length_for_loop (insn);
3721 fprintf (dump_file, ";; loop %d lsetup not before loop_start\n",
3726 if (length > MAX_LSETUP_DISTANCE)
3729 fprintf (dump_file, ";; loop %d lsetup too far away\n", loop->loop_no);
3734 /* Check if start_label appears before loop_end and calculate the
3735 offset between them. We calculate the length of instructions
3738 for (insn = loop->start_label;
3739 insn && insn != loop->loop_end;
3740 insn = NEXT_INSN (insn))
3741 length += length_for_loop (insn);
3746 fprintf (dump_file, ";; loop %d start_label not before loop_end\n",
3751 loop->length = length;
3752 if (loop->length > MAX_LOOP_LENGTH)
3755 fprintf (dump_file, ";; loop %d too long\n", loop->loop_no);
3759 /* Scan all the blocks to make sure they don't use iter_reg. */
3760 if (bfin_scan_loop (loop, iter_reg, loop->loop_end))
3763 fprintf (dump_file, ";; loop %d uses iterator\n", loop->loop_no);
3767 /* Scan all the insns to see if the loop body clobber
3768 any hardware loop registers. */
3770 reg_lc0 = gen_rtx_REG (SImode, REG_LC0);
3771 reg_lc1 = gen_rtx_REG (SImode, REG_LC1);
3772 reg_lt0 = gen_rtx_REG (SImode, REG_LT0);
3773 reg_lt1 = gen_rtx_REG (SImode, REG_LT1);
3774 reg_lb0 = gen_rtx_REG (SImode, REG_LB0);
3775 reg_lb1 = gen_rtx_REG (SImode, REG_LB1);
3777 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++)
3781 for (insn = BB_HEAD (bb);
3782 insn != NEXT_INSN (BB_END (bb));
3783 insn = NEXT_INSN (insn))
3788 if (reg_set_p (reg_lc0, insn)
3789 || reg_set_p (reg_lt0, insn)
3790 || reg_set_p (reg_lb0, insn))
3791 loop->clobber_loop0 = 1;
3793 if (reg_set_p (reg_lc1, insn)
3794 || reg_set_p (reg_lt1, insn)
3795 || reg_set_p (reg_lb1, insn))
3796 loop->clobber_loop1 |= 1;
3800 if ((loop->clobber_loop0 && loop->clobber_loop1)
3801 || (loop->depth == MAX_LOOP_DEPTH && loop->clobber_loop0))
3803 loop->depth = MAX_LOOP_DEPTH + 1;
3805 fprintf (dump_file, ";; loop %d no loop reg available\n",
3810 /* There should be an instruction before the loop_end instruction
3811 in the same basic block. And the instruction must not be
3813 - CONDITIONAL BRANCH
3817 - Returns (RTS, RTN, etc.) */
3820 last_insn = PREV_INSN (loop->loop_end);
3824 for (; last_insn != PREV_INSN (BB_HEAD (bb));
3825 last_insn = PREV_INSN (last_insn))
3826 if (INSN_P (last_insn))
3829 if (last_insn != PREV_INSN (BB_HEAD (bb)))
3832 if (single_pred_p (bb)
3833 && single_pred (bb) != ENTRY_BLOCK_PTR)
3835 bb = single_pred (bb);
3836 last_insn = BB_END (bb);
3841 last_insn = NULL_RTX;
3849 fprintf (dump_file, ";; loop %d has no last instruction\n",
3854 if (JUMP_P (last_insn))
3856 loop_info inner = (loop_info) bb->aux;
3858 && inner->outer == loop
3859 && inner->loop_end == last_insn
3860 && inner->depth == 1)
3861 /* This jump_insn is the exact loop_end of an inner loop
3862 and to be optimized away. So use the inner's last_insn. */
3863 last_insn = inner->last_insn;
3867 fprintf (dump_file, ";; loop %d has bad last instruction\n",
3872 else if (CALL_P (last_insn)
3873 || (GET_CODE (PATTERN (last_insn)) != SEQUENCE
3874 && get_attr_type (last_insn) == TYPE_SYNC)
3875 || recog_memoized (last_insn) == CODE_FOR_return_internal)
3878 fprintf (dump_file, ";; loop %d has bad last instruction\n",
3883 if (GET_CODE (PATTERN (last_insn)) == ASM_INPUT
3884 || asm_noperands (PATTERN (last_insn)) >= 0
3885 || (GET_CODE (PATTERN (last_insn)) != SEQUENCE
3886 && get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI))
3888 nop_insn = emit_insn_after (gen_nop (), last_insn);
3889 last_insn = nop_insn;
3892 loop->last_insn = last_insn;
3894 /* The loop is good for replacement. */
3895 start_label = loop->start_label;
3896 end_label = gen_label_rtx ();
3897 iter_reg = loop->iter_reg;
3899 if (loop->depth == 1 && !loop->clobber_loop1)
3904 loop->clobber_loop1 = 1;
3911 loop->clobber_loop0 = 1;
3914 /* If iter_reg is a DREG, we need generate an instruction to load
3915 the loop count into LC register. */
3916 if (D_REGNO_P (REGNO (iter_reg)))
3918 init_insn = gen_movsi (lc_reg, iter_reg);
3919 loop_init = gen_lsetup_without_autoinit (lt_reg, start_label,
3923 else if (P_REGNO_P (REGNO (iter_reg)))
3925 init_insn = NULL_RTX;
3926 loop_init = gen_lsetup_with_autoinit (lt_reg, start_label,
3933 loop->init = init_insn;
3934 loop->end_label = end_label;
3935 loop->loop_init = loop_init;
3939 fprintf (dump_file, ";; replacing loop %d initializer with\n",
3941 print_rtl_single (dump_file, loop->loop_init);
3942 fprintf (dump_file, ";; replacing loop %d terminator with\n",
3944 print_rtl_single (dump_file, loop->loop_end);
3949 if (loop->init != NULL_RTX)
3950 emit_insn (loop->init);
3951 seq_end = emit_insn (loop->loop_init);
3956 if (loop->incoming_src)
3958 rtx prev = BB_END (loop->incoming_src);
3959 if (VEC_length (edge, loop->incoming) > 1
3960 || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU))
3962 gcc_assert (JUMP_P (prev));
3963 prev = PREV_INSN (prev);
3965 emit_insn_after (seq, prev);
3973 if (loop->head != loop->incoming_dest)
3975 FOR_EACH_EDGE (e, ei, loop->head->preds)
3977 if (e->flags & EDGE_FALLTHRU)
3979 rtx newjump = gen_jump (loop->start_label);
3980 emit_insn_before (newjump, BB_HEAD (loop->head));
3981 new_bb = create_basic_block (newjump, newjump, loop->head->prev_bb);
3982 gcc_assert (new_bb = loop->head->prev_bb);
3988 emit_insn_before (seq, BB_HEAD (loop->head));
3989 seq = emit_label_before (gen_label_rtx (), seq);
3991 new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb);
3992 FOR_EACH_EDGE (e, ei, loop->incoming)
3994 if (!(e->flags & EDGE_FALLTHRU)
3995 || e->dest != loop->head)
3996 redirect_edge_and_branch_force (e, new_bb);
3998 redirect_edge_succ (e, new_bb);
4002 delete_insn (loop->loop_end);
4003 /* Insert the loop end label before the last instruction of the loop. */
4004 emit_label_before (loop->end_label, loop->last_insn);
4011 fprintf (dump_file, ";; loop %d is bad\n", loop->loop_no);
4015 if (DPREG_P (loop->iter_reg))
4017 /* If loop->iter_reg is a DREG or PREG, we can split it here
4018 without scratch register. */
4021 emit_insn_before (gen_addsi3 (loop->iter_reg,
4026 emit_insn_before (gen_cmpsi (loop->iter_reg, const0_rtx),
4029 insn = emit_jump_insn_before (gen_bne (loop->start_label),
4032 JUMP_LABEL (insn) = loop->start_label;
4033 LABEL_NUSES (loop->start_label)++;
4034 delete_insn (loop->loop_end);
4038 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
4039 a newly set up structure describing the loop, it is this function's
4040 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
4041 loop_end insn and its enclosing basic block. */
4044 bfin_discover_loop (loop_info loop, basic_block tail_bb, rtx tail_insn)
4048 VEC (basic_block,heap) *works = VEC_alloc (basic_block,heap,20);
4050 loop->tail = tail_bb;
4051 loop->head = BRANCH_EDGE (tail_bb)->dest;
4052 loop->successor = FALLTHRU_EDGE (tail_bb)->dest;
4053 loop->loop_end = tail_insn;
4054 loop->last_insn = NULL_RTX;
4055 loop->iter_reg = SET_DEST (XVECEXP (PATTERN (tail_insn), 0, 1));
4056 loop->depth = loop->length = 0;
4058 loop->clobber_loop0 = loop->clobber_loop1 = 0;
4061 loop->incoming = VEC_alloc (edge, gc, 2);
4062 loop->init = loop->loop_init = NULL_RTX;
4063 loop->start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn), 0, 0)), 1), 0);
4064 loop->end_label = NULL_RTX;
4067 VEC_safe_push (basic_block, heap, works, loop->head);
4069 while (VEC_iterate (basic_block, works, dwork++, bb))
4073 if (bb == EXIT_BLOCK_PTR)
4075 /* We've reached the exit block. The loop must be bad. */
4078 ";; Loop is bad - reached exit block while scanning\n");
4083 if (bitmap_bit_p (loop->block_bitmap, bb->index))
4086 /* We've not seen this block before. Add it to the loop's
4087 list and then add each successor to the work list. */
4089 VEC_safe_push (basic_block, heap, loop->blocks, bb);
4090 bitmap_set_bit (loop->block_bitmap, bb->index);
4094 FOR_EACH_EDGE (e, ei, bb->succs)
4096 basic_block succ = EDGE_SUCC (bb, ei.index)->dest;
4097 if (!REGNO_REG_SET_P (df_get_live_in (succ),
4098 REGNO (loop->iter_reg)))
4100 if (!VEC_space (basic_block, works, 1))
4104 VEC_block_remove (basic_block, works, 0, dwork);
4108 VEC_reserve (basic_block, heap, works, 1);
4110 VEC_quick_push (basic_block, works, succ);
4115 /* Find the predecessor, and make sure nothing else jumps into this loop. */
4119 for (dwork = 0; VEC_iterate (basic_block, loop->blocks, dwork, bb); dwork++)
4123 FOR_EACH_EDGE (e, ei, bb->preds)
4125 basic_block pred = e->src;
4127 if (!bfin_bb_in_loop (loop, pred))
4130 fprintf (dump_file, ";; Loop %d: incoming edge %d -> %d\n",
4131 loop->loop_no, pred->index,
4133 VEC_safe_push (edge, gc, loop->incoming, e);
4138 for (pass = 0, retry = 1; retry && pass < 2; pass++)
4145 FOR_EACH_EDGE (e, ei, loop->incoming)
4149 loop->incoming_src = e->src;
4150 loop->incoming_dest = e->dest;
4155 if (e->dest != loop->incoming_dest)
4156 loop->incoming_dest = NULL;
4157 if (e->src != loop->incoming_src)
4158 loop->incoming_src = NULL;
4160 if (loop->incoming_src == NULL && loop->incoming_dest == NULL)
4166 ";; retrying loop %d with forwarder blocks\n",
4174 ";; can't find suitable entry for loop %d\n",
4182 FOR_EACH_EDGE (e, ei, loop->incoming)
4184 if (forwarder_block_p (e->src))
4191 ";; Adding forwarder block %d to loop %d and retrying\n",
4192 e->src->index, loop->loop_no);
4193 VEC_safe_push (basic_block, heap, loop->blocks, e->src);
4194 bitmap_set_bit (loop->block_bitmap, e->src->index);
4195 FOR_EACH_EDGE (e2, ei2, e->src->preds)
4196 VEC_safe_push (edge, gc, loop->incoming, e2);
4197 VEC_unordered_remove (edge, loop->incoming, ei.index);
4207 VEC_free (basic_block, heap, works);
4210 /* Analyze the structure of the loops in the current function. Use STACK
4211 for bitmap allocations. Returns all the valid candidates for hardware
4212 loops found in this function. */
4214 bfin_discover_loops (bitmap_obstack *stack, FILE *dump_file)
4216 loop_info loops = NULL;
4222 /* Find all the possible loop tails. This means searching for every
4223 loop_end instruction. For each one found, create a loop_info
4224 structure and add the head block to the work list. */
4227 rtx tail = BB_END (bb);
4229 while (GET_CODE (tail) == NOTE)
4230 tail = PREV_INSN (tail);
4234 if (INSN_P (tail) && recog_memoized (tail) == CODE_FOR_loop_end)
4237 /* A possible loop end */
4239 /* There's a degenerate case we can handle - an empty loop consisting
4240 of only a back branch. Handle that by deleting the branch. */
4241 insn = BB_HEAD (BRANCH_EDGE (bb)->dest);
4242 if (next_real_insn (insn) == tail)
4246 fprintf (dump_file, ";; degenerate loop ending at\n");
4247 print_rtl_single (dump_file, tail);
4249 delete_insn_and_edges (tail);
4253 loop = XNEW (struct loop_info);
4256 loop->loop_no = nloops++;
4257 loop->blocks = VEC_alloc (basic_block, heap, 20);
4258 loop->block_bitmap = BITMAP_ALLOC (stack);
4263 fprintf (dump_file, ";; potential loop %d ending at\n",
4265 print_rtl_single (dump_file, tail);
4268 bfin_discover_loop (loop, bb, tail);
4272 tmp_bitmap = BITMAP_ALLOC (stack);
4273 /* Compute loop nestings. */
4274 for (loop = loops; loop; loop = loop->next)
4280 for (other = loop->next; other; other = other->next)
4285 bitmap_and (tmp_bitmap, other->block_bitmap, loop->block_bitmap);
4286 if (bitmap_empty_p (tmp_bitmap))
4288 if (bitmap_equal_p (tmp_bitmap, other->block_bitmap))
4290 other->outer = loop;
4291 VEC_safe_push (loop_info, heap, loop->loops, other);
4293 else if (bitmap_equal_p (tmp_bitmap, loop->block_bitmap))
4295 loop->outer = other;
4296 VEC_safe_push (loop_info, heap, other->loops, loop);
4302 ";; can't find suitable nesting for loops %d and %d\n",
4303 loop->loop_no, other->loop_no);
4304 loop->bad = other->bad = 1;
4308 BITMAP_FREE (tmp_bitmap);
4313 /* Free up the loop structures in LOOPS. */
4315 free_loops (loop_info loops)
4319 loop_info loop = loops;
4321 VEC_free (loop_info, heap, loop->loops);
4322 VEC_free (basic_block, heap, loop->blocks);
4323 BITMAP_FREE (loop->block_bitmap);
4328 #define BB_AUX_INDEX(BB) ((unsigned)(BB)->aux)
4330 /* The taken-branch edge from the loop end can actually go forward. Since the
4331 Blackfin's LSETUP instruction requires that the loop end be after the loop
4332 start, try to reorder a loop's basic blocks when we find such a case. */
4334 bfin_reorder_loops (loop_info loops, FILE *dump_file)
4341 cfg_layout_initialize (0);
4343 for (loop = loops; loop; loop = loop->next)
4353 /* Recreate an index for basic blocks that represents their order. */
4354 for (bb = ENTRY_BLOCK_PTR->next_bb, index = 0;
4355 bb != EXIT_BLOCK_PTR;
4356 bb = bb->next_bb, index++)
4357 bb->aux = (PTR) index;
4359 if (BB_AUX_INDEX (loop->head) < BB_AUX_INDEX (loop->tail))
4362 FOR_EACH_EDGE (e, ei, loop->head->succs)
4364 if (bitmap_bit_p (loop->block_bitmap, e->dest->index)
4365 && BB_AUX_INDEX (e->dest) < BB_AUX_INDEX (loop->tail))
4367 basic_block start_bb = e->dest;
4368 basic_block start_prev_bb = start_bb->prev_bb;
4371 fprintf (dump_file, ";; Moving block %d before block %d\n",
4372 loop->head->index, start_bb->index);
4373 loop->head->prev_bb->next_bb = loop->head->next_bb;
4374 loop->head->next_bb->prev_bb = loop->head->prev_bb;
4376 loop->head->prev_bb = start_prev_bb;
4377 loop->head->next_bb = start_bb;
4378 start_prev_bb->next_bb = start_bb->prev_bb = loop->head;
4382 loops = loops->next;
4387 if (bb->next_bb != EXIT_BLOCK_PTR)
4388 bb->aux = bb->next_bb;
4392 cfg_layout_finalize ();
4396 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4397 and tries to rewrite the RTL of these loops so that proper Blackfin
4398 hardware loops are generated. */
4401 bfin_reorg_loops (FILE *dump_file)
4403 loop_info loops = NULL;
4406 bitmap_obstack stack;
4408 bitmap_obstack_initialize (&stack);
4411 fprintf (dump_file, ";; Find loops, first pass\n\n");
4413 loops = bfin_discover_loops (&stack, dump_file);
4416 bfin_dump_loops (loops);
4418 bfin_reorder_loops (loops, dump_file);
4422 fprintf (dump_file, ";; Find loops, second pass\n\n");
4424 loops = bfin_discover_loops (&stack, dump_file);
4427 fprintf (dump_file, ";; All loops found:\n\n");
4428 bfin_dump_loops (loops);
4431 /* Now apply the optimizations. */
4432 for (loop = loops; loop; loop = loop->next)
4433 bfin_optimize_loop (loop);
4437 fprintf (dump_file, ";; After hardware loops optimization:\n\n");
4438 bfin_dump_loops (loops);
4444 print_rtl (dump_file, get_insns ());
4450 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
4451 Returns true if we modified the insn chain, false otherwise. */
4453 gen_one_bundle (rtx slot[3])
4455 gcc_assert (slot[1] != NULL_RTX);
4457 /* Verify that we really can do the multi-issue. */
4460 rtx t = NEXT_INSN (slot[0]);
4461 while (t != slot[1])
4463 if (GET_CODE (t) != NOTE
4464 || NOTE_KIND (t) != NOTE_INSN_DELETED)
4471 rtx t = NEXT_INSN (slot[1]);
4472 while (t != slot[2])
4474 if (GET_CODE (t) != NOTE
4475 || NOTE_KIND (t) != NOTE_INSN_DELETED)
4481 if (slot[0] == NULL_RTX)
4483 slot[0] = emit_insn_before (gen_mnop (), slot[1]);
4484 df_insn_rescan (slot[0]);
4486 if (slot[2] == NULL_RTX)
4488 slot[2] = emit_insn_after (gen_forced_nop (), slot[1]);
4489 df_insn_rescan (slot[2]);
4492 /* Avoid line number information being printed inside one bundle. */
4493 if (INSN_LOCATOR (slot[1])
4494 && INSN_LOCATOR (slot[1]) != INSN_LOCATOR (slot[0]))
4495 INSN_LOCATOR (slot[1]) = INSN_LOCATOR (slot[0]);
4496 if (INSN_LOCATOR (slot[2])
4497 && INSN_LOCATOR (slot[2]) != INSN_LOCATOR (slot[0]))
4498 INSN_LOCATOR (slot[2]) = INSN_LOCATOR (slot[0]);
4500 /* Terminate them with "|| " instead of ";" in the output. */
4501 PUT_MODE (slot[0], SImode);
4502 PUT_MODE (slot[1], SImode);
4503 /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */
4504 PUT_MODE (slot[2], QImode);
4508 /* Go through all insns, and use the information generated during scheduling
4509 to generate SEQUENCEs to represent bundles of instructions issued
4513 bfin_gen_bundles (void)
4522 slot[0] = slot[1] = slot[2] = NULL_RTX;
4523 for (insn = BB_HEAD (bb);; insn = next)
4528 if (get_attr_type (insn) == TYPE_DSP32)
4530 else if (slot[1] == NULL_RTX)
4537 next = NEXT_INSN (insn);
4538 while (next && insn != BB_END (bb)
4540 && GET_CODE (PATTERN (next)) != USE
4541 && GET_CODE (PATTERN (next)) != CLOBBER))
4544 next = NEXT_INSN (insn);
4547 /* BB_END can change due to emitting extra NOPs, so check here. */
4548 at_end = insn == BB_END (bb);
4549 if (at_end || GET_MODE (next) == TImode)
4552 || !gen_one_bundle (slot))
4553 && slot[0] != NULL_RTX)
4555 rtx pat = PATTERN (slot[0]);
4556 if (GET_CODE (pat) == SET
4557 && GET_CODE (SET_SRC (pat)) == UNSPEC
4558 && XINT (SET_SRC (pat), 1) == UNSPEC_32BIT)
4560 SET_SRC (pat) = XVECEXP (SET_SRC (pat), 0, 0);
4561 INSN_CODE (slot[0]) = -1;
4562 df_insn_rescan (slot[0]);
4566 slot[0] = slot[1] = slot[2] = NULL_RTX;
4574 /* Ensure that no var tracking notes are emitted in the middle of a
4575 three-instruction bundle. */
4578 reorder_var_tracking_notes (void)
4584 rtx queue = NULL_RTX;
4585 bool in_bundle = false;
4587 for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
4589 next = NEXT_INSN (insn);
4593 /* Emit queued up notes at the last instruction of a bundle. */
4594 if (GET_MODE (insn) == QImode)
4598 rtx next_queue = PREV_INSN (queue);
4599 PREV_INSN (NEXT_INSN (insn)) = queue;
4600 NEXT_INSN (queue) = NEXT_INSN (insn);
4601 NEXT_INSN (insn) = queue;
4602 PREV_INSN (queue) = insn;
4607 else if (GET_MODE (insn) == SImode)
4610 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
4614 rtx prev = PREV_INSN (insn);
4615 PREV_INSN (next) = prev;
4616 NEXT_INSN (prev) = next;
4618 PREV_INSN (insn) = queue;
4626 /* Return an insn type for INSN that can be used by the caller for anomaly
4627 workarounds. This differs from plain get_attr_type in that it handles
4630 static enum attr_type
4631 type_for_anomaly (rtx insn)
4633 rtx pat = PATTERN (insn);
4634 if (GET_CODE (pat) == SEQUENCE)
4637 t = get_attr_type (XVECEXP (pat, 0, 1));
4640 t = get_attr_type (XVECEXP (pat, 0, 2));
4646 return get_attr_type (insn);
4649 /* Return nonzero if INSN contains any loads that may trap. It handles
4650 SEQUENCEs correctly. */
4653 trapping_loads_p (rtx insn)
4655 rtx pat = PATTERN (insn);
4656 if (GET_CODE (pat) == SEQUENCE)
4659 t = get_attr_type (XVECEXP (pat, 0, 1));
4661 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 1)))))
4663 t = get_attr_type (XVECEXP (pat, 0, 2));
4665 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 2)))))
4670 return may_trap_p (SET_SRC (single_set (insn)));
4673 /* This function acts like NEXT_INSN, but is aware of three-insn bundles and
4674 skips all subsequent parallel instructions if INSN is the start of such
4677 find_next_insn_start (rtx insn)
4679 if (GET_MODE (insn) == SImode)
4681 while (GET_MODE (insn) != QImode)
4682 insn = NEXT_INSN (insn);
4684 return NEXT_INSN (insn);
4687 /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of
4688 a three-insn bundle, see if one of them is a load and return that if so.
4689 Return NULL_RTX if the insn does not contain loads. */
4691 find_load (rtx insn)
4693 if (get_attr_type (insn) == TYPE_MCLD)
4695 if (GET_MODE (insn) != SImode)
4698 insn = NEXT_INSN (insn);
4699 if ((GET_MODE (insn) == SImode || GET_MODE (insn) == QImode)
4700 && get_attr_type (insn) == TYPE_MCLD)
4702 } while (GET_MODE (insn) != QImode);
4706 /* We use the machine specific reorg pass for emitting CSYNC instructions
4707 after conditional branches as needed.
4709 The Blackfin is unusual in that a code sequence like
4712 may speculatively perform the load even if the condition isn't true. This
4713 happens for a branch that is predicted not taken, because the pipeline
4714 isn't flushed or stalled, so the early stages of the following instructions,
4715 which perform the memory reference, are allowed to execute before the
4716 jump condition is evaluated.
4717 Therefore, we must insert additional instructions in all places where this
4718 could lead to incorrect behavior. The manual recommends CSYNC, while
4719 VDSP seems to use NOPs (even though its corresponding compiler option is
4722 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
4723 When optimizing for size, we turn the branch into a predicted taken one.
4724 This may be slower due to mispredicts, but saves code size. */
4730 rtx last_condjump = NULL_RTX;
4731 int cycles_since_jump = INT_MAX;
4733 /* We are freeing block_for_insn in the toplev to keep compatibility
4734 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4735 compute_bb_for_insn ();
4737 if (bfin_flag_schedule_insns2)
4739 splitting_for_sched = 1;
4741 splitting_for_sched = 0;
4743 timevar_push (TV_SCHED2);
4745 timevar_pop (TV_SCHED2);
4747 /* Examine the schedule and insert nops as necessary for 64-bit parallel
4749 bfin_gen_bundles ();
4754 /* Doloop optimization */
4755 if (cfun->machine->has_hardware_loops)
4756 bfin_reorg_loops (dump_file);
4758 if (! ENABLE_WA_SPECULATIVE_LOADS && ! ENABLE_WA_SPECULATIVE_SYNCS)
4761 /* First pass: find predicted-false branches; if something after them
4762 needs nops, insert them or change the branch to predict true. */
4763 for (insn = get_insns (); insn; insn = next)
4767 next = find_next_insn_start (insn);
4769 if (NOTE_P (insn) || BARRIER_P (insn) || LABEL_P (insn))
4772 pat = PATTERN (insn);
4773 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
4774 || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC
4775 || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0)
4780 if (any_condjump_p (insn)
4781 && ! cbranch_predicted_taken_p (insn))
4783 last_condjump = insn;
4784 cycles_since_jump = 0;
4787 cycles_since_jump = INT_MAX;
4789 else if (INSN_P (insn))
4791 rtx load_insn = find_load (insn);
4792 enum attr_type type = type_for_anomaly (insn);
4793 int delay_needed = 0;
4794 if (cycles_since_jump < INT_MAX)
4795 cycles_since_jump++;
4797 if (load_insn && ENABLE_WA_SPECULATIVE_LOADS)
4799 if (trapping_loads_p (load_insn))
4802 else if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS)
4805 if (delay_needed > cycles_since_jump)
4809 rtx *op = recog_data.operand;
4811 delay_needed -= cycles_since_jump;
4813 extract_insn (last_condjump);
4816 pat = gen_cbranch_predicted_taken (op[0], op[1], op[2],
4818 cycles_since_jump = INT_MAX;
4821 /* Do not adjust cycles_since_jump in this case, so that
4822 we'll increase the number of NOPs for a subsequent insn
4824 pat = gen_cbranch_with_nops (op[0], op[1], op[2], op[3],
4825 GEN_INT (delay_needed));
4826 PATTERN (last_condjump) = pat;
4827 INSN_CODE (last_condjump) = recog (pat, insn, &num_clobbers);
4831 /* Second pass: for predicted-true branches, see if anything at the
4832 branch destination needs extra nops. */
4833 if (! ENABLE_WA_SPECULATIVE_SYNCS)
4836 if (! ENABLE_WA_RETS)
4839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4842 && any_condjump_p (insn)
4843 && (INSN_CODE (insn) == CODE_FOR_cbranch_predicted_taken
4844 || cbranch_predicted_taken_p (insn)))
4846 rtx target = JUMP_LABEL (insn);
4848 cycles_since_jump = 0;
4849 for (; target && cycles_since_jump < 3; target = NEXT_INSN (target))
4853 if (NOTE_P (target) || BARRIER_P (target) || LABEL_P (target))
4856 pat = PATTERN (target);
4857 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
4858 || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC
4859 || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0)
4862 if (INSN_P (target))
4864 enum attr_type type = type_for_anomaly (target);
4865 int delay_needed = 0;
4866 if (cycles_since_jump < INT_MAX)
4867 cycles_since_jump++;
4869 if (type == TYPE_SYNC && ENABLE_WA_SPECULATIVE_SYNCS)
4872 if (delay_needed > cycles_since_jump)
4874 rtx prev = prev_real_insn (label);
4875 delay_needed -= cycles_since_jump;
4877 fprintf (dump_file, "Adding %d nops after %d\n",
4878 delay_needed, INSN_UID (label));
4880 && INSN_CODE (prev) == CODE_FOR_cbranch_with_nops)
4887 "Reducing nops on insn %d.\n",
4890 x = XVECEXP (x, 0, 1);
4891 v = INTVAL (XVECEXP (x, 0, 0)) - delay_needed;
4892 XVECEXP (x, 0, 0) = GEN_INT (v);
4894 while (delay_needed-- > 0)
4895 emit_insn_after (gen_nop (), label);
4903 if (bfin_flag_var_tracking)
4905 timevar_push (TV_VAR_TRACKING);
4906 variable_tracking_main ();
4907 reorder_var_tracking_notes ();
4908 timevar_pop (TV_VAR_TRACKING);
4910 df_finish_pass (false);
4913 /* Handle interrupt_handler, exception_handler and nmi_handler function
4914 attributes; arguments as in struct attribute_spec.handler. */
4917 handle_int_attribute (tree *node, tree name,
4918 tree args ATTRIBUTE_UNUSED,
4919 int flags ATTRIBUTE_UNUSED,
4923 if (TREE_CODE (x) == FUNCTION_DECL)
4926 if (TREE_CODE (x) != FUNCTION_TYPE)
4928 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4929 IDENTIFIER_POINTER (name));
4930 *no_add_attrs = true;
4932 else if (funkind (x) != SUBROUTINE)
4933 error ("multiple function type attributes specified");
4938 /* Return 0 if the attributes for two types are incompatible, 1 if they
4939 are compatible, and 2 if they are nearly compatible (which causes a
4940 warning to be generated). */
4943 bfin_comp_type_attributes (const_tree type1, const_tree type2)
4945 e_funkind kind1, kind2;
4947 if (TREE_CODE (type1) != FUNCTION_TYPE)
4950 kind1 = funkind (type1);
4951 kind2 = funkind (type2);
4956 /* Check for mismatched modifiers */
4957 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1))
4958 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2)))
4961 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1))
4962 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2)))
4965 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1))
4966 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2)))
4969 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1))
4970 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2)))
4976 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4977 struct attribute_spec.handler. */
4980 bfin_handle_longcall_attribute (tree *node, tree name,
4981 tree args ATTRIBUTE_UNUSED,
4982 int flags ATTRIBUTE_UNUSED,
4985 if (TREE_CODE (*node) != FUNCTION_TYPE
4986 && TREE_CODE (*node) != FIELD_DECL
4987 && TREE_CODE (*node) != TYPE_DECL)
4989 warning (OPT_Wattributes, "`%s' attribute only applies to functions",
4990 IDENTIFIER_POINTER (name));
4991 *no_add_attrs = true;
4994 if ((strcmp (IDENTIFIER_POINTER (name), "longcall") == 0
4995 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node)))
4996 || (strcmp (IDENTIFIER_POINTER (name), "shortcall") == 0
4997 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node))))
4999 warning (OPT_Wattributes,
5000 "can't apply both longcall and shortcall attributes to the same function");
5001 *no_add_attrs = true;
5007 /* Handle a "l1_text" attribute; arguments as in
5008 struct attribute_spec.handler. */
5011 bfin_handle_l1_text_attribute (tree *node, tree name, tree ARG_UNUSED (args),
5012 int ARG_UNUSED (flags), bool *no_add_attrs)
5016 if (TREE_CODE (decl) != FUNCTION_DECL)
5018 error ("`%s' attribute only applies to functions",
5019 IDENTIFIER_POINTER (name));
5020 *no_add_attrs = true;
5023 /* The decl may have already been given a section attribute
5024 from a previous declaration. Ensure they match. */
5025 else if (DECL_SECTION_NAME (decl) != NULL_TREE
5026 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
5029 error ("section of %q+D conflicts with previous declaration",
5031 *no_add_attrs = true;
5034 DECL_SECTION_NAME (decl) = build_string (9, ".l1.text");
5039 /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute;
5040 arguments as in struct attribute_spec.handler. */
5043 bfin_handle_l1_data_attribute (tree *node, tree name, tree ARG_UNUSED (args),
5044 int ARG_UNUSED (flags), bool *no_add_attrs)
5048 if (TREE_CODE (decl) != VAR_DECL)
5050 error ("`%s' attribute only applies to variables",
5051 IDENTIFIER_POINTER (name));
5052 *no_add_attrs = true;
5054 else if (current_function_decl != NULL_TREE
5055 && !TREE_STATIC (decl))
5057 error ("`%s' attribute cannot be specified for local variables",
5058 IDENTIFIER_POINTER (name));
5059 *no_add_attrs = true;
5063 const char *section_name;
5065 if (strcmp (IDENTIFIER_POINTER (name), "l1_data") == 0)
5066 section_name = ".l1.data";
5067 else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_A") == 0)
5068 section_name = ".l1.data.A";
5069 else if (strcmp (IDENTIFIER_POINTER (name), "l1_data_B") == 0)
5070 section_name = ".l1.data.B";
5074 /* The decl may have already been given a section attribute
5075 from a previous declaration. Ensure they match. */
5076 if (DECL_SECTION_NAME (decl) != NULL_TREE
5077 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
5080 error ("section of %q+D conflicts with previous declaration",
5082 *no_add_attrs = true;
5085 DECL_SECTION_NAME (decl)
5086 = build_string (strlen (section_name) + 1, section_name);
5092 /* Table of valid machine attributes. */
5093 const struct attribute_spec bfin_attribute_table[] =
5095 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5096 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute },
5097 { "exception_handler", 0, 0, false, true, true, handle_int_attribute },
5098 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute },
5099 { "nesting", 0, 0, false, true, true, NULL },
5100 { "kspisusp", 0, 0, false, true, true, NULL },
5101 { "saveall", 0, 0, false, true, true, NULL },
5102 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute },
5103 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute },
5104 { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute },
5105 { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute },
5106 { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute },
5107 { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute },
5108 { NULL, 0, 0, false, false, false, NULL }
5111 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
5112 tell the assembler to generate pointers to function descriptors in
5116 bfin_assemble_integer (rtx value, unsigned int size, int aligned_p)
5118 if (TARGET_FDPIC && size == UNITS_PER_WORD)
5120 if (GET_CODE (value) == SYMBOL_REF
5121 && SYMBOL_REF_FUNCTION_P (value))
5123 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
5124 output_addr_const (asm_out_file, value);
5125 fputs (")\n", asm_out_file);
5130 /* We've set the unaligned SI op to NULL, so we always have to
5131 handle the unaligned case here. */
5132 assemble_integer_with_op ("\t.4byte\t", value);
5136 return default_assemble_integer (value, size, aligned_p);
5139 /* Output the assembler code for a thunk function. THUNK_DECL is the
5140 declaration for the thunk function itself, FUNCTION is the decl for
5141 the target function. DELTA is an immediate constant offset to be
5142 added to THIS. If VCALL_OFFSET is nonzero, the word at
5143 *(*this + vcall_offset) should be added to THIS. */
5146 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
5147 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
5148 HOST_WIDE_INT vcall_offset, tree function)
5151 /* The this parameter is passed as the first argument. */
5152 rtx this_rtx = gen_rtx_REG (Pmode, REG_R0);
5154 /* Adjust the this parameter by a fixed constant. */
5158 if (delta >= -64 && delta <= 63)
5160 xops[0] = GEN_INT (delta);
5161 output_asm_insn ("%1 += %0;", xops);
5163 else if (delta >= -128 && delta < -64)
5165 xops[0] = GEN_INT (delta + 64);
5166 output_asm_insn ("%1 += -64; %1 += %0;", xops);
5168 else if (delta > 63 && delta <= 126)
5170 xops[0] = GEN_INT (delta - 63);
5171 output_asm_insn ("%1 += 63; %1 += %0;", xops);
5175 xops[0] = GEN_INT (delta);
5176 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops);
5180 /* Adjust the this parameter by a value stored in the vtable. */
5183 rtx p2tmp = gen_rtx_REG (Pmode, REG_P2);
5184 rtx tmp = gen_rtx_REG (Pmode, REG_R3);
5188 output_asm_insn ("%2 = r0; %2 = [%2];", xops);
5190 /* Adjust the this parameter. */
5191 xops[0] = gen_rtx_MEM (Pmode, plus_constant (p2tmp, vcall_offset));
5192 if (!memory_operand (xops[0], Pmode))
5194 rtx tmp2 = gen_rtx_REG (Pmode, REG_P1);
5195 xops[0] = GEN_INT (vcall_offset);
5197 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops);
5198 xops[0] = gen_rtx_MEM (Pmode, p2tmp);
5201 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops);
5204 xops[0] = XEXP (DECL_RTL (function), 0);
5205 if (1 || !flag_pic || (*targetm.binds_local_p) (function))
5206 output_asm_insn ("jump.l\t%P0", xops);
5209 /* Codes for all the Blackfin builtins. */
5215 BFIN_BUILTIN_COMPOSE_2X16,
5216 BFIN_BUILTIN_EXTRACTLO,
5217 BFIN_BUILTIN_EXTRACTHI,
5219 BFIN_BUILTIN_SSADD_2X16,
5220 BFIN_BUILTIN_SSSUB_2X16,
5221 BFIN_BUILTIN_SSADDSUB_2X16,
5222 BFIN_BUILTIN_SSSUBADD_2X16,
5223 BFIN_BUILTIN_MULT_2X16,
5224 BFIN_BUILTIN_MULTR_2X16,
5225 BFIN_BUILTIN_NEG_2X16,
5226 BFIN_BUILTIN_ABS_2X16,
5227 BFIN_BUILTIN_MIN_2X16,
5228 BFIN_BUILTIN_MAX_2X16,
5230 BFIN_BUILTIN_SSADD_1X16,
5231 BFIN_BUILTIN_SSSUB_1X16,
5232 BFIN_BUILTIN_MULT_1X16,
5233 BFIN_BUILTIN_MULTR_1X16,
5234 BFIN_BUILTIN_NORM_1X16,
5235 BFIN_BUILTIN_NEG_1X16,
5236 BFIN_BUILTIN_ABS_1X16,
5237 BFIN_BUILTIN_MIN_1X16,
5238 BFIN_BUILTIN_MAX_1X16,
5240 BFIN_BUILTIN_SUM_2X16,
5241 BFIN_BUILTIN_DIFFHL_2X16,
5242 BFIN_BUILTIN_DIFFLH_2X16,
5244 BFIN_BUILTIN_SSADD_1X32,
5245 BFIN_BUILTIN_SSSUB_1X32,
5246 BFIN_BUILTIN_NORM_1X32,
5247 BFIN_BUILTIN_ROUND_1X32,
5248 BFIN_BUILTIN_NEG_1X32,
5249 BFIN_BUILTIN_ABS_1X32,
5250 BFIN_BUILTIN_MIN_1X32,
5251 BFIN_BUILTIN_MAX_1X32,
5252 BFIN_BUILTIN_MULT_1X32,
5253 BFIN_BUILTIN_MULT_1X32X32,
5254 BFIN_BUILTIN_MULT_1X32X32NS,
5256 BFIN_BUILTIN_MULHISILL,
5257 BFIN_BUILTIN_MULHISILH,
5258 BFIN_BUILTIN_MULHISIHL,
5259 BFIN_BUILTIN_MULHISIHH,
5261 BFIN_BUILTIN_LSHIFT_1X16,
5262 BFIN_BUILTIN_LSHIFT_2X16,
5263 BFIN_BUILTIN_SSASHIFT_1X16,
5264 BFIN_BUILTIN_SSASHIFT_2X16,
5265 BFIN_BUILTIN_SSASHIFT_1X32,
5267 BFIN_BUILTIN_CPLX_MUL_16,
5268 BFIN_BUILTIN_CPLX_MAC_16,
5269 BFIN_BUILTIN_CPLX_MSU_16,
5271 BFIN_BUILTIN_CPLX_MUL_16_S40,
5272 BFIN_BUILTIN_CPLX_MAC_16_S40,
5273 BFIN_BUILTIN_CPLX_MSU_16_S40,
5275 BFIN_BUILTIN_CPLX_SQU,
5277 BFIN_BUILTIN_LOADBYTES,
5282 #define def_builtin(NAME, TYPE, CODE) \
5284 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5288 /* Set up all builtin functions for this target. */
5290 bfin_init_builtins (void)
5292 tree V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
5293 tree void_ftype_void
5294 = build_function_type (void_type_node, void_list_node);
5295 tree short_ftype_short
5296 = build_function_type_list (short_integer_type_node, short_integer_type_node,
5298 tree short_ftype_int_int
5299 = build_function_type_list (short_integer_type_node, integer_type_node,
5300 integer_type_node, NULL_TREE);
5301 tree int_ftype_int_int
5302 = build_function_type_list (integer_type_node, integer_type_node,
5303 integer_type_node, NULL_TREE);
5305 = build_function_type_list (integer_type_node, integer_type_node,
5307 tree short_ftype_int
5308 = build_function_type_list (short_integer_type_node, integer_type_node,
5310 tree int_ftype_v2hi_v2hi
5311 = build_function_type_list (integer_type_node, V2HI_type_node,
5312 V2HI_type_node, NULL_TREE);
5313 tree v2hi_ftype_v2hi_v2hi
5314 = build_function_type_list (V2HI_type_node, V2HI_type_node,
5315 V2HI_type_node, NULL_TREE);
5316 tree v2hi_ftype_v2hi_v2hi_v2hi
5317 = build_function_type_list (V2HI_type_node, V2HI_type_node,
5318 V2HI_type_node, V2HI_type_node, NULL_TREE);
5319 tree v2hi_ftype_int_int
5320 = build_function_type_list (V2HI_type_node, integer_type_node,
5321 integer_type_node, NULL_TREE);
5322 tree v2hi_ftype_v2hi_int
5323 = build_function_type_list (V2HI_type_node, V2HI_type_node,
5324 integer_type_node, NULL_TREE);
5325 tree int_ftype_short_short
5326 = build_function_type_list (integer_type_node, short_integer_type_node,
5327 short_integer_type_node, NULL_TREE);
5328 tree v2hi_ftype_v2hi
5329 = build_function_type_list (V2HI_type_node, V2HI_type_node, NULL_TREE);
5330 tree short_ftype_v2hi
5331 = build_function_type_list (short_integer_type_node, V2HI_type_node,
5334 = build_function_type_list (integer_type_node,
5335 build_pointer_type (integer_type_node),
5338 /* Add the remaining MMX insns with somewhat more complicated types. */
5339 def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC);
5340 def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC);
5342 def_builtin ("__builtin_bfin_ones", short_ftype_int, BFIN_BUILTIN_ONES);
5344 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int,
5345 BFIN_BUILTIN_COMPOSE_2X16);
5346 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi,
5347 BFIN_BUILTIN_EXTRACTHI);
5348 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi,
5349 BFIN_BUILTIN_EXTRACTLO);
5351 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi,
5352 BFIN_BUILTIN_MIN_2X16);
5353 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi,
5354 BFIN_BUILTIN_MAX_2X16);
5356 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi,
5357 BFIN_BUILTIN_SSADD_2X16);
5358 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi,
5359 BFIN_BUILTIN_SSSUB_2X16);
5360 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi,
5361 BFIN_BUILTIN_SSADDSUB_2X16);
5362 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi,
5363 BFIN_BUILTIN_SSSUBADD_2X16);
5364 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi,
5365 BFIN_BUILTIN_MULT_2X16);
5366 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi,
5367 BFIN_BUILTIN_MULTR_2X16);
5368 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi,
5369 BFIN_BUILTIN_NEG_2X16);
5370 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi,
5371 BFIN_BUILTIN_ABS_2X16);
5373 def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int,
5374 BFIN_BUILTIN_MIN_1X16);
5375 def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int,
5376 BFIN_BUILTIN_MAX_1X16);
5378 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int,
5379 BFIN_BUILTIN_SSADD_1X16);
5380 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int,
5381 BFIN_BUILTIN_SSSUB_1X16);
5382 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int,
5383 BFIN_BUILTIN_MULT_1X16);
5384 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int,
5385 BFIN_BUILTIN_MULTR_1X16);
5386 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short,
5387 BFIN_BUILTIN_NEG_1X16);
5388 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short,
5389 BFIN_BUILTIN_ABS_1X16);
5390 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int,
5391 BFIN_BUILTIN_NORM_1X16);
5393 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi,
5394 BFIN_BUILTIN_SUM_2X16);
5395 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi,
5396 BFIN_BUILTIN_DIFFHL_2X16);
5397 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi,
5398 BFIN_BUILTIN_DIFFLH_2X16);
5400 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi,
5401 BFIN_BUILTIN_MULHISILL);
5402 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi,
5403 BFIN_BUILTIN_MULHISIHL);
5404 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi,
5405 BFIN_BUILTIN_MULHISILH);
5406 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi,
5407 BFIN_BUILTIN_MULHISIHH);
5409 def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int,
5410 BFIN_BUILTIN_MIN_1X32);
5411 def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int,
5412 BFIN_BUILTIN_MAX_1X32);
5414 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int,
5415 BFIN_BUILTIN_SSADD_1X32);
5416 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int,
5417 BFIN_BUILTIN_SSSUB_1X32);
5418 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int,
5419 BFIN_BUILTIN_NEG_1X32);
5420 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int,
5421 BFIN_BUILTIN_ABS_1X32);
5422 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int,
5423 BFIN_BUILTIN_NORM_1X32);
5424 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int,
5425 BFIN_BUILTIN_ROUND_1X32);
5426 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short,
5427 BFIN_BUILTIN_MULT_1X32);
5428 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int,
5429 BFIN_BUILTIN_MULT_1X32X32);
5430 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int,
5431 BFIN_BUILTIN_MULT_1X32X32NS);
5434 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int,
5435 BFIN_BUILTIN_SSASHIFT_1X16);
5436 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int,
5437 BFIN_BUILTIN_SSASHIFT_2X16);
5438 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int,
5439 BFIN_BUILTIN_LSHIFT_1X16);
5440 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int,
5441 BFIN_BUILTIN_LSHIFT_2X16);
5442 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int,
5443 BFIN_BUILTIN_SSASHIFT_1X32);
5445 /* Complex numbers. */
5446 def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi,
5447 BFIN_BUILTIN_SSADD_2X16);
5448 def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi,
5449 BFIN_BUILTIN_SSSUB_2X16);
5450 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi,
5451 BFIN_BUILTIN_CPLX_MUL_16);
5452 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi,
5453 BFIN_BUILTIN_CPLX_MAC_16);
5454 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi,
5455 BFIN_BUILTIN_CPLX_MSU_16);
5456 def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi,
5457 BFIN_BUILTIN_CPLX_MUL_16_S40);
5458 def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi,
5459 BFIN_BUILTIN_CPLX_MAC_16_S40);
5460 def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi,
5461 BFIN_BUILTIN_CPLX_MSU_16_S40);
5462 def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi,
5463 BFIN_BUILTIN_CPLX_SQU);
5465 /* "Unaligned" load. */
5466 def_builtin ("__builtin_bfin_loadbytes", int_ftype_pint,
5467 BFIN_BUILTIN_LOADBYTES);
5472 struct builtin_description
5474 const enum insn_code icode;
5475 const char *const name;
5476 const enum bfin_builtins code;
5480 static const struct builtin_description bdesc_2arg[] =
5482 { CODE_FOR_composev2hi, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16, -1 },
5484 { CODE_FOR_ssashiftv2hi3, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16, -1 },
5485 { CODE_FOR_ssashifthi3, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16, -1 },
5486 { CODE_FOR_lshiftv2hi3, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16, -1 },
5487 { CODE_FOR_lshifthi3, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16, -1 },
5488 { CODE_FOR_ssashiftsi3, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32, -1 },
5490 { CODE_FOR_sminhi3, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16, -1 },
5491 { CODE_FOR_smaxhi3, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16, -1 },
5492 { CODE_FOR_ssaddhi3, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16, -1 },
5493 { CODE_FOR_sssubhi3, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16, -1 },
5495 { CODE_FOR_sminsi3, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32, -1 },
5496 { CODE_FOR_smaxsi3, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32, -1 },
5497 { CODE_FOR_ssaddsi3, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32, -1 },
5498 { CODE_FOR_sssubsi3, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32, -1 },
5500 { CODE_FOR_sminv2hi3, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16, -1 },
5501 { CODE_FOR_smaxv2hi3, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16, -1 },
5502 { CODE_FOR_ssaddv2hi3, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16, -1 },
5503 { CODE_FOR_sssubv2hi3, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16, -1 },
5504 { CODE_FOR_ssaddsubv2hi3, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16, -1 },
5505 { CODE_FOR_sssubaddv2hi3, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16, -1 },
5507 { CODE_FOR_flag_mulhisi, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32, MACFLAG_NONE },
5508 { CODE_FOR_flag_mulhi, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16, MACFLAG_T },
5509 { CODE_FOR_flag_mulhi, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16, MACFLAG_NONE },
5510 { CODE_FOR_flag_mulv2hi, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16, MACFLAG_T },
5511 { CODE_FOR_flag_mulv2hi, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16, MACFLAG_NONE }
5514 static const struct builtin_description bdesc_1arg[] =
5516 { CODE_FOR_loadbytes, "__builtin_bfin_loadbytes", BFIN_BUILTIN_LOADBYTES, 0 },
5518 { CODE_FOR_ones, "__builtin_bfin_ones", BFIN_BUILTIN_ONES, 0 },
5520 { CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 },
5521 { CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 },
5522 { CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 },
5524 { CODE_FOR_signbitssi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 },
5525 { CODE_FOR_ssroundsi2, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32, 0 },
5526 { CODE_FOR_ssnegsi2, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32, 0 },
5527 { CODE_FOR_ssabssi2, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32, 0 },
5529 { CODE_FOR_movv2hi_hi_low, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO, 0 },
5530 { CODE_FOR_movv2hi_hi_high, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI, 0 },
5531 { CODE_FOR_ssnegv2hi2, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16, 0 },
5532 { CODE_FOR_ssabsv2hi2, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16, 0 }
5535 /* Errors in the source file can cause expand_expr to return const0_rtx
5536 where we expect a vector. To avoid crashing, use one of the vector
5537 clear instructions. */
5539 safe_vector_operand (rtx x, enum machine_mode mode)
5541 if (x != const0_rtx)
5543 x = gen_reg_rtx (SImode);
5545 emit_insn (gen_movsi (x, CONST0_RTX (SImode)));
5546 return gen_lowpart (mode, x);
5549 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
5550 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
5553 bfin_expand_binop_builtin (enum insn_code icode, tree exp, rtx target,
5557 tree arg0 = CALL_EXPR_ARG (exp, 0);
5558 tree arg1 = CALL_EXPR_ARG (exp, 1);
5559 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5560 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5561 enum machine_mode op0mode = GET_MODE (op0);
5562 enum machine_mode op1mode = GET_MODE (op1);
5563 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5564 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5565 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5567 if (VECTOR_MODE_P (mode0))
5568 op0 = safe_vector_operand (op0, mode0);
5569 if (VECTOR_MODE_P (mode1))
5570 op1 = safe_vector_operand (op1, mode1);
5573 || GET_MODE (target) != tmode
5574 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5575 target = gen_reg_rtx (tmode);
5577 if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode)
5580 op0 = gen_lowpart (HImode, op0);
5582 if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode)
5585 op1 = gen_lowpart (HImode, op1);
5587 /* In case the insn wants input operands in modes different from
5588 the result, abort. */
5589 gcc_assert ((op0mode == mode0 || op0mode == VOIDmode)
5590 && (op1mode == mode1 || op1mode == VOIDmode));
5592 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5593 op0 = copy_to_mode_reg (mode0, op0);
5594 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5595 op1 = copy_to_mode_reg (mode1, op1);
5598 pat = GEN_FCN (icode) (target, op0, op1);
5600 pat = GEN_FCN (icode) (target, op0, op1, GEN_INT (macflag));
5608 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5611 bfin_expand_unop_builtin (enum insn_code icode, tree exp,
5615 tree arg0 = CALL_EXPR_ARG (exp, 0);
5616 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5617 enum machine_mode op0mode = GET_MODE (op0);
5618 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5619 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5622 || GET_MODE (target) != tmode
5623 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5624 target = gen_reg_rtx (tmode);
5626 if (VECTOR_MODE_P (mode0))
5627 op0 = safe_vector_operand (op0, mode0);
5629 if (op0mode == SImode && mode0 == HImode)
5632 op0 = gen_lowpart (HImode, op0);
5634 gcc_assert (op0mode == mode0 || op0mode == VOIDmode);
5636 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5637 op0 = copy_to_mode_reg (mode0, op0);
5639 pat = GEN_FCN (icode) (target, op0);
5646 /* Expand an expression EXP that calls a built-in function,
5647 with result going to TARGET if that's convenient
5648 (and in mode MODE if that's convenient).
5649 SUBTARGET may be used as the target for computing one of EXP's operands.
5650 IGNORE is nonzero if the value is to be ignored. */
5653 bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5654 rtx subtarget ATTRIBUTE_UNUSED,
5655 enum machine_mode mode ATTRIBUTE_UNUSED,
5656 int ignore ATTRIBUTE_UNUSED)
5659 enum insn_code icode;
5660 const struct builtin_description *d;
5661 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
5662 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5663 tree arg0, arg1, arg2;
5664 rtx op0, op1, op2, accvec, pat, tmp1, tmp2, a0reg, a1reg;
5665 enum machine_mode tmode, mode0;
5669 case BFIN_BUILTIN_CSYNC:
5670 emit_insn (gen_csync ());
5672 case BFIN_BUILTIN_SSYNC:
5673 emit_insn (gen_ssync ());
5676 case BFIN_BUILTIN_DIFFHL_2X16:
5677 case BFIN_BUILTIN_DIFFLH_2X16:
5678 case BFIN_BUILTIN_SUM_2X16:
5679 arg0 = CALL_EXPR_ARG (exp, 0);
5680 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5681 icode = (fcode == BFIN_BUILTIN_DIFFHL_2X16 ? CODE_FOR_subhilov2hi3
5682 : fcode == BFIN_BUILTIN_DIFFLH_2X16 ? CODE_FOR_sublohiv2hi3
5683 : CODE_FOR_ssaddhilov2hi3);
5684 tmode = insn_data[icode].operand[0].mode;
5685 mode0 = insn_data[icode].operand[1].mode;
5688 || GET_MODE (target) != tmode
5689 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5690 target = gen_reg_rtx (tmode);
5692 if (VECTOR_MODE_P (mode0))
5693 op0 = safe_vector_operand (op0, mode0);
5695 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5696 op0 = copy_to_mode_reg (mode0, op0);
5698 pat = GEN_FCN (icode) (target, op0, op0);
5704 case BFIN_BUILTIN_MULT_1X32X32:
5705 case BFIN_BUILTIN_MULT_1X32X32NS:
5706 arg0 = CALL_EXPR_ARG (exp, 0);
5707 arg1 = CALL_EXPR_ARG (exp, 1);
5708 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5709 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5711 || !register_operand (target, SImode))
5712 target = gen_reg_rtx (SImode);
5714 a1reg = gen_rtx_REG (PDImode, REG_A1);
5715 a0reg = gen_rtx_REG (PDImode, REG_A0);
5716 tmp1 = gen_lowpart (V2HImode, op0);
5717 tmp2 = gen_lowpart (V2HImode, op1);
5718 emit_insn (gen_flag_macinit1hi (a1reg,
5719 gen_lowpart (HImode, op0),
5720 gen_lowpart (HImode, op1),
5721 GEN_INT (MACFLAG_FU)));
5722 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
5724 if (fcode == BFIN_BUILTIN_MULT_1X32X32)
5725 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, tmp1, tmp2,
5726 const1_rtx, const1_rtx,
5727 const1_rtx, const0_rtx, a1reg,
5728 const0_rtx, GEN_INT (MACFLAG_NONE),
5729 GEN_INT (MACFLAG_M)));
5732 /* For saturating multiplication, there's exactly one special case
5733 to be handled: multiplying the smallest negative value with
5734 itself. Due to shift correction in fractional multiplies, this
5735 can overflow. Iff this happens, OP2 will contain 1, which, when
5736 added in 32 bits to the smallest negative, wraps to the largest
5737 positive, which is the result we want. */
5738 op2 = gen_reg_rtx (V2HImode);
5739 emit_insn (gen_packv2hi (op2, tmp1, tmp2, const0_rtx, const0_rtx));
5740 emit_insn (gen_movsibi (gen_rtx_REG (BImode, REG_CC),
5741 gen_lowpart (SImode, op2)));
5742 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg, a1reg, tmp1, tmp2,
5743 const1_rtx, const1_rtx,
5744 const1_rtx, const0_rtx, a1reg,
5745 const0_rtx, GEN_INT (MACFLAG_NONE),
5746 GEN_INT (MACFLAG_M)));
5747 op2 = gen_reg_rtx (SImode);
5748 emit_insn (gen_movbisi (op2, gen_rtx_REG (BImode, REG_CC)));
5750 emit_insn (gen_flag_machi_parts_acconly (a1reg, tmp2, tmp1,
5751 const1_rtx, const0_rtx,
5752 a1reg, const0_rtx, GEN_INT (MACFLAG_M)));
5753 emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (15)));
5754 emit_insn (gen_sum_of_accumulators (target, a0reg, a0reg, a1reg));
5755 if (fcode == BFIN_BUILTIN_MULT_1X32X32NS)
5756 emit_insn (gen_addsi3 (target, target, op2));
5759 case BFIN_BUILTIN_CPLX_MUL_16:
5760 case BFIN_BUILTIN_CPLX_MUL_16_S40:
5761 arg0 = CALL_EXPR_ARG (exp, 0);
5762 arg1 = CALL_EXPR_ARG (exp, 1);
5763 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5764 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5765 accvec = gen_reg_rtx (V2PDImode);
5768 || GET_MODE (target) != V2HImode
5769 || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
5770 target = gen_reg_rtx (tmode);
5771 if (! register_operand (op0, GET_MODE (op0)))
5772 op0 = copy_to_mode_reg (GET_MODE (op0), op0);
5773 if (! register_operand (op1, GET_MODE (op1)))
5774 op1 = copy_to_mode_reg (GET_MODE (op1), op1);
5776 if (fcode == BFIN_BUILTIN_CPLX_MUL_16)
5777 emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
5778 const0_rtx, const0_rtx,
5779 const1_rtx, GEN_INT (MACFLAG_W32)));
5781 emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
5782 const0_rtx, const0_rtx,
5783 const1_rtx, GEN_INT (MACFLAG_NONE)));
5784 emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx,
5785 const1_rtx, const1_rtx,
5786 const0_rtx, accvec, const1_rtx, const0_rtx,
5787 GEN_INT (MACFLAG_NONE), accvec));
5791 case BFIN_BUILTIN_CPLX_MAC_16:
5792 case BFIN_BUILTIN_CPLX_MSU_16:
5793 case BFIN_BUILTIN_CPLX_MAC_16_S40:
5794 case BFIN_BUILTIN_CPLX_MSU_16_S40:
5795 arg0 = CALL_EXPR_ARG (exp, 0);
5796 arg1 = CALL_EXPR_ARG (exp, 1);
5797 arg2 = CALL_EXPR_ARG (exp, 2);
5798 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5799 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5800 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5801 accvec = gen_reg_rtx (V2PDImode);
5804 || GET_MODE (target) != V2HImode
5805 || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
5806 target = gen_reg_rtx (tmode);
5807 if (! register_operand (op1, GET_MODE (op1)))
5808 op1 = copy_to_mode_reg (GET_MODE (op1), op1);
5809 if (! register_operand (op2, GET_MODE (op2)))
5810 op2 = copy_to_mode_reg (GET_MODE (op2), op2);
5812 tmp1 = gen_reg_rtx (SImode);
5813 tmp2 = gen_reg_rtx (SImode);
5814 emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op0), GEN_INT (16)));
5815 emit_move_insn (tmp2, gen_lowpart (SImode, op0));
5816 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx));
5817 emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2));
5818 if (fcode == BFIN_BUILTIN_CPLX_MAC_16
5819 || fcode == BFIN_BUILTIN_CPLX_MSU_16)
5820 emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx,
5821 const0_rtx, const0_rtx,
5822 const1_rtx, accvec, const0_rtx,
5824 GEN_INT (MACFLAG_W32)));
5826 emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op1, op2, const0_rtx,
5827 const0_rtx, const0_rtx,
5828 const1_rtx, accvec, const0_rtx,
5830 GEN_INT (MACFLAG_NONE)));
5831 if (fcode == BFIN_BUILTIN_CPLX_MAC_16
5832 || fcode == BFIN_BUILTIN_CPLX_MAC_16_S40)
5842 emit_insn (gen_flag_macv2hi_parts (target, op1, op2, const1_rtx,
5843 const1_rtx, const1_rtx,
5844 const0_rtx, accvec, tmp1, tmp2,
5845 GEN_INT (MACFLAG_NONE), accvec));
5849 case BFIN_BUILTIN_CPLX_SQU:
5850 arg0 = CALL_EXPR_ARG (exp, 0);
5851 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5852 accvec = gen_reg_rtx (V2PDImode);
5853 icode = CODE_FOR_flag_mulv2hi;
5854 tmp1 = gen_reg_rtx (V2HImode);
5855 tmp2 = gen_reg_rtx (V2HImode);
5858 || GET_MODE (target) != V2HImode
5859 || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
5860 target = gen_reg_rtx (V2HImode);
5861 if (! register_operand (op0, GET_MODE (op0)))
5862 op0 = copy_to_mode_reg (GET_MODE (op0), op0);
5864 emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE)));
5866 emit_insn (gen_flag_mulhi_parts (tmp2, op0, op0, const0_rtx,
5867 const0_rtx, const1_rtx,
5868 GEN_INT (MACFLAG_NONE)));
5870 emit_insn (gen_ssaddhi3_parts (target, tmp2, tmp2, const1_rtx,
5871 const0_rtx, const0_rtx));
5873 emit_insn (gen_sssubhi3_parts (target, tmp1, tmp1, const0_rtx,
5874 const0_rtx, const1_rtx));
5882 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
5883 if (d->code == fcode)
5884 return bfin_expand_binop_builtin (d->icode, exp, target,
5887 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
5888 if (d->code == fcode)
5889 return bfin_expand_unop_builtin (d->icode, exp, target);
5894 #undef TARGET_INIT_BUILTINS
5895 #define TARGET_INIT_BUILTINS bfin_init_builtins
5897 #undef TARGET_EXPAND_BUILTIN
5898 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
5900 #undef TARGET_ASM_GLOBALIZE_LABEL
5901 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
5903 #undef TARGET_ASM_FILE_START
5904 #define TARGET_ASM_FILE_START output_file_start
5906 #undef TARGET_ATTRIBUTE_TABLE
5907 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
5909 #undef TARGET_COMP_TYPE_ATTRIBUTES
5910 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
5912 #undef TARGET_RTX_COSTS
5913 #define TARGET_RTX_COSTS bfin_rtx_costs
5915 #undef TARGET_ADDRESS_COST
5916 #define TARGET_ADDRESS_COST bfin_address_cost
5918 #undef TARGET_ASM_INTEGER
5919 #define TARGET_ASM_INTEGER bfin_assemble_integer
5921 #undef TARGET_MACHINE_DEPENDENT_REORG
5922 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
5924 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5925 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
5927 #undef TARGET_ASM_OUTPUT_MI_THUNK
5928 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
5929 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5930 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5932 #undef TARGET_SCHED_ADJUST_COST
5933 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
5935 #undef TARGET_SCHED_ISSUE_RATE
5936 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
5938 #undef TARGET_PROMOTE_PROTOTYPES
5939 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
5940 #undef TARGET_PROMOTE_FUNCTION_ARGS
5941 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
5942 #undef TARGET_PROMOTE_FUNCTION_RETURN
5943 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
5945 #undef TARGET_ARG_PARTIAL_BYTES
5946 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
5948 #undef TARGET_PASS_BY_REFERENCE
5949 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
5951 #undef TARGET_SETUP_INCOMING_VARARGS
5952 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
5954 #undef TARGET_STRUCT_VALUE_RTX
5955 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
5957 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5958 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
5960 #undef TARGET_HANDLE_OPTION
5961 #define TARGET_HANDLE_OPTION bfin_handle_option
5963 #undef TARGET_DEFAULT_TARGET_FLAGS
5964 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5966 #undef TARGET_SECONDARY_RELOAD
5967 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
5969 #undef TARGET_DELEGITIMIZE_ADDRESS
5970 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
5972 #undef TARGET_CANNOT_FORCE_CONST_MEM
5973 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
5975 #undef TARGET_RETURN_IN_MEMORY
5976 #define TARGET_RETURN_IN_MEMORY bfin_return_in_memory
5978 struct gcc_target targetm = TARGET_INITIALIZER;