1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-codes.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
41 #include "target-def.h"
47 #include "integrate.h"
49 #include "langhooks.h"
50 #include "bfin-protos.h"
53 #include "basic-block.h"
54 #include "cfglayout.h"
58 /* A C structure for machine-specific, per-function data.
59 This is added to the cfun structure. */
60 struct machine_function GTY(())
62 int has_hardware_loops;
65 /* Test and compare insns in bfin.md store the information needed to
66 generate branch and scc insns here. */
67 rtx bfin_compare_op0, bfin_compare_op1;
69 /* RTX for condition code flag register and RETS register */
70 extern GTY(()) rtx bfin_cc_rtx;
71 extern GTY(()) rtx bfin_rets_rtx;
72 rtx bfin_cc_rtx, bfin_rets_rtx;
74 int max_arg_registers = 0;
76 /* Arrays used when emitting register names. */
77 const char *short_reg_names[] = SHORT_REGISTER_NAMES;
78 const char *high_reg_names[] = HIGH_REGISTER_NAMES;
79 const char *dregs_pair_names[] = DREGS_PAIR_NAMES;
80 const char *byte_reg_names[] = BYTE_REGISTER_NAMES;
82 static int arg_regs[] = FUNCTION_ARG_REGISTERS;
84 /* Nonzero if -mshared-library-id was given. */
85 static int bfin_lib_id_given;
87 /* Nonzero if -fschedule-insns2 was given. We override it and
88 call the scheduler ourselves during reorg. */
89 static int bfin_flag_schedule_insns2;
91 /* Determines whether we run variable tracking in machine dependent
93 static int bfin_flag_var_tracking;
96 bfin_cpu_t bfin_cpu_type = DEFAULT_CPU_TYPE;
98 int splitting_for_sched;
101 bfin_globalize_label (FILE *stream, const char *name)
103 fputs (".global ", stream);
104 assemble_name (stream, name);
110 output_file_start (void)
112 FILE *file = asm_out_file;
115 /* Variable tracking should be run after all optimizations which change order
116 of insns. It also needs a valid CFG. This can't be done in
117 override_options, because flag_var_tracking is finalized after
119 bfin_flag_var_tracking = flag_var_tracking;
120 flag_var_tracking = 0;
122 fprintf (file, ".file \"%s\";\n", input_filename);
124 for (i = 0; arg_regs[i] >= 0; i++)
126 max_arg_registers = i; /* how many arg reg used */
129 /* Called early in the compilation to conditionally modify
130 fixed_regs/call_used_regs. */
133 conditional_register_usage (void)
135 /* initialize condition code flag register rtx */
136 bfin_cc_rtx = gen_rtx_REG (BImode, REG_CC);
137 bfin_rets_rtx = gen_rtx_REG (Pmode, REG_RETS);
140 /* Examine machine-dependent attributes of function type FUNTYPE and return its
141 type. See the definition of E_FUNKIND. */
143 static e_funkind funkind (tree funtype)
145 tree attrs = TYPE_ATTRIBUTES (funtype);
146 if (lookup_attribute ("interrupt_handler", attrs))
147 return INTERRUPT_HANDLER;
148 else if (lookup_attribute ("exception_handler", attrs))
149 return EXCPT_HANDLER;
150 else if (lookup_attribute ("nmi_handler", attrs))
156 /* Legitimize PIC addresses. If the address is already position-independent,
157 we return ORIG. Newly generated position-independent addresses go into a
158 reg. This is REG if nonzero, otherwise we allocate register(s) as
159 necessary. PICREG is the register holding the pointer to the PIC offset
163 legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
168 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
173 if (TARGET_ID_SHARED_LIBRARY)
174 unspec = UNSPEC_MOVE_PIC;
175 else if (GET_CODE (addr) == SYMBOL_REF
176 && SYMBOL_REF_FUNCTION_P (addr))
177 unspec = UNSPEC_FUNCDESC_GOT17M4;
179 unspec = UNSPEC_MOVE_FDPIC;
183 gcc_assert (can_create_pseudo_p ());
184 reg = gen_reg_rtx (Pmode);
187 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), unspec);
188 new = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp));
190 emit_move_insn (reg, new);
191 if (picreg == pic_offset_table_rtx)
192 current_function_uses_pic_offset_table = 1;
196 else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS)
200 if (GET_CODE (addr) == CONST)
202 addr = XEXP (addr, 0);
203 gcc_assert (GET_CODE (addr) == PLUS);
206 if (XEXP (addr, 0) == picreg)
211 gcc_assert (can_create_pseudo_p ());
212 reg = gen_reg_rtx (Pmode);
215 base = legitimize_pic_address (XEXP (addr, 0), reg, picreg);
216 addr = legitimize_pic_address (XEXP (addr, 1),
217 base == reg ? NULL_RTX : reg,
220 if (GET_CODE (addr) == CONST_INT)
222 gcc_assert (! reload_in_progress && ! reload_completed);
223 addr = force_reg (Pmode, addr);
226 if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1)))
228 base = gen_rtx_PLUS (Pmode, base, XEXP (addr, 0));
229 addr = XEXP (addr, 1);
232 return gen_rtx_PLUS (Pmode, base, addr);
238 /* Stack frame layout. */
240 /* Compute the number of DREGS to save with a push_multiple operation.
241 This could include registers that aren't modified in the function,
242 since push_multiple only takes a range of registers.
243 If IS_INTHANDLER, then everything that is live must be saved, even
244 if normally call-clobbered. */
247 n_dregs_to_save (bool is_inthandler)
251 for (i = REG_R0; i <= REG_R7; i++)
253 if (df_regs_ever_live_p (i) && (is_inthandler || ! call_used_regs[i]))
254 return REG_R7 - i + 1;
256 if (current_function_calls_eh_return)
261 unsigned test = EH_RETURN_DATA_REGNO (j);
262 if (test == INVALID_REGNUM)
265 return REG_R7 - i + 1;
273 /* Like n_dregs_to_save, but compute number of PREGS to save. */
276 n_pregs_to_save (bool is_inthandler)
280 for (i = REG_P0; i <= REG_P5; i++)
281 if ((df_regs_ever_live_p (i) && (is_inthandler || ! call_used_regs[i]))
283 && i == PIC_OFFSET_TABLE_REGNUM
284 && (current_function_uses_pic_offset_table
285 || (TARGET_ID_SHARED_LIBRARY && ! current_function_is_leaf))))
286 return REG_P5 - i + 1;
290 /* Determine if we are going to save the frame pointer in the prologue. */
293 must_save_fp_p (void)
295 return frame_pointer_needed || df_regs_ever_live_p (REG_FP);
299 stack_frame_needed_p (void)
301 /* EH return puts a new return address into the frame using an
302 address relative to the frame pointer. */
303 if (current_function_calls_eh_return)
305 return frame_pointer_needed;
308 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
309 must save all registers; this is used for interrupt handlers.
310 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
311 this for an interrupt (or exception) handler. */
314 expand_prologue_reg_save (rtx spreg, int saveall, bool is_inthandler)
316 int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler);
317 int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler);
318 int dregno = REG_R7 + 1 - ndregs;
319 int pregno = REG_P5 + 1 - npregs;
320 int total = ndregs + npregs;
327 val = GEN_INT (-total * 4);
328 pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total + 2));
329 XVECEXP (pat, 0, 0) = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, val),
330 UNSPEC_PUSH_MULTIPLE);
331 XVECEXP (pat, 0, total + 1) = gen_rtx_SET (VOIDmode, spreg,
332 gen_rtx_PLUS (Pmode, spreg,
334 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, total + 1)) = 1;
335 for (i = 0; i < total; i++)
337 rtx memref = gen_rtx_MEM (word_mode,
338 gen_rtx_PLUS (Pmode, spreg,
339 GEN_INT (- i * 4 - 4)));
343 subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode,
349 subpat = gen_rtx_SET (VOIDmode, memref, gen_rtx_REG (word_mode,
353 XVECEXP (pat, 0, i + 1) = subpat;
354 RTX_FRAME_RELATED_P (subpat) = 1;
356 insn = emit_insn (pat);
357 RTX_FRAME_RELATED_P (insn) = 1;
360 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
361 must save all registers; this is used for interrupt handlers.
362 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
363 this for an interrupt (or exception) handler. */
366 expand_epilogue_reg_restore (rtx spreg, bool saveall, bool is_inthandler)
368 int ndregs = saveall ? 8 : n_dregs_to_save (is_inthandler);
369 int npregs = saveall ? 6 : n_pregs_to_save (is_inthandler);
370 int total = ndregs + npregs;
377 pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total + 1));
378 XVECEXP (pat, 0, 0) = gen_rtx_SET (VOIDmode, spreg,
379 gen_rtx_PLUS (Pmode, spreg,
380 GEN_INT (total * 4)));
387 for (i = 0; i < total; i++)
390 ? gen_rtx_PLUS (Pmode, spreg, GEN_INT (i * 4))
392 rtx memref = gen_rtx_MEM (word_mode, addr);
395 XVECEXP (pat, 0, i + 1)
396 = gen_rtx_SET (VOIDmode, gen_rtx_REG (word_mode, regno), memref);
405 insn = emit_insn (pat);
406 RTX_FRAME_RELATED_P (insn) = 1;
409 /* Perform any needed actions needed for a function that is receiving a
410 variable number of arguments.
414 MODE and TYPE are the mode and type of the current parameter.
416 PRETEND_SIZE is a variable that should be set to the amount of stack
417 that must be pushed by the prolog to pretend that our caller pushed
420 Normally, this macro will push all remaining incoming registers on the
421 stack and set PRETEND_SIZE to the length of the registers pushed.
424 - VDSP C compiler manual (our ABI) says that a variable args function
425 should save the R0, R1 and R2 registers in the stack.
426 - The caller will always leave space on the stack for the
427 arguments that are passed in registers, so we dont have
428 to leave any extra space.
429 - now, the vastart pointer can access all arguments from the stack. */
432 setup_incoming_varargs (CUMULATIVE_ARGS *cum,
433 enum machine_mode mode ATTRIBUTE_UNUSED,
434 tree type ATTRIBUTE_UNUSED, int *pretend_size,
443 /* The move for named arguments will be generated automatically by the
444 compiler. We need to generate the move rtx for the unnamed arguments
445 if they are in the first 3 words. We assume at least 1 named argument
446 exists, so we never generate [ARGP] = R0 here. */
448 for (i = cum->words + 1; i < max_arg_registers; i++)
450 mem = gen_rtx_MEM (Pmode,
451 plus_constant (arg_pointer_rtx, (i * UNITS_PER_WORD)));
452 emit_move_insn (mem, gen_rtx_REG (Pmode, i));
458 /* Value should be nonzero if functions must have frame pointers.
459 Zero means the frame pointer need not be set up (and parms may
460 be accessed via the stack pointer) in functions that seem suitable. */
463 bfin_frame_pointer_required (void)
465 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
467 if (fkind != SUBROUTINE)
470 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
471 so we have to override it for non-leaf functions. */
472 if (TARGET_OMIT_LEAF_FRAME_POINTER && ! current_function_is_leaf)
478 /* Return the number of registers pushed during the prologue. */
481 n_regs_saved_by_prologue (void)
483 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
484 bool is_inthandler = fkind != SUBROUTINE;
485 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
486 bool all = (lookup_attribute ("saveall", attrs) != NULL_TREE
487 || (is_inthandler && !current_function_is_leaf));
488 int ndregs = all ? 8 : n_dregs_to_save (is_inthandler);
489 int npregs = all ? 6 : n_pregs_to_save (is_inthandler);
490 int n = ndregs + npregs;
492 if (all || stack_frame_needed_p ())
493 /* We use a LINK instruction in this case. */
497 if (must_save_fp_p ())
499 if (! current_function_is_leaf)
503 if (fkind != SUBROUTINE)
507 /* Increment once for ASTAT. */
511 if (lookup_attribute ("nesting", attrs))
514 for (i = REG_P7 + 1; i < REG_CC; i++)
516 || df_regs_ever_live_p (i)
517 || (!leaf_function_p () && call_used_regs[i]))
518 n += i == REG_A0 || i == REG_A1 ? 2 : 1;
523 /* Return the offset between two registers, one to be eliminated, and the other
524 its replacement, at the start of a routine. */
527 bfin_initial_elimination_offset (int from, int to)
529 HOST_WIDE_INT offset = 0;
531 if (from == ARG_POINTER_REGNUM)
532 offset = n_regs_saved_by_prologue () * 4;
534 if (to == STACK_POINTER_REGNUM)
536 if (current_function_outgoing_args_size >= FIXED_STACK_AREA)
537 offset += current_function_outgoing_args_size;
538 else if (current_function_outgoing_args_size)
539 offset += FIXED_STACK_AREA;
541 offset += get_frame_size ();
547 /* Emit code to load a constant CONSTANT into register REG; setting
548 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
549 Make sure that the insns we generate need not be split. */
552 frame_related_constant_load (rtx reg, HOST_WIDE_INT constant, bool related)
555 rtx cst = GEN_INT (constant);
557 if (constant >= -32768 && constant < 65536)
558 insn = emit_move_insn (reg, cst);
561 /* We don't call split_load_immediate here, since dwarf2out.c can get
562 confused about some of the more clever sequences it can generate. */
563 insn = emit_insn (gen_movsi_high (reg, cst));
565 RTX_FRAME_RELATED_P (insn) = 1;
566 insn = emit_insn (gen_movsi_low (reg, reg, cst));
569 RTX_FRAME_RELATED_P (insn) = 1;
572 /* Generate efficient code to add a value to a P register.
573 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
574 EPILOGUE_P is zero if this function is called for prologue,
575 otherwise it's nonzero. And it's less than zero if this is for
579 add_to_reg (rtx reg, HOST_WIDE_INT value, int frame, int epilogue_p)
584 /* Choose whether to use a sequence using a temporary register, or
585 a sequence with multiple adds. We can add a signed 7-bit value
586 in one instruction. */
587 if (value > 120 || value < -120)
595 /* For prologue or normal epilogue, P1 can be safely used
596 as the temporary register. For sibcall epilogue, we try to find
597 a call used P register, which will be restored in epilogue.
598 If we cannot find such a P register, we have to use one I register
602 tmpreg = gen_rtx_REG (SImode, REG_P1);
606 for (i = REG_P0; i <= REG_P5; i++)
607 if ((df_regs_ever_live_p (i) && ! call_used_regs[i])
609 && i == PIC_OFFSET_TABLE_REGNUM
610 && (current_function_uses_pic_offset_table
611 || (TARGET_ID_SHARED_LIBRARY
612 && ! current_function_is_leaf))))
615 tmpreg = gen_rtx_REG (SImode, i);
618 tmpreg = gen_rtx_REG (SImode, REG_P1);
619 tmpreg2 = gen_rtx_REG (SImode, REG_I0);
620 emit_move_insn (tmpreg2, tmpreg);
625 frame_related_constant_load (tmpreg, value, TRUE);
627 insn = emit_move_insn (tmpreg, GEN_INT (value));
629 insn = emit_insn (gen_addsi3 (reg, reg, tmpreg));
631 RTX_FRAME_RELATED_P (insn) = 1;
633 if (tmpreg2 != NULL_RTX)
634 emit_move_insn (tmpreg, tmpreg2);
645 /* We could use -62, but that would leave the stack unaligned, so
649 insn = emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
651 RTX_FRAME_RELATED_P (insn) = 1;
657 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
658 is too large, generate a sequence of insns that has the same effect.
659 SPREG contains (reg:SI REG_SP). */
662 emit_link_insn (rtx spreg, HOST_WIDE_INT frame_size)
664 HOST_WIDE_INT link_size = frame_size;
668 if (link_size > 262140)
671 /* Use a LINK insn with as big a constant as possible, then subtract
672 any remaining size from the SP. */
673 insn = emit_insn (gen_link (GEN_INT (-8 - link_size)));
674 RTX_FRAME_RELATED_P (insn) = 1;
676 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
678 rtx set = XVECEXP (PATTERN (insn), 0, i);
679 gcc_assert (GET_CODE (set) == SET);
680 RTX_FRAME_RELATED_P (set) = 1;
683 frame_size -= link_size;
687 /* Must use a call-clobbered PREG that isn't the static chain. */
688 rtx tmpreg = gen_rtx_REG (Pmode, REG_P1);
690 frame_related_constant_load (tmpreg, -frame_size, TRUE);
691 insn = emit_insn (gen_addsi3 (spreg, spreg, tmpreg));
692 RTX_FRAME_RELATED_P (insn) = 1;
696 /* Return the number of bytes we must reserve for outgoing arguments
697 in the current function's stack frame. */
702 if (current_function_outgoing_args_size)
704 if (current_function_outgoing_args_size >= FIXED_STACK_AREA)
705 return current_function_outgoing_args_size;
707 return FIXED_STACK_AREA;
712 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
713 function must save all its registers (true only for certain interrupt
717 do_link (rtx spreg, HOST_WIDE_INT frame_size, bool all)
719 frame_size += arg_area_size ();
721 if (all || stack_frame_needed_p ()
722 || (must_save_fp_p () && ! current_function_is_leaf))
723 emit_link_insn (spreg, frame_size);
726 if (! current_function_is_leaf)
728 rtx pat = gen_movsi (gen_rtx_MEM (Pmode,
729 gen_rtx_PRE_DEC (Pmode, spreg)),
731 rtx insn = emit_insn (pat);
732 RTX_FRAME_RELATED_P (insn) = 1;
734 if (must_save_fp_p ())
736 rtx pat = gen_movsi (gen_rtx_MEM (Pmode,
737 gen_rtx_PRE_DEC (Pmode, spreg)),
738 gen_rtx_REG (Pmode, REG_FP));
739 rtx insn = emit_insn (pat);
740 RTX_FRAME_RELATED_P (insn) = 1;
742 add_to_reg (spreg, -frame_size, 1, 0);
746 /* Like do_link, but used for epilogues to deallocate the stack frame.
747 EPILOGUE_P is zero if this function is called for prologue,
748 otherwise it's nonzero. And it's less than zero if this is for
752 do_unlink (rtx spreg, HOST_WIDE_INT frame_size, bool all, int epilogue_p)
754 frame_size += arg_area_size ();
756 if (all || stack_frame_needed_p ())
757 emit_insn (gen_unlink ());
760 rtx postinc = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, spreg));
762 add_to_reg (spreg, frame_size, 0, epilogue_p);
763 if (must_save_fp_p ())
765 rtx fpreg = gen_rtx_REG (Pmode, REG_FP);
766 emit_move_insn (fpreg, postinc);
767 emit_insn (gen_rtx_USE (VOIDmode, fpreg));
769 if (! current_function_is_leaf)
771 emit_move_insn (bfin_rets_rtx, postinc);
772 emit_insn (gen_rtx_USE (VOIDmode, bfin_rets_rtx));
777 /* Generate a prologue suitable for a function of kind FKIND. This is
778 called for interrupt and exception handler prologues.
779 SPREG contains (reg:SI REG_SP). */
782 expand_interrupt_handler_prologue (rtx spreg, e_funkind fkind)
785 HOST_WIDE_INT frame_size = get_frame_size ();
786 rtx predec1 = gen_rtx_PRE_DEC (SImode, spreg);
787 rtx predec = gen_rtx_MEM (SImode, predec1);
789 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
790 bool all = lookup_attribute ("saveall", attrs) != NULL_TREE;
791 tree kspisusp = lookup_attribute ("kspisusp", attrs);
795 insn = emit_move_insn (spreg, gen_rtx_REG (Pmode, REG_USP));
796 RTX_FRAME_RELATED_P (insn) = 1;
799 /* We need space on the stack in case we need to save the argument
801 if (fkind == EXCPT_HANDLER)
803 insn = emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (-12)));
804 RTX_FRAME_RELATED_P (insn) = 1;
807 insn = emit_move_insn (predec, gen_rtx_REG (SImode, REG_ASTAT));
808 RTX_FRAME_RELATED_P (insn) = 1;
810 /* If we're calling other functions, they won't save their call-clobbered
811 registers, so we must save everything here. */
812 if (!current_function_is_leaf)
814 expand_prologue_reg_save (spreg, all, true);
816 for (i = REG_P7 + 1; i < REG_CC; i++)
818 || df_regs_ever_live_p (i)
819 || (!leaf_function_p () && call_used_regs[i]))
821 if (i == REG_A0 || i == REG_A1)
822 insn = emit_move_insn (gen_rtx_MEM (PDImode, predec1),
823 gen_rtx_REG (PDImode, i));
825 insn = emit_move_insn (predec, gen_rtx_REG (SImode, i));
826 RTX_FRAME_RELATED_P (insn) = 1;
829 if (lookup_attribute ("nesting", attrs))
831 rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX
832 : fkind == NMI_HANDLER ? REG_RETN
834 insn = emit_move_insn (predec, srcreg);
835 RTX_FRAME_RELATED_P (insn) = 1;
838 do_link (spreg, frame_size, all);
840 if (fkind == EXCPT_HANDLER)
842 rtx r0reg = gen_rtx_REG (SImode, REG_R0);
843 rtx r1reg = gen_rtx_REG (SImode, REG_R1);
844 rtx r2reg = gen_rtx_REG (SImode, REG_R2);
847 insn = emit_move_insn (r0reg, gen_rtx_REG (SImode, REG_SEQSTAT));
848 insn = emit_insn (gen_ashrsi3 (r0reg, r0reg, GEN_INT (26)));
849 insn = emit_insn (gen_ashlsi3 (r0reg, r0reg, GEN_INT (26)));
850 insn = emit_move_insn (r1reg, spreg);
851 insn = emit_move_insn (r2reg, gen_rtx_REG (Pmode, REG_FP));
852 insn = emit_insn (gen_addsi3 (r2reg, r2reg, GEN_INT (8)));
856 /* Generate an epilogue suitable for a function of kind FKIND. This is
857 called for interrupt and exception handler epilogues.
858 SPREG contains (reg:SI REG_SP). */
861 expand_interrupt_handler_epilogue (rtx spreg, e_funkind fkind)
864 rtx postinc1 = gen_rtx_POST_INC (SImode, spreg);
865 rtx postinc = gen_rtx_MEM (SImode, postinc1);
866 tree attrs = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
867 bool all = lookup_attribute ("saveall", attrs) != NULL_TREE;
869 /* A slightly crude technique to stop flow from trying to delete "dead"
871 MEM_VOLATILE_P (postinc) = 1;
873 do_unlink (spreg, get_frame_size (), all, 1);
875 if (lookup_attribute ("nesting", attrs))
877 rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX
878 : fkind == NMI_HANDLER ? REG_RETN
880 emit_move_insn (srcreg, postinc);
883 /* If we're calling other functions, they won't save their call-clobbered
884 registers, so we must save (and restore) everything here. */
885 if (!current_function_is_leaf)
888 for (i = REG_CC - 1; i > REG_P7; i--)
890 || df_regs_ever_live_p (i)
891 || (!leaf_function_p () && call_used_regs[i]))
893 if (i == REG_A0 || i == REG_A1)
895 rtx mem = gen_rtx_MEM (PDImode, postinc1);
896 MEM_VOLATILE_P (mem) = 1;
897 emit_move_insn (gen_rtx_REG (PDImode, i), mem);
900 emit_move_insn (gen_rtx_REG (SImode, i), postinc);
903 expand_epilogue_reg_restore (spreg, all, true);
905 emit_move_insn (gen_rtx_REG (SImode, REG_ASTAT), postinc);
907 /* Deallocate any space we left on the stack in case we needed to save the
908 argument registers. */
909 if (fkind == EXCPT_HANDLER)
910 emit_insn (gen_addsi3 (spreg, spreg, GEN_INT (12)));
912 emit_jump_insn (gen_return_internal (GEN_INT (fkind)));
915 /* Used while emitting the prologue to generate code to load the correct value
916 into the PIC register, which is passed in DEST. */
919 bfin_load_pic_reg (rtx dest)
921 struct cgraph_local_info *i = NULL;
924 if (flag_unit_at_a_time)
925 i = cgraph_local_info (current_function_decl);
927 /* Functions local to the translation unit don't need to reload the
928 pic reg, since the caller always passes a usable one. */
930 return pic_offset_table_rtx;
932 if (bfin_lib_id_given)
933 addr = plus_constant (pic_offset_table_rtx, -4 - bfin_library_id * 4);
935 addr = gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
936 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
937 UNSPEC_LIBRARY_OFFSET));
938 insn = emit_insn (gen_movsi (dest, gen_rtx_MEM (Pmode, addr)));
942 /* Generate RTL for the prologue of the current function. */
945 bfin_expand_prologue (void)
947 HOST_WIDE_INT frame_size = get_frame_size ();
948 rtx spreg = gen_rtx_REG (Pmode, REG_SP);
949 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
950 rtx pic_reg_loaded = NULL_RTX;
952 if (fkind != SUBROUTINE)
954 expand_interrupt_handler_prologue (spreg, fkind);
958 if (current_function_limit_stack
959 || TARGET_STACK_CHECK_L1)
962 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM,
963 STACK_POINTER_REGNUM);
964 rtx lim = current_function_limit_stack ? stack_limit_rtx : NULL_RTX;
965 rtx p2reg = gen_rtx_REG (Pmode, REG_P2);
969 emit_move_insn (p2reg, gen_int_mode (0xFFB00000, SImode));
970 emit_move_insn (p2reg, gen_rtx_MEM (Pmode, p2reg));
973 if (GET_CODE (lim) == SYMBOL_REF)
975 if (TARGET_ID_SHARED_LIBRARY)
977 rtx p1reg = gen_rtx_REG (Pmode, REG_P1);
979 pic_reg_loaded = bfin_load_pic_reg (p2reg);
980 val = legitimize_pic_address (stack_limit_rtx, p1reg,
982 emit_move_insn (p1reg, val);
983 frame_related_constant_load (p2reg, offset, FALSE);
984 emit_insn (gen_addsi3 (p2reg, p2reg, p1reg));
989 rtx limit = plus_constant (lim, offset);
990 emit_move_insn (p2reg, limit);
997 emit_move_insn (p2reg, lim);
998 add_to_reg (p2reg, offset, 0, 0);
1001 emit_insn (gen_compare_lt (bfin_cc_rtx, spreg, lim));
1002 emit_insn (gen_trapifcc ());
1004 expand_prologue_reg_save (spreg, 0, false);
1006 do_link (spreg, frame_size, false);
1008 if (TARGET_ID_SHARED_LIBRARY
1010 && (current_function_uses_pic_offset_table
1011 || !current_function_is_leaf))
1012 bfin_load_pic_reg (pic_offset_table_rtx);
1015 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1016 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1017 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1021 bfin_expand_epilogue (int need_return, int eh_return, bool sibcall_p)
1023 rtx spreg = gen_rtx_REG (Pmode, REG_SP);
1024 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
1025 int e = sibcall_p ? -1 : 1;
1027 if (fkind != SUBROUTINE)
1029 expand_interrupt_handler_epilogue (spreg, fkind);
1033 do_unlink (spreg, get_frame_size (), false, e);
1035 expand_epilogue_reg_restore (spreg, false, false);
1037 /* Omit the return insn if this is for a sibcall. */
1042 emit_insn (gen_addsi3 (spreg, spreg, gen_rtx_REG (Pmode, REG_P2)));
1044 emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE)));
1047 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1050 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
1051 unsigned int new_reg)
1053 /* Interrupt functions can only use registers that have already been
1054 saved by the prologue, even if they would normally be
1057 if (funkind (TREE_TYPE (current_function_decl)) != SUBROUTINE
1058 && !df_regs_ever_live_p (new_reg))
1064 /* Return the value of the return address for the frame COUNT steps up
1065 from the current frame, after the prologue.
1066 We punt for everything but the current frame by returning const0_rtx. */
1069 bfin_return_addr_rtx (int count)
1074 return get_hard_reg_initial_val (Pmode, REG_RETS);
1077 /* Try machine-dependent ways of modifying an illegitimate address X
1078 to be legitimate. If we find one, return the new, valid address,
1079 otherwise return NULL_RTX.
1081 OLDX is the address as it was before break_out_memory_refs was called.
1082 In some cases it is useful to look at this to decide what needs to be done.
1084 MODE is the mode of the memory reference. */
1087 legitimize_address (rtx x ATTRIBUTE_UNUSED, rtx oldx ATTRIBUTE_UNUSED,
1088 enum machine_mode mode ATTRIBUTE_UNUSED)
1094 bfin_delegitimize_address (rtx orig_x)
1098 if (GET_CODE (x) != MEM)
1102 if (GET_CODE (x) == PLUS
1103 && GET_CODE (XEXP (x, 1)) == UNSPEC
1104 && XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC
1105 && GET_CODE (XEXP (x, 0)) == REG
1106 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
1107 return XVECEXP (XEXP (x, 1), 0, 0);
1112 /* This predicate is used to compute the length of a load/store insn.
1113 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1114 32-bit instruction. */
1117 effective_address_32bit_p (rtx op, enum machine_mode mode)
1119 HOST_WIDE_INT offset;
1121 mode = GET_MODE (op);
1124 if (GET_CODE (op) != PLUS)
1126 gcc_assert (REG_P (op) || GET_CODE (op) == POST_INC
1127 || GET_CODE (op) == PRE_DEC || GET_CODE (op) == POST_DEC);
1131 if (GET_CODE (XEXP (op, 1)) == UNSPEC)
1134 offset = INTVAL (XEXP (op, 1));
1136 /* All byte loads use a 16-bit offset. */
1137 if (GET_MODE_SIZE (mode) == 1)
1140 if (GET_MODE_SIZE (mode) == 4)
1142 /* Frame pointer relative loads can use a negative offset, all others
1143 are restricted to a small positive one. */
1144 if (XEXP (op, 0) == frame_pointer_rtx)
1145 return offset < -128 || offset > 60;
1146 return offset < 0 || offset > 60;
1149 /* Must be HImode now. */
1150 return offset < 0 || offset > 30;
1153 /* Returns true if X is a memory reference using an I register. */
1155 bfin_dsp_memref_p (rtx x)
1160 if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_INC
1161 || GET_CODE (x) == POST_DEC || GET_CODE (x) == PRE_DEC)
1166 /* Return cost of the memory address ADDR.
1167 All addressing modes are equally cheap on the Blackfin. */
1170 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED)
1175 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1178 print_address_operand (FILE *file, rtx x)
1180 switch (GET_CODE (x))
1183 output_address (XEXP (x, 0));
1184 fprintf (file, "+");
1185 output_address (XEXP (x, 1));
1189 fprintf (file, "--");
1190 output_address (XEXP (x, 0));
1193 output_address (XEXP (x, 0));
1194 fprintf (file, "++");
1197 output_address (XEXP (x, 0));
1198 fprintf (file, "--");
1202 gcc_assert (GET_CODE (x) != MEM);
1203 print_operand (file, x, 0);
1208 /* Adding intp DImode support by Tony
1214 print_operand (FILE *file, rtx x, char code)
1216 enum machine_mode mode;
1220 if (GET_MODE (current_output_insn) == SImode)
1221 fprintf (file, " ||");
1223 fprintf (file, ";");
1227 mode = GET_MODE (x);
1232 switch (GET_CODE (x))
1235 fprintf (file, "e");
1238 fprintf (file, "ne");
1241 fprintf (file, "g");
1244 fprintf (file, "l");
1247 fprintf (file, "ge");
1250 fprintf (file, "le");
1253 fprintf (file, "g");
1256 fprintf (file, "l");
1259 fprintf (file, "ge");
1262 fprintf (file, "le");
1265 output_operand_lossage ("invalid %%j value");
1269 case 'J': /* reverse logic */
1270 switch (GET_CODE(x))
1273 fprintf (file, "ne");
1276 fprintf (file, "e");
1279 fprintf (file, "le");
1282 fprintf (file, "ge");
1285 fprintf (file, "l");
1288 fprintf (file, "g");
1291 fprintf (file, "le");
1294 fprintf (file, "ge");
1297 fprintf (file, "l");
1300 fprintf (file, "g");
1303 output_operand_lossage ("invalid %%J value");
1308 switch (GET_CODE (x))
1313 gcc_assert (REGNO (x) < 32);
1314 fprintf (file, "%s", short_reg_names[REGNO (x)]);
1315 /*fprintf (file, "\n%d\n ", REGNO (x));*/
1318 else if (code == 'd')
1320 gcc_assert (REGNO (x) < 32);
1321 fprintf (file, "%s", high_reg_names[REGNO (x)]);
1324 else if (code == 'w')
1326 gcc_assert (REGNO (x) == REG_A0 || REGNO (x) == REG_A1);
1327 fprintf (file, "%s.w", reg_names[REGNO (x)]);
1329 else if (code == 'x')
1331 gcc_assert (REGNO (x) == REG_A0 || REGNO (x) == REG_A1);
1332 fprintf (file, "%s.x", reg_names[REGNO (x)]);
1334 else if (code == 'v')
1336 if (REGNO (x) == REG_A0)
1337 fprintf (file, "AV0");
1338 else if (REGNO (x) == REG_A1)
1339 fprintf (file, "AV1");
1341 output_operand_lossage ("invalid operand for code '%c'", code);
1343 else if (code == 'D')
1345 fprintf (file, "%s", dregs_pair_names[REGNO (x)]);
1347 else if (code == 'H')
1349 gcc_assert (mode == DImode || mode == DFmode);
1350 gcc_assert (REG_P (x));
1351 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
1353 else if (code == 'T')
1355 gcc_assert (D_REGNO_P (REGNO (x)));
1356 fprintf (file, "%s", byte_reg_names[REGNO (x)]);
1359 fprintf (file, "%s", reg_names[REGNO (x)]);
1365 print_address_operand (file, x);
1377 fputs ("(FU)", file);
1380 fputs ("(T)", file);
1383 fputs ("(TFU)", file);
1386 fputs ("(W32)", file);
1389 fputs ("(IS)", file);
1392 fputs ("(IU)", file);
1395 fputs ("(IH)", file);
1398 fputs ("(M)", file);
1401 fputs ("(IS,M)", file);
1404 fputs ("(ISS2)", file);
1407 fputs ("(S2RND)", file);
1414 else if (code == 'b')
1416 if (INTVAL (x) == 0)
1418 else if (INTVAL (x) == 1)
1424 /* Moves to half registers with d or h modifiers always use unsigned
1426 else if (code == 'd')
1427 x = GEN_INT ((INTVAL (x) >> 16) & 0xffff);
1428 else if (code == 'h')
1429 x = GEN_INT (INTVAL (x) & 0xffff);
1430 else if (code == 'N')
1431 x = GEN_INT (-INTVAL (x));
1432 else if (code == 'X')
1433 x = GEN_INT (exact_log2 (0xffffffff & INTVAL (x)));
1434 else if (code == 'Y')
1435 x = GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x)));
1436 else if (code == 'Z')
1437 /* Used for LINK insns. */
1438 x = GEN_INT (-8 - INTVAL (x));
1443 output_addr_const (file, x);
1447 output_operand_lossage ("invalid const_double operand");
1451 switch (XINT (x, 1))
1453 case UNSPEC_MOVE_PIC:
1454 output_addr_const (file, XVECEXP (x, 0, 0));
1455 fprintf (file, "@GOT");
1458 case UNSPEC_MOVE_FDPIC:
1459 output_addr_const (file, XVECEXP (x, 0, 0));
1460 fprintf (file, "@GOT17M4");
1463 case UNSPEC_FUNCDESC_GOT17M4:
1464 output_addr_const (file, XVECEXP (x, 0, 0));
1465 fprintf (file, "@FUNCDESC_GOT17M4");
1468 case UNSPEC_LIBRARY_OFFSET:
1469 fprintf (file, "_current_shared_library_p5_offset_");
1478 output_addr_const (file, x);
1483 /* Argument support functions. */
1485 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1486 for a call to a function whose data type is FNTYPE.
1487 For a library call, FNTYPE is 0.
1488 VDSP C Compiler manual, our ABI says that
1489 first 3 words of arguments will use R0, R1 and R2.
1493 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
1494 rtx libname ATTRIBUTE_UNUSED)
1496 static CUMULATIVE_ARGS zero_cum;
1500 /* Set up the number of registers to use for passing arguments. */
1502 cum->nregs = max_arg_registers;
1503 cum->arg_regs = arg_regs;
1505 cum->call_cookie = CALL_NORMAL;
1506 /* Check for a longcall attribute. */
1507 if (fntype && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
1508 cum->call_cookie |= CALL_SHORT;
1509 else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
1510 cum->call_cookie |= CALL_LONG;
1515 /* Update the data in CUM to advance over an argument
1516 of mode MODE and data type TYPE.
1517 (TYPE is null for libcalls where that information may not be available.) */
1520 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1521 int named ATTRIBUTE_UNUSED)
1523 int count, bytes, words;
1525 bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1526 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1528 cum->words += words;
1529 cum->nregs -= words;
1531 if (cum->nregs <= 0)
1534 cum->arg_regs = NULL;
1538 for (count = 1; count <= words; count++)
1545 /* Define where to put the arguments to a function.
1546 Value is zero to push the argument on the stack,
1547 or a hard register in which to store the argument.
1549 MODE is the argument's machine mode.
1550 TYPE is the data type of the argument (as a tree).
1551 This is null for libcalls where that information may
1553 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1554 the preceding args and about the function being called.
1555 NAMED is nonzero if this argument is a named parameter
1556 (otherwise it is an extra parameter matching an ellipsis). */
1559 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1560 int named ATTRIBUTE_UNUSED)
1563 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1565 if (mode == VOIDmode)
1566 /* Compute operand 2 of the call insn. */
1567 return GEN_INT (cum->call_cookie);
1573 return gen_rtx_REG (mode, *(cum->arg_regs));
1578 /* For an arg passed partly in registers and partly in memory,
1579 this is the number of bytes passed in registers.
1580 For args passed entirely in registers or entirely in memory, zero.
1582 Refer VDSP C Compiler manual, our ABI.
1583 First 3 words are in registers. So, if an argument is larger
1584 than the registers available, it will span the register and
1588 bfin_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1589 tree type ATTRIBUTE_UNUSED,
1590 bool named ATTRIBUTE_UNUSED)
1593 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1594 int bytes_left = cum->nregs * UNITS_PER_WORD;
1599 if (bytes_left == 0)
1601 if (bytes > bytes_left)
1606 /* Variable sized types are passed by reference. */
1609 bfin_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1610 enum machine_mode mode ATTRIBUTE_UNUSED,
1611 tree type, bool named ATTRIBUTE_UNUSED)
1613 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
1616 /* Decide whether a type should be returned in memory (true)
1617 or in a register (false). This is called by the macro
1618 RETURN_IN_MEMORY. */
1621 bfin_return_in_memory (tree type)
1623 int size = int_size_in_bytes (type);
1624 return size > 2 * UNITS_PER_WORD || size == -1;
1627 /* Register in which address to store a structure value
1628 is passed to a function. */
1630 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
1631 int incoming ATTRIBUTE_UNUSED)
1633 return gen_rtx_REG (Pmode, REG_P0);
1636 /* Return true when register may be used to pass function parameters. */
1639 function_arg_regno_p (int n)
1642 for (i = 0; arg_regs[i] != -1; i++)
1643 if (n == arg_regs[i])
1648 /* Returns 1 if OP contains a symbol reference */
1651 symbolic_reference_mentioned_p (rtx op)
1653 register const char *fmt;
1656 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1659 fmt = GET_RTX_FORMAT (GET_CODE (op));
1660 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1666 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1667 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1671 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1678 /* Decide whether we can make a sibling call to a function. DECL is the
1679 declaration of the function being targeted by the call and EXP is the
1680 CALL_EXPR representing the call. */
1683 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
1684 tree exp ATTRIBUTE_UNUSED)
1686 e_funkind fkind = funkind (TREE_TYPE (current_function_decl));
1687 if (fkind != SUBROUTINE)
1689 if (!TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA)
1692 /* When compiling for ID shared libraries, can't sibcall a local function
1693 from a non-local function, because the local function thinks it does
1694 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1695 sibcall epilogue, and we end up with the wrong value in P5. */
1697 if (!flag_unit_at_a_time || decl == NULL)
1698 /* Not enough information. */
1702 struct cgraph_local_info *this_func, *called_func;
1704 this_func = cgraph_local_info (current_function_decl);
1705 called_func = cgraph_local_info (decl);
1706 return !called_func->local || this_func->local;
1710 /* Emit RTL insns to initialize the variable parts of a trampoline at
1711 TRAMP. FNADDR is an RTX for the address of the function's pure
1712 code. CXT is an RTX for the static chain value for the function. */
1715 initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
1717 rtx t1 = copy_to_reg (fnaddr);
1718 rtx t2 = copy_to_reg (cxt);
1724 rtx a = memory_address (Pmode, plus_constant (tramp, 8));
1725 addr = memory_address (Pmode, tramp);
1726 emit_move_insn (gen_rtx_MEM (SImode, addr), a);
1730 addr = memory_address (Pmode, plus_constant (tramp, i + 2));
1731 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1));
1732 emit_insn (gen_ashrsi3 (t1, t1, GEN_INT (16)));
1733 addr = memory_address (Pmode, plus_constant (tramp, i + 6));
1734 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t1));
1736 addr = memory_address (Pmode, plus_constant (tramp, i + 10));
1737 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2));
1738 emit_insn (gen_ashrsi3 (t2, t2, GEN_INT (16)));
1739 addr = memory_address (Pmode, plus_constant (tramp, i + 14));
1740 emit_move_insn (gen_rtx_MEM (HImode, addr), gen_lowpart (HImode, t2));
1743 /* Emit insns to move operands[1] into operands[0]. */
1746 emit_pic_move (rtx *operands, enum machine_mode mode ATTRIBUTE_UNUSED)
1748 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
1750 gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed));
1751 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
1752 operands[1] = force_reg (SImode, operands[1]);
1754 operands[1] = legitimize_pic_address (operands[1], temp,
1755 TARGET_FDPIC ? OUR_FDPIC_REG
1756 : pic_offset_table_rtx);
1759 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1760 Returns true if no further code must be generated, false if the caller
1761 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1764 expand_move (rtx *operands, enum machine_mode mode)
1766 rtx op = operands[1];
1767 if ((TARGET_ID_SHARED_LIBRARY || TARGET_FDPIC)
1768 && SYMBOLIC_CONST (op))
1769 emit_pic_move (operands, mode);
1770 else if (mode == SImode && GET_CODE (op) == CONST
1771 && GET_CODE (XEXP (op, 0)) == PLUS
1772 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
1773 && !bfin_legitimate_constant_p (op))
1775 rtx dest = operands[0];
1777 gcc_assert (!reload_in_progress && !reload_completed);
1779 op0 = force_reg (mode, XEXP (op, 0));
1781 if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode))
1782 op1 = force_reg (mode, op1);
1783 if (GET_CODE (dest) == MEM)
1784 dest = gen_reg_rtx (mode);
1785 emit_insn (gen_addsi3 (dest, op0, op1));
1786 if (dest == operands[0])
1790 /* Don't generate memory->memory or constant->memory moves, go through a
1792 else if ((reload_in_progress | reload_completed) == 0
1793 && GET_CODE (operands[0]) == MEM
1794 && GET_CODE (operands[1]) != REG)
1795 operands[1] = force_reg (mode, operands[1]);
1799 /* Split one or more DImode RTL references into pairs of SImode
1800 references. The RTL can be REG, offsettable MEM, integer constant, or
1801 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1802 split and "num" is its length. lo_half and hi_half are output arrays
1803 that parallel "operands". */
1806 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
1810 rtx op = operands[num];
1812 /* simplify_subreg refuse to split volatile memory addresses,
1813 but we still have to handle it. */
1814 if (GET_CODE (op) == MEM)
1816 lo_half[num] = adjust_address (op, SImode, 0);
1817 hi_half[num] = adjust_address (op, SImode, 4);
1821 lo_half[num] = simplify_gen_subreg (SImode, op,
1822 GET_MODE (op) == VOIDmode
1823 ? DImode : GET_MODE (op), 0);
1824 hi_half[num] = simplify_gen_subreg (SImode, op,
1825 GET_MODE (op) == VOIDmode
1826 ? DImode : GET_MODE (op), 4);
1832 bfin_longcall_p (rtx op, int call_cookie)
1834 gcc_assert (GET_CODE (op) == SYMBOL_REF);
1835 if (call_cookie & CALL_SHORT)
1837 if (call_cookie & CALL_LONG)
1839 if (TARGET_LONG_CALLS)
1844 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
1845 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
1846 SIBCALL is nonzero if this is a sibling call. */
1849 bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
1851 rtx use = NULL, call;
1852 rtx callee = XEXP (fnaddr, 0);
1853 int nelts = 2 + !!sibcall;
1855 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REGNO);
1858 /* In an untyped call, we can get NULL for operand 2. */
1859 if (cookie == NULL_RTX)
1860 cookie = const0_rtx;
1862 /* Static functions and indirect calls don't need the pic register. */
1863 if (!TARGET_FDPIC && flag_pic
1864 && GET_CODE (callee) == SYMBOL_REF
1865 && !SYMBOL_REF_LOCAL_P (callee))
1866 use_reg (&use, pic_offset_table_rtx);
1870 if (GET_CODE (callee) != SYMBOL_REF
1871 || bfin_longcall_p (callee, INTVAL (cookie)))
1874 if (! address_operand (addr, Pmode))
1875 addr = force_reg (Pmode, addr);
1877 fnaddr = gen_reg_rtx (SImode);
1878 emit_insn (gen_load_funcdescsi (fnaddr, addr));
1879 fnaddr = gen_rtx_MEM (Pmode, fnaddr);
1881 picreg = gen_reg_rtx (SImode);
1882 emit_insn (gen_load_funcdescsi (picreg,
1883 plus_constant (addr, 4)));
1888 else if ((!register_no_elim_operand (callee, Pmode)
1889 && GET_CODE (callee) != SYMBOL_REF)
1890 || (GET_CODE (callee) == SYMBOL_REF
1891 && ((TARGET_ID_SHARED_LIBRARY && !TARGET_LEAF_ID_SHARED_LIBRARY)
1892 || bfin_longcall_p (callee, INTVAL (cookie)))))
1894 callee = copy_to_mode_reg (Pmode, callee);
1895 fnaddr = gen_rtx_MEM (Pmode, callee);
1897 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
1900 call = gen_rtx_SET (VOIDmode, retval, call);
1902 pat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nelts));
1904 XVECEXP (pat, 0, n++) = call;
1906 XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg);
1907 XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie);
1909 XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode);
1910 call = emit_call_insn (pat);
1912 CALL_INSN_FUNCTION_USAGE (call) = use;
1915 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
1918 hard_regno_mode_ok (int regno, enum machine_mode mode)
1920 /* Allow only dregs to store value of mode HI or QI */
1921 enum reg_class class = REGNO_REG_CLASS (regno);
1926 if (mode == V2HImode)
1927 return D_REGNO_P (regno);
1928 if (class == CCREGS)
1929 return mode == BImode;
1930 if (mode == PDImode || mode == V2PDImode)
1931 return regno == REG_A0 || regno == REG_A1;
1933 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
1934 up with a bad register class (such as ALL_REGS) for DImode. */
1936 return regno < REG_M3;
1939 && TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
1942 return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
1945 /* Implements target hook vector_mode_supported_p. */
1948 bfin_vector_mode_supported_p (enum machine_mode mode)
1950 return mode == V2HImode;
1953 /* Return the cost of moving data from a register in class CLASS1 to
1954 one in class CLASS2. A cost of 2 is the default. */
1957 bfin_register_move_cost (enum machine_mode mode,
1958 enum reg_class class1, enum reg_class class2)
1960 /* These need secondary reloads, so they're more expensive. */
1961 if ((class1 == CCREGS && class2 != DREGS)
1962 || (class1 != DREGS && class2 == CCREGS))
1965 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
1969 /* There are some stalls involved when moving from a DREG to a different
1970 class reg, and using the value in one of the following instructions.
1971 Attempt to model this by slightly discouraging such moves. */
1972 if (class1 == DREGS && class2 != DREGS)
1975 if (GET_MODE_CLASS (mode) == MODE_INT)
1977 /* Discourage trying to use the accumulators. */
1978 if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0)
1979 || TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1)
1980 || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0)
1981 || TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1))
1987 /* Return the cost of moving data of mode M between a
1988 register and memory. A value of 2 is the default; this cost is
1989 relative to those in `REGISTER_MOVE_COST'.
1991 ??? In theory L1 memory has single-cycle latency. We should add a switch
1992 that tells the compiler whether we expect to use only L1 memory for the
1993 program; it'll make the costs more accurate. */
1996 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1997 enum reg_class class,
1998 int in ATTRIBUTE_UNUSED)
2000 /* Make memory accesses slightly more expensive than any register-register
2001 move. Also, penalize non-DP registers, since they need secondary
2002 reloads to load and store. */
2003 if (! reg_class_subset_p (class, DPREGS))
2009 /* Inform reload about cases where moving X with a mode MODE to a register in
2010 CLASS requires an extra scratch register. Return the class needed for the
2011 scratch register. */
2013 static enum reg_class
2014 bfin_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, enum reg_class class,
2015 enum machine_mode mode, secondary_reload_info *sri)
2017 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2018 in most other cases we can also use PREGS. */
2019 enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS;
2020 enum reg_class x_class = NO_REGS;
2021 enum rtx_code code = GET_CODE (x);
2024 x = SUBREG_REG (x), code = GET_CODE (x);
2027 int regno = REGNO (x);
2028 if (regno >= FIRST_PSEUDO_REGISTER)
2029 regno = reg_renumber[regno];
2034 x_class = REGNO_REG_CLASS (regno);
2037 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2038 This happens as a side effect of register elimination, and we need
2039 a scratch register to do it. */
2040 if (fp_plus_const_operand (x, mode))
2042 rtx op2 = XEXP (x, 1);
2043 int large_constant_p = ! CONST_7BIT_IMM_P (INTVAL (op2));
2045 if (class == PREGS || class == PREGS_CLOBBERED)
2047 /* If destination is a DREG, we can do this without a scratch register
2048 if the constant is valid for an add instruction. */
2049 if ((class == DREGS || class == DPREGS)
2050 && ! large_constant_p)
2052 /* Reloading to anything other than a DREG? Use a PREG scratch
2054 sri->icode = CODE_FOR_reload_insi;
2058 /* Data can usually be moved freely between registers of most classes.
2059 AREGS are an exception; they can only move to or from another register
2060 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2061 if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS)
2062 return (class == DREGS || class == AREGS || class == EVEN_AREGS
2063 || class == ODD_AREGS
2066 if (class == AREGS || class == EVEN_AREGS || class == ODD_AREGS)
2068 if (x != const0_rtx && x_class != DREGS)
2074 /* CCREGS can only be moved from/to DREGS. */
2075 if (class == CCREGS && x_class != DREGS)
2077 if (x_class == CCREGS && class != DREGS)
2080 /* All registers other than AREGS can load arbitrary constants. The only
2081 case that remains is MEM. */
2083 if (! reg_class_subset_p (class, default_class))
2084 return default_class;
2088 /* Implement TARGET_HANDLE_OPTION. */
2091 bfin_handle_option (size_t code, const char *arg, int value)
2095 case OPT_mshared_library_id_:
2096 if (value > MAX_LIBRARY_ID)
2097 error ("-mshared-library-id=%s is not between 0 and %d",
2098 arg, MAX_LIBRARY_ID);
2099 bfin_lib_id_given = 1;
2103 if (strcmp (arg, "bf531") == 0)
2104 bfin_cpu_type = BFIN_CPU_BF531;
2105 else if (strcmp (arg, "bf532") == 0)
2106 bfin_cpu_type = BFIN_CPU_BF532;
2107 else if (strcmp (arg, "bf533") == 0)
2108 bfin_cpu_type = BFIN_CPU_BF533;
2109 else if (strcmp (arg, "bf534") == 0)
2110 bfin_cpu_type = BFIN_CPU_BF534;
2111 else if (strcmp (arg, "bf536") == 0)
2112 bfin_cpu_type = BFIN_CPU_BF536;
2113 else if (strcmp (arg, "bf537") == 0)
2114 bfin_cpu_type = BFIN_CPU_BF537;
2115 else if (strcmp (arg, "bf561") == 0)
2117 warning (0, "bf561 support is incomplete yet.");
2118 bfin_cpu_type = BFIN_CPU_BF561;
2129 static struct machine_function *
2130 bfin_init_machine_status (void)
2132 struct machine_function *f;
2134 f = ggc_alloc_cleared (sizeof (struct machine_function));
2139 /* Implement the macro OVERRIDE_OPTIONS. */
2142 override_options (void)
2144 if (TARGET_OMIT_LEAF_FRAME_POINTER)
2145 flag_omit_frame_pointer = 1;
2147 /* Library identification */
2148 if (bfin_lib_id_given && ! TARGET_ID_SHARED_LIBRARY)
2149 error ("-mshared-library-id= specified without -mid-shared-library");
2151 if (TARGET_ID_SHARED_LIBRARY && flag_pic == 0)
2154 if (stack_limit_rtx && TARGET_STACK_CHECK_L1)
2155 error ("Can't use multiple stack checking methods together.");
2157 if (TARGET_ID_SHARED_LIBRARY && TARGET_FDPIC)
2158 error ("ID shared libraries and FD-PIC mode can't be used together.");
2160 /* Don't allow the user to specify -mid-shared-library and -msep-data
2161 together, as it makes little sense from a user's point of view... */
2162 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
2163 error ("cannot specify both -msep-data and -mid-shared-library");
2164 /* ... internally, however, it's nearly the same. */
2165 if (TARGET_SEP_DATA)
2166 target_flags |= MASK_ID_SHARED_LIBRARY | MASK_LEAF_ID_SHARED_LIBRARY;
2168 /* There is no single unaligned SI op for PIC code. Sometimes we
2169 need to use ".4byte" and sometimes we need to use ".picptr".
2170 See bfin_assemble_integer for details. */
2172 targetm.asm_out.unaligned_op.si = 0;
2174 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2175 since we don't support it and it'll just break. */
2176 if (flag_pic && !TARGET_FDPIC && !TARGET_ID_SHARED_LIBRARY)
2179 flag_schedule_insns = 0;
2181 /* Passes after sched2 can break the helpful TImode annotations that
2182 haifa-sched puts on every insn. Just do scheduling in reorg. */
2183 bfin_flag_schedule_insns2 = flag_schedule_insns_after_reload;
2184 flag_schedule_insns_after_reload = 0;
2186 init_machine_status = bfin_init_machine_status;
2189 /* Return the destination address of BRANCH.
2190 We need to use this instead of get_attr_length, because the
2191 cbranch_with_nops pattern conservatively sets its length to 6, and
2192 we still prefer to use shorter sequences. */
2195 branch_dest (rtx branch)
2199 rtx pat = PATTERN (branch);
2200 if (GET_CODE (pat) == PARALLEL)
2201 pat = XVECEXP (pat, 0, 0);
2202 dest = SET_SRC (pat);
2203 if (GET_CODE (dest) == IF_THEN_ELSE)
2204 dest = XEXP (dest, 1);
2205 dest = XEXP (dest, 0);
2206 dest_uid = INSN_UID (dest);
2207 return INSN_ADDRESSES (dest_uid);
2210 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2211 it's a branch that's predicted taken. */
2214 cbranch_predicted_taken_p (rtx insn)
2216 rtx x = find_reg_note (insn, REG_BR_PROB, 0);
2220 int pred_val = INTVAL (XEXP (x, 0));
2222 return pred_val >= REG_BR_PROB_BASE / 2;
2228 /* Templates for use by asm_conditional_branch. */
2230 static const char *ccbranch_templates[][3] = {
2231 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2232 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2233 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2234 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2237 /* Output INSN, which is a conditional branch instruction with operands
2240 We deal with the various forms of conditional branches that can be generated
2241 by bfin_reorg to prevent the hardware from doing speculative loads, by
2242 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2243 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2244 Either of these is only necessary if the branch is short, otherwise the
2245 template we use ends in an unconditional jump which flushes the pipeline
2249 asm_conditional_branch (rtx insn, rtx *operands, int n_nops, int predict_taken)
2251 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2252 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2253 is to be taken from start of if cc rather than jump.
2254 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2256 int len = (offset >= -1024 && offset <= 1022 ? 0
2257 : offset >= -4094 && offset <= 4096 ? 1
2259 int bp = predict_taken && len == 0 ? 1 : cbranch_predicted_taken_p (insn);
2260 int idx = (bp << 1) | (GET_CODE (operands[0]) == EQ ? BRF : BRT);
2261 output_asm_insn (ccbranch_templates[idx][len], operands);
2262 gcc_assert (n_nops == 0 || !bp);
2264 while (n_nops-- > 0)
2265 output_asm_insn ("nop;", NULL);
2268 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2269 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2272 bfin_gen_compare (rtx cmp, enum machine_mode mode ATTRIBUTE_UNUSED)
2274 enum rtx_code code1, code2;
2275 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2276 rtx tem = bfin_cc_rtx;
2277 enum rtx_code code = GET_CODE (cmp);
2279 /* If we have a BImode input, then we already have a compare result, and
2280 do not need to emit another comparison. */
2281 if (GET_MODE (op0) == BImode)
2283 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
2284 tem = op0, code2 = code;
2289 /* bfin has these conditions */
2299 code1 = reverse_condition (code);
2303 emit_insn (gen_rtx_SET (BImode, tem,
2304 gen_rtx_fmt_ee (code1, BImode, op0, op1)));
2307 return gen_rtx_fmt_ee (code2, BImode, tem, CONST0_RTX (BImode));
2310 /* Return nonzero iff C has exactly one bit set if it is interpreted
2311 as a 32-bit constant. */
2314 log2constp (unsigned HOST_WIDE_INT c)
2317 return c != 0 && (c & (c-1)) == 0;
2320 /* Returns the number of consecutive least significant zeros in the binary
2321 representation of *V.
2322 We modify *V to contain the original value arithmetically shifted right by
2323 the number of zeroes. */
2326 shiftr_zero (HOST_WIDE_INT *v)
2328 unsigned HOST_WIDE_INT tmp = *v;
2329 unsigned HOST_WIDE_INT sgn;
2335 sgn = tmp & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1));
2336 while ((tmp & 0x1) == 0 && n <= 32)
2338 tmp = (tmp >> 1) | sgn;
2345 /* After reload, split the load of an immediate constant. OPERANDS are the
2346 operands of the movsi_insn pattern which we are splitting. We return
2347 nonzero if we emitted a sequence to load the constant, zero if we emitted
2348 nothing because we want to use the splitter's default sequence. */
2351 split_load_immediate (rtx operands[])
2353 HOST_WIDE_INT val = INTVAL (operands[1]);
2355 HOST_WIDE_INT shifted = val;
2356 HOST_WIDE_INT shifted_compl = ~val;
2357 int num_zero = shiftr_zero (&shifted);
2358 int num_compl_zero = shiftr_zero (&shifted_compl);
2359 unsigned int regno = REGNO (operands[0]);
2361 /* This case takes care of single-bit set/clear constants, which we could
2362 also implement with BITSET/BITCLR. */
2364 && shifted >= -32768 && shifted < 65536
2365 && (D_REGNO_P (regno)
2366 || (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2)))
2368 emit_insn (gen_movsi (operands[0], GEN_INT (shifted)));
2369 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero)));
2374 tmp |= -(tmp & 0x8000);
2376 /* If high word has one bit set or clear, try to use a bit operation. */
2377 if (D_REGNO_P (regno))
2379 if (log2constp (val & 0xFFFF0000))
2381 emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF)));
2382 emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000)));
2385 else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0)
2387 emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
2388 emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF)));
2392 if (D_REGNO_P (regno))
2394 if (CONST_7BIT_IMM_P (tmp))
2396 emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
2397 emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536)));
2401 if ((val & 0xFFFF0000) == 0)
2403 emit_insn (gen_movsi (operands[0], const0_rtx));
2404 emit_insn (gen_movsi_low (operands[0], operands[0], operands[1]));
2408 if ((val & 0xFFFF0000) == 0xFFFF0000)
2410 emit_insn (gen_movsi (operands[0], constm1_rtx));
2411 emit_insn (gen_movsi_low (operands[0], operands[0], operands[1]));
2416 /* Need DREGs for the remaining case. */
2421 && num_compl_zero && CONST_7BIT_IMM_P (shifted_compl))
2423 /* If optimizing for size, generate a sequence that has more instructions
2425 emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl)));
2426 emit_insn (gen_ashlsi3 (operands[0], operands[0],
2427 GEN_INT (num_compl_zero)));
2428 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
2434 /* Return true if the legitimate memory address for a memory operand of mode
2435 MODE. Return false if not. */
2438 bfin_valid_add (enum machine_mode mode, HOST_WIDE_INT value)
2440 unsigned HOST_WIDE_INT v = value > 0 ? value : -value;
2441 int sz = GET_MODE_SIZE (mode);
2442 int shift = sz == 1 ? 0 : sz == 2 ? 1 : 2;
2443 /* The usual offsettable_memref machinery doesn't work so well for this
2444 port, so we deal with the problem here. */
2445 if (value > 0 && sz == 8)
2447 return (v & ~(0x7fff << shift)) == 0;
2451 bfin_valid_reg_p (unsigned int regno, int strict, enum machine_mode mode,
2452 enum rtx_code outer_code)
2455 return REGNO_OK_FOR_BASE_STRICT_P (regno, mode, outer_code, SCRATCH);
2457 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno, mode, outer_code, SCRATCH);
2461 bfin_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2463 switch (GET_CODE (x)) {
2465 if (bfin_valid_reg_p (REGNO (x), strict, mode, MEM))
2469 if (REG_P (XEXP (x, 0))
2470 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS)
2471 && ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode)
2472 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2473 && bfin_valid_add (mode, INTVAL (XEXP (x, 1))))))
2478 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode)
2479 && REG_P (XEXP (x, 0))
2480 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, POST_INC))
2483 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode)
2484 && XEXP (x, 0) == stack_pointer_rtx
2485 && REG_P (XEXP (x, 0))
2486 && bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PRE_DEC))
2495 /* Decide whether we can force certain constants to memory. If we
2496 decide we can't, the caller should be able to cope with it in
2500 bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
2502 /* We have only one class of non-legitimate constants, and our movsi
2503 expander knows how to handle them. Dropping these constants into the
2504 data section would only shift the problem - we'd still get relocs
2505 outside the object, in the data section rather than the text section. */
2509 /* Ensure that for any constant of the form symbol + offset, the offset
2510 remains within the object. Any other constants are ok.
2511 This ensures that flat binaries never have to deal with relocations
2512 crossing section boundaries. */
2515 bfin_legitimate_constant_p (rtx x)
2518 HOST_WIDE_INT offset;
2520 if (GET_CODE (x) != CONST)
2524 gcc_assert (GET_CODE (x) == PLUS);
2528 if (GET_CODE (sym) != SYMBOL_REF
2529 || GET_CODE (x) != CONST_INT)
2531 offset = INTVAL (x);
2533 if (SYMBOL_REF_DECL (sym) == 0)
2536 || offset >= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym))))
2543 bfin_rtx_costs (rtx x, int code, int outer_code, int *total)
2545 int cost2 = COSTS_N_INSNS (1);
2551 if (outer_code == SET || outer_code == PLUS)
2552 *total = CONST_7BIT_IMM_P (INTVAL (x)) ? 0 : cost2;
2553 else if (outer_code == AND)
2554 *total = log2constp (~INTVAL (x)) ? 0 : cost2;
2555 else if (outer_code == LE || outer_code == LT || outer_code == EQ)
2556 *total = (INTVAL (x) >= -4 && INTVAL (x) <= 3) ? 0 : cost2;
2557 else if (outer_code == LEU || outer_code == LTU)
2558 *total = (INTVAL (x) >= 0 && INTVAL (x) <= 7) ? 0 : cost2;
2559 else if (outer_code == MULT)
2560 *total = (INTVAL (x) == 2 || INTVAL (x) == 4) ? 0 : cost2;
2561 else if (outer_code == ASHIFT && (INTVAL (x) == 1 || INTVAL (x) == 2))
2563 else if (outer_code == ASHIFT || outer_code == ASHIFTRT
2564 || outer_code == LSHIFTRT)
2565 *total = (INTVAL (x) >= 0 && INTVAL (x) <= 31) ? 0 : cost2;
2566 else if (outer_code == IOR || outer_code == XOR)
2567 *total = (INTVAL (x) & (INTVAL (x) - 1)) == 0 ? 0 : cost2;
2576 *total = COSTS_N_INSNS (2);
2582 if (GET_MODE (x) == SImode)
2584 if (GET_CODE (op0) == MULT
2585 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
2587 HOST_WIDE_INT val = INTVAL (XEXP (op0, 1));
2588 if (val == 2 || val == 4)
2591 *total += rtx_cost (XEXP (op0, 0), outer_code);
2592 *total += rtx_cost (op1, outer_code);
2597 if (GET_CODE (op0) != REG
2598 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2599 *total += rtx_cost (op0, SET);
2600 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2601 towards creating too many induction variables. */
2602 if (!reg_or_7bit_operand (op1, SImode))
2603 *total += rtx_cost (op1, SET);
2606 else if (GET_MODE (x) == DImode)
2609 if (GET_CODE (op1) != CONST_INT
2610 || !CONST_7BIT_IMM_P (INTVAL (op1)))
2611 *total += rtx_cost (op1, PLUS);
2612 if (GET_CODE (op0) != REG
2613 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2614 *total += rtx_cost (op0, PLUS);
2619 if (GET_MODE (x) == DImode)
2628 if (GET_MODE (x) == DImode)
2635 if (GET_CODE (op0) != REG
2636 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2637 *total += rtx_cost (op0, code);
2647 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2650 if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT)
2651 || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND)
2652 || (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
2653 || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT))
2660 if (GET_CODE (op0) != REG
2661 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2662 *total += rtx_cost (op0, code);
2664 if (GET_MODE (x) == DImode)
2670 if (GET_MODE (x) != SImode)
2675 if (! rhs_andsi3_operand (XEXP (x, 1), SImode))
2676 *total += rtx_cost (XEXP (x, 1), code);
2680 if (! regorlog2_operand (XEXP (x, 1), SImode))
2681 *total += rtx_cost (XEXP (x, 1), code);
2688 if (outer_code == SET
2689 && XEXP (x, 1) == const1_rtx
2690 && GET_CODE (XEXP (x, 2)) == CONST_INT)
2706 if (GET_CODE (op0) == GET_CODE (op1)
2707 && (GET_CODE (op0) == ZERO_EXTEND
2708 || GET_CODE (op0) == SIGN_EXTEND))
2710 *total = COSTS_N_INSNS (1);
2711 op0 = XEXP (op0, 0);
2712 op1 = XEXP (op1, 0);
2714 else if (optimize_size)
2715 *total = COSTS_N_INSNS (1);
2717 *total = COSTS_N_INSNS (3);
2719 if (GET_CODE (op0) != REG
2720 && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
2721 *total += rtx_cost (op0, MULT);
2722 if (GET_CODE (op1) != REG
2723 && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
2724 *total += rtx_cost (op1, MULT);
2730 *total = COSTS_N_INSNS (32);
2735 if (outer_code == SET)
2744 /* Used for communication between {push,pop}_multiple_operation (which
2745 we use not only as a predicate) and the corresponding output functions. */
2746 static int first_preg_to_save, first_dreg_to_save;
2749 push_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2751 int lastdreg = 8, lastpreg = 6;
2754 first_preg_to_save = lastpreg;
2755 first_dreg_to_save = lastdreg;
2756 for (i = 1, group = 0; i < XVECLEN (op, 0) - 1; i++)
2758 rtx t = XVECEXP (op, 0, i);
2762 if (GET_CODE (t) != SET)
2766 dest = SET_DEST (t);
2767 if (GET_CODE (dest) != MEM || ! REG_P (src))
2769 dest = XEXP (dest, 0);
2770 if (GET_CODE (dest) != PLUS
2771 || ! REG_P (XEXP (dest, 0))
2772 || REGNO (XEXP (dest, 0)) != REG_SP
2773 || GET_CODE (XEXP (dest, 1)) != CONST_INT
2774 || INTVAL (XEXP (dest, 1)) != -i * 4)
2777 regno = REGNO (src);
2780 if (D_REGNO_P (regno))
2783 first_dreg_to_save = lastdreg = regno - REG_R0;
2785 else if (regno >= REG_P0 && regno <= REG_P7)
2788 first_preg_to_save = lastpreg = regno - REG_P0;
2798 if (regno >= REG_P0 && regno <= REG_P7)
2801 first_preg_to_save = lastpreg = regno - REG_P0;
2803 else if (regno != REG_R0 + lastdreg + 1)
2808 else if (group == 2)
2810 if (regno != REG_P0 + lastpreg + 1)
2819 pop_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2821 int lastdreg = 8, lastpreg = 6;
2824 for (i = 1, group = 0; i < XVECLEN (op, 0); i++)
2826 rtx t = XVECEXP (op, 0, i);
2830 if (GET_CODE (t) != SET)
2834 dest = SET_DEST (t);
2835 if (GET_CODE (src) != MEM || ! REG_P (dest))
2837 src = XEXP (src, 0);
2841 if (! REG_P (src) || REGNO (src) != REG_SP)
2844 else if (GET_CODE (src) != PLUS
2845 || ! REG_P (XEXP (src, 0))
2846 || REGNO (XEXP (src, 0)) != REG_SP
2847 || GET_CODE (XEXP (src, 1)) != CONST_INT
2848 || INTVAL (XEXP (src, 1)) != (i - 1) * 4)
2851 regno = REGNO (dest);
2854 if (regno == REG_R7)
2859 else if (regno != REG_P0 + lastpreg - 1)
2864 else if (group == 1)
2866 if (regno != REG_R0 + lastdreg - 1)
2872 first_dreg_to_save = lastdreg;
2873 first_preg_to_save = lastpreg;
2877 /* Emit assembly code for one multi-register push described by INSN, with
2878 operands in OPERANDS. */
2881 output_push_multiple (rtx insn, rtx *operands)
2886 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2887 ok = push_multiple_operation (PATTERN (insn), VOIDmode);
2890 if (first_dreg_to_save == 8)
2891 sprintf (buf, "[--sp] = ( p5:%d );\n", first_preg_to_save);
2892 else if (first_preg_to_save == 6)
2893 sprintf (buf, "[--sp] = ( r7:%d );\n", first_dreg_to_save);
2895 sprintf (buf, "[--sp] = ( r7:%d, p5:%d );\n",
2896 first_dreg_to_save, first_preg_to_save);
2898 output_asm_insn (buf, operands);
2901 /* Emit assembly code for one multi-register pop described by INSN, with
2902 operands in OPERANDS. */
2905 output_pop_multiple (rtx insn, rtx *operands)
2910 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2911 ok = pop_multiple_operation (PATTERN (insn), VOIDmode);
2914 if (first_dreg_to_save == 8)
2915 sprintf (buf, "( p5:%d ) = [sp++];\n", first_preg_to_save);
2916 else if (first_preg_to_save == 6)
2917 sprintf (buf, "( r7:%d ) = [sp++];\n", first_dreg_to_save);
2919 sprintf (buf, "( r7:%d, p5:%d ) = [sp++];\n",
2920 first_dreg_to_save, first_preg_to_save);
2922 output_asm_insn (buf, operands);
2925 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
2928 single_move_for_movmem (rtx dst, rtx src, enum machine_mode mode, HOST_WIDE_INT offset)
2930 rtx scratch = gen_reg_rtx (mode);
2933 srcmem = adjust_address_nv (src, mode, offset);
2934 dstmem = adjust_address_nv (dst, mode, offset);
2935 emit_move_insn (scratch, srcmem);
2936 emit_move_insn (dstmem, scratch);
2939 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
2940 alignment ALIGN_EXP. Return true if successful, false if we should fall
2941 back on a different method. */
2944 bfin_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
2946 rtx srcreg, destreg, countreg;
2947 HOST_WIDE_INT align = 0;
2948 unsigned HOST_WIDE_INT count = 0;
2950 if (GET_CODE (align_exp) == CONST_INT)
2951 align = INTVAL (align_exp);
2952 if (GET_CODE (count_exp) == CONST_INT)
2954 count = INTVAL (count_exp);
2956 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
2961 /* If optimizing for size, only do single copies inline. */
2964 if (count == 2 && align < 2)
2966 if (count == 4 && align < 4)
2968 if (count != 1 && count != 2 && count != 4)
2971 if (align < 2 && count != 1)
2974 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
2975 if (destreg != XEXP (dst, 0))
2976 dst = replace_equiv_address_nv (dst, destreg);
2977 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
2978 if (srcreg != XEXP (src, 0))
2979 src = replace_equiv_address_nv (src, srcreg);
2981 if (count != 0 && align >= 2)
2983 unsigned HOST_WIDE_INT offset = 0;
2987 if ((count & ~3) == 4)
2989 single_move_for_movmem (dst, src, SImode, offset);
2992 else if (count & ~3)
2994 HOST_WIDE_INT new_count = ((count >> 2) & 0x3fffffff) - 1;
2995 countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count));
2997 emit_insn (gen_rep_movsi (destreg, srcreg, countreg, destreg, srcreg));
3001 single_move_for_movmem (dst, src, HImode, offset);
3007 if ((count & ~1) == 2)
3009 single_move_for_movmem (dst, src, HImode, offset);
3012 else if (count & ~1)
3014 HOST_WIDE_INT new_count = ((count >> 1) & 0x7fffffff) - 1;
3015 countreg = copy_to_mode_reg (Pmode, GEN_INT (new_count));
3017 emit_insn (gen_rep_movhi (destreg, srcreg, countreg, destreg, srcreg));
3022 single_move_for_movmem (dst, src, QImode, offset);
3029 /* Compute the alignment for a local variable.
3030 TYPE is the data type, and ALIGN is the alignment that
3031 the object would ordinarily have. The value of this macro is used
3032 instead of that alignment to align the object. */
3035 bfin_local_alignment (tree type, int align)
3037 /* Increasing alignment for (relatively) big types allows the builtin
3038 memcpy can use 32 bit loads/stores. */
3039 if (TYPE_SIZE (type)
3040 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3041 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) > 8
3042 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 32)
3047 /* Implement TARGET_SCHED_ISSUE_RATE. */
3050 bfin_issue_rate (void)
3056 bfin_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3058 enum attr_type insn_type, dep_insn_type;
3059 int dep_insn_code_number;
3061 /* Anti and output dependencies have zero cost. */
3062 if (REG_NOTE_KIND (link) != 0)
3065 dep_insn_code_number = recog_memoized (dep_insn);
3067 /* If we can't recognize the insns, we can't really do anything. */
3068 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
3071 insn_type = get_attr_type (insn);
3072 dep_insn_type = get_attr_type (dep_insn);
3074 if (dep_insn_type == TYPE_MOVE || dep_insn_type == TYPE_MCLD)
3076 rtx pat = PATTERN (dep_insn);
3077 rtx dest = SET_DEST (pat);
3078 rtx src = SET_SRC (pat);
3079 if (! ADDRESS_REGNO_P (REGNO (dest))
3080 || ! (MEM_P (src) || D_REGNO_P (REGNO (src))))
3082 return cost + (dep_insn_type == TYPE_MOVE ? 4 : 3);
3089 /* Increment the counter for the number of loop instructions in the
3090 current function. */
3093 bfin_hardware_loop (void)
3095 cfun->machine->has_hardware_loops++;
3098 /* Maximum loop nesting depth. */
3099 #define MAX_LOOP_DEPTH 2
3101 /* Maximum size of a loop. */
3102 #define MAX_LOOP_LENGTH 2042
3104 /* Maximum distance of the LSETUP instruction from the loop start. */
3105 #define MAX_LSETUP_DISTANCE 30
3107 /* We need to keep a vector of loops */
3108 typedef struct loop_info *loop_info;
3109 DEF_VEC_P (loop_info);
3110 DEF_VEC_ALLOC_P (loop_info,heap);
3112 /* Information about a loop we have found (or are in the process of
3114 struct loop_info GTY (())
3116 /* loop number, for dumps */
3119 /* All edges that jump into and out of the loop. */
3120 VEC(edge,gc) *incoming;
3122 /* We can handle two cases: all incoming edges have the same destination
3123 block, or all incoming edges have the same source block. These two
3124 members are set to the common source or destination we found, or NULL
3125 if different blocks were found. If both are NULL the loop can't be
3127 basic_block incoming_src;
3128 basic_block incoming_dest;
3130 /* First block in the loop. This is the one branched to by the loop_end
3134 /* Last block in the loop (the one with the loop_end insn). */
3137 /* The successor block of the loop. This is the one the loop_end insn
3139 basic_block successor;
3141 /* The last instruction in the tail. */
3144 /* The loop_end insn. */
3147 /* The iteration register. */
3150 /* The new initialization insn. */
3153 /* The new initialization instruction. */
3156 /* The new label placed at the beginning of the loop. */
3159 /* The new label placed at the end of the loop. */
3162 /* The length of the loop. */
3165 /* The nesting depth of the loop. */
3168 /* Nonzero if we can't optimize this loop. */
3171 /* True if we have visited this loop. */
3174 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3177 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3180 /* Next loop in the graph. */
3181 struct loop_info *next;
3183 /* Immediate outer loop of this loop. */
3184 struct loop_info *outer;
3186 /* Vector of blocks only within the loop, including those within
3188 VEC (basic_block,heap) *blocks;
3190 /* Same information in a bitmap. */
3191 bitmap block_bitmap;
3193 /* Vector of inner loops within this loop */
3194 VEC (loop_info,heap) *loops;
3198 bfin_dump_loops (loop_info loops)
3202 for (loop = loops; loop; loop = loop->next)
3208 fprintf (dump_file, ";; loop %d: ", loop->loop_no);
3210 fprintf (dump_file, "(bad) ");
3211 fprintf (dump_file, "{head:%d, depth:%d}", loop->head->index, loop->depth);
3213 fprintf (dump_file, " blocks: [ ");
3214 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, b); ix++)
3215 fprintf (dump_file, "%d ", b->index);
3216 fprintf (dump_file, "] ");
3218 fprintf (dump_file, " inner loops: [ ");
3219 for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, i); ix++)
3220 fprintf (dump_file, "%d ", i->loop_no);
3221 fprintf (dump_file, "]\n");
3223 fprintf (dump_file, "\n");
3226 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3227 BB. Return true, if we find it. */
3230 bfin_bb_in_loop (loop_info loop, basic_block bb)
3232 return bitmap_bit_p (loop->block_bitmap, bb->index);
3235 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3236 REG. Return true, if we find any. Don't count the loop's loop_end
3237 insn if it matches LOOP_END. */
3240 bfin_scan_loop (loop_info loop, rtx reg, rtx loop_end)
3245 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++)
3249 for (insn = BB_HEAD (bb);
3250 insn != NEXT_INSN (BB_END (bb));
3251 insn = NEXT_INSN (insn))
3255 if (insn == loop_end)
3257 if (reg_mentioned_p (reg, PATTERN (insn)))
3264 /* Estimate the length of INSN conservatively. */
3267 length_for_loop (rtx insn)
3270 if (JUMP_P (insn) && any_condjump_p (insn) && !optimize_size)
3272 if (TARGET_CSYNC_ANOMALY)
3274 else if (TARGET_SPECLD_ANOMALY)
3277 else if (LABEL_P (insn))
3279 if (TARGET_CSYNC_ANOMALY)
3284 length += get_attr_length (insn);
3289 /* Optimize LOOP. */
3292 bfin_optimize_loop (loop_info loop)
3296 rtx insn, init_insn, last_insn, nop_insn;
3297 rtx loop_init, start_label, end_label;
3298 rtx reg_lc0, reg_lc1, reg_lt0, reg_lt1, reg_lb0, reg_lb1;
3300 rtx lc_reg, lt_reg, lb_reg;
3304 int inner_depth = 0;
3314 fprintf (dump_file, ";; loop %d bad when found\n", loop->loop_no);
3318 /* Every loop contains in its list of inner loops every loop nested inside
3319 it, even if there are intermediate loops. This works because we're doing
3320 a depth-first search here and never visit a loop more than once. */
3321 for (ix = 0; VEC_iterate (loop_info, loop->loops, ix, inner); ix++)
3323 bfin_optimize_loop (inner);
3325 if (!inner->bad && inner_depth < inner->depth)
3327 inner_depth = inner->depth;
3329 loop->clobber_loop0 |= inner->clobber_loop0;
3330 loop->clobber_loop1 |= inner->clobber_loop1;
3334 loop->depth = inner_depth + 1;
3335 if (loop->depth > MAX_LOOP_DEPTH)
3338 fprintf (dump_file, ";; loop %d too deep\n", loop->loop_no);
3342 /* Get the loop iteration register. */
3343 iter_reg = loop->iter_reg;
3345 if (!DPREG_P (iter_reg))
3348 fprintf (dump_file, ";; loop %d iteration count NOT in PREG or DREG\n",
3353 if (loop->incoming_src)
3355 /* Make sure the predecessor is before the loop start label, as required by
3356 the LSETUP instruction. */
3358 for (insn = BB_END (loop->incoming_src);
3359 insn && insn != loop->start_label;
3360 insn = NEXT_INSN (insn))
3361 length += length_for_loop (insn);
3366 fprintf (dump_file, ";; loop %d lsetup not before loop_start\n",
3371 if (length > MAX_LSETUP_DISTANCE)
3374 fprintf (dump_file, ";; loop %d lsetup too far away\n", loop->loop_no);
3379 /* Check if start_label appears before loop_end and calculate the
3380 offset between them. We calculate the length of instructions
3383 for (insn = loop->start_label;
3384 insn && insn != loop->loop_end;
3385 insn = NEXT_INSN (insn))
3386 length += length_for_loop (insn);
3391 fprintf (dump_file, ";; loop %d start_label not before loop_end\n",
3396 loop->length = length;
3397 if (loop->length > MAX_LOOP_LENGTH)
3400 fprintf (dump_file, ";; loop %d too long\n", loop->loop_no);
3404 /* Scan all the blocks to make sure they don't use iter_reg. */
3405 if (bfin_scan_loop (loop, iter_reg, loop->loop_end))
3408 fprintf (dump_file, ";; loop %d uses iterator\n", loop->loop_no);
3412 /* Scan all the insns to see if the loop body clobber
3413 any hardware loop registers. */
3415 reg_lc0 = gen_rtx_REG (SImode, REG_LC0);
3416 reg_lc1 = gen_rtx_REG (SImode, REG_LC1);
3417 reg_lt0 = gen_rtx_REG (SImode, REG_LT0);
3418 reg_lt1 = gen_rtx_REG (SImode, REG_LT1);
3419 reg_lb0 = gen_rtx_REG (SImode, REG_LB0);
3420 reg_lb1 = gen_rtx_REG (SImode, REG_LB1);
3422 for (ix = 0; VEC_iterate (basic_block, loop->blocks, ix, bb); ix++)
3426 for (insn = BB_HEAD (bb);
3427 insn != NEXT_INSN (BB_END (bb));
3428 insn = NEXT_INSN (insn))
3433 if (reg_set_p (reg_lc0, insn)
3434 || reg_set_p (reg_lt0, insn)
3435 || reg_set_p (reg_lb0, insn))
3436 loop->clobber_loop0 = 1;
3438 if (reg_set_p (reg_lc1, insn)
3439 || reg_set_p (reg_lt1, insn)
3440 || reg_set_p (reg_lb1, insn))
3441 loop->clobber_loop1 |= 1;
3445 if ((loop->clobber_loop0 && loop->clobber_loop1)
3446 || (loop->depth == MAX_LOOP_DEPTH && loop->clobber_loop0))
3448 loop->depth = MAX_LOOP_DEPTH + 1;
3450 fprintf (dump_file, ";; loop %d no loop reg available\n",
3455 /* There should be an instruction before the loop_end instruction
3456 in the same basic block. And the instruction must not be
3458 - CONDITIONAL BRANCH
3462 - Returns (RTS, RTN, etc.) */
3465 last_insn = PREV_INSN (loop->loop_end);
3469 for (; last_insn != PREV_INSN (BB_HEAD (bb));
3470 last_insn = PREV_INSN (last_insn))
3471 if (INSN_P (last_insn))
3474 if (last_insn != PREV_INSN (BB_HEAD (bb)))
3477 if (single_pred_p (bb)
3478 && single_pred (bb) != ENTRY_BLOCK_PTR)
3480 bb = single_pred (bb);
3481 last_insn = BB_END (bb);
3486 last_insn = NULL_RTX;
3494 fprintf (dump_file, ";; loop %d has no last instruction\n",
3499 if (JUMP_P (last_insn))
3501 loop_info inner = bb->aux;
3503 && inner->outer == loop
3504 && inner->loop_end == last_insn
3505 && inner->depth == 1)
3506 /* This jump_insn is the exact loop_end of an inner loop
3507 and to be optimized away. So use the inner's last_insn. */
3508 last_insn = inner->last_insn;
3512 fprintf (dump_file, ";; loop %d has bad last instruction\n",
3517 else if (CALL_P (last_insn)
3518 || (GET_CODE (PATTERN (last_insn)) != SEQUENCE
3519 && get_attr_type (last_insn) == TYPE_SYNC)
3520 || recog_memoized (last_insn) == CODE_FOR_return_internal)
3523 fprintf (dump_file, ";; loop %d has bad last instruction\n",
3528 if (GET_CODE (PATTERN (last_insn)) == ASM_INPUT
3529 || asm_noperands (PATTERN (last_insn)) >= 0
3530 || (GET_CODE (PATTERN (last_insn)) != SEQUENCE
3531 && get_attr_seq_insns (last_insn) == SEQ_INSNS_MULTI))
3533 nop_insn = emit_insn_after (gen_nop (), last_insn);
3534 last_insn = nop_insn;
3537 loop->last_insn = last_insn;
3539 /* The loop is good for replacement. */
3540 start_label = loop->start_label;
3541 end_label = gen_label_rtx ();
3542 iter_reg = loop->iter_reg;
3544 if (loop->depth == 1 && !loop->clobber_loop1)
3549 loop->clobber_loop1 = 1;
3556 loop->clobber_loop0 = 1;
3559 /* If iter_reg is a DREG, we need generate an instruction to load
3560 the loop count into LC register. */
3561 if (D_REGNO_P (REGNO (iter_reg)))
3563 init_insn = gen_movsi (lc_reg, iter_reg);
3564 loop_init = gen_lsetup_without_autoinit (lt_reg, start_label,
3568 else if (P_REGNO_P (REGNO (iter_reg)))
3570 init_insn = NULL_RTX;
3571 loop_init = gen_lsetup_with_autoinit (lt_reg, start_label,
3578 loop->init = init_insn;
3579 loop->end_label = end_label;
3580 loop->loop_init = loop_init;
3584 fprintf (dump_file, ";; replacing loop %d initializer with\n",
3586 print_rtl_single (dump_file, loop->loop_init);
3587 fprintf (dump_file, ";; replacing loop %d terminator with\n",
3589 print_rtl_single (dump_file, loop->loop_end);
3594 if (loop->init != NULL_RTX)
3595 emit_insn (loop->init);
3596 seq_end = emit_insn (loop->loop_init);
3601 if (loop->incoming_src)
3603 rtx prev = BB_END (loop->incoming_src);
3604 if (VEC_length (edge, loop->incoming) > 1
3605 || !(VEC_last (edge, loop->incoming)->flags & EDGE_FALLTHRU))
3607 gcc_assert (JUMP_P (prev));
3608 prev = PREV_INSN (prev);
3610 emit_insn_after (seq, prev);
3618 if (loop->head != loop->incoming_dest)
3620 FOR_EACH_EDGE (e, ei, loop->head->preds)
3622 if (e->flags & EDGE_FALLTHRU)
3624 rtx newjump = gen_jump (loop->start_label);
3625 emit_insn_before (newjump, BB_HEAD (loop->head));
3626 new_bb = create_basic_block (newjump, newjump, loop->head->prev_bb);
3627 gcc_assert (new_bb = loop->head->prev_bb);
3633 emit_insn_before (seq, BB_HEAD (loop->head));
3634 seq = emit_label_before (gen_label_rtx (), seq);
3636 new_bb = create_basic_block (seq, seq_end, loop->head->prev_bb);
3637 FOR_EACH_EDGE (e, ei, loop->incoming)
3639 if (!(e->flags & EDGE_FALLTHRU)
3640 || e->dest != loop->head)
3641 redirect_edge_and_branch_force (e, new_bb);
3643 redirect_edge_succ (e, new_bb);
3647 delete_insn (loop->loop_end);
3648 /* Insert the loop end label before the last instruction of the loop. */
3649 emit_label_before (loop->end_label, loop->last_insn);
3656 fprintf (dump_file, ";; loop %d is bad\n", loop->loop_no);
3660 if (DPREG_P (loop->iter_reg))
3662 /* If loop->iter_reg is a DREG or PREG, we can split it here
3663 without scratch register. */
3666 emit_insn_before (gen_addsi3 (loop->iter_reg,
3671 emit_insn_before (gen_cmpsi (loop->iter_reg, const0_rtx),
3674 insn = emit_jump_insn_before (gen_bne (loop->start_label),
3677 JUMP_LABEL (insn) = loop->start_label;
3678 LABEL_NUSES (loop->start_label)++;
3679 delete_insn (loop->loop_end);
3683 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
3684 a newly set up structure describing the loop, it is this function's
3685 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
3686 loop_end insn and its enclosing basic block. */
3689 bfin_discover_loop (loop_info loop, basic_block tail_bb, rtx tail_insn)
3693 VEC (basic_block,heap) *works = VEC_alloc (basic_block,heap,20);
3695 loop->tail = tail_bb;
3696 loop->head = BRANCH_EDGE (tail_bb)->dest;
3697 loop->successor = FALLTHRU_EDGE (tail_bb)->dest;
3698 loop->loop_end = tail_insn;
3699 loop->last_insn = NULL_RTX;
3700 loop->iter_reg = SET_DEST (XVECEXP (PATTERN (tail_insn), 0, 1));
3701 loop->depth = loop->length = 0;
3703 loop->clobber_loop0 = loop->clobber_loop1 = 0;
3706 loop->incoming = VEC_alloc (edge, gc, 2);
3707 loop->init = loop->loop_init = NULL_RTX;
3708 loop->start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn), 0, 0)), 1), 0);
3709 loop->end_label = NULL_RTX;
3712 VEC_safe_push (basic_block, heap, works, loop->head);
3714 while (VEC_iterate (basic_block, works, dwork++, bb))
3718 if (bb == EXIT_BLOCK_PTR)
3720 /* We've reached the exit block. The loop must be bad. */
3723 ";; Loop is bad - reached exit block while scanning\n");
3728 if (bitmap_bit_p (loop->block_bitmap, bb->index))
3731 /* We've not seen this block before. Add it to the loop's
3732 list and then add each successor to the work list. */
3734 VEC_safe_push (basic_block, heap, loop->blocks, bb);
3735 bitmap_set_bit (loop->block_bitmap, bb->index);
3739 FOR_EACH_EDGE (e, ei, bb->succs)
3741 basic_block succ = EDGE_SUCC (bb, ei.index)->dest;
3742 if (!REGNO_REG_SET_P (df_get_live_in (succ),
3743 REGNO (loop->iter_reg)))
3745 if (!VEC_space (basic_block, works, 1))
3749 VEC_block_remove (basic_block, works, 0, dwork);
3753 VEC_reserve (basic_block, heap, works, 1);
3755 VEC_quick_push (basic_block, works, succ);
3760 /* Find the predecessor, and make sure nothing else jumps into this loop. */
3764 for (dwork = 0; VEC_iterate (basic_block, loop->blocks, dwork, bb); dwork++)
3768 FOR_EACH_EDGE (e, ei, bb->preds)
3770 basic_block pred = e->src;
3772 if (!bfin_bb_in_loop (loop, pred))
3775 fprintf (dump_file, ";; Loop %d: incoming edge %d -> %d\n",
3776 loop->loop_no, pred->index,
3778 VEC_safe_push (edge, gc, loop->incoming, e);
3783 for (pass = 0, retry = 1; retry && pass < 2; pass++)
3790 FOR_EACH_EDGE (e, ei, loop->incoming)
3794 loop->incoming_src = e->src;
3795 loop->incoming_dest = e->dest;
3800 if (e->dest != loop->incoming_dest)
3801 loop->incoming_dest = NULL;
3802 if (e->src != loop->incoming_src)
3803 loop->incoming_src = NULL;
3805 if (loop->incoming_src == NULL && loop->incoming_dest == NULL)
3811 ";; retrying loop %d with forwarder blocks\n",
3819 ";; can't find suitable entry for loop %d\n",
3827 FOR_EACH_EDGE (e, ei, loop->incoming)
3829 if (forwarder_block_p (e->src))
3836 ";; Adding forwarder block %d to loop %d and retrying\n",
3837 e->src->index, loop->loop_no);
3838 VEC_safe_push (basic_block, heap, loop->blocks, e->src);
3839 bitmap_set_bit (loop->block_bitmap, e->src->index);
3840 FOR_EACH_EDGE (e2, ei2, e->src->preds)
3841 VEC_safe_push (edge, gc, loop->incoming, e2);
3842 VEC_unordered_remove (edge, loop->incoming, ei.index);
3852 VEC_free (basic_block, heap, works);
3855 /* Analyze the structure of the loops in the current function. Use STACK
3856 for bitmap allocations. Returns all the valid candidates for hardware
3857 loops found in this function. */
3859 bfin_discover_loops (bitmap_obstack *stack, FILE *dump_file)
3861 loop_info loops = NULL;
3867 /* Find all the possible loop tails. This means searching for every
3868 loop_end instruction. For each one found, create a loop_info
3869 structure and add the head block to the work list. */
3872 rtx tail = BB_END (bb);
3874 while (GET_CODE (tail) == NOTE)
3875 tail = PREV_INSN (tail);
3879 if (INSN_P (tail) && recog_memoized (tail) == CODE_FOR_loop_end)
3881 /* A possible loop end */
3883 loop = XNEW (struct loop_info);
3886 loop->loop_no = nloops++;
3887 loop->blocks = VEC_alloc (basic_block, heap, 20);
3888 loop->block_bitmap = BITMAP_ALLOC (stack);
3893 fprintf (dump_file, ";; potential loop %d ending at\n",
3895 print_rtl_single (dump_file, tail);
3898 bfin_discover_loop (loop, bb, tail);
3902 tmp_bitmap = BITMAP_ALLOC (stack);
3903 /* Compute loop nestings. */
3904 for (loop = loops; loop; loop = loop->next)
3910 for (other = loop->next; other; other = other->next)
3915 bitmap_and (tmp_bitmap, other->block_bitmap, loop->block_bitmap);
3916 if (bitmap_empty_p (tmp_bitmap))
3918 if (bitmap_equal_p (tmp_bitmap, other->block_bitmap))
3920 other->outer = loop;
3921 VEC_safe_push (loop_info, heap, loop->loops, other);
3923 else if (bitmap_equal_p (tmp_bitmap, loop->block_bitmap))
3925 loop->outer = other;
3926 VEC_safe_push (loop_info, heap, other->loops, loop);
3932 ";; can't find suitable nesting for loops %d and %d\n",
3933 loop->loop_no, other->loop_no);
3934 loop->bad = other->bad = 1;
3938 BITMAP_FREE (tmp_bitmap);
3943 /* Free up the loop structures in LOOPS. */
3945 free_loops (loop_info loops)
3949 loop_info loop = loops;
3951 VEC_free (loop_info, heap, loop->loops);
3952 VEC_free (basic_block, heap, loop->blocks);
3953 BITMAP_FREE (loop->block_bitmap);
3958 #define BB_AUX_INDEX(BB) ((unsigned)(BB)->aux)
3960 /* The taken-branch edge from the loop end can actually go forward. Since the
3961 Blackfin's LSETUP instruction requires that the loop end be after the loop
3962 start, try to reorder a loop's basic blocks when we find such a case. */
3964 bfin_reorder_loops (loop_info loops, FILE *dump_file)
3971 cfg_layout_initialize (0);
3973 for (loop = loops; loop; loop = loop->next)
3983 /* Recreate an index for basic blocks that represents their order. */
3984 for (bb = ENTRY_BLOCK_PTR->next_bb, index = 0;
3985 bb != EXIT_BLOCK_PTR;
3986 bb = bb->next_bb, index++)
3987 bb->aux = (PTR) index;
3989 if (BB_AUX_INDEX (loop->head) < BB_AUX_INDEX (loop->tail))
3992 FOR_EACH_EDGE (e, ei, loop->head->succs)
3994 if (bitmap_bit_p (loop->block_bitmap, e->dest->index)
3995 && BB_AUX_INDEX (e->dest) < BB_AUX_INDEX (loop->tail))
3997 basic_block start_bb = e->dest;
3998 basic_block start_prev_bb = start_bb->prev_bb;
4001 fprintf (dump_file, ";; Moving block %d before block %d\n",
4002 loop->head->index, start_bb->index);
4003 loop->head->prev_bb->next_bb = loop->head->next_bb;
4004 loop->head->next_bb->prev_bb = loop->head->prev_bb;
4006 loop->head->prev_bb = start_prev_bb;
4007 loop->head->next_bb = start_bb;
4008 start_prev_bb->next_bb = start_bb->prev_bb = loop->head;
4012 loops = loops->next;
4017 if (bb->next_bb != EXIT_BLOCK_PTR)
4018 bb->aux = bb->next_bb;
4022 cfg_layout_finalize ();
4026 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4027 and tries to rewrite the RTL of these loops so that proper Blackfin
4028 hardware loops are generated. */
4031 bfin_reorg_loops (FILE *dump_file)
4033 loop_info loops = NULL;
4036 bitmap_obstack stack;
4038 bitmap_obstack_initialize (&stack);
4041 fprintf (dump_file, ";; Find loops, first pass\n\n");
4043 loops = bfin_discover_loops (&stack, dump_file);
4046 bfin_dump_loops (loops);
4048 bfin_reorder_loops (loops, dump_file);
4052 fprintf (dump_file, ";; Find loops, second pass\n\n");
4054 loops = bfin_discover_loops (&stack, dump_file);
4057 fprintf (dump_file, ";; All loops found:\n\n");
4058 bfin_dump_loops (loops);
4061 /* Now apply the optimizations. */
4062 for (loop = loops; loop; loop = loop->next)
4063 bfin_optimize_loop (loop);
4067 fprintf (dump_file, ";; After hardware loops optimization:\n\n");
4068 bfin_dump_loops (loops);
4074 print_rtl (dump_file, get_insns ());
4080 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
4081 Returns true if we modified the insn chain, false otherwise. */
4083 gen_one_bundle (rtx slot[3])
4085 gcc_assert (slot[1] != NULL_RTX);
4087 /* Verify that we really can do the multi-issue. */
4090 rtx t = NEXT_INSN (slot[0]);
4091 while (t != slot[1])
4093 if (GET_CODE (t) != NOTE
4094 || NOTE_KIND (t) != NOTE_INSN_DELETED)
4101 rtx t = NEXT_INSN (slot[1]);
4102 while (t != slot[2])
4104 if (GET_CODE (t) != NOTE
4105 || NOTE_KIND (t) != NOTE_INSN_DELETED)
4111 if (slot[0] == NULL_RTX)
4113 slot[0] = emit_insn_before (gen_mnop (), slot[1]);
4114 df_insn_rescan (slot[0]);
4116 if (slot[2] == NULL_RTX)
4118 slot[2] = emit_insn_after (gen_forced_nop (), slot[1]);
4119 df_insn_rescan (slot[2]);
4122 /* Avoid line number information being printed inside one bundle. */
4123 if (INSN_LOCATOR (slot[1])
4124 && INSN_LOCATOR (slot[1]) != INSN_LOCATOR (slot[0]))
4125 INSN_LOCATOR (slot[1]) = INSN_LOCATOR (slot[0]);
4126 if (INSN_LOCATOR (slot[2])
4127 && INSN_LOCATOR (slot[2]) != INSN_LOCATOR (slot[0]))
4128 INSN_LOCATOR (slot[2]) = INSN_LOCATOR (slot[0]);
4130 /* Terminate them with "|| " instead of ";" in the output. */
4131 PUT_MODE (slot[0], SImode);
4132 PUT_MODE (slot[1], SImode);
4133 /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */
4134 PUT_MODE (slot[2], QImode);
4138 /* Go through all insns, and use the information generated during scheduling
4139 to generate SEQUENCEs to represent bundles of instructions issued
4143 bfin_gen_bundles (void)
4152 slot[0] = slot[1] = slot[2] = NULL_RTX;
4153 for (insn = BB_HEAD (bb);; insn = next)
4158 if (get_attr_type (insn) == TYPE_DSP32)
4160 else if (slot[1] == NULL_RTX)
4167 next = NEXT_INSN (insn);
4168 while (next && insn != BB_END (bb)
4170 && GET_CODE (PATTERN (next)) != USE
4171 && GET_CODE (PATTERN (next)) != CLOBBER))
4174 next = NEXT_INSN (insn);
4177 /* BB_END can change due to emitting extra NOPs, so check here. */
4178 at_end = insn == BB_END (bb);
4179 if (at_end || GET_MODE (next) == TImode)
4182 || !gen_one_bundle (slot))
4183 && slot[0] != NULL_RTX)
4185 rtx pat = PATTERN (slot[0]);
4186 if (GET_CODE (pat) == SET
4187 && GET_CODE (SET_SRC (pat)) == UNSPEC
4188 && XINT (SET_SRC (pat), 1) == UNSPEC_32BIT)
4190 SET_SRC (pat) = XVECEXP (SET_SRC (pat), 0, 0);
4191 INSN_CODE (slot[0]) = -1;
4192 df_insn_rescan (slot[0]);
4196 slot[0] = slot[1] = slot[2] = NULL_RTX;
4204 /* Ensure that no var tracking notes are emitted in the middle of a
4205 three-instruction bundle. */
4208 reorder_var_tracking_notes (void)
4214 rtx queue = NULL_RTX;
4215 bool in_bundle = false;
4217 for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
4219 next = NEXT_INSN (insn);
4223 /* Emit queued up notes at the last instruction of a bundle. */
4224 if (GET_MODE (insn) == QImode)
4228 rtx next_queue = PREV_INSN (queue);
4229 PREV_INSN (NEXT_INSN (insn)) = queue;
4230 NEXT_INSN (queue) = NEXT_INSN (insn);
4231 NEXT_INSN (insn) = queue;
4232 PREV_INSN (queue) = insn;
4237 else if (GET_MODE (insn) == SImode)
4240 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
4244 rtx prev = PREV_INSN (insn);
4245 PREV_INSN (next) = prev;
4246 NEXT_INSN (prev) = next;
4248 PREV_INSN (insn) = queue;
4256 /* Return an insn type for INSN that can be used by the caller for anomaly
4257 workarounds. This differs from plain get_attr_type in that it handles
4260 static enum attr_type
4261 type_for_anomaly (rtx insn)
4263 rtx pat = PATTERN (insn);
4264 if (GET_CODE (pat) == SEQUENCE)
4267 t = get_attr_type (XVECEXP (pat, 0, 1));
4270 t = get_attr_type (XVECEXP (pat, 0, 2));
4276 return get_attr_type (insn);
4279 /* Return nonzero if INSN contains any loads that may trap. It handles
4280 SEQUENCEs correctly. */
4283 trapping_loads_p (rtx insn)
4285 rtx pat = PATTERN (insn);
4286 if (GET_CODE (pat) == SEQUENCE)
4289 t = get_attr_type (XVECEXP (pat, 0, 1));
4291 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 1)))))
4293 t = get_attr_type (XVECEXP (pat, 0, 2));
4295 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 2)))))
4300 return may_trap_p (SET_SRC (single_set (insn)));
4303 /* This function acts like NEXT_INSN, but is aware of three-insn bundles and
4304 skips all subsequent parallel instructions if INSN is the start of such
4307 find_next_insn_start (rtx insn)
4309 if (GET_MODE (insn) == SImode)
4311 while (GET_MODE (insn) != QImode)
4312 insn = NEXT_INSN (insn);
4314 return NEXT_INSN (insn);
4317 /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of
4318 a three-insn bundle, see if one of them is a load and return that if so.
4319 Return NULL_RTX if the insn does not contain loads. */
4321 find_load (rtx insn)
4323 if (get_attr_type (insn) == TYPE_MCLD)
4325 if (GET_MODE (insn) != SImode)
4328 insn = NEXT_INSN (insn);
4329 if ((GET_MODE (insn) == SImode || GET_MODE (insn) == QImode)
4330 && get_attr_type (insn) == TYPE_MCLD)
4332 } while (GET_MODE (insn) != QImode);
4336 /* We use the machine specific reorg pass for emitting CSYNC instructions
4337 after conditional branches as needed.
4339 The Blackfin is unusual in that a code sequence like
4342 may speculatively perform the load even if the condition isn't true. This
4343 happens for a branch that is predicted not taken, because the pipeline
4344 isn't flushed or stalled, so the early stages of the following instructions,
4345 which perform the memory reference, are allowed to execute before the
4346 jump condition is evaluated.
4347 Therefore, we must insert additional instructions in all places where this
4348 could lead to incorrect behavior. The manual recommends CSYNC, while
4349 VDSP seems to use NOPs (even though its corresponding compiler option is
4352 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
4353 When optimizing for size, we turn the branch into a predicted taken one.
4354 This may be slower due to mispredicts, but saves code size. */
4360 rtx last_condjump = NULL_RTX;
4361 int cycles_since_jump = INT_MAX;
4363 /* We are freeing block_for_insn in the toplev to keep compatibility
4364 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4365 compute_bb_for_insn ();
4367 if (bfin_flag_schedule_insns2)
4369 splitting_for_sched = 1;
4371 splitting_for_sched = 0;
4373 timevar_push (TV_SCHED2);
4375 timevar_pop (TV_SCHED2);
4377 /* Examine the schedule and insert nops as necessary for 64-bit parallel
4379 bfin_gen_bundles ();
4384 /* Doloop optimization */
4385 if (cfun->machine->has_hardware_loops)
4386 bfin_reorg_loops (dump_file);
4388 if (! TARGET_SPECLD_ANOMALY && ! TARGET_CSYNC_ANOMALY)
4391 /* First pass: find predicted-false branches; if something after them
4392 needs nops, insert them or change the branch to predict true. */
4393 for (insn = get_insns (); insn; insn = next)
4397 next = find_next_insn_start (insn);
4399 if (NOTE_P (insn) || BARRIER_P (insn) || LABEL_P (insn))
4402 pat = PATTERN (insn);
4403 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
4404 || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC
4405 || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0)
4410 if (any_condjump_p (insn)
4411 && ! cbranch_predicted_taken_p (insn))
4413 last_condjump = insn;
4414 cycles_since_jump = 0;
4417 cycles_since_jump = INT_MAX;
4419 else if (INSN_P (insn))
4421 rtx load_insn = find_load (insn);
4422 enum attr_type type = type_for_anomaly (insn);
4423 int delay_needed = 0;
4424 if (cycles_since_jump < INT_MAX)
4425 cycles_since_jump++;
4427 if (load_insn && TARGET_SPECLD_ANOMALY)
4429 if (trapping_loads_p (load_insn))
4432 else if (type == TYPE_SYNC && TARGET_CSYNC_ANOMALY)
4435 if (delay_needed > cycles_since_jump)
4439 rtx *op = recog_data.operand;
4441 delay_needed -= cycles_since_jump;
4443 extract_insn (last_condjump);
4446 pat = gen_cbranch_predicted_taken (op[0], op[1], op[2],
4448 cycles_since_jump = INT_MAX;
4451 /* Do not adjust cycles_since_jump in this case, so that
4452 we'll increase the number of NOPs for a subsequent insn
4454 pat = gen_cbranch_with_nops (op[0], op[1], op[2], op[3],
4455 GEN_INT (delay_needed));
4456 PATTERN (last_condjump) = pat;
4457 INSN_CODE (last_condjump) = recog (pat, insn, &num_clobbers);
4461 /* Second pass: for predicted-true branches, see if anything at the
4462 branch destination needs extra nops. */
4463 if (! TARGET_CSYNC_ANOMALY)
4466 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4469 && any_condjump_p (insn)
4470 && (INSN_CODE (insn) == CODE_FOR_cbranch_predicted_taken
4471 || cbranch_predicted_taken_p (insn)))
4473 rtx target = JUMP_LABEL (insn);
4475 cycles_since_jump = 0;
4476 for (; target && cycles_since_jump < 3; target = NEXT_INSN (target))
4480 if (NOTE_P (target) || BARRIER_P (target) || LABEL_P (target))
4483 pat = PATTERN (target);
4484 if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
4485 || GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ADDR_VEC
4486 || GET_CODE (pat) == ADDR_DIFF_VEC || asm_noperands (pat) >= 0)
4489 if (INSN_P (target))
4491 enum attr_type type = type_for_anomaly (target);
4492 int delay_needed = 0;
4493 if (cycles_since_jump < INT_MAX)
4494 cycles_since_jump++;
4496 if (type == TYPE_SYNC && TARGET_CSYNC_ANOMALY)
4499 if (delay_needed > cycles_since_jump)
4501 rtx prev = prev_real_insn (label);
4502 delay_needed -= cycles_since_jump;
4504 fprintf (dump_file, "Adding %d nops after %d\n",
4505 delay_needed, INSN_UID (label));
4507 && INSN_CODE (prev) == CODE_FOR_cbranch_with_nops)
4514 "Reducing nops on insn %d.\n",
4517 x = XVECEXP (x, 0, 1);
4518 v = INTVAL (XVECEXP (x, 0, 0)) - delay_needed;
4519 XVECEXP (x, 0, 0) = GEN_INT (v);
4521 while (delay_needed-- > 0)
4522 emit_insn_after (gen_nop (), label);
4530 if (bfin_flag_var_tracking)
4532 timevar_push (TV_VAR_TRACKING);
4533 variable_tracking_main ();
4534 reorder_var_tracking_notes ();
4535 timevar_pop (TV_VAR_TRACKING);
4540 /* Handle interrupt_handler, exception_handler and nmi_handler function
4541 attributes; arguments as in struct attribute_spec.handler. */
4544 handle_int_attribute (tree *node, tree name,
4545 tree args ATTRIBUTE_UNUSED,
4546 int flags ATTRIBUTE_UNUSED,
4550 if (TREE_CODE (x) == FUNCTION_DECL)
4553 if (TREE_CODE (x) != FUNCTION_TYPE)
4555 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4556 IDENTIFIER_POINTER (name));
4557 *no_add_attrs = true;
4559 else if (funkind (x) != SUBROUTINE)
4560 error ("multiple function type attributes specified");
4565 /* Return 0 if the attributes for two types are incompatible, 1 if they
4566 are compatible, and 2 if they are nearly compatible (which causes a
4567 warning to be generated). */
4570 bfin_comp_type_attributes (tree type1, tree type2)
4572 e_funkind kind1, kind2;
4574 if (TREE_CODE (type1) != FUNCTION_TYPE)
4577 kind1 = funkind (type1);
4578 kind2 = funkind (type2);
4583 /* Check for mismatched modifiers */
4584 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1))
4585 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2)))
4588 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1))
4589 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2)))
4592 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1))
4593 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2)))
4596 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1))
4597 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2)))
4603 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4604 struct attribute_spec.handler. */
4607 bfin_handle_longcall_attribute (tree *node, tree name,
4608 tree args ATTRIBUTE_UNUSED,
4609 int flags ATTRIBUTE_UNUSED,
4612 if (TREE_CODE (*node) != FUNCTION_TYPE
4613 && TREE_CODE (*node) != FIELD_DECL
4614 && TREE_CODE (*node) != TYPE_DECL)
4616 warning (OPT_Wattributes, "`%s' attribute only applies to functions",
4617 IDENTIFIER_POINTER (name));
4618 *no_add_attrs = true;
4621 if ((strcmp (IDENTIFIER_POINTER (name), "longcall") == 0
4622 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node)))
4623 || (strcmp (IDENTIFIER_POINTER (name), "shortcall") == 0
4624 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node))))
4626 warning (OPT_Wattributes,
4627 "can't apply both longcall and shortcall attributes to the same function");
4628 *no_add_attrs = true;
4634 /* Table of valid machine attributes. */
4635 const struct attribute_spec bfin_attribute_table[] =
4637 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4638 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute },
4639 { "exception_handler", 0, 0, false, true, true, handle_int_attribute },
4640 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute },
4641 { "nesting", 0, 0, false, true, true, NULL },
4642 { "kspisusp", 0, 0, false, true, true, NULL },
4643 { "saveall", 0, 0, false, true, true, NULL },
4644 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute },
4645 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute },
4646 { NULL, 0, 0, false, false, false, NULL }
4649 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
4650 tell the assembler to generate pointers to function descriptors in
4654 bfin_assemble_integer (rtx value, unsigned int size, int aligned_p)
4656 if (TARGET_FDPIC && size == UNITS_PER_WORD)
4658 if (GET_CODE (value) == SYMBOL_REF
4659 && SYMBOL_REF_FUNCTION_P (value))
4661 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
4662 output_addr_const (asm_out_file, value);
4663 fputs (")\n", asm_out_file);
4668 /* We've set the unaligned SI op to NULL, so we always have to
4669 handle the unaligned case here. */
4670 assemble_integer_with_op ("\t.4byte\t", value);
4674 return default_assemble_integer (value, size, aligned_p);
4677 /* Output the assembler code for a thunk function. THUNK_DECL is the
4678 declaration for the thunk function itself, FUNCTION is the decl for
4679 the target function. DELTA is an immediate constant offset to be
4680 added to THIS. If VCALL_OFFSET is nonzero, the word at
4681 *(*this + vcall_offset) should be added to THIS. */
4684 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
4685 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
4686 HOST_WIDE_INT vcall_offset, tree function)
4689 /* The this parameter is passed as the first argument. */
4690 rtx this = gen_rtx_REG (Pmode, REG_R0);
4692 /* Adjust the this parameter by a fixed constant. */
4696 if (delta >= -64 && delta <= 63)
4698 xops[0] = GEN_INT (delta);
4699 output_asm_insn ("%1 += %0;", xops);
4701 else if (delta >= -128 && delta < -64)
4703 xops[0] = GEN_INT (delta + 64);
4704 output_asm_insn ("%1 += -64; %1 += %0;", xops);
4706 else if (delta > 63 && delta <= 126)
4708 xops[0] = GEN_INT (delta - 63);
4709 output_asm_insn ("%1 += 63; %1 += %0;", xops);
4713 xops[0] = GEN_INT (delta);
4714 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops);
4718 /* Adjust the this parameter by a value stored in the vtable. */
4721 rtx p2tmp = gen_rtx_REG (Pmode, REG_P2);
4722 rtx tmp = gen_rtx_REG (Pmode, REG_R3);
4726 output_asm_insn ("%2 = r0; %2 = [%2];", xops);
4728 /* Adjust the this parameter. */
4729 xops[0] = gen_rtx_MEM (Pmode, plus_constant (p2tmp, vcall_offset));
4730 if (!memory_operand (xops[0], Pmode))
4732 rtx tmp2 = gen_rtx_REG (Pmode, REG_P1);
4733 xops[0] = GEN_INT (vcall_offset);
4735 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops);
4736 xops[0] = gen_rtx_MEM (Pmode, p2tmp);
4739 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops);
4742 xops[0] = XEXP (DECL_RTL (function), 0);
4743 if (1 || !flag_pic || (*targetm.binds_local_p) (function))
4744 output_asm_insn ("jump.l\t%P0", xops);
4747 /* Codes for all the Blackfin builtins. */
4752 BFIN_BUILTIN_COMPOSE_2X16,
4753 BFIN_BUILTIN_EXTRACTLO,
4754 BFIN_BUILTIN_EXTRACTHI,
4756 BFIN_BUILTIN_SSADD_2X16,
4757 BFIN_BUILTIN_SSSUB_2X16,
4758 BFIN_BUILTIN_SSADDSUB_2X16,
4759 BFIN_BUILTIN_SSSUBADD_2X16,
4760 BFIN_BUILTIN_MULT_2X16,
4761 BFIN_BUILTIN_MULTR_2X16,
4762 BFIN_BUILTIN_NEG_2X16,
4763 BFIN_BUILTIN_ABS_2X16,
4764 BFIN_BUILTIN_MIN_2X16,
4765 BFIN_BUILTIN_MAX_2X16,
4767 BFIN_BUILTIN_SSADD_1X16,
4768 BFIN_BUILTIN_SSSUB_1X16,
4769 BFIN_BUILTIN_MULT_1X16,
4770 BFIN_BUILTIN_MULTR_1X16,
4771 BFIN_BUILTIN_NORM_1X16,
4772 BFIN_BUILTIN_NEG_1X16,
4773 BFIN_BUILTIN_ABS_1X16,
4774 BFIN_BUILTIN_MIN_1X16,
4775 BFIN_BUILTIN_MAX_1X16,
4777 BFIN_BUILTIN_SUM_2X16,
4778 BFIN_BUILTIN_DIFFHL_2X16,
4779 BFIN_BUILTIN_DIFFLH_2X16,
4781 BFIN_BUILTIN_SSADD_1X32,
4782 BFIN_BUILTIN_SSSUB_1X32,
4783 BFIN_BUILTIN_NORM_1X32,
4784 BFIN_BUILTIN_ROUND_1X32,
4785 BFIN_BUILTIN_NEG_1X32,
4786 BFIN_BUILTIN_ABS_1X32,
4787 BFIN_BUILTIN_MIN_1X32,
4788 BFIN_BUILTIN_MAX_1X32,
4789 BFIN_BUILTIN_MULT_1X32,
4790 BFIN_BUILTIN_MULT_1X32X32,
4791 BFIN_BUILTIN_MULT_1X32X32NS,
4793 BFIN_BUILTIN_MULHISILL,
4794 BFIN_BUILTIN_MULHISILH,
4795 BFIN_BUILTIN_MULHISIHL,
4796 BFIN_BUILTIN_MULHISIHH,
4798 BFIN_BUILTIN_LSHIFT_1X16,
4799 BFIN_BUILTIN_LSHIFT_2X16,
4800 BFIN_BUILTIN_SSASHIFT_1X16,
4801 BFIN_BUILTIN_SSASHIFT_2X16,
4802 BFIN_BUILTIN_SSASHIFT_1X32,
4804 BFIN_BUILTIN_CPLX_MUL_16,
4805 BFIN_BUILTIN_CPLX_MAC_16,
4806 BFIN_BUILTIN_CPLX_MSU_16,
4811 #define def_builtin(NAME, TYPE, CODE) \
4813 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4817 /* Set up all builtin functions for this target. */
4819 bfin_init_builtins (void)
4821 tree V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
4822 tree void_ftype_void
4823 = build_function_type (void_type_node, void_list_node);
4824 tree short_ftype_short
4825 = build_function_type_list (short_integer_type_node, short_integer_type_node,
4827 tree short_ftype_int_int
4828 = build_function_type_list (short_integer_type_node, integer_type_node,
4829 integer_type_node, NULL_TREE);
4830 tree int_ftype_int_int
4831 = build_function_type_list (integer_type_node, integer_type_node,
4832 integer_type_node, NULL_TREE);
4834 = build_function_type_list (integer_type_node, integer_type_node,
4836 tree short_ftype_int
4837 = build_function_type_list (short_integer_type_node, integer_type_node,
4839 tree int_ftype_v2hi_v2hi
4840 = build_function_type_list (integer_type_node, V2HI_type_node,
4841 V2HI_type_node, NULL_TREE);
4842 tree v2hi_ftype_v2hi_v2hi
4843 = build_function_type_list (V2HI_type_node, V2HI_type_node,
4844 V2HI_type_node, NULL_TREE);
4845 tree v2hi_ftype_v2hi_v2hi_v2hi
4846 = build_function_type_list (V2HI_type_node, V2HI_type_node,
4847 V2HI_type_node, V2HI_type_node, NULL_TREE);
4848 tree v2hi_ftype_int_int
4849 = build_function_type_list (V2HI_type_node, integer_type_node,
4850 integer_type_node, NULL_TREE);
4851 tree v2hi_ftype_v2hi_int
4852 = build_function_type_list (V2HI_type_node, V2HI_type_node,
4853 integer_type_node, NULL_TREE);
4854 tree int_ftype_short_short
4855 = build_function_type_list (integer_type_node, short_integer_type_node,
4856 short_integer_type_node, NULL_TREE);
4857 tree v2hi_ftype_v2hi
4858 = build_function_type_list (V2HI_type_node, V2HI_type_node, NULL_TREE);
4859 tree short_ftype_v2hi
4860 = build_function_type_list (short_integer_type_node, V2HI_type_node,
4863 /* Add the remaining MMX insns with somewhat more complicated types. */
4864 def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC);
4865 def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC);
4867 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int,
4868 BFIN_BUILTIN_COMPOSE_2X16);
4869 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi,
4870 BFIN_BUILTIN_EXTRACTHI);
4871 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi,
4872 BFIN_BUILTIN_EXTRACTLO);
4874 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi,
4875 BFIN_BUILTIN_MIN_2X16);
4876 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi,
4877 BFIN_BUILTIN_MAX_2X16);
4879 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi,
4880 BFIN_BUILTIN_SSADD_2X16);
4881 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi,
4882 BFIN_BUILTIN_SSSUB_2X16);
4883 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi,
4884 BFIN_BUILTIN_SSADDSUB_2X16);
4885 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi,
4886 BFIN_BUILTIN_SSSUBADD_2X16);
4887 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi,
4888 BFIN_BUILTIN_MULT_2X16);
4889 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi,
4890 BFIN_BUILTIN_MULTR_2X16);
4891 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi,
4892 BFIN_BUILTIN_NEG_2X16);
4893 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi,
4894 BFIN_BUILTIN_ABS_2X16);
4896 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int,
4897 BFIN_BUILTIN_SSADD_1X16);
4898 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int,
4899 BFIN_BUILTIN_SSSUB_1X16);
4900 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int,
4901 BFIN_BUILTIN_MULT_1X16);
4902 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int,
4903 BFIN_BUILTIN_MULTR_1X16);
4904 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short,
4905 BFIN_BUILTIN_NEG_1X16);
4906 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short,
4907 BFIN_BUILTIN_ABS_1X16);
4908 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int,
4909 BFIN_BUILTIN_NORM_1X16);
4911 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi,
4912 BFIN_BUILTIN_SUM_2X16);
4913 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi,
4914 BFIN_BUILTIN_DIFFHL_2X16);
4915 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi,
4916 BFIN_BUILTIN_DIFFLH_2X16);
4918 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi,
4919 BFIN_BUILTIN_MULHISILL);
4920 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi,
4921 BFIN_BUILTIN_MULHISIHL);
4922 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi,
4923 BFIN_BUILTIN_MULHISILH);
4924 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi,
4925 BFIN_BUILTIN_MULHISIHH);
4927 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int,
4928 BFIN_BUILTIN_SSADD_1X32);
4929 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int,
4930 BFIN_BUILTIN_SSSUB_1X32);
4931 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int,
4932 BFIN_BUILTIN_NEG_1X32);
4933 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int,
4934 BFIN_BUILTIN_ABS_1X32);
4935 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int,
4936 BFIN_BUILTIN_NORM_1X32);
4937 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int,
4938 BFIN_BUILTIN_ROUND_1X32);
4939 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short,
4940 BFIN_BUILTIN_MULT_1X32);
4941 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int,
4942 BFIN_BUILTIN_MULT_1X32X32);
4943 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int,
4944 BFIN_BUILTIN_MULT_1X32X32NS);
4947 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int,
4948 BFIN_BUILTIN_SSASHIFT_1X16);
4949 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int,
4950 BFIN_BUILTIN_SSASHIFT_2X16);
4951 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int,
4952 BFIN_BUILTIN_LSHIFT_1X16);
4953 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int,
4954 BFIN_BUILTIN_LSHIFT_2X16);
4955 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int,
4956 BFIN_BUILTIN_SSASHIFT_1X32);
4958 /* Complex numbers. */
4959 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi,
4960 BFIN_BUILTIN_CPLX_MUL_16);
4961 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi,
4962 BFIN_BUILTIN_CPLX_MAC_16);
4963 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi,
4964 BFIN_BUILTIN_CPLX_MSU_16);
4968 struct builtin_description
4970 const enum insn_code icode;
4971 const char *const name;
4972 const enum bfin_builtins code;
4976 static const struct builtin_description bdesc_2arg[] =
4978 { CODE_FOR_composev2hi, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16, -1 },
4980 { CODE_FOR_ssashiftv2hi3, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16, -1 },
4981 { CODE_FOR_ssashifthi3, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16, -1 },
4982 { CODE_FOR_lshiftv2hi3, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16, -1 },
4983 { CODE_FOR_lshifthi3, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16, -1 },
4984 { CODE_FOR_ssashiftsi3, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32, -1 },
4986 { CODE_FOR_sminhi3, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16, -1 },
4987 { CODE_FOR_smaxhi3, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16, -1 },
4988 { CODE_FOR_ssaddhi3, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16, -1 },
4989 { CODE_FOR_sssubhi3, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16, -1 },
4991 { CODE_FOR_sminsi3, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32, -1 },
4992 { CODE_FOR_smaxsi3, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32, -1 },
4993 { CODE_FOR_ssaddsi3, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32, -1 },
4994 { CODE_FOR_sssubsi3, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32, -1 },
4996 { CODE_FOR_sminv2hi3, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16, -1 },
4997 { CODE_FOR_smaxv2hi3, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16, -1 },
4998 { CODE_FOR_ssaddv2hi3, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16, -1 },
4999 { CODE_FOR_sssubv2hi3, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16, -1 },
5000 { CODE_FOR_ssaddsubv2hi3, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16, -1 },
5001 { CODE_FOR_sssubaddv2hi3, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16, -1 },
5003 { CODE_FOR_flag_mulhisi, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32, MACFLAG_NONE },
5004 { CODE_FOR_flag_mulhi, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16, MACFLAG_T },
5005 { CODE_FOR_flag_mulhi, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16, MACFLAG_NONE },
5006 { CODE_FOR_flag_mulv2hi, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16, MACFLAG_T },
5007 { CODE_FOR_flag_mulv2hi, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16, MACFLAG_NONE }
5010 static const struct builtin_description bdesc_1arg[] =
5012 { CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 },
5013 { CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 },
5014 { CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 },
5016 { CODE_FOR_signbitssi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 },
5017 { CODE_FOR_ssroundsi2, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32, 0 },
5018 { CODE_FOR_ssnegsi2, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32, 0 },
5019 { CODE_FOR_ssabssi2, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32, 0 },
5021 { CODE_FOR_movv2hi_hi_low, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO, 0 },
5022 { CODE_FOR_movv2hi_hi_high, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI, 0 },
5023 { CODE_FOR_ssnegv2hi2, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16, 0 },
5024 { CODE_FOR_ssabsv2hi2, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16, 0 }
5027 /* Errors in the source file can cause expand_expr to return const0_rtx
5028 where we expect a vector. To avoid crashing, use one of the vector
5029 clear instructions. */
5031 safe_vector_operand (rtx x, enum machine_mode mode)
5033 if (x != const0_rtx)
5035 x = gen_reg_rtx (SImode);
5037 emit_insn (gen_movsi (x, CONST0_RTX (SImode)));
5038 return gen_lowpart (mode, x);
5041 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
5042 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
5045 bfin_expand_binop_builtin (enum insn_code icode, tree exp, rtx target,
5049 tree arg0 = CALL_EXPR_ARG (exp, 0);
5050 tree arg1 = CALL_EXPR_ARG (exp, 1);
5051 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5052 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5053 enum machine_mode op0mode = GET_MODE (op0);
5054 enum machine_mode op1mode = GET_MODE (op1);
5055 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5056 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5057 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5059 if (VECTOR_MODE_P (mode0))
5060 op0 = safe_vector_operand (op0, mode0);
5061 if (VECTOR_MODE_P (mode1))
5062 op1 = safe_vector_operand (op1, mode1);
5065 || GET_MODE (target) != tmode
5066 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5067 target = gen_reg_rtx (tmode);
5069 if ((op0mode == SImode || op0mode == VOIDmode) && mode0 == HImode)
5072 op0 = gen_lowpart (HImode, op0);
5074 if ((op1mode == SImode || op1mode == VOIDmode) && mode1 == HImode)
5077 op1 = gen_lowpart (HImode, op1);
5079 /* In case the insn wants input operands in modes different from
5080 the result, abort. */
5081 gcc_assert ((op0mode == mode0 || op0mode == VOIDmode)
5082 && (op1mode == mode1 || op1mode == VOIDmode));
5084 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5085 op0 = copy_to_mode_reg (mode0, op0);
5086 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5087 op1 = copy_to_mode_reg (mode1, op1);
5090 pat = GEN_FCN (icode) (target, op0, op1);
5092 pat = GEN_FCN (icode) (target, op0, op1, GEN_INT (macflag));
5100 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5103 bfin_expand_unop_builtin (enum insn_code icode, tree exp,
5107 tree arg0 = CALL_EXPR_ARG (exp, 0);
5108 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5109 enum machine_mode op0mode = GET_MODE (op0);
5110 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5111 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5114 || GET_MODE (target) != tmode
5115 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5116 target = gen_reg_rtx (tmode);
5118 if (VECTOR_MODE_P (mode0))
5119 op0 = safe_vector_operand (op0, mode0);
5121 if (op0mode == SImode && mode0 == HImode)
5124 op0 = gen_lowpart (HImode, op0);
5126 gcc_assert (op0mode == mode0 || op0mode == VOIDmode);
5128 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5129 op0 = copy_to_mode_reg (mode0, op0);
5131 pat = GEN_FCN (icode) (target, op0);
5138 /* Expand an expression EXP that calls a built-in function,
5139 with result going to TARGET if that's convenient
5140 (and in mode MODE if that's convenient).
5141 SUBTARGET may be used as the target for computing one of EXP's operands.
5142 IGNORE is nonzero if the value is to be ignored. */
5145 bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5146 rtx subtarget ATTRIBUTE_UNUSED,
5147 enum machine_mode mode ATTRIBUTE_UNUSED,
5148 int ignore ATTRIBUTE_UNUSED)
5151 enum insn_code icode;
5152 const struct builtin_description *d;
5153 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
5154 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5155 tree arg0, arg1, arg2;
5156 rtx op0, op1, op2, accvec, pat, tmp1, tmp2, a0reg, a1reg;
5157 enum machine_mode tmode, mode0;
5161 case BFIN_BUILTIN_CSYNC:
5162 emit_insn (gen_csync ());
5164 case BFIN_BUILTIN_SSYNC:
5165 emit_insn (gen_ssync ());
5168 case BFIN_BUILTIN_DIFFHL_2X16:
5169 case BFIN_BUILTIN_DIFFLH_2X16:
5170 case BFIN_BUILTIN_SUM_2X16:
5171 arg0 = CALL_EXPR_ARG (exp, 0);
5172 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5173 icode = (fcode == BFIN_BUILTIN_DIFFHL_2X16 ? CODE_FOR_subhilov2hi3
5174 : fcode == BFIN_BUILTIN_DIFFLH_2X16 ? CODE_FOR_sublohiv2hi3
5175 : CODE_FOR_ssaddhilov2hi3);
5176 tmode = insn_data[icode].operand[0].mode;
5177 mode0 = insn_data[icode].operand[1].mode;
5180 || GET_MODE (target) != tmode
5181 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5182 target = gen_reg_rtx (tmode);
5184 if (VECTOR_MODE_P (mode0))
5185 op0 = safe_vector_operand (op0, mode0);
5187 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5188 op0 = copy_to_mode_reg (mode0, op0);
5190 pat = GEN_FCN (icode) (target, op0, op0);
5196 case BFIN_BUILTIN_MULT_1X32X32:
5197 case BFIN_BUILTIN_MULT_1X32X32NS:
5198 arg0 = CALL_EXPR_ARG (exp, 0);
5199 arg1 = CALL_EXPR_ARG (exp, 1);
5200 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5201 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5203 || !register_operand (target, SImode))
5204 target = gen_reg_rtx (SImode);
5206 a1reg = gen_rtx_REG (PDImode, REG_A1);
5207 a0reg = gen_rtx_REG (PDImode, REG_A0);
5208 tmp1 = gen_lowpart (V2HImode, op0);
5209 tmp2 = gen_lowpart (V2HImode, op1);
5210 emit_insn (gen_flag_macinit1hi (a1reg,
5211 gen_lowpart (HImode, op0),
5212 gen_lowpart (HImode, op1),
5213 GEN_INT (MACFLAG_FU)));
5214 emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
5216 if (fcode == BFIN_BUILTIN_MULT_1X32X32)
5217 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg, a1reg, tmp1, tmp2,
5218 const1_rtx, const1_rtx,
5219 const1_rtx, const0_rtx, a1reg,
5220 const0_rtx, GEN_INT (MACFLAG_NONE),
5221 GEN_INT (MACFLAG_M)));
5224 /* For saturating multiplication, there's exactly one special case
5225 to be handled: multiplying the smallest negative value with
5226 itself. Due to shift correction in fractional multiplies, this
5227 can overflow. Iff this happens, OP2 will contain 1, which, when
5228 added in 32 bits to the smallest negative, wraps to the largest
5229 positive, which is the result we want. */
5230 op2 = gen_reg_rtx (V2HImode);
5231 emit_insn (gen_packv2hi (op2, tmp1, tmp2, const0_rtx, const0_rtx));
5232 emit_insn (gen_movsibi (gen_rtx_REG (BImode, REG_CC),
5233 gen_lowpart (SImode, op2)));
5234 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg, a1reg, tmp1, tmp2,
5235 const1_rtx, const1_rtx,
5236 const1_rtx, const0_rtx, a1reg,
5237 const0_rtx, GEN_INT (MACFLAG_NONE),
5238 GEN_INT (MACFLAG_M)));
5239 op2 = gen_reg_rtx (SImode);
5240 emit_insn (gen_movbisi (op2, gen_rtx_REG (BImode, REG_CC)));
5242 emit_insn (gen_flag_machi_parts_acconly (a1reg, tmp2, tmp1,
5243 const1_rtx, const0_rtx,
5244 a1reg, const0_rtx, GEN_INT (MACFLAG_M)));
5245 emit_insn (gen_ashrpdi3 (a1reg, a1reg, GEN_INT (15)));
5246 emit_insn (gen_sum_of_accumulators (target, a0reg, a0reg, a1reg));
5247 if (fcode == BFIN_BUILTIN_MULT_1X32X32NS)
5248 emit_insn (gen_addsi3 (target, target, op2));
5251 case BFIN_BUILTIN_CPLX_MUL_16:
5252 arg0 = CALL_EXPR_ARG (exp, 0);
5253 arg1 = CALL_EXPR_ARG (exp, 1);
5254 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5255 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5256 accvec = gen_reg_rtx (V2PDImode);
5259 || GET_MODE (target) != V2HImode
5260 || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
5261 target = gen_reg_rtx (tmode);
5262 if (! register_operand (op0, GET_MODE (op0)))
5263 op0 = copy_to_mode_reg (GET_MODE (op0), op0);
5264 if (! register_operand (op1, GET_MODE (op1)))
5265 op1 = copy_to_mode_reg (GET_MODE (op1), op1);
5267 emit_insn (gen_flag_macinit1v2hi_parts (accvec, op0, op1, const0_rtx,
5268 const0_rtx, const0_rtx,
5269 const1_rtx, GEN_INT (MACFLAG_NONE)));
5270 emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx,
5271 const1_rtx, const1_rtx,
5272 const0_rtx, accvec, const1_rtx, const0_rtx,
5273 GEN_INT (MACFLAG_NONE), accvec));
5277 case BFIN_BUILTIN_CPLX_MAC_16:
5278 case BFIN_BUILTIN_CPLX_MSU_16:
5279 arg0 = CALL_EXPR_ARG (exp, 0);
5280 arg1 = CALL_EXPR_ARG (exp, 1);
5281 arg2 = CALL_EXPR_ARG (exp, 2);
5282 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5283 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5284 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5285 accvec = gen_reg_rtx (V2PDImode);
5288 || GET_MODE (target) != V2HImode
5289 || ! (*insn_data[icode].operand[0].predicate) (target, V2HImode))
5290 target = gen_reg_rtx (tmode);
5291 if (! register_operand (op0, GET_MODE (op0)))
5292 op0 = copy_to_mode_reg (GET_MODE (op0), op0);
5293 if (! register_operand (op1, GET_MODE (op1)))
5294 op1 = copy_to_mode_reg (GET_MODE (op1), op1);
5296 tmp1 = gen_reg_rtx (SImode);
5297 tmp2 = gen_reg_rtx (SImode);
5298 emit_insn (gen_ashlsi3 (tmp1, gen_lowpart (SImode, op2), GEN_INT (16)));
5299 emit_move_insn (tmp2, gen_lowpart (SImode, op2));
5300 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode, tmp2), const0_rtx));
5301 emit_insn (gen_load_accumulator_pair (accvec, tmp1, tmp2));
5302 emit_insn (gen_flag_macv2hi_parts_acconly (accvec, op0, op1, const0_rtx,
5303 const0_rtx, const0_rtx,
5304 const1_rtx, accvec, const0_rtx,
5306 GEN_INT (MACFLAG_W32)));
5307 tmp1 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const1_rtx : const0_rtx);
5308 tmp2 = (fcode == BFIN_BUILTIN_CPLX_MAC_16 ? const0_rtx : const1_rtx);
5309 emit_insn (gen_flag_macv2hi_parts (target, op0, op1, const1_rtx,
5310 const1_rtx, const1_rtx,
5311 const0_rtx, accvec, tmp1, tmp2,
5312 GEN_INT (MACFLAG_NONE), accvec));
5320 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
5321 if (d->code == fcode)
5322 return bfin_expand_binop_builtin (d->icode, exp, target,
5325 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
5326 if (d->code == fcode)
5327 return bfin_expand_unop_builtin (d->icode, exp, target);
5332 #undef TARGET_INIT_BUILTINS
5333 #define TARGET_INIT_BUILTINS bfin_init_builtins
5335 #undef TARGET_EXPAND_BUILTIN
5336 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
5338 #undef TARGET_ASM_GLOBALIZE_LABEL
5339 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
5341 #undef TARGET_ASM_FILE_START
5342 #define TARGET_ASM_FILE_START output_file_start
5344 #undef TARGET_ATTRIBUTE_TABLE
5345 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
5347 #undef TARGET_COMP_TYPE_ATTRIBUTES
5348 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
5350 #undef TARGET_RTX_COSTS
5351 #define TARGET_RTX_COSTS bfin_rtx_costs
5353 #undef TARGET_ADDRESS_COST
5354 #define TARGET_ADDRESS_COST bfin_address_cost
5356 #undef TARGET_ASM_INTEGER
5357 #define TARGET_ASM_INTEGER bfin_assemble_integer
5359 #undef TARGET_MACHINE_DEPENDENT_REORG
5360 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
5362 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5363 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
5365 #undef TARGET_ASM_OUTPUT_MI_THUNK
5366 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
5367 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5368 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
5370 #undef TARGET_SCHED_ADJUST_COST
5371 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
5373 #undef TARGET_SCHED_ISSUE_RATE
5374 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
5376 #undef TARGET_PROMOTE_PROTOTYPES
5377 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
5378 #undef TARGET_PROMOTE_FUNCTION_ARGS
5379 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
5380 #undef TARGET_PROMOTE_FUNCTION_RETURN
5381 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
5383 #undef TARGET_ARG_PARTIAL_BYTES
5384 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
5386 #undef TARGET_PASS_BY_REFERENCE
5387 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
5389 #undef TARGET_SETUP_INCOMING_VARARGS
5390 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
5392 #undef TARGET_STRUCT_VALUE_RTX
5393 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
5395 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5396 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
5398 #undef TARGET_HANDLE_OPTION
5399 #define TARGET_HANDLE_OPTION bfin_handle_option
5401 #undef TARGET_DEFAULT_TARGET_FLAGS
5402 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5404 #undef TARGET_SECONDARY_RELOAD
5405 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
5407 #undef TARGET_DELEGITIMIZE_ADDRESS
5408 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
5410 #undef TARGET_CANNOT_FORCE_CONST_MEM
5411 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
5413 struct gcc_target targetm = TARGET_INITIALIZER;