1 ;; -*- Mode: Scheme -*-
2 ;; Machine description for GNU compiler,
3 ;; for ATMEL AVR micro controllers.
4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008
5 ;; Free Software Foundation, Inc.
6 ;; Contributed by Denis Chertykov (denisc@overta.ru)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; Special characters after '%':
25 ;; A No effect (add 0).
26 ;; B Add 1 to REG number, MEM address or CONST_INT.
29 ;; j Branch condition.
30 ;; k Reverse branch condition.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
34 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
35 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
38 ;; 0 Length of a string, see "strlenhi".
39 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
47 (TMP_REGNO 0) ; temporary register r0
48 (ZERO_REGNO 1) ; zero register r1
58 (UNSPECV_PROLOGUE_SAVES 0)
59 (UNSPECV_EPILOGUE_RESTORES 1)
60 (UNSPECV_WRITE_SP_IRQ_ON 2)
61 (UNSPECV_WRITE_SP_IRQ_OFF 3)
62 (UNSPECV_GOTO_RECEIVER 4)])
64 (include "predicates.md")
65 (include "constraints.md")
67 ;; Condition code settings.
68 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
69 (const_string "none"))
71 (define_attr "type" "branch,branch1,arith,xcall"
72 (const_string "arith"))
74 (define_attr "mcu_have_movw" "yes,no"
75 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
77 (const_string "no"))))
79 (define_attr "mcu_mega" "yes,no"
80 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
82 (const_string "no"))))
85 ;; The size of instructions in bytes.
86 ;; XXX may depend from "cc"
88 (define_attr "length" ""
89 (cond [(eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (pc) (match_dup 0))
92 (le (minus (pc) (match_dup 0))
95 (if_then_else (and (ge (minus (pc) (match_dup 0))
97 (le (minus (pc) (match_dup 0))
101 (eq_attr "type" "branch1")
102 (if_then_else (and (ge (minus (pc) (match_dup 0))
104 (le (minus (pc) (match_dup 0))
107 (if_then_else (and (ge (minus (pc) (match_dup 0))
109 (le (minus (pc) (match_dup 0))
113 (eq_attr "type" "xcall")
114 (if_then_else (eq_attr "mcu_mega" "no")
119 ;; Define mode iterator
120 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
122 ;;========================================================================
123 ;; The following is used by nonlocal_goto and setjmp.
124 ;; The receiver pattern will create no instructions since internally
125 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
126 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
127 ;; The 'null' receiver also avoids problems with optimisation
128 ;; not recognising incoming jmp and removing code that resets frame_pointer.
129 ;; The code derived from builtins.c.
131 (define_expand "nonlocal_goto_receiver"
133 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
136 emit_move_insn (virtual_stack_vars_rtx,
137 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
138 gen_int_mode (STARTING_FRAME_OFFSET,
140 /* This might change the hard frame pointer in ways that aren't
141 apparent to early optimization passes, so force a clobber. */
142 emit_clobber (hard_frame_pointer_rtx);
147 ;; Defining nonlocal_goto_receiver means we must also define this.
148 ;; even though its function is identical to that in builtins.c
150 (define_expand "nonlocal_goto"
152 (use (match_operand 0 "general_operand"))
153 (use (match_operand 1 "general_operand"))
154 (use (match_operand 2 "general_operand"))
155 (use (match_operand 3 "general_operand"))
159 rtx r_label = copy_to_reg (operands[1]);
160 rtx r_fp = operands[3];
161 rtx r_sp = operands[2];
163 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
165 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
167 emit_move_insn (hard_frame_pointer_rtx, r_fp);
168 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
170 emit_use (hard_frame_pointer_rtx);
171 emit_use (stack_pointer_rtx);
173 emit_indirect_jump (r_label);
179 (define_insn "*pushqi"
180 [(set (mem:QI (post_dec (reg:HI REG_SP)))
181 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
186 [(set_attr "length" "1,1")])
189 (define_insn "*pushhi"
190 [(set (mem:HI (post_dec (reg:HI REG_SP)))
191 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
195 push __zero_reg__\;push __zero_reg__"
196 [(set_attr "length" "2,2")])
198 (define_insn "*pushsi"
199 [(set (mem:SI (post_dec (reg:HI REG_SP)))
200 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
203 push %D0\;push %C0\;push %B0\;push %A0
204 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
205 [(set_attr "length" "4,4")])
207 (define_insn "*pushsf"
208 [(set (mem:SF (post_dec (reg:HI REG_SP)))
209 (match_operand:SF 0 "register_operand" "r"))]
215 [(set_attr "length" "4")])
217 ;;========================================================================
219 ;; The last alternative (any immediate constant to any register) is
220 ;; very expensive. It should be optimized by peephole2 if a scratch
221 ;; register is available, but then that register could just as well be
222 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
223 ;; are call-saved registers, and most of LD_REGS are call-used registers,
224 ;; so this may still be a win for registers live across function calls.
226 (define_expand "movqi"
227 [(set (match_operand:QI 0 "nonimmediate_operand" "")
228 (match_operand:QI 1 "general_operand" ""))]
230 "/* One of the ops has to be in a register. */
231 if (!register_operand(operand0, QImode)
232 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
233 operands[1] = copy_to_mode_reg(QImode, operand1);
236 (define_insn "*movqi"
237 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
238 (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))]
239 "(register_operand (operands[0],QImode)
240 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
241 "* return output_movqi (insn, operands, NULL);"
242 [(set_attr "length" "1,1,5,5,1,1,4")
243 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
245 ;; This is used in peephole2 to optimize loading immediate constants
246 ;; if a scratch register from LD_REGS happens to be available.
248 (define_insn "*reload_inqi"
249 [(set (match_operand:QI 0 "register_operand" "=l")
250 (match_operand:QI 1 "immediate_operand" "i"))
251 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
255 [(set_attr "length" "2")
256 (set_attr "cc" "none")])
259 [(match_scratch:QI 2 "d")
260 (set (match_operand:QI 0 "l_register_operand" "")
261 (match_operand:QI 1 "immediate_operand" ""))]
262 "(operands[1] != const0_rtx
263 && operands[1] != const1_rtx
264 && operands[1] != constm1_rtx)"
265 [(parallel [(set (match_dup 0) (match_dup 1))
266 (clobber (match_dup 2))])]
269 ;;============================================================================
270 ;; move word (16 bit)
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "nonimmediate_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
278 /* One of the ops has to be in a register. */
279 if (!register_operand(operand0, HImode)
280 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
282 operands[1] = copy_to_mode_reg(HImode, operand1);
286 (define_insn "*movhi_sp"
287 [(set (match_operand:HI 0 "register_operand" "=q,r")
288 (match_operand:HI 1 "register_operand" "r,q"))]
289 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
290 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
291 "* return output_movhi (insn, operands, NULL);"
292 [(set_attr "length" "5,2")
293 (set_attr "cc" "none,none")])
295 (define_insn "movhi_sp_r_irq_off"
296 [(set (match_operand:HI 0 "stack_register_operand" "=q")
297 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
298 UNSPECV_WRITE_SP_IRQ_OFF))]
302 [(set_attr "length" "2")
303 (set_attr "cc" "none")])
305 (define_insn "movhi_sp_r_irq_on"
306 [(set (match_operand:HI 0 "stack_register_operand" "=q")
307 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
308 UNSPECV_WRITE_SP_IRQ_ON))]
314 [(set_attr "length" "4")
315 (set_attr "cc" "none")])
318 [(match_scratch:QI 2 "d")
319 (set (match_operand:HI 0 "l_register_operand" "")
320 (match_operand:HI 1 "immediate_operand" ""))]
321 "(operands[1] != const0_rtx
322 && operands[1] != constm1_rtx)"
323 [(parallel [(set (match_dup 0) (match_dup 1))
324 (clobber (match_dup 2))])]
327 ;; '*' because it is not used in rtl generation, only in above peephole
328 (define_insn "*reload_inhi"
329 [(set (match_operand:HI 0 "register_operand" "=r")
330 (match_operand:HI 1 "immediate_operand" "i"))
331 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
333 "* return output_reload_inhi (insn, operands, NULL);"
334 [(set_attr "length" "4")
335 (set_attr "cc" "none")])
337 (define_insn "*movhi"
338 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
339 (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))]
340 "(register_operand (operands[0],HImode)
341 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
342 "* return output_movhi (insn, operands, NULL);"
343 [(set_attr "length" "2,6,7,2,6,5,2")
344 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
346 (define_peephole2 ; movw
347 [(set (match_operand:QI 0 "even_register_operand" "")
348 (match_operand:QI 1 "even_register_operand" ""))
349 (set (match_operand:QI 2 "odd_register_operand" "")
350 (match_operand:QI 3 "odd_register_operand" ""))]
352 && REGNO (operands[0]) == REGNO (operands[2]) - 1
353 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
354 [(set (match_dup 4) (match_dup 5))]
356 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
357 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
360 (define_peephole2 ; movw_r
361 [(set (match_operand:QI 0 "odd_register_operand" "")
362 (match_operand:QI 1 "odd_register_operand" ""))
363 (set (match_operand:QI 2 "even_register_operand" "")
364 (match_operand:QI 3 "even_register_operand" ""))]
366 && REGNO (operands[2]) == REGNO (operands[0]) - 1
367 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
368 [(set (match_dup 4) (match_dup 5))]
370 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
371 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
374 ;;==========================================================================
375 ;; move double word (32 bit)
377 (define_expand "movsi"
378 [(set (match_operand:SI 0 "nonimmediate_operand" "")
379 (match_operand:SI 1 "general_operand" ""))]
383 /* One of the ops has to be in a register. */
384 if (!register_operand (operand0, SImode)
385 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
387 operands[1] = copy_to_mode_reg (SImode, operand1);
393 (define_peephole2 ; movsi_lreg_const
394 [(match_scratch:QI 2 "d")
395 (set (match_operand:SI 0 "l_register_operand" "")
396 (match_operand:SI 1 "immediate_operand" ""))
398 "(operands[1] != const0_rtx
399 && operands[1] != constm1_rtx)"
400 [(parallel [(set (match_dup 0) (match_dup 1))
401 (clobber (match_dup 2))])]
404 ;; '*' because it is not used in rtl generation.
405 (define_insn "*reload_insi"
406 [(set (match_operand:SI 0 "register_operand" "=r")
407 (match_operand:SI 1 "immediate_operand" "i"))
408 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
410 "* return output_reload_insisf (insn, operands, NULL);"
411 [(set_attr "length" "8")
412 (set_attr "cc" "none")])
415 (define_insn "*movsi"
416 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
417 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
418 "(register_operand (operands[0],SImode)
419 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
420 "* return output_movsisf (insn, operands, NULL);"
421 [(set_attr "length" "4,4,8,9,4,10")
422 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
424 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
425 ;; move floating point numbers (32 bit)
427 (define_expand "movsf"
428 [(set (match_operand:SF 0 "nonimmediate_operand" "")
429 (match_operand:SF 1 "general_operand" ""))]
433 /* One of the ops has to be in a register. */
434 if (!register_operand (operand1, SFmode)
435 && !register_operand (operand0, SFmode))
437 operands[1] = copy_to_mode_reg (SFmode, operand1);
441 (define_insn "*movsf"
442 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
443 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
444 "register_operand (operands[0], SFmode)
445 || register_operand (operands[1], SFmode)"
446 "* return output_movsisf (insn, operands, NULL);"
447 [(set_attr "length" "4,4,8,9,4,10")
448 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
450 ;;=========================================================================
451 ;; move string (like memcpy)
452 ;; implement as RTL loop
454 (define_expand "movmemhi"
455 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
456 (match_operand:BLK 1 "memory_operand" ""))
457 (use (match_operand:HI 2 "const_int_operand" ""))
458 (use (match_operand:HI 3 "const_int_operand" ""))])]
463 enum machine_mode mode;
464 rtx label = gen_label_rtx ();
468 /* Copy pointers into new psuedos - they will be changed. */
469 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
470 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
472 /* Create rtx for tmp register - we use this as scratch. */
473 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
475 if (GET_CODE (operands[2]) != CONST_INT)
478 count = INTVAL (operands[2]);
482 /* Work out branch probability for latter use. */
483 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
485 /* See if constant fit 8 bits. */
486 mode = (count < 0x100) ? QImode : HImode;
487 /* Create loop counter register. */
488 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
490 /* Now create RTL code for move loop. */
491 /* Label at top of loop. */
494 /* Move one byte into scratch and inc pointer. */
495 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
496 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
498 /* Move to mem and inc pointer. */
499 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
500 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
502 /* Decrement count. */
503 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
505 /* Compare with zero and jump if not equal. */
506 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
508 /* Set jump probability based on loop count. */
509 jump = get_last_insn ();
510 REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_BR_PROB,
516 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
517 ;; memset (%0, %2, %1)
519 (define_expand "setmemhi"
520 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
521 (match_operand 2 "const_int_operand" ""))
522 (use (match_operand:HI 1 "const_int_operand" ""))
523 (use (match_operand:HI 3 "const_int_operand" "n"))
524 (clobber (match_scratch:HI 4 ""))
525 (clobber (match_dup 5))])]
530 enum machine_mode mode;
532 /* If value to set is not zero, use the library routine. */
533 if (operands[2] != const0_rtx)
536 if (GET_CODE (operands[1]) != CONST_INT)
539 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
540 mode = cnt8 ? QImode : HImode;
541 operands[5] = gen_rtx_SCRATCH (mode);
542 operands[1] = copy_to_mode_reg (mode,
543 gen_int_mode (INTVAL (operands[1]), mode));
544 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
545 operands[0] = gen_rtx_MEM (BLKmode, addr0);
548 (define_insn "*clrmemqi"
549 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
551 (use (match_operand:QI 1 "register_operand" "r"))
552 (use (match_operand:QI 2 "const_int_operand" "n"))
553 (clobber (match_scratch:HI 3 "=0"))
554 (clobber (match_scratch:QI 4 "=&1"))]
556 "st %a0+,__zero_reg__
559 [(set_attr "length" "3")
560 (set_attr "cc" "clobber")])
562 (define_insn "*clrmemhi"
563 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
565 (use (match_operand:HI 1 "register_operand" "!w,d"))
566 (use (match_operand:HI 2 "const_int_operand" "n,n"))
567 (clobber (match_scratch:HI 3 "=0,0"))
568 (clobber (match_scratch:HI 4 "=&1,&1"))]
571 if (which_alternative==0)
572 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
573 AS2 (sbiw,%A1,1) CR_TAB
576 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
577 AS2 (subi,%A1,1) CR_TAB
578 AS2 (sbci,%B1,0) CR_TAB
581 [(set_attr "length" "3,4")
582 (set_attr "cc" "clobber,clobber")])
584 (define_expand "strlenhi"
586 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
587 (match_operand:QI 2 "const_int_operand" "")
588 (match_operand:HI 3 "immediate_operand" "")]
590 (set (match_dup 4) (plus:HI (match_dup 4)
592 (set (match_operand:HI 0 "register_operand" "")
593 (minus:HI (match_dup 4)
598 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
600 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
601 operands[1] = gen_rtx_MEM (BLKmode, addr);
603 operands[4] = gen_reg_rtx (HImode);
606 (define_insn "*strlenhi"
607 [(set (match_operand:HI 0 "register_operand" "=e")
608 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
610 (match_operand:HI 2 "immediate_operand" "i")]
616 [(set_attr "length" "3")
617 (set_attr "cc" "clobber")])
619 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
622 (define_insn "addqi3"
623 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
624 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
625 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
632 [(set_attr "length" "1,1,1,1")
633 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
636 (define_expand "addhi3"
637 [(set (match_operand:HI 0 "register_operand" "")
638 (plus:HI (match_operand:HI 1 "register_operand" "")
639 (match_operand:HI 2 "nonmemory_operand" "")))]
643 if (GET_CODE (operands[2]) == CONST_INT)
645 short tmp = INTVAL (operands[2]);
646 operands[2] = GEN_INT(tmp);
651 (define_insn "*addhi3_zero_extend"
652 [(set (match_operand:HI 0 "register_operand" "=r")
653 (plus:HI (zero_extend:HI
654 (match_operand:QI 1 "register_operand" "r"))
655 (match_operand:HI 2 "register_operand" "0")))]
658 adc %B0,__zero_reg__"
659 [(set_attr "length" "2")
660 (set_attr "cc" "set_n")])
662 (define_insn "*addhi3_zero_extend1"
663 [(set (match_operand:HI 0 "register_operand" "=r")
664 (plus:HI (match_operand:HI 1 "register_operand" "%0")
666 (match_operand:QI 2 "register_operand" "r"))))]
669 adc %B0,__zero_reg__"
670 [(set_attr "length" "2")
671 (set_attr "cc" "set_n")])
673 (define_insn "*addhi3_sp_R_pc2"
674 [(set (match_operand:HI 1 "stack_register_operand" "=q")
675 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
676 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
679 if (CONST_INT_P (operands[0]))
681 switch(INTVAL (operands[0]))
684 return \"rcall .\" CR_TAB
688 return \"rcall .\" CR_TAB
690 \"push __tmp_reg__\";
692 return \"rcall .\" CR_TAB
695 return \"rcall .\" CR_TAB
696 \"push __tmp_reg__\";
700 return \"push __tmp_reg__\";
704 return \"pop __tmp_reg__\";
706 return \"pop __tmp_reg__\" CR_TAB
709 return \"pop __tmp_reg__\" CR_TAB
710 \"pop __tmp_reg__\" CR_TAB
713 return \"pop __tmp_reg__\" CR_TAB
714 \"pop __tmp_reg__\" CR_TAB
715 \"pop __tmp_reg__\" CR_TAB
718 return \"pop __tmp_reg__\" CR_TAB
719 \"pop __tmp_reg__\" CR_TAB
720 \"pop __tmp_reg__\" CR_TAB
721 \"pop __tmp_reg__\" CR_TAB
727 [(set (attr "length")
728 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
729 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
730 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
731 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
732 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
733 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
734 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
735 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
736 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
737 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
738 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
739 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
742 (define_insn "*addhi3_sp_R_pc3"
743 [(set (match_operand:HI 1 "stack_register_operand" "=q")
744 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
745 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
748 if (CONST_INT_P (operands[0]))
750 switch(INTVAL (operands[0]))
753 return \"rcall .\" CR_TAB
756 return \"rcall .\" CR_TAB
757 \"push __tmp_reg__\" CR_TAB
758 \"push __tmp_reg__\";
760 return \"rcall .\" CR_TAB
761 \"push __tmp_reg__\";
765 return \"push __tmp_reg__\" CR_TAB
766 \"push __tmp_reg__\";
768 return \"push __tmp_reg__\";
772 return \"pop __tmp_reg__\";
774 return \"pop __tmp_reg__\" CR_TAB
777 return \"pop __tmp_reg__\" CR_TAB
778 \"pop __tmp_reg__\" CR_TAB
781 return \"pop __tmp_reg__\" CR_TAB
782 \"pop __tmp_reg__\" CR_TAB
783 \"pop __tmp_reg__\" CR_TAB
786 return \"pop __tmp_reg__\" CR_TAB
787 \"pop __tmp_reg__\" CR_TAB
788 \"pop __tmp_reg__\" CR_TAB
789 \"pop __tmp_reg__\" CR_TAB
795 [(set (attr "length")
796 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
797 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
798 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
799 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
800 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
801 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
802 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
803 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
804 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
805 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
806 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
807 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
810 (define_insn "*addhi3"
811 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
813 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
814 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
817 add %A0,%A2\;adc %B0,%B2
820 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
821 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
822 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
823 [(set_attr "length" "2,1,1,2,3,3")
824 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
826 (define_insn "addsi3"
827 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
829 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
830 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
833 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
834 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
835 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
836 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
837 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
838 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
839 [(set_attr "length" "4,3,3,4,5,5")
840 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
842 (define_insn "*addsi3_zero_extend"
843 [(set (match_operand:SI 0 "register_operand" "=r")
844 (plus:SI (zero_extend:SI
845 (match_operand:QI 1 "register_operand" "r"))
846 (match_operand:SI 2 "register_operand" "0")))]
851 adc %D0,__zero_reg__"
852 [(set_attr "length" "4")
853 (set_attr "cc" "set_n")])
855 ;-----------------------------------------------------------------------------
857 (define_insn "subqi3"
858 [(set (match_operand:QI 0 "register_operand" "=r,d")
859 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
860 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
865 [(set_attr "length" "1,1")
866 (set_attr "cc" "set_czn,set_czn")])
868 (define_insn "subhi3"
869 [(set (match_operand:HI 0 "register_operand" "=r,d")
870 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
871 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
874 sub %A0,%A2\;sbc %B0,%B2
875 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
876 [(set_attr "length" "2,2")
877 (set_attr "cc" "set_czn,set_czn")])
879 (define_insn "*subhi3_zero_extend1"
880 [(set (match_operand:HI 0 "register_operand" "=r")
881 (minus:HI (match_operand:HI 1 "register_operand" "0")
883 (match_operand:QI 2 "register_operand" "r"))))]
886 sbc %B0,__zero_reg__"
887 [(set_attr "length" "2")
888 (set_attr "cc" "set_n")])
890 (define_insn "subsi3"
891 [(set (match_operand:SI 0 "register_operand" "=r,d")
892 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
893 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
896 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
897 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
898 [(set_attr "length" "4,4")
899 (set_attr "cc" "set_czn,set_czn")])
901 (define_insn "*subsi3_zero_extend"
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (minus:SI (match_operand:SI 1 "register_operand" "0")
905 (match_operand:QI 2 "register_operand" "r"))))]
910 sbc %D0,__zero_reg__"
911 [(set_attr "length" "4")
912 (set_attr "cc" "set_n")])
914 ;******************************************************************************
917 (define_expand "mulqi3"
918 [(set (match_operand:QI 0 "register_operand" "")
919 (mult:QI (match_operand:QI 1 "register_operand" "")
920 (match_operand:QI 2 "register_operand" "")))]
925 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
930 (define_insn "*mulqi3_enh"
931 [(set (match_operand:QI 0 "register_operand" "=r")
932 (mult:QI (match_operand:QI 1 "register_operand" "r")
933 (match_operand:QI 2 "register_operand" "r")))]
938 [(set_attr "length" "3")
939 (set_attr "cc" "clobber")])
941 (define_expand "mulqi3_call"
942 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
943 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
944 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
945 (clobber (reg:QI 22))])
946 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
950 (define_insn "*mulqi3_call"
951 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
952 (clobber (reg:QI 22))]
955 [(set_attr "type" "xcall")
956 (set_attr "cc" "clobber")])
958 (define_insn "mulqihi3"
959 [(set (match_operand:HI 0 "register_operand" "=r")
960 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
961 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
966 [(set_attr "length" "3")
967 (set_attr "cc" "clobber")])
969 (define_insn "umulqihi3"
970 [(set (match_operand:HI 0 "register_operand" "=r")
971 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
972 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
977 [(set_attr "length" "3")
978 (set_attr "cc" "clobber")])
980 (define_expand "mulhi3"
981 [(set (match_operand:HI 0 "register_operand" "")
982 (mult:HI (match_operand:HI 1 "register_operand" "")
983 (match_operand:HI 2 "register_operand" "")))]
989 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
994 (define_insn "*mulhi3_enh"
995 [(set (match_operand:HI 0 "register_operand" "=&r")
996 (mult:HI (match_operand:HI 1 "register_operand" "r")
997 (match_operand:HI 2 "register_operand" "r")))]
1006 [(set_attr "length" "7")
1007 (set_attr "cc" "clobber")])
1009 (define_expand "mulhi3_call"
1010 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1011 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1012 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1013 (clobber (reg:HI 22))
1014 (clobber (reg:QI 21))])
1015 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
1019 (define_insn "*mulhi3_call"
1020 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1021 (clobber (reg:HI 22))
1022 (clobber (reg:QI 21))]
1025 [(set_attr "type" "xcall")
1026 (set_attr "cc" "clobber")])
1028 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
1029 ;; All call-used registers clobbered otherwise - normal library call.
1030 (define_expand "mulsi3"
1031 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1032 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1033 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1034 (clobber (reg:HI 26))
1035 (clobber (reg:HI 30))])
1036 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
1040 (define_insn "*mulsi3_call"
1041 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1042 (clobber (reg:HI 26))
1043 (clobber (reg:HI 30))]
1046 [(set_attr "type" "xcall")
1047 (set_attr "cc" "clobber")])
1049 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
1052 ;; Generate libgcc.S calls ourselves, because:
1053 ;; - we know exactly which registers are clobbered (for QI and HI
1054 ;; modes, some of the call-used registers are preserved)
1055 ;; - we get both the quotient and the remainder at no extra cost
1057 (define_expand "divmodqi4"
1058 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
1059 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
1060 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1061 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1062 (clobber (reg:QI 22))
1063 (clobber (reg:QI 23))])
1064 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
1065 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
1069 (define_insn "*divmodqi4_call"
1070 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1071 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1072 (clobber (reg:QI 22))
1073 (clobber (reg:QI 23))]
1075 "%~call __divmodqi4"
1076 [(set_attr "type" "xcall")
1077 (set_attr "cc" "clobber")])
1079 (define_expand "udivmodqi4"
1080 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
1081 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
1082 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1083 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1084 (clobber (reg:QI 23))])
1085 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
1086 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
1090 (define_insn "*udivmodqi4_call"
1091 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1092 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1093 (clobber (reg:QI 23))]
1095 "%~call __udivmodqi4"
1096 [(set_attr "type" "xcall")
1097 (set_attr "cc" "clobber")])
1099 (define_expand "divmodhi4"
1100 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1101 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1102 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1103 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1104 (clobber (reg:HI 26))
1105 (clobber (reg:QI 21))])
1106 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
1107 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
1111 (define_insn "*divmodhi4_call"
1112 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1113 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1114 (clobber (reg:HI 26))
1115 (clobber (reg:QI 21))]
1117 "%~call __divmodhi4"
1118 [(set_attr "type" "xcall")
1119 (set_attr "cc" "clobber")])
1121 (define_expand "udivmodhi4"
1122 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1123 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1124 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1125 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1126 (clobber (reg:HI 26))
1127 (clobber (reg:QI 21))])
1128 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
1129 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
1133 (define_insn "*udivmodhi4_call"
1134 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1135 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1136 (clobber (reg:HI 26))
1137 (clobber (reg:QI 21))]
1139 "%~call __udivmodhi4"
1140 [(set_attr "type" "xcall")
1141 (set_attr "cc" "clobber")])
1143 (define_expand "divmodsi4"
1144 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1145 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1146 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1147 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1148 (clobber (reg:HI 26))
1149 (clobber (reg:HI 30))])
1150 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
1151 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
1155 (define_insn "*divmodsi4_call"
1156 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1157 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1158 (clobber (reg:HI 26))
1159 (clobber (reg:HI 30))]
1161 "%~call __divmodsi4"
1162 [(set_attr "type" "xcall")
1163 (set_attr "cc" "clobber")])
1165 (define_expand "udivmodsi4"
1166 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1167 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1168 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1169 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1170 (clobber (reg:HI 26))
1171 (clobber (reg:HI 30))])
1172 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
1173 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
1177 (define_insn "*udivmodsi4_call"
1178 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1179 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1180 (clobber (reg:HI 26))
1181 (clobber (reg:HI 30))]
1183 "%~call __udivmodsi4"
1184 [(set_attr "type" "xcall")
1185 (set_attr "cc" "clobber")])
1187 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
1190 (define_insn "andqi3"
1191 [(set (match_operand:QI 0 "register_operand" "=r,d")
1192 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
1193 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1198 [(set_attr "length" "1,1")
1199 (set_attr "cc" "set_zn,set_zn")])
1201 (define_insn "andhi3"
1202 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1203 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1204 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1205 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1208 if (which_alternative==0)
1209 return (AS2 (and,%A0,%A2) CR_TAB
1211 else if (which_alternative==1)
1213 if (GET_CODE (operands[2]) == CONST_INT)
1215 int mask = INTVAL (operands[2]);
1216 if ((mask & 0xff) != 0xff)
1217 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1218 if ((mask & 0xff00) != 0xff00)
1219 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1222 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1223 AS2 (andi,%B0,hi8(%2)));
1225 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1226 AS2 (and,%A0,%3) CR_TAB
1229 [(set_attr "length" "2,2,3")
1230 (set_attr "cc" "set_n,clobber,set_n")])
1232 (define_insn "andsi3"
1233 [(set (match_operand:SI 0 "register_operand" "=r,d")
1234 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1235 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1238 if (which_alternative==0)
1239 return (AS2 (and, %0,%2) CR_TAB
1240 AS2 (and, %B0,%B2) CR_TAB
1241 AS2 (and, %C0,%C2) CR_TAB
1242 AS2 (and, %D0,%D2));
1243 else if (which_alternative==1)
1245 if (GET_CODE (operands[2]) == CONST_INT)
1247 HOST_WIDE_INT mask = INTVAL (operands[2]);
1248 if ((mask & 0xff) != 0xff)
1249 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1250 if ((mask & 0xff00) != 0xff00)
1251 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1252 if ((mask & 0xff0000L) != 0xff0000L)
1253 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1254 if ((mask & 0xff000000L) != 0xff000000L)
1255 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1258 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1259 AS2 (andi, %B0,hi8(%2)) CR_TAB
1260 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1261 AS2 (andi, %D0,hhi8(%2)));
1265 [(set_attr "length" "4,4")
1266 (set_attr "cc" "set_n,set_n")])
1268 (define_peephole2 ; andi
1269 [(set (match_operand:QI 0 "d_register_operand" "")
1270 (and:QI (match_dup 0)
1271 (match_operand:QI 1 "const_int_operand" "")))
1273 (and:QI (match_dup 0)
1274 (match_operand:QI 2 "const_int_operand" "")))]
1276 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1278 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
1281 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1284 (define_insn "iorqi3"
1285 [(set (match_operand:QI 0 "register_operand" "=r,d")
1286 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1287 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1292 [(set_attr "length" "1,1")
1293 (set_attr "cc" "set_zn,set_zn")])
1295 (define_insn "iorhi3"
1296 [(set (match_operand:HI 0 "register_operand" "=r,d")
1297 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1298 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1301 if (which_alternative==0)
1302 return (AS2 (or,%A0,%A2) CR_TAB
1304 if (GET_CODE (operands[2]) == CONST_INT)
1306 int mask = INTVAL (operands[2]);
1308 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1310 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1313 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1314 AS2 (ori,%B0,hi8(%2)));
1316 [(set_attr "length" "2,2")
1317 (set_attr "cc" "set_n,clobber")])
1319 (define_insn "*iorhi3_clobber"
1320 [(set (match_operand:HI 0 "register_operand" "=r,r")
1321 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1322 (match_operand:HI 2 "immediate_operand" "M,i")))
1323 (clobber (match_scratch:QI 3 "=&d,&d"))]
1326 ldi %3,lo8(%2)\;or %A0,%3
1327 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1328 [(set_attr "length" "2,4")
1329 (set_attr "cc" "clobber,set_n")])
1331 (define_insn "iorsi3"
1332 [(set (match_operand:SI 0 "register_operand" "=r,d")
1333 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1334 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1337 if (which_alternative==0)
1338 return (AS2 (or, %0,%2) CR_TAB
1339 AS2 (or, %B0,%B2) CR_TAB
1340 AS2 (or, %C0,%C2) CR_TAB
1342 if (GET_CODE (operands[2]) == CONST_INT)
1344 HOST_WIDE_INT mask = INTVAL (operands[2]);
1346 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1348 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1349 if (mask & 0xff0000L)
1350 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1351 if (mask & 0xff000000L)
1352 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1355 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1356 AS2 (ori, %B0,hi8(%2)) CR_TAB
1357 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1358 AS2 (ori, %D0,hhi8(%2)));
1360 [(set_attr "length" "4,4")
1361 (set_attr "cc" "set_n,clobber")])
1363 (define_insn "*iorsi3_clobber"
1364 [(set (match_operand:SI 0 "register_operand" "=r,r")
1365 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1366 (match_operand:SI 2 "immediate_operand" "M,i")))
1367 (clobber (match_scratch:QI 3 "=&d,&d"))]
1370 ldi %3,lo8(%2)\;or %A0,%3
1371 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1372 [(set_attr "length" "2,8")
1373 (set_attr "cc" "clobber,set_n")])
1375 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1378 (define_insn "xorqi3"
1379 [(set (match_operand:QI 0 "register_operand" "=r")
1380 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1381 (match_operand:QI 2 "register_operand" "r")))]
1384 [(set_attr "length" "1")
1385 (set_attr "cc" "set_zn")])
1387 (define_insn "xorhi3"
1388 [(set (match_operand:HI 0 "register_operand" "=r")
1389 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1390 (match_operand:HI 2 "register_operand" "r")))]
1394 [(set_attr "length" "2")
1395 (set_attr "cc" "set_n")])
1397 (define_insn "xorsi3"
1398 [(set (match_operand:SI 0 "register_operand" "=r")
1399 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1400 (match_operand:SI 2 "register_operand" "r")))]
1406 [(set_attr "length" "4")
1407 (set_attr "cc" "set_n")])
1409 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
1412 (define_expand "rotlqi3"
1413 [(set (match_operand:QI 0 "register_operand" "")
1414 (rotate:QI (match_operand:QI 1 "register_operand" "")
1415 (match_operand:QI 2 "const_int_operand" "")))]
1419 if (INTVAL (operands[2]) != 4)
1423 (define_insn "*rotlqi3_4"
1424 [(set (match_operand:QI 0 "register_operand" "=r")
1425 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1429 [(set_attr "length" "1")
1430 (set_attr "cc" "none")])
1432 (define_expand "rotlhi3"
1433 [(set (match_operand:HI 0 "register_operand" "")
1434 (rotate:HI (match_operand:HI 1 "register_operand" "")
1435 (match_operand:HI 2 "const_int_operand" "")))]
1439 if (INTVAL (operands[2]) != 8)
1443 (define_insn_and_split "*rotlhi3_8"
1444 [(set (match_operand:HI 0 "register_operand" "=r")
1445 (rotate:HI (match_operand:HI 1 "register_operand" "r")
1448 "mov __tmp_reg__,%A0
1450 mov %B0, __tmp_reg__"
1452 && REGNO (operands[0]) != REGNO (operands[1])"
1453 [(set (match_dup 2) (match_dup 5))
1454 (set (match_dup 3) (match_dup 4))]
1455 "operands[2] = gen_lowpart (QImode, operands[0]);
1456 operands[3] = gen_highpart (QImode, operands[0]);
1458 operands[4] = gen_lowpart (QImode, operands[1]);
1459 operands[5] = gen_highpart (QImode, operands[1]);"
1460 [(set_attr "length" "3")
1461 (set_attr "cc" "none")])
1463 (define_expand "rotlsi3"
1464 [(set (match_operand:SI 0 "register_operand" "")
1465 (rotate:SI (match_operand:SI 1 "register_operand" "")
1466 (match_operand:SI 2 "const_int_operand" "")))]
1470 if (INTVAL (operands[2]) != 8
1471 || INTVAL (operands[2]) != 16
1472 || INTVAL (operands[2]) != 24)
1476 (define_insn_and_split "*rotlsi3_16"
1477 [(set (match_operand:SI 0 "register_operand" "=r")
1478 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1481 "{mov __tmp_reg__,%A0\;mov %A0,%D0\;mov %D0, __tmp_reg__\;mov __tmp_reg__,%B0\;mov %B0,%C0\;mov %C0, __tmp_reg__|movw __tmp_reg__,%A0\;movw %A0,%C0\;movw %C0, __tmp_reg__\;clr __zero_reg__}"
1483 && REGNO (operands[0]) != REGNO (operands[1])"
1484 [(set (match_dup 2) (match_dup 5))
1485 (set (match_dup 3) (match_dup 4))]
1486 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1487 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1489 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1490 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1492 operands[4] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1493 operands[5] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);"
1494 [(set (attr "length") (if_then_else (eq_attr "mcu_have_movw" "yes")
1497 (set (attr "cc") (if_then_else (eq_attr "mcu_have_movw" "yes")
1498 (const_string "clobber")
1499 (const_string "none")))])
1501 (define_insn_and_split "*rotlsi3_8"
1502 [(set (match_operand:SI 0 "register_operand" "=r")
1503 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1506 "mov __tmp_reg__,%D0
1510 mov %A0, __tmp_reg__"
1512 && REGNO (operands[0]) != REGNO (operands[1])"
1513 [(set (match_dup 2) (match_dup 9))
1514 (set (match_dup 3) (match_dup 6))
1515 (set (match_dup 4) (match_dup 7))
1516 (set (match_dup 5) (match_dup 8))]
1517 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1518 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1519 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
1520 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
1522 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1523 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1524 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
1525 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
1526 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
1527 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
1529 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1530 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
1531 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
1532 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
1533 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
1534 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);"
1535 [(set_attr "length" "5")
1536 (set_attr "cc" "none")])
1538 (define_insn_and_split "*rotlsi3_24"
1539 [(set (match_operand:SI 0 "register_operand" "=r")
1540 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1543 "mov __tmp_reg__,%A0
1547 mov %D0, __tmp_reg__"
1549 && REGNO (operands[0]) != REGNO (operands[1])"
1550 [(set (match_dup 2) (match_dup 7))
1551 (set (match_dup 3) (match_dup 8))
1552 (set (match_dup 4) (match_dup 9))
1553 (set (match_dup 5) (match_dup 6))]
1554 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1555 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1556 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
1557 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
1559 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1560 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1561 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
1562 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
1563 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
1564 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
1566 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1567 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
1568 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
1569 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
1570 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
1571 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);"
1572 [(set_attr "length" "5")
1573 (set_attr "cc" "none")])
1575 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1576 ;; arithmetic shift left
1578 (define_expand "ashlqi3"
1579 [(set (match_operand:QI 0 "register_operand" "")
1580 (ashift:QI (match_operand:QI 1 "register_operand" "")
1581 (match_operand:QI 2 "general_operand" "")))]
1585 (define_split ; ashlqi3_const4
1586 [(set (match_operand:QI 0 "d_register_operand" "")
1587 (ashift:QI (match_dup 0)
1590 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1591 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
1594 (define_split ; ashlqi3_const5
1595 [(set (match_operand:QI 0 "d_register_operand" "")
1596 (ashift:QI (match_dup 0)
1599 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1600 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1601 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
1604 (define_split ; ashlqi3_const6
1605 [(set (match_operand:QI 0 "d_register_operand" "")
1606 (ashift:QI (match_dup 0)
1609 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1610 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1611 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
1614 (define_insn "*ashlqi3"
1615 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1616 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1617 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1619 "* return ashlqi3_out (insn, operands, NULL);"
1620 [(set_attr "length" "5,0,1,2,4,6,9")
1621 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1623 (define_insn "ashlhi3"
1624 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1625 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1626 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1628 "* return ashlhi3_out (insn, operands, NULL);"
1629 [(set_attr "length" "6,0,2,2,4,10,10")
1630 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1632 (define_insn "ashlsi3"
1633 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1634 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1635 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1637 "* return ashlsi3_out (insn, operands, NULL);"
1638 [(set_attr "length" "8,0,4,4,8,10,12")
1639 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1641 ;; Optimize if a scratch register from LD_REGS happens to be available.
1643 (define_peephole2 ; ashlqi3_l_const4
1644 [(set (match_operand:QI 0 "l_register_operand" "")
1645 (ashift:QI (match_dup 0)
1647 (match_scratch:QI 1 "d")]
1649 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1650 (set (match_dup 1) (const_int -16))
1651 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1654 (define_peephole2 ; ashlqi3_l_const5
1655 [(set (match_operand:QI 0 "l_register_operand" "")
1656 (ashift:QI (match_dup 0)
1658 (match_scratch:QI 1 "d")]
1660 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1661 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1662 (set (match_dup 1) (const_int -32))
1663 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1666 (define_peephole2 ; ashlqi3_l_const6
1667 [(set (match_operand:QI 0 "l_register_operand" "")
1668 (ashift:QI (match_dup 0)
1670 (match_scratch:QI 1 "d")]
1672 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1673 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1674 (set (match_dup 1) (const_int -64))
1675 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1679 [(match_scratch:QI 3 "d")
1680 (set (match_operand:HI 0 "register_operand" "")
1681 (ashift:HI (match_operand:HI 1 "register_operand" "")
1682 (match_operand:QI 2 "const_int_operand" "")))]
1684 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1685 (clobber (match_dup 3))])]
1688 (define_insn "*ashlhi3_const"
1689 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1690 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1691 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1692 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1694 "* return ashlhi3_out (insn, operands, NULL);"
1695 [(set_attr "length" "0,2,2,4,10")
1696 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
1699 [(match_scratch:QI 3 "d")
1700 (set (match_operand:SI 0 "register_operand" "")
1701 (ashift:SI (match_operand:SI 1 "register_operand" "")
1702 (match_operand:QI 2 "const_int_operand" "")))]
1704 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1705 (clobber (match_dup 3))])]
1708 (define_insn "*ashlsi3_const"
1709 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1710 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1711 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1712 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1714 "* return ashlsi3_out (insn, operands, NULL);"
1715 [(set_attr "length" "0,4,4,10")
1716 (set_attr "cc" "none,set_n,clobber,clobber")])
1718 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1719 ;; arithmetic shift right
1721 (define_insn "ashrqi3"
1722 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1723 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1724 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
1726 "* return ashrqi3_out (insn, operands, NULL);"
1727 [(set_attr "length" "5,0,1,2,5,9")
1728 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
1730 (define_insn "ashrhi3"
1731 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1732 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1733 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1735 "* return ashrhi3_out (insn, operands, NULL);"
1736 [(set_attr "length" "6,0,2,4,4,10,10")
1737 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1739 (define_insn "ashrsi3"
1740 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1741 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1742 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1744 "* return ashrsi3_out (insn, operands, NULL);"
1745 [(set_attr "length" "8,0,4,6,8,10,12")
1746 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1748 ;; Optimize if a scratch register from LD_REGS happens to be available.
1751 [(match_scratch:QI 3 "d")
1752 (set (match_operand:HI 0 "register_operand" "")
1753 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1754 (match_operand:QI 2 "const_int_operand" "")))]
1756 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1757 (clobber (match_dup 3))])]
1760 (define_insn "*ashrhi3_const"
1761 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1762 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1763 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1764 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1766 "* return ashrhi3_out (insn, operands, NULL);"
1767 [(set_attr "length" "0,2,4,4,10")
1768 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
1771 [(match_scratch:QI 3 "d")
1772 (set (match_operand:SI 0 "register_operand" "")
1773 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1774 (match_operand:QI 2 "const_int_operand" "")))]
1776 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1777 (clobber (match_dup 3))])]
1780 (define_insn "*ashrsi3_const"
1781 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1782 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1783 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1784 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1786 "* return ashrsi3_out (insn, operands, NULL);"
1787 [(set_attr "length" "0,4,4,10")
1788 (set_attr "cc" "none,clobber,set_n,clobber")])
1790 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1791 ;; logical shift right
1793 (define_expand "lshrqi3"
1794 [(set (match_operand:QI 0 "register_operand" "")
1795 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1796 (match_operand:QI 2 "general_operand" "")))]
1800 (define_split ; lshrqi3_const4
1801 [(set (match_operand:QI 0 "d_register_operand" "")
1802 (lshiftrt:QI (match_dup 0)
1805 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1806 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
1809 (define_split ; lshrqi3_const5
1810 [(set (match_operand:QI 0 "d_register_operand" "")
1811 (lshiftrt:QI (match_dup 0)
1814 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1815 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1816 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
1819 (define_split ; lshrqi3_const6
1820 [(set (match_operand:QI 0 "d_register_operand" "")
1821 (lshiftrt:QI (match_dup 0)
1824 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1825 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1826 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
1829 (define_insn "*lshrqi3"
1830 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1831 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1832 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1834 "* return lshrqi3_out (insn, operands, NULL);"
1835 [(set_attr "length" "5,0,1,2,4,6,9")
1836 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1838 (define_insn "lshrhi3"
1839 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1840 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1841 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1843 "* return lshrhi3_out (insn, operands, NULL);"
1844 [(set_attr "length" "6,0,2,2,4,10,10")
1845 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1847 (define_insn "lshrsi3"
1848 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1849 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1850 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1852 "* return lshrsi3_out (insn, operands, NULL);"
1853 [(set_attr "length" "8,0,4,4,8,10,12")
1854 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1856 ;; Optimize if a scratch register from LD_REGS happens to be available.
1858 (define_peephole2 ; lshrqi3_l_const4
1859 [(set (match_operand:QI 0 "l_register_operand" "")
1860 (lshiftrt:QI (match_dup 0)
1862 (match_scratch:QI 1 "d")]
1864 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1865 (set (match_dup 1) (const_int 15))
1866 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1869 (define_peephole2 ; lshrqi3_l_const5
1870 [(set (match_operand:QI 0 "l_register_operand" "")
1871 (lshiftrt:QI (match_dup 0)
1873 (match_scratch:QI 1 "d")]
1875 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1876 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1877 (set (match_dup 1) (const_int 7))
1878 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1881 (define_peephole2 ; lshrqi3_l_const6
1882 [(set (match_operand:QI 0 "l_register_operand" "")
1883 (lshiftrt:QI (match_dup 0)
1885 (match_scratch:QI 1 "d")]
1887 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1888 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1889 (set (match_dup 1) (const_int 3))
1890 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1894 [(match_scratch:QI 3 "d")
1895 (set (match_operand:HI 0 "register_operand" "")
1896 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1897 (match_operand:QI 2 "const_int_operand" "")))]
1899 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1900 (clobber (match_dup 3))])]
1903 (define_insn "*lshrhi3_const"
1904 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1905 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1906 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1907 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1909 "* return lshrhi3_out (insn, operands, NULL);"
1910 [(set_attr "length" "0,2,2,4,10")
1911 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
1914 [(match_scratch:QI 3 "d")
1915 (set (match_operand:SI 0 "register_operand" "")
1916 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1917 (match_operand:QI 2 "const_int_operand" "")))]
1919 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1920 (clobber (match_dup 3))])]
1923 (define_insn "*lshrsi3_const"
1924 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1925 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1926 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1927 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1929 "* return lshrsi3_out (insn, operands, NULL);"
1930 [(set_attr "length" "0,4,4,10")
1931 (set_attr "cc" "none,clobber,clobber,clobber")])
1933 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
1936 (define_insn "absqi2"
1937 [(set (match_operand:QI 0 "register_operand" "=r")
1938 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
1942 [(set_attr "length" "2")
1943 (set_attr "cc" "clobber")])
1946 (define_insn "abssf2"
1947 [(set (match_operand:SF 0 "register_operand" "=d,r")
1948 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
1953 [(set_attr "length" "1,2")
1954 (set_attr "cc" "set_n,clobber")])
1956 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
1959 (define_insn "negqi2"
1960 [(set (match_operand:QI 0 "register_operand" "=r")
1961 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1964 [(set_attr "length" "1")
1965 (set_attr "cc" "set_zn")])
1967 (define_insn "neghi2"
1968 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
1969 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
1972 com %B0\;neg %A0\;sbci %B0,lo8(-1)
1973 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
1974 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
1975 [(set_attr "length" "3,4,4")
1976 (set_attr "cc" "set_czn,set_n,set_czn")])
1978 (define_insn "negsi2"
1979 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
1980 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
1983 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
1984 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
1985 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
1986 [(set_attr_alternative "length"
1989 (if_then_else (eq_attr "mcu_have_movw" "yes")
1992 (set_attr "cc" "set_czn,set_n,set_czn")])
1994 (define_insn "negsf2"
1995 [(set (match_operand:SF 0 "register_operand" "=d,r")
1996 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
2000 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
2001 [(set_attr "length" "1,4")
2002 (set_attr "cc" "set_n,set_n")])
2004 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2007 (define_insn "one_cmplqi2"
2008 [(set (match_operand:QI 0 "register_operand" "=r")
2009 (not:QI (match_operand:QI 1 "register_operand" "0")))]
2012 [(set_attr "length" "1")
2013 (set_attr "cc" "set_czn")])
2015 (define_insn "one_cmplhi2"
2016 [(set (match_operand:HI 0 "register_operand" "=r")
2017 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2021 [(set_attr "length" "2")
2022 (set_attr "cc" "set_n")])
2024 (define_insn "one_cmplsi2"
2025 [(set (match_operand:SI 0 "register_operand" "=r")
2026 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2032 [(set_attr "length" "4")
2033 (set_attr "cc" "set_n")])
2035 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2038 (define_insn "extendqihi2"
2039 [(set (match_operand:HI 0 "register_operand" "=r,r")
2040 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
2043 clr %B0\;sbrc %0,7\;com %B0
2044 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
2045 [(set_attr "length" "3,4")
2046 (set_attr "cc" "set_n,set_n")])
2048 (define_insn "extendqisi2"
2049 [(set (match_operand:SI 0 "register_operand" "=r,r")
2050 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
2053 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
2054 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
2055 [(set_attr "length" "5,6")
2056 (set_attr "cc" "set_n,set_n")])
2058 (define_insn "extendhisi2"
2059 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2060 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
2063 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
2064 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
2065 [(set_attr_alternative "length"
2067 (if_then_else (eq_attr "mcu_have_movw" "yes")
2070 (set_attr "cc" "set_n,set_n")])
2072 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2075 (define_insn_and_split "zero_extendqihi2"
2076 [(set (match_operand:HI 0 "register_operand" "=r")
2077 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2081 [(set (match_dup 2) (match_dup 1))
2082 (set (match_dup 3) (const_int 0))]
2083 "unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
2084 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
2086 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
2087 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
2090 (define_insn_and_split "zero_extendqisi2"
2091 [(set (match_operand:SI 0 "register_operand" "=r")
2092 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2096 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
2097 (set (match_dup 3) (const_int 0))]
2098 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2099 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2101 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2102 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2105 (define_insn_and_split "zero_extendhisi2"
2106 [(set (match_operand:SI 0 "register_operand" "=r")
2107 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2111 [(set (match_dup 2) (match_dup 1))
2112 (set (match_dup 3) (const_int 0))]
2113 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2114 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2116 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2117 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2120 (define_insn_and_split "zero_extendqidi2"
2121 [(set (match_operand:DI 0 "register_operand" "=r")
2122 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
2126 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2127 (set (match_dup 3) (const_int 0))]
2128 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2129 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2131 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2132 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2135 (define_insn_and_split "zero_extendhidi2"
2136 [(set (match_operand:DI 0 "register_operand" "=r")
2137 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
2141 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2142 (set (match_dup 3) (const_int 0))]
2143 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2144 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2146 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2147 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2150 (define_insn_and_split "zero_extendsidi2"
2151 [(set (match_operand:DI 0 "register_operand" "=r")
2152 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
2156 [(set (match_dup 2) (match_dup 1))
2157 (set (match_dup 3) (const_int 0))]
2158 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2159 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2161 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2162 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2165 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2168 (define_insn "tstqi"
2170 (match_operand:QI 0 "register_operand" "r"))]
2173 [(set_attr "cc" "compare")
2174 (set_attr "length" "1")])
2176 (define_insn "*reversed_tstqi"
2178 (compare (const_int 0)
2179 (match_operand:QI 0 "register_operand" "r")))]
2181 "cp __zero_reg__,%0"
2182 [(set_attr "cc" "compare")
2183 (set_attr "length" "1")])
2185 (define_insn "tsthi"
2187 (match_operand:HI 0 "register_operand" "!w,r"))]
2189 "* return out_tsthi (insn,NULL);"
2190 [(set_attr "cc" "compare,compare")
2191 (set_attr "length" "1,2")])
2193 (define_insn "*reversed_tsthi"
2195 (compare (const_int 0)
2196 (match_operand:HI 0 "register_operand" "r")))]
2198 "cp __zero_reg__,%A0
2199 cpc __zero_reg__,%B0"
2200 [(set_attr "cc" "compare")
2201 (set_attr "length" "2")])
2203 (define_insn "tstsi"
2205 (match_operand:SI 0 "register_operand" "r"))]
2207 "* return out_tstsi (insn,NULL);"
2208 [(set_attr "cc" "compare")
2209 (set_attr "length" "4")])
2211 (define_insn "*reversed_tstsi"
2213 (compare (const_int 0)
2214 (match_operand:SI 0 "register_operand" "r")))]
2216 "cp __zero_reg__,%A0
2217 cpc __zero_reg__,%B0
2218 cpc __zero_reg__,%C0
2219 cpc __zero_reg__,%D0"
2220 [(set_attr "cc" "compare")
2221 (set_attr "length" "4")])
2224 (define_insn "cmpqi"
2226 (compare (match_operand:QI 0 "register_operand" "r,d")
2227 (match_operand:QI 1 "nonmemory_operand" "r,i")))]
2232 [(set_attr "cc" "compare,compare")
2233 (set_attr "length" "1,1")])
2235 (define_insn "*cmpqi_sign_extend"
2237 (compare (sign_extend:HI
2238 (match_operand:QI 0 "register_operand" "d"))
2239 (match_operand:HI 1 "const_int_operand" "n")))]
2240 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2242 [(set_attr "cc" "compare")
2243 (set_attr "length" "1")])
2245 (define_insn "cmphi"
2247 (compare (match_operand:HI 0 "register_operand" "r,d,d,r,r")
2248 (match_operand:HI 1 "nonmemory_operand" "r,M,i,M,i")))
2249 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
2252 switch (which_alternative)
2255 return (AS2 (cp,%A0,%A1) CR_TAB
2258 if (reg_unused_after (insn, operands[0])
2259 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2260 && test_hard_reg_class (ADDW_REGS, operands[0]))
2261 return AS2 (sbiw,%0,%1);
2263 return (AS2 (cpi,%0,%1) CR_TAB
2264 AS2 (cpc,%B0,__zero_reg__));
2266 if (reg_unused_after (insn, operands[0]))
2267 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2268 AS2 (sbci,%B0,hi8(%1)));
2270 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2271 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2274 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2275 AS2 (cp, %A0,%2) CR_TAB
2276 AS2 (cpc, %B0,__zero_reg__));
2279 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2280 AS2 (cp, %A0,%2) CR_TAB
2281 AS2 (ldi, %2,hi8(%1)) CR_TAB
2286 [(set_attr "cc" "compare,compare,compare,compare,compare")
2287 (set_attr "length" "2,2,3,3,4")])
2290 (define_insn "cmpsi"
2292 (compare (match_operand:SI 0 "register_operand" "r,d,d,r,r")
2293 (match_operand:SI 1 "nonmemory_operand" "r,M,i,M,i")))
2294 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
2297 switch (which_alternative)
2300 return (AS2 (cp,%A0,%A1) CR_TAB
2301 AS2 (cpc,%B0,%B1) CR_TAB
2302 AS2 (cpc,%C0,%C1) CR_TAB
2305 if (reg_unused_after (insn, operands[0])
2306 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2307 && test_hard_reg_class (ADDW_REGS, operands[0]))
2308 return (AS2 (sbiw,%0,%1) CR_TAB
2309 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2310 AS2 (cpc,%D0,__zero_reg__));
2312 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2313 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2314 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2315 AS2 (cpc,%D0,__zero_reg__));
2317 if (reg_unused_after (insn, operands[0]))
2318 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2319 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2320 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2321 AS2 (sbci,%D0,hhi8(%1)));
2323 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
2324 AS2 (ldi, %2,hi8(%1)) CR_TAB
2325 AS2 (cpc, %B0,%2) CR_TAB
2326 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2327 AS2 (cpc, %C0,%2) CR_TAB
2328 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2331 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2332 AS2 (cp,%A0,%2) CR_TAB
2333 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2334 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2335 AS2 (cpc,%D0,__zero_reg__));
2337 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2338 AS2 (cp, %A0,%2) CR_TAB
2339 AS2 (ldi, %2,hi8(%1)) CR_TAB
2340 AS2 (cpc, %B0,%2) CR_TAB
2341 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2342 AS2 (cpc, %C0,%2) CR_TAB
2343 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2348 [(set_attr "cc" "compare,compare,compare,compare,compare")
2349 (set_attr "length" "4,4,7,5,8")])
2351 ; Optimize negated tests into reverse compare if overflow is undefined.
2352 (define_insn_and_split "negated_tst<mode>"
2354 (neg:QISI (match_operand:QISI 0 "register_operand")))]
2356 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2360 (compare (const_int 0)
2364 ;; ----------------------------------------------------------------------
2365 ;; JUMP INSTRUCTIONS
2366 ;; ----------------------------------------------------------------------
2367 ;; Conditional jump instructions
2369 (define_expand "beq"
2371 (if_then_else (eq (cc0) (const_int 0))
2372 (label_ref (match_operand 0 "" ""))
2377 (define_expand "bne"
2379 (if_then_else (ne (cc0) (const_int 0))
2380 (label_ref (match_operand 0 "" ""))
2385 (define_expand "bge"
2387 (if_then_else (ge (cc0) (const_int 0))
2388 (label_ref (match_operand 0 "" ""))
2393 (define_expand "bgeu"
2395 (if_then_else (geu (cc0) (const_int 0))
2396 (label_ref (match_operand 0 "" ""))
2401 (define_expand "blt"
2403 (if_then_else (lt (cc0) (const_int 0))
2404 (label_ref (match_operand 0 "" ""))
2409 (define_expand "bltu"
2411 (if_then_else (ltu (cc0) (const_int 0))
2412 (label_ref (match_operand 0 "" ""))
2419 /****************************************************************
2420 AVR not have following conditional jumps: LE,LEU,GT,GTU.
2421 Convert them all to proper jumps.
2422 *****************************************************************/
2424 (define_expand "ble"
2426 (if_then_else (le (cc0) (const_int 0))
2427 (label_ref (match_operand 0 "" ""))
2432 (define_expand "bleu"
2434 (if_then_else (leu (cc0) (const_int 0))
2435 (label_ref (match_operand 0 "" ""))
2440 (define_expand "bgt"
2442 (if_then_else (gt (cc0) (const_int 0))
2443 (label_ref (match_operand 0 "" ""))
2448 (define_expand "bgtu"
2450 (if_then_else (gtu (cc0) (const_int 0))
2451 (label_ref (match_operand 0 "" ""))
2456 ;; Test a single bit in a QI/HI/SImode register.
2457 (define_insn "*sbrx_branch"
2460 (match_operator 0 "eqne_operator"
2462 (match_operand:QI 1 "register_operand" "r")
2464 (match_operand 2 "const_int_operand" "n"))
2466 (label_ref (match_operand 3 "" ""))
2469 "* return avr_out_sbxx_branch (insn, operands);"
2470 [(set (attr "length")
2471 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2472 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2474 (if_then_else (eq_attr "mcu_mega" "no")
2477 (set_attr "cc" "clobber")])
2479 (define_insn "*sbrx_and_branchhi"
2482 (match_operator 0 "eqne_operator"
2484 (match_operand:HI 1 "register_operand" "r")
2485 (match_operand:HI 2 "single_one_operand" "n"))
2487 (label_ref (match_operand 3 "" ""))
2490 "* return avr_out_sbxx_branch (insn, operands);"
2491 [(set (attr "length")
2492 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2493 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2495 (if_then_else (eq_attr "mcu_mega" "no")
2498 (set_attr "cc" "clobber")])
2500 (define_insn "*sbrx_and_branchsi"
2503 (match_operator 0 "eqne_operator"
2505 (match_operand:SI 1 "register_operand" "r")
2506 (match_operand:SI 2 "single_one_operand" "n"))
2508 (label_ref (match_operand 3 "" ""))
2511 "* return avr_out_sbxx_branch (insn, operands);"
2512 [(set (attr "length")
2513 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2514 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2516 (if_then_else (eq_attr "mcu_mega" "no")
2519 (set_attr "cc" "clobber")])
2521 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2523 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
2524 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2525 (label_ref (match_operand 1 "" ""))
2528 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2532 (label_ref (match_dup 1))
2537 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
2538 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2539 (label_ref (match_operand 1 "" ""))
2542 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2546 (label_ref (match_dup 1))
2551 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
2552 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2553 (label_ref (match_operand 1 "" ""))
2556 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2558 (label_ref (match_dup 1))
2563 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
2564 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2565 (label_ref (match_operand 1 "" ""))
2568 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2570 (label_ref (match_dup 1))
2575 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
2576 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2577 (label_ref (match_operand 1 "" ""))
2580 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2582 (label_ref (match_dup 1))
2584 "operands[2] = GEN_INT (-2147483647 - 1);")
2587 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
2588 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2589 (label_ref (match_operand 1 "" ""))
2592 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2594 (label_ref (match_dup 1))
2596 "operands[2] = GEN_INT (-2147483647 - 1);")
2598 ;; ************************************************************************
2599 ;; Implementation of conditional jumps here.
2600 ;; Compare with 0 (test) jumps
2601 ;; ************************************************************************
2603 (define_insn "branch"
2605 (if_then_else (match_operator 1 "simple_comparison_operator"
2608 (label_ref (match_operand 0 "" ""))
2612 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2613 [(set_attr "type" "branch")
2614 (set_attr "cc" "clobber")])
2616 (define_insn "difficult_branch"
2618 (if_then_else (match_operator 1 "difficult_comparison_operator"
2621 (label_ref (match_operand 0 "" ""))
2625 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2626 [(set_attr "type" "branch1")
2627 (set_attr "cc" "clobber")])
2631 (define_insn "rvbranch"
2633 (if_then_else (match_operator 1 "simple_comparison_operator"
2637 (label_ref (match_operand 0 "" ""))))]
2640 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2641 [(set_attr "type" "branch1")
2642 (set_attr "cc" "clobber")])
2644 (define_insn "difficult_rvbranch"
2646 (if_then_else (match_operator 1 "difficult_comparison_operator"
2650 (label_ref (match_operand 0 "" ""))))]
2653 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2654 [(set_attr "type" "branch")
2655 (set_attr "cc" "clobber")])
2657 ;; **************************************************************************
2658 ;; Unconditional and other jump instructions.
2662 (label_ref (match_operand 0 "" "")))]
2665 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2666 return AS1 (jmp,%0);
2667 return AS1 (rjmp,%0);
2669 [(set (attr "length")
2670 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2671 (if_then_else (eq_attr "mcu_mega" "no")
2674 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
2675 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2678 (set_attr "cc" "none")])
2682 (define_expand "call"
2683 [(call (match_operand:HI 0 "call_insn_operand" "")
2684 (match_operand:HI 1 "general_operand" ""))]
2685 ;; Operand 1 not used on the AVR.
2691 (define_expand "call_value"
2692 [(set (match_operand 0 "register_operand" "")
2693 (call (match_operand:HI 1 "call_insn_operand" "")
2694 (match_operand:HI 2 "general_operand" "")))]
2695 ;; Operand 2 not used on the AVR.
2699 (define_insn "call_insn"
2700 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
2701 (match_operand:HI 1 "general_operand" "X,X,X,X"))]
2702 ;; We don't need in saving Z register because r30,r31 is a call used registers
2703 ;; Operand 1 not used on the AVR.
2704 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
2706 if (which_alternative==0)
2708 else if (which_alternative==1)
2711 return (AS2 (movw, r30, %0) CR_TAB
2714 return (AS2 (mov, r30, %A0) CR_TAB
2715 AS2 (mov, r31, %B0) CR_TAB
2718 else if (which_alternative==2)
2719 return AS1(%~call,%c0);
2720 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
2721 AS2 (ldi,r31,hi8(%0)) CR_TAB
2724 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2725 (set_attr_alternative "length"
2727 (if_then_else (eq_attr "mcu_have_movw" "yes")
2730 (if_then_else (eq_attr "mcu_mega" "yes")
2735 (define_insn "call_value_insn"
2736 [(set (match_operand 0 "register_operand" "=r,r,r,r")
2737 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
2738 ;; We don't need in saving Z register because r30,r31 is a call used registers
2739 (match_operand:HI 2 "general_operand" "X,X,X,X")))]
2740 ;; Operand 2 not used on the AVR.
2741 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
2743 if (which_alternative==0)
2745 else if (which_alternative==1)
2748 return (AS2 (movw, r30, %1) CR_TAB
2751 return (AS2 (mov, r30, %A1) CR_TAB
2752 AS2 (mov, r31, %B1) CR_TAB
2755 else if (which_alternative==2)
2756 return AS1(%~call,%c1);
2757 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
2758 AS2 (ldi, r31, hi8(%1)) CR_TAB
2761 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2762 (set_attr_alternative "length"
2764 (if_then_else (eq_attr "mcu_have_movw" "yes")
2767 (if_then_else (eq_attr "mcu_mega" "yes")
2776 [(set_attr "cc" "none")
2777 (set_attr "length" "1")])
2780 (define_insn "indirect_jump"
2781 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2782 "!AVR_HAVE_EIJMP_EICALL"
2785 push %A0\;push %B0\;ret"
2786 [(set_attr "length" "1,3")
2787 (set_attr "cc" "none,none")])
2789 (define_insn "*indirect_jump_avr6"
2790 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
2791 "AVR_HAVE_EIJMP_EICALL"
2793 [(set_attr "length" "1")
2794 (set_attr "cc" "none")])
2798 ;; Table made from "rjmp" instructions for <=8K devices.
2799 (define_insn "*tablejump_rjmp"
2800 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
2802 (use (label_ref (match_operand 1 "" "")))
2803 (clobber (match_dup 0))]
2804 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
2807 push %A0\;push %B0\;ret"
2808 [(set_attr "length" "1,3")
2809 (set_attr "cc" "none,none")])
2811 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2812 (define_insn "*tablejump_lib"
2813 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2815 (use (label_ref (match_operand 1 "" "")))
2816 (clobber (match_dup 0))]
2817 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2818 "jmp __tablejump2__"
2819 [(set_attr "length" "2")
2820 (set_attr "cc" "clobber")])
2822 (define_insn "*tablejump_enh"
2823 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2825 (use (label_ref (match_operand 1 "" "")))
2826 (clobber (match_dup 0))]
2827 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
2834 [(set_attr "length" "6")
2835 (set_attr "cc" "clobber")])
2837 (define_insn "*tablejump"
2838 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2840 (use (label_ref (match_operand 1 "" "")))
2841 (clobber (match_dup 0))]
2842 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
2851 [(set_attr "length" "8")
2852 (set_attr "cc" "clobber")])
2854 (define_expand "casesi"
2856 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2857 (match_operand:HI 1 "register_operand" "")))
2858 (parallel [(set (cc0)
2859 (compare (match_dup 6)
2860 (match_operand:HI 2 "register_operand" "")))
2861 (clobber (match_scratch:QI 9 ""))])
2864 (if_then_else (gtu (cc0)
2866 (label_ref (match_operand 4 "" ""))
2870 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2872 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
2873 (use (label_ref (match_dup 3)))
2874 (clobber (match_dup 6))])]
2878 operands[6] = gen_reg_rtx (HImode);
2882 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2883 ;; This instruction sets Z flag
2886 [(set (cc0) (const_int 0))]
2889 [(set_attr "length" "1")
2890 (set_attr "cc" "compare")])
2892 ;; Clear/set/test a single bit in I/O address space.
2895 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2896 (and:QI (mem:QI (match_dup 0))
2897 (match_operand:QI 1 "single_zero_operand" "n")))]
2900 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2901 return AS2 (cbi,%0-0x20,%2);
2903 [(set_attr "length" "1")
2904 (set_attr "cc" "none")])
2907 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2908 (ior:QI (mem:QI (match_dup 0))
2909 (match_operand:QI 1 "single_one_operand" "n")))]
2912 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2913 return AS2 (sbi,%0-0x20,%2);
2915 [(set_attr "length" "1")
2916 (set_attr "cc" "none")])
2918 ;; Lower half of the I/O space - use sbic/sbis directly.
2919 (define_insn "*sbix_branch"
2922 (match_operator 0 "eqne_operator"
2924 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
2926 (match_operand 2 "const_int_operand" "n"))
2928 (label_ref (match_operand 3 "" ""))
2931 "* return avr_out_sbxx_branch (insn, operands);"
2932 [(set (attr "length")
2933 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2934 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2936 (if_then_else (eq_attr "mcu_mega" "no")
2939 (set_attr "cc" "clobber")])
2941 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
2942 (define_insn "*sbix_branch_bit7"
2945 (match_operator 0 "gelt_operator"
2946 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
2948 (label_ref (match_operand 2 "" ""))
2952 operands[3] = operands[2];
2953 operands[2] = GEN_INT (7);
2954 return avr_out_sbxx_branch (insn, operands);
2956 [(set (attr "length")
2957 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2958 (le (minus (pc) (match_dup 2)) (const_int 2046)))
2960 (if_then_else (eq_attr "mcu_mega" "no")
2963 (set_attr "cc" "clobber")])
2965 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
2966 (define_insn "*sbix_branch_tmp"
2969 (match_operator 0 "eqne_operator"
2971 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
2973 (match_operand 2 "const_int_operand" "n"))
2975 (label_ref (match_operand 3 "" ""))
2978 "* return avr_out_sbxx_branch (insn, operands);"
2979 [(set (attr "length")
2980 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2981 (le (minus (pc) (match_dup 3)) (const_int 2045)))
2983 (if_then_else (eq_attr "mcu_mega" "no")
2986 (set_attr "cc" "clobber")])
2988 (define_insn "*sbix_branch_tmp_bit7"
2991 (match_operator 0 "gelt_operator"
2992 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
2994 (label_ref (match_operand 2 "" ""))
2998 operands[3] = operands[2];
2999 operands[2] = GEN_INT (7);
3000 return avr_out_sbxx_branch (insn, operands);
3002 [(set (attr "length")
3003 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
3004 (le (minus (pc) (match_dup 2)) (const_int 2045)))
3006 (if_then_else (eq_attr "mcu_mega" "no")
3009 (set_attr "cc" "clobber")])
3011 ;; ************************* Peepholes ********************************
3014 [(set (match_operand:SI 0 "d_register_operand" "")
3015 (plus:SI (match_dup 0)
3019 (compare (match_dup 0)
3021 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3023 (if_then_else (ne (cc0) (const_int 0))
3024 (label_ref (match_operand 2 "" ""))
3030 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3031 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
3032 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3033 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3035 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3036 AS2 (sbc,%B0,__zero_reg__) CR_TAB
3037 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3038 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3039 switch (avr_jump_mode (operands[2],insn))
3042 return AS1 (brcc,%2);
3044 return (AS1 (brcs,.+2) CR_TAB
3047 return (AS1 (brcs,.+4) CR_TAB
3052 [(set (match_operand:HI 0 "d_register_operand" "")
3053 (plus:HI (match_dup 0)
3057 (compare (match_dup 0)
3059 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3061 (if_then_else (ne (cc0) (const_int 0))
3062 (label_ref (match_operand 2 "" ""))
3068 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3069 output_asm_insn (AS2 (sbiw,%0,1), operands);
3071 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3072 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
3073 switch (avr_jump_mode (operands[2],insn))
3076 return AS1 (brcc,%2);
3078 return (AS1 (brcs,.+2) CR_TAB
3081 return (AS1 (brcs,.+4) CR_TAB
3086 [(set (match_operand:QI 0 "d_register_operand" "")
3087 (plus:QI (match_dup 0)
3090 (compare (match_dup 0)
3093 (if_then_else (ne (cc0) (const_int 0))
3094 (label_ref (match_operand 1 "" ""))
3100 cc_status.value1 = operands[0];
3101 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
3102 output_asm_insn (AS2 (subi,%A0,1), operands);
3103 switch (avr_jump_mode (operands[1],insn))
3106 return AS1 (brcc,%1);
3108 return (AS1 (brcs,.+2) CR_TAB
3111 return (AS1 (brcs,.+4) CR_TAB
3116 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
3118 (if_then_else (eq (cc0) (const_int 0))
3119 (label_ref (match_operand 1 "" ""))
3121 "jump_over_one_insn_p (insn, operands[1])"
3122 "cpse %0,__zero_reg__")
3126 (compare (match_operand:QI 0 "register_operand" "")
3127 (match_operand:QI 1 "register_operand" "")))
3129 (if_then_else (eq (cc0) (const_int 0))
3130 (label_ref (match_operand 2 "" ""))
3132 "jump_over_one_insn_p (insn, operands[2])"
3135 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
3136 ;;prologue/epilogue support instructions
3138 (define_insn "popqi"
3139 [(set (match_operand:QI 0 "register_operand" "=r")
3140 (mem:QI (post_inc (reg:HI REG_SP))))]
3143 [(set_attr "cc" "none")
3144 (set_attr "length" "1")])
3146 (define_insn "pophi"
3147 [(set (match_operand:HI 0 "register_operand" "=r")
3148 (mem:HI (post_inc (reg:HI REG_SP))))]
3151 [(set_attr "cc" "none")
3152 (set_attr "length" "2")])
3154 ;; Enable Interrupts
3155 (define_insn "enable_interrupt"
3156 [(unspec [(const_int 0)] UNSPEC_SEI)]
3159 [(set_attr "length" "1")
3160 (set_attr "cc" "none")
3163 ;; Disable Interrupts
3164 (define_insn "disable_interrupt"
3165 [(unspec [(const_int 0)] UNSPEC_CLI)]
3168 [(set_attr "length" "1")
3169 (set_attr "cc" "none")
3172 ;; Library prologue saves
3173 (define_insn "call_prologue_saves"
3174 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
3175 (match_operand:HI 0 "immediate_operand" "")
3176 (set (reg:HI REG_SP) (minus:HI
3178 (match_operand:HI 1 "immediate_operand" "")))
3179 (use (reg:HI REG_X))
3180 (clobber (reg:HI REG_Z))]
3182 "ldi r30,lo8(gs(1f))
3184 %~jmp __prologue_saves__+((18 - %0) * 2)
3186 [(set_attr_alternative "length"
3187 [(if_then_else (eq_attr "mcu_mega" "yes")
3190 (set_attr "cc" "clobber")
3193 ; epilogue restores using library
3194 (define_insn "epilogue_restores"
3195 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
3196 (set (reg:HI REG_Y ) (plus:HI
3198 (match_operand:HI 0 "immediate_operand" "")))
3199 (set (reg:HI REG_SP) (reg:HI REG_Y))
3200 (clobber (reg:QI REG_Z))]
3203 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
3204 [(set_attr_alternative "length"
3205 [(if_then_else (eq_attr "mcu_mega" "yes")
3208 (set_attr "cc" "clobber")
3212 (define_insn "return"
3214 "reload_completed && avr_simple_epilogue ()"
3216 [(set_attr "cc" "none")
3217 (set_attr "length" "1")])
3219 (define_insn "return_from_epilogue"
3223 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
3224 && !cfun->machine->is_naked)"
3226 [(set_attr "cc" "none")
3227 (set_attr "length" "1")])
3229 (define_insn "return_from_interrupt_epilogue"
3233 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
3234 && !cfun->machine->is_naked)"
3236 [(set_attr "cc" "none")
3237 (set_attr "length" "1")])
3239 (define_insn "return_from_naked_epilogue"
3243 && cfun->machine->is_naked)"
3245 [(set_attr "cc" "none")
3246 (set_attr "length" "0")])
3248 (define_expand "prologue"
3257 (define_expand "epilogue"