1 ;; -*- Mode: Scheme -*-
2 ;; Machine description for GNU compiler,
3 ;; for ATMEL AVR micro controllers.
4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
5 ;; 2009 Free Software Foundation, Inc.
6 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; Special characters after '%':
25 ;; A No effect (add 0).
26 ;; B Add 1 to REG number, MEM address or CONST_INT.
29 ;; j Branch condition.
30 ;; k Reverse branch condition.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
34 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
35 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
38 ;; 0 Length of a string, see "strlenhi".
39 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
47 (TMP_REGNO 0) ; temporary register r0
48 (ZERO_REGNO 1) ; zero register r1
58 (UNSPECV_PROLOGUE_SAVES 0)
59 (UNSPECV_EPILOGUE_RESTORES 1)
60 (UNSPECV_WRITE_SP_IRQ_ON 2)
61 (UNSPECV_WRITE_SP_IRQ_OFF 3)
62 (UNSPECV_GOTO_RECEIVER 4)])
64 (include "predicates.md")
65 (include "constraints.md")
67 ;; Condition code settings.
68 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
69 (const_string "none"))
71 (define_attr "type" "branch,branch1,arith,xcall"
72 (const_string "arith"))
74 (define_attr "mcu_have_movw" "yes,no"
75 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
77 (const_string "no"))))
79 (define_attr "mcu_mega" "yes,no"
80 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
82 (const_string "no"))))
85 ;; The size of instructions in bytes.
86 ;; XXX may depend from "cc"
88 (define_attr "length" ""
89 (cond [(eq_attr "type" "branch")
90 (if_then_else (and (ge (minus (pc) (match_dup 0))
92 (le (minus (pc) (match_dup 0))
95 (if_then_else (and (ge (minus (pc) (match_dup 0))
97 (le (minus (pc) (match_dup 0))
101 (eq_attr "type" "branch1")
102 (if_then_else (and (ge (minus (pc) (match_dup 0))
104 (le (minus (pc) (match_dup 0))
107 (if_then_else (and (ge (minus (pc) (match_dup 0))
109 (le (minus (pc) (match_dup 0))
113 (eq_attr "type" "xcall")
114 (if_then_else (eq_attr "mcu_mega" "no")
119 ;; Define mode iterator
120 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
122 ;;========================================================================
123 ;; The following is used by nonlocal_goto and setjmp.
124 ;; The receiver pattern will create no instructions since internally
125 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
126 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
127 ;; The 'null' receiver also avoids problems with optimisation
128 ;; not recognising incoming jmp and removing code that resets frame_pointer.
129 ;; The code derived from builtins.c.
131 (define_expand "nonlocal_goto_receiver"
133 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
136 emit_move_insn (virtual_stack_vars_rtx,
137 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
138 gen_int_mode (STARTING_FRAME_OFFSET,
140 /* This might change the hard frame pointer in ways that aren't
141 apparent to early optimization passes, so force a clobber. */
142 emit_clobber (hard_frame_pointer_rtx);
147 ;; Defining nonlocal_goto_receiver means we must also define this.
148 ;; even though its function is identical to that in builtins.c
150 (define_expand "nonlocal_goto"
152 (use (match_operand 0 "general_operand"))
153 (use (match_operand 1 "general_operand"))
154 (use (match_operand 2 "general_operand"))
155 (use (match_operand 3 "general_operand"))
159 rtx r_label = copy_to_reg (operands[1]);
160 rtx r_fp = operands[3];
161 rtx r_sp = operands[2];
163 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
165 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
167 emit_move_insn (hard_frame_pointer_rtx, r_fp);
168 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
170 emit_use (hard_frame_pointer_rtx);
171 emit_use (stack_pointer_rtx);
173 emit_indirect_jump (r_label);
179 (define_insn "*pushqi"
180 [(set (mem:QI (post_dec (reg:HI REG_SP)))
181 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
186 [(set_attr "length" "1,1")])
189 (define_insn "*pushhi"
190 [(set (mem:HI (post_dec (reg:HI REG_SP)))
191 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
195 push __zero_reg__\;push __zero_reg__"
196 [(set_attr "length" "2,2")])
198 (define_insn "*pushsi"
199 [(set (mem:SI (post_dec (reg:HI REG_SP)))
200 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
203 push %D0\;push %C0\;push %B0\;push %A0
204 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
205 [(set_attr "length" "4,4")])
207 (define_insn "*pushsf"
208 [(set (mem:SF (post_dec (reg:HI REG_SP)))
209 (match_operand:SF 0 "register_operand" "r"))]
215 [(set_attr "length" "4")])
217 ;;========================================================================
219 ;; The last alternative (any immediate constant to any register) is
220 ;; very expensive. It should be optimized by peephole2 if a scratch
221 ;; register is available, but then that register could just as well be
222 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
223 ;; are call-saved registers, and most of LD_REGS are call-used registers,
224 ;; so this may still be a win for registers live across function calls.
226 (define_expand "movqi"
227 [(set (match_operand:QI 0 "nonimmediate_operand" "")
228 (match_operand:QI 1 "general_operand" ""))]
230 "/* One of the ops has to be in a register. */
231 if (!register_operand(operand0, QImode)
232 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
233 operands[1] = copy_to_mode_reg(QImode, operand1);
236 (define_insn "*movqi"
237 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
238 (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))]
239 "(register_operand (operands[0],QImode)
240 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
241 "* return output_movqi (insn, operands, NULL);"
242 [(set_attr "length" "1,1,5,5,1,1,4")
243 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
245 ;; This is used in peephole2 to optimize loading immediate constants
246 ;; if a scratch register from LD_REGS happens to be available.
248 (define_insn "*reload_inqi"
249 [(set (match_operand:QI 0 "register_operand" "=l")
250 (match_operand:QI 1 "immediate_operand" "i"))
251 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
255 [(set_attr "length" "2")
256 (set_attr "cc" "none")])
259 [(match_scratch:QI 2 "d")
260 (set (match_operand:QI 0 "l_register_operand" "")
261 (match_operand:QI 1 "immediate_operand" ""))]
262 "(operands[1] != const0_rtx
263 && operands[1] != const1_rtx
264 && operands[1] != constm1_rtx)"
265 [(parallel [(set (match_dup 0) (match_dup 1))
266 (clobber (match_dup 2))])]
269 ;;============================================================================
270 ;; move word (16 bit)
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "nonimmediate_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
278 /* One of the ops has to be in a register. */
279 if (!register_operand(operand0, HImode)
280 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
282 operands[1] = copy_to_mode_reg(HImode, operand1);
286 (define_insn "*movhi_sp"
287 [(set (match_operand:HI 0 "register_operand" "=q,r")
288 (match_operand:HI 1 "register_operand" "r,q"))]
289 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
290 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
291 "* return output_movhi (insn, operands, NULL);"
292 [(set_attr "length" "5,2")
293 (set_attr "cc" "none,none")])
295 (define_insn "movhi_sp_r_irq_off"
296 [(set (match_operand:HI 0 "stack_register_operand" "=q")
297 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
298 UNSPECV_WRITE_SP_IRQ_OFF))]
302 [(set_attr "length" "2")
303 (set_attr "cc" "none")])
305 (define_insn "movhi_sp_r_irq_on"
306 [(set (match_operand:HI 0 "stack_register_operand" "=q")
307 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
308 UNSPECV_WRITE_SP_IRQ_ON))]
314 [(set_attr "length" "4")
315 (set_attr "cc" "none")])
318 [(match_scratch:QI 2 "d")
319 (set (match_operand:HI 0 "l_register_operand" "")
320 (match_operand:HI 1 "immediate_operand" ""))]
321 "(operands[1] != const0_rtx
322 && operands[1] != constm1_rtx)"
323 [(parallel [(set (match_dup 0) (match_dup 1))
324 (clobber (match_dup 2))])]
327 ;; '*' because it is not used in rtl generation, only in above peephole
328 (define_insn "*reload_inhi"
329 [(set (match_operand:HI 0 "register_operand" "=r")
330 (match_operand:HI 1 "immediate_operand" "i"))
331 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
333 "* return output_reload_inhi (insn, operands, NULL);"
334 [(set_attr "length" "4")
335 (set_attr "cc" "none")])
337 (define_insn "*movhi"
338 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
339 (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))]
340 "(register_operand (operands[0],HImode)
341 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
342 "* return output_movhi (insn, operands, NULL);"
343 [(set_attr "length" "2,6,7,2,6,5,2")
344 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
346 (define_peephole2 ; movw
347 [(set (match_operand:QI 0 "even_register_operand" "")
348 (match_operand:QI 1 "even_register_operand" ""))
349 (set (match_operand:QI 2 "odd_register_operand" "")
350 (match_operand:QI 3 "odd_register_operand" ""))]
352 && REGNO (operands[0]) == REGNO (operands[2]) - 1
353 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
354 [(set (match_dup 4) (match_dup 5))]
356 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
357 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
360 (define_peephole2 ; movw_r
361 [(set (match_operand:QI 0 "odd_register_operand" "")
362 (match_operand:QI 1 "odd_register_operand" ""))
363 (set (match_operand:QI 2 "even_register_operand" "")
364 (match_operand:QI 3 "even_register_operand" ""))]
366 && REGNO (operands[2]) == REGNO (operands[0]) - 1
367 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
368 [(set (match_dup 4) (match_dup 5))]
370 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
371 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
374 ;;==========================================================================
375 ;; move double word (32 bit)
377 (define_expand "movsi"
378 [(set (match_operand:SI 0 "nonimmediate_operand" "")
379 (match_operand:SI 1 "general_operand" ""))]
383 /* One of the ops has to be in a register. */
384 if (!register_operand (operand0, SImode)
385 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
387 operands[1] = copy_to_mode_reg (SImode, operand1);
393 (define_peephole2 ; movsi_lreg_const
394 [(match_scratch:QI 2 "d")
395 (set (match_operand:SI 0 "l_register_operand" "")
396 (match_operand:SI 1 "immediate_operand" ""))
398 "(operands[1] != const0_rtx
399 && operands[1] != constm1_rtx)"
400 [(parallel [(set (match_dup 0) (match_dup 1))
401 (clobber (match_dup 2))])]
404 ;; '*' because it is not used in rtl generation.
405 (define_insn "*reload_insi"
406 [(set (match_operand:SI 0 "register_operand" "=r")
407 (match_operand:SI 1 "immediate_operand" "i"))
408 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
410 "* return output_reload_insisf (insn, operands, NULL);"
411 [(set_attr "length" "8")
412 (set_attr "cc" "none")])
415 (define_insn "*movsi"
416 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
417 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
418 "(register_operand (operands[0],SImode)
419 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
420 "* return output_movsisf (insn, operands, NULL);"
421 [(set_attr "length" "4,4,8,9,4,10")
422 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
424 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
425 ;; move floating point numbers (32 bit)
427 (define_expand "movsf"
428 [(set (match_operand:SF 0 "nonimmediate_operand" "")
429 (match_operand:SF 1 "general_operand" ""))]
433 /* One of the ops has to be in a register. */
434 if (!register_operand (operand1, SFmode)
435 && !register_operand (operand0, SFmode))
437 operands[1] = copy_to_mode_reg (SFmode, operand1);
441 (define_insn "*movsf"
442 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
443 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
444 "register_operand (operands[0], SFmode)
445 || register_operand (operands[1], SFmode)"
446 "* return output_movsisf (insn, operands, NULL);"
447 [(set_attr "length" "4,4,8,9,4,10")
448 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
450 ;;=========================================================================
451 ;; move string (like memcpy)
452 ;; implement as RTL loop
454 (define_expand "movmemhi"
455 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
456 (match_operand:BLK 1 "memory_operand" ""))
457 (use (match_operand:HI 2 "const_int_operand" ""))
458 (use (match_operand:HI 3 "const_int_operand" ""))])]
463 enum machine_mode mode;
464 rtx label = gen_label_rtx ();
468 /* Copy pointers into new psuedos - they will be changed. */
469 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
470 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
472 /* Create rtx for tmp register - we use this as scratch. */
473 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
475 if (GET_CODE (operands[2]) != CONST_INT)
478 count = INTVAL (operands[2]);
482 /* Work out branch probability for latter use. */
483 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
485 /* See if constant fit 8 bits. */
486 mode = (count < 0x100) ? QImode : HImode;
487 /* Create loop counter register. */
488 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
490 /* Now create RTL code for move loop. */
491 /* Label at top of loop. */
494 /* Move one byte into scratch and inc pointer. */
495 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
496 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
498 /* Move to mem and inc pointer. */
499 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
500 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
502 /* Decrement count. */
503 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
505 /* Compare with zero and jump if not equal. */
506 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
508 /* Set jump probability based on loop count. */
509 jump = get_last_insn ();
510 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
514 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
515 ;; memset (%0, %2, %1)
517 (define_expand "setmemhi"
518 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
519 (match_operand 2 "const_int_operand" ""))
520 (use (match_operand:HI 1 "const_int_operand" ""))
521 (use (match_operand:HI 3 "const_int_operand" "n"))
522 (clobber (match_scratch:HI 4 ""))
523 (clobber (match_dup 5))])]
528 enum machine_mode mode;
530 /* If value to set is not zero, use the library routine. */
531 if (operands[2] != const0_rtx)
534 if (GET_CODE (operands[1]) != CONST_INT)
537 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
538 mode = cnt8 ? QImode : HImode;
539 operands[5] = gen_rtx_SCRATCH (mode);
540 operands[1] = copy_to_mode_reg (mode,
541 gen_int_mode (INTVAL (operands[1]), mode));
542 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
543 operands[0] = gen_rtx_MEM (BLKmode, addr0);
546 (define_insn "*clrmemqi"
547 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
549 (use (match_operand:QI 1 "register_operand" "r"))
550 (use (match_operand:QI 2 "const_int_operand" "n"))
551 (clobber (match_scratch:HI 3 "=0"))
552 (clobber (match_scratch:QI 4 "=&1"))]
554 "st %a0+,__zero_reg__
557 [(set_attr "length" "3")
558 (set_attr "cc" "clobber")])
560 (define_insn "*clrmemhi"
561 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
563 (use (match_operand:HI 1 "register_operand" "!w,d"))
564 (use (match_operand:HI 2 "const_int_operand" "n,n"))
565 (clobber (match_scratch:HI 3 "=0,0"))
566 (clobber (match_scratch:HI 4 "=&1,&1"))]
569 if (which_alternative==0)
570 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
571 AS2 (sbiw,%A1,1) CR_TAB
574 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
575 AS2 (subi,%A1,1) CR_TAB
576 AS2 (sbci,%B1,0) CR_TAB
579 [(set_attr "length" "3,4")
580 (set_attr "cc" "clobber,clobber")])
582 (define_expand "strlenhi"
584 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
585 (match_operand:QI 2 "const_int_operand" "")
586 (match_operand:HI 3 "immediate_operand" "")]
588 (set (match_dup 4) (plus:HI (match_dup 4)
590 (set (match_operand:HI 0 "register_operand" "")
591 (minus:HI (match_dup 4)
596 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
598 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
599 operands[1] = gen_rtx_MEM (BLKmode, addr);
601 operands[4] = gen_reg_rtx (HImode);
604 (define_insn "*strlenhi"
605 [(set (match_operand:HI 0 "register_operand" "=e")
606 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
608 (match_operand:HI 2 "immediate_operand" "i")]
614 [(set_attr "length" "3")
615 (set_attr "cc" "clobber")])
617 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
620 (define_insn "addqi3"
621 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
622 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
623 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
630 [(set_attr "length" "1,1,1,1")
631 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
634 (define_expand "addhi3"
635 [(set (match_operand:HI 0 "register_operand" "")
636 (plus:HI (match_operand:HI 1 "register_operand" "")
637 (match_operand:HI 2 "nonmemory_operand" "")))]
641 if (GET_CODE (operands[2]) == CONST_INT)
643 short tmp = INTVAL (operands[2]);
644 operands[2] = GEN_INT(tmp);
649 (define_insn "*addhi3_zero_extend"
650 [(set (match_operand:HI 0 "register_operand" "=r")
651 (plus:HI (zero_extend:HI
652 (match_operand:QI 1 "register_operand" "r"))
653 (match_operand:HI 2 "register_operand" "0")))]
656 adc %B0,__zero_reg__"
657 [(set_attr "length" "2")
658 (set_attr "cc" "set_n")])
660 (define_insn "*addhi3_zero_extend1"
661 [(set (match_operand:HI 0 "register_operand" "=r")
662 (plus:HI (match_operand:HI 1 "register_operand" "%0")
664 (match_operand:QI 2 "register_operand" "r"))))]
667 adc %B0,__zero_reg__"
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_n")])
671 (define_insn "*addhi3_sp_R_pc2"
672 [(set (match_operand:HI 1 "stack_register_operand" "=q")
673 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
674 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
677 if (CONST_INT_P (operands[0]))
679 switch(INTVAL (operands[0]))
682 return \"rcall .\" CR_TAB
686 return \"rcall .\" CR_TAB
688 \"push __tmp_reg__\";
690 return \"rcall .\" CR_TAB
693 return \"rcall .\" CR_TAB
694 \"push __tmp_reg__\";
698 return \"push __tmp_reg__\";
702 return \"pop __tmp_reg__\";
704 return \"pop __tmp_reg__\" CR_TAB
707 return \"pop __tmp_reg__\" CR_TAB
708 \"pop __tmp_reg__\" CR_TAB
711 return \"pop __tmp_reg__\" CR_TAB
712 \"pop __tmp_reg__\" CR_TAB
713 \"pop __tmp_reg__\" CR_TAB
716 return \"pop __tmp_reg__\" CR_TAB
717 \"pop __tmp_reg__\" CR_TAB
718 \"pop __tmp_reg__\" CR_TAB
719 \"pop __tmp_reg__\" CR_TAB
725 [(set (attr "length")
726 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
727 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
728 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
729 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
730 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
731 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
732 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
733 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
734 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
735 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
736 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
737 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
740 (define_insn "*addhi3_sp_R_pc3"
741 [(set (match_operand:HI 1 "stack_register_operand" "=q")
742 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
743 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
746 if (CONST_INT_P (operands[0]))
748 switch(INTVAL (operands[0]))
751 return \"rcall .\" CR_TAB
754 return \"rcall .\" CR_TAB
755 \"push __tmp_reg__\" CR_TAB
756 \"push __tmp_reg__\";
758 return \"rcall .\" CR_TAB
759 \"push __tmp_reg__\";
763 return \"push __tmp_reg__\" CR_TAB
764 \"push __tmp_reg__\";
766 return \"push __tmp_reg__\";
770 return \"pop __tmp_reg__\";
772 return \"pop __tmp_reg__\" CR_TAB
775 return \"pop __tmp_reg__\" CR_TAB
776 \"pop __tmp_reg__\" CR_TAB
779 return \"pop __tmp_reg__\" CR_TAB
780 \"pop __tmp_reg__\" CR_TAB
781 \"pop __tmp_reg__\" CR_TAB
784 return \"pop __tmp_reg__\" CR_TAB
785 \"pop __tmp_reg__\" CR_TAB
786 \"pop __tmp_reg__\" CR_TAB
787 \"pop __tmp_reg__\" CR_TAB
793 [(set (attr "length")
794 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
795 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
796 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
797 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
798 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
799 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
800 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
801 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
802 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
803 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
804 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
805 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
808 (define_insn "*addhi3"
809 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
811 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
812 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
815 add %A0,%A2\;adc %B0,%B2
818 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
819 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
820 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
821 [(set_attr "length" "2,1,1,2,3,3")
822 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
824 (define_insn "addsi3"
825 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
827 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
828 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
831 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
832 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
833 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
834 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
835 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
836 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
837 [(set_attr "length" "4,3,3,4,5,5")
838 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
840 (define_insn "*addsi3_zero_extend"
841 [(set (match_operand:SI 0 "register_operand" "=r")
842 (plus:SI (zero_extend:SI
843 (match_operand:QI 1 "register_operand" "r"))
844 (match_operand:SI 2 "register_operand" "0")))]
849 adc %D0,__zero_reg__"
850 [(set_attr "length" "4")
851 (set_attr "cc" "set_n")])
853 ;-----------------------------------------------------------------------------
855 (define_insn "subqi3"
856 [(set (match_operand:QI 0 "register_operand" "=r,d")
857 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
858 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
863 [(set_attr "length" "1,1")
864 (set_attr "cc" "set_czn,set_czn")])
866 (define_insn "subhi3"
867 [(set (match_operand:HI 0 "register_operand" "=r,d")
868 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
869 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
872 sub %A0,%A2\;sbc %B0,%B2
873 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
874 [(set_attr "length" "2,2")
875 (set_attr "cc" "set_czn,set_czn")])
877 (define_insn "*subhi3_zero_extend1"
878 [(set (match_operand:HI 0 "register_operand" "=r")
879 (minus:HI (match_operand:HI 1 "register_operand" "0")
881 (match_operand:QI 2 "register_operand" "r"))))]
884 sbc %B0,__zero_reg__"
885 [(set_attr "length" "2")
886 (set_attr "cc" "set_n")])
888 (define_insn "subsi3"
889 [(set (match_operand:SI 0 "register_operand" "=r,d")
890 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
891 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
894 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
895 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
896 [(set_attr "length" "4,4")
897 (set_attr "cc" "set_czn,set_czn")])
899 (define_insn "*subsi3_zero_extend"
900 [(set (match_operand:SI 0 "register_operand" "=r")
901 (minus:SI (match_operand:SI 1 "register_operand" "0")
903 (match_operand:QI 2 "register_operand" "r"))))]
908 sbc %D0,__zero_reg__"
909 [(set_attr "length" "4")
910 (set_attr "cc" "set_n")])
912 ;******************************************************************************
915 (define_expand "mulqi3"
916 [(set (match_operand:QI 0 "register_operand" "")
917 (mult:QI (match_operand:QI 1 "register_operand" "")
918 (match_operand:QI 2 "register_operand" "")))]
923 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
928 (define_insn "*mulqi3_enh"
929 [(set (match_operand:QI 0 "register_operand" "=r")
930 (mult:QI (match_operand:QI 1 "register_operand" "r")
931 (match_operand:QI 2 "register_operand" "r")))]
936 [(set_attr "length" "3")
937 (set_attr "cc" "clobber")])
939 (define_expand "mulqi3_call"
940 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
941 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
942 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
943 (clobber (reg:QI 22))])
944 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
948 (define_insn "*mulqi3_call"
949 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
950 (clobber (reg:QI 22))]
953 [(set_attr "type" "xcall")
954 (set_attr "cc" "clobber")])
956 (define_insn "mulqihi3"
957 [(set (match_operand:HI 0 "register_operand" "=r")
958 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
959 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
964 [(set_attr "length" "3")
965 (set_attr "cc" "clobber")])
967 (define_insn "umulqihi3"
968 [(set (match_operand:HI 0 "register_operand" "=r")
969 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
970 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
975 [(set_attr "length" "3")
976 (set_attr "cc" "clobber")])
978 (define_expand "mulhi3"
979 [(set (match_operand:HI 0 "register_operand" "")
980 (mult:HI (match_operand:HI 1 "register_operand" "")
981 (match_operand:HI 2 "register_operand" "")))]
987 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
992 (define_insn "*mulhi3_enh"
993 [(set (match_operand:HI 0 "register_operand" "=&r")
994 (mult:HI (match_operand:HI 1 "register_operand" "r")
995 (match_operand:HI 2 "register_operand" "r")))]
1004 [(set_attr "length" "7")
1005 (set_attr "cc" "clobber")])
1007 (define_expand "mulhi3_call"
1008 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1009 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1010 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1011 (clobber (reg:HI 22))
1012 (clobber (reg:QI 21))])
1013 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
1017 (define_insn "*mulhi3_call"
1018 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1019 (clobber (reg:HI 22))
1020 (clobber (reg:QI 21))]
1023 [(set_attr "type" "xcall")
1024 (set_attr "cc" "clobber")])
1026 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
1027 ;; All call-used registers clobbered otherwise - normal library call.
1028 (define_expand "mulsi3"
1029 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1030 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1031 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1032 (clobber (reg:HI 26))
1033 (clobber (reg:HI 30))])
1034 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
1038 (define_insn "*mulsi3_call"
1039 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1040 (clobber (reg:HI 26))
1041 (clobber (reg:HI 30))]
1044 [(set_attr "type" "xcall")
1045 (set_attr "cc" "clobber")])
1047 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
1050 ;; Generate libgcc.S calls ourselves, because:
1051 ;; - we know exactly which registers are clobbered (for QI and HI
1052 ;; modes, some of the call-used registers are preserved)
1053 ;; - we get both the quotient and the remainder at no extra cost
1055 (define_expand "divmodqi4"
1056 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
1057 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
1058 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1059 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1060 (clobber (reg:QI 22))
1061 (clobber (reg:QI 23))])
1062 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
1063 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
1067 (define_insn "*divmodqi4_call"
1068 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1069 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1070 (clobber (reg:QI 22))
1071 (clobber (reg:QI 23))]
1073 "%~call __divmodqi4"
1074 [(set_attr "type" "xcall")
1075 (set_attr "cc" "clobber")])
1077 (define_expand "udivmodqi4"
1078 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
1079 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
1080 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1081 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1082 (clobber (reg:QI 23))])
1083 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
1084 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
1088 (define_insn "*udivmodqi4_call"
1089 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1090 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1091 (clobber (reg:QI 23))]
1093 "%~call __udivmodqi4"
1094 [(set_attr "type" "xcall")
1095 (set_attr "cc" "clobber")])
1097 (define_expand "divmodhi4"
1098 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1099 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1100 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1101 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1102 (clobber (reg:HI 26))
1103 (clobber (reg:QI 21))])
1104 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
1105 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
1109 (define_insn "*divmodhi4_call"
1110 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1111 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1112 (clobber (reg:HI 26))
1113 (clobber (reg:QI 21))]
1115 "%~call __divmodhi4"
1116 [(set_attr "type" "xcall")
1117 (set_attr "cc" "clobber")])
1119 (define_expand "udivmodhi4"
1120 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1121 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1122 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1123 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1124 (clobber (reg:HI 26))
1125 (clobber (reg:QI 21))])
1126 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
1127 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
1131 (define_insn "*udivmodhi4_call"
1132 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1133 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1134 (clobber (reg:HI 26))
1135 (clobber (reg:QI 21))]
1137 "%~call __udivmodhi4"
1138 [(set_attr "type" "xcall")
1139 (set_attr "cc" "clobber")])
1141 (define_expand "divmodsi4"
1142 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1143 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1144 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1145 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1146 (clobber (reg:HI 26))
1147 (clobber (reg:HI 30))])
1148 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
1149 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
1153 (define_insn "*divmodsi4_call"
1154 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1155 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1156 (clobber (reg:HI 26))
1157 (clobber (reg:HI 30))]
1159 "%~call __divmodsi4"
1160 [(set_attr "type" "xcall")
1161 (set_attr "cc" "clobber")])
1163 (define_expand "udivmodsi4"
1164 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1165 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1166 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1167 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1168 (clobber (reg:HI 26))
1169 (clobber (reg:HI 30))])
1170 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
1171 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
1175 (define_insn "*udivmodsi4_call"
1176 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1177 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1178 (clobber (reg:HI 26))
1179 (clobber (reg:HI 30))]
1181 "%~call __udivmodsi4"
1182 [(set_attr "type" "xcall")
1183 (set_attr "cc" "clobber")])
1185 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
1188 (define_insn "andqi3"
1189 [(set (match_operand:QI 0 "register_operand" "=r,d")
1190 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
1191 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1196 [(set_attr "length" "1,1")
1197 (set_attr "cc" "set_zn,set_zn")])
1199 (define_insn "andhi3"
1200 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1201 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1202 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1203 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1206 if (which_alternative==0)
1207 return ("and %A0,%A2" CR_TAB
1209 else if (which_alternative==1)
1211 if (GET_CODE (operands[2]) == CONST_INT)
1213 int mask = INTVAL (operands[2]);
1214 if ((mask & 0xff) != 0xff)
1215 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1216 if ((mask & 0xff00) != 0xff00)
1217 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1220 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1221 AS2 (andi,%B0,hi8(%2)));
1223 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1227 [(set_attr "length" "2,2,3")
1228 (set_attr "cc" "set_n,clobber,set_n")])
1230 (define_insn "andsi3"
1231 [(set (match_operand:SI 0 "register_operand" "=r,d")
1232 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1233 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1236 if (which_alternative==0)
1237 return ("and %0,%2" CR_TAB
1238 "and %B0,%B2" CR_TAB
1239 "and %C0,%C2" CR_TAB
1241 else if (which_alternative==1)
1243 if (GET_CODE (operands[2]) == CONST_INT)
1245 HOST_WIDE_INT mask = INTVAL (operands[2]);
1246 if ((mask & 0xff) != 0xff)
1247 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1248 if ((mask & 0xff00) != 0xff00)
1249 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1250 if ((mask & 0xff0000L) != 0xff0000L)
1251 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1252 if ((mask & 0xff000000L) != 0xff000000L)
1253 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1256 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1257 AS2 (andi, %B0,hi8(%2)) CR_TAB
1258 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1259 AS2 (andi, %D0,hhi8(%2)));
1263 [(set_attr "length" "4,4")
1264 (set_attr "cc" "set_n,clobber")])
1266 (define_peephole2 ; andi
1267 [(set (match_operand:QI 0 "d_register_operand" "")
1268 (and:QI (match_dup 0)
1269 (match_operand:QI 1 "const_int_operand" "")))
1271 (and:QI (match_dup 0)
1272 (match_operand:QI 2 "const_int_operand" "")))]
1274 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1276 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
1279 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1282 (define_insn "iorqi3"
1283 [(set (match_operand:QI 0 "register_operand" "=r,d")
1284 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1285 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1290 [(set_attr "length" "1,1")
1291 (set_attr "cc" "set_zn,set_zn")])
1293 (define_insn "iorhi3"
1294 [(set (match_operand:HI 0 "register_operand" "=r,d")
1295 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1296 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1299 if (which_alternative==0)
1300 return ("or %A0,%A2" CR_TAB
1302 if (GET_CODE (operands[2]) == CONST_INT)
1304 int mask = INTVAL (operands[2]);
1306 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1308 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1311 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1312 AS2 (ori,%B0,hi8(%2)));
1314 [(set_attr "length" "2,2")
1315 (set_attr "cc" "set_n,clobber")])
1317 (define_insn "*iorhi3_clobber"
1318 [(set (match_operand:HI 0 "register_operand" "=r,r")
1319 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1320 (match_operand:HI 2 "immediate_operand" "M,i")))
1321 (clobber (match_scratch:QI 3 "=&d,&d"))]
1324 ldi %3,lo8(%2)\;or %A0,%3
1325 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1326 [(set_attr "length" "2,4")
1327 (set_attr "cc" "clobber,set_n")])
1329 (define_insn "iorsi3"
1330 [(set (match_operand:SI 0 "register_operand" "=r,d")
1331 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1332 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1335 if (which_alternative==0)
1336 return ("or %0,%2" CR_TAB
1340 if (GET_CODE (operands[2]) == CONST_INT)
1342 HOST_WIDE_INT mask = INTVAL (operands[2]);
1344 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1346 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1347 if (mask & 0xff0000L)
1348 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1349 if (mask & 0xff000000L)
1350 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1353 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1354 AS2 (ori, %B0,hi8(%2)) CR_TAB
1355 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1356 AS2 (ori, %D0,hhi8(%2)));
1358 [(set_attr "length" "4,4")
1359 (set_attr "cc" "set_n,clobber")])
1361 (define_insn "*iorsi3_clobber"
1362 [(set (match_operand:SI 0 "register_operand" "=r,r")
1363 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1364 (match_operand:SI 2 "immediate_operand" "M,i")))
1365 (clobber (match_scratch:QI 3 "=&d,&d"))]
1368 ldi %3,lo8(%2)\;or %A0,%3
1369 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1370 [(set_attr "length" "2,8")
1371 (set_attr "cc" "clobber,set_n")])
1373 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1376 (define_insn "xorqi3"
1377 [(set (match_operand:QI 0 "register_operand" "=r")
1378 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1379 (match_operand:QI 2 "register_operand" "r")))]
1382 [(set_attr "length" "1")
1383 (set_attr "cc" "set_zn")])
1385 (define_insn "xorhi3"
1386 [(set (match_operand:HI 0 "register_operand" "=r")
1387 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1388 (match_operand:HI 2 "register_operand" "r")))]
1392 [(set_attr "length" "2")
1393 (set_attr "cc" "set_n")])
1395 (define_insn "xorsi3"
1396 [(set (match_operand:SI 0 "register_operand" "=r")
1397 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1398 (match_operand:SI 2 "register_operand" "r")))]
1404 [(set_attr "length" "4")
1405 (set_attr "cc" "set_n")])
1407 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
1410 (define_expand "rotlqi3"
1411 [(set (match_operand:QI 0 "register_operand" "")
1412 (rotate:QI (match_operand:QI 1 "register_operand" "")
1413 (match_operand:QI 2 "const_int_operand" "")))]
1417 if (INTVAL (operands[2]) != 4)
1421 (define_insn "*rotlqi3_4"
1422 [(set (match_operand:QI 0 "register_operand" "=r")
1423 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1427 [(set_attr "length" "1")
1428 (set_attr "cc" "none")])
1430 (define_expand "rotlhi3"
1431 [(set (match_operand:HI 0 "register_operand" "")
1432 (rotate:HI (match_operand:HI 1 "register_operand" "")
1433 (match_operand:HI 2 "const_int_operand" "")))]
1437 if (INTVAL (operands[2]) != 8)
1441 (define_insn_and_split "*rotlhi3_8"
1442 [(set (match_operand:HI 0 "register_operand" "=r")
1443 (rotate:HI (match_operand:HI 1 "register_operand" "r")
1446 "mov __tmp_reg__,%A0
1448 mov %B0, __tmp_reg__"
1450 && REGNO (operands[0]) != REGNO (operands[1])"
1451 [(set (match_dup 2) (match_dup 5))
1452 (set (match_dup 3) (match_dup 4))]
1453 "operands[2] = gen_lowpart (QImode, operands[0]);
1454 operands[3] = gen_highpart (QImode, operands[0]);
1456 operands[4] = gen_lowpart (QImode, operands[1]);
1457 operands[5] = gen_highpart (QImode, operands[1]);"
1458 [(set_attr "length" "3")
1459 (set_attr "cc" "none")])
1461 (define_expand "rotlsi3"
1462 [(set (match_operand:SI 0 "register_operand" "")
1463 (rotate:SI (match_operand:SI 1 "register_operand" "")
1464 (match_operand:SI 2 "const_int_operand" "")))]
1468 if (INTVAL (operands[2]) != 8
1469 || INTVAL (operands[2]) != 16
1470 || INTVAL (operands[2]) != 24)
1474 (define_insn_and_split "*rotlsi3_16"
1475 [(set (match_operand:SI 0 "register_operand" "=r")
1476 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1479 "{mov __tmp_reg__,%A1\;mov %A0,%C1\;mov %C0, __tmp_reg__\;mov __tmp_reg__,%B1\;mov %B0,%D1\;mov %D0, __tmp_reg__|movw __tmp_reg__,%A1\;movw %A0,%C1\;movw %C0, __tmp_reg__\;clr __zero_reg__}"
1481 && REGNO (operands[0]) != REGNO (operands[1])"
1482 [(set (match_dup 2) (match_dup 5))
1483 (set (match_dup 3) (match_dup 4))]
1484 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1485 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1487 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1488 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1490 operands[4] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1491 operands[5] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
1493 if (REGNO (operands[0]) == REGNO(operands[1]) + 2)
1495 emit_move_insn (operands[3], operands[4]);
1498 else if (REGNO (operands[0]) == REGNO(operands[1]) - 2)
1500 emit_move_insn (operands[2], operands[5]);
1503 [(set (attr "length") (if_then_else (eq_attr "mcu_have_movw" "yes")
1506 (set (attr "cc") (if_then_else (eq_attr "mcu_have_movw" "yes")
1507 (const_string "clobber")
1508 (const_string "none")))])
1510 (define_insn_and_split "*rotlsi3_8"
1511 [(set (match_operand:SI 0 "register_operand" "=r")
1512 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1515 "mov __tmp_reg__,%D1
1519 mov %A0, __tmp_reg__"
1521 && REGNO (operands[0]) != REGNO (operands[1])"
1523 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1524 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1525 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
1526 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
1528 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1529 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1530 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
1531 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
1532 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
1533 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
1535 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1536 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
1537 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
1538 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
1539 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
1540 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
1542 if (REGNO (operands[0]) < REGNO(operands[1]))
1544 emit_move_insn (operands[2], operands[9]);
1545 emit_move_insn (operands[3], operands[6]);
1546 emit_move_insn (operands[4], operands[7]);
1547 emit_move_insn (operands[5], operands[8]);
1551 emit_move_insn (operands[5], operands[8]);
1552 emit_move_insn (operands[2], operands[9]);
1553 emit_move_insn (operands[4], operands[7]);
1554 emit_move_insn (operands[3], operands[6]);
1557 [(set_attr "length" "5")
1558 (set_attr "cc" "none")])
1560 (define_insn_and_split "*rotlsi3_24"
1561 [(set (match_operand:SI 0 "register_operand" "=r")
1562 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1565 "mov __tmp_reg__,%A1
1569 mov %D0, __tmp_reg__"
1571 && REGNO (operands[0]) != REGNO (operands[1])"
1573 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
1574 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
1575 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
1576 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
1578 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
1579 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
1580 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
1581 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
1582 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
1583 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
1585 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
1586 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
1587 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
1588 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
1589 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
1590 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
1592 if (REGNO (operands[0]) < REGNO(operands[1]))
1594 emit_move_insn (operands[2], operands[7]);
1595 emit_move_insn (operands[5], operands[6]);
1596 emit_move_insn (operands[3], operands[8]);
1597 emit_move_insn (operands[4], operands[9]);
1601 emit_move_insn (operands[5], operands[6]);
1602 emit_move_insn (operands[4], operands[9]);
1603 emit_move_insn (operands[3], operands[8]);
1604 emit_move_insn (operands[2], operands[7]);
1607 [(set_attr "length" "5")
1608 (set_attr "cc" "none")])
1610 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1611 ;; arithmetic shift left
1613 (define_expand "ashlqi3"
1614 [(set (match_operand:QI 0 "register_operand" "")
1615 (ashift:QI (match_operand:QI 1 "register_operand" "")
1616 (match_operand:QI 2 "general_operand" "")))]
1620 (define_split ; ashlqi3_const4
1621 [(set (match_operand:QI 0 "d_register_operand" "")
1622 (ashift:QI (match_dup 0)
1625 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1626 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
1629 (define_split ; ashlqi3_const5
1630 [(set (match_operand:QI 0 "d_register_operand" "")
1631 (ashift:QI (match_dup 0)
1634 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1635 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1636 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
1639 (define_split ; ashlqi3_const6
1640 [(set (match_operand:QI 0 "d_register_operand" "")
1641 (ashift:QI (match_dup 0)
1644 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1645 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1646 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
1649 (define_insn "*ashlqi3"
1650 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1651 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1652 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1654 "* return ashlqi3_out (insn, operands, NULL);"
1655 [(set_attr "length" "5,0,1,2,4,6,9")
1656 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1658 (define_insn "ashlhi3"
1659 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1660 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1661 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1663 "* return ashlhi3_out (insn, operands, NULL);"
1664 [(set_attr "length" "6,0,2,2,4,10,10")
1665 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1667 (define_insn "ashlsi3"
1668 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1669 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1670 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1672 "* return ashlsi3_out (insn, operands, NULL);"
1673 [(set_attr "length" "8,0,4,4,8,10,12")
1674 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1676 ;; Optimize if a scratch register from LD_REGS happens to be available.
1678 (define_peephole2 ; ashlqi3_l_const4
1679 [(set (match_operand:QI 0 "l_register_operand" "")
1680 (ashift:QI (match_dup 0)
1682 (match_scratch:QI 1 "d")]
1684 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1685 (set (match_dup 1) (const_int -16))
1686 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1689 (define_peephole2 ; ashlqi3_l_const5
1690 [(set (match_operand:QI 0 "l_register_operand" "")
1691 (ashift:QI (match_dup 0)
1693 (match_scratch:QI 1 "d")]
1695 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1696 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1697 (set (match_dup 1) (const_int -32))
1698 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1701 (define_peephole2 ; ashlqi3_l_const6
1702 [(set (match_operand:QI 0 "l_register_operand" "")
1703 (ashift:QI (match_dup 0)
1705 (match_scratch:QI 1 "d")]
1707 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1708 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1709 (set (match_dup 1) (const_int -64))
1710 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1714 [(match_scratch:QI 3 "d")
1715 (set (match_operand:HI 0 "register_operand" "")
1716 (ashift:HI (match_operand:HI 1 "register_operand" "")
1717 (match_operand:QI 2 "const_int_operand" "")))]
1719 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1720 (clobber (match_dup 3))])]
1723 (define_insn "*ashlhi3_const"
1724 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1725 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1726 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1727 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1729 "* return ashlhi3_out (insn, operands, NULL);"
1730 [(set_attr "length" "0,2,2,4,10")
1731 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
1734 [(match_scratch:QI 3 "d")
1735 (set (match_operand:SI 0 "register_operand" "")
1736 (ashift:SI (match_operand:SI 1 "register_operand" "")
1737 (match_operand:QI 2 "const_int_operand" "")))]
1739 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1740 (clobber (match_dup 3))])]
1743 (define_insn "*ashlsi3_const"
1744 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1745 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1746 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1747 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1749 "* return ashlsi3_out (insn, operands, NULL);"
1750 [(set_attr "length" "0,4,4,10")
1751 (set_attr "cc" "none,set_n,clobber,clobber")])
1753 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1754 ;; arithmetic shift right
1756 (define_insn "ashrqi3"
1757 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1758 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1759 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
1761 "* return ashrqi3_out (insn, operands, NULL);"
1762 [(set_attr "length" "5,0,1,2,5,9")
1763 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
1765 (define_insn "ashrhi3"
1766 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1767 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1768 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1770 "* return ashrhi3_out (insn, operands, NULL);"
1771 [(set_attr "length" "6,0,2,4,4,10,10")
1772 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1774 (define_insn "ashrsi3"
1775 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1776 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1777 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1779 "* return ashrsi3_out (insn, operands, NULL);"
1780 [(set_attr "length" "8,0,4,6,8,10,12")
1781 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1783 ;; Optimize if a scratch register from LD_REGS happens to be available.
1786 [(match_scratch:QI 3 "d")
1787 (set (match_operand:HI 0 "register_operand" "")
1788 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1789 (match_operand:QI 2 "const_int_operand" "")))]
1791 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1792 (clobber (match_dup 3))])]
1795 (define_insn "*ashrhi3_const"
1796 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1797 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1798 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1799 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1801 "* return ashrhi3_out (insn, operands, NULL);"
1802 [(set_attr "length" "0,2,4,4,10")
1803 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
1806 [(match_scratch:QI 3 "d")
1807 (set (match_operand:SI 0 "register_operand" "")
1808 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1809 (match_operand:QI 2 "const_int_operand" "")))]
1811 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1812 (clobber (match_dup 3))])]
1815 (define_insn "*ashrsi3_const"
1816 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1817 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1818 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1819 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1821 "* return ashrsi3_out (insn, operands, NULL);"
1822 [(set_attr "length" "0,4,4,10")
1823 (set_attr "cc" "none,clobber,set_n,clobber")])
1825 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1826 ;; logical shift right
1828 (define_expand "lshrqi3"
1829 [(set (match_operand:QI 0 "register_operand" "")
1830 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1831 (match_operand:QI 2 "general_operand" "")))]
1835 (define_split ; lshrqi3_const4
1836 [(set (match_operand:QI 0 "d_register_operand" "")
1837 (lshiftrt:QI (match_dup 0)
1840 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1841 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
1844 (define_split ; lshrqi3_const5
1845 [(set (match_operand:QI 0 "d_register_operand" "")
1846 (lshiftrt:QI (match_dup 0)
1849 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1850 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1851 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
1854 (define_split ; lshrqi3_const6
1855 [(set (match_operand:QI 0 "d_register_operand" "")
1856 (lshiftrt:QI (match_dup 0)
1859 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1860 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1861 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
1864 (define_insn "*lshrqi3"
1865 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1866 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1867 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1869 "* return lshrqi3_out (insn, operands, NULL);"
1870 [(set_attr "length" "5,0,1,2,4,6,9")
1871 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1873 (define_insn "lshrhi3"
1874 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1875 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1876 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1878 "* return lshrhi3_out (insn, operands, NULL);"
1879 [(set_attr "length" "6,0,2,2,4,10,10")
1880 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1882 (define_insn "lshrsi3"
1883 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1884 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1885 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1887 "* return lshrsi3_out (insn, operands, NULL);"
1888 [(set_attr "length" "8,0,4,4,8,10,12")
1889 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1891 ;; Optimize if a scratch register from LD_REGS happens to be available.
1893 (define_peephole2 ; lshrqi3_l_const4
1894 [(set (match_operand:QI 0 "l_register_operand" "")
1895 (lshiftrt:QI (match_dup 0)
1897 (match_scratch:QI 1 "d")]
1899 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1900 (set (match_dup 1) (const_int 15))
1901 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1904 (define_peephole2 ; lshrqi3_l_const5
1905 [(set (match_operand:QI 0 "l_register_operand" "")
1906 (lshiftrt:QI (match_dup 0)
1908 (match_scratch:QI 1 "d")]
1910 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1911 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1912 (set (match_dup 1) (const_int 7))
1913 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1916 (define_peephole2 ; lshrqi3_l_const6
1917 [(set (match_operand:QI 0 "l_register_operand" "")
1918 (lshiftrt:QI (match_dup 0)
1920 (match_scratch:QI 1 "d")]
1922 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1923 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1924 (set (match_dup 1) (const_int 3))
1925 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1929 [(match_scratch:QI 3 "d")
1930 (set (match_operand:HI 0 "register_operand" "")
1931 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1932 (match_operand:QI 2 "const_int_operand" "")))]
1934 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1935 (clobber (match_dup 3))])]
1938 (define_insn "*lshrhi3_const"
1939 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1940 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1941 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1942 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1944 "* return lshrhi3_out (insn, operands, NULL);"
1945 [(set_attr "length" "0,2,2,4,10")
1946 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
1949 [(match_scratch:QI 3 "d")
1950 (set (match_operand:SI 0 "register_operand" "")
1951 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1952 (match_operand:QI 2 "const_int_operand" "")))]
1954 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1955 (clobber (match_dup 3))])]
1958 (define_insn "*lshrsi3_const"
1959 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1960 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1961 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1962 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1964 "* return lshrsi3_out (insn, operands, NULL);"
1965 [(set_attr "length" "0,4,4,10")
1966 (set_attr "cc" "none,clobber,clobber,clobber")])
1968 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
1971 (define_insn "absqi2"
1972 [(set (match_operand:QI 0 "register_operand" "=r")
1973 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
1977 [(set_attr "length" "2")
1978 (set_attr "cc" "clobber")])
1981 (define_insn "abssf2"
1982 [(set (match_operand:SF 0 "register_operand" "=d,r")
1983 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
1988 [(set_attr "length" "1,2")
1989 (set_attr "cc" "set_n,clobber")])
1991 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
1994 (define_insn "negqi2"
1995 [(set (match_operand:QI 0 "register_operand" "=r")
1996 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1999 [(set_attr "length" "1")
2000 (set_attr "cc" "set_zn")])
2002 (define_insn "neghi2"
2003 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
2004 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
2007 com %B0\;neg %A0\;sbci %B0,lo8(-1)
2008 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
2009 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
2010 [(set_attr "length" "3,4,4")
2011 (set_attr "cc" "set_czn,set_n,set_czn")])
2013 (define_insn "negsi2"
2014 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
2015 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
2018 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
2019 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
2020 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
2021 [(set_attr_alternative "length"
2024 (if_then_else (eq_attr "mcu_have_movw" "yes")
2027 (set_attr "cc" "set_czn,set_n,set_czn")])
2029 (define_insn "negsf2"
2030 [(set (match_operand:SF 0 "register_operand" "=d,r")
2031 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
2035 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
2036 [(set_attr "length" "1,4")
2037 (set_attr "cc" "set_n,set_n")])
2039 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2042 (define_insn "one_cmplqi2"
2043 [(set (match_operand:QI 0 "register_operand" "=r")
2044 (not:QI (match_operand:QI 1 "register_operand" "0")))]
2047 [(set_attr "length" "1")
2048 (set_attr "cc" "set_czn")])
2050 (define_insn "one_cmplhi2"
2051 [(set (match_operand:HI 0 "register_operand" "=r")
2052 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2056 [(set_attr "length" "2")
2057 (set_attr "cc" "set_n")])
2059 (define_insn "one_cmplsi2"
2060 [(set (match_operand:SI 0 "register_operand" "=r")
2061 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2067 [(set_attr "length" "4")
2068 (set_attr "cc" "set_n")])
2070 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2073 (define_insn "extendqihi2"
2074 [(set (match_operand:HI 0 "register_operand" "=r,r")
2075 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
2078 clr %B0\;sbrc %0,7\;com %B0
2079 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
2080 [(set_attr "length" "3,4")
2081 (set_attr "cc" "set_n,set_n")])
2083 (define_insn "extendqisi2"
2084 [(set (match_operand:SI 0 "register_operand" "=r,r")
2085 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
2088 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
2089 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
2090 [(set_attr "length" "5,6")
2091 (set_attr "cc" "set_n,set_n")])
2093 (define_insn "extendhisi2"
2094 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2095 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
2098 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
2099 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
2100 [(set_attr_alternative "length"
2102 (if_then_else (eq_attr "mcu_have_movw" "yes")
2105 (set_attr "cc" "set_n,set_n")])
2107 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2110 (define_insn_and_split "zero_extendqihi2"
2111 [(set (match_operand:HI 0 "register_operand" "=r")
2112 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2116 [(set (match_dup 2) (match_dup 1))
2117 (set (match_dup 3) (const_int 0))]
2118 "unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
2119 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
2121 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
2122 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
2125 (define_insn_and_split "zero_extendqisi2"
2126 [(set (match_operand:SI 0 "register_operand" "=r")
2127 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2131 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
2132 (set (match_dup 3) (const_int 0))]
2133 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2134 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2136 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2137 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2140 (define_insn_and_split "zero_extendhisi2"
2141 [(set (match_operand:SI 0 "register_operand" "=r")
2142 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2146 [(set (match_dup 2) (match_dup 1))
2147 (set (match_dup 3) (const_int 0))]
2148 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2149 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2151 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2152 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2155 (define_insn_and_split "zero_extendqidi2"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
2161 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2162 (set (match_dup 3) (const_int 0))]
2163 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2164 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2166 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2167 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2170 (define_insn_and_split "zero_extendhidi2"
2171 [(set (match_operand:DI 0 "register_operand" "=r")
2172 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
2176 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2177 (set (match_dup 3) (const_int 0))]
2178 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2179 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2181 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2182 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2185 (define_insn_and_split "zero_extendsidi2"
2186 [(set (match_operand:DI 0 "register_operand" "=r")
2187 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
2191 [(set (match_dup 2) (match_dup 1))
2192 (set (match_dup 3) (const_int 0))]
2193 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2194 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2196 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2197 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2200 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2203 ; Optimize negated tests into reverse compare if overflow is undefined.
2204 (define_insn "*negated_tstqi"
2206 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
2208 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2209 "cp __zero_reg__,%0"
2210 [(set_attr "cc" "compare")
2211 (set_attr "length" "1")])
2213 (define_insn "*reversed_tstqi"
2215 (compare (const_int 0)
2216 (match_operand:QI 0 "register_operand" "r")))]
2218 "cp __zero_reg__,%0"
2219 [(set_attr "cc" "compare")
2220 (set_attr "length" "2")])
2222 (define_insn "*negated_tsthi"
2224 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
2226 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2227 "cp __zero_reg__,%A0
2228 cpc __zero_reg__,%B0"
2229 [(set_attr "cc" "compare")
2230 (set_attr "length" "2")])
2232 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
2233 ;; though it is unused, because this pattern is synthesized by avr_reorg.
2234 (define_insn "*reversed_tsthi"
2236 (compare (const_int 0)
2237 (match_operand:HI 0 "register_operand" "r")))
2238 (clobber (match_scratch:QI 1 "=X"))]
2240 "cp __zero_reg__,%A0
2241 cpc __zero_reg__,%B0"
2242 [(set_attr "cc" "compare")
2243 (set_attr "length" "2")])
2245 (define_insn "*negated_tstsi"
2247 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
2249 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2250 "cp __zero_reg__,%A0
2251 cpc __zero_reg__,%B0
2252 cpc __zero_reg__,%C0
2253 cpc __zero_reg__,%D0"
2254 [(set_attr "cc" "compare")
2255 (set_attr "length" "4")])
2257 (define_insn "*reversed_tstsi"
2259 (compare (const_int 0)
2260 (match_operand:SI 0 "register_operand" "r")))
2261 (clobber (match_scratch:QI 1 "=X"))]
2263 "cp __zero_reg__,%A0
2264 cpc __zero_reg__,%B0
2265 cpc __zero_reg__,%C0
2266 cpc __zero_reg__,%D0"
2267 [(set_attr "cc" "compare")
2268 (set_attr "length" "4")])
2271 (define_insn "*cmpqi"
2273 (compare (match_operand:QI 0 "register_operand" "r,r,d")
2274 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
2280 [(set_attr "cc" "compare,compare,compare")
2281 (set_attr "length" "1,1,1")])
2283 (define_insn "*cmpqi_sign_extend"
2285 (compare (sign_extend:HI
2286 (match_operand:QI 0 "register_operand" "d"))
2287 (match_operand:HI 1 "const_int_operand" "n")))]
2288 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2290 [(set_attr "cc" "compare")
2291 (set_attr "length" "1")])
2293 (define_insn "*cmphi"
2295 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r")
2296 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i")))
2297 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))]
2300 switch (which_alternative)
2303 return out_tsthi (insn, operands[0], NULL);
2306 return (AS2 (cp,%A0,%A1) CR_TAB
2309 if (reg_unused_after (insn, operands[0])
2310 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2311 && test_hard_reg_class (ADDW_REGS, operands[0]))
2312 return AS2 (sbiw,%0,%1);
2314 return (AS2 (cpi,%0,%1) CR_TAB
2315 AS2 (cpc,%B0,__zero_reg__));
2317 if (reg_unused_after (insn, operands[0]))
2318 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2319 AS2 (sbci,%B0,hi8(%1)));
2321 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2322 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2325 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2326 AS2 (cp, %A0,%2) CR_TAB
2327 AS2 (cpc, %B0,__zero_reg__));
2330 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2331 AS2 (cp, %A0,%2) CR_TAB
2332 AS2 (ldi, %2,hi8(%1)) CR_TAB
2337 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare")
2338 (set_attr "length" "1,2,2,2,3,3,4")])
2341 (define_insn "*cmpsi"
2343 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r")
2344 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i")))
2345 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))]
2348 switch (which_alternative)
2351 return out_tstsi (insn, operands[0], NULL);
2354 return (AS2 (cp,%A0,%A1) CR_TAB
2355 AS2 (cpc,%B0,%B1) CR_TAB
2356 AS2 (cpc,%C0,%C1) CR_TAB
2359 if (reg_unused_after (insn, operands[0])
2360 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2361 && test_hard_reg_class (ADDW_REGS, operands[0]))
2362 return (AS2 (sbiw,%0,%1) CR_TAB
2363 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2364 AS2 (cpc,%D0,__zero_reg__));
2366 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2367 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2368 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2369 AS2 (cpc,%D0,__zero_reg__));
2371 if (reg_unused_after (insn, operands[0]))
2372 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2373 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2374 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2375 AS2 (sbci,%D0,hhi8(%1)));
2377 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
2378 AS2 (ldi, %2,hi8(%1)) CR_TAB
2379 AS2 (cpc, %B0,%2) CR_TAB
2380 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2381 AS2 (cpc, %C0,%2) CR_TAB
2382 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2385 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2386 AS2 (cp,%A0,%2) CR_TAB
2387 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2388 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2389 AS2 (cpc,%D0,__zero_reg__));
2391 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2392 AS2 (cp, %A0,%2) CR_TAB
2393 AS2 (ldi, %2,hi8(%1)) CR_TAB
2394 AS2 (cpc, %B0,%2) CR_TAB
2395 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2396 AS2 (cpc, %C0,%2) CR_TAB
2397 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2402 [(set_attr "cc" "compare,compare,compare,compare,compare,compare")
2403 (set_attr "length" "4,4,4,7,5,8")])
2406 ;; ----------------------------------------------------------------------
2407 ;; JUMP INSTRUCTIONS
2408 ;; ----------------------------------------------------------------------
2409 ;; Conditional jump instructions
2411 (define_expand "cbranchsi4"
2412 [(parallel [(set (cc0)
2413 (compare (match_operand:SI 1 "register_operand" "")
2414 (match_operand:SI 2 "nonmemory_operand" "")))
2415 (clobber (match_scratch:QI 4 ""))])
2418 (match_operator 0 "ordered_comparison_operator" [(cc0)
2420 (label_ref (match_operand 3 "" ""))
2424 (define_expand "cbranchhi4"
2425 [(parallel [(set (cc0)
2426 (compare (match_operand:HI 1 "register_operand" "")
2427 (match_operand:HI 2 "nonmemory_operand" "")))
2428 (clobber (match_scratch:QI 4 ""))])
2431 (match_operator 0 "ordered_comparison_operator" [(cc0)
2433 (label_ref (match_operand 3 "" ""))
2437 (define_expand "cbranchqi4"
2439 (compare (match_operand:QI 1 "register_operand" "")
2440 (match_operand:QI 2 "nonmemory_operand" "")))
2443 (match_operator 0 "ordered_comparison_operator" [(cc0)
2445 (label_ref (match_operand 3 "" ""))
2450 ;; Test a single bit in a QI/HI/SImode register.
2451 (define_insn "*sbrx_branch"
2454 (match_operator 0 "eqne_operator"
2456 (match_operand:QI 1 "register_operand" "r")
2458 (match_operand 2 "const_int_operand" "n"))
2460 (label_ref (match_operand 3 "" ""))
2463 "* return avr_out_sbxx_branch (insn, operands);"
2464 [(set (attr "length")
2465 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2466 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2468 (if_then_else (eq_attr "mcu_mega" "no")
2471 (set_attr "cc" "clobber")])
2473 (define_insn "*sbrx_and_branchhi"
2476 (match_operator 0 "eqne_operator"
2478 (match_operand:HI 1 "register_operand" "r")
2479 (match_operand:HI 2 "single_one_operand" "n"))
2481 (label_ref (match_operand 3 "" ""))
2484 "* return avr_out_sbxx_branch (insn, operands);"
2485 [(set (attr "length")
2486 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2487 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2489 (if_then_else (eq_attr "mcu_mega" "no")
2492 (set_attr "cc" "clobber")])
2494 (define_insn "*sbrx_and_branchsi"
2497 (match_operator 0 "eqne_operator"
2499 (match_operand:SI 1 "register_operand" "r")
2500 (match_operand:SI 2 "single_one_operand" "n"))
2502 (label_ref (match_operand 3 "" ""))
2505 "* return avr_out_sbxx_branch (insn, operands);"
2506 [(set (attr "length")
2507 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2508 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2510 (if_then_else (eq_attr "mcu_mega" "no")
2513 (set_attr "cc" "clobber")])
2515 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2517 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2519 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2520 (label_ref (match_operand 1 "" ""))
2523 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2527 (label_ref (match_dup 1))
2532 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2534 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2535 (label_ref (match_operand 1 "" ""))
2538 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2542 (label_ref (match_dup 1))
2547 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2549 (clobber (match_operand:HI 2 ""))])
2550 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2551 (label_ref (match_operand 1 "" ""))
2554 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2556 (label_ref (match_dup 1))
2561 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2563 (clobber (match_operand:HI 2 ""))])
2564 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2565 (label_ref (match_operand 1 "" ""))
2568 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2570 (label_ref (match_dup 1))
2575 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2577 (clobber (match_operand:SI 2 ""))])
2578 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2579 (label_ref (match_operand 1 "" ""))
2582 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2584 (label_ref (match_dup 1))
2586 "operands[2] = GEN_INT (-2147483647 - 1);")
2589 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2591 (clobber (match_operand:SI 2 ""))])
2592 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2593 (label_ref (match_operand 1 "" ""))
2596 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2598 (label_ref (match_dup 1))
2600 "operands[2] = GEN_INT (-2147483647 - 1);")
2602 ;; ************************************************************************
2603 ;; Implementation of conditional jumps here.
2604 ;; Compare with 0 (test) jumps
2605 ;; ************************************************************************
2607 (define_insn "branch"
2609 (if_then_else (match_operator 1 "simple_comparison_operator"
2612 (label_ref (match_operand 0 "" ""))
2616 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2617 [(set_attr "type" "branch")
2618 (set_attr "cc" "clobber")])
2620 ;; ****************************************************************
2621 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
2622 ;; Convert them all to proper jumps.
2623 ;; ****************************************************************/
2625 (define_insn "difficult_branch"
2627 (if_then_else (match_operator 1 "difficult_comparison_operator"
2630 (label_ref (match_operand 0 "" ""))
2634 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2635 [(set_attr "type" "branch1")
2636 (set_attr "cc" "clobber")])
2640 (define_insn "rvbranch"
2642 (if_then_else (match_operator 1 "simple_comparison_operator"
2646 (label_ref (match_operand 0 "" ""))))]
2649 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2650 [(set_attr "type" "branch1")
2651 (set_attr "cc" "clobber")])
2653 (define_insn "difficult_rvbranch"
2655 (if_then_else (match_operator 1 "difficult_comparison_operator"
2659 (label_ref (match_operand 0 "" ""))))]
2662 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2663 [(set_attr "type" "branch")
2664 (set_attr "cc" "clobber")])
2666 ;; **************************************************************************
2667 ;; Unconditional and other jump instructions.
2671 (label_ref (match_operand 0 "" "")))]
2674 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2675 return AS1 (jmp,%0);
2676 return AS1 (rjmp,%0);
2678 [(set (attr "length")
2679 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2680 (if_then_else (eq_attr "mcu_mega" "no")
2683 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
2684 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2687 (set_attr "cc" "none")])
2691 (define_expand "call"
2692 [(call (match_operand:HI 0 "call_insn_operand" "")
2693 (match_operand:HI 1 "general_operand" ""))]
2694 ;; Operand 1 not used on the AVR.
2700 (define_expand "call_value"
2701 [(set (match_operand 0 "register_operand" "")
2702 (call (match_operand:HI 1 "call_insn_operand" "")
2703 (match_operand:HI 2 "general_operand" "")))]
2704 ;; Operand 2 not used on the AVR.
2708 (define_insn "call_insn"
2709 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
2710 (match_operand:HI 1 "general_operand" "X,X,X,X"))]
2711 ;; We don't need in saving Z register because r30,r31 is a call used registers
2712 ;; Operand 1 not used on the AVR.
2713 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
2715 if (which_alternative==0)
2717 else if (which_alternative==1)
2720 return (AS2 (movw, r30, %0) CR_TAB
2723 return (AS2 (mov, r30, %A0) CR_TAB
2724 AS2 (mov, r31, %B0) CR_TAB
2727 else if (which_alternative==2)
2728 return AS1(%~call,%c0);
2729 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
2730 AS2 (ldi,r31,hi8(%0)) CR_TAB
2733 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2734 (set_attr_alternative "length"
2736 (if_then_else (eq_attr "mcu_have_movw" "yes")
2739 (if_then_else (eq_attr "mcu_mega" "yes")
2744 (define_insn "call_value_insn"
2745 [(set (match_operand 0 "register_operand" "=r,r,r,r")
2746 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
2747 ;; We don't need in saving Z register because r30,r31 is a call used registers
2748 (match_operand:HI 2 "general_operand" "X,X,X,X")))]
2749 ;; Operand 2 not used on the AVR.
2750 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
2752 if (which_alternative==0)
2754 else if (which_alternative==1)
2757 return (AS2 (movw, r30, %1) CR_TAB
2760 return (AS2 (mov, r30, %A1) CR_TAB
2761 AS2 (mov, r31, %B1) CR_TAB
2764 else if (which_alternative==2)
2765 return AS1(%~call,%c1);
2766 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
2767 AS2 (ldi, r31, hi8(%1)) CR_TAB
2770 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2771 (set_attr_alternative "length"
2773 (if_then_else (eq_attr "mcu_have_movw" "yes")
2776 (if_then_else (eq_attr "mcu_mega" "yes")
2785 [(set_attr "cc" "none")
2786 (set_attr "length" "1")])
2789 (define_insn "indirect_jump"
2790 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2791 "!AVR_HAVE_EIJMP_EICALL"
2794 push %A0\;push %B0\;ret"
2795 [(set_attr "length" "1,3")
2796 (set_attr "cc" "none,none")])
2798 (define_insn "*indirect_jump_avr6"
2799 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
2800 "AVR_HAVE_EIJMP_EICALL"
2802 [(set_attr "length" "1")
2803 (set_attr "cc" "none")])
2807 ;; Table made from "rjmp" instructions for <=8K devices.
2808 (define_insn "*tablejump_rjmp"
2809 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
2811 (use (label_ref (match_operand 1 "" "")))
2812 (clobber (match_dup 0))]
2813 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
2816 push %A0\;push %B0\;ret"
2817 [(set_attr "length" "1,3")
2818 (set_attr "cc" "none,none")])
2820 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2821 (define_insn "*tablejump_lib"
2822 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2824 (use (label_ref (match_operand 1 "" "")))
2825 (clobber (match_dup 0))]
2826 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2827 "jmp __tablejump2__"
2828 [(set_attr "length" "2")
2829 (set_attr "cc" "clobber")])
2831 (define_insn "*tablejump_enh"
2832 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2834 (use (label_ref (match_operand 1 "" "")))
2835 (clobber (match_dup 0))]
2836 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
2843 [(set_attr "length" "6")
2844 (set_attr "cc" "clobber")])
2846 (define_insn "*tablejump"
2847 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2849 (use (label_ref (match_operand 1 "" "")))
2850 (clobber (match_dup 0))]
2851 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
2860 [(set_attr "length" "8")
2861 (set_attr "cc" "clobber")])
2863 (define_expand "casesi"
2865 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2866 (match_operand:HI 1 "register_operand" "")))
2867 (parallel [(set (cc0)
2868 (compare (match_dup 6)
2869 (match_operand:HI 2 "register_operand" "")))
2870 (clobber (match_scratch:QI 9 ""))])
2873 (if_then_else (gtu (cc0)
2875 (label_ref (match_operand 4 "" ""))
2879 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2881 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
2882 (use (label_ref (match_dup 3)))
2883 (clobber (match_dup 6))])]
2887 operands[6] = gen_reg_rtx (HImode);
2891 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2892 ;; This instruction sets Z flag
2895 [(set (cc0) (const_int 0))]
2898 [(set_attr "length" "1")
2899 (set_attr "cc" "compare")])
2901 ;; Clear/set/test a single bit in I/O address space.
2904 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2905 (and:QI (mem:QI (match_dup 0))
2906 (match_operand:QI 1 "single_zero_operand" "n")))]
2909 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2910 return AS2 (cbi,%0-0x20,%2);
2912 [(set_attr "length" "1")
2913 (set_attr "cc" "none")])
2916 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2917 (ior:QI (mem:QI (match_dup 0))
2918 (match_operand:QI 1 "single_one_operand" "n")))]
2921 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2922 return AS2 (sbi,%0-0x20,%2);
2924 [(set_attr "length" "1")
2925 (set_attr "cc" "none")])
2927 ;; Lower half of the I/O space - use sbic/sbis directly.
2928 (define_insn "*sbix_branch"
2931 (match_operator 0 "eqne_operator"
2933 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
2935 (match_operand 2 "const_int_operand" "n"))
2937 (label_ref (match_operand 3 "" ""))
2940 "* return avr_out_sbxx_branch (insn, operands);"
2941 [(set (attr "length")
2942 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2943 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2945 (if_then_else (eq_attr "mcu_mega" "no")
2948 (set_attr "cc" "clobber")])
2950 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
2951 (define_insn "*sbix_branch_bit7"
2954 (match_operator 0 "gelt_operator"
2955 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
2957 (label_ref (match_operand 2 "" ""))
2961 operands[3] = operands[2];
2962 operands[2] = GEN_INT (7);
2963 return avr_out_sbxx_branch (insn, operands);
2965 [(set (attr "length")
2966 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2967 (le (minus (pc) (match_dup 2)) (const_int 2046)))
2969 (if_then_else (eq_attr "mcu_mega" "no")
2972 (set_attr "cc" "clobber")])
2974 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
2975 (define_insn "*sbix_branch_tmp"
2978 (match_operator 0 "eqne_operator"
2980 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
2982 (match_operand 2 "const_int_operand" "n"))
2984 (label_ref (match_operand 3 "" ""))
2987 "* return avr_out_sbxx_branch (insn, operands);"
2988 [(set (attr "length")
2989 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2990 (le (minus (pc) (match_dup 3)) (const_int 2045)))
2992 (if_then_else (eq_attr "mcu_mega" "no")
2995 (set_attr "cc" "clobber")])
2997 (define_insn "*sbix_branch_tmp_bit7"
3000 (match_operator 0 "gelt_operator"
3001 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
3003 (label_ref (match_operand 2 "" ""))
3007 operands[3] = operands[2];
3008 operands[2] = GEN_INT (7);
3009 return avr_out_sbxx_branch (insn, operands);
3011 [(set (attr "length")
3012 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
3013 (le (minus (pc) (match_dup 2)) (const_int 2045)))
3015 (if_then_else (eq_attr "mcu_mega" "no")
3018 (set_attr "cc" "clobber")])
3020 ;; ************************* Peepholes ********************************
3023 [(set (match_operand:SI 0 "d_register_operand" "")
3024 (plus:SI (match_dup 0)
3028 (compare (match_dup 0)
3030 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3032 (if_then_else (ne (cc0) (const_int 0))
3033 (label_ref (match_operand 2 "" ""))
3039 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3040 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
3041 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3042 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3044 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3045 AS2 (sbc,%B0,__zero_reg__) CR_TAB
3046 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3047 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3048 switch (avr_jump_mode (operands[2],insn))
3051 return AS1 (brcc,%2);
3053 return (AS1 (brcs,.+2) CR_TAB
3056 return (AS1 (brcs,.+4) CR_TAB
3061 [(set (match_operand:HI 0 "d_register_operand" "")
3062 (plus:HI (match_dup 0)
3066 (compare (match_dup 0)
3068 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3070 (if_then_else (ne (cc0) (const_int 0))
3071 (label_ref (match_operand 2 "" ""))
3077 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3078 output_asm_insn (AS2 (sbiw,%0,1), operands);
3080 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3081 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
3082 switch (avr_jump_mode (operands[2],insn))
3085 return AS1 (brcc,%2);
3087 return (AS1 (brcs,.+2) CR_TAB
3090 return (AS1 (brcs,.+4) CR_TAB
3095 [(set (match_operand:QI 0 "d_register_operand" "")
3096 (plus:QI (match_dup 0)
3099 (compare (match_dup 0)
3102 (if_then_else (ne (cc0) (const_int 0))
3103 (label_ref (match_operand 1 "" ""))
3109 cc_status.value1 = operands[0];
3110 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
3111 output_asm_insn (AS2 (subi,%A0,1), operands);
3112 switch (avr_jump_mode (operands[1],insn))
3115 return AS1 (brcc,%1);
3117 return (AS1 (brcs,.+2) CR_TAB
3120 return (AS1 (brcs,.+4) CR_TAB
3126 (compare (match_operand:QI 0 "register_operand" "")
3129 (if_then_else (eq (cc0) (const_int 0))
3130 (label_ref (match_operand 1 "" ""))
3132 "jump_over_one_insn_p (insn, operands[1])"
3133 "cpse %0,__zero_reg__")
3137 (compare (match_operand:QI 0 "register_operand" "")
3138 (match_operand:QI 1 "register_operand" "")))
3140 (if_then_else (eq (cc0) (const_int 0))
3141 (label_ref (match_operand 2 "" ""))
3143 "jump_over_one_insn_p (insn, operands[2])"
3146 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
3147 ;;prologue/epilogue support instructions
3149 (define_insn "popqi"
3150 [(set (match_operand:QI 0 "register_operand" "=r")
3151 (mem:QI (post_inc (reg:HI REG_SP))))]
3154 [(set_attr "cc" "none")
3155 (set_attr "length" "1")])
3157 (define_insn "pophi"
3158 [(set (match_operand:HI 0 "register_operand" "=r")
3159 (mem:HI (post_inc (reg:HI REG_SP))))]
3162 [(set_attr "cc" "none")
3163 (set_attr "length" "2")])
3165 ;; Enable Interrupts
3166 (define_insn "enable_interrupt"
3167 [(unspec [(const_int 0)] UNSPEC_SEI)]
3170 [(set_attr "length" "1")
3171 (set_attr "cc" "none")
3174 ;; Disable Interrupts
3175 (define_insn "disable_interrupt"
3176 [(unspec [(const_int 0)] UNSPEC_CLI)]
3179 [(set_attr "length" "1")
3180 (set_attr "cc" "none")
3183 ;; Library prologue saves
3184 (define_insn "call_prologue_saves"
3185 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
3186 (match_operand:HI 0 "immediate_operand" "")
3187 (set (reg:HI REG_SP) (minus:HI
3189 (match_operand:HI 1 "immediate_operand" "")))
3190 (use (reg:HI REG_X))
3191 (clobber (reg:HI REG_Z))]
3193 "ldi r30,lo8(gs(1f))
3195 %~jmp __prologue_saves__+((18 - %0) * 2)
3197 [(set_attr_alternative "length"
3198 [(if_then_else (eq_attr "mcu_mega" "yes")
3201 (set_attr "cc" "clobber")
3204 ; epilogue restores using library
3205 (define_insn "epilogue_restores"
3206 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
3207 (set (reg:HI REG_Y ) (plus:HI
3209 (match_operand:HI 0 "immediate_operand" "")))
3210 (set (reg:HI REG_SP) (reg:HI REG_Y))
3211 (clobber (reg:QI REG_Z))]
3214 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
3215 [(set_attr_alternative "length"
3216 [(if_then_else (eq_attr "mcu_mega" "yes")
3219 (set_attr "cc" "clobber")
3223 (define_insn "return"
3225 "reload_completed && avr_simple_epilogue ()"
3227 [(set_attr "cc" "none")
3228 (set_attr "length" "1")])
3230 (define_insn "return_from_epilogue"
3234 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
3235 && !cfun->machine->is_naked)"
3237 [(set_attr "cc" "none")
3238 (set_attr "length" "1")])
3240 (define_insn "return_from_interrupt_epilogue"
3244 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
3245 && !cfun->machine->is_naked)"
3247 [(set_attr "cc" "none")
3248 (set_attr "length" "1")])
3250 (define_insn "return_from_naked_epilogue"
3254 && cfun->machine->is_naked)"
3256 [(set_attr "cc" "none")
3257 (set_attr "length" "0")])
3259 (define_expand "prologue"
3268 (define_expand "epilogue"