1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004, 2007, 2008 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
29 return (GET_CODE (op) == REG
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
35 (define_predicate "arm_hard_register_operand"
38 return REGNO (op) < FIRST_PSEUDO_REGISTER;
42 (define_predicate "low_register_operand"
43 (and (match_code "reg")
44 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
46 ;; A low register or const_int.
47 (define_predicate "low_reg_or_int_operand"
48 (ior (match_code "const_int")
49 (match_operand 0 "low_register_operand")))
51 ;; Any core register, or any pseudo. */
52 (define_predicate "arm_general_register_operand"
53 (match_code "reg,subreg")
55 if (GET_CODE (op) == SUBREG)
58 return (GET_CODE (op) == REG
59 && (REGNO (op) <= LAST_ARM_REGNUM
60 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
63 (define_predicate "f_register_operand"
64 (match_code "reg,subreg")
66 if (GET_CODE (op) == SUBREG)
69 /* We don't consider registers whose class is NO_REGS
70 to be a register operand. */
71 return (GET_CODE (op) == REG
72 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
73 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
76 (define_special_predicate "subreg_lowpart_operator"
77 (and (match_code "subreg")
78 (match_test "subreg_lowpart_p (op)")))
80 ;; Reg, subreg(reg) or const_int.
81 (define_predicate "reg_or_int_operand"
82 (ior (match_code "const_int")
83 (match_operand 0 "s_register_operand")))
85 (define_predicate "arm_immediate_operand"
86 (and (match_code "const_int")
87 (match_test "const_ok_for_arm (INTVAL (op))")))
89 (define_predicate "arm_neg_immediate_operand"
90 (and (match_code "const_int")
91 (match_test "const_ok_for_arm (-INTVAL (op))")))
93 (define_predicate "arm_not_immediate_operand"
94 (and (match_code "const_int")
95 (match_test "const_ok_for_arm (~INTVAL (op))")))
97 ;; Something valid on the RHS of an ARM data-processing instruction
98 (define_predicate "arm_rhs_operand"
99 (ior (match_operand 0 "s_register_operand")
100 (match_operand 0 "arm_immediate_operand")))
102 (define_predicate "arm_rhsm_operand"
103 (ior (match_operand 0 "arm_rhs_operand")
104 (match_operand 0 "memory_operand")))
106 (define_predicate "arm_add_operand"
107 (ior (match_operand 0 "arm_rhs_operand")
108 (match_operand 0 "arm_neg_immediate_operand")))
110 (define_predicate "arm_addimm_operand"
111 (ior (match_operand 0 "arm_immediate_operand")
112 (match_operand 0 "arm_neg_immediate_operand")))
114 (define_predicate "arm_not_operand"
115 (ior (match_operand 0 "arm_rhs_operand")
116 (match_operand 0 "arm_not_immediate_operand")))
118 ;; True if the operand is a memory reference which contains an
119 ;; offsettable address.
120 (define_predicate "offsettable_memory_operand"
121 (and (match_code "mem")
123 "offsettable_address_p (reload_completed | reload_in_progress,
124 mode, XEXP (op, 0))")))
126 ;; True if the operand is a memory operand that does not have an
127 ;; automodified base register (and thus will not generate output reloads).
128 (define_predicate "call_memory_operand"
129 (and (match_code "mem")
130 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
132 (match_operand 0 "memory_operand"))))
134 (define_predicate "arm_reload_memory_operand"
135 (and (match_code "mem,reg,subreg")
136 (match_test "(!CONSTANT_P (op)
137 && (true_regnum(op) == -1
138 || (GET_CODE (op) == REG
139 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
141 ;; True for valid operands for the rhs of an floating point insns.
142 ;; Allows regs or certain consts on FPA, just regs for everything else.
143 (define_predicate "arm_float_rhs_operand"
144 (ior (match_operand 0 "s_register_operand")
145 (and (match_code "const_double")
146 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
148 (define_predicate "arm_float_add_operand"
149 (ior (match_operand 0 "arm_float_rhs_operand")
150 (and (match_code "const_double")
151 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
153 (define_predicate "vfp_compare_operand"
154 (ior (match_operand 0 "s_register_operand")
155 (and (match_code "const_double")
156 (match_test "arm_const_double_rtx (op)"))))
158 (define_predicate "arm_float_compare_operand"
159 (if_then_else (match_test "TARGET_VFP")
160 (match_operand 0 "vfp_compare_operand")
161 (match_operand 0 "arm_float_rhs_operand")))
163 ;; True for valid index operands.
164 (define_predicate "index_operand"
165 (ior (match_operand 0 "s_register_operand")
166 (and (match_operand 0 "immediate_operand")
167 (match_test "(GET_CODE (op) != CONST_INT
168 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
170 ;; True for operators that can be combined with a shift in ARM state.
171 (define_special_predicate "shiftable_operator"
172 (and (match_code "plus,minus,ior,xor,and")
173 (match_test "mode == GET_MODE (op)")))
175 ;; True for logical binary operators.
176 (define_special_predicate "logical_binary_operator"
177 (and (match_code "ior,xor,and")
178 (match_test "mode == GET_MODE (op)")))
180 ;; True for shift operators.
181 (define_special_predicate "shift_operator"
182 (and (ior (ior (and (match_code "mult")
183 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
184 (and (match_code "rotate")
185 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
186 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
187 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
188 (match_test "mode == GET_MODE (op)")))
190 ;; True for operators that have 16-bit thumb variants. */
191 (define_special_predicate "thumb_16bit_operator"
192 (match_code "plus,minus,and,ior,xor"))
195 (define_special_predicate "equality_operator"
196 (match_code "eq,ne"))
198 ;; True for integer comparisons and, if FP is active, for comparisons
199 ;; other than LTGT or UNEQ.
200 (define_special_predicate "arm_comparison_operator"
201 (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
202 (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
203 && (TARGET_FPA || TARGET_VFP)")
204 (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
206 (define_special_predicate "minmax_operator"
207 (and (match_code "smin,smax,umin,umax")
208 (match_test "mode == GET_MODE (op)")))
210 (define_special_predicate "cc_register"
211 (and (match_code "reg")
212 (and (match_test "REGNO (op) == CC_REGNUM")
213 (ior (match_test "mode == GET_MODE (op)")
214 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
216 (define_special_predicate "dominant_cc_register"
219 if (mode == VOIDmode)
221 mode = GET_MODE (op);
223 if (GET_MODE_CLASS (mode) != MODE_CC)
227 return (cc_register (op, mode)
228 && (mode == CC_DNEmode
229 || mode == CC_DEQmode
230 || mode == CC_DLEmode
231 || mode == CC_DLTmode
232 || mode == CC_DGEmode
233 || mode == CC_DGTmode
234 || mode == CC_DLEUmode
235 || mode == CC_DLTUmode
236 || mode == CC_DGEUmode
237 || mode == CC_DGTUmode));
240 (define_special_predicate "arm_extendqisi_mem_op"
241 (and (match_operand 0 "memory_operand")
242 (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
245 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
246 (ior (match_operand 0 "arm_extendqisi_mem_op")
247 (match_operand 0 "s_register_operand")))
249 (define_predicate "power_of_two_operand"
250 (match_code "const_int")
252 HOST_WIDE_INT value = INTVAL (op);
254 return value != 0 && (value & (value - 1)) == 0;
257 (define_predicate "nonimmediate_di_operand"
258 (match_code "reg,subreg,mem")
260 if (s_register_operand (op, mode))
263 if (GET_CODE (op) == SUBREG)
264 op = SUBREG_REG (op);
266 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
269 (define_predicate "di_operand"
270 (ior (match_code "const_int,const_double")
271 (and (match_code "reg,subreg,mem")
272 (match_operand 0 "nonimmediate_di_operand"))))
274 (define_predicate "nonimmediate_soft_df_operand"
275 (match_code "reg,subreg,mem")
277 if (s_register_operand (op, mode))
280 if (GET_CODE (op) == SUBREG)
281 op = SUBREG_REG (op);
283 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
286 (define_predicate "soft_df_operand"
287 (ior (match_code "const_double")
288 (and (match_code "reg,subreg,mem")
289 (match_operand 0 "nonimmediate_soft_df_operand"))))
291 (define_predicate "const_shift_operand"
292 (and (match_code "const_int")
293 (ior (match_operand 0 "power_of_two_operand")
294 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
297 (define_special_predicate "load_multiple_operation"
298 (match_code "parallel")
300 HOST_WIDE_INT count = XVECLEN (op, 0);
303 HOST_WIDE_INT i = 1, base = 0;
307 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
310 /* Check to see if this might be a write-back. */
311 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
316 /* Now check it more carefully. */
317 if (GET_CODE (SET_DEST (elt)) != REG
318 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
319 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
320 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
324 /* Perform a quick check so we don't blow up below. */
326 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
327 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
328 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
331 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
332 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
334 for (; i < count; i++)
336 elt = XVECEXP (op, 0, i);
338 if (GET_CODE (elt) != SET
339 || GET_CODE (SET_DEST (elt)) != REG
340 || GET_MODE (SET_DEST (elt)) != SImode
341 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
342 || GET_CODE (SET_SRC (elt)) != MEM
343 || GET_MODE (SET_SRC (elt)) != SImode
344 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
345 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
346 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
347 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
354 (define_special_predicate "store_multiple_operation"
355 (match_code "parallel")
357 HOST_WIDE_INT count = XVECLEN (op, 0);
360 HOST_WIDE_INT i = 1, base = 0;
364 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
367 /* Check to see if this might be a write-back. */
368 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
373 /* Now check it more carefully. */
374 if (GET_CODE (SET_DEST (elt)) != REG
375 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
376 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
377 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
381 /* Perform a quick check so we don't blow up below. */
383 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
384 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
385 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
388 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
389 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
391 for (; i < count; i++)
393 elt = XVECEXP (op, 0, i);
395 if (GET_CODE (elt) != SET
396 || GET_CODE (SET_SRC (elt)) != REG
397 || GET_MODE (SET_SRC (elt)) != SImode
398 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
399 || GET_CODE (SET_DEST (elt)) != MEM
400 || GET_MODE (SET_DEST (elt)) != SImode
401 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
402 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
403 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
404 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
411 (define_special_predicate "multi_register_push"
412 (match_code "parallel")
414 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
415 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
416 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
422 ;;-------------------------------------------------------------------------
427 (define_predicate "thumb1_cmp_operand"
428 (ior (and (match_code "reg,subreg")
429 (match_operand 0 "s_register_operand"))
430 (and (match_code "const_int")
431 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
433 (define_predicate "thumb1_cmpneg_operand"
434 (and (match_code "const_int")
435 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
437 ;; Return TRUE if a result can be stored in OP without clobbering the
438 ;; condition code register. Prior to reload we only accept a
439 ;; register. After reload we have to be able to handle memory as
440 ;; well, since a pseudo may not get a hard reg and reload cannot
441 ;; handle output-reloads on jump insns.
443 ;; We could possibly handle mem before reload as well, but that might
444 ;; complicate things with the need to handle increment
446 (define_predicate "thumb_cbrch_target_operand"
447 (and (match_code "reg,subreg,mem")
448 (ior (match_operand 0 "s_register_operand")
449 (and (match_test "reload_in_progress || reload_completed")
450 (match_operand 0 "memory_operand")))))
452 ;;-------------------------------------------------------------------------
454 ;; MAVERICK predicates
457 (define_predicate "cirrus_register_operand"
458 (match_code "reg,subreg")
460 if (GET_CODE (op) == SUBREG)
461 op = SUBREG_REG (op);
463 return (GET_CODE (op) == REG
464 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
465 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
468 (define_predicate "cirrus_fp_register"
469 (match_code "reg,subreg")
471 if (GET_CODE (op) == SUBREG)
472 op = SUBREG_REG (op);
474 return (GET_CODE (op) == REG
475 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
476 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
479 (define_predicate "cirrus_shift_const"
480 (and (match_code "const_int")
481 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
486 (define_predicate "const_multiple_of_8_operand"
487 (match_code "const_int")
489 unsigned HOST_WIDE_INT val = INTVAL (op);
490 return (val & 7) == 0;
493 (define_predicate "imm_for_neon_mov_operand"
494 (match_code "const_vector")
496 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
499 (define_predicate "imm_for_neon_logic_operand"
500 (match_code "const_vector")
502 return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
505 (define_predicate "imm_for_neon_inv_logic_operand"
506 (match_code "const_vector")
508 return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
511 (define_predicate "neon_logic_op2"
512 (ior (match_operand 0 "imm_for_neon_logic_operand")
513 (match_operand 0 "s_register_operand")))
515 (define_predicate "neon_inv_logic_op2"
516 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
517 (match_operand 0 "s_register_operand")))
519 ;; TODO: We could check lane numbers more precisely based on the mode.
520 (define_predicate "neon_lane_number"
521 (and (match_code "const_int")
522 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))