gcc/config/arm/iwmmxt.md

   1 ;; ??? This file needs auditing for thumb2
   2 ;; Patterns for the Intel Wireless MMX technology architecture.
   3 ;; Copyright (C) 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it under
   9 ;; the terms of the GNU General Public License as published by the Free
  10 ;; Software Foundation; either version 3, or (at your option) any later
  11 ;; version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22
  23 (define_insn "iwmmxt_iordi3"
  24   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  25         (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  26                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  27   "TARGET_REALLY_IWMMXT"
  28   "@
  29    wor%?\\t%0, %1, %2
  30    #
  31    #"
  32   [(set_attr "predicable" "yes")
  33    (set_attr "length" "4,8,8")])
  34
  35 (define_insn "iwmmxt_xordi3"
  36   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  37         (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  38                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  39   "TARGET_REALLY_IWMMXT"
  40   "@
  41    wxor%?\\t%0, %1, %2
  42    #
  43    #"
  44   [(set_attr "predicable" "yes")
  45    (set_attr "length" "4,8,8")])
  46
  47 (define_insn "iwmmxt_anddi3"
  48   [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
  49         (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
  50                 (match_operand:DI 2 "register_operand"  "y,r,r")))]
  51   "TARGET_REALLY_IWMMXT"
  52   "@
  53    wand%?\\t%0, %1, %2
  54    #
  55    #"
  56   [(set_attr "predicable" "yes")
  57    (set_attr "length" "4,8,8")])
  58
  59 (define_insn "iwmmxt_nanddi3"
  60   [(set (match_operand:DI                 0 "register_operand" "=y")
  61         (and:DI (match_operand:DI         1 "register_operand"  "y")
  62                 (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
  63   "TARGET_REALLY_IWMMXT"
  64   "wandn%?\\t%0, %1, %2"
  65   [(set_attr "predicable" "yes")])
  66
  67 (define_insn "*iwmmxt_arm_movdi"
  68   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
  69         (match_operand:DI 1 "di_operand"              "rIK,mi,r,y,yr,y,yrUy,y"))]
  70   "TARGET_REALLY_IWMMXT
  71    && (   register_operand (operands[0], DImode)
  72        || register_operand (operands[1], DImode))"
  73   "*
  74 {
  75   switch (which_alternative)
  76     {
  77     default:
  78       return output_move_double (operands);
  79     case 0:
  80       return \"#\";
  81     case 3:
  82       return \"wmov%?\\t%0,%1\";
  83     case 4:
  84       return \"tmcrr%?\\t%0,%Q1,%R1\";
  85     case 5:
  86       return \"tmrrc%?\\t%Q0,%R0,%1\";
  87     case 6:
  88       return \"wldrd%?\\t%0,%1\";
  89     case 7:
  90       return \"wstrd%?\\t%1,%0\";
  91     }
  92 }"
  93   [(set_attr "length"         "8,8,8,4,4,4,4,4")
  94    (set_attr "type"           "*,load1,store2,*,*,*,*,*")
  95    (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
  96    (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
  97 )
  98
  99 (define_insn "*iwmmxt_movsi_insn"
 100   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,rk, m,z,r,?z,Uy,z")
 101         (match_operand:SI 1 "general_operand"      "rk, I,K,mi,rk,r,z,Uy,z, z"))]
 102   "TARGET_REALLY_IWMMXT
 103    && (   register_operand (operands[0], SImode)
 104        || register_operand (operands[1], SImode))"
 105   "*
 106    switch (which_alternative)
 107    {
 108    case 0: return \"mov\\t%0, %1\";
 109    case 1: return \"mov\\t%0, %1\";
 110    case 2: return \"mvn\\t%0, #%B1\";
 111    case 3: return \"ldr\\t%0, %1\";
 112    case 4: return \"str\\t%1, %0\";
 113    case 5: return \"tmcr\\t%0, %1\";
 114    case 6: return \"tmrc\\t%0, %1\";
 115    case 7: return arm_output_load_gr (operands);
 116    case 8: return \"wstrw\\t%1, %0\";
 117    default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
 118   }"
 119   [(set_attr "type"           "*,*,*,load1,store1,*,*,load1,store1,*")
 120    (set_attr "length"         "*,*,*,*,        *,*,*,  16,     *,8")
 121    (set_attr "pool_range"     "*,*,*,4096,     *,*,*,1024,     *,*")
 122    (set_attr "neg_pool_range" "*,*,*,4084,     *,*,*,   *,  1012,*")
 123    ;; Note - the "predicable" attribute is not allowed to have alternatives.
 124    ;; Since the wSTRw wCx instruction is not predicable, we cannot support
 125    ;; predicating any of the alternatives in this template.  Instead,
 126    ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
 127    (set_attr "predicable"     "no")
 128    ;; Also - we have to pretend that these insns clobber the condition code
 129    ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
 130    ;; them.
 131    (set_attr "conds" "clob")]
 132 )
 133
 134 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
 135 ;; cond_exec version explicitly, with appropriate constraints.
 136
 137 (define_insn "*cond_iwmmxt_movsi_insn"
 138   [(cond_exec
 139      (match_operator 2 "arm_comparison_operator"
 140       [(match_operand 3 "cc_register" "")
 141       (const_int 0)])
 142      (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
 143           (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
 144   "TARGET_REALLY_IWMMXT
 145    && (   register_operand (operands[0], SImode)
 146        || register_operand (operands[1], SImode))"
 147   "*
 148    switch (which_alternative)
 149    {
 150    case 0: return \"mov%?\\t%0, %1\";
 151    case 1: return \"mvn%?\\t%0, #%B1\";
 152    case 2: return \"ldr%?\\t%0, %1\";
 153    case 3: return \"str%?\\t%1, %0\";
 154    case 4: return \"tmcr%?\\t%0, %1\";
 155    default: return \"tmrc%?\\t%0, %1\";
 156   }"
 157   [(set_attr "type"           "*,*,load1,store1,*,*")
 158    (set_attr "pool_range"     "*,*,4096,     *,*,*")
 159    (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
 160 )
 161
 162 (define_insn "mov<mode>_internal"
 163   [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
 164         (match_operand:VMMX 1 "general_operand"       "y,y,mi,y,r,r,mi,r"))]
 165   "TARGET_REALLY_IWMMXT"
 166   "*
 167    switch (which_alternative)
 168    {
 169    case 0: return \"wmov%?\\t%0, %1\";
 170    case 1: return \"wstrd%?\\t%1, %0\";
 171    case 2: return \"wldrd%?\\t%0, %1\";
 172    case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
 173    case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
 174    case 5: return \"#\";
 175    default: return output_move_double (operands);
 176    }"
 177   [(set_attr "predicable" "yes")
 178    (set_attr "length"         "4,     4,   4,4,4,8,   8,8")
 179    (set_attr "type"           "*,store1,load1,*,*,*,load1,store1")
 180    (set_attr "pool_range"     "*,     *, 256,*,*,*, 256,*")
 181    (set_attr "neg_pool_range" "*,     *, 244,*,*,*, 244,*")])
 182
 183 ;; Vector add/subtract
 184
 185 (define_insn "*add<mode>3_iwmmxt"
 186   [(set (match_operand:VMMX            0 "register_operand" "=y")
 187         (plus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 188                    (match_operand:VMMX 2 "register_operand"  "y")))]
 189   "TARGET_REALLY_IWMMXT"
 190   "wadd<MMX_char>%?\\t%0, %1, %2"
 191   [(set_attr "predicable" "yes")])
 192
 193 (define_insn "ssaddv8qi3"
 194   [(set (match_operand:V8QI               0 "register_operand" "=y")
 195         (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 196                       (match_operand:V8QI 2 "register_operand"  "y")))]
 197   "TARGET_REALLY_IWMMXT"
 198   "waddbss%?\\t%0, %1, %2"
 199   [(set_attr "predicable" "yes")])
 200
 201 (define_insn "ssaddv4hi3"
 202   [(set (match_operand:V4HI               0 "register_operand" "=y")
 203         (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 204                       (match_operand:V4HI 2 "register_operand"  "y")))]
 205   "TARGET_REALLY_IWMMXT"
 206   "waddhss%?\\t%0, %1, %2"
 207   [(set_attr "predicable" "yes")])
 208
 209 (define_insn "ssaddv2si3"
 210   [(set (match_operand:V2SI               0 "register_operand" "=y")
 211         (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 212                       (match_operand:V2SI 2 "register_operand"  "y")))]
 213   "TARGET_REALLY_IWMMXT"
 214   "waddwss%?\\t%0, %1, %2"
 215   [(set_attr "predicable" "yes")])
 216
 217 (define_insn "usaddv8qi3"
 218   [(set (match_operand:V8QI               0 "register_operand" "=y")
 219         (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 220                       (match_operand:V8QI 2 "register_operand"  "y")))]
 221   "TARGET_REALLY_IWMMXT"
 222   "waddbus%?\\t%0, %1, %2"
 223   [(set_attr "predicable" "yes")])
 224
 225 (define_insn "usaddv4hi3"
 226   [(set (match_operand:V4HI               0 "register_operand" "=y")
 227         (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
 228                       (match_operand:V4HI 2 "register_operand"  "y")))]
 229   "TARGET_REALLY_IWMMXT"
 230   "waddhus%?\\t%0, %1, %2"
 231   [(set_attr "predicable" "yes")])
 232
 233 (define_insn "usaddv2si3"
 234   [(set (match_operand:V2SI               0 "register_operand" "=y")
 235         (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
 236                       (match_operand:V2SI 2 "register_operand"  "y")))]
 237   "TARGET_REALLY_IWMMXT"
 238   "waddwus%?\\t%0, %1, %2"
 239   [(set_attr "predicable" "yes")])
 240
 241 (define_insn "*sub<mode>3_iwmmxt"
 242   [(set (match_operand:VMMX             0 "register_operand" "=y")
 243         (minus:VMMX (match_operand:VMMX 1 "register_operand"  "y")
 244                     (match_operand:VMMX 2 "register_operand"  "y")))]
 245   "TARGET_REALLY_IWMMXT"
 246   "wsub<MMX_char>%?\\t%0, %1, %2"
 247   [(set_attr "predicable" "yes")])
 248
 249 (define_insn "sssubv8qi3"
 250   [(set (match_operand:V8QI                0 "register_operand" "=y")
 251         (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
 252                        (match_operand:V8QI 2 "register_operand"  "y")))]
 253   "TARGET_REALLY_IWMMXT"
 254   "wsubbss%?\\t%0, %1, %2"
 255   [(set_attr "predicable" "yes")])
 256
 257 (define_insn "sssubv4hi3"
 258   [(set (match_operand:V4HI                0 "register_operand" "=y")
 259         (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 260                        (match_operand:V4HI 2 "register_operand" "y")))]
 261   "TARGET_REALLY_IWMMXT"
 262   "wsubhss%?\\t%0, %1, %2"
 263   [(set_attr "predicable" "yes")])
 264
 265 (define_insn "sssubv2si3"
 266   [(set (match_operand:V2SI                0 "register_operand" "=y")
 267         (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 268                        (match_operand:V2SI 2 "register_operand" "y")))]
 269   "TARGET_REALLY_IWMMXT"
 270   "wsubwss%?\\t%0, %1, %2"
 271   [(set_attr "predicable" "yes")])
 272
 273 (define_insn "ussubv8qi3"
 274   [(set (match_operand:V8QI                0 "register_operand" "=y")
 275         (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
 276                        (match_operand:V8QI 2 "register_operand" "y")))]
 277   "TARGET_REALLY_IWMMXT"
 278   "wsubbus%?\\t%0, %1, %2"
 279   [(set_attr "predicable" "yes")])
 280
 281 (define_insn "ussubv4hi3"
 282   [(set (match_operand:V4HI                0 "register_operand" "=y")
 283         (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
 284                        (match_operand:V4HI 2 "register_operand" "y")))]
 285   "TARGET_REALLY_IWMMXT"
 286   "wsubhus%?\\t%0, %1, %2"
 287   [(set_attr "predicable" "yes")])
 288
 289 (define_insn "ussubv2si3"
 290   [(set (match_operand:V2SI                0 "register_operand" "=y")
 291         (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
 292                        (match_operand:V2SI 2 "register_operand" "y")))]
 293   "TARGET_REALLY_IWMMXT"
 294   "wsubwus%?\\t%0, %1, %2"
 295   [(set_attr "predicable" "yes")])
 296
 297 (define_insn "*mulv4hi3_iwmmxt"
 298   [(set (match_operand:V4HI            0 "register_operand" "=y")
 299         (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
 300                    (match_operand:V4HI 2 "register_operand" "y")))]
 301   "TARGET_REALLY_IWMMXT"
 302   "wmulul%?\\t%0, %1, %2"
 303   [(set_attr "predicable" "yes")])
 304
 305 (define_insn "smulv4hi3_highpart"
 306   [(set (match_operand:V4HI                                0 "register_operand" "=y")
 307         (truncate:V4HI
 308          (lshiftrt:V4SI
 309           (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 310                      (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 311           (const_int 16))))]
 312   "TARGET_REALLY_IWMMXT"
 313   "wmulsm%?\\t%0, %1, %2"
 314   [(set_attr "predicable" "yes")])
 315
 316 (define_insn "umulv4hi3_highpart"
 317   [(set (match_operand:V4HI                                0 "register_operand" "=y")
 318         (truncate:V4HI
 319          (lshiftrt:V4SI
 320           (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
 321                      (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
 322           (const_int 16))))]
 323   "TARGET_REALLY_IWMMXT"
 324   "wmulum%?\\t%0, %1, %2"
 325   [(set_attr "predicable" "yes")])
 326
 327 (define_insn "iwmmxt_wmacs"
 328   [(set (match_operand:DI               0 "register_operand" "=y")
 329         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 330                     (match_operand:V4HI 2 "register_operand" "y")
 331                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
 332   "TARGET_REALLY_IWMMXT"
 333   "wmacs%?\\t%0, %2, %3"
 334   [(set_attr "predicable" "yes")])
 335
 336 (define_insn "iwmmxt_wmacsz"
 337   [(set (match_operand:DI               0 "register_operand" "=y")
 338         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 339                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
 340   "TARGET_REALLY_IWMMXT"
 341   "wmacsz%?\\t%0, %1, %2"
 342   [(set_attr "predicable" "yes")])
 343
 344 (define_insn "iwmmxt_wmacu"
 345   [(set (match_operand:DI               0 "register_operand" "=y")
 346         (unspec:DI [(match_operand:DI   1 "register_operand" "0")
 347                     (match_operand:V4HI 2 "register_operand" "y")
 348                     (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
 349   "TARGET_REALLY_IWMMXT"
 350   "wmacu%?\\t%0, %2, %3"
 351   [(set_attr "predicable" "yes")])
 352
 353 (define_insn "iwmmxt_wmacuz"
 354   [(set (match_operand:DI               0 "register_operand" "=y")
 355         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
 356                     (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
 357   "TARGET_REALLY_IWMMXT"
 358   "wmacuz%?\\t%0, %1, %2"
 359   [(set_attr "predicable" "yes")])
 360
 361 ;; Same as xordi3, but don't show input operands so that we don't think
 362 ;; they are live.
 363 (define_insn "iwmmxt_clrdi"
 364   [(set (match_operand:DI 0 "register_operand" "=y")
 365         (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
 366   "TARGET_REALLY_IWMMXT"
 367   "wxor%?\\t%0, %0, %0"
 368   [(set_attr "predicable" "yes")])
 369
 370 ;; Seems like cse likes to generate these, so we have to support them.
 371
 372 (define_insn "*iwmmxt_clrv8qi"
 373   [(set (match_operand:V8QI 0 "register_operand" "=y")
 374         (const_vector:V8QI [(const_int 0) (const_int 0)
 375                             (const_int 0) (const_int 0)
 376                             (const_int 0) (const_int 0)
 377                             (const_int 0) (const_int 0)]))]
 378   "TARGET_REALLY_IWMMXT"
 379   "wxor%?\\t%0, %0, %0"
 380   [(set_attr "predicable" "yes")])
 381
 382 (define_insn "*iwmmxt_clrv4hi"
 383   [(set (match_operand:V4HI 0 "register_operand" "=y")
 384         (const_vector:V4HI [(const_int 0) (const_int 0)
 385                             (const_int 0) (const_int 0)]))]
 386   "TARGET_REALLY_IWMMXT"
 387   "wxor%?\\t%0, %0, %0"
 388   [(set_attr "predicable" "yes")])
 389
 390 (define_insn "*iwmmxt_clrv2si"
 391   [(set (match_operand:V2SI 0 "register_operand" "=y")
 392         (const_vector:V2SI [(const_int 0) (const_int 0)]))]
 393   "TARGET_REALLY_IWMMXT"
 394   "wxor%?\\t%0, %0, %0"
 395   [(set_attr "predicable" "yes")])
 396
 397 ;; Unsigned averages/sum of absolute differences
 398
 399 (define_insn "iwmmxt_uavgrndv8qi3"
 400   [(set (match_operand:V8QI              0 "register_operand" "=y")
 401         (ashiftrt:V8QI
 402          (plus:V8QI (plus:V8QI
 403                      (match_operand:V8QI 1 "register_operand" "y")
 404                      (match_operand:V8QI 2 "register_operand" "y"))
 405                     (const_vector:V8QI [(const_int 1)
 406                                         (const_int 1)
 407                                         (const_int 1)
 408                                         (const_int 1)
 409                                         (const_int 1)
 410                                         (const_int 1)
 411                                         (const_int 1)
 412                                         (const_int 1)]))
 413          (const_int 1)))]
 414   "TARGET_REALLY_IWMMXT"
 415   "wavg2br%?\\t%0, %1, %2"
 416   [(set_attr "predicable" "yes")])
 417
 418 (define_insn "iwmmxt_uavgrndv4hi3"
 419   [(set (match_operand:V4HI              0 "register_operand" "=y")
 420         (ashiftrt:V4HI
 421          (plus:V4HI (plus:V4HI
 422                      (match_operand:V4HI 1 "register_operand" "y")
 423                      (match_operand:V4HI 2 "register_operand" "y"))
 424                     (const_vector:V4HI [(const_int 1)
 425                                         (const_int 1)
 426                                         (const_int 1)
 427                                         (const_int 1)]))
 428          (const_int 1)))]
 429   "TARGET_REALLY_IWMMXT"
 430   "wavg2hr%?\\t%0, %1, %2"
 431   [(set_attr "predicable" "yes")])
 432
 433
 434 (define_insn "iwmmxt_uavgv8qi3"
 435   [(set (match_operand:V8QI                 0 "register_operand" "=y")
 436         (ashiftrt:V8QI (plus:V8QI
 437                         (match_operand:V8QI 1 "register_operand" "y")
 438                         (match_operand:V8QI 2 "register_operand" "y"))
 439                        (const_int 1)))]
 440   "TARGET_REALLY_IWMMXT"
 441   "wavg2b%?\\t%0, %1, %2"
 442   [(set_attr "predicable" "yes")])
 443
 444 (define_insn "iwmmxt_uavgv4hi3"
 445   [(set (match_operand:V4HI                 0 "register_operand" "=y")
 446         (ashiftrt:V4HI (plus:V4HI
 447                         (match_operand:V4HI 1 "register_operand" "y")
 448                         (match_operand:V4HI 2 "register_operand" "y"))
 449                        (const_int 1)))]
 450   "TARGET_REALLY_IWMMXT"
 451   "wavg2h%?\\t%0, %1, %2"
 452   [(set_attr "predicable" "yes")])
 453
 454 (define_insn "iwmmxt_psadbw"
 455   [(set (match_operand:V8QI                       0 "register_operand" "=y")
 456         (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
 457                               (match_operand:V8QI 2 "register_operand" "y"))))]
 458   "TARGET_REALLY_IWMMXT"
 459   "psadbw%?\\t%0, %1, %2"
 460   [(set_attr "predicable" "yes")])
 461
 462
 463 ;; Insert/extract/shuffle
 464
 465 (define_insn "iwmmxt_tinsrb"
 466   [(set (match_operand:V8QI                             0 "register_operand"    "=y")
 467         (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
 468                         (vec_duplicate:V8QI
 469                          (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
 470                         (match_operand:SI               3 "immediate_operand"    "i")))]
 471   "TARGET_REALLY_IWMMXT"
 472   "tinsrb%?\\t%0, %2, %3"
 473   [(set_attr "predicable" "yes")])
 474
 475 (define_insn "iwmmxt_tinsrh"
 476   [(set (match_operand:V4HI                             0 "register_operand"    "=y")
 477         (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
 478                         (vec_duplicate:V4HI
 479                          (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
 480                         (match_operand:SI               3 "immediate_operand"    "i")))]
 481   "TARGET_REALLY_IWMMXT"
 482   "tinsrh%?\\t%0, %2, %3"
 483   [(set_attr "predicable" "yes")])
 484
 485 (define_insn "iwmmxt_tinsrw"
 486   [(set (match_operand:V2SI                 0 "register_operand"    "=y")
 487         (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
 488                         (vec_duplicate:V2SI
 489                          (match_operand:SI  2 "nonimmediate_operand" "r"))
 490                         (match_operand:SI   3 "immediate_operand"    "i")))]
 491   "TARGET_REALLY_IWMMXT"
 492   "tinsrw%?\\t%0, %2, %3"
 493   [(set_attr "predicable" "yes")])
 494
 495 (define_insn "iwmmxt_textrmub"
 496   [(set (match_operand:SI                                  0 "register_operand" "=r")
 497         (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
 498                                        (parallel
 499                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 500   "TARGET_REALLY_IWMMXT"
 501   "textrmub%?\\t%0, %1, %2"
 502   [(set_attr "predicable" "yes")])
 503
 504 (define_insn "iwmmxt_textrmsb"
 505   [(set (match_operand:SI                                  0 "register_operand" "=r")
 506         (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
 507                                        (parallel
 508                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 509   "TARGET_REALLY_IWMMXT"
 510   "textrmsb%?\\t%0, %1, %2"
 511   [(set_attr "predicable" "yes")])
 512
 513 (define_insn "iwmmxt_textrmuh"
 514   [(set (match_operand:SI                                  0 "register_operand" "=r")
 515         (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
 516                                        (parallel
 517                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 518   "TARGET_REALLY_IWMMXT"
 519   "textrmuh%?\\t%0, %1, %2"
 520   [(set_attr "predicable" "yes")])
 521
 522 (define_insn "iwmmxt_textrmsh"
 523   [(set (match_operand:SI                                  0 "register_operand" "=r")
 524         (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
 525                                        (parallel
 526                                         [(match_operand:SI 2 "immediate_operand" "i")]))))]
 527   "TARGET_REALLY_IWMMXT"
 528   "textrmsh%?\\t%0, %1, %2"
 529   [(set_attr "predicable" "yes")])
 530
 531 ;; There are signed/unsigned variants of this instruction, but they are
 532 ;; pointless.
 533 (define_insn "iwmmxt_textrmw"
 534   [(set (match_operand:SI                           0 "register_operand" "=r")
 535         (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
 536                        (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
 537   "TARGET_REALLY_IWMMXT"
 538   "textrmsw%?\\t%0, %1, %2"
 539   [(set_attr "predicable" "yes")])
 540
 541 (define_insn "iwmmxt_wshufh"
 542   [(set (match_operand:V4HI               0 "register_operand" "=y")
 543         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
 544                       (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
 545   "TARGET_REALLY_IWMMXT"
 546   "wshufh%?\\t%0, %1, %2"
 547   [(set_attr "predicable" "yes")])
 548
 549 ;; Mask-generating comparisons
 550 ;;
 551 ;; Note - you cannot use patterns like these here:
 552 ;;
 553 ;;   (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
 554 ;;
 555 ;; Because GCC will assume that the truth value (1 or 0) is installed
 556 ;; into the entire destination vector, (with the '1' going into the least
 557 ;; significant element of the vector).  This is not how these instructions
 558 ;; behave.
 559 ;;
 560 ;; Unfortunately the current patterns are illegal.  They are SET insns
 561 ;; without a SET in them.  They work in most cases for ordinary code
 562 ;; generation, but there are circumstances where they can cause gcc to fail.
 563 ;; XXX - FIXME.
 564
 565 (define_insn "eqv8qi3"
 566   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 567                      (match_operand:V8QI 1 "register_operand"  "y")
 568                      (match_operand:V8QI 2 "register_operand"  "y")]
 569                     VUNSPEC_WCMP_EQ)]
 570   "TARGET_REALLY_IWMMXT"
 571   "wcmpeqb%?\\t%0, %1, %2"
 572   [(set_attr "predicable" "yes")])
 573
 574 (define_insn "eqv4hi3"
 575   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 576                      (match_operand:V4HI 1 "register_operand"  "y")
 577                      (match_operand:V4HI 2 "register_operand"  "y")]
 578                     VUNSPEC_WCMP_EQ)]
 579   "TARGET_REALLY_IWMMXT"
 580   "wcmpeqh%?\\t%0, %1, %2"
 581   [(set_attr "predicable" "yes")])
 582
 583 (define_insn "eqv2si3"
 584   [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
 585                           (match_operand:V2SI 1 "register_operand"  "y")
 586                           (match_operand:V2SI 2 "register_operand"  "y")]
 587                          VUNSPEC_WCMP_EQ)]
 588   "TARGET_REALLY_IWMMXT"
 589   "wcmpeqw%?\\t%0, %1, %2"
 590   [(set_attr "predicable" "yes")])
 591
 592 (define_insn "gtuv8qi3"
 593   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 594                      (match_operand:V8QI 1 "register_operand"  "y")
 595                      (match_operand:V8QI 2 "register_operand"  "y")]
 596                     VUNSPEC_WCMP_GTU)]
 597   "TARGET_REALLY_IWMMXT"
 598   "wcmpgtub%?\\t%0, %1, %2"
 599   [(set_attr "predicable" "yes")])
 600
 601 (define_insn "gtuv4hi3"
 602   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 603                      (match_operand:V4HI 1 "register_operand"  "y")
 604                      (match_operand:V4HI 2 "register_operand"  "y")]
 605                     VUNSPEC_WCMP_GTU)]
 606   "TARGET_REALLY_IWMMXT"
 607   "wcmpgtuh%?\\t%0, %1, %2"
 608   [(set_attr "predicable" "yes")])
 609
 610 (define_insn "gtuv2si3"
 611   [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
 612                      (match_operand:V2SI 1 "register_operand"  "y")
 613                      (match_operand:V2SI 2 "register_operand"  "y")]
 614                     VUNSPEC_WCMP_GTU)]
 615   "TARGET_REALLY_IWMMXT"
 616   "wcmpgtuw%?\\t%0, %1, %2"
 617   [(set_attr "predicable" "yes")])
 618
 619 (define_insn "gtv8qi3"
 620   [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
 621                      (match_operand:V8QI 1 "register_operand"  "y")
 622                      (match_operand:V8QI 2 "register_operand"  "y")]
 623                     VUNSPEC_WCMP_GT)]
 624   "TARGET_REALLY_IWMMXT"
 625   "wcmpgtsb%?\\t%0, %1, %2"
 626   [(set_attr "predicable" "yes")])
 627
 628 (define_insn "gtv4hi3"
 629   [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
 630                      (match_operand:V4HI 1 "register_operand"  "y")
 631                      (match_operand:V4HI 2 "register_operand"  "y")]
 632                     VUNSPEC_WCMP_GT)]
 633   "TARGET_REALLY_IWMMXT"
 634   "wcmpgtsh%?\\t%0, %1, %2"
 635   [(set_attr "predicable" "yes")])
 636
 637 (define_insn "gtv2si3"
 638   [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
 639                      (match_operand:V2SI 1 "register_operand"  "y")
 640                      (match_operand:V2SI 2 "register_operand"  "y")]
 641                     VUNSPEC_WCMP_GT)]
 642   "TARGET_REALLY_IWMMXT"
 643   "wcmpgtsw%?\\t%0, %1, %2"
 644   [(set_attr "predicable" "yes")])
 645
 646 ;; Max/min insns
 647
 648 (define_insn "*smax<mode>3_iwmmxt"
 649   [(set (match_operand:VMMX            0 "register_operand" "=y")
 650         (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
 651                    (match_operand:VMMX 2 "register_operand" "y")))]
 652   "TARGET_REALLY_IWMMXT"
 653   "wmaxs<MMX_char>%?\\t%0, %1, %2"
 654   [(set_attr "predicable" "yes")])
 655
 656 (define_insn "*umax<mode>3_iwmmxt"
 657   [(set (match_operand:VMMX            0 "register_operand" "=y")
 658         (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
 659                    (match_operand:VMMX 2 "register_operand" "y")))]
 660   "TARGET_REALLY_IWMMXT"
 661   "wmaxu<MMX_char>%?\\t%0, %1, %2"
 662   [(set_attr "predicable" "yes")])
 663
 664 (define_insn "*smin<mode>3_iwmmxt"
 665   [(set (match_operand:VMMX            0 "register_operand" "=y")
 666         (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
 667                    (match_operand:VMMX 2 "register_operand" "y")))]
 668   "TARGET_REALLY_IWMMXT"
 669   "wmins<MMX_char>%?\\t%0, %1, %2"
 670   [(set_attr "predicable" "yes")])
 671
 672 (define_insn "*umin<mode>3_iwmmxt"
 673   [(set (match_operand:VMMX            0 "register_operand" "=y")
 674         (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
 675                    (match_operand:VMMX 2 "register_operand" "y")))]
 676   "TARGET_REALLY_IWMMXT"
 677   "wminu<MMX_char>%?\\t%0, %1, %2"
 678   [(set_attr "predicable" "yes")])
 679
 680 ;; Pack/unpack insns.
 681
 682 (define_insn "iwmmxt_wpackhss"
 683   [(set (match_operand:V8QI                    0 "register_operand" "=y")
 684         (vec_concat:V8QI
 685          (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 686          (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 687   "TARGET_REALLY_IWMMXT"
 688   "wpackhss%?\\t%0, %1, %2"
 689   [(set_attr "predicable" "yes")])
 690
 691 (define_insn "iwmmxt_wpackwss"
 692   [(set (match_operand:V4HI                    0 "register_operand" "=y")
 693         (vec_concat:V4HI
 694          (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 695          (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
 696   "TARGET_REALLY_IWMMXT"
 697   "wpackwss%?\\t%0, %1, %2"
 698   [(set_attr "predicable" "yes")])
 699
 700 (define_insn "iwmmxt_wpackdss"
 701   [(set (match_operand:V2SI                0 "register_operand" "=y")
 702         (vec_concat:V2SI
 703          (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
 704          (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
 705   "TARGET_REALLY_IWMMXT"
 706   "wpackdss%?\\t%0, %1, %2"
 707   [(set_attr "predicable" "yes")])
 708
 709 (define_insn "iwmmxt_wpackhus"
 710   [(set (match_operand:V8QI                    0 "register_operand" "=y")
 711         (vec_concat:V8QI
 712          (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
 713          (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
 714   "TARGET_REALLY_IWMMXT"
 715   "wpackhus%?\\t%0, %1, %2"
 716   [(set_attr "predicable" "yes")])
 717
 718 (define_insn "iwmmxt_wpackwus"
 719   [(set (match_operand:V4HI                    0 "register_operand" "=y")
 720         (vec_concat:V4HI
 721          (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
 722          (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
 723   "TARGET_REALLY_IWMMXT"
 724   "wpackwus%?\\t%0, %1, %2"
 725   [(set_attr "predicable" "yes")])
 726
 727 (define_insn "iwmmxt_wpackdus"
 728   [(set (match_operand:V2SI                0 "register_operand" "=y")
 729         (vec_concat:V2SI
 730          (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
 731          (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
 732   "TARGET_REALLY_IWMMXT"
 733   "wpackdus%?\\t%0, %1, %2"
 734   [(set_attr "predicable" "yes")])
 735
 736
 737 (define_insn "iwmmxt_wunpckihb"
 738   [(set (match_operand:V8QI                   0 "register_operand" "=y")
 739         (vec_merge:V8QI
 740          (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
 741                           (parallel [(const_int 4)
 742                                      (const_int 0)
 743                                      (const_int 5)
 744                                      (const_int 1)
 745                                      (const_int 6)
 746                                      (const_int 2)
 747                                      (const_int 7)
 748                                      (const_int 3)]))
 749          (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
 750                           (parallel [(const_int 0)
 751                                      (const_int 4)
 752                                      (const_int 1)
 753                                      (const_int 5)
 754                                      (const_int 2)
 755                                      (const_int 6)
 756                                      (const_int 3)
 757                                      (const_int 7)]))
 758          (const_int 85)))]
 759   "TARGET_REALLY_IWMMXT"
 760   "wunpckihb%?\\t%0, %1, %2"
 761   [(set_attr "predicable" "yes")])
 762
 763 (define_insn "iwmmxt_wunpckihh"
 764   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 765         (vec_merge:V4HI
 766          (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
 767                           (parallel [(const_int 0)
 768                                      (const_int 2)
 769                                      (const_int 1)
 770                                      (const_int 3)]))
 771          (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
 772                           (parallel [(const_int 2)
 773                                      (const_int 0)
 774                                      (const_int 3)
 775                                      (const_int 1)]))
 776          (const_int 5)))]
 777   "TARGET_REALLY_IWMMXT"
 778   "wunpckihh%?\\t%0, %1, %2"
 779   [(set_attr "predicable" "yes")])
 780
 781 (define_insn "iwmmxt_wunpckihw"
 782   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 783         (vec_merge:V2SI
 784          (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
 785                           (parallel [(const_int 0)
 786                                      (const_int 1)]))
 787          (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
 788                           (parallel [(const_int 1)
 789                                      (const_int 0)]))
 790          (const_int 1)))]
 791   "TARGET_REALLY_IWMMXT"
 792   "wunpckihw%?\\t%0, %1, %2"
 793   [(set_attr "predicable" "yes")])
 794
 795 (define_insn "iwmmxt_wunpckilb"
 796   [(set (match_operand:V8QI                   0 "register_operand" "=y")
 797         (vec_merge:V8QI
 798          (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
 799                           (parallel [(const_int 0)
 800                                      (const_int 4)
 801                                      (const_int 1)
 802                                      (const_int 5)
 803                                      (const_int 2)
 804                                      (const_int 6)
 805                                      (const_int 3)
 806                                      (const_int 7)]))
 807          (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
 808                           (parallel [(const_int 4)
 809                                      (const_int 0)
 810                                      (const_int 5)
 811                                      (const_int 1)
 812                                      (const_int 6)
 813                                      (const_int 2)
 814                                      (const_int 7)
 815                                      (const_int 3)]))
 816          (const_int 85)))]
 817   "TARGET_REALLY_IWMMXT"
 818   "wunpckilb%?\\t%0, %1, %2"
 819   [(set_attr "predicable" "yes")])
 820
 821 (define_insn "iwmmxt_wunpckilh"
 822   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 823         (vec_merge:V4HI
 824          (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
 825                           (parallel [(const_int 2)
 826                                      (const_int 0)
 827                                      (const_int 3)
 828                                      (const_int 1)]))
 829          (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
 830                           (parallel [(const_int 0)
 831                                      (const_int 2)
 832                                      (const_int 1)
 833                                      (const_int 3)]))
 834          (const_int 5)))]
 835   "TARGET_REALLY_IWMMXT"
 836   "wunpckilh%?\\t%0, %1, %2"
 837   [(set_attr "predicable" "yes")])
 838
 839 (define_insn "iwmmxt_wunpckilw"
 840   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 841         (vec_merge:V2SI
 842          (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
 843                            (parallel [(const_int 1)
 844                                       (const_int 0)]))
 845          (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
 846                           (parallel [(const_int 0)
 847                                      (const_int 1)]))
 848          (const_int 1)))]
 849   "TARGET_REALLY_IWMMXT"
 850   "wunpckilw%?\\t%0, %1, %2"
 851   [(set_attr "predicable" "yes")])
 852
 853 (define_insn "iwmmxt_wunpckehub"
 854   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 855         (zero_extend:V4HI
 856          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
 857                           (parallel [(const_int 4) (const_int 5)
 858                                      (const_int 6) (const_int 7)]))))]
 859   "TARGET_REALLY_IWMMXT"
 860   "wunpckehub%?\\t%0, %1"
 861   [(set_attr "predicable" "yes")])
 862
 863 (define_insn "iwmmxt_wunpckehuh"
 864   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 865         (zero_extend:V2SI
 866          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
 867                           (parallel [(const_int 2) (const_int 3)]))))]
 868   "TARGET_REALLY_IWMMXT"
 869   "wunpckehuh%?\\t%0, %1"
 870   [(set_attr "predicable" "yes")])
 871
 872 (define_insn "iwmmxt_wunpckehuw"
 873   [(set (match_operand:DI                   0 "register_operand" "=y")
 874         (zero_extend:DI
 875          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
 876                         (parallel [(const_int 1)]))))]
 877   "TARGET_REALLY_IWMMXT"
 878   "wunpckehuw%?\\t%0, %1"
 879   [(set_attr "predicable" "yes")])
 880
 881 (define_insn "iwmmxt_wunpckehsb"
 882   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 883         (sign_extend:V4HI
 884          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
 885                           (parallel [(const_int 4) (const_int 5)
 886                                      (const_int 6) (const_int 7)]))))]
 887   "TARGET_REALLY_IWMMXT"
 888   "wunpckehsb%?\\t%0, %1"
 889   [(set_attr "predicable" "yes")])
 890
 891 (define_insn "iwmmxt_wunpckehsh"
 892   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 893         (sign_extend:V2SI
 894          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
 895                           (parallel [(const_int 2) (const_int 3)]))))]
 896   "TARGET_REALLY_IWMMXT"
 897   "wunpckehsh%?\\t%0, %1"
 898   [(set_attr "predicable" "yes")])
 899
 900 (define_insn "iwmmxt_wunpckehsw"
 901   [(set (match_operand:DI                   0 "register_operand" "=y")
 902         (sign_extend:DI
 903          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
 904                         (parallel [(const_int 1)]))))]
 905   "TARGET_REALLY_IWMMXT"
 906   "wunpckehsw%?\\t%0, %1"
 907   [(set_attr "predicable" "yes")])
 908
 909 (define_insn "iwmmxt_wunpckelub"
 910   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 911         (zero_extend:V4HI
 912          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
 913                           (parallel [(const_int 0) (const_int 1)
 914                                      (const_int 2) (const_int 3)]))))]
 915   "TARGET_REALLY_IWMMXT"
 916   "wunpckelub%?\\t%0, %1"
 917   [(set_attr "predicable" "yes")])
 918
 919 (define_insn "iwmmxt_wunpckeluh"
 920   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 921         (zero_extend:V2SI
 922          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
 923                           (parallel [(const_int 0) (const_int 1)]))))]
 924   "TARGET_REALLY_IWMMXT"
 925   "wunpckeluh%?\\t%0, %1"
 926   [(set_attr "predicable" "yes")])
 927
 928 (define_insn "iwmmxt_wunpckeluw"
 929   [(set (match_operand:DI                   0 "register_operand" "=y")
 930         (zero_extend:DI
 931          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
 932                         (parallel [(const_int 0)]))))]
 933   "TARGET_REALLY_IWMMXT"
 934   "wunpckeluw%?\\t%0, %1"
 935   [(set_attr "predicable" "yes")])
 936
 937 (define_insn "iwmmxt_wunpckelsb"
 938   [(set (match_operand:V4HI                   0 "register_operand" "=y")
 939         (sign_extend:V4HI
 940          (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
 941                           (parallel [(const_int 0) (const_int 1)
 942                                      (const_int 2) (const_int 3)]))))]
 943   "TARGET_REALLY_IWMMXT"
 944   "wunpckelsb%?\\t%0, %1"
 945   [(set_attr "predicable" "yes")])
 946
 947 (define_insn "iwmmxt_wunpckelsh"
 948   [(set (match_operand:V2SI                   0 "register_operand" "=y")
 949         (sign_extend:V2SI
 950          (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
 951                           (parallel [(const_int 0) (const_int 1)]))))]
 952   "TARGET_REALLY_IWMMXT"
 953   "wunpckelsh%?\\t%0, %1"
 954   [(set_attr "predicable" "yes")])
 955
 956 (define_insn "iwmmxt_wunpckelsw"
 957   [(set (match_operand:DI                   0 "register_operand" "=y")
 958         (sign_extend:DI
 959          (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
 960                         (parallel [(const_int 0)]))))]
 961   "TARGET_REALLY_IWMMXT"
 962   "wunpckelsw%?\\t%0, %1"
 963   [(set_attr "predicable" "yes")])
 964
 965 ;; Shifts
 966
 967 (define_insn "rorv4hi3"
 968   [(set (match_operand:V4HI                0 "register_operand" "=y")
 969         (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
 970                        (match_operand:SI   2 "register_operand" "z")))]
 971   "TARGET_REALLY_IWMMXT"
 972   "wrorhg%?\\t%0, %1, %2"
 973   [(set_attr "predicable" "yes")])
 974
 975 (define_insn "rorv2si3"
 976   [(set (match_operand:V2SI                0 "register_operand" "=y")
 977         (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
 978                        (match_operand:SI   2 "register_operand" "z")))]
 979   "TARGET_REALLY_IWMMXT"
 980   "wrorwg%?\\t%0, %1, %2"
 981   [(set_attr "predicable" "yes")])
 982
 983 (define_insn "rordi3"
 984   [(set (match_operand:DI              0 "register_operand" "=y")
 985         (rotatert:DI (match_operand:DI 1 "register_operand" "y")
 986                    (match_operand:SI   2 "register_operand" "z")))]
 987   "TARGET_REALLY_IWMMXT"
 988   "wrordg%?\\t%0, %1, %2"
 989   [(set_attr "predicable" "yes")])
 990
 991 (define_insn "ashr<mode>3_iwmmxt"
 992   [(set (match_operand:VSHFT                 0 "register_operand" "=y")
 993         (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
 994                         (match_operand:SI    2 "register_operand" "z")))]
 995   "TARGET_REALLY_IWMMXT"
 996   "wsra<MMX_char>g%?\\t%0, %1, %2"
 997   [(set_attr "predicable" "yes")])
 998
 999 (define_insn "lshr<mode>3_iwmmxt"
1000   [(set (match_operand:VSHFT                 0 "register_operand" "=y")
1001         (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1002                         (match_operand:SI    2 "register_operand" "z")))]
1003   "TARGET_REALLY_IWMMXT"
1004   "wsrl<MMX_char>g%?\\t%0, %1, %2"
1005   [(set_attr "predicable" "yes")])
1006
1007 (define_insn "ashl<mode>3_iwmmxt"
1008   [(set (match_operand:VSHFT               0 "register_operand" "=y")
1009         (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y")
1010                       (match_operand:SI    2 "register_operand" "z")))]
1011   "TARGET_REALLY_IWMMXT"
1012   "wsll<MMX_char>g%?\\t%0, %1, %2"
1013   [(set_attr "predicable" "yes")])
1014
1015 (define_insn "rorv4hi3_di"
1016   [(set (match_operand:V4HI                0 "register_operand" "=y")
1017         (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1018                        (match_operand:DI   2 "register_operand" "y")))]
1019   "TARGET_REALLY_IWMMXT"
1020   "wrorh%?\\t%0, %1, %2"
1021   [(set_attr "predicable" "yes")])
1022
1023 (define_insn "rorv2si3_di"
1024   [(set (match_operand:V2SI                0 "register_operand" "=y")
1025         (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1026                        (match_operand:DI   2 "register_operand" "y")))]
1027   "TARGET_REALLY_IWMMXT"
1028   "wrorw%?\\t%0, %1, %2"
1029   [(set_attr "predicable" "yes")])
1030
1031 (define_insn "rordi3_di"
1032   [(set (match_operand:DI              0 "register_operand" "=y")
1033         (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1034                    (match_operand:DI   2 "register_operand" "y")))]
1035   "TARGET_REALLY_IWMMXT"
1036   "wrord%?\\t%0, %1, %2"
1037   [(set_attr "predicable" "yes")])
1038
1039 (define_insn "ashrv4hi3_di"
1040   [(set (match_operand:V4HI                0 "register_operand" "=y")
1041         (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1042                        (match_operand:DI   2 "register_operand" "y")))]
1043   "TARGET_REALLY_IWMMXT"
1044   "wsrah%?\\t%0, %1, %2"
1045   [(set_attr "predicable" "yes")])
1046
1047 (define_insn "ashrv2si3_di"
1048   [(set (match_operand:V2SI                0 "register_operand" "=y")
1049         (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1050                        (match_operand:DI   2 "register_operand" "y")))]
1051   "TARGET_REALLY_IWMMXT"
1052   "wsraw%?\\t%0, %1, %2"
1053   [(set_attr "predicable" "yes")])
1054
1055 (define_insn "ashrdi3_di"
1056   [(set (match_operand:DI              0 "register_operand" "=y")
1057         (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1058                    (match_operand:DI   2 "register_operand" "y")))]
1059   "TARGET_REALLY_IWMMXT"
1060   "wsrad%?\\t%0, %1, %2"
1061   [(set_attr "predicable" "yes")])
1062
1063 (define_insn "lshrv4hi3_di"
1064   [(set (match_operand:V4HI                0 "register_operand" "=y")
1065         (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1066                        (match_operand:DI   2 "register_operand" "y")))]
1067   "TARGET_REALLY_IWMMXT"
1068   "wsrlh%?\\t%0, %1, %2"
1069   [(set_attr "predicable" "yes")])
1070
1071 (define_insn "lshrv2si3_di"
1072   [(set (match_operand:V2SI                0 "register_operand" "=y")
1073         (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1074                        (match_operand:DI   2 "register_operand" "y")))]
1075   "TARGET_REALLY_IWMMXT"
1076   "wsrlw%?\\t%0, %1, %2"
1077   [(set_attr "predicable" "yes")])
1078
1079 (define_insn "lshrdi3_di"
1080   [(set (match_operand:DI              0 "register_operand" "=y")
1081         (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1082                      (match_operand:DI 2 "register_operand" "y")))]
1083   "TARGET_REALLY_IWMMXT"
1084   "wsrld%?\\t%0, %1, %2"
1085   [(set_attr "predicable" "yes")])
1086
1087 (define_insn "ashlv4hi3_di"
1088   [(set (match_operand:V4HI              0 "register_operand" "=y")
1089         (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1090                      (match_operand:DI   2 "register_operand" "y")))]
1091   "TARGET_REALLY_IWMMXT"
1092   "wsllh%?\\t%0, %1, %2"
1093   [(set_attr "predicable" "yes")])
1094
1095 (define_insn "ashlv2si3_di"
1096   [(set (match_operand:V2SI              0 "register_operand" "=y")
1097         (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1098                        (match_operand:DI 2 "register_operand" "y")))]
1099   "TARGET_REALLY_IWMMXT"
1100   "wsllw%?\\t%0, %1, %2"
1101   [(set_attr "predicable" "yes")])
1102
1103 (define_insn "ashldi3_di"
1104   [(set (match_operand:DI            0 "register_operand" "=y")
1105         (ashift:DI (match_operand:DI 1 "register_operand" "y")
1106                    (match_operand:DI 2 "register_operand" "y")))]
1107   "TARGET_REALLY_IWMMXT"
1108   "wslld%?\\t%0, %1, %2"
1109   [(set_attr "predicable" "yes")])
1110
1111 (define_insn "iwmmxt_wmadds"
1112   [(set (match_operand:V4HI               0 "register_operand" "=y")
1113         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1114                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1115   "TARGET_REALLY_IWMMXT"
1116   "wmadds%?\\t%0, %1, %2"
1117   [(set_attr "predicable" "yes")])
1118
1119 (define_insn "iwmmxt_wmaddu"
1120   [(set (match_operand:V4HI               0 "register_operand" "=y")
1121         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1122                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1123   "TARGET_REALLY_IWMMXT"
1124   "wmaddu%?\\t%0, %1, %2"
1125   [(set_attr "predicable" "yes")])
1126
1127 (define_insn "iwmmxt_tmia"
1128   [(set (match_operand:DI                    0 "register_operand" "=y")
1129         (plus:DI (match_operand:DI           1 "register_operand" "0")
1130                  (mult:DI (sign_extend:DI
1131                            (match_operand:SI 2 "register_operand" "r"))
1132                           (sign_extend:DI
1133                            (match_operand:SI 3 "register_operand" "r")))))]
1134   "TARGET_REALLY_IWMMXT"
1135   "tmia%?\\t%0, %2, %3"
1136   [(set_attr "predicable" "yes")])
1137
1138 (define_insn "iwmmxt_tmiaph"
1139   [(set (match_operand:DI          0 "register_operand" "=y")
1140         (plus:DI (match_operand:DI 1 "register_operand" "0")
1141                  (plus:DI
1142                   (mult:DI (sign_extend:DI
1143                             (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1144                            (sign_extend:DI
1145                             (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1146                   (mult:DI (sign_extend:DI
1147                             (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1148                            (sign_extend:DI
1149                             (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1150   "TARGET_REALLY_IWMMXT"
1151   "tmiaph%?\\t%0, %2, %3"
1152   [(set_attr "predicable" "yes")])
1153
1154 (define_insn "iwmmxt_tmiabb"
1155   [(set (match_operand:DI          0 "register_operand" "=y")
1156         (plus:DI (match_operand:DI 1 "register_operand" "0")
1157                  (mult:DI (sign_extend:DI
1158                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1159                           (sign_extend:DI
1160                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1161   "TARGET_REALLY_IWMMXT"
1162   "tmiabb%?\\t%0, %2, %3"
1163   [(set_attr "predicable" "yes")])
1164
1165 (define_insn "iwmmxt_tmiatb"
1166   [(set (match_operand:DI          0 "register_operand" "=y")
1167         (plus:DI (match_operand:DI 1 "register_operand" "0")
1168                  (mult:DI (sign_extend:DI
1169                            (truncate:HI (ashiftrt:SI
1170                                          (match_operand:SI 2 "register_operand" "r")
1171                                          (const_int 16))))
1172                           (sign_extend:DI
1173                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1174   "TARGET_REALLY_IWMMXT"
1175   "tmiatb%?\\t%0, %2, %3"
1176   [(set_attr "predicable" "yes")])
1177
1178 (define_insn "iwmmxt_tmiabt"
1179   [(set (match_operand:DI          0 "register_operand" "=y")
1180         (plus:DI (match_operand:DI 1 "register_operand" "0")
1181                  (mult:DI (sign_extend:DI
1182                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1183                           (sign_extend:DI
1184                            (truncate:HI (ashiftrt:SI
1185                                          (match_operand:SI 3 "register_operand" "r")
1186                                          (const_int 16)))))))]
1187   "TARGET_REALLY_IWMMXT"
1188   "tmiabt%?\\t%0, %2, %3"
1189   [(set_attr "predicable" "yes")])
1190
1191 (define_insn "iwmmxt_tmiatt"
1192   [(set (match_operand:DI          0 "register_operand" "=y")
1193         (plus:DI (match_operand:DI 1 "register_operand" "0")
1194                  (mult:DI (sign_extend:DI
1195                            (truncate:HI (ashiftrt:SI
1196                                          (match_operand:SI 2 "register_operand" "r")
1197                                          (const_int 16))))
1198                           (sign_extend:DI
1199                            (truncate:HI (ashiftrt:SI
1200                                          (match_operand:SI 3 "register_operand" "r")
1201                                          (const_int 16)))))))]
1202   "TARGET_REALLY_IWMMXT"
1203   "tmiatt%?\\t%0, %2, %3"
1204   [(set_attr "predicable" "yes")])
1205
1206 (define_insn "iwmmxt_tbcstqi"
1207   [(set (match_operand:V8QI                   0 "register_operand" "=y")
1208         (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1209   "TARGET_REALLY_IWMMXT"
1210   "tbcstb%?\\t%0, %1"
1211   [(set_attr "predicable" "yes")])
1212
1213 (define_insn "iwmmxt_tbcsthi"
1214   [(set (match_operand:V4HI                   0 "register_operand" "=y")
1215         (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1216   "TARGET_REALLY_IWMMXT"
1217   "tbcsth%?\\t%0, %1"
1218   [(set_attr "predicable" "yes")])
1219
1220 (define_insn "iwmmxt_tbcstsi"
1221   [(set (match_operand:V2SI                   0 "register_operand" "=y")
1222         (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1223   "TARGET_REALLY_IWMMXT"
1224   "tbcstw%?\\t%0, %1"
1225   [(set_attr "predicable" "yes")])
1226
1227 (define_insn "iwmmxt_tmovmskb"
1228   [(set (match_operand:SI               0 "register_operand" "=r")
1229         (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1230   "TARGET_REALLY_IWMMXT"
1231   "tmovmskb%?\\t%0, %1"
1232   [(set_attr "predicable" "yes")])
1233
1234 (define_insn "iwmmxt_tmovmskh"
1235   [(set (match_operand:SI               0 "register_operand" "=r")
1236         (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1237   "TARGET_REALLY_IWMMXT"
1238   "tmovmskh%?\\t%0, %1"
1239   [(set_attr "predicable" "yes")])
1240
1241 (define_insn "iwmmxt_tmovmskw"
1242   [(set (match_operand:SI               0 "register_operand" "=r")
1243         (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1244   "TARGET_REALLY_IWMMXT"
1245   "tmovmskw%?\\t%0, %1"
1246   [(set_attr "predicable" "yes")])
1247
1248 (define_insn "iwmmxt_waccb"
1249   [(set (match_operand:DI               0 "register_operand" "=y")
1250         (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1251   "TARGET_REALLY_IWMMXT"
1252   "waccb%?\\t%0, %1"
1253   [(set_attr "predicable" "yes")])
1254
1255 (define_insn "iwmmxt_wacch"
1256   [(set (match_operand:DI               0 "register_operand" "=y")
1257         (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1258   "TARGET_REALLY_IWMMXT"
1259   "wacch%?\\t%0, %1"
1260   [(set_attr "predicable" "yes")])
1261
1262 (define_insn "iwmmxt_waccw"
1263   [(set (match_operand:DI               0 "register_operand" "=y")
1264         (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1265   "TARGET_REALLY_IWMMXT"
1266   "waccw%?\\t%0, %1"
1267   [(set_attr "predicable" "yes")])
1268
1269 (define_insn "iwmmxt_walign"
1270   [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
1271         (subreg:V8QI (ashiftrt:TI
1272                       (subreg:TI (vec_concat:V16QI
1273                                   (match_operand:V8QI 1 "register_operand" "y,y")
1274                                   (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1275                       (mult:SI
1276                        (match_operand:SI              3 "nonmemory_operand" "i,z")
1277                        (const_int 8))) 0))]
1278   "TARGET_REALLY_IWMMXT"
1279   "@
1280    waligni%?\\t%0, %1, %2, %3
1281    walignr%U3%?\\t%0, %1, %2"
1282   [(set_attr "predicable" "yes")])
1283
1284 (define_insn "iwmmxt_tmrc"
1285   [(set (match_operand:SI                      0 "register_operand" "=r")
1286         (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1287                             VUNSPEC_TMRC))]
1288   "TARGET_REALLY_IWMMXT"
1289   "tmrc%?\\t%0, %w1"
1290   [(set_attr "predicable" "yes")])
1291
1292 (define_insn "iwmmxt_tmcr"
1293   [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1294                         (match_operand:SI 1 "register_operand"  "r")]
1295                        VUNSPEC_TMCR)]
1296   "TARGET_REALLY_IWMMXT"
1297   "tmcr%?\\t%w0, %1"
1298   [(set_attr "predicable" "yes")])
1299
1300 (define_insn "iwmmxt_wsadb"
1301   [(set (match_operand:V8QI               0 "register_operand" "=y")
1302         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1303                       (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1304   "TARGET_REALLY_IWMMXT"
1305   "wsadb%?\\t%0, %1, %2"
1306   [(set_attr "predicable" "yes")])
1307
1308 (define_insn "iwmmxt_wsadh"
1309   [(set (match_operand:V4HI               0 "register_operand" "=y")
1310         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1311                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1312   "TARGET_REALLY_IWMMXT"
1313   "wsadh%?\\t%0, %1, %2"
1314   [(set_attr "predicable" "yes")])
1315
1316 (define_insn "iwmmxt_wsadbz"
1317   [(set (match_operand:V8QI               0 "register_operand" "=y")
1318         (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1319                       (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1320   "TARGET_REALLY_IWMMXT"
1321   "wsadbz%?\\t%0, %1, %2"
1322   [(set_attr "predicable" "yes")])
1323
1324 (define_insn "iwmmxt_wsadhz"
1325   [(set (match_operand:V4HI               0 "register_operand" "=y")
1326         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1327                       (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1328   "TARGET_REALLY_IWMMXT"
1329   "wsadhz%?\\t%0, %1, %2"
1330   [(set_attr "predicable" "yes")])
1331