1 ; Options for the ARM port of the compiler.
3 ; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
22 Target RejectNegative Joined Var(target_abi_name)
26 Target Report Mask(ABORT_NORETURN)
27 Generate a call to abort if a noreturn function returns
30 Target RejectNegative Mask(APCS_FRAME) MaskExists Undocumented
33 Target Report Mask(APCS_FLOAT)
34 Pass FP arguments in FP registers
37 Target Report Mask(APCS_FRAME)
38 Generate APCS conformant stack frames
41 Target Report Mask(APCS_REENT)
42 Generate re-entrant, PIC code
45 Target Report Mask(APCS_STACK) Undocumented
48 Target RejectNegative Joined
49 Specify the name of the target architecture
52 Target RejectNegative InverseMask(THUMB) Undocumented
55 Target Report RejectNegative Mask(BIG_END)
56 Assume target CPU is configured as big endian
58 mcallee-super-interworking
59 Target Report Mask(CALLEE_INTERWORKING)
60 Thumb: Assume non-static functions may be called from ARM code
62 mcaller-super-interworking
63 Target Report Mask(CALLER_INTERWORKING)
64 Thumb: Assume function pointers may go to non-Thumb aware code
66 mcirrus-fix-invalid-insns
67 Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
68 Cirrus: Place NOPs to avoid invalid instruction combinations
71 Target RejectNegative Joined
72 Specify the name of the target CPU
75 Target RejectNegative Joined Var(target_float_abi_name)
76 Specify if floating point hardware should be used
79 Target RejectNegative Joined Undocumented Var(target_fpe_name)
82 Target RejectNegative Joined Var(target_fp16_format_name)
83 Specify the __fp16 floating-point format
87 Target RejectNegative Mask(FPE) Undocumented
90 Target RejectNegative Joined Undocumented Var(target_fpe_name)
93 Target RejectNegative Joined Var(target_fpu_name)
94 Specify the name of the target floating point hardware/format
98 Alias for -mfloat-abi=hard
101 Target Report RejectNegative InverseMask(BIG_END)
102 Assume target CPU is configured as little endian
105 Target Report Mask(LONG_CALLS)
106 Generate call insns as indirect calls, if necessary
109 Target RejectNegative Joined Var(arm_pic_register_string)
110 Specify the register to be used for PIC addressing
113 Target Report Mask(POKE_FUNCTION_NAME)
114 Store function names in object code
117 Target Report Mask(SCHED_PROLOG)
118 Permit scheduling of a function's prologue sequence
121 Target Report Mask(SINGLE_PIC_BASE)
122 Do not load the PIC register in function prologues
125 Target RejectNegative
126 Alias for -mfloat-abi=soft
128 mstructure-size-boundary=
129 Target RejectNegative Joined Var(structure_size_string)
130 Specify the minimum bit alignment of structures
133 Target Report Mask(THUMB)
134 Compile for the Thumb not the ARM
137 Target Report Mask(INTERWORK)
138 Support calls between Thumb and ARM instruction sets
141 Target RejectNegative Joined Var(target_thread_switch)
142 Specify how to access the thread pointer
145 Target Report Mask(TPCS_FRAME)
146 Thumb: Generate (non-leaf) stack frames even if not needed
149 Target Report Mask(TPCS_LEAF_FRAME)
150 Thumb: Generate (leaf) stack frames even if not needed
153 Target RejectNegative Joined
154 Tune code for the given processor
157 Target Report RejectNegative Mask(LITTLE_WORDS)
158 Assume big endian bytes, little endian words
160 mvectorize-with-neon-quad
161 Target Report Mask(NEON_VECTORIZE_QUAD)
162 Use Neon quad-word (rather than double-word) registers for vectorization
165 Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
166 Only generate absolute relocations on word sized values.
169 Target Report Var(fix_cm3_ldrd) Init(2)
170 Avoid overlapping destination and address registers on LDRD instructions
171 that may trigger Cortex-M3 errata.