1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* The archetecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
41 builtin_define ("__thumb__"); \
45 builtin_define ("__ARMEB__"); \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
53 builtin_define ("__ARMEL__"); \
55 builtin_define ("__THUMBEL__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
62 builtin_define ("__VFP_FP__"); \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
83 /* The various ARM cores. */
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
88 #include "arm-cores.def"
90 /* Used to indicate that no processor has been specified. */
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
98 #include "arm-cores.def"
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
106 typedef enum arm_cond_code
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
113 extern arm_cc arm_current_cc;
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Run-time compilation parameters selecting different hardware subsets. */
121 extern int target_flags;
122 /* The floating point mode. */
123 extern const char *target_fpu_name;
124 /* For backwards compatibility. */
125 extern const char *target_fpe_name;
126 /* Whether to use floating point hardware. */
127 extern const char *target_float_abi_name;
128 /* For -m{soft,hard}-float. */
129 extern const char *target_float_switch;
130 /* Which ABI to use. */
131 extern const char *target_abi_name;
132 /* Define the information needed to generate branch insns. This is
133 stored from the compare operation. */
134 extern GTY(()) rtx arm_compare_op0;
135 extern GTY(()) rtx arm_compare_op1;
136 /* The label of the current constant pool. */
137 extern rtx pool_vector_label;
138 /* Set to 1 when a return insn is output, this means that the epilogue
140 extern int return_used_this_function;
141 /* Used to produce AOF syntax assembler. */
142 extern GTY(()) rtx aof_pic_label;
144 /* Just in case configure has failed to define anything. */
145 #ifndef TARGET_CPU_DEFAULT
146 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
151 #define CPP_SPEC "%(subtarget_cpp_spec) \
152 %{msoft-float:%{mhard-float: \
153 %e-msoft-float and -mhard_float may not be used together}} \
154 %{mbig-endian:%{mlittle-endian: \
155 %e-mbig-endian and -mlittle-endian may not be used together}}"
161 /* This macro defines names of additional specifications to put in the specs
162 that can be used in various specifications like CC1_SPEC. Its definition
163 is an initializer with a subgrouping for each command option.
165 Each subgrouping contains a string constant, that defines the
166 specification name, and a string constant that used by the GCC driver
169 Do not define this macro if it does not need to do anything. */
170 #define EXTRA_SPECS \
171 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
172 SUBTARGET_EXTRA_SPECS
174 #ifndef SUBTARGET_EXTRA_SPECS
175 #define SUBTARGET_EXTRA_SPECS
178 #ifndef SUBTARGET_CPP_SPEC
179 #define SUBTARGET_CPP_SPEC ""
182 /* Run-time Target Specification. */
183 #ifndef TARGET_VERSION
184 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
187 /* Nonzero if the function prologue (and epilogue) should obey
188 the ARM Procedure Call Standard. */
189 #define ARM_FLAG_APCS_FRAME (1 << 0)
191 /* Nonzero if the function prologue should output the function name to enable
192 the post mortem debugger to print a backtrace (very useful on RISCOS,
193 unused on RISCiX). Specifying this flag also enables
194 -fno-omit-frame-pointer.
195 XXX Must still be implemented in the prologue. */
196 #define ARM_FLAG_POKE (1 << 1)
198 /* Nonzero if floating point instructions are emulated by the FPE, in which
199 case instruction scheduling becomes very uninteresting. */
200 #define ARM_FLAG_FPE (1 << 2)
202 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
204 /* Nonzero if stack checking should be performed on entry to each function
205 which allocates temporary variables on the stack. */
206 #define ARM_FLAG_APCS_STACK (1 << 4)
208 /* Nonzero if floating point parameters should be passed to functions in
209 floating point registers. */
210 #define ARM_FLAG_APCS_FLOAT (1 << 5)
212 /* Nonzero if re-entrant, position independent code should be generated.
213 This is equivalent to -fpic. */
214 #define ARM_FLAG_APCS_REENT (1 << 6)
216 /* FLAG 0x0080 now spare (used to be alignment traps). */
217 /* FLAG (1 << 8) is now spare (used to be soft-float). */
219 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
220 #define ARM_FLAG_BIG_END (1 << 9)
222 /* Nonzero if we should compile for Thumb interworking. */
223 #define ARM_FLAG_INTERWORK (1 << 10)
225 /* Nonzero if we should have little-endian words even when compiling for
226 big-endian (for backwards compatibility with older versions of GCC). */
227 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
229 /* Nonzero if we need to protect the prolog from scheduling */
230 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
232 /* Nonzero if a call to abort should be generated if a noreturn
233 function tries to return. */
234 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
236 /* Nonzero if function prologues should not load the PIC register. */
237 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
239 /* Nonzero if all call instructions should be indirect. */
240 #define ARM_FLAG_LONG_CALLS (1 << 15)
242 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
243 #define ARM_FLAG_THUMB (1 << 16)
245 /* Set if a TPCS style stack frame should be generated, for non-leaf
246 functions, even if they do not need one. */
247 #define THUMB_FLAG_BACKTRACE (1 << 17)
249 /* Set if a TPCS style stack frame should be generated, for leaf
250 functions, even if they do not need one. */
251 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
253 /* Set if externally visible functions should assume that they
254 might be called in ARM mode, from a non-thumb aware code. */
255 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
257 /* Set if calls via function pointers should assume that their
258 destination is non-Thumb aware. */
259 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
261 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
262 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
264 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
265 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
266 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
267 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
268 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
269 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
270 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
271 /* Use hardware floating point instructions. */
272 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
273 /* Use hardware floating point calling convention. */
274 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
275 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
276 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
277 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
278 #define TARGET_IWMMXT (arm_arch_iwmmxt)
279 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
280 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
281 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
282 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
283 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
284 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
285 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
286 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
287 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
288 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
289 #define TARGET_ARM (! TARGET_THUMB)
290 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
291 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
292 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
293 #define TARGET_BACKTRACE (leaf_function_p () \
294 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
295 : (target_flags & THUMB_FLAG_BACKTRACE))
296 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
297 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
298 #define TARGET_AAPCS_BASED \
299 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
301 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
302 then TARGET_AAPCS_BASED must be true -- but the converse does not
303 hold. TARGET_BPABI implies the use of the BPABI runtime library,
304 etc., in addition to just the AAPCS calling conventions. */
306 #define TARGET_BPABI false
309 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
310 #ifndef SUBTARGET_SWITCHES
311 #define SUBTARGET_SWITCHES
314 #define TARGET_SWITCHES \
316 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
317 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
318 N_("Generate APCS conformant stack frames") }, \
319 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
320 {"poke-function-name", ARM_FLAG_POKE, \
321 N_("Store function names in object code") }, \
322 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
323 {"fpe", ARM_FLAG_FPE, "" }, \
324 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
325 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
326 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
327 N_("Pass FP arguments in FP registers") }, \
328 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
329 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
330 N_("Generate re-entrant, PIC code") }, \
331 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
332 {"big-endian", ARM_FLAG_BIG_END, \
333 N_("Assume target CPU is configured as big endian") }, \
334 {"little-endian", -ARM_FLAG_BIG_END, \
335 N_("Assume target CPU is configured as little endian") }, \
336 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
337 N_("Assume big endian bytes, little endian words") }, \
338 {"thumb-interwork", ARM_FLAG_INTERWORK, \
339 N_("Support calls between Thumb and ARM instruction sets") }, \
340 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
341 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
342 N_("Generate a call to abort if a noreturn function returns")}, \
343 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
344 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
345 N_("Do not move instructions into a function's prologue") }, \
346 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
347 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
348 N_("Do not load the PIC register in function prologues") }, \
349 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
350 {"long-calls", ARM_FLAG_LONG_CALLS, \
351 N_("Generate call insns as indirect calls, if necessary") }, \
352 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
353 {"thumb", ARM_FLAG_THUMB, \
354 N_("Compile for the Thumb not the ARM") }, \
355 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
356 {"arm", -ARM_FLAG_THUMB, "" }, \
357 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
358 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
359 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
360 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
361 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
362 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
363 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
364 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
365 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
367 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
368 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
369 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
371 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
372 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
373 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
374 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
376 {"", TARGET_DEFAULT, "" } \
379 #define TARGET_OPTIONS \
381 {"cpu=", & arm_select[0].string, \
382 N_("Specify the name of the target CPU"), 0}, \
383 {"arch=", & arm_select[1].string, \
384 N_("Specify the name of the target architecture"), 0}, \
385 {"tune=", & arm_select[2].string, "", 0}, \
386 {"fpe=", & target_fpe_name, "", 0}, \
387 {"fp=", & target_fpe_name, "", 0}, \
388 {"fpu=", & target_fpu_name, \
389 N_("Specify the name of the target floating point hardware/format"), 0}, \
390 {"float-abi=", & target_float_abi_name, \
391 N_("Specify if floating point hardware should be used"), 0}, \
392 {"structure-size-boundary=", & structure_size_string, \
393 N_("Specify the minimum bit alignment of structures"), 0}, \
394 {"pic-register=", & arm_pic_register_string, \
395 N_("Specify the register to be used for PIC addressing"), 0}, \
396 {"abi=", &target_abi_name, N_("Specify an ABI"), 0}, \
397 {"soft-float", &target_float_switch, \
398 N_("Alias for -mfloat-abi=soft"), 0}, \
399 {"hard-float", &target_float_switch, \
400 N_("Alias for -mfloat-abi=hard"), 0} \
403 /* Support for a compile-time default CPU, et cetera. The rules are:
404 --with-arch is ignored if -march or -mcpu are specified.
405 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
407 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
409 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
411 --with-fpu is ignored if -mfpu is specified.
412 --with-abi is ignored is -mabi is specified. */
413 #define OPTION_DEFAULT_SPECS \
414 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
415 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
416 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
418 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
419 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
420 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
422 struct arm_cpu_select
426 const struct processors * processors;
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
434 /* Which floating point model to use. */
437 ARM_FP_MODEL_UNKNOWN,
438 /* FPA model (Hardware or software). */
440 /* Cirrus Maverick floating point model. */
441 ARM_FP_MODEL_MAVERICK,
442 /* VFP floating point model. */
446 extern enum arm_fp_model arm_fp_model;
448 /* Which floating point hardware is available. Also update
449 fp_model_for_fpu in arm.c when adding entries to this list. */
452 /* No FP hardware. */
454 /* Full FPA support. */
456 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
458 /* Emulated FPA hardware, Issue 3 emulator. */
460 /* Cirrus Maverick floating point co-processor. */
466 /* Recast the floating point class to be the floating point attribute. */
467 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
469 /* What type of floating point to tune for */
470 extern enum fputype arm_fpu_tune;
472 /* What type of floating point instructions are available */
473 extern enum fputype arm_fpu_arch;
478 ARM_FLOAT_ABI_SOFTFP,
482 extern enum float_abi_type arm_float_abi;
484 #ifndef TARGET_DEFAULT_FLOAT_ABI
485 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
488 /* Which ABI to use. */
497 extern enum arm_abi_type arm_abi;
499 #ifndef ARM_DEFAULT_ABI
500 #define ARM_DEFAULT_ABI ARM_ABI_APCS
503 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504 extern int arm_arch3m;
506 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
507 extern int arm_arch4;
509 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
510 extern int arm_arch4t;
512 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
513 extern int arm_arch5;
515 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
516 extern int arm_arch5e;
518 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519 extern int arm_arch6;
521 /* Nonzero if this chip can benefit from load scheduling. */
522 extern int arm_ld_sched;
524 /* Nonzero if generating thumb code. */
525 extern int thumb_code;
527 /* Nonzero if this chip is a StrongARM. */
528 extern int arm_is_strong;
530 /* Nonzero if this chip is a Cirrus variant. */
531 extern int arm_arch_cirrus;
533 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
534 extern int arm_arch_iwmmxt;
536 /* Nonzero if this chip is an XScale. */
537 extern int arm_arch_xscale;
539 /* Nonzero if tuning for XScale */
540 extern int arm_tune_xscale;
542 /* Nonzero if this chip is an ARM6 or an ARM7. */
543 extern int arm_is_6_or_7;
545 /* Nonzero if we should define __THUMB_INTERWORK__ in the
547 XXX This is a bit of a hack, it's intended to help work around
548 problems in GLD which doesn't understand that armv5t code is
549 interworking clean. */
550 extern int arm_cpp_interwork;
552 #ifndef TARGET_DEFAULT
553 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
556 /* The frame pointer register used in gcc has nothing to do with debugging;
557 that is controlled by the APCS-FRAME option. */
558 #define CAN_DEBUG_WITHOUT_FP
560 #define OVERRIDE_OPTIONS arm_override_options ()
562 /* Nonzero if PIC code requires explicit qualifiers to generate
563 PLT and GOT relocs rather than the assembler doing so implicitly.
564 Subtargets can override these if required. */
565 #ifndef NEED_GOT_RELOC
566 #define NEED_GOT_RELOC 0
568 #ifndef NEED_PLT_RELOC
569 #define NEED_PLT_RELOC 0
572 /* Nonzero if we need to refer to the GOT with a PC-relative
573 offset. In other words, generate
575 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
579 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
581 The default is true, which matches NetBSD. Subtargets can
582 override this if required. */
587 /* Target machine storage Layout. */
590 /* Define this macro if it is advisable to hold scalars in registers
591 in a wider mode than that declared by the program. In such cases,
592 the value is constrained to be within the bounds of the declared
593 type, but kept valid in the wider mode. The signedness of the
594 extension may differ from that of the type. */
596 /* It is far faster to zero extend chars than to sign extend them */
598 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
599 if (GET_MODE_CLASS (MODE) == MODE_INT \
600 && GET_MODE_SIZE (MODE) < 4) \
602 if (MODE == QImode) \
604 else if (MODE == HImode) \
609 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
610 if (GET_MODE_CLASS (MODE) == MODE_INT \
611 && GET_MODE_SIZE (MODE) < 4) \
614 /* Define this if most significant bit is lowest numbered
615 in instructions that operate on numbered bit-fields. */
616 #define BITS_BIG_ENDIAN 0
618 /* Define this if most significant byte of a word is the lowest numbered.
619 Most ARM processors are run in little endian mode, so that is the default.
620 If you want to have it run-time selectable, change the definition in a
621 cover file to be TARGET_BIG_ENDIAN. */
622 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
624 /* Define this if most significant word of a multiword number is the lowest
626 This is always false, even when in big-endian mode. */
627 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
629 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
630 on processor pre-defineds when compiling libgcc2.c. */
631 #if defined(__ARMEB__) && !defined(__ARMWEL__)
632 #define LIBGCC2_WORDS_BIG_ENDIAN 1
634 #define LIBGCC2_WORDS_BIG_ENDIAN 0
637 /* Define this if most significant word of doubles is the lowest numbered.
638 The rules are different based on whether or not we use FPA-format,
639 VFP-format or some other floating point co-processor's format doubles. */
640 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
642 #define UNITS_PER_WORD 4
644 /* True if natural alignment is used for doubleword types. */
645 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
647 #define DOUBLEWORD_ALIGNMENT 64
649 #define PARM_BOUNDARY 32
651 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
653 #define PREFERRED_STACK_BOUNDARY \
654 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
656 #define FUNCTION_BOUNDARY 32
658 /* The lowest bit is used to indicate Thumb-mode functions, so the
659 vbit must go into the delta field of pointers to member
661 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
663 #define EMPTY_FIELD_BOUNDARY 32
665 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
667 /* XXX Blah -- this macro is used directly by libobjc. Since it
668 supports no vector modes, cut out the complexity and fall back
669 on BIGGEST_FIELD_ALIGNMENT. */
670 #ifdef IN_TARGET_LIBS
671 #define BIGGEST_FIELD_ALIGNMENT 64
674 /* Make strings word-aligned so strcpy from constants will be faster. */
675 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
677 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
678 ((TREE_CODE (EXP) == STRING_CST \
679 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
680 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
682 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
683 value set in previous versions of this toolchain was 8, which produces more
684 compact structures. The command line option -mstructure_size_boundary=<n>
685 can be used to change this value. For compatibility with the ARM SDK
686 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
687 0020D) page 2-20 says "Structures are aligned on word boundaries".
688 The AAPCS specifies a value of 8. */
689 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
690 extern int arm_structure_size_boundary;
692 /* This is the value used to initialize arm_structure_size_boundary. If a
693 particular arm target wants to change the default value it should change
694 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
695 for an example of this. */
696 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
697 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
700 /* Used when parsing command line option -mstructure_size_boundary. */
701 extern const char * structure_size_string;
703 /* Nonzero if move instructions will actually fail to work
704 when given unaligned data. */
705 #define STRICT_ALIGNMENT 1
707 /* wchar_t is unsigned under the AAPCS. */
709 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
711 #define WCHAR_TYPE_SIZE BITS_PER_WORD
715 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
718 /* AAPCS requires that structure alignment is affected by bitfields. */
719 #ifndef PCC_BITFIELD_TYPE_MATTERS
720 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
724 /* Standard register usage. */
726 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
727 (S - saved over call).
729 r0 * argument word/integer result
732 r4-r8 S register variable
733 r9 S (rfp) register variable (real frame pointer)
735 r10 F S (sl) stack limit (used by -mapcs-stack-check)
736 r11 F S (fp) argument pointer
737 r12 (ip) temp workspace
738 r13 F S (sp) lower end of current stack frame
739 r14 (lr) link address/workspace
740 r15 F (pc) program counter
742 f0 floating point result
743 f1-f3 floating point scratch
745 f4-f7 S floating point variable
747 cc This is NOT a real register, but is used internally
748 to represent things that use or set the condition
750 sfp This isn't either. It is used during rtl generation
751 since the offset between the frame pointer and the
752 auto's isn't known until after register allocation.
753 afp Nor this, we only need this because of non-local
754 goto. Without it fp appears to be used and the
755 elimination code won't get rid of sfp. It tracks
756 fp exactly at all times.
758 *: See CONDITIONAL_REGISTER_USAGE */
761 mvf0 Cirrus floating point result
762 mvf1-mvf3 Cirrus floating point scratch
763 mvf4-mvf15 S Cirrus floating point variable. */
765 /* s0-s15 VFP scratch (aka d0-d7).
766 s16-s31 S VFP variable (aka d8-d15).
767 vfpcc Not a real register. Represents the VFP condition
770 /* The stack backtrace structure is as follows:
771 fp points to here: | save code pointer | [fp]
772 | return link value | [fp, #-4]
773 | return sp value | [fp, #-8]
774 | return fp value | [fp, #-12]
775 [| saved r10 value |]
786 [| saved f7 value |] three words
787 [| saved f6 value |] three words
788 [| saved f5 value |] three words
789 [| saved f4 value |] three words
790 r0-r3 are not normally saved in a C function. */
792 /* 1 for registers that have pervasive standard uses
793 and are not available for the register allocator. */
794 #define FIXED_REGISTERS \
812 /* 1 for registers not available across function calls.
813 These must include the FIXED_REGISTERS and also any
814 registers that can be used without being saved.
815 The latter must include the registers where values are returned
816 and the register where structure-value addresses are passed.
817 Aside from that, you can include as many other registers as you like.
818 The CC is not preserved over function calls on the ARM 6, so it is
819 easier to assume this for all. SFP is preserved, since FP is. */
820 #define CALL_USED_REGISTERS \
838 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
839 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
842 #define CONDITIONAL_REGISTER_USAGE \
846 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
848 for (regno = FIRST_FPA_REGNUM; \
849 regno <= LAST_FPA_REGNUM; ++regno) \
850 fixed_regs[regno] = call_used_regs[regno] = 1; \
853 if (TARGET_THUMB && optimize_size) \
855 /* When optimizing for size, it's better not to use \
856 the HI regs, because of the overhead of stacking \
858 for (regno = FIRST_HI_REGNUM; \
859 regno <= LAST_HI_REGNUM; ++regno) \
860 fixed_regs[regno] = call_used_regs[regno] = 1; \
863 /* The link register can be clobbered by any branch insn, \
864 but we have no way to track that at present, so mark \
865 it as unavailable. */ \
867 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
869 if (TARGET_ARM && TARGET_HARD_FLOAT) \
871 if (TARGET_MAVERICK) \
873 for (regno = FIRST_FPA_REGNUM; \
874 regno <= LAST_FPA_REGNUM; ++ regno) \
875 fixed_regs[regno] = call_used_regs[regno] = 1; \
876 for (regno = FIRST_CIRRUS_FP_REGNUM; \
877 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
879 fixed_regs[regno] = 0; \
880 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
885 for (regno = FIRST_VFP_REGNUM; \
886 regno <= LAST_VFP_REGNUM; ++ regno) \
888 fixed_regs[regno] = 0; \
889 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
894 if (TARGET_REALLY_IWMMXT) \
896 regno = FIRST_IWMMXT_GR_REGNUM; \
897 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
898 and wCG1 as call-preserved registers. The 2002/11/21 \
899 revision changed this so that all wCG registers are \
900 scratch registers. */ \
901 for (regno = FIRST_IWMMXT_GR_REGNUM; \
902 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
903 fixed_regs[regno] = call_used_regs[regno] = 0; \
904 /* The XScale ABI has wR0 - wR9 as scratch registers, \
905 the rest as call-preserved registers. */ \
906 for (regno = FIRST_IWMMXT_REGNUM; \
907 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
909 fixed_regs[regno] = 0; \
910 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
914 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
916 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
917 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
919 else if (TARGET_APCS_STACK) \
921 fixed_regs[10] = 1; \
922 call_used_regs[10] = 1; \
924 /* -mcaller-super-interworking reserves r11 for calls to \
925 _interwork_r11_call_via_rN(). Making the register global \
926 is an easy way of ensuring that it remains valid for all \
928 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING) \
930 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
931 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
932 if (TARGET_CALLER_INTERWORKING) \
933 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
935 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
938 /* These are a couple of extensions to the formats accepted
940 %@ prints out ASM_COMMENT_START
941 %r prints out REGISTER_PREFIX reg_names[arg] */
942 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
944 fputs (ASM_COMMENT_START, FILE); \
948 fputs (REGISTER_PREFIX, FILE); \
949 fputs (reg_names [va_arg (ARGS, int)], FILE); \
952 /* Round X up to the nearest word. */
953 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
955 /* Convert fron bytes to ints. */
956 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
958 /* The number of (integer) registers required to hold a quantity of type MODE.
959 Also used for VFP registers. */
960 #define ARM_NUM_REGS(MODE) \
961 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
963 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
964 #define ARM_NUM_REGS2(MODE, TYPE) \
965 ARM_NUM_INTS ((MODE) == BLKmode ? \
966 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
968 /* The number of (integer) argument register available. */
969 #define NUM_ARG_REGS 4
971 /* Return the register number of the N'th (integer) argument. */
972 #define ARG_REGISTER(N) (N - 1)
974 /* Specify the registers used for certain standard purposes.
975 The values of these macros are register numbers. */
977 /* The number of the last argument register. */
978 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
980 /* The numbers of the Thumb register ranges. */
981 #define FIRST_LO_REGNUM 0
982 #define LAST_LO_REGNUM 7
983 #define FIRST_HI_REGNUM 8
984 #define LAST_HI_REGNUM 11
986 /* We use sjlj exceptions for backwards compatibility. */
987 #define MUST_USE_SJLJ_EXCEPTIONS 1
988 /* We can generate DWARF2 Unwind info, even though we don't use it. */
989 #define DWARF2_UNWIND_INFO 1
991 /* Use r0 and r1 to pass exception handling information. */
992 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
994 /* The register that holds the return address in exception handlers. */
995 #define ARM_EH_STACKADJ_REGNUM 2
996 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
998 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
999 as an invisible last argument (possible since varargs don't exist in
1000 Pascal), so the following is not true. */
1001 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1003 /* Define this to be where the real frame pointer is if it is not possible to
1004 work out the offset between the frame pointer and the automatic variables
1005 until after register allocation has taken place. FRAME_POINTER_REGNUM
1006 should point to a special register that we will make sure is eliminated.
1008 For the Thumb we have another problem. The TPCS defines the frame pointer
1009 as r11, and GCC believes that it is always possible to use the frame pointer
1010 as base register for addressing purposes. (See comments in
1011 find_reloads_address()). But - the Thumb does not allow high registers,
1012 including r11, to be used as base address registers. Hence our problem.
1014 The solution used here, and in the old thumb port is to use r7 instead of
1015 r11 as the hard frame pointer and to have special code to generate
1016 backtrace structures on the stack (if required to do so via a command line
1017 option) using r11. This is the only 'user visible' use of r11 as a frame
1019 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1020 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1022 #define HARD_FRAME_POINTER_REGNUM \
1024 ? ARM_HARD_FRAME_POINTER_REGNUM \
1025 : THUMB_HARD_FRAME_POINTER_REGNUM)
1027 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1029 /* Register to use for pushing function arguments. */
1030 #define STACK_POINTER_REGNUM SP_REGNUM
1032 /* ARM floating pointer registers. */
1033 #define FIRST_FPA_REGNUM 16
1034 #define LAST_FPA_REGNUM 23
1036 #define FIRST_IWMMXT_GR_REGNUM 43
1037 #define LAST_IWMMXT_GR_REGNUM 46
1038 #define FIRST_IWMMXT_REGNUM 47
1039 #define LAST_IWMMXT_REGNUM 62
1040 #define IS_IWMMXT_REGNUM(REGNUM) \
1041 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1042 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1043 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1045 /* Base register for access to local variables of the function. */
1046 #define FRAME_POINTER_REGNUM 25
1048 /* Base register for access to arguments of the function. */
1049 #define ARG_POINTER_REGNUM 26
1051 #define FIRST_CIRRUS_FP_REGNUM 27
1052 #define LAST_CIRRUS_FP_REGNUM 42
1053 #define IS_CIRRUS_REGNUM(REGNUM) \
1054 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1056 #define FIRST_VFP_REGNUM 63
1057 #define LAST_VFP_REGNUM 94
1058 #define IS_VFP_REGNUM(REGNUM) \
1059 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1061 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1062 /* + 16 Cirrus registers take us up to 43. */
1063 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1064 /* VFP adds 32 + 1 more. */
1065 #define FIRST_PSEUDO_REGISTER 96
1067 /* Value should be nonzero if functions must have frame pointers.
1068 Zero means the frame pointer need not be set up (and parms may be accessed
1069 via the stack pointer) in functions that seem suitable.
1070 If we have to have a frame pointer we might as well make use of it.
1071 APCS says that the frame pointer does not need to be pushed in leaf
1072 functions, or simple tail call functions. */
1073 #define FRAME_POINTER_REQUIRED \
1074 (current_function_has_nonlocal_label \
1075 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1077 /* Return number of consecutive hard regs needed starting at reg REGNO
1078 to hold something of mode MODE.
1079 This is ordinarily the length in words of a value of mode MODE
1080 but can be less for certain modes in special long registers.
1082 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1084 #define HARD_REGNO_NREGS(REGNO, MODE) \
1086 && REGNO >= FIRST_FPA_REGNUM \
1087 && REGNO != FRAME_POINTER_REGNUM \
1088 && REGNO != ARG_POINTER_REGNUM) \
1089 && !IS_VFP_REGNUM (REGNO) \
1090 ? 1 : ARM_NUM_REGS (MODE))
1092 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1093 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1094 arm_hard_regno_mode_ok ((REGNO), (MODE))
1096 /* Value is 1 if it is a good idea to tie two pseudo registers
1097 when one has mode MODE1 and one has mode MODE2.
1098 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1099 for any hard reg, then this must be 0 for correct output. */
1100 #define MODES_TIEABLE_P(MODE1, MODE2) \
1101 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1103 #define VALID_IWMMXT_REG_MODE(MODE) \
1104 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1106 /* The order in which register should be allocated. It is good to use ip
1107 since no saving is required (though calls clobber it) and it never contains
1108 function parameters. It is quite good to use lr since other calls may
1109 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1110 least likely to contain a function parameter; in addition results are
1113 #define REG_ALLOC_ORDER \
1115 3, 2, 1, 0, 12, 14, 4, 5, \
1116 6, 7, 8, 10, 9, 11, 13, 15, \
1117 16, 17, 18, 19, 20, 21, 22, 23, \
1118 27, 28, 29, 30, 31, 32, 33, 34, \
1119 35, 36, 37, 38, 39, 40, 41, 42, \
1120 43, 44, 45, 46, 47, 48, 49, 50, \
1121 51, 52, 53, 54, 55, 56, 57, 58, \
1124 78, 77, 76, 75, 74, 73, 72, 71, \
1125 70, 69, 68, 67, 66, 65, 64, 63, \
1126 79, 80, 81, 82, 83, 84, 85, 86, \
1127 87, 88, 89, 90, 91, 92, 93, 94, \
1131 /* Interrupt functions can only use registers that have already been
1132 saved by the prologue, even if they would normally be
1134 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1135 (! IS_INTERRUPT (cfun->machine->func_type) || \
1136 regs_ever_live[DST])
1138 /* Register and constant classes. */
1140 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1141 Now that the Thumb is involved it has become more complicated. */
1161 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1163 /* Give names of register classes as strings for dump file. */
1164 #define REG_CLASS_NAMES \
1182 /* Define which registers fit in which classes.
1183 This is an initializer for a vector of HARD_REG_SET
1184 of length N_REG_CLASSES. */
1185 #define REG_CLASS_CONTENTS \
1187 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1188 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1189 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1190 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1191 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1192 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1193 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1194 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1195 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1196 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1197 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1198 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1199 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1200 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1203 /* The same information, inverted:
1204 Return the class number of the smallest class containing
1205 reg number REGNO. This could be a conditional expression
1206 or could index an array. */
1207 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1209 /* FPA registers can't do subreg as all values are reformatted to internal
1210 precision. VFP registers may only be accessed in the mode they
1212 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1213 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1214 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1215 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1218 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1219 using r0-r4 for function arguments, r7 for the stack frame and don't
1220 have enough left over to do doubleword arithmetic. */
1221 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1222 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1223 || (CLASS) == CC_REG)
1225 /* The class value for index registers, and the one for base regs. */
1226 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1227 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1229 /* For the Thumb the high registers cannot be used as base registers
1230 when addressing quantities in QI or HI mode; if we don't know the
1231 mode, then we must be conservative. */
1232 #define MODE_BASE_REG_CLASS(MODE) \
1233 (TARGET_ARM ? GENERAL_REGS : \
1234 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1236 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1237 instead of BASE_REGS. */
1238 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1240 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1241 registers explicitly used in the rtl to be used as spill registers
1242 but prevents the compiler from extending the lifetime of these
1244 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1246 /* Get reg_class from a letter such as appears in the machine description.
1247 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1248 ARM, but several more letters for the Thumb. */
1249 #define REG_CLASS_FROM_LETTER(C) \
1250 ( (C) == 'f' ? FPA_REGS \
1251 : (C) == 'v' ? CIRRUS_REGS \
1252 : (C) == 'w' ? VFP_REGS \
1253 : (C) == 'y' ? IWMMXT_REGS \
1254 : (C) == 'z' ? IWMMXT_GR_REGS \
1255 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1256 : TARGET_ARM ? NO_REGS \
1257 : (C) == 'h' ? HI_REGS \
1258 : (C) == 'b' ? BASE_REGS \
1259 : (C) == 'k' ? STACK_REG \
1260 : (C) == 'c' ? CC_REG \
1263 /* The letters I, J, K, L and M in a register constraint string
1264 can be used to stand for particular ranges of immediate operands.
1265 This macro defines what the ranges are.
1266 C is the letter, and VALUE is a constant value.
1267 Return 1 if VALUE is in the range specified by C.
1268 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1269 J: valid indexing constants.
1270 K: ~value ok in rhs argument of data operand.
1271 L: -value ok in rhs argument of data operand.
1272 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1273 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1274 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1275 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1276 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1277 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1278 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1279 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1282 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1283 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1284 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1285 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1286 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1287 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1288 && ((VAL) & 3) == 0) : \
1289 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1290 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1293 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1295 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1297 /* Constant letter 'G' for the FP immediate constants.
1298 'H' means the same constant negated. */
1299 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1300 ((C) == 'G' ? arm_const_double_rtx (X) : \
1301 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1303 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1305 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1307 /* For the ARM, `Q' means that this is a memory operand that is just
1308 an offset from a register.
1309 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1310 address. This means that the symbol is in the text segment and can be
1311 accessed without using a load.
1312 'D' Prefixes a number of const_double operands where:
1313 'Da' is a constant that takes two ARM insns to load.
1314 'Db' takes three ARM insns.
1315 'Dc' takes four ARM insns, if we allow that in this compilation.
1316 'U' Prefixes an extended memory constraint where:
1317 'Uv' is an address valid for VFP load/store insns.
1318 'Uy' is an address valid for iwmmxt load/store insns.
1319 'Uq' is an address valid for ldrsb. */
1321 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1322 (((C) == 'D') ? (GET_CODE (OP) == CONST_DOUBLE \
1323 && (((STR)[1] == 'a' \
1324 && arm_const_double_inline_cost (OP) == 2) \
1325 || ((STR)[1] == 'b' \
1326 && arm_const_double_inline_cost (OP) == 3) \
1327 || ((STR)[1] == 'c' \
1328 && arm_const_double_inline_cost (OP) == 4 \
1329 && !(optimize_size || arm_ld_sched)))) : \
1330 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1331 && GET_CODE (XEXP (OP, 0)) == REG) : \
1332 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1333 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1334 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1335 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1336 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1337 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1338 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1339 ((C) == 'U' && (STR)[1] == 'q') \
1340 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1343 #define CONSTRAINT_LEN(C,STR) \
1344 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1346 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1347 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1348 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1350 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1352 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1353 : EXTRA_CONSTRAINT_THUMB (X, C))
1355 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1357 /* Given an rtx X being reloaded into a reg required to be
1358 in class CLASS, return the class of reg to actually use.
1359 In general this is just CLASS, but for the Thumb we prefer
1360 a LO_REGS class or a subset. */
1361 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1362 (TARGET_ARM ? (CLASS) : \
1363 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1365 /* Must leave BASE_REGS reloads alone */
1366 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1367 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1368 ? ((true_regnum (X) == -1 ? LO_REGS \
1369 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1373 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1374 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1375 ? ((true_regnum (X) == -1 ? LO_REGS \
1376 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1380 /* Return the register class of a scratch register needed to copy IN into
1381 or out of a register in CLASS in MODE. If it can be done directly,
1382 NO_REGS is returned. */
1383 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1384 /* Restrict which direct reloads are allowed for VFP regs. */ \
1385 ((TARGET_VFP && TARGET_HARD_FLOAT \
1386 && (CLASS) == VFP_REGS) \
1387 ? vfp_secondary_reload_class (MODE, X) \
1389 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1390 ? GENERAL_REGS : NO_REGS) \
1391 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1393 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1394 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1395 /* Restrict which direct reloads are allowed for VFP regs. */ \
1396 ((TARGET_VFP && TARGET_HARD_FLOAT \
1397 && (CLASS) == VFP_REGS) \
1398 ? vfp_secondary_reload_class (MODE, X) : \
1399 /* Cannot load constants into Cirrus registers. */ \
1400 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1401 && (CLASS) == CIRRUS_REGS \
1402 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1405 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1406 && CONSTANT_P (X)) \
1408 (((MODE) == HImode && ! arm_arch4 \
1409 && (GET_CODE (X) == MEM \
1410 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1411 && true_regnum (X) == -1))) \
1412 ? GENERAL_REGS : NO_REGS) \
1413 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1415 /* Try a machine-dependent way of reloading an illegitimate address
1416 operand. If we find one, push the reload and jump to WIN. This
1417 macro is used in only one place: `find_reloads_address' in reload.c.
1419 For the ARM, we wish to handle large displacements off a base
1420 register by splitting the addend across a MOV and the mem insn.
1421 This can cut the number of reloads needed. */
1422 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1425 if (GET_CODE (X) == PLUS \
1426 && GET_CODE (XEXP (X, 0)) == REG \
1427 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1428 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1429 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1431 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1432 HOST_WIDE_INT low, high; \
1434 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1435 low = ((val & 0xf) ^ 0x8) - 0x8; \
1436 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1437 /* Need to be careful, -256 is not a valid offset. */ \
1438 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1439 else if (MODE == SImode \
1440 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1441 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1442 /* Need to be careful, -4096 is not a valid offset. */ \
1443 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1444 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1445 /* Need to be careful, -256 is not a valid offset. */ \
1446 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1447 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1448 && TARGET_HARD_FLOAT && TARGET_FPA) \
1449 /* Need to be careful, -1024 is not a valid offset. */ \
1450 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1454 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1455 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1456 - (unsigned HOST_WIDE_INT) 0x80000000); \
1457 /* Check for overflow or zero */ \
1458 if (low == 0 || high == 0 || (high + low != val)) \
1461 /* Reload the high part into a base reg; leave the low part \
1463 X = gen_rtx_PLUS (GET_MODE (X), \
1464 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1467 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1468 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1469 VOIDmode, 0, 0, OPNUM, TYPE); \
1475 /* XXX If an HImode FP+large_offset address is converted to an HImode
1476 SP+large_offset address, then reload won't know how to fix it. It sees
1477 only that SP isn't valid for HImode, and so reloads the SP into an index
1478 register, but the resulting address is still invalid because the offset
1479 is too big. We fix it here instead by reloading the entire address. */
1480 /* We could probably achieve better results by defining PROMOTE_MODE to help
1481 cope with the variances between the Thumb's signed and unsigned byte and
1482 halfword load instructions. */
1483 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1485 if (GET_CODE (X) == PLUS \
1486 && GET_MODE_SIZE (MODE) < 4 \
1487 && GET_CODE (XEXP (X, 0)) == REG \
1488 && XEXP (X, 0) == stack_pointer_rtx \
1489 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1490 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1494 push_reload (orig_X, NULL_RTX, &X, NULL, \
1495 MODE_BASE_REG_CLASS (MODE), \
1496 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1501 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1503 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1505 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1507 /* Return the maximum number of consecutive registers
1508 needed to represent mode MODE in a register of class CLASS.
1509 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1510 #define CLASS_MAX_NREGS(CLASS, MODE) \
1511 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1513 /* If defined, gives a class of registers that cannot be used as the
1514 operand of a SUBREG that changes the mode of the object illegally. */
1516 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1517 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1519 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1520 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1521 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1522 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1523 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1524 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1525 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1526 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1527 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1530 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1532 /* Stack layout; function entry, exit and calling. */
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD 1
1538 /* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542 #define FRAME_GROWS_DOWNWARD 1
1544 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1545 When present, it is one word in size, and sits at the top of the frame,
1546 between the soft frame pointer and either r7 or r11.
1548 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1549 and only then if some outgoing arguments are passed on the stack. It would
1550 be tempting to also check whether the stack arguments are passed by indirect
1551 calls, but there seems to be no reason in principle why a post-reload pass
1552 couldn't convert a direct call into an indirect one. */
1553 #define CALLER_INTERWORKING_SLOT_SIZE \
1554 (TARGET_CALLER_INTERWORKING \
1555 && current_function_outgoing_args_size != 0 \
1556 ? UNITS_PER_WORD : 0)
1558 /* Offset within stack frame to start allocating local variables at.
1559 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1560 first local allocated. Otherwise, it is the offset to the BEGINNING
1561 of the first local allocated. */
1562 #define STARTING_FRAME_OFFSET 0
1564 /* If we generate an insn to push BYTES bytes,
1565 this says how many the stack pointer really advances by. */
1566 /* The push insns do not do this rounding implicitly.
1567 So don't define this. */
1568 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1570 /* Define this if the maximum size of all the outgoing args is to be
1571 accumulated and pushed during the prologue. The amount can be
1572 found in the variable current_function_outgoing_args_size. */
1573 #define ACCUMULATE_OUTGOING_ARGS 1
1575 /* Offset of first parameter from the argument pointer register value. */
1576 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1578 /* Value is the number of byte of arguments automatically
1579 popped when returning from a subroutine call.
1580 FUNDECL is the declaration node of the function (as a tree),
1581 FUNTYPE is the data type of the function (as a tree),
1582 or for a library call it is an identifier node for the subroutine name.
1583 SIZE is the number of bytes of arguments passed on the stack.
1585 On the ARM, the caller does not pop any of its arguments that were passed
1587 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1589 /* Define how to find the value returned by a library function
1590 assuming the value has mode MODE. */
1591 #define LIBCALL_VALUE(MODE) \
1592 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1593 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1594 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1595 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1596 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1597 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1598 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1599 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1600 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1602 /* Define how to find the value returned by a function.
1603 VALTYPE is the data type of the value (as a tree).
1604 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1605 otherwise, FUNC is 0. */
1606 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1607 arm_function_value (VALTYPE, FUNC);
1609 /* 1 if N is a possible register number for a function value.
1610 On the ARM, only r0 and f0 can return results. */
1611 /* On a Cirrus chip, mvf0 can return results. */
1612 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1613 ((REGNO) == ARG_REGISTER (1) \
1614 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1615 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1616 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1617 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1618 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1620 /* How large values are returned */
1621 /* A C expression which can inhibit the returning of certain function values
1622 in registers, based on the type of value. */
1623 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1625 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1626 values must be in memory. On the ARM, they need only do so if larger
1627 than a word, or if they contain elements offset from zero in the struct. */
1628 #define DEFAULT_PCC_STRUCT_RETURN 0
1630 /* Flags for the call/call_value rtl operations set up by function_arg. */
1631 #define CALL_NORMAL 0x00000000 /* No special processing. */
1632 #define CALL_LONG 0x00000001 /* Always call indirect. */
1633 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1635 /* These bits describe the different types of function supported
1636 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1637 normal function and an interworked function, for example. Knowing the
1638 type of a function is important for determining its prologue and
1640 Note value 7 is currently unassigned. Also note that the interrupt
1641 function types all have bit 2 set, so that they can be tested for easily.
1642 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1643 machine_function structure is initialized (to zero) func_type will
1644 default to unknown. This will force the first use of arm_current_func_type
1645 to call arm_compute_func_type. */
1646 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1647 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1648 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1649 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1650 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1651 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1653 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1655 /* In addition functions can have several type modifiers,
1656 outlined by these bit masks: */
1657 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1658 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1659 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1660 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1662 /* Some macros to test these flags. */
1663 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1664 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1665 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1666 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1667 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1670 /* Structure used to hold the function stack frame layout. Offsets are
1671 relative to the stack pointer on function entry. Positive offsets are
1672 in the direction of stack growth.
1673 Only soft_frame is used in thumb mode. */
1675 typedef struct arm_stack_offsets GTY(())
1677 int saved_args; /* ARG_POINTER_REGNUM. */
1678 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1680 int soft_frame; /* FRAME_POINTER_REGNUM. */
1681 int outgoing_args; /* STACK_POINTER_REGNUM. */
1685 /* A C structure for machine-specific, per-function data.
1686 This is added to the cfun structure. */
1687 typedef struct machine_function GTY(())
1689 /* Additional stack adjustment in __builtin_eh_throw. */
1690 rtx eh_epilogue_sp_ofs;
1691 /* Records if LR has to be saved for far jumps. */
1693 /* Records if ARG_POINTER was ever live. */
1694 int arg_pointer_live;
1695 /* Records if the save of LR has been eliminated. */
1696 int lr_save_eliminated;
1697 /* The size of the stack frame. Only valid after reload. */
1698 arm_stack_offsets stack_offsets;
1699 /* Records the type of the current function. */
1700 unsigned long func_type;
1701 /* Record if the function has a variable argument list. */
1702 int uses_anonymous_args;
1703 /* Records if sibcalls are blocked because an argument
1704 register is needed to preserve stack alignment. */
1705 int sibcall_blocked;
1709 /* A C type for declaring a variable that is used as the first argument of
1710 `FUNCTION_ARG' and other related values. For some target machines, the
1711 type `int' suffices and can hold the number of bytes of argument so far. */
1714 /* This is the number of registers of arguments scanned so far. */
1716 /* This is the number of iWMMXt register arguments scanned so far. */
1720 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1725 /* Define where to put the arguments to a function.
1726 Value is zero to push the argument on the stack,
1727 or a hard register in which to store the argument.
1729 MODE is the argument's machine mode.
1730 TYPE is the data type of the argument (as a tree).
1731 This is null for libcalls where that information may
1733 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1734 the preceding args and about the function being called.
1735 NAMED is nonzero if this argument is a named parameter
1736 (otherwise it is an extra parameter matching an ellipsis).
1738 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1739 other arguments are passed on the stack. If (NAMED == 0) (which happens
1740 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1741 defined), say it is passed in the stack (function_prologue will
1742 indeed make it pass in the stack if necessary). */
1743 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1744 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1746 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1747 for a call to a function whose data type is FNTYPE.
1748 For a library call, FNTYPE is 0.
1749 On the ARM, the offset starts at 0. */
1750 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1751 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1753 /* Update the data in CUM to advance over an argument
1754 of mode MODE and data type TYPE.
1755 (TYPE is null for libcalls where that information may not be available.) */
1756 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1758 if (arm_vector_mode_supported_p (MODE) \
1759 && (CUM).named_count > (CUM).nargs) \
1760 (CUM).iwmmxt_nregs += 1; \
1762 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1764 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1765 argument with the specified mode and type. If it is not defined,
1766 `PARM_BOUNDARY' is used for all arguments. */
1767 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1768 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1769 ? DOUBLEWORD_ALIGNMENT \
1772 /* 1 if N is a possible register number for function argument passing.
1773 On the ARM, r0-r3 are used to pass args. */
1774 #define FUNCTION_ARG_REGNO_P(REGNO) \
1775 (IN_RANGE ((REGNO), 0, 3) \
1776 || (TARGET_IWMMXT_ABI \
1777 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1780 /* If your target environment doesn't prefix user functions with an
1781 underscore, you may wish to re-define this to prevent any conflicts.
1782 e.g. AOF may prefix mcount with an underscore. */
1783 #ifndef ARM_MCOUNT_NAME
1784 #define ARM_MCOUNT_NAME "*mcount"
1787 /* Call the function profiler with a given profile label. The Acorn
1788 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1789 On the ARM the full profile code will look like:
1798 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1799 will output the .text section.
1801 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1802 ``prof'' doesn't seem to mind about this!
1804 Note - this version of the code is designed to work in both ARM and
1806 #ifndef ARM_FUNCTION_PROFILER
1807 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1812 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1813 IP_REGNUM, LR_REGNUM); \
1814 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1815 fputc ('\n', STREAM); \
1816 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1817 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1818 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1822 #ifdef THUMB_FUNCTION_PROFILER
1823 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1825 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1827 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1829 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1830 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1833 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1834 the stack pointer does not matter. The value is tested only in
1835 functions that have frame pointers.
1836 No definition is equivalent to always zero.
1838 On the ARM, the function epilogue recovers the stack pointer from the
1840 #define EXIT_IGNORE_STACK 1
1842 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1844 /* Determine if the epilogue should be output as RTL.
1845 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1846 #define USE_RETURN_INSN(ISCOND) \
1847 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1849 /* Definitions for register eliminations.
1851 This is an array of structures. Each structure initializes one pair
1852 of eliminable registers. The "from" register number is given first,
1853 followed by "to". Eliminations of the same "from" register are listed
1854 in order of preference.
1856 We have two registers that can be eliminated on the ARM. First, the
1857 arg pointer register can often be eliminated in favor of the stack
1858 pointer register. Secondly, the pseudo frame pointer register can always
1859 be eliminated; it is replaced with either the stack or the real frame
1860 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1861 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1863 #define ELIMINABLE_REGS \
1864 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1865 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1866 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1867 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1868 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1869 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1870 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1872 /* Given FROM and TO register numbers, say whether this elimination is
1873 allowed. Frame pointer elimination is automatically handled.
1875 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1876 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1877 pointer, we must eliminate FRAME_POINTER_REGNUM into
1878 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1879 ARG_POINTER_REGNUM. */
1880 #define CAN_ELIMINATE(FROM, TO) \
1881 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1882 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1883 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1884 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1887 /* Define the offset between two registers, one to be eliminated, and the
1888 other its replacement, at the start of a routine. */
1889 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1891 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1893 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1895 /* Special case handling of the location of arguments passed on the stack. */
1896 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1898 /* Initialize data used by insn expanders. This is called from insn_emit,
1899 once for every function before code is generated. */
1900 #define INIT_EXPANDERS arm_init_expanders ()
1902 /* Output assembler code for a block containing the constant parts
1903 of a trampoline, leaving space for the variable parts.
1905 On the ARM, (if r8 is the static chain regnum, and remembering that
1906 referencing pc adds an offset of 8) the trampoline looks like:
1909 .word static chain value
1910 .word function's address
1911 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1912 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1914 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1915 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1916 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1917 PC_REGNUM, PC_REGNUM); \
1918 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1919 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1922 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1923 Why - because it is easier. This code will always be branched to via
1924 a BX instruction and since the compiler magically generates the address
1925 of the function the linker has no opportunity to ensure that the
1926 bottom bit is set. Thus the processor will be in ARM mode when it
1927 reaches this code. So we duplicate the ARM trampoline code and add
1928 a switch into Thumb mode as well. */
1929 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1931 fprintf (FILE, "\t.code 32\n"); \
1932 fprintf (FILE, ".Ltrampoline_start:\n"); \
1933 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1934 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1935 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1936 IP_REGNUM, PC_REGNUM); \
1937 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1938 IP_REGNUM, IP_REGNUM); \
1939 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1940 fprintf (FILE, "\t.word\t0\n"); \
1941 fprintf (FILE, "\t.word\t0\n"); \
1942 fprintf (FILE, "\t.code 16\n"); \
1945 #define TRAMPOLINE_TEMPLATE(FILE) \
1947 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1949 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1951 /* Length in units of the trampoline for entering a nested function. */
1952 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1954 /* Alignment required for a trampoline in bits. */
1955 #define TRAMPOLINE_ALIGNMENT 32
1957 /* Emit RTL insns to initialize the variable parts of a trampoline.
1958 FNADDR is an RTX for the address of the function's pure code.
1959 CXT is an RTX for the static chain value for the function. */
1960 #ifndef INITIALIZE_TRAMPOLINE
1961 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1963 emit_move_insn (gen_rtx_MEM (SImode, \
1964 plus_constant (TRAMP, \
1965 TARGET_ARM ? 8 : 16)), \
1967 emit_move_insn (gen_rtx_MEM (SImode, \
1968 plus_constant (TRAMP, \
1969 TARGET_ARM ? 12 : 20)), \
1975 /* Addressing modes, and classification of registers for them. */
1976 #define HAVE_POST_INCREMENT 1
1977 #define HAVE_PRE_INCREMENT TARGET_ARM
1978 #define HAVE_POST_DECREMENT TARGET_ARM
1979 #define HAVE_PRE_DECREMENT TARGET_ARM
1980 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1981 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1982 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1983 #define HAVE_POST_MODIFY_REG TARGET_ARM
1985 /* Macros to check register numbers against specific register classes. */
1987 /* These assume that REGNO is a hard or pseudo reg number.
1988 They give nonzero only if REGNO is a hard reg of the suitable class
1989 or a pseudo reg currently allocated to a suitable hard reg.
1990 Since they use reg_renumber, they are safe only once reg_renumber
1991 has been allocated, which happens in local-alloc.c. */
1992 #define TEST_REGNO(R, TEST, VALUE) \
1993 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1995 /* On the ARM, don't allow the pc to be used. */
1996 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1997 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1998 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1999 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2001 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2002 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2003 || (GET_MODE_SIZE (MODE) >= 4 \
2004 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2006 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2008 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2009 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2011 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2012 For Thumb, we can not use SP + reg, so reject SP. */
2013 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2014 REGNO_OK_FOR_INDEX_P (X)
2016 /* For ARM code, we don't care about the mode, but for Thumb, the index
2017 must be suitable for use in a QImode load. */
2018 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2019 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2021 /* Maximum number of registers that can appear in a valid memory address.
2022 Shifts in addresses can't be by a register. */
2023 #define MAX_REGS_PER_ADDRESS 2
2025 /* Recognize any constant value that is a valid address. */
2026 /* XXX We can address any constant, eventually... */
2028 #ifdef AOF_ASSEMBLER
2030 #define CONSTANT_ADDRESS_P(X) \
2031 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2035 #define CONSTANT_ADDRESS_P(X) \
2036 (GET_CODE (X) == SYMBOL_REF \
2037 && (CONSTANT_POOL_ADDRESS_P (X) \
2038 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2040 #endif /* AOF_ASSEMBLER */
2042 /* Nonzero if the constant value X is a legitimate general operand.
2043 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2045 On the ARM, allow any integer (invalid ones are removed later by insn
2046 patterns), nice doubles and symbol_refs which refer to the function's
2049 When generating pic allow anything. */
2050 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2052 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2053 ( GET_CODE (X) == CONST_INT \
2054 || GET_CODE (X) == CONST_DOUBLE \
2055 || CONSTANT_ADDRESS_P (X) \
2058 #define LEGITIMATE_CONSTANT_P(X) \
2059 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2061 /* Special characters prefixed to function names
2062 in order to encode attribute like information.
2063 Note, '@' and '*' have already been taken. */
2064 #define SHORT_CALL_FLAG_CHAR '^'
2065 #define LONG_CALL_FLAG_CHAR '#'
2067 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2068 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2070 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2071 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2073 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2074 #define SUBTARGET_NAME_ENCODING_LENGTHS
2077 /* This is a C fragment for the inside of a switch statement.
2078 Each case label should return the number of characters to
2079 be stripped from the start of a function's name, if that
2080 name starts with the indicated character. */
2081 #define ARM_NAME_ENCODING_LENGTHS \
2082 case SHORT_CALL_FLAG_CHAR: return 1; \
2083 case LONG_CALL_FLAG_CHAR: return 1; \
2084 case '*': return 1; \
2085 SUBTARGET_NAME_ENCODING_LENGTHS
2087 /* This is how to output a reference to a user-level label named NAME.
2088 `assemble_name' uses this. */
2089 #undef ASM_OUTPUT_LABELREF
2090 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2091 arm_asm_output_labelref (FILE, NAME)
2093 /* Set the short-call flag for any function compiled in the current
2094 compilation unit. We skip this for functions with the section
2095 attribute when long-calls are in effect as this tells the compiler
2096 that the section might be placed a long way from the caller.
2097 See arm_is_longcall_p() for more information. */
2098 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2099 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
2100 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2102 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2103 and check its validity for a certain class.
2104 We have two alternate definitions for each of them.
2105 The usual definition accepts all pseudo regs; the other rejects
2106 them unless they have been allocated suitable hard regs.
2107 The symbol REG_OK_STRICT causes the latter definition to be used. */
2108 #ifndef REG_OK_STRICT
2110 #define ARM_REG_OK_FOR_BASE_P(X) \
2111 (REGNO (X) <= LAST_ARM_REGNUM \
2112 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2113 || REGNO (X) == FRAME_POINTER_REGNUM \
2114 || REGNO (X) == ARG_POINTER_REGNUM)
2116 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2117 (REGNO (X) <= LAST_LO_REGNUM \
2118 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2119 || (GET_MODE_SIZE (MODE) >= 4 \
2120 && (REGNO (X) == STACK_POINTER_REGNUM \
2121 || (X) == hard_frame_pointer_rtx \
2122 || (X) == arg_pointer_rtx)))
2124 #define REG_STRICT_P 0
2126 #else /* REG_OK_STRICT */
2128 #define ARM_REG_OK_FOR_BASE_P(X) \
2129 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2131 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2132 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2134 #define REG_STRICT_P 1
2136 #endif /* REG_OK_STRICT */
2138 /* Now define some helpers in terms of the above. */
2140 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2142 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2143 : ARM_REG_OK_FOR_BASE_P (X))
2145 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2147 /* For Thumb, a valid index register is anything that can be used in
2148 a byte load instruction. */
2149 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2151 /* Nonzero if X is a hard reg that can be used as an index
2152 or if it is a pseudo reg. On the Thumb, the stack pointer
2154 #define REG_OK_FOR_INDEX_P(X) \
2156 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2157 : ARM_REG_OK_FOR_INDEX_P (X))
2159 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2160 For Thumb, we can not use SP + reg, so reject SP. */
2161 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2162 REG_OK_FOR_INDEX_P (X)
2164 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2165 that is a valid memory address for an instruction.
2166 The MODE argument is the machine mode for the MEM expression
2167 that wants to use this address. */
2169 #define ARM_BASE_REGISTER_RTX_P(X) \
2170 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2172 #define ARM_INDEX_REGISTER_RTX_P(X) \
2173 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2175 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2177 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2181 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2183 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2187 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2189 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2190 else /* if (TARGET_THUMB) */ \
2191 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2194 /* Try machine-dependent ways of modifying an illegitimate address
2195 to be legitimate. If we find one, return the new, valid address. */
2196 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2198 X = arm_legitimize_address (X, OLDX, MODE); \
2201 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2203 X = thumb_legitimize_address (X, OLDX, MODE); \
2206 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2209 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2211 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2213 if (memory_address_p (MODE, X)) \
2217 /* Go to LABEL if ADDR (a legitimate address expression)
2218 has an effect that depends on the machine mode it is used for. */
2219 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2221 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2222 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2226 /* Nothing helpful to do for the Thumb */
2227 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2229 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2232 /* Specify the machine mode that this machine uses
2233 for the index in the tablejump instruction. */
2234 #define CASE_VECTOR_MODE Pmode
2236 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2237 unsigned is probably best, but may break some code. */
2238 #ifndef DEFAULT_SIGNED_CHAR
2239 #define DEFAULT_SIGNED_CHAR 0
2242 /* Max number of bytes we can move from memory to memory
2243 in one reasonably fast instruction. */
2247 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2249 /* Define if operations between registers always perform the operation
2250 on the full register even if a narrower mode is specified. */
2251 #define WORD_REGISTER_OPERATIONS
2253 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2254 will either zero-extend or sign-extend. The value of this macro should
2255 be the code that says which one of the two operations is implicitly
2256 done, UNKNOWN if none. */
2257 #define LOAD_EXTEND_OP(MODE) \
2258 (TARGET_THUMB ? ZERO_EXTEND : \
2259 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2260 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2262 /* Nonzero if access to memory by bytes is slow and undesirable. */
2263 #define SLOW_BYTE_ACCESS 0
2265 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2267 /* Immediate shift counts are truncated by the output routines (or was it
2268 the assembler?). Shift counts in a register are truncated by ARM. Note
2269 that the native compiler puts too large (> 32) immediate shift counts
2270 into a register and shifts by the register, letting the ARM decide what
2271 to do instead of doing that itself. */
2272 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2273 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2274 On the arm, Y in a register is used modulo 256 for the shift. Only for
2275 rotates is modulo 32 used. */
2276 /* #define SHIFT_COUNT_TRUNCATED 1 */
2278 /* All integers have the same format so truncation is easy. */
2279 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2281 /* Calling from registers is a massive pain. */
2282 #define NO_FUNCTION_CSE 1
2284 /* The machine modes of pointers and functions */
2285 #define Pmode SImode
2286 #define FUNCTION_MODE Pmode
2288 #define ARM_FRAME_RTX(X) \
2289 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2290 || (X) == arg_pointer_rtx)
2292 /* Moves to and from memory are quite expensive */
2293 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2294 (TARGET_ARM ? 10 : \
2295 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2296 * (CLASS == LO_REGS ? 1 : 2)))
2298 /* Try to generate sequences that don't involve branches, we can then use
2299 conditional instructions */
2300 #define BRANCH_COST \
2301 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2303 /* Position Independent Code. */
2304 /* We decide which register to use based on the compilation options and
2305 the assembler in use; this is more general than the APCS restriction of
2306 using sb (r9) all the time. */
2307 extern int arm_pic_register;
2309 /* Used when parsing command line option -mpic-register=. */
2310 extern const char * arm_pic_register_string;
2312 /* The register number of the register used to address a table of static
2313 data addresses in memory. */
2314 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2316 /* We can't directly access anything that contains a symbol,
2317 nor can we indirect via the constant pool. */
2318 #define LEGITIMATE_PIC_OPERAND_P(X) \
2319 (!(symbol_mentioned_p (X) \
2320 || label_mentioned_p (X) \
2321 || (GET_CODE (X) == SYMBOL_REF \
2322 && CONSTANT_POOL_ADDRESS_P (X) \
2323 && (symbol_mentioned_p (get_pool_constant (X)) \
2324 || label_mentioned_p (get_pool_constant (X))))))
2326 /* We need to know when we are making a constant pool; this determines
2327 whether data needs to be in the GOT or can be referenced via a GOT
2329 extern int making_const_table;
2331 /* Handle pragmas for compatibility with Intel's compilers. */
2332 #define REGISTER_TARGET_PRAGMAS() do { \
2333 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2334 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2335 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2338 /* Condition code information. */
2339 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2340 return the mode to be used for the comparison. */
2342 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2344 #define REVERSIBLE_CC_MODE(MODE) 1
2346 #define REVERSE_CONDITION(CODE,MODE) \
2347 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2348 ? reverse_condition_maybe_unordered (code) \
2349 : reverse_condition (code))
2351 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2354 if (GET_CODE (OP1) == CONST_INT \
2355 && ! (const_ok_for_arm (INTVAL (OP1)) \
2356 || (const_ok_for_arm (- INTVAL (OP1))))) \
2358 rtx const_op = OP1; \
2359 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2365 /* The arm5 clz instruction returns 32. */
2366 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2369 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2371 /* Output a push or a pop instruction (only used when profiling). */
2372 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2376 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2377 STACK_POINTER_REGNUM, REGNO); \
2379 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2383 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2387 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2388 STACK_POINTER_REGNUM, REGNO); \
2390 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2393 /* This is how to output a label which precedes a jumptable. Since
2394 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2395 #undef ASM_OUTPUT_CASE_LABEL
2396 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2400 ASM_OUTPUT_ALIGN (FILE, 2); \
2401 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2405 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2410 if (is_called_in_ARM_mode (DECL) \
2411 || current_function_is_thunk) \
2412 fprintf (STREAM, "\t.code 32\n") ; \
2414 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2416 if (TARGET_POKE_FUNCTION_NAME) \
2417 arm_poke_function_name (STREAM, (char *) NAME); \
2421 /* For aliases of functions we use .thumb_set instead. */
2422 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2425 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2426 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2428 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2430 fprintf (FILE, "\t.thumb_set "); \
2431 assemble_name (FILE, LABEL1); \
2432 fprintf (FILE, ","); \
2433 assemble_name (FILE, LABEL2); \
2434 fprintf (FILE, "\n"); \
2437 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2441 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2442 /* To support -falign-* switches we need to use .p2align so
2443 that alignment directives in code sections will be padded
2444 with no-op instructions, rather than zeroes. */
2445 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2448 if ((MAX_SKIP) == 0) \
2449 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2451 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2452 (int) (LOG), (int) (MAX_SKIP)); \
2456 /* Only perform branch elimination (by making instructions conditional) if
2457 we're optimizing. Otherwise it's of no use anyway. */
2458 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2459 if (TARGET_ARM && optimize) \
2460 arm_final_prescan_insn (INSN); \
2461 else if (TARGET_THUMB) \
2462 thumb_final_prescan_insn (INSN)
2464 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2465 (CODE == '@' || CODE == '|' \
2466 || (TARGET_ARM && (CODE == '?')) \
2467 || (TARGET_THUMB && (CODE == '_')))
2469 /* Output an operand of an instruction. */
2470 #define PRINT_OPERAND(STREAM, X, CODE) \
2471 arm_print_operand (STREAM, X, CODE)
2473 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2474 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2475 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2476 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2477 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2478 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2481 /* Output the address of an operand. */
2482 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2484 int is_minus = GET_CODE (X) == MINUS; \
2486 if (GET_CODE (X) == REG) \
2487 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2488 else if (GET_CODE (X) == PLUS || is_minus) \
2490 rtx base = XEXP (X, 0); \
2491 rtx index = XEXP (X, 1); \
2492 HOST_WIDE_INT offset = 0; \
2493 if (GET_CODE (base) != REG) \
2495 /* Ensure that BASE is a register. */ \
2496 /* (one of them must be). */ \
2501 switch (GET_CODE (index)) \
2504 offset = INTVAL (index); \
2507 asm_fprintf (STREAM, "[%r, #%wd]", \
2508 REGNO (base), offset); \
2512 asm_fprintf (STREAM, "[%r, %s%r]", \
2513 REGNO (base), is_minus ? "-" : "", \
2523 asm_fprintf (STREAM, "[%r, %s%r", \
2524 REGNO (base), is_minus ? "-" : "", \
2525 REGNO (XEXP (index, 0))); \
2526 arm_print_operand (STREAM, index, 'S'); \
2527 fputs ("]", STREAM); \
2535 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2536 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2538 extern enum machine_mode output_memory_reference_mode; \
2540 if (GET_CODE (XEXP (X, 0)) != REG) \
2543 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2544 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2545 REGNO (XEXP (X, 0)), \
2546 GET_CODE (X) == PRE_DEC ? "-" : "", \
2547 GET_MODE_SIZE (output_memory_reference_mode)); \
2549 asm_fprintf (STREAM, "[%r], #%s%d", \
2550 REGNO (XEXP (X, 0)), \
2551 GET_CODE (X) == POST_DEC ? "-" : "", \
2552 GET_MODE_SIZE (output_memory_reference_mode)); \
2554 else if (GET_CODE (X) == PRE_MODIFY) \
2556 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2557 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2558 asm_fprintf (STREAM, "#%wd]!", \
2559 INTVAL (XEXP (XEXP (X, 1), 1))); \
2561 asm_fprintf (STREAM, "%r]!", \
2562 REGNO (XEXP (XEXP (X, 1), 1))); \
2564 else if (GET_CODE (X) == POST_MODIFY) \
2566 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2567 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2568 asm_fprintf (STREAM, "#%wd", \
2569 INTVAL (XEXP (XEXP (X, 1), 1))); \
2571 asm_fprintf (STREAM, "%r", \
2572 REGNO (XEXP (XEXP (X, 1), 1))); \
2574 else output_addr_const (STREAM, X); \
2577 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2579 if (GET_CODE (X) == REG) \
2580 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2581 else if (GET_CODE (X) == POST_INC) \
2582 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2583 else if (GET_CODE (X) == PLUS) \
2585 if (GET_CODE (XEXP (X, 0)) != REG) \
2587 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2588 asm_fprintf (STREAM, "[%r, #%wd]", \
2589 REGNO (XEXP (X, 0)), \
2590 INTVAL (XEXP (X, 1))); \
2592 asm_fprintf (STREAM, "[%r, %r]", \
2593 REGNO (XEXP (X, 0)), \
2594 REGNO (XEXP (X, 1))); \
2597 output_addr_const (STREAM, X); \
2600 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2602 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2604 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2606 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2607 if (GET_CODE (X) != CONST_VECTOR \
2608 || ! arm_emit_vector_const (FILE, X)) \
2611 /* A C expression whose value is RTL representing the value of the return
2612 address for the frame COUNT steps up from the current frame. */
2614 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2615 arm_return_addr (COUNT, FRAME)
2617 /* Mask of the bits in the PC that contain the real return address
2618 when running in 26-bit mode. */
2619 #define RETURN_ADDR_MASK26 (0x03fffffc)
2621 /* Pick up the return address upon entry to a procedure. Used for
2622 dwarf2 unwind information. This also enables the table driven
2624 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2625 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2627 /* Used to mask out junk bits from the return address, such as
2628 processor state, interrupt status, condition codes and the like. */
2629 #define MASK_RETURN_ADDR \
2630 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2631 in 26 bit mode, the condition codes must be masked out of the \
2632 return address. This does not apply to ARM6 and later processors \
2633 when running in 32 bit mode. */ \
2634 ((arm_arch4 || TARGET_THUMB) \
2635 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2636 : arm_gen_return_addr_mask ())
2646 ARM_BUILTIN_WAVG2BR,
2647 ARM_BUILTIN_WAVG2HR,
2674 ARM_BUILTIN_TMOVMSKB,
2675 ARM_BUILTIN_TMOVMSKH,
2676 ARM_BUILTIN_TMOVMSKW,
2685 ARM_BUILTIN_WPACKHSS,
2686 ARM_BUILTIN_WPACKWSS,
2687 ARM_BUILTIN_WPACKDSS,
2688 ARM_BUILTIN_WPACKHUS,
2689 ARM_BUILTIN_WPACKWUS,
2690 ARM_BUILTIN_WPACKDUS,
2695 ARM_BUILTIN_WADDSSB,
2696 ARM_BUILTIN_WADDSSH,
2697 ARM_BUILTIN_WADDSSW,
2698 ARM_BUILTIN_WADDUSB,
2699 ARM_BUILTIN_WADDUSH,
2700 ARM_BUILTIN_WADDUSW,
2704 ARM_BUILTIN_WSUBSSB,
2705 ARM_BUILTIN_WSUBSSH,
2706 ARM_BUILTIN_WSUBSSW,
2707 ARM_BUILTIN_WSUBUSB,
2708 ARM_BUILTIN_WSUBUSH,
2709 ARM_BUILTIN_WSUBUSW,
2716 ARM_BUILTIN_WCMPEQB,
2717 ARM_BUILTIN_WCMPEQH,
2718 ARM_BUILTIN_WCMPEQW,
2719 ARM_BUILTIN_WCMPGTUB,
2720 ARM_BUILTIN_WCMPGTUH,
2721 ARM_BUILTIN_WCMPGTUW,
2722 ARM_BUILTIN_WCMPGTSB,
2723 ARM_BUILTIN_WCMPGTSH,
2724 ARM_BUILTIN_WCMPGTSW,
2726 ARM_BUILTIN_TEXTRMSB,
2727 ARM_BUILTIN_TEXTRMSH,
2728 ARM_BUILTIN_TEXTRMSW,
2729 ARM_BUILTIN_TEXTRMUB,
2730 ARM_BUILTIN_TEXTRMUH,
2731 ARM_BUILTIN_TEXTRMUW,
2781 ARM_BUILTIN_WUNPCKIHB,
2782 ARM_BUILTIN_WUNPCKIHH,
2783 ARM_BUILTIN_WUNPCKIHW,
2784 ARM_BUILTIN_WUNPCKILB,
2785 ARM_BUILTIN_WUNPCKILH,
2786 ARM_BUILTIN_WUNPCKILW,
2788 ARM_BUILTIN_WUNPCKEHSB,
2789 ARM_BUILTIN_WUNPCKEHSH,
2790 ARM_BUILTIN_WUNPCKEHSW,
2791 ARM_BUILTIN_WUNPCKEHUB,
2792 ARM_BUILTIN_WUNPCKEHUH,
2793 ARM_BUILTIN_WUNPCKEHUW,
2794 ARM_BUILTIN_WUNPCKELSB,
2795 ARM_BUILTIN_WUNPCKELSH,
2796 ARM_BUILTIN_WUNPCKELSW,
2797 ARM_BUILTIN_WUNPCKELUB,
2798 ARM_BUILTIN_WUNPCKELUH,
2799 ARM_BUILTIN_WUNPCKELUW,
2803 #endif /* ! GCC_ARM_H */
OSDN Git Service
