1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
69 builtin_define ("__ARM_NEON__"); \
71 /* Add a define for interworking. \
72 Needed when building libgcc.a. */ \
73 if (arm_cpp_interwork) \
74 builtin_define ("__THUMB_INTERWORK__"); \
76 builtin_assert ("cpu=arm"); \
77 builtin_assert ("machine=arm"); \
79 builtin_define (arm_arch_name); \
80 if (arm_arch_cirrus) \
81 builtin_define ("__MAVERICK__"); \
82 if (arm_arch_xscale) \
83 builtin_define ("__XSCALE__"); \
84 if (arm_arch_iwmmxt) \
85 builtin_define ("__IWMMXT__"); \
86 if (TARGET_AAPCS_BASED) \
87 builtin_define ("__ARM_EABI__"); \
90 /* The various ARM cores. */
93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
95 #include "arm-cores.def"
97 /* Used to indicate that no processor has been specified. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
110 /* The processor for which instructions should be scheduled. */
111 extern enum processor_type arm_tune;
113 typedef enum arm_cond_code
115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
120 extern arm_cc arm_current_cc;
122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
124 extern int arm_target_label;
125 extern int arm_ccfsm_state;
126 extern GTY(()) rtx arm_target_insn;
127 /* The label of the current constant pool. */
128 extern rtx pool_vector_label;
129 /* Set to 1 when a return insn is output, this means that the epilogue
131 extern int return_used_this_function;
132 /* Callback to output language specific object attributes. */
133 extern void (*arm_lang_output_object_attributes_hook)(void);
135 /* Just in case configure has failed to define anything. */
136 #ifndef TARGET_CPU_DEFAULT
137 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
142 #define CPP_SPEC "%(subtarget_cpp_spec) \
143 %{msoft-float:%{mhard-float: \
144 %e-msoft-float and -mhard_float may not be used together}} \
145 %{mbig-endian:%{mlittle-endian: \
146 %e-mbig-endian and -mlittle-endian may not be used together}}"
152 /* This macro defines names of additional specifications to put in the specs
153 that can be used in various specifications like CC1_SPEC. Its definition
154 is an initializer with a subgrouping for each command option.
156 Each subgrouping contains a string constant, that defines the
157 specification name, and a string constant that used by the GCC driver
160 Do not define this macro if it does not need to do anything. */
161 #define EXTRA_SPECS \
162 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
163 SUBTARGET_EXTRA_SPECS
165 #ifndef SUBTARGET_EXTRA_SPECS
166 #define SUBTARGET_EXTRA_SPECS
169 #ifndef SUBTARGET_CPP_SPEC
170 #define SUBTARGET_CPP_SPEC ""
173 /* Run-time Target Specification. */
174 #ifndef TARGET_VERSION
175 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
178 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
179 /* Use hardware floating point instructions. */
180 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
181 /* Use hardware floating point calling convention. */
182 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
183 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
184 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
185 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
186 #define TARGET_IWMMXT (arm_arch_iwmmxt)
187 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
188 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
189 #define TARGET_ARM (! TARGET_THUMB)
190 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
191 #define TARGET_BACKTRACE (leaf_function_p () \
192 ? TARGET_TPCS_LEAF_FRAME \
194 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
195 #define TARGET_AAPCS_BASED \
196 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
198 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
199 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
201 /* Only 16-bit thumb code. */
202 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
203 /* Arm or Thumb-2 32-bit code. */
204 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
205 /* 32-bit Thumb-2 code. */
206 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
208 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
210 /* The following two macros concern the ability to execute coprocessor
211 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
212 only ever tested when we know we are generating for VFP hardware; we need
213 to be more careful with TARGET_NEON as noted below. */
215 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
216 #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \
217 && (arm_fpu_arch == FPUTYPE_VFP3 \
218 || arm_fpu_arch == FPUTYPE_NEON \
219 || arm_fpu_arch == FPUTYPE_NEON_FP16))
221 /* FPU supports VFPv3 instructions. */
222 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
223 && (arm_fpu_arch == FPUTYPE_VFP3D16 \
226 /* FPU supports NEON/VFP half-precision floating-point. */
227 #define TARGET_NEON_FP16 (arm_fpu_arch == FPUTYPE_NEON_FP16)
229 /* FPU supports Neon instructions. The setting of this macro gets
230 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
231 and TARGET_HARD_FLOAT to ensure that NEON instructions are
233 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
234 && arm_fp_model == ARM_FP_MODEL_VFP \
235 && (arm_fpu_arch == FPUTYPE_NEON \
236 || arm_fpu_arch == FPUTYPE_NEON_FP16))
238 /* "DSP" multiply instructions, eg. SMULxy. */
239 #define TARGET_DSP_MULTIPLY \
240 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
241 /* Integer SIMD instructions, and extend-accumulate instructions. */
242 #define TARGET_INT_SIMD \
243 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
245 /* Should MOVW/MOVT be used in preference to a constant pool. */
246 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
248 /* We could use unified syntax for arm mode, but for now we just use it
250 #define TARGET_UNIFIED_ASM TARGET_THUMB2
253 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
254 then TARGET_AAPCS_BASED must be true -- but the converse does not
255 hold. TARGET_BPABI implies the use of the BPABI runtime library,
256 etc., in addition to just the AAPCS calling conventions. */
258 #define TARGET_BPABI false
261 /* Support for a compile-time default CPU, et cetera. The rules are:
262 --with-arch is ignored if -march or -mcpu are specified.
263 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
265 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
267 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
269 --with-fpu is ignored if -mfpu is specified.
270 --with-abi is ignored is -mabi is specified. */
271 #define OPTION_DEFAULT_SPECS \
272 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
273 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
274 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
276 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
277 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
278 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
279 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
281 /* Which floating point model to use. */
284 ARM_FP_MODEL_UNKNOWN,
285 /* FPA model (Hardware or software). */
287 /* Cirrus Maverick floating point model. */
288 ARM_FP_MODEL_MAVERICK,
289 /* VFP floating point model. */
293 extern enum arm_fp_model arm_fp_model;
295 /* Which floating point hardware is available. Also update
296 fp_model_for_fpu in arm.c when adding entries to this list. */
299 /* No FP hardware. */
301 /* Full FPA support. */
303 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
305 /* Emulated FPA hardware, Issue 3 emulator. */
307 /* Cirrus Maverick floating point co-processor. */
317 /* Neon with half-precision float extensions. */
321 /* Recast the floating point class to be the floating point attribute. */
322 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
324 /* What type of floating point to tune for */
325 extern enum fputype arm_fpu_tune;
327 /* What type of floating point instructions are available */
328 extern enum fputype arm_fpu_arch;
333 ARM_FLOAT_ABI_SOFTFP,
337 extern enum float_abi_type arm_float_abi;
339 #ifndef TARGET_DEFAULT_FLOAT_ABI
340 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
343 /* Which __fp16 format to use.
344 The enumeration values correspond to the numbering for the
345 Tag_ABI_FP_16bit_format attribute.
347 enum arm_fp16_format_type
349 ARM_FP16_FORMAT_NONE = 0,
350 ARM_FP16_FORMAT_IEEE = 1,
351 ARM_FP16_FORMAT_ALTERNATIVE = 2
354 extern enum arm_fp16_format_type arm_fp16_format;
355 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
356 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
358 /* Which ABI to use. */
368 extern enum arm_abi_type arm_abi;
370 #ifndef ARM_DEFAULT_ABI
371 #define ARM_DEFAULT_ABI ARM_ABI_APCS
374 /* Which thread pointer access sequence to use. */
381 extern enum arm_tp_type target_thread_pointer;
383 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
384 extern int arm_arch3m;
386 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
387 extern int arm_arch4;
389 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
390 extern int arm_arch4t;
392 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
393 extern int arm_arch5;
395 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
396 extern int arm_arch5e;
398 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
399 extern int arm_arch6;
401 /* Nonzero if instructions not present in the 'M' profile can be used. */
402 extern int arm_arch_notm;
404 /* Nonzero if this chip can benefit from load scheduling. */
405 extern int arm_ld_sched;
407 /* Nonzero if generating thumb code. */
408 extern int thumb_code;
410 /* Nonzero if this chip is a StrongARM. */
411 extern int arm_tune_strongarm;
413 /* Nonzero if this chip is a Cirrus variant. */
414 extern int arm_arch_cirrus;
416 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
417 extern int arm_arch_iwmmxt;
419 /* Nonzero if this chip is an XScale. */
420 extern int arm_arch_xscale;
422 /* Nonzero if tuning for XScale. */
423 extern int arm_tune_xscale;
425 /* Nonzero if tuning for stores via the write buffer. */
426 extern int arm_tune_wbuf;
428 /* Nonzero if tuning for Cortex-A9. */
429 extern int arm_tune_cortex_a9;
431 /* Nonzero if we should define __THUMB_INTERWORK__ in the
433 XXX This is a bit of a hack, it's intended to help work around
434 problems in GLD which doesn't understand that armv5t code is
435 interworking clean. */
436 extern int arm_cpp_interwork;
438 /* Nonzero if chip supports Thumb 2. */
439 extern int arm_arch_thumb2;
441 /* Nonzero if chip supports integer division instruction. */
442 extern int arm_arch_hwdiv;
444 #ifndef TARGET_DEFAULT
445 #define TARGET_DEFAULT (MASK_APCS_FRAME)
448 /* The frame pointer register used in gcc has nothing to do with debugging;
449 that is controlled by the APCS-FRAME option. */
450 #define CAN_DEBUG_WITHOUT_FP
452 #define OVERRIDE_OPTIONS arm_override_options ()
454 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
455 arm_optimization_options ((LEVEL), (SIZE))
457 /* Nonzero if PIC code requires explicit qualifiers to generate
458 PLT and GOT relocs rather than the assembler doing so implicitly.
459 Subtargets can override these if required. */
460 #ifndef NEED_GOT_RELOC
461 #define NEED_GOT_RELOC 0
463 #ifndef NEED_PLT_RELOC
464 #define NEED_PLT_RELOC 0
467 /* Nonzero if we need to refer to the GOT with a PC-relative
468 offset. In other words, generate
470 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
474 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
476 The default is true, which matches NetBSD. Subtargets can
477 override this if required. */
482 /* Target machine storage Layout. */
485 /* Define this macro if it is advisable to hold scalars in registers
486 in a wider mode than that declared by the program. In such cases,
487 the value is constrained to be within the bounds of the declared
488 type, but kept valid in the wider mode. The signedness of the
489 extension may differ from that of the type. */
491 /* It is far faster to zero extend chars than to sign extend them */
493 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
494 if (GET_MODE_CLASS (MODE) == MODE_INT \
495 && GET_MODE_SIZE (MODE) < 4) \
497 if (MODE == QImode) \
499 else if (MODE == HImode) \
504 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
505 if (GET_MODE_CLASS (MODE) == MODE_INT \
506 && GET_MODE_SIZE (MODE) < 4) \
509 /* Define this if most significant bit is lowest numbered
510 in instructions that operate on numbered bit-fields. */
511 #define BITS_BIG_ENDIAN 0
513 /* Define this if most significant byte of a word is the lowest numbered.
514 Most ARM processors are run in little endian mode, so that is the default.
515 If you want to have it run-time selectable, change the definition in a
516 cover file to be TARGET_BIG_ENDIAN. */
517 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
519 /* Define this if most significant word of a multiword number is the lowest
521 This is always false, even when in big-endian mode. */
522 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
524 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
525 on processor pre-defineds when compiling libgcc2.c. */
526 #if defined(__ARMEB__) && !defined(__ARMWEL__)
527 #define LIBGCC2_WORDS_BIG_ENDIAN 1
529 #define LIBGCC2_WORDS_BIG_ENDIAN 0
532 /* Define this if most significant word of doubles is the lowest numbered.
533 The rules are different based on whether or not we use FPA-format,
534 VFP-format or some other floating point co-processor's format doubles. */
535 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
537 #define UNITS_PER_WORD 4
539 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
540 registers when autovectorizing for Neon, at least until multiple vector
541 widths are supported properly by the middle-end. */
542 #define UNITS_PER_SIMD_WORD(MODE) \
543 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
545 /* True if natural alignment is used for doubleword types. */
546 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
548 #define DOUBLEWORD_ALIGNMENT 64
550 #define PARM_BOUNDARY 32
552 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
554 #define PREFERRED_STACK_BOUNDARY \
555 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
557 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
559 /* The lowest bit is used to indicate Thumb-mode functions, so the
560 vbit must go into the delta field of pointers to member
562 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
564 #define EMPTY_FIELD_BOUNDARY 32
566 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
568 /* XXX Blah -- this macro is used directly by libobjc. Since it
569 supports no vector modes, cut out the complexity and fall back
570 on BIGGEST_FIELD_ALIGNMENT. */
571 #ifdef IN_TARGET_LIBS
572 #define BIGGEST_FIELD_ALIGNMENT 64
575 /* Make strings word-aligned so strcpy from constants will be faster. */
576 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
578 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
579 ((TREE_CODE (EXP) == STRING_CST \
581 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
582 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
584 /* Align definitions of arrays, unions and structures so that
585 initializations and copies can be made more efficient. This is not
586 ABI-changing, so it only affects places where we can see the
588 #define DATA_ALIGNMENT(EXP, ALIGN) \
589 ((((ALIGN) < BITS_PER_WORD) \
590 && (TREE_CODE (EXP) == ARRAY_TYPE \
591 || TREE_CODE (EXP) == UNION_TYPE \
592 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
594 /* Similarly, make sure that objects on the stack are sensibly aligned. */
595 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
597 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
598 value set in previous versions of this toolchain was 8, which produces more
599 compact structures. The command line option -mstructure_size_boundary=<n>
600 can be used to change this value. For compatibility with the ARM SDK
601 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
602 0020D) page 2-20 says "Structures are aligned on word boundaries".
603 The AAPCS specifies a value of 8. */
604 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
605 extern int arm_structure_size_boundary;
607 /* This is the value used to initialize arm_structure_size_boundary. If a
608 particular arm target wants to change the default value it should change
609 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
610 for an example of this. */
611 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
612 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
615 /* Nonzero if move instructions will actually fail to work
616 when given unaligned data. */
617 #define STRICT_ALIGNMENT 1
619 /* wchar_t is unsigned under the AAPCS. */
621 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
623 #define WCHAR_TYPE_SIZE BITS_PER_WORD
627 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
631 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
634 /* AAPCS requires that structure alignment is affected by bitfields. */
635 #ifndef PCC_BITFIELD_TYPE_MATTERS
636 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
640 /* Standard register usage. */
642 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
643 (S - saved over call).
645 r0 * argument word/integer result
648 r4-r8 S register variable
649 r9 S (rfp) register variable (real frame pointer)
651 r10 F S (sl) stack limit (used by -mapcs-stack-check)
652 r11 F S (fp) argument pointer
653 r12 (ip) temp workspace
654 r13 F S (sp) lower end of current stack frame
655 r14 (lr) link address/workspace
656 r15 F (pc) program counter
658 f0 floating point result
659 f1-f3 floating point scratch
661 f4-f7 S floating point variable
663 cc This is NOT a real register, but is used internally
664 to represent things that use or set the condition
666 sfp This isn't either. It is used during rtl generation
667 since the offset between the frame pointer and the
668 auto's isn't known until after register allocation.
669 afp Nor this, we only need this because of non-local
670 goto. Without it fp appears to be used and the
671 elimination code won't get rid of sfp. It tracks
672 fp exactly at all times.
674 *: See CONDITIONAL_REGISTER_USAGE */
677 mvf0 Cirrus floating point result
678 mvf1-mvf3 Cirrus floating point scratch
679 mvf4-mvf15 S Cirrus floating point variable. */
681 /* s0-s15 VFP scratch (aka d0-d7).
682 s16-s31 S VFP variable (aka d8-d15).
683 vfpcc Not a real register. Represents the VFP condition
686 /* The stack backtrace structure is as follows:
687 fp points to here: | save code pointer | [fp]
688 | return link value | [fp, #-4]
689 | return sp value | [fp, #-8]
690 | return fp value | [fp, #-12]
691 [| saved r10 value |]
702 [| saved f7 value |] three words
703 [| saved f6 value |] three words
704 [| saved f5 value |] three words
705 [| saved f4 value |] three words
706 r0-r3 are not normally saved in a C function. */
708 /* 1 for registers that have pervasive standard uses
709 and are not available for the register allocator. */
710 #define FIXED_REGISTERS \
732 /* 1 for registers not available across function calls.
733 These must include the FIXED_REGISTERS and also any
734 registers that can be used without being saved.
735 The latter must include the registers where values are returned
736 and the register where structure-value addresses are passed.
737 Aside from that, you can include as many other registers as you like.
738 The CC is not preserved over function calls on the ARM 6, so it is
739 easier to assume this for all. SFP is preserved, since FP is. */
740 #define CALL_USED_REGISTERS \
762 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
763 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
766 #define CONDITIONAL_REGISTER_USAGE \
770 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
772 for (regno = FIRST_FPA_REGNUM; \
773 regno <= LAST_FPA_REGNUM; ++regno) \
774 fixed_regs[regno] = call_used_regs[regno] = 1; \
777 if (TARGET_THUMB && optimize_size) \
779 /* When optimizing for size, it's better not to use \
780 the HI regs, because of the overhead of stacking \
782 /* ??? Is this still true for thumb2? */ \
783 for (regno = FIRST_HI_REGNUM; \
784 regno <= LAST_HI_REGNUM; ++regno) \
785 fixed_regs[regno] = call_used_regs[regno] = 1; \
788 /* The link register can be clobbered by any branch insn, \
789 but we have no way to track that at present, so mark \
790 it as unavailable. */ \
792 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
794 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
796 if (TARGET_MAVERICK) \
798 for (regno = FIRST_FPA_REGNUM; \
799 regno <= LAST_FPA_REGNUM; ++ regno) \
800 fixed_regs[regno] = call_used_regs[regno] = 1; \
801 for (regno = FIRST_CIRRUS_FP_REGNUM; \
802 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
804 fixed_regs[regno] = 0; \
805 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
810 /* VFPv3 registers are disabled when earlier VFP \
811 versions are selected due to the definition of \
812 LAST_VFP_REGNUM. */ \
813 for (regno = FIRST_VFP_REGNUM; \
814 regno <= LAST_VFP_REGNUM; ++ regno) \
816 fixed_regs[regno] = 0; \
817 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
818 || regno >= FIRST_VFP_REGNUM + 32; \
823 if (TARGET_REALLY_IWMMXT) \
825 regno = FIRST_IWMMXT_GR_REGNUM; \
826 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
827 and wCG1 as call-preserved registers. The 2002/11/21 \
828 revision changed this so that all wCG registers are \
829 scratch registers. */ \
830 for (regno = FIRST_IWMMXT_GR_REGNUM; \
831 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
832 fixed_regs[regno] = 0; \
833 /* The XScale ABI has wR0 - wR9 as scratch registers, \
834 the rest as call-preserved registers. */ \
835 for (regno = FIRST_IWMMXT_REGNUM; \
836 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
838 fixed_regs[regno] = 0; \
839 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
843 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
845 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
846 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
848 else if (TARGET_APCS_STACK) \
850 fixed_regs[10] = 1; \
851 call_used_regs[10] = 1; \
853 /* -mcaller-super-interworking reserves r11 for calls to \
854 _interwork_r11_call_via_rN(). Making the register global \
855 is an easy way of ensuring that it remains valid for all \
857 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
858 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
860 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
861 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
862 if (TARGET_CALLER_INTERWORKING) \
863 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
865 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
868 /* These are a couple of extensions to the formats accepted
870 %@ prints out ASM_COMMENT_START
871 %r prints out REGISTER_PREFIX reg_names[arg] */
872 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
874 fputs (ASM_COMMENT_START, FILE); \
878 fputs (REGISTER_PREFIX, FILE); \
879 fputs (reg_names [va_arg (ARGS, int)], FILE); \
882 /* Round X up to the nearest word. */
883 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
885 /* Convert fron bytes to ints. */
886 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
888 /* The number of (integer) registers required to hold a quantity of type MODE.
889 Also used for VFP registers. */
890 #define ARM_NUM_REGS(MODE) \
891 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
893 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
894 #define ARM_NUM_REGS2(MODE, TYPE) \
895 ARM_NUM_INTS ((MODE) == BLKmode ? \
896 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
898 /* The number of (integer) argument register available. */
899 #define NUM_ARG_REGS 4
901 /* Return the register number of the N'th (integer) argument. */
902 #define ARG_REGISTER(N) (N - 1)
904 /* Specify the registers used for certain standard purposes.
905 The values of these macros are register numbers. */
907 /* The number of the last argument register. */
908 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
910 /* The numbers of the Thumb register ranges. */
911 #define FIRST_LO_REGNUM 0
912 #define LAST_LO_REGNUM 7
913 #define FIRST_HI_REGNUM 8
914 #define LAST_HI_REGNUM 11
916 #ifndef TARGET_UNWIND_INFO
917 /* We use sjlj exceptions for backwards compatibility. */
918 #define MUST_USE_SJLJ_EXCEPTIONS 1
921 /* We can generate DWARF2 Unwind info, even though we don't use it. */
922 #define DWARF2_UNWIND_INFO 1
924 /* Use r0 and r1 to pass exception handling information. */
925 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
927 /* The register that holds the return address in exception handlers. */
928 #define ARM_EH_STACKADJ_REGNUM 2
929 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
931 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
932 as an invisible last argument (possible since varargs don't exist in
933 Pascal), so the following is not true. */
934 #define STATIC_CHAIN_REGNUM 12
936 /* Define this to be where the real frame pointer is if it is not possible to
937 work out the offset between the frame pointer and the automatic variables
938 until after register allocation has taken place. FRAME_POINTER_REGNUM
939 should point to a special register that we will make sure is eliminated.
941 For the Thumb we have another problem. The TPCS defines the frame pointer
942 as r11, and GCC believes that it is always possible to use the frame pointer
943 as base register for addressing purposes. (See comments in
944 find_reloads_address()). But - the Thumb does not allow high registers,
945 including r11, to be used as base address registers. Hence our problem.
947 The solution used here, and in the old thumb port is to use r7 instead of
948 r11 as the hard frame pointer and to have special code to generate
949 backtrace structures on the stack (if required to do so via a command line
950 option) using r11. This is the only 'user visible' use of r11 as a frame
952 #define ARM_HARD_FRAME_POINTER_REGNUM 11
953 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
955 #define HARD_FRAME_POINTER_REGNUM \
957 ? ARM_HARD_FRAME_POINTER_REGNUM \
958 : THUMB_HARD_FRAME_POINTER_REGNUM)
960 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
962 /* Register to use for pushing function arguments. */
963 #define STACK_POINTER_REGNUM SP_REGNUM
965 /* ARM floating pointer registers. */
966 #define FIRST_FPA_REGNUM 16
967 #define LAST_FPA_REGNUM 23
968 #define IS_FPA_REGNUM(REGNUM) \
969 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
971 #define FIRST_IWMMXT_GR_REGNUM 43
972 #define LAST_IWMMXT_GR_REGNUM 46
973 #define FIRST_IWMMXT_REGNUM 47
974 #define LAST_IWMMXT_REGNUM 62
975 #define IS_IWMMXT_REGNUM(REGNUM) \
976 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
977 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
978 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
980 /* Base register for access to local variables of the function. */
981 #define FRAME_POINTER_REGNUM 25
983 /* Base register for access to arguments of the function. */
984 #define ARG_POINTER_REGNUM 26
986 #define FIRST_CIRRUS_FP_REGNUM 27
987 #define LAST_CIRRUS_FP_REGNUM 42
988 #define IS_CIRRUS_REGNUM(REGNUM) \
989 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
991 #define FIRST_VFP_REGNUM 63
992 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
993 #define LAST_VFP_REGNUM \
994 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
996 #define IS_VFP_REGNUM(REGNUM) \
997 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
999 /* VFP registers are split into two types: those defined by VFP versions < 3
1000 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1001 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1002 in various parts of the backend, we implement as "fake" single-precision
1003 registers (which would be S32-S63, but cannot be used in that way). The
1004 following macros define these ranges of registers. */
1005 #define LAST_LO_VFP_REGNUM 94
1006 #define FIRST_HI_VFP_REGNUM 95
1007 #define LAST_HI_VFP_REGNUM 126
1009 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1010 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1012 /* DFmode values are only valid in even register pairs. */
1013 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1014 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1016 /* Neon Quad values must start at a multiple of four registers. */
1017 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1018 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1020 /* Neon structures of vectors must be in even register pairs and there
1021 must be enough registers available. Because of various patterns
1022 requiring quad registers, we require them to start at a multiple of
1024 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1025 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1026 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1028 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1029 /* + 16 Cirrus registers take us up to 43. */
1030 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1031 /* VFP (VFP3) adds 32 (64) + 1 more. */
1032 #define FIRST_PSEUDO_REGISTER 128
1034 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1036 /* Value should be nonzero if functions must have frame pointers.
1037 Zero means the frame pointer need not be set up (and parms may be accessed
1038 via the stack pointer) in functions that seem suitable.
1039 If we have to have a frame pointer we might as well make use of it.
1040 APCS says that the frame pointer does not need to be pushed in leaf
1041 functions, or simple tail call functions. */
1043 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1044 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1047 #define FRAME_POINTER_REQUIRED \
1048 (cfun->has_nonlocal_label \
1049 || SUBTARGET_FRAME_POINTER_REQUIRED \
1050 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1052 /* Return number of consecutive hard regs needed starting at reg REGNO
1053 to hold something of mode MODE.
1054 This is ordinarily the length in words of a value of mode MODE
1055 but can be less for certain modes in special long registers.
1057 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1059 #define HARD_REGNO_NREGS(REGNO, MODE) \
1061 && REGNO >= FIRST_FPA_REGNUM \
1062 && REGNO != FRAME_POINTER_REGNUM \
1063 && REGNO != ARG_POINTER_REGNUM) \
1064 && !IS_VFP_REGNUM (REGNO) \
1065 ? 1 : ARM_NUM_REGS (MODE))
1067 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1068 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1069 arm_hard_regno_mode_ok ((REGNO), (MODE))
1071 /* Value is 1 if it is a good idea to tie two pseudo registers
1072 when one has mode MODE1 and one has mode MODE2.
1073 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1074 for any hard reg, then this must be 0 for correct output. */
1075 #define MODES_TIEABLE_P(MODE1, MODE2) \
1076 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1078 #define VALID_IWMMXT_REG_MODE(MODE) \
1079 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1081 /* Modes valid for Neon D registers. */
1082 #define VALID_NEON_DREG_MODE(MODE) \
1083 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1084 || (MODE) == V2SFmode || (MODE) == DImode)
1086 /* Modes valid for Neon Q registers. */
1087 #define VALID_NEON_QREG_MODE(MODE) \
1088 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1089 || (MODE) == V4SFmode || (MODE) == V2DImode)
1091 /* Structure modes valid for Neon registers. */
1092 #define VALID_NEON_STRUCT_MODE(MODE) \
1093 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1094 || (MODE) == CImode || (MODE) == XImode)
1096 /* The order in which register should be allocated. It is good to use ip
1097 since no saving is required (though calls clobber it) and it never contains
1098 function parameters. It is quite good to use lr since other calls may
1099 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1100 least likely to contain a function parameter; in addition results are
1102 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1103 then D8-D15. The reason for doing this is to attempt to reduce register
1104 pressure when both single- and double-precision registers are used in a
1107 #define REG_ALLOC_ORDER \
1109 3, 2, 1, 0, 12, 14, 4, 5, \
1110 6, 7, 8, 10, 9, 11, 13, 15, \
1111 16, 17, 18, 19, 20, 21, 22, 23, \
1112 27, 28, 29, 30, 31, 32, 33, 34, \
1113 35, 36, 37, 38, 39, 40, 41, 42, \
1114 43, 44, 45, 46, 47, 48, 49, 50, \
1115 51, 52, 53, 54, 55, 56, 57, 58, \
1118 95, 96, 97, 98, 99, 100, 101, 102, \
1119 103, 104, 105, 106, 107, 108, 109, 110, \
1120 111, 112, 113, 114, 115, 116, 117, 118, \
1121 119, 120, 121, 122, 123, 124, 125, 126, \
1122 78, 77, 76, 75, 74, 73, 72, 71, \
1123 70, 69, 68, 67, 66, 65, 64, 63, \
1124 79, 80, 81, 82, 83, 84, 85, 86, \
1125 87, 88, 89, 90, 91, 92, 93, 94, \
1129 /* Use different register alloc ordering for Thumb. */
1130 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
1132 /* Interrupt functions can only use registers that have already been
1133 saved by the prologue, even if they would normally be
1135 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1136 (! IS_INTERRUPT (cfun->machine->func_type) || \
1137 df_regs_ever_live_p (DST))
1139 /* Register and constant classes. */
1141 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1142 Now that the Thumb is involved it has become more complicated. */
1166 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1168 /* Give names of register classes as strings for dump file. */
1169 #define REG_CLASS_NAMES \
1191 /* Define which registers fit in which classes.
1192 This is an initializer for a vector of HARD_REG_SET
1193 of length N_REG_CLASSES. */
1194 #define REG_CLASS_CONTENTS \
1196 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1197 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1198 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1199 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1200 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1201 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1202 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1203 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1204 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1205 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1206 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1207 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1208 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1209 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1210 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1211 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1212 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1213 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1216 /* Any of the VFP register classes. */
1217 #define IS_VFP_CLASS(X) \
1218 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1219 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1221 /* The same information, inverted:
1222 Return the class number of the smallest class containing
1223 reg number REGNO. This could be a conditional expression
1224 or could index an array. */
1225 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1227 /* The following macro defines cover classes for Integrated Register
1228 Allocator. Cover classes is a set of non-intersected register
1229 classes covering all hard registers used for register allocation
1230 purpose. Any move between two registers of a cover class should be
1231 cheaper than load or store of the registers. The macro value is
1232 array of register classes with LIM_REG_CLASSES used as the end
1235 #define IRA_COVER_CLASSES \
1237 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1241 /* FPA registers can't do subreg as all values are reformatted to internal
1242 precision. VFP registers may only be accessed in the mode they
1244 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1245 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1246 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1247 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1250 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1251 using r0-r4 for function arguments, r7 for the stack frame and don't
1252 have enough left over to do doubleword arithmetic. */
1253 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1254 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1255 || (CLASS) == CC_REG)
1257 /* The class value for index registers, and the one for base regs. */
1258 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1259 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1261 /* For the Thumb the high registers cannot be used as base registers
1262 when addressing quantities in QI or HI mode; if we don't know the
1263 mode, then we must be conservative. */
1264 #define MODE_BASE_REG_CLASS(MODE) \
1265 (TARGET_32BIT ? CORE_REGS : \
1266 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1268 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1269 instead of BASE_REGS. */
1270 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1272 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1273 registers explicitly used in the rtl to be used as spill registers
1274 but prevents the compiler from extending the lifetime of these
1276 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1278 /* Given an rtx X being reloaded into a reg required to be
1279 in class CLASS, return the class of reg to actually use.
1280 In general this is just CLASS, but for the Thumb core registers and
1281 immediate constants we prefer a LO_REGS class or a subset. */
1282 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1283 (TARGET_ARM ? (CLASS) : \
1284 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1285 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1286 ? LO_REGS : (CLASS)))
1288 /* Must leave BASE_REGS reloads alone */
1289 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1290 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1291 ? ((true_regnum (X) == -1 ? LO_REGS \
1292 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1296 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1297 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1298 ? ((true_regnum (X) == -1 ? LO_REGS \
1299 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1303 /* Return the register class of a scratch register needed to copy IN into
1304 or out of a register in CLASS in MODE. If it can be done directly,
1305 NO_REGS is returned. */
1306 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1307 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1308 ((TARGET_VFP && TARGET_HARD_FLOAT \
1309 && IS_VFP_CLASS (CLASS)) \
1310 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1311 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1312 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1314 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1315 ? GENERAL_REGS : NO_REGS) \
1316 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1318 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1319 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1320 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1321 ((TARGET_VFP && TARGET_HARD_FLOAT \
1322 && IS_VFP_CLASS (CLASS)) \
1323 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1324 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1325 coproc_secondary_reload_class (MODE, X, TRUE) : \
1326 /* Cannot load constants into Cirrus registers. */ \
1327 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1328 && (CLASS) == CIRRUS_REGS \
1329 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1332 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1333 && CONSTANT_P (X)) \
1335 (((MODE) == HImode && ! arm_arch4 \
1336 && (GET_CODE (X) == MEM \
1337 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1338 && true_regnum (X) == -1))) \
1339 ? GENERAL_REGS : NO_REGS) \
1340 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1342 /* Try a machine-dependent way of reloading an illegitimate address
1343 operand. If we find one, push the reload and jump to WIN. This
1344 macro is used in only one place: `find_reloads_address' in reload.c.
1346 For the ARM, we wish to handle large displacements off a base
1347 register by splitting the addend across a MOV and the mem insn.
1348 This can cut the number of reloads needed. */
1349 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1352 if (GET_CODE (X) == PLUS \
1353 && GET_CODE (XEXP (X, 0)) == REG \
1354 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1355 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1356 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1358 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1359 HOST_WIDE_INT low, high; \
1361 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1362 low = ((val & 0xf) ^ 0x8) - 0x8; \
1363 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1364 /* Need to be careful, -256 is not a valid offset. */ \
1365 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1366 else if (MODE == SImode \
1367 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1368 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1369 /* Need to be careful, -4096 is not a valid offset. */ \
1370 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1371 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1372 /* Need to be careful, -256 is not a valid offset. */ \
1373 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1374 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1375 && TARGET_HARD_FLOAT && TARGET_FPA) \
1376 /* Need to be careful, -1024 is not a valid offset. */ \
1377 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1381 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1382 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1383 - (unsigned HOST_WIDE_INT) 0x80000000); \
1384 /* Check for overflow or zero */ \
1385 if (low == 0 || high == 0 || (high + low != val)) \
1388 /* Reload the high part into a base reg; leave the low part \
1390 X = gen_rtx_PLUS (GET_MODE (X), \
1391 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1394 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1395 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1396 VOIDmode, 0, 0, OPNUM, TYPE); \
1402 /* XXX If an HImode FP+large_offset address is converted to an HImode
1403 SP+large_offset address, then reload won't know how to fix it. It sees
1404 only that SP isn't valid for HImode, and so reloads the SP into an index
1405 register, but the resulting address is still invalid because the offset
1406 is too big. We fix it here instead by reloading the entire address. */
1407 /* We could probably achieve better results by defining PROMOTE_MODE to help
1408 cope with the variances between the Thumb's signed and unsigned byte and
1409 halfword load instructions. */
1410 /* ??? This should be safe for thumb2, but we may be able to do better. */
1411 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1413 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1421 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1423 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1425 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1427 /* Return the maximum number of consecutive registers
1428 needed to represent mode MODE in a register of class CLASS.
1429 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1430 #define CLASS_MAX_NREGS(CLASS, MODE) \
1431 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1433 /* If defined, gives a class of registers that cannot be used as the
1434 operand of a SUBREG that changes the mode of the object illegally. */
1436 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1437 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1439 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1440 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1441 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1442 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1443 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1444 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1445 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1446 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1447 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1450 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1452 /* Stack layout; function entry, exit and calling. */
1454 /* Define this if pushing a word on the stack
1455 makes the stack pointer a smaller address. */
1456 #define STACK_GROWS_DOWNWARD 1
1458 /* Define this to nonzero if the nominal address of the stack frame
1459 is at the high-address end of the local variables;
1460 that is, each additional local variable allocated
1461 goes at a more negative offset in the frame. */
1462 #define FRAME_GROWS_DOWNWARD 1
1464 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1465 When present, it is one word in size, and sits at the top of the frame,
1466 between the soft frame pointer and either r7 or r11.
1468 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1469 and only then if some outgoing arguments are passed on the stack. It would
1470 be tempting to also check whether the stack arguments are passed by indirect
1471 calls, but there seems to be no reason in principle why a post-reload pass
1472 couldn't convert a direct call into an indirect one. */
1473 #define CALLER_INTERWORKING_SLOT_SIZE \
1474 (TARGET_CALLER_INTERWORKING \
1475 && crtl->outgoing_args_size != 0 \
1476 ? UNITS_PER_WORD : 0)
1478 /* Offset within stack frame to start allocating local variables at.
1479 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1480 first local allocated. Otherwise, it is the offset to the BEGINNING
1481 of the first local allocated. */
1482 #define STARTING_FRAME_OFFSET 0
1484 /* If we generate an insn to push BYTES bytes,
1485 this says how many the stack pointer really advances by. */
1486 /* The push insns do not do this rounding implicitly.
1487 So don't define this. */
1488 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1490 /* Define this if the maximum size of all the outgoing args is to be
1491 accumulated and pushed during the prologue. The amount can be
1492 found in the variable crtl->outgoing_args_size. */
1493 #define ACCUMULATE_OUTGOING_ARGS 1
1495 /* Offset of first parameter from the argument pointer register value. */
1496 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1498 /* Value is the number of byte of arguments automatically
1499 popped when returning from a subroutine call.
1500 FUNDECL is the declaration node of the function (as a tree),
1501 FUNTYPE is the data type of the function (as a tree),
1502 or for a library call it is an identifier node for the subroutine name.
1503 SIZE is the number of bytes of arguments passed on the stack.
1505 On the ARM, the caller does not pop any of its arguments that were passed
1507 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1509 /* Define how to find the value returned by a library function
1510 assuming the value has mode MODE. */
1511 #define LIBCALL_VALUE(MODE) \
1512 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1513 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1514 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1515 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1516 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1517 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1518 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1519 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1520 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1522 /* Define how to find the value returned by a function.
1523 VALTYPE is the data type of the value (as a tree).
1524 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1525 otherwise, FUNC is 0. */
1526 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1527 arm_function_value (VALTYPE, FUNC);
1529 /* 1 if N is a possible register number for a function value.
1530 On the ARM, only r0 and f0 can return results. */
1531 /* On a Cirrus chip, mvf0 can return results. */
1532 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1533 ((REGNO) == ARG_REGISTER (1) \
1534 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1535 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1536 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1537 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1538 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1540 /* Amount of memory needed for an untyped call to save all possible return
1542 #define APPLY_RESULT_SIZE arm_apply_result_size()
1544 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1545 values must be in memory. On the ARM, they need only do so if larger
1546 than a word, or if they contain elements offset from zero in the struct. */
1547 #define DEFAULT_PCC_STRUCT_RETURN 0
1549 /* These bits describe the different types of function supported
1550 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1551 normal function and an interworked function, for example. Knowing the
1552 type of a function is important for determining its prologue and
1554 Note value 7 is currently unassigned. Also note that the interrupt
1555 function types all have bit 2 set, so that they can be tested for easily.
1556 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1557 machine_function structure is initialized (to zero) func_type will
1558 default to unknown. This will force the first use of arm_current_func_type
1559 to call arm_compute_func_type. */
1560 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1561 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1562 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1563 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1564 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1565 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1567 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1569 /* In addition functions can have several type modifiers,
1570 outlined by these bit masks: */
1571 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1572 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1573 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1574 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1575 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1577 /* Some macros to test these flags. */
1578 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1579 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1580 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1581 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1582 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1583 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1586 /* Structure used to hold the function stack frame layout. Offsets are
1587 relative to the stack pointer on function entry. Positive offsets are
1588 in the direction of stack growth.
1589 Only soft_frame is used in thumb mode. */
1591 typedef struct GTY(()) arm_stack_offsets
1593 int saved_args; /* ARG_POINTER_REGNUM. */
1594 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1596 int soft_frame; /* FRAME_POINTER_REGNUM. */
1597 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1598 int outgoing_args; /* STACK_POINTER_REGNUM. */
1599 unsigned int saved_regs_mask;
1603 /* A C structure for machine-specific, per-function data.
1604 This is added to the cfun structure. */
1605 typedef struct GTY(()) machine_function
1607 /* Additional stack adjustment in __builtin_eh_throw. */
1608 rtx eh_epilogue_sp_ofs;
1609 /* Records if LR has to be saved for far jumps. */
1611 /* Records if ARG_POINTER was ever live. */
1612 int arg_pointer_live;
1613 /* Records if the save of LR has been eliminated. */
1614 int lr_save_eliminated;
1615 /* The size of the stack frame. Only valid after reload. */
1616 arm_stack_offsets stack_offsets;
1617 /* Records the type of the current function. */
1618 unsigned long func_type;
1619 /* Record if the function has a variable argument list. */
1620 int uses_anonymous_args;
1621 /* Records if sibcalls are blocked because an argument
1622 register is needed to preserve stack alignment. */
1623 int sibcall_blocked;
1624 /* The PIC register for this function. This might be a pseudo. */
1626 /* Labels for per-function Thumb call-via stubs. One per potential calling
1627 register. We can never call via LR or PC. We can call via SP if a
1628 trampoline happens to be on the top of the stack. */
1630 /* Set to 1 when a return insn is output, this means that the epilogue
1632 int return_used_this_function;
1636 /* As in the machine_function, a global set of call-via labels, for code
1637 that is in text_section. */
1638 extern GTY(()) rtx thumb_call_via_label[14];
1640 /* A C type for declaring a variable that is used as the first argument of
1641 `FUNCTION_ARG' and other related values. For some target machines, the
1642 type `int' suffices and can hold the number of bytes of argument so far. */
1645 /* This is the number of registers of arguments scanned so far. */
1647 /* This is the number of iWMMXt register arguments scanned so far. */
1654 /* Define where to put the arguments to a function.
1655 Value is zero to push the argument on the stack,
1656 or a hard register in which to store the argument.
1658 MODE is the argument's machine mode.
1659 TYPE is the data type of the argument (as a tree).
1660 This is null for libcalls where that information may
1662 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1663 the preceding args and about the function being called.
1664 NAMED is nonzero if this argument is a named parameter
1665 (otherwise it is an extra parameter matching an ellipsis).
1667 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1668 other arguments are passed on the stack. If (NAMED == 0) (which happens
1669 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1670 defined), say it is passed in the stack (function_prologue will
1671 indeed make it pass in the stack if necessary). */
1672 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1673 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1675 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1676 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1678 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1679 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1681 /* For AAPCS, padding should never be below the argument. For other ABIs,
1682 * mimic the default. */
1683 #define PAD_VARARGS_DOWN \
1684 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1686 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1687 for a call to a function whose data type is FNTYPE.
1688 For a library call, FNTYPE is 0.
1689 On the ARM, the offset starts at 0. */
1690 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1691 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1693 /* Update the data in CUM to advance over an argument
1694 of mode MODE and data type TYPE.
1695 (TYPE is null for libcalls where that information may not be available.) */
1696 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1698 if (arm_vector_mode_supported_p (MODE) \
1699 && (CUM).named_count > (CUM).nargs \
1700 && TARGET_IWMMXT_ABI) \
1701 (CUM).iwmmxt_nregs += 1; \
1703 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1705 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1706 argument with the specified mode and type. If it is not defined,
1707 `PARM_BOUNDARY' is used for all arguments. */
1708 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1709 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1710 ? DOUBLEWORD_ALIGNMENT \
1713 /* 1 if N is a possible register number for function argument passing.
1714 On the ARM, r0-r3 are used to pass args. */
1715 #define FUNCTION_ARG_REGNO_P(REGNO) \
1716 (IN_RANGE ((REGNO), 0, 3) \
1717 || (TARGET_IWMMXT_ABI \
1718 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1721 /* If your target environment doesn't prefix user functions with an
1722 underscore, you may wish to re-define this to prevent any conflicts. */
1723 #ifndef ARM_MCOUNT_NAME
1724 #define ARM_MCOUNT_NAME "*mcount"
1727 /* Call the function profiler with a given profile label. The Acorn
1728 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1729 On the ARM the full profile code will look like:
1738 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1739 will output the .text section.
1741 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1742 ``prof'' doesn't seem to mind about this!
1744 Note - this version of the code is designed to work in both ARM and
1746 #ifndef ARM_FUNCTION_PROFILER
1747 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1752 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1753 IP_REGNUM, LR_REGNUM); \
1754 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1755 fputc ('\n', STREAM); \
1756 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1757 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1758 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1762 #ifdef THUMB_FUNCTION_PROFILER
1763 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1765 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1767 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1769 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1770 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1773 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1774 the stack pointer does not matter. The value is tested only in
1775 functions that have frame pointers.
1776 No definition is equivalent to always zero.
1778 On the ARM, the function epilogue recovers the stack pointer from the
1780 #define EXIT_IGNORE_STACK 1
1782 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1784 /* Determine if the epilogue should be output as RTL.
1785 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1786 /* This is disabled for Thumb-2 because it will confuse the
1787 conditional insn counter. */
1788 #define USE_RETURN_INSN(ISCOND) \
1789 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1791 /* Definitions for register eliminations.
1793 This is an array of structures. Each structure initializes one pair
1794 of eliminable registers. The "from" register number is given first,
1795 followed by "to". Eliminations of the same "from" register are listed
1796 in order of preference.
1798 We have two registers that can be eliminated on the ARM. First, the
1799 arg pointer register can often be eliminated in favor of the stack
1800 pointer register. Secondly, the pseudo frame pointer register can always
1801 be eliminated; it is replaced with either the stack or the real frame
1802 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1803 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1805 #define ELIMINABLE_REGS \
1806 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1807 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1808 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1809 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1810 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1811 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1812 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1814 /* Given FROM and TO register numbers, say whether this elimination is
1815 allowed. Frame pointer elimination is automatically handled.
1817 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1818 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1819 pointer, we must eliminate FRAME_POINTER_REGNUM into
1820 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1821 ARG_POINTER_REGNUM. */
1822 #define CAN_ELIMINATE(FROM, TO) \
1823 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1824 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1825 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1826 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1829 /* Define the offset between two registers, one to be eliminated, and the
1830 other its replacement, at the start of a routine. */
1831 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1833 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1835 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1837 /* Special case handling of the location of arguments passed on the stack. */
1838 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1840 /* Initialize data used by insn expanders. This is called from insn_emit,
1841 once for every function before code is generated. */
1842 #define INIT_EXPANDERS arm_init_expanders ()
1844 /* Output assembler code for a block containing the constant parts
1845 of a trampoline, leaving space for the variable parts.
1847 On the ARM, (if r8 is the static chain regnum, and remembering that
1848 referencing pc adds an offset of 8) the trampoline looks like:
1851 .word static chain value
1852 .word function's address
1853 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1854 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1856 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1857 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1858 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1859 PC_REGNUM, PC_REGNUM); \
1860 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1861 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1864 /* The Thumb-2 trampoline is similar to the arm implementation.
1865 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1866 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1868 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1869 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1870 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1871 PC_REGNUM, PC_REGNUM); \
1872 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1873 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1876 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1878 ASM_OUTPUT_ALIGN(FILE, 2); \
1879 fprintf (FILE, "\t.code\t16\n"); \
1880 fprintf (FILE, ".Ltrampoline_start:\n"); \
1881 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1882 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1884 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1885 STATIC_CHAIN_REGNUM); \
1886 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1888 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1890 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1892 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1893 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1896 #define TRAMPOLINE_TEMPLATE(FILE) \
1898 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1899 else if (TARGET_THUMB2) \
1900 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1902 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1904 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1906 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1909 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1910 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1913 /* Length in units of the trampoline for entering a nested function. */
1914 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1916 /* Alignment required for a trampoline in bits. */
1917 #define TRAMPOLINE_ALIGNMENT 32
1920 /* Emit RTL insns to initialize the variable parts of a trampoline.
1921 FNADDR is an RTX for the address of the function's pure code.
1922 CXT is an RTX for the static chain value for the function. */
1923 #ifndef INITIALIZE_TRAMPOLINE
1924 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1926 emit_move_insn (gen_rtx_MEM (SImode, \
1927 plus_constant (TRAMP, \
1928 TARGET_32BIT ? 8 : 12)), \
1930 emit_move_insn (gen_rtx_MEM (SImode, \
1931 plus_constant (TRAMP, \
1932 TARGET_32BIT ? 12 : 16)), \
1934 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1935 LCT_NORMAL, VOIDmode, 2, TRAMP, Pmode, \
1936 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1941 /* Addressing modes, and classification of registers for them. */
1942 #define HAVE_POST_INCREMENT 1
1943 #define HAVE_PRE_INCREMENT TARGET_32BIT
1944 #define HAVE_POST_DECREMENT TARGET_32BIT
1945 #define HAVE_PRE_DECREMENT TARGET_32BIT
1946 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1947 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1948 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1949 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1951 /* Macros to check register numbers against specific register classes. */
1953 /* These assume that REGNO is a hard or pseudo reg number.
1954 They give nonzero only if REGNO is a hard reg of the suitable class
1955 or a pseudo reg currently allocated to a suitable hard reg.
1956 Since they use reg_renumber, they are safe only once reg_renumber
1957 has been allocated, which happens in local-alloc.c. */
1958 #define TEST_REGNO(R, TEST, VALUE) \
1959 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1961 /* Don't allow the pc to be used. */
1962 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1963 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1964 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1965 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1967 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1968 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1969 || (GET_MODE_SIZE (MODE) >= 4 \
1970 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1972 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1974 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1975 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1977 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1978 For Thumb, we can not use SP + reg, so reject SP. */
1979 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1980 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1982 /* For ARM code, we don't care about the mode, but for Thumb, the index
1983 must be suitable for use in a QImode load. */
1984 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1985 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1986 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1988 /* Maximum number of registers that can appear in a valid memory address.
1989 Shifts in addresses can't be by a register. */
1990 #define MAX_REGS_PER_ADDRESS 2
1992 /* Recognize any constant value that is a valid address. */
1993 /* XXX We can address any constant, eventually... */
1994 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1995 #define CONSTANT_ADDRESS_P(X) \
1996 (GET_CODE (X) == SYMBOL_REF \
1997 && (CONSTANT_POOL_ADDRESS_P (X) \
1998 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2000 /* True if SYMBOL + OFFSET constants must refer to something within
2001 SYMBOL's section. */
2002 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
2004 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
2005 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
2006 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
2009 /* Nonzero if the constant value X is a legitimate general operand.
2010 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2012 On the ARM, allow any integer (invalid ones are removed later by insn
2013 patterns), nice doubles and symbol_refs which refer to the function's
2016 When generating pic allow anything. */
2017 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2019 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2020 ( GET_CODE (X) == CONST_INT \
2021 || GET_CODE (X) == CONST_DOUBLE \
2022 || CONSTANT_ADDRESS_P (X) \
2025 #define LEGITIMATE_CONSTANT_P(X) \
2026 (!arm_cannot_force_const_mem (X) \
2027 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
2028 : THUMB_LEGITIMATE_CONSTANT_P (X)))
2030 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2031 #define SUBTARGET_NAME_ENCODING_LENGTHS
2034 /* This is a C fragment for the inside of a switch statement.
2035 Each case label should return the number of characters to
2036 be stripped from the start of a function's name, if that
2037 name starts with the indicated character. */
2038 #define ARM_NAME_ENCODING_LENGTHS \
2039 case '*': return 1; \
2040 SUBTARGET_NAME_ENCODING_LENGTHS
2042 /* This is how to output a reference to a user-level label named NAME.
2043 `assemble_name' uses this. */
2044 #undef ASM_OUTPUT_LABELREF
2045 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2046 arm_asm_output_labelref (FILE, NAME)
2048 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
2049 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2050 if (TARGET_THUMB2) \
2051 thumb2_asm_output_opcode (STREAM);
2053 /* The EABI specifies that constructors should go in .init_array.
2054 Other targets use .ctors for compatibility. */
2055 #ifndef ARM_EABI_CTORS_SECTION_OP
2056 #define ARM_EABI_CTORS_SECTION_OP \
2057 "\t.section\t.init_array,\"aw\",%init_array"
2059 #ifndef ARM_EABI_DTORS_SECTION_OP
2060 #define ARM_EABI_DTORS_SECTION_OP \
2061 "\t.section\t.fini_array,\"aw\",%fini_array"
2063 #define ARM_CTORS_SECTION_OP \
2064 "\t.section\t.ctors,\"aw\",%progbits"
2065 #define ARM_DTORS_SECTION_OP \
2066 "\t.section\t.dtors,\"aw\",%progbits"
2068 /* Define CTORS_SECTION_ASM_OP. */
2069 #undef CTORS_SECTION_ASM_OP
2070 #undef DTORS_SECTION_ASM_OP
2072 # define CTORS_SECTION_ASM_OP \
2073 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2074 # define DTORS_SECTION_ASM_OP \
2075 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2076 #else /* !defined (IN_LIBGCC2) */
2077 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2078 so we cannot use the definition above. */
2079 # ifdef __ARM_EABI__
2080 /* The .ctors section is not part of the EABI, so we do not define
2081 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2082 from trying to use it. We do define it when doing normal
2083 compilation, as .init_array can be used instead of .ctors. */
2084 /* There is no need to emit begin or end markers when using
2085 init_array; the dynamic linker will compute the size of the
2086 array itself based on special symbols created by the static
2087 linker. However, we do need to arrange to set up
2088 exception-handling here. */
2089 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2090 # define CTOR_LIST_END /* empty */
2091 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2092 # define DTOR_LIST_END /* empty */
2093 # else /* !defined (__ARM_EABI__) */
2094 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2095 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2096 # endif /* !defined (__ARM_EABI__) */
2097 #endif /* !defined (IN_LIBCC2) */
2099 /* True if the operating system can merge entities with vague linkage
2100 (e.g., symbols in COMDAT group) during dynamic linking. */
2101 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2102 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2105 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2107 #ifdef TARGET_UNWIND_INFO
2108 #define ARM_EABI_UNWIND_TABLES \
2109 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2111 #define ARM_EABI_UNWIND_TABLES 0
2114 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2115 and check its validity for a certain class.
2116 We have two alternate definitions for each of them.
2117 The usual definition accepts all pseudo regs; the other rejects
2118 them unless they have been allocated suitable hard regs.
2119 The symbol REG_OK_STRICT causes the latter definition to be used.
2120 Thumb-2 has the same restrictions as arm. */
2121 #ifndef REG_OK_STRICT
2123 #define ARM_REG_OK_FOR_BASE_P(X) \
2124 (REGNO (X) <= LAST_ARM_REGNUM \
2125 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2126 || REGNO (X) == FRAME_POINTER_REGNUM \
2127 || REGNO (X) == ARG_POINTER_REGNUM)
2129 #define ARM_REG_OK_FOR_INDEX_P(X) \
2130 ((REGNO (X) <= LAST_ARM_REGNUM \
2131 && REGNO (X) != STACK_POINTER_REGNUM) \
2132 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2133 || REGNO (X) == FRAME_POINTER_REGNUM \
2134 || REGNO (X) == ARG_POINTER_REGNUM)
2136 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2137 (REGNO (X) <= LAST_LO_REGNUM \
2138 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2139 || (GET_MODE_SIZE (MODE) >= 4 \
2140 && (REGNO (X) == STACK_POINTER_REGNUM \
2141 || (X) == hard_frame_pointer_rtx \
2142 || (X) == arg_pointer_rtx)))
2144 #define REG_STRICT_P 0
2146 #else /* REG_OK_STRICT */
2148 #define ARM_REG_OK_FOR_BASE_P(X) \
2149 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2151 #define ARM_REG_OK_FOR_INDEX_P(X) \
2152 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2154 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2155 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2157 #define REG_STRICT_P 1
2159 #endif /* REG_OK_STRICT */
2161 /* Now define some helpers in terms of the above. */
2163 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2165 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2166 : ARM_REG_OK_FOR_BASE_P (X))
2168 /* For 16-bit Thumb, a valid index register is anything that can be used in
2169 a byte load instruction. */
2170 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2171 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2173 /* Nonzero if X is a hard reg that can be used as an index
2174 or if it is a pseudo reg. On the Thumb, the stack pointer
2176 #define REG_OK_FOR_INDEX_P(X) \
2178 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2179 : ARM_REG_OK_FOR_INDEX_P (X))
2181 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2182 For Thumb, we can not use SP + reg, so reject SP. */
2183 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2184 REG_OK_FOR_INDEX_P (X)
2186 #define ARM_BASE_REGISTER_RTX_P(X) \
2187 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2189 #define ARM_INDEX_REGISTER_RTX_P(X) \
2190 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2192 /* Define this for compatibility reasons. */
2193 #define HANDLE_PRAGMA_PACK_PUSH_POP
2195 /* Specify the machine mode that this machine uses
2196 for the index in the tablejump instruction. */
2197 #define CASE_VECTOR_MODE Pmode
2199 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2201 && (optimize_size || flag_pic)))
2203 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2205 ? (min >= 0 && max < 512 \
2206 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2207 : min >= -256 && max < 256 \
2208 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2209 : min >= 0 && max < 8192 \
2210 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2211 : min >= -4096 && max < 4096 \
2212 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2214 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2215 : (max >= 0x200) ? HImode \
2218 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2219 unsigned is probably best, but may break some code. */
2220 #ifndef DEFAULT_SIGNED_CHAR
2221 #define DEFAULT_SIGNED_CHAR 0
2224 /* Max number of bytes we can move from memory to memory
2225 in one reasonably fast instruction. */
2229 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2231 /* Define if operations between registers always perform the operation
2232 on the full register even if a narrower mode is specified. */
2233 #define WORD_REGISTER_OPERATIONS
2235 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2236 will either zero-extend or sign-extend. The value of this macro should
2237 be the code that says which one of the two operations is implicitly
2238 done, UNKNOWN if none. */
2239 #define LOAD_EXTEND_OP(MODE) \
2240 (TARGET_THUMB ? ZERO_EXTEND : \
2241 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2242 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2244 /* Nonzero if access to memory by bytes is slow and undesirable. */
2245 #define SLOW_BYTE_ACCESS 0
2247 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2249 /* Immediate shift counts are truncated by the output routines (or was it
2250 the assembler?). Shift counts in a register are truncated by ARM. Note
2251 that the native compiler puts too large (> 32) immediate shift counts
2252 into a register and shifts by the register, letting the ARM decide what
2253 to do instead of doing that itself. */
2254 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2255 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2256 On the arm, Y in a register is used modulo 256 for the shift. Only for
2257 rotates is modulo 32 used. */
2258 /* #define SHIFT_COUNT_TRUNCATED 1 */
2260 /* All integers have the same format so truncation is easy. */
2261 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2263 /* Calling from registers is a massive pain. */
2264 #define NO_FUNCTION_CSE 1
2266 /* The machine modes of pointers and functions */
2267 #define Pmode SImode
2268 #define FUNCTION_MODE Pmode
2270 #define ARM_FRAME_RTX(X) \
2271 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2272 || (X) == arg_pointer_rtx)
2274 /* Moves to and from memory are quite expensive */
2275 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2276 (TARGET_32BIT ? 10 : \
2277 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2278 * (CLASS == LO_REGS ? 1 : 2)))
2280 /* Try to generate sequences that don't involve branches, we can then use
2281 conditional instructions */
2282 #define BRANCH_COST(speed_p, predictable_p) \
2283 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2285 /* Position Independent Code. */
2286 /* We decide which register to use based on the compilation options and
2287 the assembler in use; this is more general than the APCS restriction of
2288 using sb (r9) all the time. */
2289 extern unsigned arm_pic_register;
2291 /* The register number of the register used to address a table of static
2292 data addresses in memory. */
2293 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2295 /* We can't directly access anything that contains a symbol,
2296 nor can we indirect via the constant pool. One exception is
2297 UNSPEC_TLS, which is always PIC. */
2298 #define LEGITIMATE_PIC_OPERAND_P(X) \
2299 (!(symbol_mentioned_p (X) \
2300 || label_mentioned_p (X) \
2301 || (GET_CODE (X) == SYMBOL_REF \
2302 && CONSTANT_POOL_ADDRESS_P (X) \
2303 && (symbol_mentioned_p (get_pool_constant (X)) \
2304 || label_mentioned_p (get_pool_constant (X))))) \
2305 || tls_mentioned_p (X))
2307 /* We need to know when we are making a constant pool; this determines
2308 whether data needs to be in the GOT or can be referenced via a GOT
2310 extern int making_const_table;
2312 /* Handle pragmas for compatibility with Intel's compilers. */
2313 /* Also abuse this to register additional C specific EABI attributes. */
2314 #define REGISTER_TARGET_PRAGMAS() do { \
2315 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2316 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2317 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2318 arm_lang_object_attributes_init(); \
2321 /* Condition code information. */
2322 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2323 return the mode to be used for the comparison. */
2325 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2327 #define REVERSIBLE_CC_MODE(MODE) 1
2329 #define REVERSE_CONDITION(CODE,MODE) \
2330 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2331 ? reverse_condition_maybe_unordered (code) \
2332 : reverse_condition (code))
2334 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2337 if (GET_CODE (OP1) == CONST_INT \
2338 && ! (const_ok_for_arm (INTVAL (OP1)) \
2339 || (const_ok_for_arm (- INTVAL (OP1))))) \
2341 rtx const_op = OP1; \
2342 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2349 /* The arm5 clz instruction returns 32. */
2350 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2353 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2354 TARGET_THUMB2 ? "\t.thumb\n" : "")
2356 /* Output a push or a pop instruction (only used when profiling). */
2357 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2361 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2362 STACK_POINTER_REGNUM, REGNO); \
2364 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2368 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2372 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2373 STACK_POINTER_REGNUM, REGNO); \
2375 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2378 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2379 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2381 /* This is how to output a label which precedes a jumptable. Since
2382 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2383 #undef ASM_OUTPUT_CASE_LABEL
2384 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2387 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2388 ASM_OUTPUT_ALIGN (FILE, 2); \
2389 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2393 /* Make sure subsequent insns are aligned after a TBB. */
2394 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2397 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2398 ASM_OUTPUT_ALIGN (FILE, 1); \
2402 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2407 if (is_called_in_ARM_mode (DECL) \
2408 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2409 && cfun->is_thunk)) \
2410 fprintf (STREAM, "\t.code 32\n") ; \
2411 else if (TARGET_THUMB1) \
2412 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2414 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2416 if (TARGET_POKE_FUNCTION_NAME) \
2417 arm_poke_function_name (STREAM, (const char *) NAME); \
2421 /* For aliases of functions we use .thumb_set instead. */
2422 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2425 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2426 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2428 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2430 fprintf (FILE, "\t.thumb_set "); \
2431 assemble_name (FILE, LABEL1); \
2432 fprintf (FILE, ","); \
2433 assemble_name (FILE, LABEL2); \
2434 fprintf (FILE, "\n"); \
2437 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2441 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2442 /* To support -falign-* switches we need to use .p2align so
2443 that alignment directives in code sections will be padded
2444 with no-op instructions, rather than zeroes. */
2445 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2448 if ((MAX_SKIP) == 0) \
2449 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2451 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2452 (int) (LOG), (int) (MAX_SKIP)); \
2456 /* Add two bytes to the length of conditionally executed Thumb-2
2457 instructions for the IT instruction. */
2458 #define ADJUST_INSN_LENGTH(insn, length) \
2459 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2462 /* Only perform branch elimination (by making instructions conditional) if
2463 we're optimizing. For Thumb-2 check if any IT instructions need
2465 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2466 if (TARGET_ARM && optimize) \
2467 arm_final_prescan_insn (INSN); \
2468 else if (TARGET_THUMB2) \
2469 thumb2_final_prescan_insn (INSN); \
2470 else if (TARGET_THUMB1) \
2471 thumb1_final_prescan_insn (INSN)
2473 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2474 (CODE == '@' || CODE == '|' || CODE == '.' \
2475 || CODE == '(' || CODE == ')' || CODE == '#' \
2476 || (TARGET_32BIT && (CODE == '?')) \
2477 || (TARGET_THUMB2 && (CODE == '!')) \
2478 || (TARGET_THUMB && (CODE == '_')))
2480 /* Output an operand of an instruction. */
2481 #define PRINT_OPERAND(STREAM, X, CODE) \
2482 arm_print_operand (STREAM, X, CODE)
2484 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2485 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2486 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2487 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2488 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2489 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2492 /* Output the address of an operand. */
2493 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2495 int is_minus = GET_CODE (X) == MINUS; \
2497 if (GET_CODE (X) == REG) \
2498 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2499 else if (GET_CODE (X) == PLUS || is_minus) \
2501 rtx base = XEXP (X, 0); \
2502 rtx index = XEXP (X, 1); \
2503 HOST_WIDE_INT offset = 0; \
2504 if (GET_CODE (base) != REG \
2505 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2507 /* Ensure that BASE is a register. */ \
2508 /* (one of them must be). */ \
2509 /* Also ensure the SP is not used as in index register. */ \
2514 switch (GET_CODE (index)) \
2517 offset = INTVAL (index); \
2520 asm_fprintf (STREAM, "[%r, #%wd]", \
2521 REGNO (base), offset); \
2525 asm_fprintf (STREAM, "[%r, %s%r]", \
2526 REGNO (base), is_minus ? "-" : "", \
2536 asm_fprintf (STREAM, "[%r, %s%r", \
2537 REGNO (base), is_minus ? "-" : "", \
2538 REGNO (XEXP (index, 0))); \
2539 arm_print_operand (STREAM, index, 'S'); \
2540 fputs ("]", STREAM); \
2545 gcc_unreachable (); \
2548 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2549 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2551 extern enum machine_mode output_memory_reference_mode; \
2553 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2555 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2556 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2557 REGNO (XEXP (X, 0)), \
2558 GET_CODE (X) == PRE_DEC ? "-" : "", \
2559 GET_MODE_SIZE (output_memory_reference_mode)); \
2561 asm_fprintf (STREAM, "[%r], #%s%d", \
2562 REGNO (XEXP (X, 0)), \
2563 GET_CODE (X) == POST_DEC ? "-" : "", \
2564 GET_MODE_SIZE (output_memory_reference_mode)); \
2566 else if (GET_CODE (X) == PRE_MODIFY) \
2568 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2569 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2570 asm_fprintf (STREAM, "#%wd]!", \
2571 INTVAL (XEXP (XEXP (X, 1), 1))); \
2573 asm_fprintf (STREAM, "%r]!", \
2574 REGNO (XEXP (XEXP (X, 1), 1))); \
2576 else if (GET_CODE (X) == POST_MODIFY) \
2578 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2579 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2580 asm_fprintf (STREAM, "#%wd", \
2581 INTVAL (XEXP (XEXP (X, 1), 1))); \
2583 asm_fprintf (STREAM, "%r", \
2584 REGNO (XEXP (XEXP (X, 1), 1))); \
2586 else output_addr_const (STREAM, X); \
2589 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2591 if (GET_CODE (X) == REG) \
2592 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2593 else if (GET_CODE (X) == POST_INC) \
2594 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2595 else if (GET_CODE (X) == PLUS) \
2597 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2598 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2599 asm_fprintf (STREAM, "[%r, #%wd]", \
2600 REGNO (XEXP (X, 0)), \
2601 INTVAL (XEXP (X, 1))); \
2603 asm_fprintf (STREAM, "[%r, %r]", \
2604 REGNO (XEXP (X, 0)), \
2605 REGNO (XEXP (X, 1))); \
2608 output_addr_const (STREAM, X); \
2611 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2613 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2615 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2617 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2618 if (arm_output_addr_const_extra (file, x) == FALSE) \
2621 /* A C expression whose value is RTL representing the value of the return
2622 address for the frame COUNT steps up from the current frame. */
2624 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2625 arm_return_addr (COUNT, FRAME)
2627 /* Mask of the bits in the PC that contain the real return address
2628 when running in 26-bit mode. */
2629 #define RETURN_ADDR_MASK26 (0x03fffffc)
2631 /* Pick up the return address upon entry to a procedure. Used for
2632 dwarf2 unwind information. This also enables the table driven
2634 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2635 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2637 /* Used to mask out junk bits from the return address, such as
2638 processor state, interrupt status, condition codes and the like. */
2639 #define MASK_RETURN_ADDR \
2640 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2641 in 26 bit mode, the condition codes must be masked out of the \
2642 return address. This does not apply to ARM6 and later processors \
2643 when running in 32 bit mode. */ \
2644 ((arm_arch4 || TARGET_THUMB) \
2645 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2646 : arm_gen_return_addr_mask ())
2649 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2650 symbolic names defined here (which would require too much duplication).
2659 ARM_BUILTIN_WAVG2BR,
2660 ARM_BUILTIN_WAVG2HR,
2687 ARM_BUILTIN_TMOVMSKB,
2688 ARM_BUILTIN_TMOVMSKH,
2689 ARM_BUILTIN_TMOVMSKW,
2698 ARM_BUILTIN_WPACKHSS,
2699 ARM_BUILTIN_WPACKWSS,
2700 ARM_BUILTIN_WPACKDSS,
2701 ARM_BUILTIN_WPACKHUS,
2702 ARM_BUILTIN_WPACKWUS,
2703 ARM_BUILTIN_WPACKDUS,
2708 ARM_BUILTIN_WADDSSB,
2709 ARM_BUILTIN_WADDSSH,
2710 ARM_BUILTIN_WADDSSW,
2711 ARM_BUILTIN_WADDUSB,
2712 ARM_BUILTIN_WADDUSH,
2713 ARM_BUILTIN_WADDUSW,
2717 ARM_BUILTIN_WSUBSSB,
2718 ARM_BUILTIN_WSUBSSH,
2719 ARM_BUILTIN_WSUBSSW,
2720 ARM_BUILTIN_WSUBUSB,
2721 ARM_BUILTIN_WSUBUSH,
2722 ARM_BUILTIN_WSUBUSW,
2729 ARM_BUILTIN_WCMPEQB,
2730 ARM_BUILTIN_WCMPEQH,
2731 ARM_BUILTIN_WCMPEQW,
2732 ARM_BUILTIN_WCMPGTUB,
2733 ARM_BUILTIN_WCMPGTUH,
2734 ARM_BUILTIN_WCMPGTUW,
2735 ARM_BUILTIN_WCMPGTSB,
2736 ARM_BUILTIN_WCMPGTSH,
2737 ARM_BUILTIN_WCMPGTSW,
2739 ARM_BUILTIN_TEXTRMSB,
2740 ARM_BUILTIN_TEXTRMSH,
2741 ARM_BUILTIN_TEXTRMSW,
2742 ARM_BUILTIN_TEXTRMUB,
2743 ARM_BUILTIN_TEXTRMUH,
2744 ARM_BUILTIN_TEXTRMUW,
2794 ARM_BUILTIN_WUNPCKIHB,
2795 ARM_BUILTIN_WUNPCKIHH,
2796 ARM_BUILTIN_WUNPCKIHW,
2797 ARM_BUILTIN_WUNPCKILB,
2798 ARM_BUILTIN_WUNPCKILH,
2799 ARM_BUILTIN_WUNPCKILW,
2801 ARM_BUILTIN_WUNPCKEHSB,
2802 ARM_BUILTIN_WUNPCKEHSH,
2803 ARM_BUILTIN_WUNPCKEHSW,
2804 ARM_BUILTIN_WUNPCKEHUB,
2805 ARM_BUILTIN_WUNPCKEHUH,
2806 ARM_BUILTIN_WUNPCKEHUW,
2807 ARM_BUILTIN_WUNPCKELSB,
2808 ARM_BUILTIN_WUNPCKELSH,
2809 ARM_BUILTIN_WUNPCKELSW,
2810 ARM_BUILTIN_WUNPCKELUB,
2811 ARM_BUILTIN_WUNPCKELUH,
2812 ARM_BUILTIN_WUNPCKELUW,
2814 ARM_BUILTIN_THREAD_POINTER,
2816 ARM_BUILTIN_NEON_BASE,
2818 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2821 /* Do not emit .note.GNU-stack by default. */
2822 #ifndef NEED_INDICATE_EXEC_STACK
2823 #define NEED_INDICATE_EXEC_STACK 0
2826 #endif /* ! GCC_ARM_H */
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