1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
29 /* The architecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
41 builtin_define ("__thumb__"); \
43 builtin_define ("__thumb2__"); \
47 builtin_define ("__ARMEB__"); \
49 builtin_define ("__THUMBEB__"); \
50 if (TARGET_LITTLE_WORDS) \
51 builtin_define ("__ARMWEL__"); \
55 builtin_define ("__ARMEL__"); \
57 builtin_define ("__THUMBEL__"); \
60 if (TARGET_SOFT_FLOAT) \
61 builtin_define ("__SOFTFP__"); \
64 builtin_define ("__VFP_FP__"); \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (arm_cpp_interwork) \
69 builtin_define ("__THUMB_INTERWORK__"); \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
74 builtin_define (arm_arch_name); \
75 if (arm_arch_cirrus) \
76 builtin_define ("__MAVERICK__"); \
77 if (arm_arch_xscale) \
78 builtin_define ("__XSCALE__"); \
79 if (arm_arch_iwmmxt) \
80 builtin_define ("__IWMMXT__"); \
81 if (TARGET_AAPCS_BASED) \
82 builtin_define ("__ARM_EABI__"); \
85 /* The various ARM cores. */
88 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
90 #include "arm-cores.def"
92 /* Used to indicate that no processor has been specified. */
98 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
100 #include "arm-cores.def"
105 /* The processor for which instructions should be scheduled. */
106 extern enum processor_type arm_tune;
108 typedef enum arm_cond_code
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
115 extern arm_cc arm_current_cc;
117 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
119 extern int arm_target_label;
120 extern int arm_ccfsm_state;
121 extern GTY(()) rtx arm_target_insn;
122 /* Define the information needed to generate branch insns. This is
123 stored from the compare operation. */
124 extern GTY(()) rtx arm_compare_op0;
125 extern GTY(()) rtx arm_compare_op1;
126 /* The label of the current constant pool. */
127 extern rtx pool_vector_label;
128 /* Set to 1 when a return insn is output, this means that the epilogue
130 extern int return_used_this_function;
131 /* Used to produce AOF syntax assembler. */
132 extern GTY(()) rtx aof_pic_label;
134 /* Just in case configure has failed to define anything. */
135 #ifndef TARGET_CPU_DEFAULT
136 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
141 #define CPP_SPEC "%(subtarget_cpp_spec) \
142 %{msoft-float:%{mhard-float: \
143 %e-msoft-float and -mhard_float may not be used together}} \
144 %{mbig-endian:%{mlittle-endian: \
145 %e-mbig-endian and -mlittle-endian may not be used together}}"
151 /* This macro defines names of additional specifications to put in the specs
152 that can be used in various specifications like CC1_SPEC. Its definition
153 is an initializer with a subgrouping for each command option.
155 Each subgrouping contains a string constant, that defines the
156 specification name, and a string constant that used by the GCC driver
159 Do not define this macro if it does not need to do anything. */
160 #define EXTRA_SPECS \
161 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
162 SUBTARGET_EXTRA_SPECS
164 #ifndef SUBTARGET_EXTRA_SPECS
165 #define SUBTARGET_EXTRA_SPECS
168 #ifndef SUBTARGET_CPP_SPEC
169 #define SUBTARGET_CPP_SPEC ""
172 /* Run-time Target Specification. */
173 #ifndef TARGET_VERSION
174 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
177 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point instructions. */
179 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
180 /* Use hardware floating point calling convention. */
181 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
182 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
183 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
184 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
185 #define TARGET_IWMMXT (arm_arch_iwmmxt)
186 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
187 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
188 #define TARGET_ARM (! TARGET_THUMB)
189 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
190 #define TARGET_BACKTRACE (leaf_function_p () \
191 ? TARGET_TPCS_LEAF_FRAME \
193 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
194 #define TARGET_AAPCS_BASED \
195 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
197 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
198 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
200 /* Only 16-bit thumb code. */
201 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
202 /* Arm or Thumb-2 32-bit code. */
203 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
204 /* 32-bit Thumb-2 code. */
205 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
207 /* "DSP" multiply instructions, eg. SMULxy. */
208 #define TARGET_DSP_MULTIPLY \
209 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
210 /* Integer SIMD instructions, and extend-accumulate instructions. */
211 #define TARGET_INT_SIMD \
212 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
214 /* We could use unified syntax for arm mode, but for now we just use it
216 #define TARGET_UNIFIED_ASM TARGET_THUMB2
219 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
220 then TARGET_AAPCS_BASED must be true -- but the converse does not
221 hold. TARGET_BPABI implies the use of the BPABI runtime library,
222 etc., in addition to just the AAPCS calling conventions. */
224 #define TARGET_BPABI false
227 /* Support for a compile-time default CPU, et cetera. The rules are:
228 --with-arch is ignored if -march or -mcpu are specified.
229 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
231 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
233 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
235 --with-fpu is ignored if -mfpu is specified.
236 --with-abi is ignored is -mabi is specified. */
237 #define OPTION_DEFAULT_SPECS \
238 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
239 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
240 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
242 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
243 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
244 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
245 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
247 /* Which floating point model to use. */
250 ARM_FP_MODEL_UNKNOWN,
251 /* FPA model (Hardware or software). */
253 /* Cirrus Maverick floating point model. */
254 ARM_FP_MODEL_MAVERICK,
255 /* VFP floating point model. */
259 extern enum arm_fp_model arm_fp_model;
261 /* Which floating point hardware is available. Also update
262 fp_model_for_fpu in arm.c when adding entries to this list. */
265 /* No FP hardware. */
267 /* Full FPA support. */
269 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
271 /* Emulated FPA hardware, Issue 3 emulator. */
273 /* Cirrus Maverick floating point co-processor. */
279 /* Recast the floating point class to be the floating point attribute. */
280 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
282 /* What type of floating point to tune for */
283 extern enum fputype arm_fpu_tune;
285 /* What type of floating point instructions are available */
286 extern enum fputype arm_fpu_arch;
291 ARM_FLOAT_ABI_SOFTFP,
295 extern enum float_abi_type arm_float_abi;
297 #ifndef TARGET_DEFAULT_FLOAT_ABI
298 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
301 /* Which ABI to use. */
311 extern enum arm_abi_type arm_abi;
313 #ifndef ARM_DEFAULT_ABI
314 #define ARM_DEFAULT_ABI ARM_ABI_APCS
317 /* Which thread pointer access sequence to use. */
324 extern enum arm_tp_type target_thread_pointer;
326 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
327 extern int arm_arch3m;
329 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
330 extern int arm_arch4;
332 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
333 extern int arm_arch4t;
335 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
336 extern int arm_arch5;
338 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
339 extern int arm_arch5e;
341 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
342 extern int arm_arch6;
344 /* Nonzero if instructions not present in the 'M' profile can be used. */
345 extern int arm_arch_notm;
347 /* Nonzero if this chip can benefit from load scheduling. */
348 extern int arm_ld_sched;
350 /* Nonzero if generating thumb code. */
351 extern int thumb_code;
353 /* Nonzero if this chip is a StrongARM. */
354 extern int arm_tune_strongarm;
356 /* Nonzero if this chip is a Cirrus variant. */
357 extern int arm_arch_cirrus;
359 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
360 extern int arm_arch_iwmmxt;
362 /* Nonzero if this chip is an XScale. */
363 extern int arm_arch_xscale;
365 /* Nonzero if tuning for XScale. */
366 extern int arm_tune_xscale;
368 /* Nonzero if tuning for stores via the write buffer. */
369 extern int arm_tune_wbuf;
371 /* Nonzero if we should define __THUMB_INTERWORK__ in the
373 XXX This is a bit of a hack, it's intended to help work around
374 problems in GLD which doesn't understand that armv5t code is
375 interworking clean. */
376 extern int arm_cpp_interwork;
378 /* Nonzero if chip supports Thumb 2. */
379 extern int arm_arch_thumb2;
381 /* Nonzero if chip supports integer division instruction. */
382 extern int arm_arch_hwdiv;
384 #ifndef TARGET_DEFAULT
385 #define TARGET_DEFAULT (MASK_APCS_FRAME)
388 /* The frame pointer register used in gcc has nothing to do with debugging;
389 that is controlled by the APCS-FRAME option. */
390 #define CAN_DEBUG_WITHOUT_FP
392 #define OVERRIDE_OPTIONS arm_override_options ()
394 /* Nonzero if PIC code requires explicit qualifiers to generate
395 PLT and GOT relocs rather than the assembler doing so implicitly.
396 Subtargets can override these if required. */
397 #ifndef NEED_GOT_RELOC
398 #define NEED_GOT_RELOC 0
400 #ifndef NEED_PLT_RELOC
401 #define NEED_PLT_RELOC 0
404 /* Nonzero if we need to refer to the GOT with a PC-relative
405 offset. In other words, generate
407 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
411 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
413 The default is true, which matches NetBSD. Subtargets can
414 override this if required. */
419 /* Target machine storage Layout. */
422 /* Define this macro if it is advisable to hold scalars in registers
423 in a wider mode than that declared by the program. In such cases,
424 the value is constrained to be within the bounds of the declared
425 type, but kept valid in the wider mode. The signedness of the
426 extension may differ from that of the type. */
428 /* It is far faster to zero extend chars than to sign extend them */
430 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
431 if (GET_MODE_CLASS (MODE) == MODE_INT \
432 && GET_MODE_SIZE (MODE) < 4) \
434 if (MODE == QImode) \
436 else if (MODE == HImode) \
441 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
442 if ((GET_MODE_CLASS (MODE) == MODE_INT \
443 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
444 && GET_MODE_SIZE (MODE) < 4) \
447 /* Define this if most significant bit is lowest numbered
448 in instructions that operate on numbered bit-fields. */
449 #define BITS_BIG_ENDIAN 0
451 /* Define this if most significant byte of a word is the lowest numbered.
452 Most ARM processors are run in little endian mode, so that is the default.
453 If you want to have it run-time selectable, change the definition in a
454 cover file to be TARGET_BIG_ENDIAN. */
455 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
457 /* Define this if most significant word of a multiword number is the lowest
459 This is always false, even when in big-endian mode. */
460 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
462 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
463 on processor pre-defineds when compiling libgcc2.c. */
464 #if defined(__ARMEB__) && !defined(__ARMWEL__)
465 #define LIBGCC2_WORDS_BIG_ENDIAN 1
467 #define LIBGCC2_WORDS_BIG_ENDIAN 0
470 /* Define this if most significant word of doubles is the lowest numbered.
471 The rules are different based on whether or not we use FPA-format,
472 VFP-format or some other floating point co-processor's format doubles. */
473 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
475 #define UNITS_PER_WORD 4
477 /* True if natural alignment is used for doubleword types. */
478 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
480 #define DOUBLEWORD_ALIGNMENT 64
482 #define PARM_BOUNDARY 32
484 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
486 #define PREFERRED_STACK_BOUNDARY \
487 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
489 #define FUNCTION_BOUNDARY 32
491 /* The lowest bit is used to indicate Thumb-mode functions, so the
492 vbit must go into the delta field of pointers to member
494 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
496 #define EMPTY_FIELD_BOUNDARY 32
498 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
500 /* XXX Blah -- this macro is used directly by libobjc. Since it
501 supports no vector modes, cut out the complexity and fall back
502 on BIGGEST_FIELD_ALIGNMENT. */
503 #ifdef IN_TARGET_LIBS
504 #define BIGGEST_FIELD_ALIGNMENT 64
507 /* Make strings word-aligned so strcpy from constants will be faster. */
508 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
510 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
511 ((TREE_CODE (EXP) == STRING_CST \
513 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
514 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
516 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
517 value set in previous versions of this toolchain was 8, which produces more
518 compact structures. The command line option -mstructure_size_boundary=<n>
519 can be used to change this value. For compatibility with the ARM SDK
520 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
521 0020D) page 2-20 says "Structures are aligned on word boundaries".
522 The AAPCS specifies a value of 8. */
523 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
524 extern int arm_structure_size_boundary;
526 /* This is the value used to initialize arm_structure_size_boundary. If a
527 particular arm target wants to change the default value it should change
528 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
529 for an example of this. */
530 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
531 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
534 /* Nonzero if move instructions will actually fail to work
535 when given unaligned data. */
536 #define STRICT_ALIGNMENT 1
538 /* wchar_t is unsigned under the AAPCS. */
540 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
542 #define WCHAR_TYPE_SIZE BITS_PER_WORD
546 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
550 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
553 /* AAPCS requires that structure alignment is affected by bitfields. */
554 #ifndef PCC_BITFIELD_TYPE_MATTERS
555 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
559 /* Standard register usage. */
561 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
562 (S - saved over call).
564 r0 * argument word/integer result
567 r4-r8 S register variable
568 r9 S (rfp) register variable (real frame pointer)
570 r10 F S (sl) stack limit (used by -mapcs-stack-check)
571 r11 F S (fp) argument pointer
572 r12 (ip) temp workspace
573 r13 F S (sp) lower end of current stack frame
574 r14 (lr) link address/workspace
575 r15 F (pc) program counter
577 f0 floating point result
578 f1-f3 floating point scratch
580 f4-f7 S floating point variable
582 cc This is NOT a real register, but is used internally
583 to represent things that use or set the condition
585 sfp This isn't either. It is used during rtl generation
586 since the offset between the frame pointer and the
587 auto's isn't known until after register allocation.
588 afp Nor this, we only need this because of non-local
589 goto. Without it fp appears to be used and the
590 elimination code won't get rid of sfp. It tracks
591 fp exactly at all times.
593 *: See CONDITIONAL_REGISTER_USAGE */
596 mvf0 Cirrus floating point result
597 mvf1-mvf3 Cirrus floating point scratch
598 mvf4-mvf15 S Cirrus floating point variable. */
600 /* s0-s15 VFP scratch (aka d0-d7).
601 s16-s31 S VFP variable (aka d8-d15).
602 vfpcc Not a real register. Represents the VFP condition
605 /* The stack backtrace structure is as follows:
606 fp points to here: | save code pointer | [fp]
607 | return link value | [fp, #-4]
608 | return sp value | [fp, #-8]
609 | return fp value | [fp, #-12]
610 [| saved r10 value |]
621 [| saved f7 value |] three words
622 [| saved f6 value |] three words
623 [| saved f5 value |] three words
624 [| saved f4 value |] three words
625 r0-r3 are not normally saved in a C function. */
627 /* 1 for registers that have pervasive standard uses
628 and are not available for the register allocator. */
629 #define FIXED_REGISTERS \
647 /* 1 for registers not available across function calls.
648 These must include the FIXED_REGISTERS and also any
649 registers that can be used without being saved.
650 The latter must include the registers where values are returned
651 and the register where structure-value addresses are passed.
652 Aside from that, you can include as many other registers as you like.
653 The CC is not preserved over function calls on the ARM 6, so it is
654 easier to assume this for all. SFP is preserved, since FP is. */
655 #define CALL_USED_REGISTERS \
673 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
674 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
677 #define CONDITIONAL_REGISTER_USAGE \
681 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
683 for (regno = FIRST_FPA_REGNUM; \
684 regno <= LAST_FPA_REGNUM; ++regno) \
685 fixed_regs[regno] = call_used_regs[regno] = 1; \
688 if (TARGET_THUMB && optimize_size) \
690 /* When optimizing for size, it's better not to use \
691 the HI regs, because of the overhead of stacking \
693 /* ??? Is this still true for thumb2? */ \
694 for (regno = FIRST_HI_REGNUM; \
695 regno <= LAST_HI_REGNUM; ++regno) \
696 fixed_regs[regno] = call_used_regs[regno] = 1; \
699 /* The link register can be clobbered by any branch insn, \
700 but we have no way to track that at present, so mark \
701 it as unavailable. */ \
703 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
705 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
707 if (TARGET_MAVERICK) \
709 for (regno = FIRST_FPA_REGNUM; \
710 regno <= LAST_FPA_REGNUM; ++ regno) \
711 fixed_regs[regno] = call_used_regs[regno] = 1; \
712 for (regno = FIRST_CIRRUS_FP_REGNUM; \
713 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
715 fixed_regs[regno] = 0; \
716 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
721 for (regno = FIRST_VFP_REGNUM; \
722 regno <= LAST_VFP_REGNUM; ++ regno) \
724 fixed_regs[regno] = 0; \
725 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
730 if (TARGET_REALLY_IWMMXT) \
732 regno = FIRST_IWMMXT_GR_REGNUM; \
733 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
734 and wCG1 as call-preserved registers. The 2002/11/21 \
735 revision changed this so that all wCG registers are \
736 scratch registers. */ \
737 for (regno = FIRST_IWMMXT_GR_REGNUM; \
738 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
739 fixed_regs[regno] = 0; \
740 /* The XScale ABI has wR0 - wR9 as scratch registers, \
741 the rest as call-preserved registers. */ \
742 for (regno = FIRST_IWMMXT_REGNUM; \
743 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
745 fixed_regs[regno] = 0; \
746 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
750 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
752 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
753 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
755 else if (TARGET_APCS_STACK) \
757 fixed_regs[10] = 1; \
758 call_used_regs[10] = 1; \
760 /* -mcaller-super-interworking reserves r11 for calls to \
761 _interwork_r11_call_via_rN(). Making the register global \
762 is an easy way of ensuring that it remains valid for all \
764 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
765 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
767 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
768 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
769 if (TARGET_CALLER_INTERWORKING) \
770 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
772 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
775 /* These are a couple of extensions to the formats accepted
777 %@ prints out ASM_COMMENT_START
778 %r prints out REGISTER_PREFIX reg_names[arg] */
779 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
781 fputs (ASM_COMMENT_START, FILE); \
785 fputs (REGISTER_PREFIX, FILE); \
786 fputs (reg_names [va_arg (ARGS, int)], FILE); \
789 /* Round X up to the nearest word. */
790 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
792 /* Convert fron bytes to ints. */
793 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
795 /* The number of (integer) registers required to hold a quantity of type MODE.
796 Also used for VFP registers. */
797 #define ARM_NUM_REGS(MODE) \
798 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
800 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
801 #define ARM_NUM_REGS2(MODE, TYPE) \
802 ARM_NUM_INTS ((MODE) == BLKmode ? \
803 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
805 /* The number of (integer) argument register available. */
806 #define NUM_ARG_REGS 4
808 /* Return the register number of the N'th (integer) argument. */
809 #define ARG_REGISTER(N) (N - 1)
811 /* Specify the registers used for certain standard purposes.
812 The values of these macros are register numbers. */
814 /* The number of the last argument register. */
815 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
817 /* The numbers of the Thumb register ranges. */
818 #define FIRST_LO_REGNUM 0
819 #define LAST_LO_REGNUM 7
820 #define FIRST_HI_REGNUM 8
821 #define LAST_HI_REGNUM 11
823 #ifndef TARGET_UNWIND_INFO
824 /* We use sjlj exceptions for backwards compatibility. */
825 #define MUST_USE_SJLJ_EXCEPTIONS 1
828 /* We can generate DWARF2 Unwind info, even though we don't use it. */
829 #define DWARF2_UNWIND_INFO 1
831 /* Use r0 and r1 to pass exception handling information. */
832 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
834 /* The register that holds the return address in exception handlers. */
835 #define ARM_EH_STACKADJ_REGNUM 2
836 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
838 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
839 as an invisible last argument (possible since varargs don't exist in
840 Pascal), so the following is not true. */
841 #define STATIC_CHAIN_REGNUM 12
843 /* Define this to be where the real frame pointer is if it is not possible to
844 work out the offset between the frame pointer and the automatic variables
845 until after register allocation has taken place. FRAME_POINTER_REGNUM
846 should point to a special register that we will make sure is eliminated.
848 For the Thumb we have another problem. The TPCS defines the frame pointer
849 as r11, and GCC believes that it is always possible to use the frame pointer
850 as base register for addressing purposes. (See comments in
851 find_reloads_address()). But - the Thumb does not allow high registers,
852 including r11, to be used as base address registers. Hence our problem.
854 The solution used here, and in the old thumb port is to use r7 instead of
855 r11 as the hard frame pointer and to have special code to generate
856 backtrace structures on the stack (if required to do so via a command line
857 option) using r11. This is the only 'user visible' use of r11 as a frame
859 #define ARM_HARD_FRAME_POINTER_REGNUM 11
860 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
862 #define HARD_FRAME_POINTER_REGNUM \
864 ? ARM_HARD_FRAME_POINTER_REGNUM \
865 : THUMB_HARD_FRAME_POINTER_REGNUM)
867 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
869 /* Register to use for pushing function arguments. */
870 #define STACK_POINTER_REGNUM SP_REGNUM
872 /* ARM floating pointer registers. */
873 #define FIRST_FPA_REGNUM 16
874 #define LAST_FPA_REGNUM 23
875 #define IS_FPA_REGNUM(REGNUM) \
876 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
878 #define FIRST_IWMMXT_GR_REGNUM 43
879 #define LAST_IWMMXT_GR_REGNUM 46
880 #define FIRST_IWMMXT_REGNUM 47
881 #define LAST_IWMMXT_REGNUM 62
882 #define IS_IWMMXT_REGNUM(REGNUM) \
883 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
884 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
885 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
887 /* Base register for access to local variables of the function. */
888 #define FRAME_POINTER_REGNUM 25
890 /* Base register for access to arguments of the function. */
891 #define ARG_POINTER_REGNUM 26
893 #define FIRST_CIRRUS_FP_REGNUM 27
894 #define LAST_CIRRUS_FP_REGNUM 42
895 #define IS_CIRRUS_REGNUM(REGNUM) \
896 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
898 #define FIRST_VFP_REGNUM 63
899 #define LAST_VFP_REGNUM 94
900 #define IS_VFP_REGNUM(REGNUM) \
901 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
903 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
904 /* + 16 Cirrus registers take us up to 43. */
905 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
906 /* VFP adds 32 + 1 more. */
907 #define FIRST_PSEUDO_REGISTER 96
909 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
911 /* Value should be nonzero if functions must have frame pointers.
912 Zero means the frame pointer need not be set up (and parms may be accessed
913 via the stack pointer) in functions that seem suitable.
914 If we have to have a frame pointer we might as well make use of it.
915 APCS says that the frame pointer does not need to be pushed in leaf
916 functions, or simple tail call functions. */
918 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
919 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
922 #define FRAME_POINTER_REQUIRED \
923 (current_function_has_nonlocal_label \
924 || SUBTARGET_FRAME_POINTER_REQUIRED \
925 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
927 /* Return number of consecutive hard regs needed starting at reg REGNO
928 to hold something of mode MODE.
929 This is ordinarily the length in words of a value of mode MODE
930 but can be less for certain modes in special long registers.
932 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
934 #define HARD_REGNO_NREGS(REGNO, MODE) \
936 && REGNO >= FIRST_FPA_REGNUM \
937 && REGNO != FRAME_POINTER_REGNUM \
938 && REGNO != ARG_POINTER_REGNUM) \
939 && !IS_VFP_REGNUM (REGNO) \
940 ? 1 : ARM_NUM_REGS (MODE))
942 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
943 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
944 arm_hard_regno_mode_ok ((REGNO), (MODE))
946 /* Value is 1 if it is a good idea to tie two pseudo registers
947 when one has mode MODE1 and one has mode MODE2.
948 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
949 for any hard reg, then this must be 0 for correct output. */
950 #define MODES_TIEABLE_P(MODE1, MODE2) \
951 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
953 #define VALID_IWMMXT_REG_MODE(MODE) \
954 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
956 /* The order in which register should be allocated. It is good to use ip
957 since no saving is required (though calls clobber it) and it never contains
958 function parameters. It is quite good to use lr since other calls may
959 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
960 least likely to contain a function parameter; in addition results are
963 #define REG_ALLOC_ORDER \
965 3, 2, 1, 0, 12, 14, 4, 5, \
966 6, 7, 8, 10, 9, 11, 13, 15, \
967 16, 17, 18, 19, 20, 21, 22, 23, \
968 27, 28, 29, 30, 31, 32, 33, 34, \
969 35, 36, 37, 38, 39, 40, 41, 42, \
970 43, 44, 45, 46, 47, 48, 49, 50, \
971 51, 52, 53, 54, 55, 56, 57, 58, \
974 78, 77, 76, 75, 74, 73, 72, 71, \
975 70, 69, 68, 67, 66, 65, 64, 63, \
976 79, 80, 81, 82, 83, 84, 85, 86, \
977 87, 88, 89, 90, 91, 92, 93, 94, \
981 /* Interrupt functions can only use registers that have already been
982 saved by the prologue, even if they would normally be
984 #define HARD_REGNO_RENAME_OK(SRC, DST) \
985 (! IS_INTERRUPT (cfun->machine->func_type) || \
988 /* Register and constant classes. */
990 /* Register classes: used to be simple, just all ARM regs or all FPA regs
991 Now that the Thumb is involved it has become more complicated. */
1011 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1013 /* Give names of register classes as strings for dump file. */
1014 #define REG_CLASS_NAMES \
1032 /* Define which registers fit in which classes.
1033 This is an initializer for a vector of HARD_REG_SET
1034 of length N_REG_CLASSES. */
1035 #define REG_CLASS_CONTENTS \
1037 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1038 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1039 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1040 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1041 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1042 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1043 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1044 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1045 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1046 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1047 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1048 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1049 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1050 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1053 /* The same information, inverted:
1054 Return the class number of the smallest class containing
1055 reg number REGNO. This could be a conditional expression
1056 or could index an array. */
1057 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1059 /* FPA registers can't do subreg as all values are reformatted to internal
1060 precision. VFP registers may only be accessed in the mode they
1062 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1063 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1064 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1065 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1068 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1069 using r0-r4 for function arguments, r7 for the stack frame and don't
1070 have enough left over to do doubleword arithmetic. */
1071 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1072 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1073 || (CLASS) == CC_REG)
1075 /* The class value for index registers, and the one for base regs. */
1076 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1077 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1079 /* For the Thumb the high registers cannot be used as base registers
1080 when addressing quantities in QI or HI mode; if we don't know the
1081 mode, then we must be conservative. */
1082 #define MODE_BASE_REG_CLASS(MODE) \
1083 (TARGET_32BIT ? GENERAL_REGS : \
1084 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1086 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1087 instead of BASE_REGS. */
1088 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1090 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1091 registers explicitly used in the rtl to be used as spill registers
1092 but prevents the compiler from extending the lifetime of these
1094 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1096 /* Given an rtx X being reloaded into a reg required to be
1097 in class CLASS, return the class of reg to actually use.
1098 In general this is just CLASS, but for the Thumb core registers and
1099 immediate constants we prefer a LO_REGS class or a subset. */
1100 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1101 (TARGET_ARM ? (CLASS) : \
1102 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1103 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1105 /* Must leave BASE_REGS reloads alone */
1106 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1107 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1108 ? ((true_regnum (X) == -1 ? LO_REGS \
1109 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1113 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1114 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1115 ? ((true_regnum (X) == -1 ? LO_REGS \
1116 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1120 /* Return the register class of a scratch register needed to copy IN into
1121 or out of a register in CLASS in MODE. If it can be done directly,
1122 NO_REGS is returned. */
1123 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1124 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1125 ((TARGET_VFP && TARGET_HARD_FLOAT \
1126 && (CLASS) == VFP_REGS) \
1127 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1128 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1129 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1131 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1132 ? GENERAL_REGS : NO_REGS) \
1133 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1135 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1136 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1137 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1138 ((TARGET_VFP && TARGET_HARD_FLOAT \
1139 && (CLASS) == VFP_REGS) \
1140 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1141 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1142 coproc_secondary_reload_class (MODE, X, TRUE) : \
1143 /* Cannot load constants into Cirrus registers. */ \
1144 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1145 && (CLASS) == CIRRUS_REGS \
1146 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1149 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1150 && CONSTANT_P (X)) \
1152 (((MODE) == HImode && ! arm_arch4 \
1153 && (GET_CODE (X) == MEM \
1154 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1155 && true_regnum (X) == -1))) \
1156 ? GENERAL_REGS : NO_REGS) \
1157 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1159 /* Try a machine-dependent way of reloading an illegitimate address
1160 operand. If we find one, push the reload and jump to WIN. This
1161 macro is used in only one place: `find_reloads_address' in reload.c.
1163 For the ARM, we wish to handle large displacements off a base
1164 register by splitting the addend across a MOV and the mem insn.
1165 This can cut the number of reloads needed. */
1166 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1169 if (GET_CODE (X) == PLUS \
1170 && GET_CODE (XEXP (X, 0)) == REG \
1171 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1172 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1173 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1175 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1176 HOST_WIDE_INT low, high; \
1178 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1179 low = ((val & 0xf) ^ 0x8) - 0x8; \
1180 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1181 /* Need to be careful, -256 is not a valid offset. */ \
1182 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1183 else if (MODE == SImode \
1184 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1185 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1186 /* Need to be careful, -4096 is not a valid offset. */ \
1187 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1188 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1189 /* Need to be careful, -256 is not a valid offset. */ \
1190 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1191 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1192 && TARGET_HARD_FLOAT && TARGET_FPA) \
1193 /* Need to be careful, -1024 is not a valid offset. */ \
1194 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1198 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1199 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1200 - (unsigned HOST_WIDE_INT) 0x80000000); \
1201 /* Check for overflow or zero */ \
1202 if (low == 0 || high == 0 || (high + low != val)) \
1205 /* Reload the high part into a base reg; leave the low part \
1207 X = gen_rtx_PLUS (GET_MODE (X), \
1208 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1211 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1212 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1213 VOIDmode, 0, 0, OPNUM, TYPE); \
1219 /* XXX If an HImode FP+large_offset address is converted to an HImode
1220 SP+large_offset address, then reload won't know how to fix it. It sees
1221 only that SP isn't valid for HImode, and so reloads the SP into an index
1222 register, but the resulting address is still invalid because the offset
1223 is too big. We fix it here instead by reloading the entire address. */
1224 /* We could probably achieve better results by defining PROMOTE_MODE to help
1225 cope with the variances between the Thumb's signed and unsigned byte and
1226 halfword load instructions. */
1227 /* ??? This should be safe for thumb2, but we may be able to do better. */
1228 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1230 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1238 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1240 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1242 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1244 /* Return the maximum number of consecutive registers
1245 needed to represent mode MODE in a register of class CLASS.
1246 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1247 #define CLASS_MAX_NREGS(CLASS, MODE) \
1248 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1250 /* If defined, gives a class of registers that cannot be used as the
1251 operand of a SUBREG that changes the mode of the object illegally. */
1253 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1254 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1256 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1257 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1258 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1259 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1260 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1261 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1262 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1263 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1264 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1267 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1269 /* Stack layout; function entry, exit and calling. */
1271 /* Define this if pushing a word on the stack
1272 makes the stack pointer a smaller address. */
1273 #define STACK_GROWS_DOWNWARD 1
1275 /* Define this to nonzero if the nominal address of the stack frame
1276 is at the high-address end of the local variables;
1277 that is, each additional local variable allocated
1278 goes at a more negative offset in the frame. */
1279 #define FRAME_GROWS_DOWNWARD 1
1281 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1282 When present, it is one word in size, and sits at the top of the frame,
1283 between the soft frame pointer and either r7 or r11.
1285 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1286 and only then if some outgoing arguments are passed on the stack. It would
1287 be tempting to also check whether the stack arguments are passed by indirect
1288 calls, but there seems to be no reason in principle why a post-reload pass
1289 couldn't convert a direct call into an indirect one. */
1290 #define CALLER_INTERWORKING_SLOT_SIZE \
1291 (TARGET_CALLER_INTERWORKING \
1292 && current_function_outgoing_args_size != 0 \
1293 ? UNITS_PER_WORD : 0)
1295 /* Offset within stack frame to start allocating local variables at.
1296 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1297 first local allocated. Otherwise, it is the offset to the BEGINNING
1298 of the first local allocated. */
1299 #define STARTING_FRAME_OFFSET 0
1301 /* If we generate an insn to push BYTES bytes,
1302 this says how many the stack pointer really advances by. */
1303 /* The push insns do not do this rounding implicitly.
1304 So don't define this. */
1305 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1307 /* Define this if the maximum size of all the outgoing args is to be
1308 accumulated and pushed during the prologue. The amount can be
1309 found in the variable current_function_outgoing_args_size. */
1310 #define ACCUMULATE_OUTGOING_ARGS 1
1312 /* Offset of first parameter from the argument pointer register value. */
1313 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1315 /* Value is the number of byte of arguments automatically
1316 popped when returning from a subroutine call.
1317 FUNDECL is the declaration node of the function (as a tree),
1318 FUNTYPE is the data type of the function (as a tree),
1319 or for a library call it is an identifier node for the subroutine name.
1320 SIZE is the number of bytes of arguments passed on the stack.
1322 On the ARM, the caller does not pop any of its arguments that were passed
1324 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1326 /* Define how to find the value returned by a library function
1327 assuming the value has mode MODE. */
1328 #define LIBCALL_VALUE(MODE) \
1329 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1330 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1331 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1332 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1333 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1334 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1335 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1336 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1337 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1339 /* Define how to find the value returned by a function.
1340 VALTYPE is the data type of the value (as a tree).
1341 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1342 otherwise, FUNC is 0. */
1343 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1344 arm_function_value (VALTYPE, FUNC);
1346 /* 1 if N is a possible register number for a function value.
1347 On the ARM, only r0 and f0 can return results. */
1348 /* On a Cirrus chip, mvf0 can return results. */
1349 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1350 ((REGNO) == ARG_REGISTER (1) \
1351 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1352 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1353 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1354 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1355 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1357 /* Amount of memory needed for an untyped call to save all possible return
1359 #define APPLY_RESULT_SIZE arm_apply_result_size()
1361 /* How large values are returned */
1362 /* A C expression which can inhibit the returning of certain function values
1363 in registers, based on the type of value. */
1364 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1366 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1367 values must be in memory. On the ARM, they need only do so if larger
1368 than a word, or if they contain elements offset from zero in the struct. */
1369 #define DEFAULT_PCC_STRUCT_RETURN 0
1371 /* These bits describe the different types of function supported
1372 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1373 normal function and an interworked function, for example. Knowing the
1374 type of a function is important for determining its prologue and
1376 Note value 7 is currently unassigned. Also note that the interrupt
1377 function types all have bit 2 set, so that they can be tested for easily.
1378 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1379 machine_function structure is initialized (to zero) func_type will
1380 default to unknown. This will force the first use of arm_current_func_type
1381 to call arm_compute_func_type. */
1382 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1383 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1384 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1385 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1386 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1387 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1389 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1391 /* In addition functions can have several type modifiers,
1392 outlined by these bit masks: */
1393 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1394 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1395 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1396 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1397 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1399 /* Some macros to test these flags. */
1400 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1401 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1402 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1403 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1404 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1405 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1408 /* Structure used to hold the function stack frame layout. Offsets are
1409 relative to the stack pointer on function entry. Positive offsets are
1410 in the direction of stack growth.
1411 Only soft_frame is used in thumb mode. */
1413 typedef struct arm_stack_offsets GTY(())
1415 int saved_args; /* ARG_POINTER_REGNUM. */
1416 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1418 int soft_frame; /* FRAME_POINTER_REGNUM. */
1419 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1420 int outgoing_args; /* STACK_POINTER_REGNUM. */
1424 /* A C structure for machine-specific, per-function data.
1425 This is added to the cfun structure. */
1426 typedef struct machine_function GTY(())
1428 /* Additional stack adjustment in __builtin_eh_throw. */
1429 rtx eh_epilogue_sp_ofs;
1430 /* Records if LR has to be saved for far jumps. */
1432 /* Records if ARG_POINTER was ever live. */
1433 int arg_pointer_live;
1434 /* Records if the save of LR has been eliminated. */
1435 int lr_save_eliminated;
1436 /* The size of the stack frame. Only valid after reload. */
1437 arm_stack_offsets stack_offsets;
1438 /* Records the type of the current function. */
1439 unsigned long func_type;
1440 /* Record if the function has a variable argument list. */
1441 int uses_anonymous_args;
1442 /* Records if sibcalls are blocked because an argument
1443 register is needed to preserve stack alignment. */
1444 int sibcall_blocked;
1445 /* The PIC register for this function. This might be a pseudo. */
1447 /* Labels for per-function Thumb call-via stubs. One per potential calling
1448 register. We can never call via LR or PC. We can call via SP if a
1449 trampoline happens to be on the top of the stack. */
1454 /* As in the machine_function, a global set of call-via labels, for code
1455 that is in text_section. */
1456 extern GTY(()) rtx thumb_call_via_label[14];
1458 /* A C type for declaring a variable that is used as the first argument of
1459 `FUNCTION_ARG' and other related values. For some target machines, the
1460 type `int' suffices and can hold the number of bytes of argument so far. */
1463 /* This is the number of registers of arguments scanned so far. */
1465 /* This is the number of iWMMXt register arguments scanned so far. */
1472 /* Define where to put the arguments to a function.
1473 Value is zero to push the argument on the stack,
1474 or a hard register in which to store the argument.
1476 MODE is the argument's machine mode.
1477 TYPE is the data type of the argument (as a tree).
1478 This is null for libcalls where that information may
1480 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1481 the preceding args and about the function being called.
1482 NAMED is nonzero if this argument is a named parameter
1483 (otherwise it is an extra parameter matching an ellipsis).
1485 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1486 other arguments are passed on the stack. If (NAMED == 0) (which happens
1487 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1488 defined), say it is passed in the stack (function_prologue will
1489 indeed make it pass in the stack if necessary). */
1490 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1491 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1493 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1494 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1496 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1497 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1499 /* For AAPCS, padding should never be below the argument. For other ABIs,
1500 * mimic the default. */
1501 #define PAD_VARARGS_DOWN \
1502 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1504 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1505 for a call to a function whose data type is FNTYPE.
1506 For a library call, FNTYPE is 0.
1507 On the ARM, the offset starts at 0. */
1508 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1509 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1511 /* Update the data in CUM to advance over an argument
1512 of mode MODE and data type TYPE.
1513 (TYPE is null for libcalls where that information may not be available.) */
1514 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1516 if (arm_vector_mode_supported_p (MODE) \
1517 && (CUM).named_count > (CUM).nargs \
1518 && TARGET_IWMMXT_ABI) \
1519 (CUM).iwmmxt_nregs += 1; \
1521 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1523 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1524 argument with the specified mode and type. If it is not defined,
1525 `PARM_BOUNDARY' is used for all arguments. */
1526 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1527 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1528 ? DOUBLEWORD_ALIGNMENT \
1531 /* 1 if N is a possible register number for function argument passing.
1532 On the ARM, r0-r3 are used to pass args. */
1533 #define FUNCTION_ARG_REGNO_P(REGNO) \
1534 (IN_RANGE ((REGNO), 0, 3) \
1535 || (TARGET_IWMMXT_ABI \
1536 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1539 /* If your target environment doesn't prefix user functions with an
1540 underscore, you may wish to re-define this to prevent any conflicts.
1541 e.g. AOF may prefix mcount with an underscore. */
1542 #ifndef ARM_MCOUNT_NAME
1543 #define ARM_MCOUNT_NAME "*mcount"
1546 /* Call the function profiler with a given profile label. The Acorn
1547 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1548 On the ARM the full profile code will look like:
1557 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1558 will output the .text section.
1560 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1561 ``prof'' doesn't seem to mind about this!
1563 Note - this version of the code is designed to work in both ARM and
1565 #ifndef ARM_FUNCTION_PROFILER
1566 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1571 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1572 IP_REGNUM, LR_REGNUM); \
1573 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1574 fputc ('\n', STREAM); \
1575 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1576 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1577 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1581 #ifdef THUMB_FUNCTION_PROFILER
1582 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1584 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1586 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1588 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1589 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1592 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1593 the stack pointer does not matter. The value is tested only in
1594 functions that have frame pointers.
1595 No definition is equivalent to always zero.
1597 On the ARM, the function epilogue recovers the stack pointer from the
1599 #define EXIT_IGNORE_STACK 1
1601 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1603 /* Determine if the epilogue should be output as RTL.
1604 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1605 /* This is disabled for Thumb-2 because it will confuse the
1606 conditional insn counter. */
1607 #define USE_RETURN_INSN(ISCOND) \
1608 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1610 /* Definitions for register eliminations.
1612 This is an array of structures. Each structure initializes one pair
1613 of eliminable registers. The "from" register number is given first,
1614 followed by "to". Eliminations of the same "from" register are listed
1615 in order of preference.
1617 We have two registers that can be eliminated on the ARM. First, the
1618 arg pointer register can often be eliminated in favor of the stack
1619 pointer register. Secondly, the pseudo frame pointer register can always
1620 be eliminated; it is replaced with either the stack or the real frame
1621 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1622 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1624 #define ELIMINABLE_REGS \
1625 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1626 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1627 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1628 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1629 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1630 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1631 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1633 /* Given FROM and TO register numbers, say whether this elimination is
1634 allowed. Frame pointer elimination is automatically handled.
1636 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1637 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1638 pointer, we must eliminate FRAME_POINTER_REGNUM into
1639 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1640 ARG_POINTER_REGNUM. */
1641 #define CAN_ELIMINATE(FROM, TO) \
1642 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1643 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1644 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1645 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1648 /* Define the offset between two registers, one to be eliminated, and the
1649 other its replacement, at the start of a routine. */
1650 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1652 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1654 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1656 /* Special case handling of the location of arguments passed on the stack. */
1657 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1659 /* Initialize data used by insn expanders. This is called from insn_emit,
1660 once for every function before code is generated. */
1661 #define INIT_EXPANDERS arm_init_expanders ()
1663 /* Output assembler code for a block containing the constant parts
1664 of a trampoline, leaving space for the variable parts.
1666 On the ARM, (if r8 is the static chain regnum, and remembering that
1667 referencing pc adds an offset of 8) the trampoline looks like:
1670 .word static chain value
1671 .word function's address
1672 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1673 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1675 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1676 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1677 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1678 PC_REGNUM, PC_REGNUM); \
1679 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1680 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1683 /* The Thumb-2 trampoline is similar to the arm implementation.
1684 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1685 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1687 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1688 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1689 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1690 PC_REGNUM, PC_REGNUM); \
1691 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1692 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1695 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1697 ASM_OUTPUT_ALIGN(FILE, 2); \
1698 fprintf (FILE, "\t.code\t16\n"); \
1699 fprintf (FILE, ".Ltrampoline_start:\n"); \
1700 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1701 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1703 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1704 STATIC_CHAIN_REGNUM); \
1705 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1707 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1709 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1711 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1712 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1715 #define TRAMPOLINE_TEMPLATE(FILE) \
1717 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1718 else if (TARGET_THUMB2) \
1719 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1721 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1723 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1725 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1728 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1729 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1732 /* Length in units of the trampoline for entering a nested function. */
1733 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1735 /* Alignment required for a trampoline in bits. */
1736 #define TRAMPOLINE_ALIGNMENT 32
1739 /* Emit RTL insns to initialize the variable parts of a trampoline.
1740 FNADDR is an RTX for the address of the function's pure code.
1741 CXT is an RTX for the static chain value for the function. */
1742 #ifndef INITIALIZE_TRAMPOLINE
1743 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1745 emit_move_insn (gen_rtx_MEM (SImode, \
1746 plus_constant (TRAMP, \
1747 TARGET_32BIT ? 8 : 12)), \
1749 emit_move_insn (gen_rtx_MEM (SImode, \
1750 plus_constant (TRAMP, \
1751 TARGET_32BIT ? 12 : 16)), \
1753 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1754 0, VOIDmode, 2, TRAMP, Pmode, \
1755 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1760 /* Addressing modes, and classification of registers for them. */
1761 #define HAVE_POST_INCREMENT 1
1762 #define HAVE_PRE_INCREMENT TARGET_32BIT
1763 #define HAVE_POST_DECREMENT TARGET_32BIT
1764 #define HAVE_PRE_DECREMENT TARGET_32BIT
1765 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1766 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1767 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1768 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1770 /* Macros to check register numbers against specific register classes. */
1772 /* These assume that REGNO is a hard or pseudo reg number.
1773 They give nonzero only if REGNO is a hard reg of the suitable class
1774 or a pseudo reg currently allocated to a suitable hard reg.
1775 Since they use reg_renumber, they are safe only once reg_renumber
1776 has been allocated, which happens in local-alloc.c. */
1777 #define TEST_REGNO(R, TEST, VALUE) \
1778 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1780 /* Don't allow the pc to be used. */
1781 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1782 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1783 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1784 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1786 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1787 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1788 || (GET_MODE_SIZE (MODE) >= 4 \
1789 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1791 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1793 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1794 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1796 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1797 For Thumb, we can not use SP + reg, so reject SP. */
1798 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1799 REGNO_OK_FOR_INDEX_P (X)
1801 /* For ARM code, we don't care about the mode, but for Thumb, the index
1802 must be suitable for use in a QImode load. */
1803 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1804 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1806 /* Maximum number of registers that can appear in a valid memory address.
1807 Shifts in addresses can't be by a register. */
1808 #define MAX_REGS_PER_ADDRESS 2
1810 /* Recognize any constant value that is a valid address. */
1811 /* XXX We can address any constant, eventually... */
1813 #ifdef AOF_ASSEMBLER
1815 #define CONSTANT_ADDRESS_P(X) \
1816 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1820 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1821 #define CONSTANT_ADDRESS_P(X) \
1822 (GET_CODE (X) == SYMBOL_REF \
1823 && (CONSTANT_POOL_ADDRESS_P (X) \
1824 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1826 #endif /* AOF_ASSEMBLER */
1828 /* Nonzero if the constant value X is a legitimate general operand.
1829 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1831 On the ARM, allow any integer (invalid ones are removed later by insn
1832 patterns), nice doubles and symbol_refs which refer to the function's
1835 When generating pic allow anything. */
1836 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1838 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1839 ( GET_CODE (X) == CONST_INT \
1840 || GET_CODE (X) == CONST_DOUBLE \
1841 || CONSTANT_ADDRESS_P (X) \
1844 #define LEGITIMATE_CONSTANT_P(X) \
1845 (!arm_tls_referenced_p (X) \
1846 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1847 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1849 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1850 #define SUBTARGET_NAME_ENCODING_LENGTHS
1853 /* This is a C fragment for the inside of a switch statement.
1854 Each case label should return the number of characters to
1855 be stripped from the start of a function's name, if that
1856 name starts with the indicated character. */
1857 #define ARM_NAME_ENCODING_LENGTHS \
1858 case '*': return 1; \
1859 SUBTARGET_NAME_ENCODING_LENGTHS
1861 /* This is how to output a reference to a user-level label named NAME.
1862 `assemble_name' uses this. */
1863 #undef ASM_OUTPUT_LABELREF
1864 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1865 arm_asm_output_labelref (FILE, NAME)
1867 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1868 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1869 if (TARGET_THUMB2) \
1870 thumb2_asm_output_opcode (STREAM);
1872 /* The EABI specifies that constructors should go in .init_array.
1873 Other targets use .ctors for compatibility. */
1874 #ifndef ARM_EABI_CTORS_SECTION_OP
1875 #define ARM_EABI_CTORS_SECTION_OP \
1876 "\t.section\t.init_array,\"aw\",%init_array"
1878 #ifndef ARM_EABI_DTORS_SECTION_OP
1879 #define ARM_EABI_DTORS_SECTION_OP \
1880 "\t.section\t.fini_array,\"aw\",%fini_array"
1882 #define ARM_CTORS_SECTION_OP \
1883 "\t.section\t.ctors,\"aw\",%progbits"
1884 #define ARM_DTORS_SECTION_OP \
1885 "\t.section\t.dtors,\"aw\",%progbits"
1887 /* Define CTORS_SECTION_ASM_OP. */
1888 #undef CTORS_SECTION_ASM_OP
1889 #undef DTORS_SECTION_ASM_OP
1891 # define CTORS_SECTION_ASM_OP \
1892 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1893 # define DTORS_SECTION_ASM_OP \
1894 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1895 #else /* !defined (IN_LIBGCC2) */
1896 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1897 so we cannot use the definition above. */
1898 # ifdef __ARM_EABI__
1899 /* The .ctors section is not part of the EABI, so we do not define
1900 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1901 from trying to use it. We do define it when doing normal
1902 compilation, as .init_array can be used instead of .ctors. */
1903 /* There is no need to emit begin or end markers when using
1904 init_array; the dynamic linker will compute the size of the
1905 array itself based on special symbols created by the static
1906 linker. However, we do need to arrange to set up
1907 exception-handling here. */
1908 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1909 # define CTOR_LIST_END /* empty */
1910 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1911 # define DTOR_LIST_END /* empty */
1912 # else /* !defined (__ARM_EABI__) */
1913 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1914 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1915 # endif /* !defined (__ARM_EABI__) */
1916 #endif /* !defined (IN_LIBCC2) */
1918 /* True if the operating system can merge entities with vague linkage
1919 (e.g., symbols in COMDAT group) during dynamic linking. */
1920 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1921 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1924 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1926 #ifdef TARGET_UNWIND_INFO
1927 #define ARM_EABI_UNWIND_TABLES \
1928 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1930 #define ARM_EABI_UNWIND_TABLES 0
1933 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1934 and check its validity for a certain class.
1935 We have two alternate definitions for each of them.
1936 The usual definition accepts all pseudo regs; the other rejects
1937 them unless they have been allocated suitable hard regs.
1938 The symbol REG_OK_STRICT causes the latter definition to be used.
1939 Thumb-2 has the same restrictions as arm. */
1940 #ifndef REG_OK_STRICT
1942 #define ARM_REG_OK_FOR_BASE_P(X) \
1943 (REGNO (X) <= LAST_ARM_REGNUM \
1944 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1945 || REGNO (X) == FRAME_POINTER_REGNUM \
1946 || REGNO (X) == ARG_POINTER_REGNUM)
1948 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1949 (REGNO (X) <= LAST_LO_REGNUM \
1950 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1951 || (GET_MODE_SIZE (MODE) >= 4 \
1952 && (REGNO (X) == STACK_POINTER_REGNUM \
1953 || (X) == hard_frame_pointer_rtx \
1954 || (X) == arg_pointer_rtx)))
1956 #define REG_STRICT_P 0
1958 #else /* REG_OK_STRICT */
1960 #define ARM_REG_OK_FOR_BASE_P(X) \
1961 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1963 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1964 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1966 #define REG_STRICT_P 1
1968 #endif /* REG_OK_STRICT */
1970 /* Now define some helpers in terms of the above. */
1972 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1974 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1975 : ARM_REG_OK_FOR_BASE_P (X))
1977 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1979 /* For 16-bit Thumb, a valid index register is anything that can be used in
1980 a byte load instruction. */
1981 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1982 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1984 /* Nonzero if X is a hard reg that can be used as an index
1985 or if it is a pseudo reg. On the Thumb, the stack pointer
1987 #define REG_OK_FOR_INDEX_P(X) \
1989 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1990 : ARM_REG_OK_FOR_INDEX_P (X))
1992 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1993 For Thumb, we can not use SP + reg, so reject SP. */
1994 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1995 REG_OK_FOR_INDEX_P (X)
1997 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1998 that is a valid memory address for an instruction.
1999 The MODE argument is the machine mode for the MEM expression
2000 that wants to use this address. */
2002 #define ARM_BASE_REGISTER_RTX_P(X) \
2003 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2005 #define ARM_INDEX_REGISTER_RTX_P(X) \
2006 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2008 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2010 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2014 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2016 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2020 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2022 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2026 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2028 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2029 else if (TARGET_THUMB2) \
2030 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2031 else /* if (TARGET_THUMB1) */ \
2032 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2035 /* Try machine-dependent ways of modifying an illegitimate address
2036 to be legitimate. If we find one, return the new, valid address. */
2037 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2039 X = arm_legitimize_address (X, OLDX, MODE); \
2042 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2043 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2047 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2049 X = thumb_legitimize_address (X, OLDX, MODE); \
2052 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2055 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2056 else if (TARGET_THUMB2) \
2057 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2059 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2061 if (memory_address_p (MODE, X)) \
2065 /* Go to LABEL if ADDR (a legitimate address expression)
2066 has an effect that depends on the machine mode it is used for. */
2067 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2069 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2070 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2074 /* Nothing helpful to do for the Thumb */
2075 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2077 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2080 /* Specify the machine mode that this machine uses
2081 for the index in the tablejump instruction. */
2082 #define CASE_VECTOR_MODE Pmode
2084 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2086 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2087 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2088 : (max >= 0x200) ? HImode \
2091 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2092 unsigned is probably best, but may break some code. */
2093 #ifndef DEFAULT_SIGNED_CHAR
2094 #define DEFAULT_SIGNED_CHAR 0
2097 /* Max number of bytes we can move from memory to memory
2098 in one reasonably fast instruction. */
2102 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2104 /* Define if operations between registers always perform the operation
2105 on the full register even if a narrower mode is specified. */
2106 #define WORD_REGISTER_OPERATIONS
2108 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2109 will either zero-extend or sign-extend. The value of this macro should
2110 be the code that says which one of the two operations is implicitly
2111 done, UNKNOWN if none. */
2112 #define LOAD_EXTEND_OP(MODE) \
2113 (TARGET_THUMB ? ZERO_EXTEND : \
2114 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2115 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2117 /* Nonzero if access to memory by bytes is slow and undesirable. */
2118 #define SLOW_BYTE_ACCESS 0
2120 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2122 /* Immediate shift counts are truncated by the output routines (or was it
2123 the assembler?). Shift counts in a register are truncated by ARM. Note
2124 that the native compiler puts too large (> 32) immediate shift counts
2125 into a register and shifts by the register, letting the ARM decide what
2126 to do instead of doing that itself. */
2127 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2128 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2129 On the arm, Y in a register is used modulo 256 for the shift. Only for
2130 rotates is modulo 32 used. */
2131 /* #define SHIFT_COUNT_TRUNCATED 1 */
2133 /* All integers have the same format so truncation is easy. */
2134 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2136 /* Calling from registers is a massive pain. */
2137 #define NO_FUNCTION_CSE 1
2139 /* The machine modes of pointers and functions */
2140 #define Pmode SImode
2141 #define FUNCTION_MODE Pmode
2143 #define ARM_FRAME_RTX(X) \
2144 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2145 || (X) == arg_pointer_rtx)
2147 /* Moves to and from memory are quite expensive */
2148 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2149 (TARGET_32BIT ? 10 : \
2150 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2151 * (CLASS == LO_REGS ? 1 : 2)))
2153 /* Try to generate sequences that don't involve branches, we can then use
2154 conditional instructions */
2155 #define BRANCH_COST \
2156 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2158 /* Position Independent Code. */
2159 /* We decide which register to use based on the compilation options and
2160 the assembler in use; this is more general than the APCS restriction of
2161 using sb (r9) all the time. */
2162 extern unsigned arm_pic_register;
2164 /* The register number of the register used to address a table of static
2165 data addresses in memory. */
2166 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2168 /* We can't directly access anything that contains a symbol,
2169 nor can we indirect via the constant pool. One exception is
2170 UNSPEC_TLS, which is always PIC. */
2171 #define LEGITIMATE_PIC_OPERAND_P(X) \
2172 (!(symbol_mentioned_p (X) \
2173 || label_mentioned_p (X) \
2174 || (GET_CODE (X) == SYMBOL_REF \
2175 && CONSTANT_POOL_ADDRESS_P (X) \
2176 && (symbol_mentioned_p (get_pool_constant (X)) \
2177 || label_mentioned_p (get_pool_constant (X))))) \
2178 || tls_mentioned_p (X))
2180 /* We need to know when we are making a constant pool; this determines
2181 whether data needs to be in the GOT or can be referenced via a GOT
2183 extern int making_const_table;
2185 /* Handle pragmas for compatibility with Intel's compilers. */
2186 #define REGISTER_TARGET_PRAGMAS() do { \
2187 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2188 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2189 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2192 /* Condition code information. */
2193 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2194 return the mode to be used for the comparison. */
2196 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2198 #define REVERSIBLE_CC_MODE(MODE) 1
2200 #define REVERSE_CONDITION(CODE,MODE) \
2201 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2202 ? reverse_condition_maybe_unordered (code) \
2203 : reverse_condition (code))
2205 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2208 if (GET_CODE (OP1) == CONST_INT \
2209 && ! (const_ok_for_arm (INTVAL (OP1)) \
2210 || (const_ok_for_arm (- INTVAL (OP1))))) \
2212 rtx const_op = OP1; \
2213 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2220 /* The arm5 clz instruction returns 32. */
2221 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2224 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2225 TARGET_THUMB2 ? "\t.thumb\n" : "")
2227 /* Output a push or a pop instruction (only used when profiling). */
2228 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2232 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2233 STACK_POINTER_REGNUM, REGNO); \
2235 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2239 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2243 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2244 STACK_POINTER_REGNUM, REGNO); \
2246 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2249 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2250 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2252 /* This is how to output a label which precedes a jumptable. Since
2253 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2254 #undef ASM_OUTPUT_CASE_LABEL
2255 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2258 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2259 ASM_OUTPUT_ALIGN (FILE, 2); \
2260 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2264 /* Make sure subsequent insns are aligned after a TBB. */
2265 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2268 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2269 ASM_OUTPUT_ALIGN (FILE, 1); \
2273 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2278 if (is_called_in_ARM_mode (DECL) \
2279 || (TARGET_THUMB1 && current_function_is_thunk)) \
2280 fprintf (STREAM, "\t.code 32\n") ; \
2281 else if (TARGET_THUMB1) \
2282 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2284 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2286 if (TARGET_POKE_FUNCTION_NAME) \
2287 arm_poke_function_name (STREAM, (char *) NAME); \
2291 /* For aliases of functions we use .thumb_set instead. */
2292 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2295 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2296 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2298 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2300 fprintf (FILE, "\t.thumb_set "); \
2301 assemble_name (FILE, LABEL1); \
2302 fprintf (FILE, ","); \
2303 assemble_name (FILE, LABEL2); \
2304 fprintf (FILE, "\n"); \
2307 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2311 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2312 /* To support -falign-* switches we need to use .p2align so
2313 that alignment directives in code sections will be padded
2314 with no-op instructions, rather than zeroes. */
2315 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2318 if ((MAX_SKIP) == 0) \
2319 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2321 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2322 (int) (LOG), (int) (MAX_SKIP)); \
2326 /* Add two bytes to the length of conditionally executed Thumb-2
2327 instructions for the IT instruction. */
2328 #define ADJUST_INSN_LENGTH(insn, length) \
2329 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2332 /* Only perform branch elimination (by making instructions conditional) if
2333 we're optimizing. For Thumb-2 check if any IT instructions need
2335 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2336 if (TARGET_ARM && optimize) \
2337 arm_final_prescan_insn (INSN); \
2338 else if (TARGET_THUMB2) \
2339 thumb2_final_prescan_insn (INSN); \
2340 else if (TARGET_THUMB1) \
2341 thumb1_final_prescan_insn (INSN)
2343 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2344 (CODE == '@' || CODE == '|' || CODE == '.' \
2345 || CODE == '(' || CODE == ')' \
2346 || (TARGET_32BIT && (CODE == '?')) \
2347 || (TARGET_THUMB2 && (CODE == '!')) \
2348 || (TARGET_THUMB && (CODE == '_')))
2350 /* Output an operand of an instruction. */
2351 #define PRINT_OPERAND(STREAM, X, CODE) \
2352 arm_print_operand (STREAM, X, CODE)
2354 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2355 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2356 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2357 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2358 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2359 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2362 /* Output the address of an operand. */
2363 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2365 int is_minus = GET_CODE (X) == MINUS; \
2367 if (GET_CODE (X) == REG) \
2368 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2369 else if (GET_CODE (X) == PLUS || is_minus) \
2371 rtx base = XEXP (X, 0); \
2372 rtx index = XEXP (X, 1); \
2373 HOST_WIDE_INT offset = 0; \
2374 if (GET_CODE (base) != REG) \
2376 /* Ensure that BASE is a register. */ \
2377 /* (one of them must be). */ \
2382 switch (GET_CODE (index)) \
2385 offset = INTVAL (index); \
2388 asm_fprintf (STREAM, "[%r, #%wd]", \
2389 REGNO (base), offset); \
2393 asm_fprintf (STREAM, "[%r, %s%r]", \
2394 REGNO (base), is_minus ? "-" : "", \
2404 asm_fprintf (STREAM, "[%r, %s%r", \
2405 REGNO (base), is_minus ? "-" : "", \
2406 REGNO (XEXP (index, 0))); \
2407 arm_print_operand (STREAM, index, 'S'); \
2408 fputs ("]", STREAM); \
2413 gcc_unreachable (); \
2416 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2417 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2419 extern enum machine_mode output_memory_reference_mode; \
2421 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2423 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2424 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2425 REGNO (XEXP (X, 0)), \
2426 GET_CODE (X) == PRE_DEC ? "-" : "", \
2427 GET_MODE_SIZE (output_memory_reference_mode)); \
2429 asm_fprintf (STREAM, "[%r], #%s%d", \
2430 REGNO (XEXP (X, 0)), \
2431 GET_CODE (X) == POST_DEC ? "-" : "", \
2432 GET_MODE_SIZE (output_memory_reference_mode)); \
2434 else if (GET_CODE (X) == PRE_MODIFY) \
2436 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2437 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2438 asm_fprintf (STREAM, "#%wd]!", \
2439 INTVAL (XEXP (XEXP (X, 1), 1))); \
2441 asm_fprintf (STREAM, "%r]!", \
2442 REGNO (XEXP (XEXP (X, 1), 1))); \
2444 else if (GET_CODE (X) == POST_MODIFY) \
2446 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2447 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2448 asm_fprintf (STREAM, "#%wd", \
2449 INTVAL (XEXP (XEXP (X, 1), 1))); \
2451 asm_fprintf (STREAM, "%r", \
2452 REGNO (XEXP (XEXP (X, 1), 1))); \
2454 else output_addr_const (STREAM, X); \
2457 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2459 if (GET_CODE (X) == REG) \
2460 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2461 else if (GET_CODE (X) == POST_INC) \
2462 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2463 else if (GET_CODE (X) == PLUS) \
2465 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2466 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2467 asm_fprintf (STREAM, "[%r, #%wd]", \
2468 REGNO (XEXP (X, 0)), \
2469 INTVAL (XEXP (X, 1))); \
2471 asm_fprintf (STREAM, "[%r, %r]", \
2472 REGNO (XEXP (X, 0)), \
2473 REGNO (XEXP (X, 1))); \
2476 output_addr_const (STREAM, X); \
2479 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2481 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2483 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2485 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2486 if (arm_output_addr_const_extra (file, x) == FALSE) \
2489 /* A C expression whose value is RTL representing the value of the return
2490 address for the frame COUNT steps up from the current frame. */
2492 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2493 arm_return_addr (COUNT, FRAME)
2495 /* Mask of the bits in the PC that contain the real return address
2496 when running in 26-bit mode. */
2497 #define RETURN_ADDR_MASK26 (0x03fffffc)
2499 /* Pick up the return address upon entry to a procedure. Used for
2500 dwarf2 unwind information. This also enables the table driven
2502 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2503 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2505 /* Used to mask out junk bits from the return address, such as
2506 processor state, interrupt status, condition codes and the like. */
2507 #define MASK_RETURN_ADDR \
2508 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2509 in 26 bit mode, the condition codes must be masked out of the \
2510 return address. This does not apply to ARM6 and later processors \
2511 when running in 32 bit mode. */ \
2512 ((arm_arch4 || TARGET_THUMB) \
2513 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2514 : arm_gen_return_addr_mask ())
2524 ARM_BUILTIN_WAVG2BR,
2525 ARM_BUILTIN_WAVG2HR,
2552 ARM_BUILTIN_TMOVMSKB,
2553 ARM_BUILTIN_TMOVMSKH,
2554 ARM_BUILTIN_TMOVMSKW,
2563 ARM_BUILTIN_WPACKHSS,
2564 ARM_BUILTIN_WPACKWSS,
2565 ARM_BUILTIN_WPACKDSS,
2566 ARM_BUILTIN_WPACKHUS,
2567 ARM_BUILTIN_WPACKWUS,
2568 ARM_BUILTIN_WPACKDUS,
2573 ARM_BUILTIN_WADDSSB,
2574 ARM_BUILTIN_WADDSSH,
2575 ARM_BUILTIN_WADDSSW,
2576 ARM_BUILTIN_WADDUSB,
2577 ARM_BUILTIN_WADDUSH,
2578 ARM_BUILTIN_WADDUSW,
2582 ARM_BUILTIN_WSUBSSB,
2583 ARM_BUILTIN_WSUBSSH,
2584 ARM_BUILTIN_WSUBSSW,
2585 ARM_BUILTIN_WSUBUSB,
2586 ARM_BUILTIN_WSUBUSH,
2587 ARM_BUILTIN_WSUBUSW,
2594 ARM_BUILTIN_WCMPEQB,
2595 ARM_BUILTIN_WCMPEQH,
2596 ARM_BUILTIN_WCMPEQW,
2597 ARM_BUILTIN_WCMPGTUB,
2598 ARM_BUILTIN_WCMPGTUH,
2599 ARM_BUILTIN_WCMPGTUW,
2600 ARM_BUILTIN_WCMPGTSB,
2601 ARM_BUILTIN_WCMPGTSH,
2602 ARM_BUILTIN_WCMPGTSW,
2604 ARM_BUILTIN_TEXTRMSB,
2605 ARM_BUILTIN_TEXTRMSH,
2606 ARM_BUILTIN_TEXTRMSW,
2607 ARM_BUILTIN_TEXTRMUB,
2608 ARM_BUILTIN_TEXTRMUH,
2609 ARM_BUILTIN_TEXTRMUW,
2659 ARM_BUILTIN_WUNPCKIHB,
2660 ARM_BUILTIN_WUNPCKIHH,
2661 ARM_BUILTIN_WUNPCKIHW,
2662 ARM_BUILTIN_WUNPCKILB,
2663 ARM_BUILTIN_WUNPCKILH,
2664 ARM_BUILTIN_WUNPCKILW,
2666 ARM_BUILTIN_WUNPCKEHSB,
2667 ARM_BUILTIN_WUNPCKEHSH,
2668 ARM_BUILTIN_WUNPCKEHSW,
2669 ARM_BUILTIN_WUNPCKEHUB,
2670 ARM_BUILTIN_WUNPCKEHUH,
2671 ARM_BUILTIN_WUNPCKEHUW,
2672 ARM_BUILTIN_WUNPCKELSB,
2673 ARM_BUILTIN_WUNPCKELSH,
2674 ARM_BUILTIN_WUNPCKELSW,
2675 ARM_BUILTIN_WUNPCKELUB,
2676 ARM_BUILTIN_WUNPCKELUH,
2677 ARM_BUILTIN_WUNPCKELUW,
2679 ARM_BUILTIN_THREAD_POINTER,
2684 /* Do not emit .note.GNU-stack by default. */
2685 #ifndef NEED_INDICATE_EXEC_STACK
2686 #define NEED_INDICATE_EXEC_STACK 0
2689 #endif /* ! GCC_ARM_H */
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