1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
36 #define TARGET_CPU_arm2 0x0000
37 #define TARGET_CPU_arm250 0x0000
38 #define TARGET_CPU_arm3 0x0000
39 #define TARGET_CPU_arm6 0x0001
40 #define TARGET_CPU_arm600 0x0001
41 #define TARGET_CPU_arm610 0x0002
42 #define TARGET_CPU_arm7 0x0001
43 #define TARGET_CPU_arm7m 0x0004
44 #define TARGET_CPU_arm7dm 0x0004
45 #define TARGET_CPU_arm7dmi 0x0004
46 #define TARGET_CPU_arm700 0x0001
47 #define TARGET_CPU_arm710 0x0002
48 #define TARGET_CPU_arm7100 0x0002
49 #define TARGET_CPU_arm7500 0x0002
50 #define TARGET_CPU_arm7500fe 0x1001
51 #define TARGET_CPU_arm7tdmi 0x0008
52 #define TARGET_CPU_arm8 0x0010
53 #define TARGET_CPU_arm810 0x0020
54 #define TARGET_CPU_strongarm 0x0040
55 #define TARGET_CPU_strongarm110 0x0040
56 #define TARGET_CPU_strongarm1100 0x0040
57 #define TARGET_CPU_arm9 0x0080
58 #define TARGET_CPU_arm9tdmi 0x0080
59 /* Configure didn't specify */
60 #define TARGET_CPU_generic 0x8000
64 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
65 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
67 extern enum arm_cond_code arm_current_cc;
68 extern char *arm_condition_codes[];
70 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
72 /* This is needed by the tail-calling peepholes */
73 extern int frame_pointer_needed;
76 /* Just in case configure has failed to define anything. */
77 #ifndef TARGET_CPU_DEFAULT
78 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
81 /* If the configuration file doesn't specify the cpu, the subtarget may
82 override it. If it doesn't, then default to an ARM6. */
83 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
84 #undef TARGET_CPU_DEFAULT
85 #ifdef SUBTARGET_CPU_DEFAULT
86 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
93 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
96 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
99 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
102 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 Unrecognized value in TARGET_CPU_DEFAULT.
114 #ifndef CPP_PREDEFINES
115 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
119 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
120 %(cpp_endian) %(subtarget_cpp_spec)"
122 /* Set the architecture define -- if -march= is set, then it overrides
123 the -mcpu= setting. */
124 #define CPP_CPU_ARCH_SPEC "\
125 %{march=arm2:-D__ARM_ARCH_2__} \
126 %{march=arm250:-D__ARM_ARCH_2__} \
127 %{march=arm3:-D__ARM_ARCH_2__} \
128 %{march=arm6:-D__ARM_ARCH_3__} \
129 %{march=arm600:-D__ARM_ARCH_3__} \
130 %{march=arm610:-D__ARM_ARCH_3__} \
131 %{march=arm7:-D__ARM_ARCH_3__} \
132 %{march=arm700:-D__ARM_ARCH_3__} \
133 %{march=arm710:-D__ARM_ARCH_3__} \
134 %{march=arm7100:-D__ARM_ARCH_3__} \
135 %{march=arm7500:-D__ARM_ARCH_3__} \
136 %{march=arm7500fe:-D__ARM_ARCH_3__} \
137 %{march=arm7m:-D__ARM_ARCH_3M__} \
138 %{march=arm7dm:-D__ARM_ARCH_3M__} \
139 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
140 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
141 %{march=arm8:-D__ARM_ARCH_4__} \
142 %{march=arm810:-D__ARM_ARCH_4__} \
143 %{march=arm9:-D__ARM_ARCH_4T__} \
144 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
145 %{march=strongarm:-D__ARM_ARCH_4__} \
146 %{march=strongarm110:-D__ARM_ARCH_4__} \
147 %{march=strongarm1100:-D__ARM_ARCH_4__} \
148 %{march=armv2:-D__ARM_ARCH_2__} \
149 %{march=armv2a:-D__ARM_ARCH_2__} \
150 %{march=armv3:-D__ARM_ARCH_3__} \
151 %{march=armv3m:-D__ARM_ARCH_3M__} \
152 %{march=armv4:-D__ARM_ARCH_4__} \
153 %{march=armv4t:-D__ARM_ARCH_4T__} \
155 %{mcpu=arm2:-D__ARM_ARCH_2__} \
156 %{mcpu=arm250:-D__ARM_ARCH_2__} \
157 %{mcpu=arm3:-D__ARM_ARCH_2__} \
158 %{mcpu=arm6:-D__ARM_ARCH_3__} \
159 %{mcpu=arm600:-D__ARM_ARCH_3__} \
160 %{mcpu=arm610:-D__ARM_ARCH_3__} \
161 %{mcpu=arm7:-D__ARM_ARCH_3__} \
162 %{mcpu=arm700:-D__ARM_ARCH_3__} \
163 %{mcpu=arm710:-D__ARM_ARCH_3__} \
164 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
165 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
167 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
168 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
169 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
170 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
171 %{mcpu=arm8:-D__ARM_ARCH_4__} \
172 %{mcpu=arm810:-D__ARM_ARCH_4__} \
173 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
174 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
175 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
176 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
177 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
178 %{!mcpu*:%(cpp_cpu_arch_default)}} \
181 /* Define __APCS_26__ if the PC also contains the PSR */
182 #define CPP_APCS_PC_SPEC "\
183 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
185 %{mapcs-26:-D__APCS_26__} \
186 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
189 #ifndef CPP_APCS_PC_DEFAULT_SPEC
190 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
193 #define CPP_FLOAT_SPEC "\
195 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
197 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
200 /* Default is hard float, which doesn't define anything */
201 #define CPP_FLOAT_DEFAULT_SPEC ""
203 #define CPP_ENDIAN_SPEC "\
206 %e-mbig-endian and -mlittle-endian may not be used together} \
207 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
208 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
211 /* Default is little endian, which doesn't define anything. */
212 #define CPP_ENDIAN_DEFAULT_SPEC ""
216 /* This macro defines names of additional specifications to put in the specs
217 that can be used in various specifications like CC1_SPEC. Its definition
218 is an initializer with a subgrouping for each command option.
220 Each subgrouping contains a string constant, that defines the
221 specification name, and a string constant that used by the GNU CC driver
224 Do not define this macro if it does not need to do anything. */
225 #define EXTRA_SPECS \
226 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
227 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
228 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
229 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
230 { "cpp_float", CPP_FLOAT_SPEC }, \
231 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
232 { "cpp_endian", CPP_ENDIAN_SPEC }, \
233 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
235 SUBTARGET_EXTRA_SPECS
237 #define SUBTARGET_EXTRA_SPECS
238 #define SUBTARGET_CPP_SPEC ""
241 /* Run-time Target Specification. */
242 #ifndef TARGET_VERSION
243 #define TARGET_VERSION \
244 fputs (" (ARM/generic)", stderr);
247 /* Run-time compilation parameters selecting different hardware subsets. */
248 extern int target_flags;
250 /* The floating point instruction architecture, can be 2 or 3 */
251 extern const char * target_fp_name;
253 /* Nonzero if the function prologue (and epilogue) should obey
254 the ARM Procedure Call Standard. */
255 #define ARM_FLAG_APCS_FRAME (0x0001)
257 /* Nonzero if the function prologue should output the function name to enable
258 the post mortem debugger to print a backtrace (very useful on RISCOS,
259 unused on RISCiX). Specifying this flag also enables
260 -fno-omit-frame-pointer.
261 XXX Must still be implemented in the prologue. */
262 #define ARM_FLAG_POKE (0x0002)
264 /* Nonzero if floating point instructions are emulated by the FPE, in which
265 case instruction scheduling becomes very uninteresting. */
266 #define ARM_FLAG_FPE (0x0004)
268 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
269 that assume restoration of the condition flags when returning from a
270 branch and link (ie a function). */
271 #define ARM_FLAG_APCS_32 (0x0020)
273 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
275 /* Nonzero if stack checking should be performed on entry to each function
276 which allocates temporary variables on the stack. */
277 #define ARM_FLAG_APCS_STACK (0x0040)
279 /* Nonzero if floating point parameters should be passed to functions in
280 floating point registers. */
281 #define ARM_FLAG_APCS_FLOAT (0x0080)
283 /* Nonzero if re-entrant, position independent code should be generated.
284 This is equivalent to -fpic. */
285 #define ARM_FLAG_APCS_REENT (0x0100)
287 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
288 loaded byte-at-a-time. */
289 #define ARM_FLAG_SHORT_BYTE (0x0200)
291 /* Nonzero if all floating point instructions are missing (and there is no
292 emulator either). Generate function calls for all ops in this case. */
293 #define ARM_FLAG_SOFT_FLOAT (0x0400)
295 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
296 #define ARM_FLAG_BIG_END (0x0800)
298 /* Nonzero if we should compile for Thumb interworking. */
299 #define ARM_FLAG_THUMB (0x1000)
301 /* Nonzero if we should have little-endian words even when compiling for
302 big-endian (for backwards compatibility with older versions of GCC). */
303 #define ARM_FLAG_LITTLE_WORDS (0x2000)
305 /* Nonzero if we need to protect the prolog from scheduling */
306 #define ARM_FLAG_NO_SCHED_PRO (0x4000)
308 /* Nonzero if a call to abort should be generated if a noreturn
309 function tries to return. */
310 #define ARM_FLAG_ABORT_NORETURN (0x8000)
312 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
313 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
314 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
315 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
316 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
317 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
318 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
319 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
320 that short values sould not be accessed using word load instructions
321 as there is a possibility that they may not be word aligned and this
322 would generate an MMU fault. On processors which do not have a 16 bit
323 load instruction therefore, short values must be loaded by individual
324 byte accesses rather than loading a word and then shifting the desired
326 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
327 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
328 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
329 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
330 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
331 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
332 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
333 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
335 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
336 Bit 31 is reserved. See riscix.h. */
337 #ifndef SUBTARGET_SWITCHES
338 #define SUBTARGET_SWITCHES
341 #define TARGET_SWITCHES \
343 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
344 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
345 "Generate APCS conformant stack frames" }, \
346 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
347 {"poke-function-name", ARM_FLAG_POKE, \
348 "Store function names in object code" }, \
349 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
350 {"fpe", ARM_FLAG_FPE, "" }, \
351 {"apcs-32", ARM_FLAG_APCS_32, \
352 "Use the 32bit version of the APCS" }, \
353 {"apcs-26", -ARM_FLAG_APCS_32, \
354 "Use the 26bit version of the APCS" }, \
355 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
356 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
357 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
358 "Pass FP arguments in FP registers" }, \
359 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
360 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
361 "Generate re-entrant, PIC code" }, \
362 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
363 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
364 "Load shorts a byte at a time" }, \
365 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
366 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
367 "Load words a byte at a time" }, \
368 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
369 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
370 "Use library calls to perform FP operations" }, \
371 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
372 "Use hardware floating point instructions" }, \
373 {"big-endian", ARM_FLAG_BIG_END, \
374 "Assume target CPU is configured as big endian" }, \
375 {"little-endian", -ARM_FLAG_BIG_END, \
376 "Assume target CPU is configured as little endian" }, \
377 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
378 "Assume big endian bytes, little endian words" }, \
379 {"thumb-interwork", ARM_FLAG_THUMB, \
380 "Support calls between THUMB and ARM instructions sets" }, \
381 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \
382 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
383 "Generate a call to abort if a noreturn function returns"}, \
384 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
385 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
386 "Do not move instructions into a function's prologue" }, \
387 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
389 {"", TARGET_DEFAULT } \
392 #define TARGET_OPTIONS \
394 {"cpu=", & arm_select[0].string, \
395 "Specify the name of the target CPU" }, \
396 {"arch=", & arm_select[1].string, \
397 "Specify the name of the target architecture" }, \
398 {"tune=", & arm_select[2].string, "" }, \
399 {"fpe=", & target_fp_name, "" }, \
400 {"fp=", & target_fp_name, \
401 "Specify the version of the floating point emulator" }, \
402 { "structure-size-boundary=", & structure_size_string, \
403 "Specify the minumum bit alignment of structures" } \
406 struct arm_cpu_select
410 const struct processors * processors;
413 /* This is a magic array. If the user specifies a command line switch
414 which matches one of the entries in TARGET_OPTIONS then the corresponding
415 string pointer will be set to the value specified by the user. */
416 extern struct arm_cpu_select arm_select[];
424 /* Recast the program mode class to be the prog_mode attribute */
425 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
427 extern enum prog_mode_type arm_prgmode;
429 /* What sort of floating point unit do we have? Hardware or software.
430 If software, is it issue 2 or issue 3? */
431 enum floating_point_type
438 /* Recast the floating point class to be the floating point attribute. */
439 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
441 /* What type of floating point to tune for */
442 extern enum floating_point_type arm_fpu;
444 /* What type of floating point instructions are available */
445 extern enum floating_point_type arm_fpu_arch;
447 /* Default floating point architecture. Override in sub-target if
449 #define FP_DEFAULT FP_SOFT2
451 /* Nonzero if the processor has a fast multiply insn, and one that does
452 a 64-bit multiply of two 32-bit values. */
453 extern int arm_fast_multiply;
455 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
456 extern int arm_arch4;
458 /* Nonzero if this chip can benefit from load scheduling. */
459 extern int arm_ld_sched;
461 /* Nonzero if this chip is a StrongARM. */
462 extern int arm_is_strong;
464 /* Nonzero if this chip is a an ARM6 or an ARM7. */
465 extern int arm_is_6_or_7;
467 #ifndef TARGET_DEFAULT
468 #define TARGET_DEFAULT 0
471 /* The frame pointer register used in gcc has nothing to do with debugging;
472 that is controlled by the APCS-FRAME option. */
473 /* Not fully implemented yet */
474 /* #define CAN_DEBUG_WITHOUT_FP 1 */
476 #define TARGET_MEM_FUNCTIONS 1
478 #define OVERRIDE_OPTIONS arm_override_options ()
480 /* Target machine storage Layout. */
483 /* Define this macro if it is advisable to hold scalars in registers
484 in a wider mode than that declared by the program. In such cases,
485 the value is constrained to be within the bounds of the declared
486 type, but kept valid in the wider mode. The signedness of the
487 extension may differ from that of the type. */
489 /* It is far faster to zero extend chars than to sign extend them */
491 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
492 if (GET_MODE_CLASS (MODE) == MODE_INT \
493 && GET_MODE_SIZE (MODE) < 4) \
495 if (MODE == QImode) \
497 else if (MODE == HImode) \
498 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
502 /* Define this macro if the promotion described by `PROMOTE_MODE'
503 should also be done for outgoing function arguments. */
504 /* This is required to ensure that push insns always push a word. */
505 #define PROMOTE_FUNCTION_ARGS
507 /* Define for XFmode extended real floating point support.
508 This will automatically cause REAL_ARITHMETIC to be defined. */
510 I think I have added all the code to make this work. Unfortunately,
511 early releases of the floating point emulation code on RISCiX used a
512 different format for extended precision numbers. On my RISCiX box there
513 is a bug somewhere which causes the machine to lock up when running enquire
514 with long doubles. There is the additional aspect that Norcroft C
515 treats long doubles as doubles and we ought to remain compatible.
516 Perhaps someone with an FPA coprocessor and not running RISCiX would like
517 to try this someday. */
518 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
520 /* Disable XFmode patterns in md file */
521 #define ENABLE_XF_PATTERNS 0
523 /* Define if you don't want extended real, but do want to use the
524 software floating point emulator for REAL_ARITHMETIC and
525 decimal <-> binary conversion. */
526 /* See comment above */
527 #define REAL_ARITHMETIC
529 /* Define this if most significant bit is lowest numbered
530 in instructions that operate on numbered bit-fields. */
531 #define BITS_BIG_ENDIAN 0
533 /* Define this if most significant byte of a word is the lowest numbered.
534 Most ARM processors are run in little endian mode, so that is the default.
535 If you want to have it run-time selectable, change the definition in a
536 cover file to be TARGET_BIG_ENDIAN. */
537 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
539 /* Define this if most significant word of a multiword number is the lowest
541 This is always false, even when in big-endian mode. */
542 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
544 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
545 on processor pre-defineds when compiling libgcc2.c. */
546 #if defined(__ARMEB__) && !defined(__ARMWEL__)
547 #define LIBGCC2_WORDS_BIG_ENDIAN 1
549 #define LIBGCC2_WORDS_BIG_ENDIAN 0
552 /* Define this if most significant word of doubles is the lowest numbered.
553 This is always true, even when in little-endian mode. */
554 #define FLOAT_WORDS_BIG_ENDIAN 1
556 /* Number of bits in an addressable storage unit */
557 #define BITS_PER_UNIT 8
559 #define BITS_PER_WORD 32
561 #define UNITS_PER_WORD 4
563 #define POINTER_SIZE 32
565 #define PARM_BOUNDARY 32
567 #define STACK_BOUNDARY 32
569 #define FUNCTION_BOUNDARY 32
571 #define EMPTY_FIELD_BOUNDARY 32
573 #define BIGGEST_ALIGNMENT 32
575 /* Make strings word-aligned so strcpy from constants will be faster. */
576 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
577 (TREE_CODE (EXP) == STRING_CST \
578 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
580 /* Every structures size must be a multiple of 32 bits. */
581 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
582 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
584 #ifndef STRUCTURE_SIZE_BOUNDARY
585 #define STRUCTURE_SIZE_BOUNDARY 32
588 /* Used when parsing command line option -mstructure_size_boundary. */
589 extern const char * structure_size_string;
591 /* Non-zero if move instructions will actually fail to work
592 when given unaligned data. */
593 #define STRICT_ALIGNMENT 1
595 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
598 /* Standard register usage. */
600 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
601 (S - saved over call).
603 r0 * argument word/integer result
606 r4-r8 S register variable
607 r9 S (rfp) register variable (real frame pointer)
609 r10 F S (sl) stack limit (used by -mapcs-stack-check)
610 r11 F S (fp) argument pointer
611 r12 (ip) temp workspace
612 r13 F S (sp) lower end of current stack frame
613 r14 (lr) link address/workspace
614 r15 F (pc) program counter
616 f0 floating point result
617 f1-f3 floating point scratch
619 f4-f7 S floating point variable
621 cc This is NOT a real register, but is used internally
622 to represent things that use or set the condition
624 sfp This isn't either. It is used during rtl generation
625 since the offset between the frame pointer and the
626 auto's isn't known until after register allocation.
627 afp Nor this, we only need this because of non-local
628 goto. Without it fp appears to be used and the
629 elimination code won't get rid of sfp. It tracks
630 fp exactly at all times.
632 *: See CONDITIONAL_REGISTER_USAGE */
634 /* The stack backtrace structure is as follows:
635 fp points to here: | save code pointer | [fp]
636 | return link value | [fp, #-4]
637 | return sp value | [fp, #-8]
638 | return fp value | [fp, #-12]
639 [| saved r10 value |]
650 [| saved f7 value |] three words
651 [| saved f6 value |] three words
652 [| saved f5 value |] three words
653 [| saved f4 value |] three words
654 r0-r3 are not normally saved in a C function. */
656 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
657 #define FIRST_PSEUDO_REGISTER 27
659 /* 1 for registers that have pervasive standard uses
660 and are not available for the register allocator. */
661 #define FIXED_REGISTERS \
669 /* 1 for registers not available across function calls.
670 These must include the FIXED_REGISTERS and also any
671 registers that can be used without being saved.
672 The latter must include the registers where values are returned
673 and the register where structure-value addresses are passed.
674 Aside from that, you can include as many other registers as you like.
675 The CC is not preserved over function calls on the ARM 6, so it is
676 easier to assume this for all. SFP is preserved, since FP is. */
677 #define CALL_USED_REGISTERS \
685 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
686 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
689 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
690 trampled. This effectively reduces the number of available registers by 1.
691 XXX It is a hack, I know.
692 XXX Is this still needed? */
693 #define CONDITIONAL_REGISTER_USAGE \
697 if (TARGET_SOFT_FLOAT) \
700 for (regno = 16; regno < 24; ++regno) \
701 fixed_regs[regno] = call_used_regs[regno] = 1; \
705 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
706 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
708 else if (TARGET_APCS_STACK) \
710 fixed_regs[10] = 1; \
711 call_used_regs[10] = 1; \
713 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
716 /* Return number of consecutive hard regs needed starting at reg REGNO
717 to hold something of mode MODE.
718 This is ordinarily the length in words of a value of mode MODE
719 but can be less for certain modes in special long registers.
721 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
723 #define HARD_REGNO_NREGS(REGNO, MODE) \
724 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
725 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
726 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
728 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
729 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
731 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
732 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
733 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
734 || REGNO == ARG_POINTER_REGNUM \
735 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
737 /* Value is 1 if it is a good idea to tie two pseudo registers
738 when one has mode MODE1 and one has mode MODE2.
739 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
740 for any hard reg, then this must be 0 for correct output. */
741 #define MODES_TIEABLE_P(MODE1, MODE2) \
742 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
744 /* Specify the registers used for certain standard purposes.
745 The values of these macros are register numbers. */
747 /* Define this if the program counter is overloaded on a register. */
750 /* Register to use for pushing function arguments. */
751 #define STACK_POINTER_REGNUM 13
753 /* Base register for access to local variables of the function. */
754 #define FRAME_POINTER_REGNUM 25
756 /* Define this to be where the real frame pointer is if it is not possible to
757 work out the offset between the frame pointer and the automatic variables
758 until after register allocation has taken place. FRAME_POINTER_REGNUM
759 should point to a special register that we will make sure is eliminated. */
760 #define HARD_FRAME_POINTER_REGNUM 11
762 /* Value should be nonzero if functions must have frame pointers.
763 Zero means the frame pointer need not be set up (and parms may be accessed
764 via the stack pointer) in functions that seem suitable.
765 If we have to have a frame pointer we might as well make use of it.
766 APCS says that the frame pointer does not need to be pushed in leaf
767 functions, or simple tail call functions. */
768 #define FRAME_POINTER_REQUIRED \
769 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
771 /* Base register for access to arguments of the function. */
772 #define ARG_POINTER_REGNUM 26
774 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
775 as an invisible last argument (possible since varargs don't exist in
776 Pascal), so the following is not true. */
777 #define STATIC_CHAIN_REGNUM 8
779 /* Register in which address to store a structure value
780 is passed to a function. */
781 #define STRUCT_VALUE_REGNUM 0
783 /* Internal, so that we don't need to refer to a raw number */
786 /* The order in which register should be allocated. It is good to use ip
787 since no saving is required (though calls clobber it) and it never contains
788 function parameters. It is quite good to use lr since other calls may
789 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
790 least likely to contain a function parameter; in addition results are
793 #define REG_ALLOC_ORDER \
795 3, 2, 1, 0, 12, 14, 4, 5, \
796 6, 7, 8, 10, 9, 11, 13, 15, \
797 16, 17, 18, 19, 20, 21, 22, 23, \
801 /* Register and constant classes. */
803 /* Register classes: all ARM regs or all FPU regs---simple! */
813 #define N_REG_CLASSES (int) LIM_REG_CLASSES
815 /* Give names of register classes as strings for dump file. */
816 #define REG_CLASS_NAMES \
824 /* Define which registers fit in which classes.
825 This is an initializer for a vector of HARD_REG_SET
826 of length N_REG_CLASSES. */
827 #define REG_CLASS_CONTENTS \
829 { 0x0000000 }, /* NO_REGS */ \
830 { 0x0FF0000 }, /* FPU_REGS */ \
831 { 0x200FFFF }, /* GENERAL_REGS */ \
832 { 0x2FFFFFF } /* ALL_REGS */ \
835 /* The same information, inverted:
836 Return the class number of the smallest class containing
837 reg number REGNO. This could be a conditional expression
838 or could index an array. */
839 #define REGNO_REG_CLASS(REGNO) \
840 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
841 || REGNO == ARG_POINTER_REGNUM) \
842 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
843 ? NO_REGS : FPU_REGS)
845 /* The class value for index registers, and the one for base regs. */
846 #define INDEX_REG_CLASS GENERAL_REGS
847 #define BASE_REG_CLASS GENERAL_REGS
849 /* Get reg_class from a letter such as appears in the machine description.
850 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
851 #define REG_CLASS_FROM_LETTER(C) \
852 ((C)=='f' ? FPU_REGS : NO_REGS)
854 /* The letters I, J, K, L and M in a register constraint string
855 can be used to stand for particular ranges of immediate operands.
856 This macro defines what the ranges are.
857 C is the letter, and VALUE is a constant value.
858 Return 1 if VALUE is in the range specified by C.
859 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
860 J: valid indexing constants.
861 K: ~value ok in rhs argument of data operand.
862 L: -value ok in rhs argument of data operand.
863 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
864 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
865 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
866 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
867 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
868 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
869 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
870 || (((VALUE) & ((VALUE) - 1)) == 0)) \
873 /* For the ARM, `Q' means that this is a memory operand that is just
874 an offset from a register.
875 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
876 address. This means that the symbol is in the text segment and can be
877 accessed without using a load. */
879 #define EXTRA_CONSTRAINT(OP, C) \
880 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
881 : (C) == 'R' ? (GET_CODE (OP) == MEM \
882 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
883 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
884 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
887 /* Constant letter 'G' for the FPU immediate constants.
888 'H' means the same constant negated. */
889 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
890 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
891 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
893 /* Given an rtx X being reloaded into a reg required to be
894 in class CLASS, return the class of reg to actually use.
895 In general this is just CLASS; but on some machines
896 in some cases it is preferable to use a more restrictive class. */
897 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
899 /* Return the register class of a scratch register needed to copy IN into
900 or out of a register in CLASS in MODE. If it can be done directly,
901 NO_REGS is returned. */
902 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
903 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
904 ? GENERAL_REGS : NO_REGS)
906 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
907 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
908 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
909 && (GET_CODE (X) == MEM \
910 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
911 && true_regnum (X) == -1))) \
912 ? GENERAL_REGS : NO_REGS)
914 /* Try a machine-dependent way of reloading an illegitimate address
915 operand. If we find one, push the reload and jump to WIN. This
916 macro is used in only one place: `find_reloads_address' in reload.c.
918 For the ARM, we wish to handle large displacements off a base
919 register by splitting the addend across a MOV and the mem insn.
920 This can cut the number of reloads needed. */
921 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
923 if (GET_CODE (X) == PLUS \
924 && GET_CODE (XEXP (X, 0)) == REG \
925 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
926 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
927 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
929 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
930 HOST_WIDE_INT low, high; \
932 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
933 low = ((val & 0xf) ^ 0x8) - 0x8; \
934 else if (MODE == SImode || MODE == QImode \
935 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
936 || (MODE == HImode && ! arm_arch4)) \
937 /* Need to be careful, -4096 is not a valid offset */ \
938 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
939 else if (MODE == HImode && arm_arch4) \
940 /* Need to be careful, -256 is not a valid offset */ \
941 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
942 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
943 && TARGET_HARD_FLOAT) \
944 /* Need to be careful, -1024 is not a valid offset */ \
945 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
949 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
950 /* Check for overflow or zero */ \
951 if (low == 0 || high == 0 || (high + low != val)) \
954 /* Reload the high part into a base reg; leave the low part \
956 X = gen_rtx_PLUS (GET_MODE (X), \
957 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
960 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
961 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
967 /* Return the maximum number of consecutive registers
968 needed to represent mode MODE in a register of class CLASS.
969 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
970 #define CLASS_MAX_NREGS(CLASS, MODE) \
971 ((CLASS) == FPU_REGS ? 1 \
972 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
974 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
975 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
976 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
977 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
980 /* Stack layout; function entry, exit and calling. */
982 /* Define this if pushing a word on the stack
983 makes the stack pointer a smaller address. */
984 #define STACK_GROWS_DOWNWARD 1
986 /* Define this if the nominal address of the stack frame
987 is at the high-address end of the local variables;
988 that is, each additional local variable allocated
989 goes at a more negative offset in the frame. */
990 #define FRAME_GROWS_DOWNWARD 1
992 /* Offset within stack frame to start allocating local variables at.
993 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
994 first local allocated. Otherwise, it is the offset to the BEGINNING
995 of the first local allocated. */
996 #define STARTING_FRAME_OFFSET 0
998 /* If we generate an insn to push BYTES bytes,
999 this says how many the stack pointer really advances by. */
1000 /* The push insns do not do this rounding implicitly. So don't define this. */
1001 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1003 /* Define this if the maximum size of all the outgoing args is to be
1004 accumulated and pushed during the prologue. The amount can be
1005 found in the variable current_function_outgoing_args_size. */
1006 #define ACCUMULATE_OUTGOING_ARGS
1008 /* Offset of first parameter from the argument pointer register value. */
1009 #define FIRST_PARM_OFFSET(FNDECL) 4
1011 /* Value is the number of byte of arguments automatically
1012 popped when returning from a subroutine call.
1013 FUNDECL is the declaration node of the function (as a tree),
1014 FUNTYPE is the data type of the function (as a tree),
1015 or for a library call it is an identifier node for the subroutine name.
1016 SIZE is the number of bytes of arguments passed on the stack.
1018 On the ARM, the caller does not pop any of its arguments that were passed
1020 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1022 /* Define how to find the value returned by a function.
1023 VALTYPE is the data type of the value (as a tree).
1024 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1025 otherwise, FUNC is 0. */
1026 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1027 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
1028 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
1029 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))
1031 /* Define how to find the value returned by a library function
1032 assuming the value has mode MODE. */
1033 #define LIBCALL_VALUE(MODE) \
1034 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1035 ? gen_rtx_REG (MODE, 16) \
1036 : gen_rtx_REG (MODE, 0))
1038 /* 1 if N is a possible register number for a function value.
1039 On the ARM, only r0 and f0 can return results. */
1040 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1041 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1043 /* How large values are returned */
1044 /* A C expression which can inhibit the returning of certain function values
1045 in registers, based on the type of value. */
1046 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1048 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1049 values must be in memory. On the ARM, they need only do so if larger
1050 than a word, or if they contain elements offset from zero in the struct. */
1051 #define DEFAULT_PCC_STRUCT_RETURN 0
1053 /* Define where to put the arguments to a function.
1054 Value is zero to push the argument on the stack,
1055 or a hard register in which to store the argument.
1057 MODE is the argument's machine mode.
1058 TYPE is the data type of the argument (as a tree).
1059 This is null for libcalls where that information may
1061 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1062 the preceding args and about the function being called.
1063 NAMED is nonzero if this argument is a named parameter
1064 (otherwise it is an extra parameter matching an ellipsis).
1066 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1067 other arguments are passed on the stack. If (NAMED == 0) (which happens
1068 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1069 passed in the stack (function_prologue will indeed make it pass in the
1070 stack if necessary). */
1071 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1073 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \
1076 /* For an arg passed partly in registers and partly in memory,
1077 this is the number of registers used.
1078 For args passed entirely in registers or entirely in memory, zero. */
1079 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1080 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
1081 ? GET_MODE_SIZE (MODE) \
1082 : int_size_in_bytes (TYPE)) \
1083 ? 4 - (CUM) / 4 : 0)
1085 /* A C type for declaring a variable that is used as the first argument of
1086 `FUNCTION_ARG' and other related values. For some target machines, the
1087 type `int' suffices and can hold the number of bytes of argument so far.
1089 On the ARM, this is the number of bytes of arguments scanned so far. */
1090 #define CUMULATIVE_ARGS int
1092 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1093 for a call to a function whose data type is FNTYPE.
1094 For a library call, FNTYPE is 0.
1095 On the ARM, the offset starts at 0. */
1096 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1097 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1099 /* Update the data in CUM to advance over an argument
1100 of mode MODE and data type TYPE.
1101 (TYPE is null for libcalls where that information may not be available.) */
1102 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1103 (CUM) += ((MODE) != BLKmode \
1104 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1105 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1107 /* 1 if N is a possible register number for function argument passing.
1108 On the ARM, r0-r3 are used to pass args. */
1109 #define FUNCTION_ARG_REGNO_P(REGNO) \
1110 ((REGNO) >= 0 && (REGNO) <= 3)
1112 /* Perform any actions needed for a function that is receiving a variable
1113 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1114 of the current parameter. PRETEND_SIZE is a variable that should be set to
1115 the amount of stack that must be pushed by the prolog to pretend that our
1118 Normally, this macro will push all remaining incoming registers on the
1119 stack and set PRETEND_SIZE to the length of the registers pushed.
1121 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1122 named arg and all anonymous args onto the stack.
1123 XXX I know the prologue shouldn't be pushing registers, but it is faster
1125 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1127 extern int current_function_anonymous_args; \
1128 current_function_anonymous_args = 1; \
1130 (PRETEND_SIZE) = 16 - (CUM); \
1133 /* Generate assembly output for the start of a function. */
1134 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1135 output_func_prologue ((STREAM), (SIZE))
1137 /* If your target environment doesn't prefix user functions with an
1138 underscore, you may wish to re-define this to prevent any conflicts.
1139 e.g. AOF may prefix mcount with an underscore. */
1140 #ifndef ARM_MCOUNT_NAME
1141 #define ARM_MCOUNT_NAME "*mcount"
1144 /* Call the function profiler with a given profile label. The Acorn
1145 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1146 On the ARM the full profile code will look like:
1155 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1156 will output the .text section.
1158 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1159 ``prof'' doesn't seem to mind about this! */
1160 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1165 fprintf ((STREAM), "\tmov\t%s%s, %s%s\n\tbl\t", \
1166 REGISTER_PREFIX, reg_names[12] /* ip */, \
1167 REGISTER_PREFIX, reg_names[14] /* lr */); \
1168 assemble_name ((STREAM), ARM_MCOUNT_NAME); \
1169 fputc ('\n', (STREAM)); \
1170 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", (LABELNO)); \
1171 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1172 ASM_OUTPUT_INT ((STREAM), sym); \
1175 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1176 the stack pointer does not matter. The value is tested only in
1177 functions that have frame pointers.
1178 No definition is equivalent to always zero.
1180 On the ARM, the function epilogue recovers the stack pointer from the
1182 #define EXIT_IGNORE_STACK 1
1184 /* Generate the assembly code for function exit. */
1185 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1186 output_func_epilogue ((STREAM), (SIZE))
1188 /* Determine if the epilogue should be output as RTL.
1189 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1190 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1192 /* Definitions for register eliminations.
1194 This is an array of structures. Each structure initializes one pair
1195 of eliminable registers. The "from" register number is given first,
1196 followed by "to". Eliminations of the same "from" register are listed
1197 in order of preference.
1199 We have two registers that can be eliminated on the ARM. First, the
1200 arg pointer register can often be eliminated in favor of the stack
1201 pointer register. Secondly, the pseudo frame pointer register can always
1202 be eliminated; it is replaced with either the stack or the real frame
1205 #define ELIMINABLE_REGS \
1206 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1207 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1208 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1209 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1211 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1212 Frame pointer elimination is automatically handled.
1214 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1215 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1216 pointer, we must eliminate FRAME_POINTER_REGNUM into
1217 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1218 #define CAN_ELIMINATE(FROM, TO) \
1219 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1221 /* Define the offset between two registers, one to be eliminated, and the other
1222 its replacement, at the start of a routine. */
1223 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1225 int volatile_func = arm_volatile_func (); \
1226 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1228 else if ((FROM) == FRAME_POINTER_REGNUM \
1229 && (TO) == STACK_POINTER_REGNUM) \
1230 (OFFSET) = (current_function_outgoing_args_size \
1231 + ((get_frame_size () + 3) & ~3)); \
1236 int saved_hard_reg = 0; \
1238 if (! volatile_func) \
1240 for (regno = 0; regno <= 10; regno++) \
1241 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1242 saved_hard_reg = 1, offset += 4; \
1243 for (regno = 16; regno <=23; regno++) \
1244 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1247 if ((FROM) == FRAME_POINTER_REGNUM) \
1248 (OFFSET) = -offset; \
1251 if (! frame_pointer_needed) \
1253 if (! volatile_func \
1254 && (regs_ever_live[14] || saved_hard_reg)) \
1256 offset += current_function_outgoing_args_size; \
1257 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1262 /* Output assembler code for a block containing the constant parts
1263 of a trampoline, leaving space for the variable parts.
1265 On the ARM, (if r8 is the static chain regnum, and remembering that
1266 referencing pc adds an offset of 8) the trampoline looks like:
1269 .word static chain value
1270 .word function's address
1271 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1272 #define TRAMPOLINE_TEMPLATE(FILE) \
1274 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1275 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1276 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1277 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1278 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1279 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1280 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1281 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1284 /* Length in units of the trampoline for entering a nested function. */
1285 #define TRAMPOLINE_SIZE 16
1287 /* Alignment required for a trampoline in units. */
1288 #define TRAMPOLINE_ALIGN 4
1290 /* Emit RTL insns to initialize the variable parts of a trampoline.
1291 FNADDR is an RTX for the address of the function's pure code.
1292 CXT is an RTX for the static chain value for the function. */
1293 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1295 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1297 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1302 /* Addressing modes, and classification of registers for them. */
1304 #define HAVE_POST_INCREMENT 1
1305 #define HAVE_PRE_INCREMENT 1
1306 #define HAVE_POST_DECREMENT 1
1307 #define HAVE_PRE_DECREMENT 1
1309 /* Macros to check register numbers against specific register classes. */
1311 /* These assume that REGNO is a hard or pseudo reg number.
1312 They give nonzero only if REGNO is a hard reg of the suitable class
1313 or a pseudo reg currently allocated to a suitable hard reg.
1314 Since they use reg_renumber, they are safe only once reg_renumber
1315 has been allocated, which happens in local-alloc.c.
1317 On the ARM, don't allow the pc to be used. */
1318 #define REGNO_OK_FOR_BASE_P(REGNO) \
1319 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1320 || (REGNO) == ARG_POINTER_REGNUM \
1321 || (unsigned) reg_renumber[(REGNO)] < 15 \
1322 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1323 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1324 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1325 REGNO_OK_FOR_BASE_P(REGNO)
1327 /* Maximum number of registers that can appear in a valid memory address.
1328 Shifts in addresses can't be by a register. */
1330 #define MAX_REGS_PER_ADDRESS 2
1332 /* Recognize any constant value that is a valid address. */
1333 /* XXX We can address any constant, eventually... */
1335 #ifdef AOF_ASSEMBLER
1337 #define CONSTANT_ADDRESS_P(X) \
1338 (GET_CODE (X) == SYMBOL_REF \
1339 && CONSTANT_POOL_ADDRESS_P (X))
1343 #define CONSTANT_ADDRESS_P(X) \
1344 (GET_CODE (X) == SYMBOL_REF \
1345 && (CONSTANT_POOL_ADDRESS_P (X) \
1346 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1348 #endif /* AOF_ASSEMBLER */
1350 /* Nonzero if the constant value X is a legitimate general operand.
1351 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1353 On the ARM, allow any integer (invalid ones are removed later by insn
1354 patterns), nice doubles and symbol_refs which refer to the function's
1355 constant pool XXX. */
1356 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1358 /* Symbols in the text segment can be accessed without indirecting via the
1359 constant pool; it may take an extra binary operation, but this is still
1360 faster than indirecting via memory. Don't do this when not optimizing,
1361 since we won't be calculating al of the offsets necessary to do this
1363 /* This doesn't work with AOF syntax, since the string table may be in
1364 a different AREA. */
1365 #ifndef AOF_ASSEMBLER
1366 #define ENCODE_SECTION_INFO(decl) \
1368 if (optimize > 0 && TREE_CONSTANT (decl) \
1369 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1371 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1372 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1373 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1378 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1379 and check its validity for a certain class.
1380 We have two alternate definitions for each of them.
1381 The usual definition accepts all pseudo regs; the other rejects
1382 them unless they have been allocated suitable hard regs.
1383 The symbol REG_OK_STRICT causes the latter definition to be used. */
1384 #ifndef REG_OK_STRICT
1386 /* Nonzero if X is a hard reg that can be used as a base reg
1387 or if it is a pseudo reg. */
1388 #define REG_OK_FOR_BASE_P(X) \
1389 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1390 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1392 /* Nonzero if X is a hard reg that can be used as an index
1393 or if it is a pseudo reg. */
1394 #define REG_OK_FOR_INDEX_P(X) \
1395 REG_OK_FOR_BASE_P(X)
1397 #define REG_OK_FOR_PRE_POST_P(X) \
1398 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1399 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1403 /* Nonzero if X is a hard reg that can be used as a base reg. */
1404 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1406 /* Nonzero if X is a hard reg that can be used as an index. */
1407 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1409 #define REG_OK_FOR_PRE_POST_P(X) \
1410 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1411 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1412 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1413 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1417 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1418 that is a valid memory address for an instruction.
1419 The MODE argument is the machine mode for the MEM expression
1420 that wants to use this address.
1422 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1423 #define BASE_REGISTER_RTX_P(X) \
1424 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1426 #define INDEX_REGISTER_RTX_P(X) \
1427 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1429 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1430 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1431 only be small constants. */
1432 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1435 HOST_WIDE_INT range; \
1436 enum rtx_code code = GET_CODE (INDEX); \
1438 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1440 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1441 && INTVAL (INDEX) > -1024 \
1442 && (INTVAL (INDEX) & 3) == 0) \
1447 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1449 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1450 && (! arm_arch4 || (MODE) != HImode)) \
1452 rtx xiop0 = XEXP (INDEX, 0); \
1453 rtx xiop1 = XEXP (INDEX, 1); \
1454 if (INDEX_REGISTER_RTX_P (xiop0) \
1455 && power_of_two_operand (xiop1, SImode)) \
1457 if (INDEX_REGISTER_RTX_P (xiop1) \
1458 && power_of_two_operand (xiop0, SImode)) \
1461 if (GET_MODE_SIZE (MODE) <= 4 \
1462 && (code == LSHIFTRT || code == ASHIFTRT \
1463 || code == ASHIFT || code == ROTATERT) \
1464 && (! arm_arch4 || (MODE) != HImode)) \
1466 rtx op = XEXP (INDEX, 1); \
1467 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1468 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1469 && INTVAL (op) <= 31) \
1472 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1473 range = ((MODE) == HImode || (MODE) == QImode) \
1474 ? (arm_arch4 ? 256 : 4095) : 4096; \
1475 if (code == CONST_INT && INTVAL (INDEX) < range \
1476 && INTVAL (INDEX) > -range) \
1481 /* Jump to LABEL if X is a valid address RTX. This must also take
1482 REG_OK_STRICT into account when deciding about valid registers, but it uses
1483 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1484 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1485 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1486 refs must be forced though a static cell to ensure addressability. */
1487 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1489 if (BASE_REGISTER_RTX_P (X)) \
1491 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1492 && GET_CODE (XEXP (X, 0)) == REG \
1493 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1495 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1496 && (GET_CODE (X) == LABEL_REF \
1497 || (GET_CODE (X) == CONST \
1498 && GET_CODE (XEXP ((X), 0)) == PLUS \
1499 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1500 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1502 else if ((MODE) == TImode) \
1504 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1506 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1507 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1509 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1510 if (val == 4 || val == -4 || val == -8) \
1514 else if (GET_CODE (X) == PLUS) \
1516 rtx xop0 = XEXP(X,0); \
1517 rtx xop1 = XEXP(X,1); \
1519 if (BASE_REGISTER_RTX_P (xop0)) \
1520 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1521 else if (BASE_REGISTER_RTX_P (xop1)) \
1522 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1524 /* Reload currently can't handle MINUS, so disable this for now */ \
1525 /* else if (GET_CODE (X) == MINUS) \
1527 rtx xop0 = XEXP (X,0); \
1528 rtx xop1 = XEXP (X,1); \
1530 if (BASE_REGISTER_RTX_P (xop0)) \
1531 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1533 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1534 && GET_CODE (X) == SYMBOL_REF \
1535 && CONSTANT_POOL_ADDRESS_P (X) \
1537 && symbol_mentioned_p (get_pool_constant (X)))) \
1539 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1540 && (GET_MODE_SIZE (MODE) <= 4) \
1541 && GET_CODE (XEXP (X, 0)) == REG \
1542 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1546 /* Try machine-dependent ways of modifying an illegitimate address
1547 to be legitimate. If we find one, return the new, valid address.
1548 This macro is used in only one place: `memory_address' in explow.c.
1550 OLDX is the address as it was before break_out_memory_refs was called.
1551 In some cases it is useful to look at this to decide what needs to be done.
1553 MODE and WIN are passed so that this macro can use
1554 GO_IF_LEGITIMATE_ADDRESS.
1556 It is always safe for this macro to do nothing. It exists to recognize
1557 opportunities to optimize the output.
1559 On the ARM, try to convert [REG, #BIGCONST]
1560 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1561 where VALIDCONST == 0 in case of TImode. */
1562 extern struct rtx_def *legitimize_pic_address ();
1563 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1565 if (GET_CODE (X) == PLUS) \
1567 rtx xop0 = XEXP (X, 0); \
1568 rtx xop1 = XEXP (X, 1); \
1570 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1571 xop0 = force_reg (SImode, xop0); \
1572 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1573 xop1 = force_reg (SImode, xop1); \
1574 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1576 HOST_WIDE_INT n, low_n; \
1577 rtx base_reg, val; \
1578 n = INTVAL (xop1); \
1580 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1592 low_n = ((MODE) == TImode ? 0 \
1593 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1596 base_reg = gen_reg_rtx (SImode); \
1597 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1598 GEN_INT (n)), NULL_RTX); \
1599 emit_move_insn (base_reg, val); \
1600 (X) = (low_n == 0 ? base_reg \
1601 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1603 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1604 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1606 else if (GET_CODE (X) == MINUS) \
1608 rtx xop0 = XEXP (X, 0); \
1609 rtx xop1 = XEXP (X, 1); \
1611 if (CONSTANT_P (xop0)) \
1612 xop0 = force_reg (SImode, xop0); \
1613 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1614 xop1 = force_reg (SImode, xop1); \
1615 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1616 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1619 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1620 if (memory_address_p (MODE, X)) \
1624 /* Go to LABEL if ADDR (a legitimate address expression)
1625 has an effect that depends on the machine mode it is used for. */
1626 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1628 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1629 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1633 /* Specify the machine mode that this machine uses
1634 for the index in the tablejump instruction. */
1635 #define CASE_VECTOR_MODE SImode
1637 /* Define as C expression which evaluates to nonzero if the tablejump
1638 instruction expects the table to contain offsets from the address of the
1640 Do not define this if the table should contain absolute addresses. */
1641 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1643 /* Specify the tree operation to be used to convert reals to integers. */
1644 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1646 /* This is the kind of divide that is easiest to do in the general case. */
1647 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1649 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1650 unsigned is probably best, but may break some code. */
1651 #ifndef DEFAULT_SIGNED_CHAR
1652 #define DEFAULT_SIGNED_CHAR 0
1655 /* Don't cse the address of the function being compiled. */
1656 #define NO_RECURSIVE_FUNCTION_CSE 1
1658 /* Max number of bytes we can move from memory to memory
1659 in one reasonably fast instruction. */
1662 /* Define if operations between registers always perform the operation
1663 on the full register even if a narrower mode is specified. */
1664 #define WORD_REGISTER_OPERATIONS
1666 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1667 will either zero-extend or sign-extend. The value of this macro should
1668 be the code that says which one of the two operations is implicitly
1669 done, NIL if none. */
1670 #define LOAD_EXTEND_OP(MODE) \
1671 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1672 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1674 /* Define this if zero-extension is slow (more than one real instruction).
1675 On the ARM, it is more than one instruction only if not fetching from
1677 /* #define SLOW_ZERO_EXTEND */
1679 /* Nonzero if access to memory by bytes is slow and undesirable. */
1680 #define SLOW_BYTE_ACCESS 0
1682 /* Immediate shift counts are truncated by the output routines (or was it
1683 the assembler?). Shift counts in a register are truncated by ARM. Note
1684 that the native compiler puts too large (> 32) immediate shift counts
1685 into a register and shifts by the register, letting the ARM decide what
1686 to do instead of doing that itself. */
1687 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1688 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1689 On the arm, Y in a register is used modulo 256 for the shift. Only for
1690 rotates is modulo 32 used. */
1691 /* #define SHIFT_COUNT_TRUNCATED 1 */
1693 /* All integers have the same format so truncation is easy. */
1694 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1696 /* Calling from registers is a massive pain. */
1697 #define NO_FUNCTION_CSE 1
1699 /* Chars and shorts should be passed as ints. */
1700 #define PROMOTE_PROTOTYPES 1
1702 /* The machine modes of pointers and functions */
1703 #define Pmode SImode
1704 #define FUNCTION_MODE Pmode
1706 /* The structure type of the machine dependent info field of insns
1707 No uses for this yet. */
1708 /* #define INSN_MACHINE_INFO struct machine_info */
1710 /* The relative costs of various types of constants. Note that cse.c defines
1711 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1712 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1714 if (const_ok_for_arm (INTVAL (RTX))) \
1715 return (OUTER_CODE) == SET ? 2 : -1; \
1716 else if (OUTER_CODE == AND \
1717 && const_ok_for_arm (~INTVAL (RTX))) \
1719 else if ((OUTER_CODE == COMPARE \
1720 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1721 && const_ok_for_arm (-INTVAL (RTX))) \
1729 case CONST_DOUBLE: \
1730 if (const_double_rtx_ok_for_fpu (RTX)) \
1731 return (OUTER_CODE) == SET ? 2 : -1; \
1732 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1733 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1737 #define ARM_FRAME_RTX(X) \
1738 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1739 || (X) == arg_pointer_rtx)
1741 #define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
1742 return arm_rtx_costs (X, CODE);
1744 /* Moves to and from memory are quite expensive */
1745 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1747 /* All address computations that can be done are free, but rtx cost returns
1748 the same for practically all of them. So we weight the different types
1749 of address here in the order (most pref first):
1750 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1751 #define ADDRESS_COST(X) \
1752 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1753 || GET_CODE (X) == SYMBOL_REF) \
1755 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1756 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1758 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1759 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1760 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1761 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1762 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1763 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1769 /* Try to generate sequences that don't involve branches, we can then use
1770 conditional instructions */
1771 #define BRANCH_COST 4
1773 /* A C statement to update the variable COST based on the relationship
1774 between INSN that is dependent on DEP through dependence LINK. */
1775 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1776 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1778 /* Position Independent Code. */
1779 /* We decide which register to use based on the compilation options and
1780 the assembler in use; this is more general than the APCS restriction of
1781 using sb (r9) all the time. */
1782 extern int arm_pic_register;
1784 /* The register number of the register used to address a table of static
1785 data addresses in memory. */
1786 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1788 #define FINALIZE_PIC arm_finalize_pic ()
1790 /* We can't directly access anything that contains a symbol,
1791 nor can we indirect via the constant pool. */
1792 #define LEGITIMATE_PIC_OPERAND_P(X) \
1793 (! symbol_mentioned_p (X) \
1794 && (! CONSTANT_POOL_ADDRESS_P (X) \
1795 || ! symbol_mentioned_p (get_pool_constant (X))))
1799 /* Condition code information. */
1800 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1801 return the mode to be used for the comparison.
1802 CCFPEmode should be used with floating inequalities,
1803 CCFPmode should be used with floating equalities.
1804 CC_NOOVmode should be used with SImode integer equalities.
1805 CC_Zmode should be used if only the Z flag is set correctly
1806 CCmode should be used otherwise. */
1808 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1809 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1810 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1811 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1813 #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \
1814 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \
1815 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C"
1817 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1819 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1821 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1824 if (GET_CODE (OP1) == CONST_INT \
1825 && ! (const_ok_for_arm (INTVAL (OP1)) \
1826 || (const_ok_for_arm (- INTVAL (OP1))))) \
1828 rtx const_op = OP1; \
1829 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1834 #define STORE_FLAG_VALUE 1
1836 /* Define the information needed to generate branch insns. This is
1837 stored from the compare operation. Note that we can't use "rtx" here
1838 since it hasn't been defined! */
1840 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1842 /* Define the codes that are matched by predicates in arm.c */
1843 #define PREDICATE_CODES \
1844 {"s_register_operand", {SUBREG, REG}}, \
1845 {"f_register_operand", {SUBREG, REG}}, \
1846 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1847 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1848 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1849 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1850 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1851 {"offsettable_memory_operand", {MEM}}, \
1852 {"bad_signed_byte_operand", {MEM}}, \
1853 {"alignable_memory_operand", {MEM}}, \
1854 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1855 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1856 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1857 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1858 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1859 {"load_multiple_operation", {PARALLEL}}, \
1860 {"store_multiple_operation", {PARALLEL}}, \
1861 {"equality_operator", {EQ, NE}}, \
1862 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1863 {"const_shift_operand", {CONST_INT}}, \
1864 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1865 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1866 {"multi_register_push", {PARALLEL}}, \
1867 {"cc_register", {REG}}, \
1868 {"dominant_cc_register", {REG}},
1872 /* Gcc puts the pool in the wrong place for ARM, since we can only
1873 load addresses a limited distance around the pc. We do some
1874 special munging to move the constant pool values to the correct
1875 point in the code. */
1876 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1878 /* The pool is empty, since we have moved everything into the code. */
1879 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1882 /* Output an internal label definition. */
1883 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1884 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1887 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1888 extern int arm_target_label, arm_ccfsm_state; \
1889 extern rtx arm_target_insn; \
1891 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1892 && !strcmp (PREFIX, "L")) \
1894 arm_ccfsm_state = 0; \
1895 arm_target_insn = NULL; \
1897 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1898 ASM_OUTPUT_LABEL (STREAM, s); \
1902 /* Output a push or a pop instruction (only used when profiling). */
1903 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1904 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1905 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1907 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1908 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1909 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1911 /* Target characters. */
1912 #define TARGET_BELL 007
1913 #define TARGET_BS 010
1914 #define TARGET_TAB 011
1915 #define TARGET_NEWLINE 012
1916 #define TARGET_VT 013
1917 #define TARGET_FF 014
1918 #define TARGET_CR 015
1920 /* Only perform branch elimination (by making instructions conditional) if
1921 we're optimising. Otherwise it's of no use anyway. */
1922 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1924 arm_final_prescan_insn (INSN)
1926 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1927 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1928 /* Output an operand of an instruction. */
1929 #define PRINT_OPERAND(STREAM, X, CODE) \
1930 arm_print_operand (STREAM, X, CODE)
1932 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1933 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1934 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1935 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1936 ? ((~ (HOST_WIDE_INT) 0) \
1937 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1940 /* Output the address of an operand. */
1941 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1943 int is_minus = GET_CODE (X) == MINUS; \
1945 if (GET_CODE (X) == REG) \
1946 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1947 reg_names[REGNO (X)]); \
1948 else if (GET_CODE (X) == PLUS || is_minus) \
1950 rtx base = XEXP (X, 0); \
1951 rtx index = XEXP (X, 1); \
1952 char * base_reg_name; \
1953 HOST_WIDE_INT offset = 0; \
1954 if (GET_CODE (base) != REG) \
1956 /* Ensure that BASE is a register (one of them must be). */ \
1961 base_reg_name = reg_names[REGNO (base)]; \
1962 switch (GET_CODE (index)) \
1965 offset = INTVAL (index); \
1968 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
1969 base_reg_name, offset); \
1973 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
1974 base_reg_name, is_minus ? "-" : "", \
1975 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1984 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1985 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
1986 reg_names[REGNO (XEXP (index, 0))]); \
1987 arm_print_operand (STREAM, index, 'S'); \
1988 fputs ("]", STREAM); \
1996 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1997 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1999 extern int output_memory_reference_mode; \
2001 if (GET_CODE (XEXP (X, 0)) != REG) \
2004 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2005 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
2006 reg_names[REGNO (XEXP (X, 0))], \
2007 GET_CODE (X) == PRE_DEC ? "-" : "", \
2008 GET_MODE_SIZE (output_memory_reference_mode)); \
2010 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
2011 reg_names[REGNO (XEXP (X, 0))], \
2012 GET_CODE (X) == POST_DEC ? "-" : "", \
2013 GET_MODE_SIZE (output_memory_reference_mode)); \
2015 else output_addr_const(STREAM, X); \
2018 /* Handles PIC addr specially */
2019 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2021 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
2023 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2024 fputs(" - (", STREAM); \
2025 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2026 fputs(")", STREAM); \
2028 else output_addr_const(STREAM, X); \
2031 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2032 Used for C++ multiple inheritance. */
2033 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2035 int mi_delta = (DELTA); \
2036 char *mi_op = mi_delta < 0 ? "sub" : "add"; \
2038 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2040 if (mi_delta < 0) mi_delta = -mi_delta; \
2041 while (mi_delta != 0) \
2043 if (mi_delta & (3 << shift) == 0) \
2047 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \
2048 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
2049 REGISTER_PREFIX, reg_names[this_regno], \
2050 mi_delta & (0xff << shift)); \
2051 mi_delta &= ~(0xff << shift); \
2055 fputs ("\tb\t", FILE); \
2056 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2057 fputc ('\n', FILE); \
2060 /* A C expression whose value is RTL representing the value of the return
2061 address for the frame COUNT steps up from the current frame. */
2063 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2065 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2068 /* Used to mask out junk bits from the return address, such as
2069 processor state, interrupt status, condition codes and the like. */
2070 #define MASK_RETURN_ADDR \
2071 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2072 in 26 bit mode, the condition codes must be masked out of the \
2073 return address. This does not apply to ARM6 and later processors \
2074 when running in 32 bit mode. */ \
2075 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2077 /* The remainder of this file is only needed for building the compiler
2078 itself, not for the collateral. */
2079 #ifdef HAVE_CONFIG_H
2081 /* Prototypes for functions in arm.c */
2083 #ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */
2084 #define STDIO_PROTO(ARGS) PROTO (ARGS)
2086 #define STDIO_PROTO(ARGS) ()
2091 #define Tree union tree_node *
2098 #define Rtx struct rtx_def *
2103 #ifndef HOST_WIDE_INT
2106 #define Hint HOST_WIDE_INT
2108 #ifndef HAVE_MACHINE_MODES
2109 #include "machmode.h"
2111 #define Mmode enum machine_mode
2114 #define RTX_CODE_PROTO(ARGS) PROTO (ARGS)
2116 #define RTX_CODE_PROTO(ARGS) ()
2118 #define Rcode enum rtx_code
2120 void arm_override_options PROTO ((void));
2121 int use_return_insn PROTO ((int));
2122 int const_ok_for_arm PROTO ((Hint));
2123 int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, Hint, Rtx, Rtx, int));
2124 Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
2125 int arm_return_in_memory PROTO ((Tree));
2126 int legitimate_pic_operand_p PROTO ((Rtx));
2127 Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
2128 int is_pic PROTO ((Rtx));
2129 void arm_finalize_pic PROTO ((void));
2130 int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
2131 int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
2132 int const_double_rtx_ok_for_fpu PROTO ((Rtx));
2133 int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx));
2134 int s_register_operand PROTO ((Rtx, Mmode));
2135 int f_register_operand PROTO ((Rtx, Mmode));
2136 int reg_or_int_operand PROTO ((Rtx, Mmode));
2137 int reload_memory_operand PROTO ((Rtx, Mmode));
2138 int arm_rhs_operand PROTO ((Rtx, Mmode));
2139 int arm_rhsm_operand PROTO ((Rtx, Mmode));
2140 int arm_add_operand PROTO ((Rtx, Mmode));
2141 int arm_not_operand PROTO ((Rtx, Mmode));
2142 int offsettable_memory_operand PROTO ((Rtx, Mmode));
2143 int alignable_memory_operand PROTO ((Rtx, Mmode));
2144 int bad_signed_byte_operand PROTO ((Rtx, Mmode));
2145 int fpu_rhs_operand PROTO ((Rtx, Mmode));
2146 int fpu_add_operand PROTO ((Rtx, Mmode));
2147 int power_of_two_operand PROTO ((Rtx, Mmode));
2148 int di_operand PROTO ((Rtx, Mmode));
2149 int soft_df_operand PROTO ((Rtx, Mmode));
2150 int index_operand PROTO ((Rtx, Mmode));
2151 int const_shift_operand PROTO ((Rtx, Mmode));
2152 int shiftable_operator PROTO ((Rtx, Mmode));
2153 int shift_operator PROTO ((Rtx, Mmode));
2154 int equality_operator PROTO ((Rtx, Mmode));
2155 int minmax_operator PROTO ((Rtx, Mmode));
2156 int cc_register PROTO ((Rtx, Mmode));
2157 int dominant_cc_register PROTO ((Rtx, Mmode));
2158 int symbol_mentioned_p PROTO ((Rtx));
2159 int label_mentioned_p PROTO ((Rtx));
2160 Rcode minmax_code PROTO ((Rtx));
2161 int adjacent_mem_locations PROTO ((Rtx, Rtx));
2162 int load_multiple_operation PROTO ((Rtx, Mmode));
2163 int store_multiple_operation PROTO ((Rtx, Mmode));
2164 int load_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
2165 char * emit_ldm_seq PROTO ((Rtx *, int));
2166 int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
2167 char * emit_stm_seq PROTO ((Rtx *, int));
2168 int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
2169 Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2170 Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2171 int arm_gen_movstrqi PROTO ((Rtx *));
2172 Rtx gen_rotated_half_load PROTO ((Rtx));
2173 Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx));
2174 Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int));
2175 void arm_reload_in_hi PROTO ((Rtx *));
2176 void arm_reload_out_hi PROTO ((Rtx *));
2177 void arm_reorg PROTO ((Rtx));
2178 char * fp_immediate_constant PROTO ((Rtx));
2179 void print_multi_reg STDIO_PROTO ((FILE *, char *, int, int));
2180 char * output_call PROTO ((Rtx *));
2181 char * output_call_mem PROTO ((Rtx *));
2182 char * output_mov_long_double_fpu_from_arm PROTO ((Rtx *));
2183 char * output_mov_long_double_arm_from_fpu PROTO ((Rtx *));
2184 char * output_mov_long_double_arm_from_arm PROTO ((Rtx *));
2185 char * output_mov_double_fpu_from_arm PROTO ((Rtx *));
2186 char * output_mov_double_arm_from_fpu PROTO ((Rtx *));
2187 char * output_move_double PROTO ((Rtx *));
2188 char * output_mov_immediate PROTO ((Rtx *));
2189 char * output_add_immediate PROTO ((Rtx *));
2190 char * arithmetic_instr PROTO ((Rtx, int));
2191 void output_ascii_pseudo_op STDIO_PROTO ((FILE *, unsigned char *, int));
2192 char * output_return_instruction PROTO ((Rtx, int, int));
2193 int arm_volatile_func PROTO ((void));
2194 void arm_poke_function_name STDIO_PROTO ((FILE *, char *));
2195 void output_func_prologue STDIO_PROTO ((FILE *, int));
2196 void output_func_epilogue STDIO_PROTO ((FILE *, int));
2197 void arm_expand_prologue PROTO ((void));
2198 void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int));
2199 void arm_final_prescan_insn PROTO ((Rtx));
2200 int short_branch PROTO ((int, int));
2201 void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */
2202 int multi_register_push PROTO ((Rtx, Mmode));
2203 #ifdef AOF_ASSEMBLER
2204 Rtx aof_pic_entry PROTO ((Rtx));
2205 void aof_dump_pic_table STDIO_PROTO ((FILE *));
2206 char * aof_text_section PROTO ((void));
2207 char * aof_data_section PROTO ((void));
2208 void aof_add_import PROTO ((char *));
2209 void aof_delete_import PROTO ((char *));
2210 void aof_dump_imports STDIO_PROTO ((FILE *));
2212 #endif /* HAVE_CONFIG_H */
2214 #endif /* __ARM_H__ */
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