1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define ("__arm__"); \
36 builtin_define ("__thumb__"); \
40 builtin_define ("__ARMEB__"); \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
48 builtin_define ("__ARMEL__"); \
50 builtin_define ("__THUMBEL__"); \
54 builtin_define ("__APCS_32__"); \
56 builtin_define ("__APCS_26__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 /* Configure didn't specify. */
100 #define TARGET_CPU_generic 0x8000
102 typedef enum arm_cond_code
104 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
105 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
109 extern arm_cc arm_current_cc;
111 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
113 extern int arm_target_label;
114 extern int arm_ccfsm_state;
115 extern GTY(()) rtx arm_target_insn;
116 /* Run-time compilation parameters selecting different hardware subsets. */
117 extern int target_flags;
118 /* The floating point instruction architecture, can be 2 or 3 */
119 extern const char * target_fp_name;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
137 /* If the configuration file doesn't specify the cpu, the subtarget may
138 override it. If it doesn't, then default to an ARM6. */
139 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
140 #undef TARGET_CPU_DEFAULT
142 #ifdef SUBTARGET_CPU_DEFAULT
143 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
145 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
149 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
150 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
152 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
153 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
155 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
156 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
158 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
159 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
162 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
164 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
165 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
167 Unrecognized value in TARGET_CPU_DEFAULT.
176 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
177 %{mapcs-32:%{mapcs-26: \
178 %e-mapcs-26 and -mapcs-32 may not be used together}} \
179 %{msoft-float:%{mhard-float: \
180 %e-msoft-float and -mhard_float may not be used together}} \
181 %{mbig-endian:%{mlittle-endian: \
182 %e-mbig-endian and -mlittle-endian may not be used together}}"
184 /* Set the architecture define -- if -march= is set, then it overrides
185 the -mcpu= setting. */
186 #define CPP_CPU_ARCH_SPEC "\
187 %{march=arm2:-D__ARM_ARCH_2__} \
188 %{march=arm250:-D__ARM_ARCH_2__} \
189 %{march=arm3:-D__ARM_ARCH_2__} \
190 %{march=arm6:-D__ARM_ARCH_3__} \
191 %{march=arm600:-D__ARM_ARCH_3__} \
192 %{march=arm610:-D__ARM_ARCH_3__} \
193 %{march=arm7:-D__ARM_ARCH_3__} \
194 %{march=arm700:-D__ARM_ARCH_3__} \
195 %{march=arm710:-D__ARM_ARCH_3__} \
196 %{march=arm720:-D__ARM_ARCH_3__} \
197 %{march=arm7100:-D__ARM_ARCH_3__} \
198 %{march=arm7500:-D__ARM_ARCH_3__} \
199 %{march=arm7500fe:-D__ARM_ARCH_3__} \
200 %{march=arm7m:-D__ARM_ARCH_3M__} \
201 %{march=arm7dm:-D__ARM_ARCH_3M__} \
202 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
203 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
204 %{march=arm8:-D__ARM_ARCH_4__} \
205 %{march=arm810:-D__ARM_ARCH_4__} \
206 %{march=arm9:-D__ARM_ARCH_4T__} \
207 %{march=arm920:-D__ARM_ARCH_4__} \
208 %{march=arm920t:-D__ARM_ARCH_4T__} \
209 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
210 %{march=strongarm:-D__ARM_ARCH_4__} \
211 %{march=strongarm110:-D__ARM_ARCH_4__} \
212 %{march=strongarm1100:-D__ARM_ARCH_4__} \
213 %{march=xscale:-D__ARM_ARCH_5TE__} \
214 %{march=xscale:-D__XSCALE__} \
215 %{march=armv2:-D__ARM_ARCH_2__} \
216 %{march=armv2a:-D__ARM_ARCH_2__} \
217 %{march=armv3:-D__ARM_ARCH_3__} \
218 %{march=armv3m:-D__ARM_ARCH_3M__} \
219 %{march=armv4:-D__ARM_ARCH_4__} \
220 %{march=armv4t:-D__ARM_ARCH_4T__} \
221 %{march=armv5:-D__ARM_ARCH_5__} \
222 %{march=armv5t:-D__ARM_ARCH_5T__} \
223 %{march=armv5e:-D__ARM_ARCH_5E__} \
224 %{march=armv5te:-D__ARM_ARCH_5TE__} \
226 %{mcpu=arm2:-D__ARM_ARCH_2__} \
227 %{mcpu=arm250:-D__ARM_ARCH_2__} \
228 %{mcpu=arm3:-D__ARM_ARCH_2__} \
229 %{mcpu=arm6:-D__ARM_ARCH_3__} \
230 %{mcpu=arm600:-D__ARM_ARCH_3__} \
231 %{mcpu=arm610:-D__ARM_ARCH_3__} \
232 %{mcpu=arm7:-D__ARM_ARCH_3__} \
233 %{mcpu=arm700:-D__ARM_ARCH_3__} \
234 %{mcpu=arm710:-D__ARM_ARCH_3__} \
235 %{mcpu=arm720:-D__ARM_ARCH_3__} \
236 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
237 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
238 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
239 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
240 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
241 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
242 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
243 %{mcpu=arm8:-D__ARM_ARCH_4__} \
244 %{mcpu=arm810:-D__ARM_ARCH_4__} \
245 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
246 %{mcpu=arm920:-D__ARM_ARCH_4__} \
247 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
248 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
249 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
250 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
251 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
252 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
253 %{mcpu=xscale:-D__XSCALE__} \
254 %{!mcpu*:%(cpp_cpu_arch_default)}} \
261 /* This macro defines names of additional specifications to put in the specs
262 that can be used in various specifications like CC1_SPEC. Its definition
263 is an initializer with a subgrouping for each command option.
265 Each subgrouping contains a string constant, that defines the
266 specification name, and a string constant that used by the GNU CC driver
269 Do not define this macro if it does not need to do anything. */
270 #define EXTRA_SPECS \
271 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
272 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
273 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
274 SUBTARGET_EXTRA_SPECS
276 #ifndef SUBTARGET_EXTRA_SPECS
277 #define SUBTARGET_EXTRA_SPECS
280 #ifndef SUBTARGET_CPP_SPEC
281 #define SUBTARGET_CPP_SPEC ""
284 /* Run-time Target Specification. */
285 #ifndef TARGET_VERSION
286 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
289 /* Nonzero if the function prologue (and epilogue) should obey
290 the ARM Procedure Call Standard. */
291 #define ARM_FLAG_APCS_FRAME (1 << 0)
293 /* Nonzero if the function prologue should output the function name to enable
294 the post mortem debugger to print a backtrace (very useful on RISCOS,
295 unused on RISCiX). Specifying this flag also enables
296 -fno-omit-frame-pointer.
297 XXX Must still be implemented in the prologue. */
298 #define ARM_FLAG_POKE (1 << 1)
300 /* Nonzero if floating point instructions are emulated by the FPE, in which
301 case instruction scheduling becomes very uninteresting. */
302 #define ARM_FLAG_FPE (1 << 2)
304 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
305 that assume restoration of the condition flags when returning from a
306 branch and link (ie a function). */
307 #define ARM_FLAG_APCS_32 (1 << 3)
309 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
311 /* Nonzero if stack checking should be performed on entry to each function
312 which allocates temporary variables on the stack. */
313 #define ARM_FLAG_APCS_STACK (1 << 4)
315 /* Nonzero if floating point parameters should be passed to functions in
316 floating point registers. */
317 #define ARM_FLAG_APCS_FLOAT (1 << 5)
319 /* Nonzero if re-entrant, position independent code should be generated.
320 This is equivalent to -fpic. */
321 #define ARM_FLAG_APCS_REENT (1 << 6)
323 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
324 be loaded using either LDRH or LDRB instructions. */
325 #define ARM_FLAG_MMU_TRAPS (1 << 7)
327 /* Nonzero if all floating point instructions are missing (and there is no
328 emulator either). Generate function calls for all ops in this case. */
329 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
331 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
332 #define ARM_FLAG_BIG_END (1 << 9)
334 /* Nonzero if we should compile for Thumb interworking. */
335 #define ARM_FLAG_INTERWORK (1 << 10)
337 /* Nonzero if we should have little-endian words even when compiling for
338 big-endian (for backwards compatibility with older versions of GCC). */
339 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
341 /* Nonzero if we need to protect the prolog from scheduling */
342 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
344 /* Nonzero if a call to abort should be generated if a noreturn
345 function tries to return. */
346 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
348 /* Nonzero if function prologues should not load the PIC register. */
349 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
351 /* Nonzero if all call instructions should be indirect. */
352 #define ARM_FLAG_LONG_CALLS (1 << 15)
354 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
355 #define ARM_FLAG_THUMB (1 << 16)
357 /* Set if a TPCS style stack frame should be generated, for non-leaf
358 functions, even if they do not need one. */
359 #define THUMB_FLAG_BACKTRACE (1 << 17)
361 /* Set if a TPCS style stack frame should be generated, for leaf
362 functions, even if they do not need one. */
363 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
365 /* Set if externally visible functions should assume that they
366 might be called in ARM mode, from a non-thumb aware code. */
367 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
369 /* Set if calls via function pointers should assume that their
370 destination is non-Thumb aware. */
371 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
373 /* Nonzero means target uses VFP FP. */
374 #define ARM_FLAG_VFP (1 << 21)
376 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
377 #define ARM_FLAG_ATPCS (1 << 22)
379 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
380 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
381 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
382 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
383 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
384 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
385 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
386 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
387 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
388 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
389 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
390 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
391 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
392 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
393 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
394 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
395 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
396 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
397 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
398 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
399 #define TARGET_ARM (! TARGET_THUMB)
400 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
401 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
402 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
403 #define TARGET_BACKTRACE (leaf_function_p () \
404 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
405 : (target_flags & THUMB_FLAG_BACKTRACE))
407 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
408 #ifndef SUBTARGET_SWITCHES
409 #define SUBTARGET_SWITCHES
412 #define TARGET_SWITCHES \
414 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
415 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
416 N_("Generate APCS conformant stack frames") }, \
417 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
418 {"poke-function-name", ARM_FLAG_POKE, \
419 N_("Store function names in object code") }, \
420 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
421 {"fpe", ARM_FLAG_FPE, "" }, \
422 {"apcs-32", ARM_FLAG_APCS_32, \
423 N_("Use the 32-bit version of the APCS") }, \
424 {"apcs-26", -ARM_FLAG_APCS_32, \
425 N_("Use the 26-bit version of the APCS") }, \
426 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
427 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
428 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
429 N_("Pass FP arguments in FP registers") }, \
430 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
431 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
432 N_("Generate re-entrant, PIC code") }, \
433 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
434 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
435 N_("The MMU will trap on unaligned accesses") }, \
436 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
437 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
438 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
439 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
440 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
441 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
442 N_("Use library calls to perform FP operations") }, \
443 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
444 N_("Use hardware floating point instructions") }, \
445 {"big-endian", ARM_FLAG_BIG_END, \
446 N_("Assume target CPU is configured as big endian") }, \
447 {"little-endian", -ARM_FLAG_BIG_END, \
448 N_("Assume target CPU is configured as little endian") }, \
449 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
450 N_("Assume big endian bytes, little endian words") }, \
451 {"thumb-interwork", ARM_FLAG_INTERWORK, \
452 N_("Support calls between Thumb and ARM instruction sets") }, \
453 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
454 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
455 N_("Generate a call to abort if a noreturn function returns")}, \
456 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
457 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
458 N_("Do not move instructions into a function's prologue") }, \
459 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
460 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
461 N_("Do not load the PIC register in function prologues") }, \
462 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
463 {"long-calls", ARM_FLAG_LONG_CALLS, \
464 N_("Generate call insns as indirect calls, if necessary") }, \
465 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
466 {"thumb", ARM_FLAG_THUMB, \
467 N_("Compile for the Thumb not the ARM") }, \
468 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
469 {"arm", -ARM_FLAG_THUMB, "" }, \
470 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
471 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
472 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
473 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
474 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
475 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
476 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
477 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
478 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
480 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
481 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
482 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
485 {"", TARGET_DEFAULT, "" } \
488 #define TARGET_OPTIONS \
490 {"cpu=", & arm_select[0].string, \
491 N_("Specify the name of the target CPU") }, \
492 {"arch=", & arm_select[1].string, \
493 N_("Specify the name of the target architecture") }, \
494 {"tune=", & arm_select[2].string, "" }, \
495 {"fpe=", & target_fp_name, "" }, \
496 {"fp=", & target_fp_name, \
497 N_("Specify the version of the floating point emulator") }, \
498 {"structure-size-boundary=", & structure_size_string, \
499 N_("Specify the minimum bit alignment of structures") }, \
500 {"pic-register=", & arm_pic_register_string, \
501 N_("Specify the register to be used for PIC addressing") } \
504 struct arm_cpu_select
508 const struct processors * processors;
511 /* This is a magic array. If the user specifies a command line switch
512 which matches one of the entries in TARGET_OPTIONS then the corresponding
513 string pointer will be set to the value specified by the user. */
514 extern struct arm_cpu_select arm_select[];
522 /* Recast the program mode class to be the prog_mode attribute */
523 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
525 extern enum prog_mode_type arm_prgmode;
527 /* What sort of floating point unit do we have? Hardware or software.
528 If software, is it issue 2 or issue 3? */
529 enum floating_point_type
536 /* Recast the floating point class to be the floating point attribute. */
537 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
539 /* What type of floating point to tune for */
540 extern enum floating_point_type arm_fpu;
542 /* What type of floating point instructions are available */
543 extern enum floating_point_type arm_fpu_arch;
545 /* Default floating point architecture. Override in sub-target if
548 #define FP_DEFAULT FP_SOFT2
551 /* Nonzero if the processor has a fast multiply insn, and one that does
552 a 64-bit multiply of two 32-bit values. */
553 extern int arm_fast_multiply;
555 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
556 extern int arm_arch4;
558 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
559 extern int arm_arch5;
561 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
562 extern int arm_arch5e;
564 /* Nonzero if this chip can benefit from load scheduling. */
565 extern int arm_ld_sched;
567 /* Nonzero if generating thumb code. */
568 extern int thumb_code;
570 /* Nonzero if this chip is a StrongARM. */
571 extern int arm_is_strong;
573 /* Nonzero if this chip is an XScale. */
574 extern int arm_is_xscale;
576 /* Nonzero if this chip is an ARM6 or an ARM7. */
577 extern int arm_is_6_or_7;
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
583 /* The frame pointer register used in gcc has nothing to do with debugging;
584 that is controlled by the APCS-FRAME option. */
585 #define CAN_DEBUG_WITHOUT_FP
587 #undef TARGET_MEM_FUNCTIONS
588 #define TARGET_MEM_FUNCTIONS 1
590 #define OVERRIDE_OPTIONS arm_override_options ()
592 /* Nonzero if PIC code requires explicit qualifiers to generate
593 PLT and GOT relocs rather than the assembler doing so implicitly.
594 Subtargets can override these if required. */
595 #ifndef NEED_GOT_RELOC
596 #define NEED_GOT_RELOC 0
598 #ifndef NEED_PLT_RELOC
599 #define NEED_PLT_RELOC 0
602 /* Nonzero if we need to refer to the GOT with a PC-relative
603 offset. In other words, generate
605 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
609 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
611 The default is true, which matches NetBSD. Subtargets can
612 override this if required. */
617 /* Target machine storage Layout. */
620 /* Define this macro if it is advisable to hold scalars in registers
621 in a wider mode than that declared by the program. In such cases,
622 the value is constrained to be within the bounds of the declared
623 type, but kept valid in the wider mode. The signedness of the
624 extension may differ from that of the type. */
626 /* It is far faster to zero extend chars than to sign extend them */
628 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
629 if (GET_MODE_CLASS (MODE) == MODE_INT \
630 && GET_MODE_SIZE (MODE) < 4) \
632 if (MODE == QImode) \
634 else if (MODE == HImode) \
635 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
639 /* Define this macro if the promotion described by `PROMOTE_MODE'
640 should also be done for outgoing function arguments. */
641 /* This is required to ensure that push insns always push a word. */
642 #define PROMOTE_FUNCTION_ARGS
645 I think I have added all the code to make this work. Unfortunately,
646 early releases of the floating point emulation code on RISCiX used a
647 different format for extended precision numbers. On my RISCiX box there
648 is a bug somewhere which causes the machine to lock up when running enquire
649 with long doubles. There is the additional aspect that Norcroft C
650 treats long doubles as doubles and we ought to remain compatible.
651 Perhaps someone with an FPA coprocessor and not running RISCiX would like
652 to try this someday. */
653 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
655 /* Disable XFmode patterns in md file */
656 #define ENABLE_XF_PATTERNS 0
658 /* Define this if most significant bit is lowest numbered
659 in instructions that operate on numbered bit-fields. */
660 #define BITS_BIG_ENDIAN 0
662 /* Define this if most significant byte of a word is the lowest numbered.
663 Most ARM processors are run in little endian mode, so that is the default.
664 If you want to have it run-time selectable, change the definition in a
665 cover file to be TARGET_BIG_ENDIAN. */
666 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
668 /* Define this if most significant word of a multiword number is the lowest
670 This is always false, even when in big-endian mode. */
671 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
673 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
674 on processor pre-defineds when compiling libgcc2.c. */
675 #if defined(__ARMEB__) && !defined(__ARMWEL__)
676 #define LIBGCC2_WORDS_BIG_ENDIAN 1
678 #define LIBGCC2_WORDS_BIG_ENDIAN 0
681 /* Define this if most significant word of doubles is the lowest numbered.
682 The rules are different based on whether or not we use FPA-format or
683 VFP-format doubles. */
684 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
686 #define UNITS_PER_WORD 4
688 #define PARM_BOUNDARY 32
690 #define STACK_BOUNDARY 32
692 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
694 #define FUNCTION_BOUNDARY 32
696 /* The lowest bit is used to indicate Thumb-mode functions, so the
697 vbit must go into the delta field of pointers to member
699 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
701 #define EMPTY_FIELD_BOUNDARY 32
703 #define BIGGEST_ALIGNMENT 32
705 /* Make strings word-aligned so strcpy from constants will be faster. */
706 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
708 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
709 ((TREE_CODE (EXP) == STRING_CST \
710 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
711 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
713 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
714 value set in previous versions of this toolchain was 8, which produces more
715 compact structures. The command line option -mstructure_size_boundary=<n>
716 can be used to change this value. For compatibility with the ARM SDK
717 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
718 0020D) page 2-20 says "Structures are aligned on word boundaries". */
719 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
720 extern int arm_structure_size_boundary;
722 /* This is the value used to initialize arm_structure_size_boundary. If a
723 particular arm target wants to change the default value it should change
724 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
725 for an example of this. */
726 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
727 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
730 /* Used when parsing command line option -mstructure_size_boundary. */
731 extern const char * structure_size_string;
733 /* Nonzero if move instructions will actually fail to work
734 when given unaligned data. */
735 #define STRICT_ALIGNMENT 1
737 /* Standard register usage. */
739 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
740 (S - saved over call).
742 r0 * argument word/integer result
745 r4-r8 S register variable
746 r9 S (rfp) register variable (real frame pointer)
748 r10 F S (sl) stack limit (used by -mapcs-stack-check)
749 r11 F S (fp) argument pointer
750 r12 (ip) temp workspace
751 r13 F S (sp) lower end of current stack frame
752 r14 (lr) link address/workspace
753 r15 F (pc) program counter
755 f0 floating point result
756 f1-f3 floating point scratch
758 f4-f7 S floating point variable
760 cc This is NOT a real register, but is used internally
761 to represent things that use or set the condition
763 sfp This isn't either. It is used during rtl generation
764 since the offset between the frame pointer and the
765 auto's isn't known until after register allocation.
766 afp Nor this, we only need this because of non-local
767 goto. Without it fp appears to be used and the
768 elimination code won't get rid of sfp. It tracks
769 fp exactly at all times.
771 *: See CONDITIONAL_REGISTER_USAGE */
773 /* The stack backtrace structure is as follows:
774 fp points to here: | save code pointer | [fp]
775 | return link value | [fp, #-4]
776 | return sp value | [fp, #-8]
777 | return fp value | [fp, #-12]
778 [| saved r10 value |]
789 [| saved f7 value |] three words
790 [| saved f6 value |] three words
791 [| saved f5 value |] three words
792 [| saved f4 value |] three words
793 r0-r3 are not normally saved in a C function. */
795 /* 1 for registers that have pervasive standard uses
796 and are not available for the register allocator. */
797 #define FIXED_REGISTERS \
805 /* 1 for registers not available across function calls.
806 These must include the FIXED_REGISTERS and also any
807 registers that can be used without being saved.
808 The latter must include the registers where values are returned
809 and the register where structure-value addresses are passed.
810 Aside from that, you can include as many other registers as you like.
811 The CC is not preserved over function calls on the ARM 6, so it is
812 easier to assume this for all. SFP is preserved, since FP is. */
813 #define CALL_USED_REGISTERS \
821 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
822 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
825 #define CONDITIONAL_REGISTER_USAGE \
829 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
831 for (regno = FIRST_ARM_FP_REGNUM; \
832 regno <= LAST_ARM_FP_REGNUM; ++regno) \
833 fixed_regs[regno] = call_used_regs[regno] = 1; \
835 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
837 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
838 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
840 else if (TARGET_APCS_STACK) \
842 fixed_regs[10] = 1; \
843 call_used_regs[10] = 1; \
845 if (TARGET_APCS_FRAME) \
847 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
848 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
850 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
853 /* These are a couple of extensions to the formats accecpted
855 %@ prints out ASM_COMMENT_START
856 %r prints out REGISTER_PREFIX reg_names[arg] */
857 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
859 fputs (ASM_COMMENT_START, FILE); \
863 fputs (REGISTER_PREFIX, FILE); \
864 fputs (reg_names [va_arg (ARGS, int)], FILE); \
867 /* Round X up to the nearest word. */
868 #define ROUND_UP(X) (((X) + 3) & ~3)
870 /* Convert fron bytes to ints. */
871 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
873 /* The number of (integer) registers required to hold a quantity of type MODE. */
874 #define ARM_NUM_REGS(MODE) \
875 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
877 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
878 #define ARM_NUM_REGS2(MODE, TYPE) \
879 ARM_NUM_INTS ((MODE) == BLKmode ? \
880 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
882 /* The number of (integer) argument register available. */
883 #define NUM_ARG_REGS 4
885 /* Return the regiser number of the N'th (integer) argument. */
886 #define ARG_REGISTER(N) (N - 1)
888 #if 0 /* FIXME: The ARM backend has special code to handle structure
889 returns, and will reserve its own hidden first argument. So
890 if this macro is enabled a *second* hidden argument will be
891 reserved, which will break binary compatibility with old
892 toolchains and also thunk handling. One day this should be
894 /* RTX for structure returns. NULL means use a hidden first argument. */
895 #define STRUCT_VALUE 0
897 /* Register in which address to store a structure value
898 is passed to a function. */
899 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
902 /* Specify the registers used for certain standard purposes.
903 The values of these macros are register numbers. */
905 /* The number of the last argument register. */
906 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
908 /* The number of the last "lo" register (thumb). */
909 #define LAST_LO_REGNUM 7
911 /* The register that holds the return address in exception handlers. */
912 #define EXCEPTION_LR_REGNUM 2
914 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
915 as an invisible last argument (possible since varargs don't exist in
916 Pascal), so the following is not true. */
917 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
919 /* Define this to be where the real frame pointer is if it is not possible to
920 work out the offset between the frame pointer and the automatic variables
921 until after register allocation has taken place. FRAME_POINTER_REGNUM
922 should point to a special register that we will make sure is eliminated.
924 For the Thumb we have another problem. The TPCS defines the frame pointer
925 as r11, and GCC belives that it is always possible to use the frame pointer
926 as base register for addressing purposes. (See comments in
927 find_reloads_address()). But - the Thumb does not allow high registers,
928 including r11, to be used as base address registers. Hence our problem.
930 The solution used here, and in the old thumb port is to use r7 instead of
931 r11 as the hard frame pointer and to have special code to generate
932 backtrace structures on the stack (if required to do so via a command line
933 option) using r11. This is the only 'user visable' use of r11 as a frame
935 #define ARM_HARD_FRAME_POINTER_REGNUM 11
936 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
938 #define HARD_FRAME_POINTER_REGNUM \
940 ? ARM_HARD_FRAME_POINTER_REGNUM \
941 : THUMB_HARD_FRAME_POINTER_REGNUM)
943 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
945 /* Register to use for pushing function arguments. */
946 #define STACK_POINTER_REGNUM SP_REGNUM
948 /* ARM floating pointer registers. */
949 #define FIRST_ARM_FP_REGNUM 16
950 #define LAST_ARM_FP_REGNUM 23
952 /* Base register for access to local variables of the function. */
953 #define FRAME_POINTER_REGNUM 25
955 /* Base register for access to arguments of the function. */
956 #define ARG_POINTER_REGNUM 26
958 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
959 #define FIRST_PSEUDO_REGISTER 27
961 /* Value should be nonzero if functions must have frame pointers.
962 Zero means the frame pointer need not be set up (and parms may be accessed
963 via the stack pointer) in functions that seem suitable.
964 If we have to have a frame pointer we might as well make use of it.
965 APCS says that the frame pointer does not need to be pushed in leaf
966 functions, or simple tail call functions. */
967 #define FRAME_POINTER_REQUIRED \
968 (current_function_has_nonlocal_label \
969 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
971 /* Return number of consecutive hard regs needed starting at reg REGNO
972 to hold something of mode MODE.
973 This is ordinarily the length in words of a value of mode MODE
974 but can be less for certain modes in special long registers.
976 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
978 #define HARD_REGNO_NREGS(REGNO, MODE) \
980 && REGNO >= FIRST_ARM_FP_REGNUM \
981 && REGNO != FRAME_POINTER_REGNUM \
982 && REGNO != ARG_POINTER_REGNUM) \
983 ? 1 : ARM_NUM_REGS (MODE))
985 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
986 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
987 arm_hard_regno_mode_ok ((REGNO), (MODE))
989 /* Value is 1 if it is a good idea to tie two pseudo registers
990 when one has mode MODE1 and one has mode MODE2.
991 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
992 for any hard reg, then this must be 0 for correct output. */
993 #define MODES_TIEABLE_P(MODE1, MODE2) \
994 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
996 /* The order in which register should be allocated. It is good to use ip
997 since no saving is required (though calls clobber it) and it never contains
998 function parameters. It is quite good to use lr since other calls may
999 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1000 least likely to contain a function parameter; in addition results are
1002 #define REG_ALLOC_ORDER \
1004 3, 2, 1, 0, 12, 14, 4, 5, \
1005 6, 7, 8, 10, 9, 11, 13, 15, \
1006 16, 17, 18, 19, 20, 21, 22, 23, \
1010 /* Interrupt functions can only use registers that have already been
1011 saved by the prologue, even if they would normally be
1013 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1014 (! IS_INTERRUPT (cfun->machine->func_type) || \
1015 regs_ever_live[DST])
1017 /* Register and constant classes. */
1019 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1020 Now that the Thumb is involved it has become more complicated. */
1035 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1037 /* Give names of register classes as strings for dump file. */
1038 #define REG_CLASS_NAMES \
1051 /* Define which registers fit in which classes.
1052 This is an initializer for a vector of HARD_REG_SET
1053 of length N_REG_CLASSES. */
1054 #define REG_CLASS_CONTENTS \
1056 { 0x0000000 }, /* NO_REGS */ \
1057 { 0x0FF0000 }, /* FPU_REGS */ \
1058 { 0x00000FF }, /* LO_REGS */ \
1059 { 0x0002000 }, /* STACK_REG */ \
1060 { 0x00020FF }, /* BASE_REGS */ \
1061 { 0x000FF00 }, /* HI_REGS */ \
1062 { 0x1000000 }, /* CC_REG */ \
1063 { 0x200FFFF }, /* GENERAL_REGS */ \
1064 { 0x2FFFFFF } /* ALL_REGS */ \
1067 /* The same information, inverted:
1068 Return the class number of the smallest class containing
1069 reg number REGNO. This could be a conditional expression
1070 or could index an array. */
1071 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1073 /* The class value for index registers, and the one for base regs. */
1074 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1075 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1077 /* For the Thumb the high registers cannot be used as base registers
1078 when addressing quanitities in QI or HI mode; if we don't know the
1079 mode, then we must be conservative. After reload we must also be
1080 conservative, since we can't support SP+reg addressing, and we
1081 can't fix up any bad substitutions. */
1082 #define MODE_BASE_REG_CLASS(MODE) \
1083 (TARGET_ARM ? GENERAL_REGS : \
1084 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1086 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1087 registers explicitly used in the rtl to be used as spill registers
1088 but prevents the compiler from extending the lifetime of these
1090 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1092 /* Get reg_class from a letter such as appears in the machine description.
1093 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1094 ARM, but several more letters for the Thumb. */
1095 #define REG_CLASS_FROM_LETTER(C) \
1096 ( (C) == 'f' ? FPU_REGS \
1097 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1098 : TARGET_ARM ? NO_REGS \
1099 : (C) == 'h' ? HI_REGS \
1100 : (C) == 'b' ? BASE_REGS \
1101 : (C) == 'k' ? STACK_REG \
1102 : (C) == 'c' ? CC_REG \
1105 /* The letters I, J, K, L and M in a register constraint string
1106 can be used to stand for particular ranges of immediate operands.
1107 This macro defines what the ranges are.
1108 C is the letter, and VALUE is a constant value.
1109 Return 1 if VALUE is in the range specified by C.
1110 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1111 J: valid indexing constants.
1112 K: ~value ok in rhs argument of data operand.
1113 L: -value ok in rhs argument of data operand.
1114 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1115 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1116 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1117 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1118 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1119 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1120 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1121 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1124 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1125 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1126 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1127 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1128 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1129 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1130 && ((VAL) & 3) == 0) : \
1131 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1132 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1135 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1137 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1139 /* Constant letter 'G' for the FPU immediate constants.
1140 'H' means the same constant negated. */
1141 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1142 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1143 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1145 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1147 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1149 /* For the ARM, `Q' means that this is a memory operand that is just
1150 an offset from a register.
1151 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1152 address. This means that the symbol is in the text segment and can be
1153 accessed without using a load. */
1155 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1156 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1157 (C) == 'R' ? (GET_CODE (OP) == MEM \
1158 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1159 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1160 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1163 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1164 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1165 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1167 #define EXTRA_CONSTRAINT(X, C) \
1169 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1171 /* Given an rtx X being reloaded into a reg required to be
1172 in class CLASS, return the class of reg to actually use.
1173 In general this is just CLASS, but for the Thumb we prefer
1174 a LO_REGS class or a subset. */
1175 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1176 (TARGET_ARM ? (CLASS) : \
1177 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1179 /* Must leave BASE_REGS reloads alone */
1180 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1181 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1182 ? ((true_regnum (X) == -1 ? LO_REGS \
1183 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1187 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1188 ((CLASS) != LO_REGS \
1189 ? ((true_regnum (X) == -1 ? LO_REGS \
1190 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1194 /* Return the register class of a scratch register needed to copy IN into
1195 or out of a register in CLASS in MODE. If it can be done directly,
1196 NO_REGS is returned. */
1197 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1199 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1200 ? GENERAL_REGS : NO_REGS) \
1201 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1203 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1204 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1206 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1207 && (GET_CODE (X) == MEM \
1208 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1209 && true_regnum (X) == -1))) \
1210 ? GENERAL_REGS : NO_REGS) \
1211 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1213 /* Try a machine-dependent way of reloading an illegitimate address
1214 operand. If we find one, push the reload and jump to WIN. This
1215 macro is used in only one place: `find_reloads_address' in reload.c.
1217 For the ARM, we wish to handle large displacements off a base
1218 register by splitting the addend across a MOV and the mem insn.
1219 This can cut the number of reloads needed. */
1220 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1223 if (GET_CODE (X) == PLUS \
1224 && GET_CODE (XEXP (X, 0)) == REG \
1225 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1226 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1227 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1229 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1230 HOST_WIDE_INT low, high; \
1232 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1233 low = ((val & 0xf) ^ 0x8) - 0x8; \
1234 else if (MODE == SImode \
1235 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1236 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1237 /* Need to be careful, -4096 is not a valid offset. */ \
1238 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1239 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1240 /* Need to be careful, -256 is not a valid offset. */ \
1241 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1242 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1243 && TARGET_HARD_FLOAT) \
1244 /* Need to be careful, -1024 is not a valid offset. */ \
1245 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1249 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1250 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1251 - (unsigned HOST_WIDE_INT) 0x80000000); \
1252 /* Check for overflow or zero */ \
1253 if (low == 0 || high == 0 || (high + low != val)) \
1256 /* Reload the high part into a base reg; leave the low part \
1258 X = gen_rtx_PLUS (GET_MODE (X), \
1259 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1262 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1263 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1264 VOIDmode, 0, 0, OPNUM, TYPE); \
1270 /* ??? If an HImode FP+large_offset address is converted to an HImode
1271 SP+large_offset address, then reload won't know how to fix it. It sees
1272 only that SP isn't valid for HImode, and so reloads the SP into an index
1273 register, but the resulting address is still invalid because the offset
1274 is too big. We fix it here instead by reloading the entire address. */
1275 /* We could probably achieve better results by defining PROMOTE_MODE to help
1276 cope with the variances between the Thumb's signed and unsigned byte and
1277 halfword load instructions. */
1278 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1280 if (GET_CODE (X) == PLUS \
1281 && GET_MODE_SIZE (MODE) < 4 \
1282 && GET_CODE (XEXP (X, 0)) == REG \
1283 && XEXP (X, 0) == stack_pointer_rtx \
1284 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1285 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1289 push_reload (orig_X, NULL_RTX, &X, NULL, \
1290 MODE_BASE_REG_CLASS (MODE), \
1291 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1296 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1298 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1300 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1302 /* Return the maximum number of consecutive registers
1303 needed to represent mode MODE in a register of class CLASS.
1304 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1305 #define CLASS_MAX_NREGS(CLASS, MODE) \
1306 ((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE))
1308 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1309 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1311 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1312 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1314 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1316 /* Stack layout; function entry, exit and calling. */
1318 /* Define this if pushing a word on the stack
1319 makes the stack pointer a smaller address. */
1320 #define STACK_GROWS_DOWNWARD 1
1322 /* Define this if the nominal address of the stack frame
1323 is at the high-address end of the local variables;
1324 that is, each additional local variable allocated
1325 goes at a more negative offset in the frame. */
1326 #define FRAME_GROWS_DOWNWARD 1
1328 /* Offset within stack frame to start allocating local variables at.
1329 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1330 first local allocated. Otherwise, it is the offset to the BEGINNING
1331 of the first local allocated. */
1332 #define STARTING_FRAME_OFFSET 0
1334 /* If we generate an insn to push BYTES bytes,
1335 this says how many the stack pointer really advances by. */
1336 /* The push insns do not do this rounding implicitly.
1337 So don't define this. */
1338 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1340 /* Define this if the maximum size of all the outgoing args is to be
1341 accumulated and pushed during the prologue. The amount can be
1342 found in the variable current_function_outgoing_args_size. */
1343 #define ACCUMULATE_OUTGOING_ARGS 1
1345 /* Offset of first parameter from the argument pointer register value. */
1346 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1348 /* Value is the number of byte of arguments automatically
1349 popped when returning from a subroutine call.
1350 FUNDECL is the declaration node of the function (as a tree),
1351 FUNTYPE is the data type of the function (as a tree),
1352 or for a library call it is an identifier node for the subroutine name.
1353 SIZE is the number of bytes of arguments passed on the stack.
1355 On the ARM, the caller does not pop any of its arguments that were passed
1357 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1359 /* Define how to find the value returned by a library function
1360 assuming the value has mode MODE. */
1361 #define LIBCALL_VALUE(MODE) \
1362 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1363 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1364 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1366 /* Define how to find the value returned by a function.
1367 VALTYPE is the data type of the value (as a tree).
1368 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1369 otherwise, FUNC is 0. */
1370 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1371 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1373 /* 1 if N is a possible register number for a function value.
1374 On the ARM, only r0 and f0 can return results. */
1375 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1376 ((REGNO) == ARG_REGISTER (1) \
1377 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1379 /* How large values are returned */
1380 /* A C expression which can inhibit the returning of certain function values
1381 in registers, based on the type of value. */
1382 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1384 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1385 values must be in memory. On the ARM, they need only do so if larger
1386 than a word, or if they contain elements offset from zero in the struct. */
1387 #define DEFAULT_PCC_STRUCT_RETURN 0
1389 /* Flags for the call/call_value rtl operations set up by function_arg. */
1390 #define CALL_NORMAL 0x00000000 /* No special processing. */
1391 #define CALL_LONG 0x00000001 /* Always call indirect. */
1392 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1394 /* These bits describe the different types of function supported
1395 by the ARM backend. They are exclusive. ie a function cannot be both a
1396 normal function and an interworked function, for example. Knowing the
1397 type of a function is important for determining its prologue and
1399 Note value 7 is currently unassigned. Also note that the interrupt
1400 function types all have bit 2 set, so that they can be tested for easily.
1401 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1402 machine_function structure is initialized (to zero) func_type will
1403 default to unknown. This will force the first use of arm_current_func_type
1404 to call arm_compute_func_type. */
1405 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1406 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1407 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1408 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1409 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1410 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1411 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1413 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1415 /* In addition functions can have several type modifiers,
1416 outlined by these bit masks: */
1417 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1418 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1419 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1420 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1422 /* Some macros to test these flags. */
1423 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1424 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1425 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1426 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1427 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1429 /* A C structure for machine-specific, per-function data.
1430 This is added to the cfun structure. */
1431 typedef struct machine_function GTY(())
1433 /* Additionsl stack adjustment in __builtin_eh_throw. */
1434 rtx eh_epilogue_sp_ofs;
1435 /* Records if LR has to be saved for far jumps. */
1437 /* Records if ARG_POINTER was ever live. */
1438 int arg_pointer_live;
1439 /* Records if the save of LR has been eliminated. */
1440 int lr_save_eliminated;
1441 /* The size of the stack frame. Only valid after reload. */
1443 /* Records the type of the current function. */
1444 unsigned long func_type;
1445 /* Record if the function has a variable argument list. */
1446 int uses_anonymous_args;
1450 /* A C type for declaring a variable that is used as the first argument of
1451 `FUNCTION_ARG' and other related values. For some target machines, the
1452 type `int' suffices and can hold the number of bytes of argument so far. */
1455 /* This is the number of registers of arguments scanned so far. */
1457 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1461 /* Define where to put the arguments to a function.
1462 Value is zero to push the argument on the stack,
1463 or a hard register in which to store the argument.
1465 MODE is the argument's machine mode.
1466 TYPE is the data type of the argument (as a tree).
1467 This is null for libcalls where that information may
1469 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1470 the preceding args and about the function being called.
1471 NAMED is nonzero if this argument is a named parameter
1472 (otherwise it is an extra parameter matching an ellipsis).
1474 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1475 other arguments are passed on the stack. If (NAMED == 0) (which happens
1476 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1477 passed in the stack (function_prologue will indeed make it pass in the
1478 stack if necessary). */
1479 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1480 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1482 /* For an arg passed partly in registers and partly in memory,
1483 this is the number of registers used.
1484 For args passed entirely in registers or entirely in memory, zero. */
1485 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1486 ( NUM_ARG_REGS > (CUM).nregs \
1487 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1488 ? NUM_ARG_REGS - (CUM).nregs : 0)
1490 /* A C expression that indicates when an argument must be passed by
1491 reference. If nonzero for an argument, a copy of that argument is
1492 made in memory and a pointer to the argument is passed instead of
1493 the argument itself. The pointer is passed in whatever way is
1494 appropriate for passing a pointer to that type. */
1495 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1496 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1498 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1499 for a call to a function whose data type is FNTYPE.
1500 For a library call, FNTYPE is 0.
1501 On the ARM, the offset starts at 0. */
1502 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1503 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1505 /* Update the data in CUM to advance over an argument
1506 of mode MODE and data type TYPE.
1507 (TYPE is null for libcalls where that information may not be available.) */
1508 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1509 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1511 /* 1 if N is a possible register number for function argument passing.
1512 On the ARM, r0-r3 are used to pass args. */
1513 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1515 /* Implement `va_arg'. */
1516 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1517 arm_va_arg (valist, type)
1522 /* A C expression that evaluates to true if it is ok to perform a sibling
1524 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1526 /* Perform any actions needed for a function that is receiving a variable
1527 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1528 of the current parameter. PRETEND_SIZE is a variable that should be set to
1529 the amount of stack that must be pushed by the prolog to pretend that our
1532 Normally, this macro will push all remaining incoming registers on the
1533 stack and set PRETEND_SIZE to the length of the registers pushed.
1535 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1536 named arg and all anonymous args onto the stack.
1537 XXX I know the prologue shouldn't be pushing registers, but it is faster
1539 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1541 cfun->machine->uses_anonymous_args = 1; \
1542 if ((CUM).nregs < NUM_ARG_REGS) \
1543 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1546 /* If your target environment doesn't prefix user functions with an
1547 underscore, you may wish to re-define this to prevent any conflicts.
1548 e.g. AOF may prefix mcount with an underscore. */
1549 #ifndef ARM_MCOUNT_NAME
1550 #define ARM_MCOUNT_NAME "*mcount"
1553 /* Call the function profiler with a given profile label. The Acorn
1554 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1555 On the ARM the full profile code will look like:
1564 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1565 will output the .text section.
1567 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1568 ``prof'' doesn't seem to mind about this!
1570 Note - this version of the code is designed to work in both ARM and
1572 #ifndef ARM_FUNCTION_PROFILER
1573 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1578 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1579 IP_REGNUM, LR_REGNUM); \
1580 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1581 fputc ('\n', STREAM); \
1582 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1583 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1584 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1588 #ifdef THUMB_FUNCTION_PROFILER
1589 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1591 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1593 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1595 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1596 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1599 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1600 the stack pointer does not matter. The value is tested only in
1601 functions that have frame pointers.
1602 No definition is equivalent to always zero.
1604 On the ARM, the function epilogue recovers the stack pointer from the
1606 #define EXIT_IGNORE_STACK 1
1608 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1610 /* Determine if the epilogue should be output as RTL.
1611 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1612 #define USE_RETURN_INSN(ISCOND) \
1613 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1615 /* Definitions for register eliminations.
1617 This is an array of structures. Each structure initializes one pair
1618 of eliminable registers. The "from" register number is given first,
1619 followed by "to". Eliminations of the same "from" register are listed
1620 in order of preference.
1622 We have two registers that can be eliminated on the ARM. First, the
1623 arg pointer register can often be eliminated in favor of the stack
1624 pointer register. Secondly, the pseudo frame pointer register can always
1625 be eliminated; it is replaced with either the stack or the real frame
1626 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1627 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1629 #define ELIMINABLE_REGS \
1630 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1631 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1632 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1633 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1634 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1635 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1636 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1638 /* Given FROM and TO register numbers, say whether this elimination is
1639 allowed. Frame pointer elimination is automatically handled.
1641 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1642 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1643 pointer, we must eliminate FRAME_POINTER_REGNUM into
1644 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1645 ARG_POINTER_REGNUM. */
1646 #define CAN_ELIMINATE(FROM, TO) \
1647 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1648 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1649 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1650 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1653 #define THUMB_REG_PUSHED_P(reg) \
1654 (regs_ever_live [reg] \
1655 && (! call_used_regs [reg] \
1656 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1657 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1659 /* Define the offset between two registers, one to be eliminated, and the
1660 other its replacement, at the start of a routine. */
1661 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1664 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1668 /* Note: This macro must match the code in thumb_function_prologue(). */
1669 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1672 if ((FROM) == ARG_POINTER_REGNUM) \
1674 int count_regs = 0; \
1676 for (regno = 8; regno < 13; regno ++) \
1677 if (THUMB_REG_PUSHED_P (regno)) \
1680 (OFFSET) += 4 * count_regs; \
1682 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1683 if (THUMB_REG_PUSHED_P (regno)) \
1685 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1686 (OFFSET) += 4 * (count_regs + 1); \
1687 if (TARGET_BACKTRACE) \
1689 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1695 if ((TO) == STACK_POINTER_REGNUM) \
1697 (OFFSET) += current_function_outgoing_args_size; \
1698 (OFFSET) += thumb_get_frame_size (); \
1702 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1704 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1706 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1708 /* Special case handling of the location of arguments passed on the stack. */
1709 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1711 /* Initialize data used by insn expanders. This is called from insn_emit,
1712 once for every function before code is generated. */
1713 #define INIT_EXPANDERS arm_init_expanders ()
1715 /* Output assembler code for a block containing the constant parts
1716 of a trampoline, leaving space for the variable parts.
1718 On the ARM, (if r8 is the static chain regnum, and remembering that
1719 referencing pc adds an offset of 8) the trampoline looks like:
1722 .word static chain value
1723 .word function's address
1724 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1725 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1727 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1728 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1729 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1730 PC_REGNUM, PC_REGNUM); \
1731 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1732 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1735 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1736 Why - because it is easier. This code will always be branched to via
1737 a BX instruction and since the compiler magically generates the address
1738 of the function the linker has no opportunity to ensure that the
1739 bottom bit is set. Thus the processor will be in ARM mode when it
1740 reaches this code. So we duplicate the ARM trampoline code and add
1741 a switch into Thumb mode as well. */
1742 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1744 fprintf (FILE, "\t.code 32\n"); \
1745 fprintf (FILE, ".Ltrampoline_start:\n"); \
1746 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1747 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1748 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1749 IP_REGNUM, PC_REGNUM); \
1750 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1751 IP_REGNUM, IP_REGNUM); \
1752 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1753 fprintf (FILE, "\t.word\t0\n"); \
1754 fprintf (FILE, "\t.word\t0\n"); \
1755 fprintf (FILE, "\t.code 16\n"); \
1758 #define TRAMPOLINE_TEMPLATE(FILE) \
1760 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1762 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1764 /* Length in units of the trampoline for entering a nested function. */
1765 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1767 /* Alignment required for a trampoline in bits. */
1768 #define TRAMPOLINE_ALIGNMENT 32
1770 /* Emit RTL insns to initialize the variable parts of a trampoline.
1771 FNADDR is an RTX for the address of the function's pure code.
1772 CXT is an RTX for the static chain value for the function. */
1773 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1776 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1778 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1782 /* Addressing modes, and classification of registers for them. */
1783 #define HAVE_POST_INCREMENT 1
1784 #define HAVE_PRE_INCREMENT TARGET_ARM
1785 #define HAVE_POST_DECREMENT TARGET_ARM
1786 #define HAVE_PRE_DECREMENT TARGET_ARM
1788 /* Macros to check register numbers against specific register classes. */
1790 /* These assume that REGNO is a hard or pseudo reg number.
1791 They give nonzero only if REGNO is a hard reg of the suitable class
1792 or a pseudo reg currently allocated to a suitable hard reg.
1793 Since they use reg_renumber, they are safe only once reg_renumber
1794 has been allocated, which happens in local-alloc.c. */
1795 #define TEST_REGNO(R, TEST, VALUE) \
1796 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1798 /* On the ARM, don't allow the pc to be used. */
1799 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1800 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1801 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1802 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1804 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1805 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1806 || (GET_MODE_SIZE (MODE) >= 4 \
1807 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1809 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1811 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1812 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1814 /* For ARM code, we don't care about the mode, but for Thumb, the index
1815 must be suitable for use in a QImode load. */
1816 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1817 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1819 /* Maximum number of registers that can appear in a valid memory address.
1820 Shifts in addresses can't be by a register. */
1821 #define MAX_REGS_PER_ADDRESS 2
1823 /* Recognize any constant value that is a valid address. */
1824 /* XXX We can address any constant, eventually... */
1826 #ifdef AOF_ASSEMBLER
1828 #define CONSTANT_ADDRESS_P(X) \
1829 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1833 #define CONSTANT_ADDRESS_P(X) \
1834 (GET_CODE (X) == SYMBOL_REF \
1835 && (CONSTANT_POOL_ADDRESS_P (X) \
1836 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1838 #endif /* AOF_ASSEMBLER */
1840 /* Nonzero if the constant value X is a legitimate general operand.
1841 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1843 On the ARM, allow any integer (invalid ones are removed later by insn
1844 patterns), nice doubles and symbol_refs which refer to the function's
1847 When generating pic allow anything. */
1848 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1850 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1851 ( GET_CODE (X) == CONST_INT \
1852 || GET_CODE (X) == CONST_DOUBLE \
1853 || CONSTANT_ADDRESS_P (X) \
1856 #define LEGITIMATE_CONSTANT_P(X) \
1857 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1859 /* Special characters prefixed to function names
1860 in order to encode attribute like information.
1861 Note, '@' and '*' have already been taken. */
1862 #define SHORT_CALL_FLAG_CHAR '^'
1863 #define LONG_CALL_FLAG_CHAR '#'
1865 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1866 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1868 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1869 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1871 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1872 #define SUBTARGET_NAME_ENCODING_LENGTHS
1875 /* This is a C fragement for the inside of a switch statement.
1876 Each case label should return the number of characters to
1877 be stripped from the start of a function's name, if that
1878 name starts with the indicated character. */
1879 #define ARM_NAME_ENCODING_LENGTHS \
1880 case SHORT_CALL_FLAG_CHAR: return 1; \
1881 case LONG_CALL_FLAG_CHAR: return 1; \
1882 case '*': return 1; \
1883 SUBTARGET_NAME_ENCODING_LENGTHS
1885 /* This is how to output a reference to a user-level label named NAME.
1886 `assemble_name' uses this. */
1887 #undef ASM_OUTPUT_LABELREF
1888 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1889 arm_asm_output_labelref (FILE, NAME)
1891 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1892 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1894 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1895 and check its validity for a certain class.
1896 We have two alternate definitions for each of them.
1897 The usual definition accepts all pseudo regs; the other rejects
1898 them unless they have been allocated suitable hard regs.
1899 The symbol REG_OK_STRICT causes the latter definition to be used. */
1900 #ifndef REG_OK_STRICT
1902 #define ARM_REG_OK_FOR_BASE_P(X) \
1903 (REGNO (X) <= LAST_ARM_REGNUM \
1904 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1905 || REGNO (X) == FRAME_POINTER_REGNUM \
1906 || REGNO (X) == ARG_POINTER_REGNUM)
1908 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1909 (REGNO (X) <= LAST_LO_REGNUM \
1910 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1911 || (GET_MODE_SIZE (MODE) >= 4 \
1912 && (REGNO (X) == STACK_POINTER_REGNUM \
1913 || (X) == hard_frame_pointer_rtx \
1914 || (X) == arg_pointer_rtx)))
1916 #else /* REG_OK_STRICT */
1918 #define ARM_REG_OK_FOR_BASE_P(X) \
1919 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1921 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1922 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1924 #endif /* REG_OK_STRICT */
1926 /* Now define some helpers in terms of the above. */
1928 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1930 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1931 : ARM_REG_OK_FOR_BASE_P (X))
1933 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1935 /* For Thumb, a valid index register is anything that can be used in
1936 a byte load instruction. */
1937 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1939 /* Nonzero if X is a hard reg that can be used as an index
1940 or if it is a pseudo reg. On the Thumb, the stack pointer
1942 #define REG_OK_FOR_INDEX_P(X) \
1944 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1945 : ARM_REG_OK_FOR_INDEX_P (X))
1948 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1949 that is a valid memory address for an instruction.
1950 The MODE argument is the machine mode for the MEM expression
1951 that wants to use this address.
1953 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1955 /* --------------------------------arm version----------------------------- */
1956 #define ARM_BASE_REGISTER_RTX_P(X) \
1957 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1959 #define ARM_INDEX_REGISTER_RTX_P(X) \
1960 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1962 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1963 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1964 only be small constants. */
1965 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1968 HOST_WIDE_INT range; \
1969 enum rtx_code code = GET_CODE (INDEX); \
1971 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1973 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1974 && INTVAL (INDEX) > -1024 \
1975 && (INTVAL (INDEX) & 3) == 0) \
1980 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
1981 && GET_MODE_SIZE (MODE) <= 4) \
1983 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1984 && (! arm_arch4 || (MODE) != HImode)) \
1986 rtx xiop0 = XEXP (INDEX, 0); \
1987 rtx xiop1 = XEXP (INDEX, 1); \
1988 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
1989 && power_of_two_operand (xiop1, SImode)) \
1991 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
1992 && power_of_two_operand (xiop0, SImode)) \
1995 if (GET_MODE_SIZE (MODE) <= 4 \
1996 && (code == LSHIFTRT || code == ASHIFTRT \
1997 || code == ASHIFT || code == ROTATERT) \
1998 && (! arm_arch4 || (MODE) != HImode)) \
2000 rtx op = XEXP (INDEX, 1); \
2001 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2002 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2003 && INTVAL (op) <= 31) \
2006 /* NASTY: Since this limits the addressing of unsigned \
2008 range = ((MODE) == HImode || (MODE) == QImode) \
2009 ? (arm_arch4 ? 256 : 4095) : 4096; \
2010 if (code == CONST_INT && INTVAL (INDEX) < range \
2011 && INTVAL (INDEX) > -range) \
2017 /* Jump to LABEL if X is a valid address RTX. This must take
2018 REG_OK_STRICT into account when deciding about valid registers.
2020 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2021 floating SYMBOL_REF to the constant pool. Allow REG-only and
2022 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2023 forced though a static cell to ensure addressability. */
2024 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2026 if (ARM_BASE_REGISTER_RTX_P (X)) \
2028 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2029 && GET_CODE (XEXP (X, 0)) == REG \
2030 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2032 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2033 && (GET_CODE (X) == LABEL_REF \
2034 || (GET_CODE (X) == CONST \
2035 && GET_CODE (XEXP ((X), 0)) == PLUS \
2036 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2037 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2039 else if ((MODE) == TImode) \
2041 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2043 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2044 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2046 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2047 if (val == 4 || val == -4 || val == -8) \
2051 else if (GET_CODE (X) == PLUS) \
2053 rtx xop0 = XEXP (X, 0); \
2054 rtx xop1 = XEXP (X, 1); \
2056 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2057 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2058 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2059 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2061 /* Reload currently can't handle MINUS, so disable this for now */ \
2062 /* else if (GET_CODE (X) == MINUS) \
2064 rtx xop0 = XEXP (X,0); \
2065 rtx xop1 = XEXP (X,1); \
2067 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2068 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2070 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2071 && GET_CODE (X) == SYMBOL_REF \
2072 && CONSTANT_POOL_ADDRESS_P (X) \
2074 && symbol_mentioned_p (get_pool_constant (X)))) \
2076 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2077 && (GET_MODE_SIZE (MODE) <= 4) \
2078 && GET_CODE (XEXP (X, 0)) == REG \
2079 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2083 /* ---------------------thumb version----------------------------------*/
2084 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2085 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2086 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2087 && ((VAL) & 1) == 0) \
2088 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2089 && ((VAL) & 3) == 0))
2091 /* The AP may be eliminated to either the SP or the FP, so we use the
2092 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2094 /* ??? Verify whether the above is the right approach. */
2096 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2097 needs special handling also. */
2099 /* ??? Look at how the mips16 port solves this problem. It probably uses
2100 better ways to solve some of these problems. */
2102 /* Although it is not incorrect, we don't accept QImode and HImode
2103 addresses based on the frame pointer or arg pointer until the
2104 reload pass starts. This is so that eliminating such addresses
2105 into stack based ones won't produce impossible code. */
2106 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2108 /* ??? Not clear if this is right. Experiment. */ \
2109 if (GET_MODE_SIZE (MODE) < 4 \
2110 && ! (reload_in_progress || reload_completed) \
2111 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2112 || reg_mentioned_p (arg_pointer_rtx, X) \
2113 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2114 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2115 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2116 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2118 /* Accept any base register. SP only in SImode or larger. */ \
2119 else if (GET_CODE (X) == REG \
2120 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2122 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2123 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2124 && GET_CODE (X) == SYMBOL_REF \
2125 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2127 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2128 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2129 && (GET_CODE (X) == LABEL_REF \
2130 || (GET_CODE (X) == CONST \
2131 && GET_CODE (XEXP (X, 0)) == PLUS \
2132 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2133 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2135 /* Post-inc indexing only supported for SImode and larger. */ \
2136 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2137 && GET_CODE (XEXP (X, 0)) == REG \
2138 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2140 else if (GET_CODE (X) == PLUS) \
2142 /* REG+REG address can be any two index registers. */ \
2143 /* We disallow FRAME+REG addressing since we know that FRAME \
2144 will be replaced with STACK, and SP relative addressing only \
2145 permits SP+OFFSET. */ \
2146 if (GET_MODE_SIZE (MODE) <= 4 \
2147 && GET_CODE (XEXP (X, 0)) == REG \
2148 && GET_CODE (XEXP (X, 1)) == REG \
2149 && XEXP (X, 0) != frame_pointer_rtx \
2150 && XEXP (X, 1) != frame_pointer_rtx \
2151 && XEXP (X, 0) != virtual_stack_vars_rtx \
2152 && XEXP (X, 1) != virtual_stack_vars_rtx \
2153 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2154 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2156 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2157 else if (GET_CODE (XEXP (X, 0)) == REG \
2158 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2159 || XEXP (X, 0) == arg_pointer_rtx) \
2160 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2161 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2163 /* REG+const has 10 bit offset for SP, but only SImode and \
2164 larger is supported. */ \
2165 /* ??? Should probably check for DI/DFmode overflow here \
2166 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2167 else if (GET_CODE (XEXP (X, 0)) == REG \
2168 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2169 && GET_MODE_SIZE (MODE) >= 4 \
2170 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2171 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2172 + GET_MODE_SIZE (MODE)) <= 1024 \
2173 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2175 else if (GET_CODE (XEXP (X, 0)) == REG \
2176 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2177 && GET_MODE_SIZE (MODE) >= 4 \
2178 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2179 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2182 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2183 && GET_CODE (X) == SYMBOL_REF \
2184 && CONSTANT_POOL_ADDRESS_P (X) \
2186 && symbol_mentioned_p (get_pool_constant (X)))) \
2190 /* ------------------------------------------------------------------- */
2191 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2193 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2194 else /* if (TARGET_THUMB) */ \
2195 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2196 /* ------------------------------------------------------------------- */
2198 /* Try machine-dependent ways of modifying an illegitimate address
2199 to be legitimate. If we find one, return the new, valid address.
2200 This macro is used in only one place: `memory_address' in explow.c.
2202 OLDX is the address as it was before break_out_memory_refs was called.
2203 In some cases it is useful to look at this to decide what needs to be done.
2205 MODE and WIN are passed so that this macro can use
2206 GO_IF_LEGITIMATE_ADDRESS.
2208 It is always safe for this macro to do nothing. It exists to recognize
2209 opportunities to optimize the output.
2211 On the ARM, try to convert [REG, #BIGCONST]
2212 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2213 where VALIDCONST == 0 in case of TImode. */
2214 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2216 if (GET_CODE (X) == PLUS) \
2218 rtx xop0 = XEXP (X, 0); \
2219 rtx xop1 = XEXP (X, 1); \
2221 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2222 xop0 = force_reg (SImode, xop0); \
2223 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2224 xop1 = force_reg (SImode, xop1); \
2225 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2226 && GET_CODE (xop1) == CONST_INT) \
2228 HOST_WIDE_INT n, low_n; \
2229 rtx base_reg, val; \
2230 n = INTVAL (xop1); \
2232 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2244 low_n = ((MODE) == TImode ? 0 \
2245 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2248 base_reg = gen_reg_rtx (SImode); \
2249 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2250 GEN_INT (n)), NULL_RTX); \
2251 emit_move_insn (base_reg, val); \
2252 (X) = (low_n == 0 ? base_reg \
2253 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2255 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2256 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2258 else if (GET_CODE (X) == MINUS) \
2260 rtx xop0 = XEXP (X, 0); \
2261 rtx xop1 = XEXP (X, 1); \
2263 if (CONSTANT_P (xop0)) \
2264 xop0 = force_reg (SImode, xop0); \
2265 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2266 xop1 = force_reg (SImode, xop1); \
2267 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2268 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2271 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2272 if (memory_address_p (MODE, X)) \
2276 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2278 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2280 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2282 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2284 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2286 /* Go to LABEL if ADDR (a legitimate address expression)
2287 has an effect that depends on the machine mode it is used for. */
2288 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2290 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2291 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2295 /* Nothing helpful to do for the Thumb */
2296 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2298 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2301 /* Specify the machine mode that this machine uses
2302 for the index in the tablejump instruction. */
2303 #define CASE_VECTOR_MODE Pmode
2305 /* Define as C expression which evaluates to nonzero if the tablejump
2306 instruction expects the table to contain offsets from the address of the
2308 Do not define this if the table should contain absolute addresses. */
2309 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2311 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2312 unsigned is probably best, but may break some code. */
2313 #ifndef DEFAULT_SIGNED_CHAR
2314 #define DEFAULT_SIGNED_CHAR 0
2317 /* Don't cse the address of the function being compiled. */
2318 #define NO_RECURSIVE_FUNCTION_CSE 1
2320 /* Max number of bytes we can move from memory to memory
2321 in one reasonably fast instruction. */
2325 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2327 /* Define if operations between registers always perform the operation
2328 on the full register even if a narrower mode is specified. */
2329 #define WORD_REGISTER_OPERATIONS
2331 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2332 will either zero-extend or sign-extend. The value of this macro should
2333 be the code that says which one of the two operations is implicitly
2334 done, NIL if none. */
2335 #define LOAD_EXTEND_OP(MODE) \
2336 (TARGET_THUMB ? ZERO_EXTEND : \
2337 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2338 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2340 /* Nonzero if access to memory by bytes is slow and undesirable. */
2341 #define SLOW_BYTE_ACCESS 0
2343 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2345 /* Immediate shift counts are truncated by the output routines (or was it
2346 the assembler?). Shift counts in a register are truncated by ARM. Note
2347 that the native compiler puts too large (> 32) immediate shift counts
2348 into a register and shifts by the register, letting the ARM decide what
2349 to do instead of doing that itself. */
2350 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2351 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2352 On the arm, Y in a register is used modulo 256 for the shift. Only for
2353 rotates is modulo 32 used. */
2354 /* #define SHIFT_COUNT_TRUNCATED 1 */
2356 /* All integers have the same format so truncation is easy. */
2357 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2359 /* Calling from registers is a massive pain. */
2360 #define NO_FUNCTION_CSE 1
2362 /* Chars and shorts should be passed as ints. */
2363 #define PROMOTE_PROTOTYPES 1
2365 /* The machine modes of pointers and functions */
2366 #define Pmode SImode
2367 #define FUNCTION_MODE Pmode
2369 #define ARM_FRAME_RTX(X) \
2370 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2371 || (X) == arg_pointer_rtx)
2373 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2374 return arm_rtx_costs (X, CODE, OUTER_CODE);
2376 /* Moves to and from memory are quite expensive */
2377 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2378 (TARGET_ARM ? 10 : \
2379 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2380 * (CLASS == LO_REGS ? 1 : 2)))
2382 /* All address computations that can be done are free, but rtx cost returns
2383 the same for practically all of them. So we weight the different types
2384 of address here in the order (most pref first):
2385 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2386 #define ARM_ADDRESS_COST(X) \
2387 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2388 || GET_CODE (X) == SYMBOL_REF) \
2390 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2391 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2393 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2394 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2395 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2396 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2397 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2398 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2402 #define THUMB_ADDRESS_COST(X) \
2403 ((GET_CODE (X) == REG \
2404 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2405 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2408 #define ADDRESS_COST(X) \
2409 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2411 /* Try to generate sequences that don't involve branches, we can then use
2412 conditional instructions */
2413 #define BRANCH_COST \
2414 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2416 /* Position Independent Code. */
2417 /* We decide which register to use based on the compilation options and
2418 the assembler in use; this is more general than the APCS restriction of
2419 using sb (r9) all the time. */
2420 extern int arm_pic_register;
2422 /* Used when parsing command line option -mpic-register=. */
2423 extern const char * arm_pic_register_string;
2425 /* The register number of the register used to address a table of static
2426 data addresses in memory. */
2427 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2429 #define FINALIZE_PIC arm_finalize_pic (1)
2431 /* We can't directly access anything that contains a symbol,
2432 nor can we indirect via the constant pool. */
2433 #define LEGITIMATE_PIC_OPERAND_P(X) \
2434 (!(symbol_mentioned_p (X) \
2435 || label_mentioned_p (X) \
2436 || (GET_CODE (X) == SYMBOL_REF \
2437 && CONSTANT_POOL_ADDRESS_P (X) \
2438 && (symbol_mentioned_p (get_pool_constant (X)) \
2439 || label_mentioned_p (get_pool_constant (X))))))
2441 /* We need to know when we are making a constant pool; this determines
2442 whether data needs to be in the GOT or can be referenced via a GOT
2444 extern int making_const_table;
2446 /* Handle pragmas for compatibility with Intel's compilers. */
2447 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2448 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2449 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2450 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2453 /* Condition code information. */
2454 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2455 return the mode to be used for the comparison. */
2457 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2459 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2461 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2464 if (GET_CODE (OP1) == CONST_INT \
2465 && ! (const_ok_for_arm (INTVAL (OP1)) \
2466 || (const_ok_for_arm (- INTVAL (OP1))))) \
2468 rtx const_op = OP1; \
2469 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2475 #define STORE_FLAG_VALUE 1
2479 /* Gcc puts the pool in the wrong place for ARM, since we can only
2480 load addresses a limited distance around the pc. We do some
2481 special munging to move the constant pool values to the correct
2482 point in the code. */
2483 #define MACHINE_DEPENDENT_REORG(INSN) \
2487 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2489 /* Output an internal label definition. */
2490 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2491 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2494 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2496 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2497 && !strcmp (PREFIX, "L")) \
2499 arm_ccfsm_state = 0; \
2500 arm_target_insn = NULL; \
2502 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2503 ASM_OUTPUT_LABEL (STREAM, s); \
2508 /* Output a push or a pop instruction (only used when profiling). */
2509 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2511 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2512 STACK_POINTER_REGNUM, REGNO); \
2514 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2517 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2519 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2520 STACK_POINTER_REGNUM, REGNO); \
2522 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2524 /* This is how to output a label which precedes a jumptable. Since
2525 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2526 #undef ASM_OUTPUT_CASE_LABEL
2527 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2531 ASM_OUTPUT_ALIGN (FILE, 2); \
2532 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2536 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2541 if (is_called_in_ARM_mode (DECL)) \
2542 fprintf (STREAM, "\t.code 32\n") ; \
2544 fprintf (STREAM, "\t.thumb_func\n") ; \
2546 if (TARGET_POKE_FUNCTION_NAME) \
2547 arm_poke_function_name (STREAM, (char *) NAME); \
2551 /* For aliases of functions we use .thumb_set instead. */
2552 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2555 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2556 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2558 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2560 fprintf (FILE, "\t.thumb_set "); \
2561 assemble_name (FILE, LABEL1); \
2562 fprintf (FILE, ","); \
2563 assemble_name (FILE, LABEL2); \
2564 fprintf (FILE, "\n"); \
2567 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2571 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2572 /* To support -falign-* switches we need to use .p2align so
2573 that alignment directives in code sections will be padded
2574 with no-op instructions, rather than zeroes. */
2575 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2578 if ((MAX_SKIP) == 0) \
2579 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2581 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2582 (LOG), (MAX_SKIP)); \
2586 /* Only perform branch elimination (by making instructions conditional) if
2587 we're optimising. Otherwise it's of no use anyway. */
2588 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2589 if (TARGET_ARM && optimize) \
2590 arm_final_prescan_insn (INSN); \
2591 else if (TARGET_THUMB) \
2592 thumb_final_prescan_insn (INSN)
2594 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2595 (CODE == '@' || CODE == '|' \
2596 || (TARGET_ARM && (CODE == '?')) \
2597 || (TARGET_THUMB && (CODE == '_')))
2599 /* Output an operand of an instruction. */
2600 #define PRINT_OPERAND(STREAM, X, CODE) \
2601 arm_print_operand (STREAM, X, CODE)
2603 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2604 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2605 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2606 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2607 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2608 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2611 /* Output the address of an operand. */
2612 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2614 int is_minus = GET_CODE (X) == MINUS; \
2616 if (GET_CODE (X) == REG) \
2617 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2618 else if (GET_CODE (X) == PLUS || is_minus) \
2620 rtx base = XEXP (X, 0); \
2621 rtx index = XEXP (X, 1); \
2622 HOST_WIDE_INT offset = 0; \
2623 if (GET_CODE (base) != REG) \
2625 /* Ensure that BASE is a register */ \
2626 /* (one of them must be). */ \
2631 switch (GET_CODE (index)) \
2634 offset = INTVAL (index); \
2637 asm_fprintf (STREAM, "[%r, #%d]", \
2638 REGNO (base), offset); \
2642 asm_fprintf (STREAM, "[%r, %s%r]", \
2643 REGNO (base), is_minus ? "-" : "", \
2653 asm_fprintf (STREAM, "[%r, %s%r", \
2654 REGNO (base), is_minus ? "-" : "", \
2655 REGNO (XEXP (index, 0))); \
2656 arm_print_operand (STREAM, index, 'S'); \
2657 fputs ("]", STREAM); \
2665 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2666 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2668 extern int output_memory_reference_mode; \
2670 if (GET_CODE (XEXP (X, 0)) != REG) \
2673 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2674 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2675 REGNO (XEXP (X, 0)), \
2676 GET_CODE (X) == PRE_DEC ? "-" : "", \
2677 GET_MODE_SIZE (output_memory_reference_mode));\
2679 asm_fprintf (STREAM, "[%r], #%s%d", \
2680 REGNO (XEXP (X, 0)), \
2681 GET_CODE (X) == POST_DEC ? "-" : "", \
2682 GET_MODE_SIZE (output_memory_reference_mode));\
2684 else output_addr_const (STREAM, X); \
2687 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2689 if (GET_CODE (X) == REG) \
2690 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2691 else if (GET_CODE (X) == POST_INC) \
2692 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2693 else if (GET_CODE (X) == PLUS) \
2695 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2696 asm_fprintf (STREAM, "[%r, #%d]", \
2697 REGNO (XEXP (X, 0)), \
2698 (int) INTVAL (XEXP (X, 1))); \
2700 asm_fprintf (STREAM, "[%r, %r]", \
2701 REGNO (XEXP (X, 0)), \
2702 REGNO (XEXP (X, 1))); \
2705 output_addr_const (STREAM, X); \
2708 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2710 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2712 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2714 /* A C expression whose value is RTL representing the value of the return
2715 address for the frame COUNT steps up from the current frame. */
2717 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2718 arm_return_addr (COUNT, FRAME)
2720 /* Mask of the bits in the PC that contain the real return address
2721 when running in 26-bit mode. */
2722 #define RETURN_ADDR_MASK26 (0x03fffffc)
2724 /* Pick up the return address upon entry to a procedure. Used for
2725 dwarf2 unwind information. This also enables the table driven
2727 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2728 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2730 /* Used to mask out junk bits from the return address, such as
2731 processor state, interrupt status, condition codes and the like. */
2732 #define MASK_RETURN_ADDR \
2733 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2734 in 26 bit mode, the condition codes must be masked out of the \
2735 return address. This does not apply to ARM6 and later processors \
2736 when running in 32 bit mode. */ \
2737 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2738 : (arm_arch4 || TARGET_THUMB) ? \
2739 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2740 : arm_gen_return_addr_mask ())
2743 /* Define the codes that are matched by predicates in arm.c */
2744 #define PREDICATE_CODES \
2745 {"s_register_operand", {SUBREG, REG}}, \
2746 {"arm_hard_register_operand", {REG}}, \
2747 {"f_register_operand", {SUBREG, REG}}, \
2748 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2749 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2750 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2751 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2752 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2753 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2754 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2755 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2756 {"offsettable_memory_operand", {MEM}}, \
2757 {"bad_signed_byte_operand", {MEM}}, \
2758 {"alignable_memory_operand", {MEM}}, \
2759 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2760 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2761 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2762 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2763 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2764 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2765 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2766 {"load_multiple_operation", {PARALLEL}}, \
2767 {"store_multiple_operation", {PARALLEL}}, \
2768 {"equality_operator", {EQ, NE}}, \
2769 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2770 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2772 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2773 {"const_shift_operand", {CONST_INT}}, \
2774 {"multi_register_push", {PARALLEL}}, \
2775 {"cc_register", {REG}}, \
2776 {"logical_binary_operator", {AND, IOR, XOR}}, \
2777 {"dominant_cc_register", {REG}},
2779 /* Define this if you have special predicates that know special things
2780 about modes. Genrecog will warn about certain forms of
2781 match_operand without a mode; if the operand predicate is listed in
2782 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2783 #define SPECIAL_MODE_PREDICATES \
2784 "cc_register", "dominant_cc_register",
2791 #endif /* ! GCC_ARM_H */
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