1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify */
52 #define TARGET_CPU_generic 0x8000
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
108 Unrecognized value in TARGET_CPU_DEFAULT.
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm720:-D__ARM_ARCH_3__} \
136 %{march=arm7100:-D__ARM_ARCH_3__} \
137 %{march=arm7500:-D__ARM_ARCH_3__} \
138 %{march=arm7500fe:-D__ARM_ARCH_3__} \
139 %{march=arm7m:-D__ARM_ARCH_3M__} \
140 %{march=arm7dm:-D__ARM_ARCH_3M__} \
141 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
142 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
143 %{march=arm8:-D__ARM_ARCH_4__} \
144 %{march=arm810:-D__ARM_ARCH_4__} \
145 %{march=arm9:-D__ARM_ARCH_4T__} \
146 %{march=arm920:-D__ARM_ARCH_4__} \
147 %{march=arm920t:-D__ARM_ARCH_4T__} \
148 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
149 %{march=strongarm:-D__ARM_ARCH_4__} \
150 %{march=strongarm110:-D__ARM_ARCH_4__} \
151 %{march=strongarm1100:-D__ARM_ARCH_4__} \
152 %{march=armv2:-D__ARM_ARCH_2__} \
153 %{march=armv2a:-D__ARM_ARCH_2__} \
154 %{march=armv3:-D__ARM_ARCH_3__} \
155 %{march=armv3m:-D__ARM_ARCH_3M__} \
156 %{march=armv4:-D__ARM_ARCH_4__} \
157 %{march=armv4t:-D__ARM_ARCH_4T__} \
158 %{march=armv5:-D__ARM_ARCH_5__} \
160 %{mcpu=arm2:-D__ARM_ARCH_2__} \
161 %{mcpu=arm250:-D__ARM_ARCH_2__} \
162 %{mcpu=arm3:-D__ARM_ARCH_2__} \
163 %{mcpu=arm6:-D__ARM_ARCH_3__} \
164 %{mcpu=arm600:-D__ARM_ARCH_3__} \
165 %{mcpu=arm610:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7:-D__ARM_ARCH_3__} \
167 %{mcpu=arm700:-D__ARM_ARCH_3__} \
168 %{mcpu=arm710:-D__ARM_ARCH_3__} \
169 %{mcpu=arm720:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
172 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
173 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
175 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
176 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm8:-D__ARM_ARCH_4__} \
178 %{mcpu=arm810:-D__ARM_ARCH_4__} \
179 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm920:-D__ARM_ARCH_4__} \
181 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
182 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
183 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
184 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
185 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
186 %{!mcpu*:%(cpp_cpu_arch_default)}} \
189 /* Define __APCS_26__ if the PC also contains the PSR */
190 #define CPP_APCS_PC_SPEC "\
191 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
193 %{mapcs-26:-D__APCS_26__} \
194 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
197 #ifndef CPP_APCS_PC_DEFAULT_SPEC
198 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
201 #define CPP_FLOAT_SPEC "\
203 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
205 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
208 /* Default is hard float, which doesn't define anything */
209 #define CPP_FLOAT_DEFAULT_SPEC ""
211 #define CPP_ENDIAN_SPEC "\
214 %e-mbig-endian and -mlittle-endian may not be used together} \
215 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
216 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
219 /* Default is little endian, which doesn't define anything. */
220 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__"
224 /* This macro defines names of additional specifications to put in the specs
225 that can be used in various specifications like CC1_SPEC. Its definition
226 is an initializer with a subgrouping for each command option.
228 Each subgrouping contains a string constant, that defines the
229 specification name, and a string constant that used by the GNU CC driver
232 Do not define this macro if it does not need to do anything. */
233 #define EXTRA_SPECS \
234 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
235 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
236 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
237 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
238 { "cpp_float", CPP_FLOAT_SPEC }, \
239 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
240 { "cpp_endian", CPP_ENDIAN_SPEC }, \
241 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
242 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
243 SUBTARGET_EXTRA_SPECS
245 #define SUBTARGET_EXTRA_SPECS
246 #ifndef SUBTARGET_CPP_SPEC
247 #define SUBTARGET_CPP_SPEC ""
251 /* Run-time Target Specification. */
252 #ifndef TARGET_VERSION
253 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
256 /* Nonzero if the function prologue (and epilogue) should obey
257 the ARM Procedure Call Standard. */
258 #define ARM_FLAG_APCS_FRAME (1 << 0)
260 /* Nonzero if the function prologue should output the function name to enable
261 the post mortem debugger to print a backtrace (very useful on RISCOS,
262 unused on RISCiX). Specifying this flag also enables
263 -fno-omit-frame-pointer.
264 XXX Must still be implemented in the prologue. */
265 #define ARM_FLAG_POKE (1 << 1)
267 /* Nonzero if floating point instructions are emulated by the FPE, in which
268 case instruction scheduling becomes very uninteresting. */
269 #define ARM_FLAG_FPE (1 << 2)
271 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
272 that assume restoration of the condition flags when returning from a
273 branch and link (ie a function). */
274 #define ARM_FLAG_APCS_32 (1 << 3)
276 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
278 /* Nonzero if stack checking should be performed on entry to each function
279 which allocates temporary variables on the stack. */
280 #define ARM_FLAG_APCS_STACK (1 << 4)
282 /* Nonzero if floating point parameters should be passed to functions in
283 floating point registers. */
284 #define ARM_FLAG_APCS_FLOAT (1 << 5)
286 /* Nonzero if re-entrant, position independent code should be generated.
287 This is equivalent to -fpic. */
288 #define ARM_FLAG_APCS_REENT (1 << 6)
290 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
291 be loaded using either LDRH or LDRB instructions. */
292 #define ARM_FLAG_MMU_TRAPS (1 << 7)
294 /* Nonzero if all floating point instructions are missing (and there is no
295 emulator either). Generate function calls for all ops in this case. */
296 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
298 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
299 #define ARM_FLAG_BIG_END (1 << 9)
301 /* Nonzero if we should compile for Thumb interworking. */
302 #define ARM_FLAG_INTERWORK (1 << 10)
304 /* Nonzero if we should have little-endian words even when compiling for
305 big-endian (for backwards compatibility with older versions of GCC). */
306 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
308 /* Nonzero if we need to protect the prolog from scheduling */
309 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
311 /* Nonzero if a call to abort should be generated if a noreturn
312 function tries to return. */
313 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
315 /* Nonzero if function prologues should not load the PIC register. */
316 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
318 /* Nonzero if all call instructions should be indirect. */
319 #define ARM_FLAG_LONG_CALLS (1 << 15)
321 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
322 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
323 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
324 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
325 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
326 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
327 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
328 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
329 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
330 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
331 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
332 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
333 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
334 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
335 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
336 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
337 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
339 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
340 Bit 31 is reserved. See riscix.h. */
341 #ifndef SUBTARGET_SWITCHES
342 #define SUBTARGET_SWITCHES
345 #define TARGET_SWITCHES \
347 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
348 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
349 "Generate APCS conformant stack frames" }, \
350 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
351 {"poke-function-name", ARM_FLAG_POKE, \
352 "Store function names in object code" }, \
353 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
354 {"fpe", ARM_FLAG_FPE, "" }, \
355 {"apcs-32", ARM_FLAG_APCS_32, \
356 "Use the 32bit version of the APCS" }, \
357 {"apcs-26", -ARM_FLAG_APCS_32, \
358 "Use the 26bit version of the APCS" }, \
359 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
360 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
361 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
362 "Pass FP arguments in FP registers" }, \
363 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
364 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
365 "Generate re-entrant, PIC code" }, \
366 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
367 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
368 "The MMU will trap on unaligned accesses" },\
369 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
370 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
371 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
372 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
373 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
374 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
375 "Use library calls to perform FP operations" }, \
376 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
377 "Use hardware floating point instructions" }, \
378 {"big-endian", ARM_FLAG_BIG_END, \
379 "Assume target CPU is configured as big endian" }, \
380 {"little-endian", -ARM_FLAG_BIG_END, \
381 "Assume target CPU is configured as little endian" }, \
382 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
383 "Assume big endian bytes, little endian words" }, \
384 {"thumb-interwork", ARM_FLAG_INTERWORK, \
385 "Support calls between THUMB and ARM instructions sets" }, \
386 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
387 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
388 "Generate a call to abort if a noreturn function returns"}, \
389 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
390 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
391 "Do not move instructions into a function's prologue" }, \
392 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
393 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
394 "Do not load the PIC register in function prologues" }, \
395 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
396 {"long-calls", ARM_FLAG_LONG_CALLS, \
397 "Generate all call instructions as indirect calls"}, \
398 {"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \
400 {"", TARGET_DEFAULT, "" } \
403 #define TARGET_OPTIONS \
405 {"cpu=", & arm_select[0].string, \
406 "Specify the name of the target CPU" }, \
407 {"arch=", & arm_select[1].string, \
408 "Specify the name of the target architecture" }, \
409 {"tune=", & arm_select[2].string, "" }, \
410 {"fpe=", & target_fp_name, "" }, \
411 {"fp=", & target_fp_name, \
412 "Specify the version of the floating point emulator" }, \
413 { "structure-size-boundary=", & structure_size_string, \
414 "Specify the minumum bit alignment of structures" }, \
415 { "pic-register=", & arm_pic_register_string, \
416 "Specify the register to be used for PIC addressing" } \
419 struct arm_cpu_select
423 const struct processors * processors;
426 /* This is a magic array. If the user specifies a command line switch
427 which matches one of the entries in TARGET_OPTIONS then the corresponding
428 string pointer will be set to the value specified by the user. */
429 extern struct arm_cpu_select arm_select[];
437 /* Recast the program mode class to be the prog_mode attribute */
438 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
440 extern enum prog_mode_type arm_prgmode;
442 /* What sort of floating point unit do we have? Hardware or software.
443 If software, is it issue 2 or issue 3? */
444 enum floating_point_type
451 /* Recast the floating point class to be the floating point attribute. */
452 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
454 /* What type of floating point to tune for */
455 extern enum floating_point_type arm_fpu;
457 /* What type of floating point instructions are available */
458 extern enum floating_point_type arm_fpu_arch;
460 /* Default floating point architecture. Override in sub-target if
462 #define FP_DEFAULT FP_SOFT2
464 /* Nonzero if the processor has a fast multiply insn, and one that does
465 a 64-bit multiply of two 32-bit values. */
466 extern int arm_fast_multiply;
468 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
469 extern int arm_arch4;
471 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
472 extern int arm_arch5;
474 /* Nonzero if this chip can benefit from load scheduling. */
475 extern int arm_ld_sched;
477 /* Nonzero if this chip is a StrongARM. */
478 extern int arm_is_strong;
480 /* Nonzero if this chip is a an ARM6 or an ARM7. */
481 extern int arm_is_6_or_7;
483 #ifndef TARGET_DEFAULT
484 #define TARGET_DEFAULT 0
487 /* The frame pointer register used in gcc has nothing to do with debugging;
488 that is controlled by the APCS-FRAME option. */
489 /* Not fully implemented yet */
490 /* #define CAN_DEBUG_WITHOUT_FP 1 */
492 #define TARGET_MEM_FUNCTIONS 1
494 #define OVERRIDE_OPTIONS arm_override_options ()
496 /* Nonzero if PIC code requires explicit qualifiers to generate
497 PLT and GOT relocs rather than the assembler doing so implicitly.
498 Subtargets can override these if required. */
499 #ifndef NEED_GOT_RELOC
500 #define NEED_GOT_RELOC 0
502 #ifndef NEED_PLT_RELOC
503 #define NEED_PLT_RELOC 0
506 /* Nonzero if we need to refer to the GOT with a PC-relative
507 offset. In other words, generate
509 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
513 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
515 The default is true, which matches NetBSD. Subtargets can
516 override this if required. */
521 /* Target machine storage Layout. */
524 /* Define this macro if it is advisable to hold scalars in registers
525 in a wider mode than that declared by the program. In such cases,
526 the value is constrained to be within the bounds of the declared
527 type, but kept valid in the wider mode. The signedness of the
528 extension may differ from that of the type. */
530 /* It is far faster to zero extend chars than to sign extend them */
532 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
533 if (GET_MODE_CLASS (MODE) == MODE_INT \
534 && GET_MODE_SIZE (MODE) < 4) \
536 if (MODE == QImode) \
538 else if (MODE == HImode) \
539 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
543 /* Define this macro if the promotion described by `PROMOTE_MODE'
544 should also be done for outgoing function arguments. */
545 /* This is required to ensure that push insns always push a word. */
546 #define PROMOTE_FUNCTION_ARGS
548 /* Define for XFmode extended real floating point support.
549 This will automatically cause REAL_ARITHMETIC to be defined. */
551 I think I have added all the code to make this work. Unfortunately,
552 early releases of the floating point emulation code on RISCiX used a
553 different format for extended precision numbers. On my RISCiX box there
554 is a bug somewhere which causes the machine to lock up when running enquire
555 with long doubles. There is the additional aspect that Norcroft C
556 treats long doubles as doubles and we ought to remain compatible.
557 Perhaps someone with an FPA coprocessor and not running RISCiX would like
558 to try this someday. */
559 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
561 /* Disable XFmode patterns in md file */
562 #define ENABLE_XF_PATTERNS 0
564 /* Define if you don't want extended real, but do want to use the
565 software floating point emulator for REAL_ARITHMETIC and
566 decimal <-> binary conversion. */
567 /* See comment above */
568 #define REAL_ARITHMETIC
570 /* Define this if most significant bit is lowest numbered
571 in instructions that operate on numbered bit-fields. */
572 #define BITS_BIG_ENDIAN 0
574 /* Define this if most significant byte of a word is the lowest numbered.
575 Most ARM processors are run in little endian mode, so that is the default.
576 If you want to have it run-time selectable, change the definition in a
577 cover file to be TARGET_BIG_ENDIAN. */
578 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
580 /* Define this if most significant word of a multiword number is the lowest
582 This is always false, even when in big-endian mode. */
583 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
585 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
586 on processor pre-defineds when compiling libgcc2.c. */
587 #if defined(__ARMEB__) && !defined(__ARMWEL__)
588 #define LIBGCC2_WORDS_BIG_ENDIAN 1
590 #define LIBGCC2_WORDS_BIG_ENDIAN 0
593 /* Define this if most significant word of doubles is the lowest numbered.
594 This is always true, even when in little-endian mode. */
595 #define FLOAT_WORDS_BIG_ENDIAN 1
597 /* Number of bits in an addressable storage unit */
598 #define BITS_PER_UNIT 8
600 #define BITS_PER_WORD 32
602 #define UNITS_PER_WORD 4
604 #define POINTER_SIZE 32
606 #define PARM_BOUNDARY 32
608 #define STACK_BOUNDARY 32
610 #define FUNCTION_BOUNDARY 32
612 #define EMPTY_FIELD_BOUNDARY 32
614 #define BIGGEST_ALIGNMENT 32
616 /* Make strings word-aligned so strcpy from constants will be faster. */
617 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
618 (TREE_CODE (EXP) == STRING_CST \
619 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
621 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
622 value set in previous versions of this toolchain was 8, which produces more
623 compact structures. The command line option -mstructure_size_boundary=<n>
624 can be used to change this value. For compatability with the ARM SDK
625 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
626 0020D) page 2-20 says "Structures are aligned on word boundaries". */
627 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
628 extern int arm_structure_size_boundary;
630 /* This is the value used to initialise arm_structure_size_boundary. If a
631 particular arm target wants to change the default value it should change
632 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
633 for an example of this. */
634 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
635 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
638 /* Used when parsing command line option -mstructure_size_boundary. */
639 extern const char * structure_size_string;
641 /* Non-zero if move instructions will actually fail to work
642 when given unaligned data. */
643 #define STRICT_ALIGNMENT 1
645 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
648 /* Standard register usage. */
650 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
651 (S - saved over call).
653 r0 * argument word/integer result
656 r4-r8 S register variable
657 r9 S (rfp) register variable (real frame pointer)
659 r10 F S (sl) stack limit (used by -mapcs-stack-check)
660 r11 F S (fp) argument pointer
661 r12 (ip) temp workspace
662 r13 F S (sp) lower end of current stack frame
663 r14 (lr) link address/workspace
664 r15 F (pc) program counter
666 f0 floating point result
667 f1-f3 floating point scratch
669 f4-f7 S floating point variable
671 cc This is NOT a real register, but is used internally
672 to represent things that use or set the condition
674 sfp This isn't either. It is used during rtl generation
675 since the offset between the frame pointer and the
676 auto's isn't known until after register allocation.
677 afp Nor this, we only need this because of non-local
678 goto. Without it fp appears to be used and the
679 elimination code won't get rid of sfp. It tracks
680 fp exactly at all times.
682 *: See CONDITIONAL_REGISTER_USAGE */
684 /* The stack backtrace structure is as follows:
685 fp points to here: | save code pointer | [fp]
686 | return link value | [fp, #-4]
687 | return sp value | [fp, #-8]
688 | return fp value | [fp, #-12]
689 [| saved r10 value |]
700 [| saved f7 value |] three words
701 [| saved f6 value |] three words
702 [| saved f5 value |] three words
703 [| saved f4 value |] three words
704 r0-r3 are not normally saved in a C function. */
706 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
707 #define FIRST_PSEUDO_REGISTER 27
709 /* 1 for registers that have pervasive standard uses
710 and are not available for the register allocator. */
711 #define FIXED_REGISTERS \
719 /* 1 for registers not available across function calls.
720 These must include the FIXED_REGISTERS and also any
721 registers that can be used without being saved.
722 The latter must include the registers where values are returned
723 and the register where structure-value addresses are passed.
724 Aside from that, you can include as many other registers as you like.
725 The CC is not preserved over function calls on the ARM 6, so it is
726 easier to assume this for all. SFP is preserved, since FP is. */
727 #define CALL_USED_REGISTERS \
735 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
736 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
739 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
740 trampled. This effectively reduces the number of available registers by 1.
741 XXX It is a hack, I know.
742 XXX Is this still needed? */
743 #define CONDITIONAL_REGISTER_USAGE \
747 if (TARGET_SOFT_FLOAT) \
750 for (regno = 16; regno < 24; ++regno) \
751 fixed_regs[regno] = call_used_regs[regno] = 1; \
755 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
756 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
758 else if (TARGET_APCS_STACK) \
760 fixed_regs[10] = 1; \
761 call_used_regs[10] = 1; \
763 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
766 /* These are a couple of extensions to the formats accecpted
768 %@ prints out ASM_COMMENT_START
769 %r prints out REGISTER_PREFIX reg_names[arg] */
770 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
772 fputs (ASM_COMMENT_START, FILE); \
776 fputs (REGISTER_PREFIX, FILE); \
777 fputs (reg_names [va_arg (ARGS, int)], FILE); \
780 /* Convert fron bytes to ints. */
781 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
783 /* The number of (integer) registers required to hold a quantity of type MODE. */
784 #define NUM_REGS(MODE) \
785 NUM_INTS (GET_MODE_SIZE (MODE))
787 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
788 #define NUM_REGS2(MODE, TYPE) \
789 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
791 /* The number of (integer) argument register available. */
792 #define NUM_ARG_REGS 4
794 /* Return the regiser number of the N'th (integer) argument. */
795 #define ARG_REGISTER(N) (N - 1)
797 /* The number of the last argument register. */
798 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
800 /* Return number of consecutive hard regs needed starting at reg REGNO
801 to hold something of mode MODE.
802 This is ordinarily the length in words of a value of mode MODE
803 but can be less for certain modes in special long registers.
805 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
807 #define HARD_REGNO_NREGS(REGNO, MODE) \
809 && REGNO != FRAME_POINTER_REGNUM \
810 && REGNO != ARG_POINTER_REGNUM) \
811 ? 1 : NUM_REGS (MODE))
813 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
814 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
816 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
817 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
818 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
819 || REGNO == ARG_POINTER_REGNUM \
820 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
822 /* Value is 1 if it is a good idea to tie two pseudo registers
823 when one has mode MODE1 and one has mode MODE2.
824 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
825 for any hard reg, then this must be 0 for correct output. */
826 #define MODES_TIEABLE_P(MODE1, MODE2) \
827 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
829 /* Specify the registers used for certain standard purposes.
830 The values of these macros are register numbers. */
832 /* Define this if the program counter is overloaded on a register. */
835 /* Register to use for pushing function arguments. */
836 #define STACK_POINTER_REGNUM 13
837 #define SP_REGNUM STACK_POINTER_REGNUM
839 /* Base register for access to local variables of the function. */
840 #define FRAME_POINTER_REGNUM 25
842 /* Define this to be where the real frame pointer is if it is not possible to
843 work out the offset between the frame pointer and the automatic variables
844 until after register allocation has taken place. FRAME_POINTER_REGNUM
845 should point to a special register that we will make sure is eliminated. */
846 #define HARD_FRAME_POINTER_REGNUM 11
847 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
849 /* Register which holds return address from a subroutine call. */
852 /* Scratch register - used in all kinds of places, eg trampolines. */
855 /* Value should be nonzero if functions must have frame pointers.
856 Zero means the frame pointer need not be set up (and parms may be accessed
857 via the stack pointer) in functions that seem suitable.
858 If we have to have a frame pointer we might as well make use of it.
859 APCS says that the frame pointer does not need to be pushed in leaf
860 functions, or simple tail call functions. */
861 #define FRAME_POINTER_REQUIRED \
862 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
864 /* Base register for access to arguments of the function. */
865 #define ARG_POINTER_REGNUM 26
867 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
868 as an invisible last argument (possible since varargs don't exist in
869 Pascal), so the following is not true. */
870 #define STATIC_CHAIN_REGNUM 8
872 /* Register in which address to store a structure value
873 is passed to a function. */
874 #define STRUCT_VALUE_REGNUM 0
876 /* Internal, so that we don't need to refer to a raw number */
879 /* The order in which register should be allocated. It is good to use ip
880 since no saving is required (though calls clobber it) and it never contains
881 function parameters. It is quite good to use lr since other calls may
882 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
883 least likely to contain a function parameter; in addition results are
886 #define REG_ALLOC_ORDER \
888 3, 2, 1, 0, 12, 14, 4, 5, \
889 6, 7, 8, 10, 9, 11, 13, 15, \
890 16, 17, 18, 19, 20, 21, 22, 23, \
894 /* Register and constant classes. */
896 /* Register classes: all ARM regs or all FPU regs---simple! */
906 #define N_REG_CLASSES (int) LIM_REG_CLASSES
908 /* Give names of register classes as strings for dump file. */
909 #define REG_CLASS_NAMES \
917 /* Define which registers fit in which classes.
918 This is an initializer for a vector of HARD_REG_SET
919 of length N_REG_CLASSES. */
920 #define REG_CLASS_CONTENTS \
922 { 0x0000000 }, /* NO_REGS */ \
923 { 0x0FF0000 }, /* FPU_REGS */ \
924 { 0x200FFFF }, /* GENERAL_REGS */ \
925 { 0x2FFFFFF } /* ALL_REGS */ \
928 /* The same information, inverted:
929 Return the class number of the smallest class containing
930 reg number REGNO. This could be a conditional expression
931 or could index an array. */
932 #define REGNO_REG_CLASS(REGNO) \
933 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
934 || REGNO == ARG_POINTER_REGNUM) \
935 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
936 ? NO_REGS : FPU_REGS)
938 /* The class value for index registers, and the one for base regs. */
939 #define INDEX_REG_CLASS GENERAL_REGS
940 #define BASE_REG_CLASS GENERAL_REGS
942 /* Get reg_class from a letter such as appears in the machine description.
943 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
944 #define REG_CLASS_FROM_LETTER(C) \
945 ((C)=='f' ? FPU_REGS : NO_REGS)
947 /* The letters I, J, K, L and M in a register constraint string
948 can be used to stand for particular ranges of immediate operands.
949 This macro defines what the ranges are.
950 C is the letter, and VALUE is a constant value.
951 Return 1 if VALUE is in the range specified by C.
952 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
953 J: valid indexing constants.
954 K: ~value ok in rhs argument of data operand.
955 L: -value ok in rhs argument of data operand.
956 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
957 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
958 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
959 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
960 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
961 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
962 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
963 || (((VALUE) & ((VALUE) - 1)) == 0)) \
966 /* For the ARM, `Q' means that this is a memory operand that is just
967 an offset from a register.
968 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
969 address. This means that the symbol is in the text segment and can be
970 accessed without using a load. */
972 #define EXTRA_CONSTRAINT(OP, C) \
973 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
974 : (C) == 'R' ? (GET_CODE (OP) == MEM \
975 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
976 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
977 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
980 /* Constant letter 'G' for the FPU immediate constants.
981 'H' means the same constant negated. */
982 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
983 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
984 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
986 /* Given an rtx X being reloaded into a reg required to be
987 in class CLASS, return the class of reg to actually use.
988 In general this is just CLASS; but on some machines
989 in some cases it is preferable to use a more restrictive class. */
990 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
992 /* Return the register class of a scratch register needed to copy IN into
993 or out of a register in CLASS in MODE. If it can be done directly,
994 NO_REGS is returned. */
995 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
996 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
997 ? GENERAL_REGS : NO_REGS)
999 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1000 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1001 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1002 && (GET_CODE (X) == MEM \
1003 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1004 && true_regnum (X) == -1))) \
1005 ? GENERAL_REGS : NO_REGS)
1007 /* Try a machine-dependent way of reloading an illegitimate address
1008 operand. If we find one, push the reload and jump to WIN. This
1009 macro is used in only one place: `find_reloads_address' in reload.c.
1011 For the ARM, we wish to handle large displacements off a base
1012 register by splitting the addend across a MOV and the mem insn.
1013 This can cut the number of reloads needed. */
1014 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1017 if (GET_CODE (X) == PLUS \
1018 && GET_CODE (XEXP (X, 0)) == REG \
1019 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1020 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1021 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1023 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1024 HOST_WIDE_INT low, high; \
1026 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1027 low = ((val & 0xf) ^ 0x8) - 0x8; \
1028 else if (MODE == SImode \
1029 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1030 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1031 /* Need to be careful, -4096 is not a valid offset */ \
1032 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1033 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1034 /* Need to be careful, -256 is not a valid offset */ \
1035 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1036 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1037 && TARGET_HARD_FLOAT) \
1038 /* Need to be careful, -1024 is not a valid offset */ \
1039 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1043 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
1044 /* Check for overflow or zero */ \
1045 if (low == 0 || high == 0 || (high + low != val)) \
1048 /* Reload the high part into a base reg; leave the low part \
1050 X = gen_rtx_PLUS (GET_MODE (X), \
1051 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1054 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1055 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1062 /* Return the maximum number of consecutive registers
1063 needed to represent mode MODE in a register of class CLASS.
1064 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1065 #define CLASS_MAX_NREGS(CLASS, MODE) \
1066 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1068 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1069 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1070 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1071 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1074 /* Stack layout; function entry, exit and calling. */
1076 /* Define this if pushing a word on the stack
1077 makes the stack pointer a smaller address. */
1078 #define STACK_GROWS_DOWNWARD 1
1080 /* Define this if the nominal address of the stack frame
1081 is at the high-address end of the local variables;
1082 that is, each additional local variable allocated
1083 goes at a more negative offset in the frame. */
1084 #define FRAME_GROWS_DOWNWARD 1
1086 /* Offset within stack frame to start allocating local variables at.
1087 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1088 first local allocated. Otherwise, it is the offset to the BEGINNING
1089 of the first local allocated. */
1090 #define STARTING_FRAME_OFFSET 0
1092 /* If we generate an insn to push BYTES bytes,
1093 this says how many the stack pointer really advances by. */
1094 /* The push insns do not do this rounding implicitly. So don't define this. */
1095 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1097 /* Define this if the maximum size of all the outgoing args is to be
1098 accumulated and pushed during the prologue. The amount can be
1099 found in the variable current_function_outgoing_args_size. */
1100 #define ACCUMULATE_OUTGOING_ARGS 1
1102 /* Offset of first parameter from the argument pointer register value. */
1103 #define FIRST_PARM_OFFSET(FNDECL) 4
1105 /* Value is the number of byte of arguments automatically
1106 popped when returning from a subroutine call.
1107 FUNDECL is the declaration node of the function (as a tree),
1108 FUNTYPE is the data type of the function (as a tree),
1109 or for a library call it is an identifier node for the subroutine name.
1110 SIZE is the number of bytes of arguments passed on the stack.
1112 On the ARM, the caller does not pop any of its arguments that were passed
1114 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1116 /* Define how to find the value returned by a library function
1117 assuming the value has mode MODE. */
1118 #define LIBCALL_VALUE(MODE) \
1119 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1120 ? gen_rtx_REG (MODE, 16) \
1121 : gen_rtx_REG (MODE, 0))
1123 /* Define how to find the value returned by a function.
1124 VALTYPE is the data type of the value (as a tree).
1125 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1126 otherwise, FUNC is 0. */
1127 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1128 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1130 /* 1 if N is a possible register number for a function value.
1131 On the ARM, only r0 and f0 can return results. */
1132 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1133 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1135 /* How large values are returned */
1136 /* A C expression which can inhibit the returning of certain function values
1137 in registers, based on the type of value. */
1138 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1140 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1141 values must be in memory. On the ARM, they need only do so if larger
1142 than a word, or if they contain elements offset from zero in the struct. */
1143 #define DEFAULT_PCC_STRUCT_RETURN 0
1145 /* Define where to put the arguments to a function.
1146 Value is zero to push the argument on the stack,
1147 or a hard register in which to store the argument.
1149 MODE is the argument's machine mode.
1150 TYPE is the data type of the argument (as a tree).
1151 This is null for libcalls where that information may
1153 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1154 the preceding args and about the function being called.
1155 NAMED is nonzero if this argument is a named parameter
1156 (otherwise it is an extra parameter matching an ellipsis).
1158 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1159 other arguments are passed on the stack. If (NAMED == 0) (which happens
1160 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1161 passed in the stack (function_prologue will indeed make it pass in the
1162 stack if necessary). */
1163 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1165 ? ((CUM) >= NUM_ARG_REGS ? 0 : gen_rtx_REG (MODE, CUM))\
1168 /* For an arg passed partly in registers and partly in memory,
1169 this is the number of registers used.
1170 For args passed entirely in registers or entirely in memory, zero. */
1171 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1172 ( NUM_ARG_REGS > (CUM) \
1173 && (NUM_ARG_REGS < ((CUM) + NUM_REGS2 (MODE, TYPE))) \
1174 ? NUM_ARG_REGS - (CUM) : 0)
1176 /* A C type for declaring a variable that is used as the first argument of
1177 `FUNCTION_ARG' and other related values. For some target machines, the
1178 type `int' suffices and can hold the number of bytes of argument so far.
1180 On the ARM, this is the number of bytes of arguments scanned so far. */
1181 #define CUMULATIVE_ARGS int
1183 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1184 for a call to a function whose data type is FNTYPE.
1185 For a library call, FNTYPE is 0.
1186 On the ARM, the offset starts at 0. */
1187 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1188 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 1 : 0))
1190 /* Update the data in CUM to advance over an argument
1191 of mode MODE and data type TYPE.
1192 (TYPE is null for libcalls where that information may not be available.) */
1193 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1194 (CUM) += NUM_REGS2 (MODE, TYPE)
1196 /* 1 if N is a possible register number for function argument passing.
1197 On the ARM, r0-r3 are used to pass args. */
1198 #define FUNCTION_ARG_REGNO_P(REGNO) \
1199 ((REGNO) >= 0 && (REGNO) <= 3)
1201 /* Perform any actions needed for a function that is receiving a variable
1202 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1203 of the current parameter. PRETEND_SIZE is a variable that should be set to
1204 the amount of stack that must be pushed by the prolog to pretend that our
1207 Normally, this macro will push all remaining incoming registers on the
1208 stack and set PRETEND_SIZE to the length of the registers pushed.
1210 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1211 named arg and all anonymous args onto the stack.
1212 XXX I know the prologue shouldn't be pushing registers, but it is faster
1214 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1216 extern int current_function_anonymous_args; \
1217 current_function_anonymous_args = 1; \
1218 if ((CUM) < NUM_ARG_REGS) \
1219 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM)) * UNITS_PER_WORD; \
1222 /* Generate assembly output for the start of a function. */
1223 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1224 output_func_prologue ((STREAM), (SIZE))
1226 /* If your target environment doesn't prefix user functions with an
1227 underscore, you may wish to re-define this to prevent any conflicts.
1228 e.g. AOF may prefix mcount with an underscore. */
1229 #ifndef ARM_MCOUNT_NAME
1230 #define ARM_MCOUNT_NAME "*mcount"
1233 /* Call the function profiler with a given profile label. The Acorn
1234 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1235 On the ARM the full profile code will look like:
1244 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1245 will output the .text section.
1247 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1248 ``prof'' doesn't seem to mind about this! */
1249 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1254 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1255 IP_REGNUM, LR_REGNUM); \
1256 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1257 fputc ('\n', STREAM); \
1258 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1259 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1260 ASM_OUTPUT_INT (STREAM, sym); \
1263 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1264 the stack pointer does not matter. The value is tested only in
1265 functions that have frame pointers.
1266 No definition is equivalent to always zero.
1268 On the ARM, the function epilogue recovers the stack pointer from the
1270 #define EXIT_IGNORE_STACK 1
1272 /* Generate the assembly code for function exit. */
1273 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1274 output_func_epilogue (SIZE)
1276 /* Determine if the epilogue should be output as RTL.
1277 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1278 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1280 /* Definitions for register eliminations.
1282 This is an array of structures. Each structure initializes one pair
1283 of eliminable registers. The "from" register number is given first,
1284 followed by "to". Eliminations of the same "from" register are listed
1285 in order of preference.
1287 We have two registers that can be eliminated on the ARM. First, the
1288 arg pointer register can often be eliminated in favor of the stack
1289 pointer register. Secondly, the pseudo frame pointer register can always
1290 be eliminated; it is replaced with either the stack or the real frame
1293 #define ELIMINABLE_REGS \
1294 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1295 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1296 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1297 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1299 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1300 Frame pointer elimination is automatically handled.
1302 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1303 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1304 pointer, we must eliminate FRAME_POINTER_REGNUM into
1305 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1306 #define CAN_ELIMINATE(FROM, TO) \
1307 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1309 /* Define the offset between two registers, one to be eliminated, and the other
1310 its replacement, at the start of a routine. */
1311 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1313 int volatile_func = arm_volatile_func (); \
1314 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1316 else if ((FROM) == FRAME_POINTER_REGNUM \
1317 && (TO) == STACK_POINTER_REGNUM) \
1318 (OFFSET) = current_function_outgoing_args_size \
1319 + ((get_frame_size () + 3) & ~3); \
1324 int saved_hard_reg = 0; \
1326 if (! volatile_func) \
1328 for (regno = 0; regno <= 10; regno++) \
1329 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1330 saved_hard_reg = 1, offset += 4; \
1331 /* PIC register is a fixed reg, so call_used_regs set. */ \
1332 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1333 saved_hard_reg = 1, offset += 4; \
1334 for (regno = 16; regno <=23; regno++) \
1335 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1338 if ((FROM) == FRAME_POINTER_REGNUM) \
1339 (OFFSET) = -offset; \
1342 if (! frame_pointer_needed) \
1344 if (! volatile_func \
1345 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1347 offset += current_function_outgoing_args_size; \
1348 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1353 /* Output assembler code for a block containing the constant parts
1354 of a trampoline, leaving space for the variable parts.
1356 On the ARM, (if r8 is the static chain regnum, and remembering that
1357 referencing pc adds an offset of 8) the trampoline looks like:
1360 .word static chain value
1361 .word function's address
1362 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1363 #define TRAMPOLINE_TEMPLATE(FILE) \
1365 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1366 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1367 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1368 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1369 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1370 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1371 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1372 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1375 /* Length in units of the trampoline for entering a nested function. */
1376 #define TRAMPOLINE_SIZE 16
1378 /* Alignment required for a trampoline in units. */
1379 #define TRAMPOLINE_ALIGN 4
1381 /* Emit RTL insns to initialize the variable parts of a trampoline.
1382 FNADDR is an RTX for the address of the function's pure code.
1383 CXT is an RTX for the static chain value for the function. */
1384 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1386 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1388 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1393 /* Addressing modes, and classification of registers for them. */
1395 #define HAVE_POST_INCREMENT 1
1396 #define HAVE_PRE_INCREMENT 1
1397 #define HAVE_POST_DECREMENT 1
1398 #define HAVE_PRE_DECREMENT 1
1400 /* Macros to check register numbers against specific register classes. */
1402 /* These assume that REGNO is a hard or pseudo reg number.
1403 They give nonzero only if REGNO is a hard reg of the suitable class
1404 or a pseudo reg currently allocated to a suitable hard reg.
1405 Since they use reg_renumber, they are safe only once reg_renumber
1406 has been allocated, which happens in local-alloc.c.
1408 On the ARM, don't allow the pc to be used. */
1409 #define REGNO_OK_FOR_BASE_P(REGNO) \
1410 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1411 || (REGNO) == ARG_POINTER_REGNUM \
1412 || (unsigned) reg_renumber[(REGNO)] < 15 \
1413 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1414 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1415 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1416 REGNO_OK_FOR_BASE_P(REGNO)
1418 /* Maximum number of registers that can appear in a valid memory address.
1419 Shifts in addresses can't be by a register. */
1421 #define MAX_REGS_PER_ADDRESS 2
1423 /* Recognize any constant value that is a valid address. */
1424 /* XXX We can address any constant, eventually... */
1426 #ifdef AOF_ASSEMBLER
1428 #define CONSTANT_ADDRESS_P(X) \
1429 (GET_CODE (X) == SYMBOL_REF \
1430 && CONSTANT_POOL_ADDRESS_P (X))
1434 #define CONSTANT_ADDRESS_P(X) \
1435 (GET_CODE (X) == SYMBOL_REF \
1436 && (CONSTANT_POOL_ADDRESS_P (X) \
1437 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1439 #endif /* AOF_ASSEMBLER */
1441 /* Nonzero if the constant value X is a legitimate general operand.
1442 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1444 On the ARM, allow any integer (invalid ones are removed later by insn
1445 patterns), nice doubles and symbol_refs which refer to the function's
1446 constant pool XXX. */
1447 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1449 /* Symbols in the text segment can be accessed without indirecting via the
1450 constant pool; it may take an extra binary operation, but this is still
1451 faster than indirecting via memory. Don't do this when not optimizing,
1452 since we won't be calculating al of the offsets necessary to do this
1454 /* This doesn't work with AOF syntax, since the string table may be in
1455 a different AREA. */
1456 #ifndef AOF_ASSEMBLER
1457 #define ENCODE_SECTION_INFO(decl) \
1459 if (optimize > 0 && TREE_CONSTANT (decl) \
1460 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1462 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1463 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1464 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1469 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1470 and check its validity for a certain class.
1471 We have two alternate definitions for each of them.
1472 The usual definition accepts all pseudo regs; the other rejects
1473 them unless they have been allocated suitable hard regs.
1474 The symbol REG_OK_STRICT causes the latter definition to be used. */
1475 #ifndef REG_OK_STRICT
1477 /* Nonzero if X is a hard reg that can be used as a base reg
1478 or if it is a pseudo reg. */
1479 #define REG_OK_FOR_BASE_P(X) \
1480 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1481 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1483 /* Nonzero if X is a hard reg that can be used as an index
1484 or if it is a pseudo reg. */
1485 #define REG_OK_FOR_INDEX_P(X) \
1486 REG_OK_FOR_BASE_P(X)
1488 #define REG_OK_FOR_PRE_POST_P(X) \
1489 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1490 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1494 /* Nonzero if X is a hard reg that can be used as a base reg. */
1495 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1497 /* Nonzero if X is a hard reg that can be used as an index. */
1498 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1500 #define REG_OK_FOR_PRE_POST_P(X) \
1501 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1502 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1503 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1504 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1508 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1509 that is a valid memory address for an instruction.
1510 The MODE argument is the machine mode for the MEM expression
1511 that wants to use this address.
1513 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1514 #define BASE_REGISTER_RTX_P(X) \
1515 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1517 #define INDEX_REGISTER_RTX_P(X) \
1518 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1520 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1521 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1522 only be small constants. */
1523 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1526 HOST_WIDE_INT range; \
1527 enum rtx_code code = GET_CODE (INDEX); \
1529 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1531 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1532 && INTVAL (INDEX) > -1024 \
1533 && (INTVAL (INDEX) & 3) == 0) \
1538 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1540 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1541 && (! arm_arch4 || (MODE) != HImode)) \
1543 rtx xiop0 = XEXP (INDEX, 0); \
1544 rtx xiop1 = XEXP (INDEX, 1); \
1545 if (INDEX_REGISTER_RTX_P (xiop0) \
1546 && power_of_two_operand (xiop1, SImode)) \
1548 if (INDEX_REGISTER_RTX_P (xiop1) \
1549 && power_of_two_operand (xiop0, SImode)) \
1552 if (GET_MODE_SIZE (MODE) <= 4 \
1553 && (code == LSHIFTRT || code == ASHIFTRT \
1554 || code == ASHIFT || code == ROTATERT) \
1555 && (! arm_arch4 || (MODE) != HImode)) \
1557 rtx op = XEXP (INDEX, 1); \
1558 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1559 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1560 && INTVAL (op) <= 31) \
1563 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1564 range = ((MODE) == HImode || (MODE) == QImode) \
1565 ? (arm_arch4 ? 256 : 4095) : 4096; \
1566 if (code == CONST_INT && INTVAL (INDEX) < range \
1567 && INTVAL (INDEX) > -range) \
1573 /* Jump to LABEL if X is a valid address RTX. This must also take
1574 REG_OK_STRICT into account when deciding about valid registers, but it uses
1575 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1576 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1577 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1578 refs must be forced though a static cell to ensure addressability. */
1579 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1581 if (BASE_REGISTER_RTX_P (X)) \
1583 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1584 && GET_CODE (XEXP (X, 0)) == REG \
1585 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1587 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1588 && (GET_CODE (X) == LABEL_REF \
1589 || (GET_CODE (X) == CONST \
1590 && GET_CODE (XEXP ((X), 0)) == PLUS \
1591 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1592 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1594 else if ((MODE) == TImode) \
1596 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1598 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1599 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1601 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1602 if (val == 4 || val == -4 || val == -8) \
1606 else if (GET_CODE (X) == PLUS) \
1608 rtx xop0 = XEXP(X,0); \
1609 rtx xop1 = XEXP(X,1); \
1611 if (BASE_REGISTER_RTX_P (xop0)) \
1612 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1613 else if (BASE_REGISTER_RTX_P (xop1)) \
1614 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1616 /* Reload currently can't handle MINUS, so disable this for now */ \
1617 /* else if (GET_CODE (X) == MINUS) \
1619 rtx xop0 = XEXP (X,0); \
1620 rtx xop1 = XEXP (X,1); \
1622 if (BASE_REGISTER_RTX_P (xop0)) \
1623 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1625 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1626 && GET_CODE (X) == SYMBOL_REF \
1627 && CONSTANT_POOL_ADDRESS_P (X) \
1629 && symbol_mentioned_p (get_pool_constant (X)))) \
1631 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1632 && (GET_MODE_SIZE (MODE) <= 4) \
1633 && GET_CODE (XEXP (X, 0)) == REG \
1634 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1638 /* Try machine-dependent ways of modifying an illegitimate address
1639 to be legitimate. If we find one, return the new, valid address.
1640 This macro is used in only one place: `memory_address' in explow.c.
1642 OLDX is the address as it was before break_out_memory_refs was called.
1643 In some cases it is useful to look at this to decide what needs to be done.
1645 MODE and WIN are passed so that this macro can use
1646 GO_IF_LEGITIMATE_ADDRESS.
1648 It is always safe for this macro to do nothing. It exists to recognize
1649 opportunities to optimize the output.
1651 On the ARM, try to convert [REG, #BIGCONST]
1652 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1653 where VALIDCONST == 0 in case of TImode. */
1654 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1656 if (GET_CODE (X) == PLUS) \
1658 rtx xop0 = XEXP (X, 0); \
1659 rtx xop1 = XEXP (X, 1); \
1661 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1662 xop0 = force_reg (SImode, xop0); \
1663 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1664 xop1 = force_reg (SImode, xop1); \
1665 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1667 HOST_WIDE_INT n, low_n; \
1668 rtx base_reg, val; \
1669 n = INTVAL (xop1); \
1671 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1683 low_n = ((MODE) == TImode ? 0 \
1684 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1687 base_reg = gen_reg_rtx (SImode); \
1688 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1689 GEN_INT (n)), NULL_RTX); \
1690 emit_move_insn (base_reg, val); \
1691 (X) = (low_n == 0 ? base_reg \
1692 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1694 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1695 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1697 else if (GET_CODE (X) == MINUS) \
1699 rtx xop0 = XEXP (X, 0); \
1700 rtx xop1 = XEXP (X, 1); \
1702 if (CONSTANT_P (xop0)) \
1703 xop0 = force_reg (SImode, xop0); \
1704 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1705 xop1 = force_reg (SImode, xop1); \
1706 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1707 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1710 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1711 if (memory_address_p (MODE, X)) \
1715 /* Go to LABEL if ADDR (a legitimate address expression)
1716 has an effect that depends on the machine mode it is used for. */
1717 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1719 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1720 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1724 /* Specify the machine mode that this machine uses
1725 for the index in the tablejump instruction. */
1726 #define CASE_VECTOR_MODE SImode
1728 /* Define as C expression which evaluates to nonzero if the tablejump
1729 instruction expects the table to contain offsets from the address of the
1731 Do not define this if the table should contain absolute addresses. */
1732 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1734 /* Specify the tree operation to be used to convert reals to integers. */
1735 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1737 /* This is the kind of divide that is easiest to do in the general case. */
1738 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1740 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1741 unsigned is probably best, but may break some code. */
1742 #ifndef DEFAULT_SIGNED_CHAR
1743 #define DEFAULT_SIGNED_CHAR 0
1746 /* Don't cse the address of the function being compiled. */
1747 #define NO_RECURSIVE_FUNCTION_CSE 1
1749 /* Max number of bytes we can move from memory to memory
1750 in one reasonably fast instruction. */
1753 /* Define if operations between registers always perform the operation
1754 on the full register even if a narrower mode is specified. */
1755 #define WORD_REGISTER_OPERATIONS
1757 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1758 will either zero-extend or sign-extend. The value of this macro should
1759 be the code that says which one of the two operations is implicitly
1760 done, NIL if none. */
1761 #define LOAD_EXTEND_OP(MODE) \
1762 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1763 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1765 /* Define this if zero-extension is slow (more than one real instruction).
1766 On the ARM, it is more than one instruction only if not fetching from
1768 /* #define SLOW_ZERO_EXTEND */
1770 /* Nonzero if access to memory by bytes is slow and undesirable. */
1771 #define SLOW_BYTE_ACCESS 0
1773 /* Immediate shift counts are truncated by the output routines (or was it
1774 the assembler?). Shift counts in a register are truncated by ARM. Note
1775 that the native compiler puts too large (> 32) immediate shift counts
1776 into a register and shifts by the register, letting the ARM decide what
1777 to do instead of doing that itself. */
1778 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1779 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1780 On the arm, Y in a register is used modulo 256 for the shift. Only for
1781 rotates is modulo 32 used. */
1782 /* #define SHIFT_COUNT_TRUNCATED 1 */
1784 /* All integers have the same format so truncation is easy. */
1785 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1787 /* Calling from registers is a massive pain. */
1788 #define NO_FUNCTION_CSE 1
1790 /* Chars and shorts should be passed as ints. */
1791 #define PROMOTE_PROTOTYPES 1
1793 /* The machine modes of pointers and functions */
1794 #define Pmode SImode
1795 #define FUNCTION_MODE Pmode
1797 /* The structure type of the machine dependent info field of insns
1798 No uses for this yet. */
1799 /* #define INSN_MACHINE_INFO struct machine_info */
1801 /* The relative costs of various types of constants. Note that cse.c defines
1802 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1803 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1805 if (const_ok_for_arm (INTVAL (RTX))) \
1806 return (OUTER_CODE) == SET ? 2 : -1; \
1807 else if (OUTER_CODE == AND \
1808 && const_ok_for_arm (~INTVAL (RTX))) \
1810 else if ((OUTER_CODE == COMPARE \
1811 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1812 && const_ok_for_arm (-INTVAL (RTX))) \
1820 case CONST_DOUBLE: \
1821 if (const_double_rtx_ok_for_fpu (RTX)) \
1822 return (OUTER_CODE) == SET ? 2 : -1; \
1823 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1824 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1828 #define ARM_FRAME_RTX(X) \
1829 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1830 || (X) == arg_pointer_rtx)
1832 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1833 return arm_rtx_costs (X, CODE);
1835 /* Moves to and from memory are quite expensive */
1836 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1838 /* All address computations that can be done are free, but rtx cost returns
1839 the same for practically all of them. So we weight the different types
1840 of address here in the order (most pref first):
1841 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1842 #define ADDRESS_COST(X) \
1843 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1844 || GET_CODE (X) == SYMBOL_REF) \
1846 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1847 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1849 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1850 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1851 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1852 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1853 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1854 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1858 /* Try to generate sequences that don't involve branches, we can then use
1859 conditional instructions */
1860 #define BRANCH_COST 4
1862 /* A C statement to update the variable COST based on the relationship
1863 between INSN that is dependent on DEP through dependence LINK. */
1864 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1865 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1867 /* Position Independent Code. */
1868 /* We decide which register to use based on the compilation options and
1869 the assembler in use; this is more general than the APCS restriction of
1870 using sb (r9) all the time. */
1871 extern int arm_pic_register;
1873 /* Used when parsing command line option -mpic-register=. */
1874 extern const char * arm_pic_register_string;
1876 /* The register number of the register used to address a table of static
1877 data addresses in memory. */
1878 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1880 #define FINALIZE_PIC arm_finalize_pic ()
1882 /* We can't directly access anything that contains a symbol,
1883 nor can we indirect via the constant pool. */
1884 #define LEGITIMATE_PIC_OPERAND_P(X) \
1885 (! symbol_mentioned_p (X) \
1886 && (! CONSTANT_POOL_ADDRESS_P (X) \
1887 || ! symbol_mentioned_p (get_pool_constant (X))))
1889 /* We need to know when we are making a constant pool; this determines
1890 whether data needs to be in the GOT or can be referenced via a GOT
1892 extern int making_const_table;
1895 /* Condition code information. */
1896 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1897 return the mode to be used for the comparison.
1898 CCFPEmode should be used with floating inequalities,
1899 CCFPmode should be used with floating equalities.
1900 CC_NOOVmode should be used with SImode integer equalities.
1901 CC_Zmode should be used if only the Z flag is set correctly
1902 CCmode should be used otherwise. */
1904 #define EXTRA_CC_MODES \
1905 CC(CC_NOOVmode, "CC_NOOV") \
1906 CC(CC_Zmode, "CC_Z") \
1907 CC(CC_SWPmode, "CC_SWP") \
1908 CC(CCFPmode, "CCFP") \
1909 CC(CCFPEmode, "CCFPE") \
1910 CC(CC_DNEmode, "CC_DNE") \
1911 CC(CC_DEQmode, "CC_DEQ") \
1912 CC(CC_DLEmode, "CC_DLE") \
1913 CC(CC_DLTmode, "CC_DLT") \
1914 CC(CC_DGEmode, "CC_DGE") \
1915 CC(CC_DGTmode, "CC_DGT") \
1916 CC(CC_DLEUmode, "CC_DLEU") \
1917 CC(CC_DLTUmode, "CC_DLTU") \
1918 CC(CC_DGEUmode, "CC_DGEU") \
1919 CC(CC_DGTUmode, "CC_DGTU") \
1920 CC(CC_Cmode, "CC_C")
1922 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1924 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1926 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1929 if (GET_CODE (OP1) == CONST_INT \
1930 && ! (const_ok_for_arm (INTVAL (OP1)) \
1931 || (const_ok_for_arm (- INTVAL (OP1))))) \
1933 rtx const_op = OP1; \
1934 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1940 #define STORE_FLAG_VALUE 1
1942 /* Define the information needed to generate branch insns. This is
1943 stored from the compare operation. Note that we can't use "rtx" here
1944 since it hasn't been defined! */
1946 extern struct rtx_def * arm_compare_op0;
1947 extern struct rtx_def * arm_compare_op1;
1949 /* Define the codes that are matched by predicates in arm.c */
1950 #define PREDICATE_CODES \
1951 {"s_register_operand", {SUBREG, REG}}, \
1952 {"f_register_operand", {SUBREG, REG}}, \
1953 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1954 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1955 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1956 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1957 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1958 {"offsettable_memory_operand", {MEM}}, \
1959 {"bad_signed_byte_operand", {MEM}}, \
1960 {"alignable_memory_operand", {MEM}}, \
1961 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1962 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1963 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1964 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1965 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1966 {"load_multiple_operation", {PARALLEL}}, \
1967 {"store_multiple_operation", {PARALLEL}}, \
1968 {"equality_operator", {EQ, NE}}, \
1969 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1970 {"const_shift_operand", {CONST_INT}}, \
1971 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1972 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1973 {"multi_register_push", {PARALLEL}}, \
1974 {"cc_register", {REG}}, \
1975 {"logical_binary_operator", {AND, IOR, XOR}}, \
1976 {"dominant_cc_register", {REG}},
1980 /* Gcc puts the pool in the wrong place for ARM, since we can only
1981 load addresses a limited distance around the pc. We do some
1982 special munging to move the constant pool values to the correct
1983 point in the code. */
1984 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1986 /* Output an internal label definition. */
1987 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1988 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1991 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1993 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1994 && !strcmp (PREFIX, "L")) \
1996 arm_ccfsm_state = 0; \
1997 arm_target_insn = NULL; \
1999 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2000 ASM_OUTPUT_LABEL (STREAM, s); \
2005 /* Output a push or a pop instruction (only used when profiling). */
2006 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2007 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2009 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2010 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2012 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2015 if (TARGET_POKE_FUNCTION_NAME) \
2016 arm_poke_function_name (STREAM, NAME); \
2020 /* Target characters. */
2021 #define TARGET_BELL 007
2022 #define TARGET_BS 010
2023 #define TARGET_TAB 011
2024 #define TARGET_NEWLINE 012
2025 #define TARGET_VT 013
2026 #define TARGET_FF 014
2027 #define TARGET_CR 015
2029 /* Only perform branch elimination (by making instructions conditional) if
2030 we're optimising. Otherwise it's of no use anyway. */
2031 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2033 arm_final_prescan_insn (INSN)
2035 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2036 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2038 /* Output an operand of an instruction. */
2039 #define PRINT_OPERAND(STREAM, X, CODE) \
2040 arm_print_operand (STREAM, X, CODE)
2042 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2043 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2044 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
2045 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
2046 ? ((~ (HOST_WIDE_INT) 0) \
2047 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2050 /* Output the address of an operand. */
2051 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2053 int is_minus = GET_CODE (X) == MINUS; \
2055 if (GET_CODE (X) == REG) \
2056 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2057 else if (GET_CODE (X) == PLUS || is_minus) \
2059 rtx base = XEXP (X, 0); \
2060 rtx index = XEXP (X, 1); \
2062 HOST_WIDE_INT offset = 0; \
2063 if (GET_CODE (base) != REG) \
2065 /* Ensure that BASE is a register (one of them must be). */ \
2070 base_reg = REGNO (base); \
2071 switch (GET_CODE (index)) \
2074 offset = INTVAL (index); \
2077 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2081 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2082 is_minus ? "-" : "", REGNO (index)); \
2091 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2092 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2093 arm_print_operand (STREAM, index, 'S'); \
2094 fputs ("]", STREAM); \
2102 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2103 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2105 extern int output_memory_reference_mode; \
2107 if (GET_CODE (XEXP (X, 0)) != REG) \
2110 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2111 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2112 REGNO (XEXP (X, 0)), \
2113 GET_CODE (X) == PRE_DEC ? "-" : "", \
2114 GET_MODE_SIZE (output_memory_reference_mode)); \
2116 asm_fprintf (STREAM, "[%r], #%s%d", \
2117 REGNO (XEXP (X, 0)), \
2118 GET_CODE (X) == POST_DEC ? "-" : "", \
2119 GET_MODE_SIZE (output_memory_reference_mode)); \
2121 else output_addr_const (STREAM, X); \
2124 /* Handles PIC addr specially */
2125 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2127 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2129 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2130 fputs (" - (", STREAM); \
2131 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2132 fputs (")", STREAM); \
2134 else output_addr_const (STREAM, X); \
2136 /* Mark symbols as position independent. We only do this in the \
2137 .text segment, not in the .data segment. */ \
2138 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2139 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2141 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2142 fprintf (STREAM, "(GOTOFF)"); \
2143 else if (GET_CODE (X) == LABEL_REF) \
2144 fprintf (STREAM, "(GOTOFF)"); \
2146 fprintf (STREAM, "(GOT)"); \
2150 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2151 Used for C++ multiple inheritance. */
2152 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2155 int mi_delta = (DELTA); \
2156 char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2158 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2160 if (mi_delta < 0) mi_delta = -mi_delta; \
2161 while (mi_delta != 0) \
2163 if (mi_delta & (3 << shift) == 0) \
2167 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2168 mi_op, this_regno, this_regno, \
2169 mi_delta & (0xff << shift)); \
2170 mi_delta &= ~(0xff << shift); \
2174 fputs ("\tb\t", FILE); \
2175 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2176 if (NEED_PLT_RELOC) \
2177 fputs ("(PLT)", FILE); \
2178 fputc ('\n', FILE); \
2182 /* A C expression whose value is RTL representing the value of the return
2183 address for the frame COUNT steps up from the current frame. */
2185 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2187 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2190 /* Used to mask out junk bits from the return address, such as
2191 processor state, interrupt status, condition codes and the like. */
2192 #define MASK_RETURN_ADDR \
2193 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2194 in 26 bit mode, the condition codes must be masked out of the \
2195 return address. This does not apply to ARM6 and later processors \
2196 when running in 32 bit mode. */ \
2197 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2199 #endif /* __ARM_H__ */
OSDN Git Service
