1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
29 /* The archetecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
41 builtin_define ("__thumb__"); \
45 builtin_define ("__ARMEB__"); \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
53 builtin_define ("__ARMEL__"); \
55 builtin_define ("__THUMBEL__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
62 builtin_define ("__VFP_FP__"); \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (TARGET_INTERWORK) \
67 builtin_define ("__THUMB_INTERWORK__"); \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
81 /* The various ARM cores. */
84 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
86 #include "arm-cores.def"
88 /* Used to indicate that no processor has been specified. */
94 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
96 #include "arm-cores.def"
101 /* The processor for which instructions should be scheduled. */
102 extern enum processor_type arm_tune;
104 typedef enum arm_cond_code
106 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
107 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
111 extern arm_cc arm_current_cc;
113 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
115 extern int arm_target_label;
116 extern int arm_ccfsm_state;
117 extern GTY(()) rtx arm_target_insn;
118 /* Run-time compilation parameters selecting different hardware subsets. */
119 extern int target_flags;
120 /* The floating point mode. */
121 extern const char *target_fpu_name;
122 /* For backwards compatibility. */
123 extern const char *target_fpe_name;
124 /* Whether to use floating point hardware. */
125 extern const char *target_float_abi_name;
126 /* Which ABI to use. */
127 extern const char *target_abi_name;
128 /* Define the information needed to generate branch insns. This is
129 stored from the compare operation. */
130 extern GTY(()) rtx arm_compare_op0;
131 extern GTY(()) rtx arm_compare_op1;
132 /* The label of the current constant pool. */
133 extern rtx pool_vector_label;
134 /* Set to 1 when a return insn is output, this means that the epilogue
136 extern int return_used_this_function;
137 /* Used to produce AOF syntax assembler. */
138 extern GTY(()) rtx aof_pic_label;
140 /* Just in case configure has failed to define anything. */
141 #ifndef TARGET_CPU_DEFAULT
142 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
147 #define CPP_SPEC "%(subtarget_cpp_spec) \
148 %{msoft-float:%{mhard-float: \
149 %e-msoft-float and -mhard_float may not be used together}} \
150 %{mbig-endian:%{mlittle-endian: \
151 %e-mbig-endian and -mlittle-endian may not be used together}}"
157 /* This macro defines names of additional specifications to put in the specs
158 that can be used in various specifications like CC1_SPEC. Its definition
159 is an initializer with a subgrouping for each command option.
161 Each subgrouping contains a string constant, that defines the
162 specification name, and a string constant that used by the GCC driver
165 Do not define this macro if it does not need to do anything. */
166 #define EXTRA_SPECS \
167 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
168 SUBTARGET_EXTRA_SPECS
170 #ifndef SUBTARGET_EXTRA_SPECS
171 #define SUBTARGET_EXTRA_SPECS
174 #ifndef SUBTARGET_CPP_SPEC
175 #define SUBTARGET_CPP_SPEC ""
178 /* Run-time Target Specification. */
179 #ifndef TARGET_VERSION
180 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
183 /* Nonzero if the function prologue (and epilogue) should obey
184 the ARM Procedure Call Standard. */
185 #define ARM_FLAG_APCS_FRAME (1 << 0)
187 /* Nonzero if the function prologue should output the function name to enable
188 the post mortem debugger to print a backtrace (very useful on RISCOS,
189 unused on RISCiX). Specifying this flag also enables
190 -fno-omit-frame-pointer.
191 XXX Must still be implemented in the prologue. */
192 #define ARM_FLAG_POKE (1 << 1)
194 /* Nonzero if floating point instructions are emulated by the FPE, in which
195 case instruction scheduling becomes very uninteresting. */
196 #define ARM_FLAG_FPE (1 << 2)
198 /* FLAG 0x0008 now spare (used to be apcs-32 selection). */
200 /* Nonzero if stack checking should be performed on entry to each function
201 which allocates temporary variables on the stack. */
202 #define ARM_FLAG_APCS_STACK (1 << 4)
204 /* Nonzero if floating point parameters should be passed to functions in
205 floating point registers. */
206 #define ARM_FLAG_APCS_FLOAT (1 << 5)
208 /* Nonzero if re-entrant, position independent code should be generated.
209 This is equivalent to -fpic. */
210 #define ARM_FLAG_APCS_REENT (1 << 6)
212 /* FLAG 0x0080 now spare (used to be alignment traps). */
213 /* Nonzero if all floating point instructions are missing (and there is no
214 emulator either). Generate function calls for all ops in this case. */
215 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
217 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
218 #define ARM_FLAG_BIG_END (1 << 9)
220 /* Nonzero if we should compile for Thumb interworking. */
221 #define ARM_FLAG_INTERWORK (1 << 10)
223 /* Nonzero if we should have little-endian words even when compiling for
224 big-endian (for backwards compatibility with older versions of GCC). */
225 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
227 /* Nonzero if we need to protect the prolog from scheduling */
228 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
230 /* Nonzero if a call to abort should be generated if a noreturn
231 function tries to return. */
232 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
234 /* Nonzero if function prologues should not load the PIC register. */
235 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
237 /* Nonzero if all call instructions should be indirect. */
238 #define ARM_FLAG_LONG_CALLS (1 << 15)
240 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
241 #define ARM_FLAG_THUMB (1 << 16)
243 /* Set if a TPCS style stack frame should be generated, for non-leaf
244 functions, even if they do not need one. */
245 #define THUMB_FLAG_BACKTRACE (1 << 17)
247 /* Set if a TPCS style stack frame should be generated, for leaf
248 functions, even if they do not need one. */
249 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
251 /* Set if externally visible functions should assume that they
252 might be called in ARM mode, from a non-thumb aware code. */
253 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
255 /* Set if calls via function pointers should assume that their
256 destination is non-Thumb aware. */
257 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
259 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
260 #define CIRRUS_FIX_INVALID_INSNS (1 << 21)
262 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
263 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
264 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
265 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
266 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
267 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
268 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
269 #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
270 #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
271 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
272 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
273 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
274 #define TARGET_IWMMXT (arm_arch_iwmmxt)
275 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
276 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
277 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
278 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
279 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
280 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
281 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
282 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
283 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
284 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
285 #define TARGET_ARM (! TARGET_THUMB)
286 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
287 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
288 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
289 #define TARGET_BACKTRACE (leaf_function_p () \
290 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
291 : (target_flags & THUMB_FLAG_BACKTRACE))
292 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
293 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
294 #define TARGET_AAPCS_BASED \
295 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
297 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
298 #ifndef SUBTARGET_SWITCHES
299 #define SUBTARGET_SWITCHES
302 #define TARGET_SWITCHES \
304 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
305 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
306 N_("Generate APCS conformant stack frames") }, \
307 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
308 {"poke-function-name", ARM_FLAG_POKE, \
309 N_("Store function names in object code") }, \
310 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
311 {"fpe", ARM_FLAG_FPE, "" }, \
312 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
313 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
314 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
315 N_("Pass FP arguments in FP registers") }, \
316 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
317 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
318 N_("Generate re-entrant, PIC code") }, \
319 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
320 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
321 N_("Use library calls to perform FP operations") }, \
322 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
323 N_("Use hardware floating point instructions") }, \
324 {"big-endian", ARM_FLAG_BIG_END, \
325 N_("Assume target CPU is configured as big endian") }, \
326 {"little-endian", -ARM_FLAG_BIG_END, \
327 N_("Assume target CPU is configured as little endian") }, \
328 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
329 N_("Assume big endian bytes, little endian words") }, \
330 {"thumb-interwork", ARM_FLAG_INTERWORK, \
331 N_("Support calls between Thumb and ARM instruction sets") }, \
332 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
333 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
334 N_("Generate a call to abort if a noreturn function returns")}, \
335 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
336 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
337 N_("Do not move instructions into a function's prologue") }, \
338 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
339 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
340 N_("Do not load the PIC register in function prologues") }, \
341 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
342 {"long-calls", ARM_FLAG_LONG_CALLS, \
343 N_("Generate call insns as indirect calls, if necessary") }, \
344 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
345 {"thumb", ARM_FLAG_THUMB, \
346 N_("Compile for the Thumb not the ARM") }, \
347 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
348 {"arm", -ARM_FLAG_THUMB, "" }, \
349 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
350 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
351 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
352 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
353 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
354 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
355 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
356 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
357 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
359 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
360 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
361 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
363 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
364 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
365 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
366 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
368 {"", TARGET_DEFAULT, "" } \
371 #define TARGET_OPTIONS \
373 {"cpu=", & arm_select[0].string, \
374 N_("Specify the name of the target CPU"), 0}, \
375 {"arch=", & arm_select[1].string, \
376 N_("Specify the name of the target architecture"), 0}, \
377 {"tune=", & arm_select[2].string, "", 0}, \
378 {"fpe=", & target_fpe_name, "", 0}, \
379 {"fp=", & target_fpe_name, "", 0}, \
380 {"fpu=", & target_fpu_name, \
381 N_("Specify the name of the target floating point hardware/format"), 0}, \
382 {"float-abi=", & target_float_abi_name, \
383 N_("Specify if floating point hardware should be used"), 0}, \
384 {"structure-size-boundary=", & structure_size_string, \
385 N_("Specify the minimum bit alignment of structures"), 0}, \
386 {"pic-register=", & arm_pic_register_string, \
387 N_("Specify the register to be used for PIC addressing"), 0}, \
388 {"abi=", &target_abi_name, N_("Specify an ABI"), 0} \
391 /* Support for a compile-time default CPU, et cetera. The rules are:
392 --with-arch is ignored if -march or -mcpu are specified.
393 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
395 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
397 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
399 --with-fpu is ignored if -mfpu is specified.
400 --with-abi is ignored is -mabi is specified. */
401 #define OPTION_DEFAULT_SPECS \
402 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
403 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
404 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
406 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
407 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
408 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
410 struct arm_cpu_select
414 const struct processors * processors;
417 /* This is a magic array. If the user specifies a command line switch
418 which matches one of the entries in TARGET_OPTIONS then the corresponding
419 string pointer will be set to the value specified by the user. */
420 extern struct arm_cpu_select arm_select[];
422 /* Which floating point model to use. */
425 ARM_FP_MODEL_UNKNOWN,
426 /* FPA model (Hardware or software). */
428 /* Cirrus Maverick floating point model. */
429 ARM_FP_MODEL_MAVERICK,
430 /* VFP floating point model. */
434 extern enum arm_fp_model arm_fp_model;
436 /* Which floating point hardware is available. Also update
437 fp_model_for_fpu in arm.c when adding entries to this list. */
440 /* No FP hardware. */
442 /* Full FPA support. */
444 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
446 /* Emulated FPA hardware, Issue 3 emulator. */
448 /* Cirrus Maverick floating point co-processor. */
454 /* Recast the floating point class to be the floating point attribute. */
455 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
457 /* What type of floating point to tune for */
458 extern enum fputype arm_fpu_tune;
460 /* What type of floating point instructions are available */
461 extern enum fputype arm_fpu_arch;
466 ARM_FLOAT_ABI_SOFTFP,
470 extern enum float_abi_type arm_float_abi;
472 /* Which ABI to use. */
481 extern enum arm_abi_type arm_abi;
483 #ifndef ARM_DEFAULT_ABI
484 #define ARM_DEFAULT_ABI ARM_ABI_APCS
487 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
488 extern int arm_arch3m;
490 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
491 extern int arm_arch4;
493 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
494 extern int arm_arch5;
496 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
497 extern int arm_arch5e;
499 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
500 extern int arm_arch6;
502 /* Nonzero if this chip can benefit from load scheduling. */
503 extern int arm_ld_sched;
505 /* Nonzero if generating thumb code. */
506 extern int thumb_code;
508 /* Nonzero if this chip is a StrongARM. */
509 extern int arm_is_strong;
511 /* Nonzero if this chip is a Cirrus variant. */
512 extern int arm_arch_cirrus;
514 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
515 extern int arm_arch_iwmmxt;
517 /* Nonzero if this chip is an XScale. */
518 extern int arm_arch_xscale;
520 /* Nonzero if tuning for XScale */
521 extern int arm_tune_xscale;
523 /* Nonzero if this chip is an ARM6 or an ARM7. */
524 extern int arm_is_6_or_7;
526 #ifndef TARGET_DEFAULT
527 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
530 /* The frame pointer register used in gcc has nothing to do with debugging;
531 that is controlled by the APCS-FRAME option. */
532 #define CAN_DEBUG_WITHOUT_FP
534 #undef TARGET_MEM_FUNCTIONS
535 #define TARGET_MEM_FUNCTIONS 1
537 #define OVERRIDE_OPTIONS arm_override_options ()
539 /* Nonzero if PIC code requires explicit qualifiers to generate
540 PLT and GOT relocs rather than the assembler doing so implicitly.
541 Subtargets can override these if required. */
542 #ifndef NEED_GOT_RELOC
543 #define NEED_GOT_RELOC 0
545 #ifndef NEED_PLT_RELOC
546 #define NEED_PLT_RELOC 0
549 /* Nonzero if we need to refer to the GOT with a PC-relative
550 offset. In other words, generate
552 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
556 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
558 The default is true, which matches NetBSD. Subtargets can
559 override this if required. */
564 /* Target machine storage Layout. */
567 /* Define this macro if it is advisable to hold scalars in registers
568 in a wider mode than that declared by the program. In such cases,
569 the value is constrained to be within the bounds of the declared
570 type, but kept valid in the wider mode. The signedness of the
571 extension may differ from that of the type. */
573 /* It is far faster to zero extend chars than to sign extend them */
575 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
576 if (GET_MODE_CLASS (MODE) == MODE_INT \
577 && GET_MODE_SIZE (MODE) < 4) \
579 if (MODE == QImode) \
581 else if (MODE == HImode) \
586 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
587 if (GET_MODE_CLASS (MODE) == MODE_INT \
588 && GET_MODE_SIZE (MODE) < 4) \
591 /* Define this if most significant bit is lowest numbered
592 in instructions that operate on numbered bit-fields. */
593 #define BITS_BIG_ENDIAN 0
595 /* Define this if most significant byte of a word is the lowest numbered.
596 Most ARM processors are run in little endian mode, so that is the default.
597 If you want to have it run-time selectable, change the definition in a
598 cover file to be TARGET_BIG_ENDIAN. */
599 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
601 /* Define this if most significant word of a multiword number is the lowest
603 This is always false, even when in big-endian mode. */
604 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
606 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
607 on processor pre-defineds when compiling libgcc2.c. */
608 #if defined(__ARMEB__) && !defined(__ARMWEL__)
609 #define LIBGCC2_WORDS_BIG_ENDIAN 1
611 #define LIBGCC2_WORDS_BIG_ENDIAN 0
614 /* Define this if most significant word of doubles is the lowest numbered.
615 The rules are different based on whether or not we use FPA-format,
616 VFP-format or some other floating point co-processor's format doubles. */
617 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
619 #define UNITS_PER_WORD 4
621 /* True if natural alignment is used for doubleword types. */
622 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
624 #define DOUBLEWORD_ALIGNMENT 64
626 #define PARM_BOUNDARY 32
628 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
630 #define PREFERRED_STACK_BOUNDARY \
631 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
633 #define FUNCTION_BOUNDARY 32
635 /* The lowest bit is used to indicate Thumb-mode functions, so the
636 vbit must go into the delta field of pointers to member
638 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
640 #define EMPTY_FIELD_BOUNDARY 32
642 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
644 /* XXX Blah -- this macro is used directly by libobjc. Since it
645 supports no vector modes, cut out the complexity and fall back
646 on BIGGEST_FIELD_ALIGNMENT. */
647 #ifdef IN_TARGET_LIBS
648 #define BIGGEST_FIELD_ALIGNMENT 64
651 /* Make strings word-aligned so strcpy from constants will be faster. */
652 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
654 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
655 ((TREE_CODE (EXP) == STRING_CST \
656 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
657 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
659 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
660 value set in previous versions of this toolchain was 8, which produces more
661 compact structures. The command line option -mstructure_size_boundary=<n>
662 can be used to change this value. For compatibility with the ARM SDK
663 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
664 0020D) page 2-20 says "Structures are aligned on word boundaries".
665 The AAPCS specifies a value of 8. */
666 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
667 extern int arm_structure_size_boundary;
669 /* This is the value used to initialize arm_structure_size_boundary. If a
670 particular arm target wants to change the default value it should change
671 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
672 for an example of this. */
673 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
674 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
677 /* Used when parsing command line option -mstructure_size_boundary. */
678 extern const char * structure_size_string;
680 /* Nonzero if move instructions will actually fail to work
681 when given unaligned data. */
682 #define STRICT_ALIGNMENT 1
684 /* wchar_t is unsigned under the AAPCS. */
686 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
688 #define WCHAR_TYPE_SIZE BITS_PER_WORD
692 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
695 /* AAPCS requires that structure alignment is affected by bitfields. */
696 #ifndef PCC_BITFIELD_TYPE_MATTERS
697 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
701 /* Standard register usage. */
703 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
704 (S - saved over call).
706 r0 * argument word/integer result
709 r4-r8 S register variable
710 r9 S (rfp) register variable (real frame pointer)
712 r10 F S (sl) stack limit (used by -mapcs-stack-check)
713 r11 F S (fp) argument pointer
714 r12 (ip) temp workspace
715 r13 F S (sp) lower end of current stack frame
716 r14 (lr) link address/workspace
717 r15 F (pc) program counter
719 f0 floating point result
720 f1-f3 floating point scratch
722 f4-f7 S floating point variable
724 cc This is NOT a real register, but is used internally
725 to represent things that use or set the condition
727 sfp This isn't either. It is used during rtl generation
728 since the offset between the frame pointer and the
729 auto's isn't known until after register allocation.
730 afp Nor this, we only need this because of non-local
731 goto. Without it fp appears to be used and the
732 elimination code won't get rid of sfp. It tracks
733 fp exactly at all times.
735 *: See CONDITIONAL_REGISTER_USAGE */
738 mvf0 Cirrus floating point result
739 mvf1-mvf3 Cirrus floating point scratch
740 mvf4-mvf15 S Cirrus floating point variable. */
742 /* s0-s15 VFP scratch (aka d0-d7).
743 s16-s31 S VFP variable (aka d8-d15).
744 vfpcc Not a real register. Represents the VFP condition
747 /* The stack backtrace structure is as follows:
748 fp points to here: | save code pointer | [fp]
749 | return link value | [fp, #-4]
750 | return sp value | [fp, #-8]
751 | return fp value | [fp, #-12]
752 [| saved r10 value |]
763 [| saved f7 value |] three words
764 [| saved f6 value |] three words
765 [| saved f5 value |] three words
766 [| saved f4 value |] three words
767 r0-r3 are not normally saved in a C function. */
769 /* 1 for registers that have pervasive standard uses
770 and are not available for the register allocator. */
771 #define FIXED_REGISTERS \
789 /* 1 for registers not available across function calls.
790 These must include the FIXED_REGISTERS and also any
791 registers that can be used without being saved.
792 The latter must include the registers where values are returned
793 and the register where structure-value addresses are passed.
794 Aside from that, you can include as many other registers as you like.
795 The CC is not preserved over function calls on the ARM 6, so it is
796 easier to assume this for all. SFP is preserved, since FP is. */
797 #define CALL_USED_REGISTERS \
815 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
816 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
819 #define CONDITIONAL_REGISTER_USAGE \
823 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
825 for (regno = FIRST_FPA_REGNUM; \
826 regno <= LAST_FPA_REGNUM; ++regno) \
827 fixed_regs[regno] = call_used_regs[regno] = 1; \
830 if (TARGET_THUMB && optimize_size) \
832 /* When optimizing for size, it's better not to use \
833 the HI regs, because of the overhead of stacking \
835 for (regno = FIRST_HI_REGNUM; \
836 regno <= LAST_HI_REGNUM; ++regno) \
837 fixed_regs[regno] = call_used_regs[regno] = 1; \
840 /* The link register can be clobbered by any branch insn, \
841 but we have no way to track that at present, so mark \
842 it as unavailable. */ \
844 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
846 if (TARGET_ARM && TARGET_HARD_FLOAT) \
848 if (TARGET_MAVERICK) \
850 for (regno = FIRST_FPA_REGNUM; \
851 regno <= LAST_FPA_REGNUM; ++ regno) \
852 fixed_regs[regno] = call_used_regs[regno] = 1; \
853 for (regno = FIRST_CIRRUS_FP_REGNUM; \
854 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
856 fixed_regs[regno] = 0; \
857 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
862 for (regno = FIRST_VFP_REGNUM; \
863 regno <= LAST_VFP_REGNUM; ++ regno) \
865 fixed_regs[regno] = 0; \
866 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
871 if (TARGET_REALLY_IWMMXT) \
873 regno = FIRST_IWMMXT_GR_REGNUM; \
874 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
875 and wCG1 as call-preserved registers. The 2002/11/21 \
876 revision changed this so that all wCG registers are \
877 scratch registers. */ \
878 for (regno = FIRST_IWMMXT_GR_REGNUM; \
879 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
880 fixed_regs[regno] = call_used_regs[regno] = 0; \
881 /* The XScale ABI has wR0 - wR9 as scratch registers, \
882 the rest as call-preserved registers. */ \
883 for (regno = FIRST_IWMMXT_REGNUM; \
884 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
886 fixed_regs[regno] = 0; \
887 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
891 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
893 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
894 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
896 else if (TARGET_APCS_STACK) \
898 fixed_regs[10] = 1; \
899 call_used_regs[10] = 1; \
901 if (TARGET_APCS_FRAME) \
903 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
904 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
906 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
909 /* These are a couple of extensions to the formats accepted
911 %@ prints out ASM_COMMENT_START
912 %r prints out REGISTER_PREFIX reg_names[arg] */
913 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
915 fputs (ASM_COMMENT_START, FILE); \
919 fputs (REGISTER_PREFIX, FILE); \
920 fputs (reg_names [va_arg (ARGS, int)], FILE); \
923 /* Round X up to the nearest word. */
924 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
926 /* Convert fron bytes to ints. */
927 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
929 /* The number of (integer) registers required to hold a quantity of type MODE.
930 Also used for VFP registers. */
931 #define ARM_NUM_REGS(MODE) \
932 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
934 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
935 #define ARM_NUM_REGS2(MODE, TYPE) \
936 ARM_NUM_INTS ((MODE) == BLKmode ? \
937 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
939 /* The number of (integer) argument register available. */
940 #define NUM_ARG_REGS 4
942 /* Return the register number of the N'th (integer) argument. */
943 #define ARG_REGISTER(N) (N - 1)
945 /* Specify the registers used for certain standard purposes.
946 The values of these macros are register numbers. */
948 /* The number of the last argument register. */
949 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
951 /* The numbers of the Thumb register ranges. */
952 #define FIRST_LO_REGNUM 0
953 #define LAST_LO_REGNUM 7
954 #define FIRST_HI_REGNUM 8
955 #define LAST_HI_REGNUM 11
957 /* The register that holds the return address in exception handlers. */
958 #define EXCEPTION_LR_REGNUM 2
960 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
961 as an invisible last argument (possible since varargs don't exist in
962 Pascal), so the following is not true. */
963 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
965 /* Define this to be where the real frame pointer is if it is not possible to
966 work out the offset between the frame pointer and the automatic variables
967 until after register allocation has taken place. FRAME_POINTER_REGNUM
968 should point to a special register that we will make sure is eliminated.
970 For the Thumb we have another problem. The TPCS defines the frame pointer
971 as r11, and GCC believes that it is always possible to use the frame pointer
972 as base register for addressing purposes. (See comments in
973 find_reloads_address()). But - the Thumb does not allow high registers,
974 including r11, to be used as base address registers. Hence our problem.
976 The solution used here, and in the old thumb port is to use r7 instead of
977 r11 as the hard frame pointer and to have special code to generate
978 backtrace structures on the stack (if required to do so via a command line
979 option) using r11. This is the only 'user visible' use of r11 as a frame
981 #define ARM_HARD_FRAME_POINTER_REGNUM 11
982 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
984 #define HARD_FRAME_POINTER_REGNUM \
986 ? ARM_HARD_FRAME_POINTER_REGNUM \
987 : THUMB_HARD_FRAME_POINTER_REGNUM)
989 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
991 /* Register to use for pushing function arguments. */
992 #define STACK_POINTER_REGNUM SP_REGNUM
994 /* ARM floating pointer registers. */
995 #define FIRST_FPA_REGNUM 16
996 #define LAST_FPA_REGNUM 23
998 #define FIRST_IWMMXT_GR_REGNUM 43
999 #define LAST_IWMMXT_GR_REGNUM 46
1000 #define FIRST_IWMMXT_REGNUM 47
1001 #define LAST_IWMMXT_REGNUM 62
1002 #define IS_IWMMXT_REGNUM(REGNUM) \
1003 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1004 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1005 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1007 /* Base register for access to local variables of the function. */
1008 #define FRAME_POINTER_REGNUM 25
1010 /* Base register for access to arguments of the function. */
1011 #define ARG_POINTER_REGNUM 26
1013 #define FIRST_CIRRUS_FP_REGNUM 27
1014 #define LAST_CIRRUS_FP_REGNUM 42
1015 #define IS_CIRRUS_REGNUM(REGNUM) \
1016 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1018 #define FIRST_VFP_REGNUM 63
1019 #define LAST_VFP_REGNUM 94
1020 #define IS_VFP_REGNUM(REGNUM) \
1021 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1023 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1024 /* + 16 Cirrus registers take us up to 43. */
1025 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1026 /* VFP adds 32 + 1 more. */
1027 #define FIRST_PSEUDO_REGISTER 96
1029 /* Value should be nonzero if functions must have frame pointers.
1030 Zero means the frame pointer need not be set up (and parms may be accessed
1031 via the stack pointer) in functions that seem suitable.
1032 If we have to have a frame pointer we might as well make use of it.
1033 APCS says that the frame pointer does not need to be pushed in leaf
1034 functions, or simple tail call functions. */
1035 #define FRAME_POINTER_REQUIRED \
1036 (current_function_has_nonlocal_label \
1037 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1039 /* Return number of consecutive hard regs needed starting at reg REGNO
1040 to hold something of mode MODE.
1041 This is ordinarily the length in words of a value of mode MODE
1042 but can be less for certain modes in special long registers.
1044 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1046 #define HARD_REGNO_NREGS(REGNO, MODE) \
1048 && REGNO >= FIRST_FPA_REGNUM \
1049 && REGNO != FRAME_POINTER_REGNUM \
1050 && REGNO != ARG_POINTER_REGNUM) \
1051 && !IS_VFP_REGNUM (REGNO) \
1052 ? 1 : ARM_NUM_REGS (MODE))
1054 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1055 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1056 arm_hard_regno_mode_ok ((REGNO), (MODE))
1058 /* Value is 1 if it is a good idea to tie two pseudo registers
1059 when one has mode MODE1 and one has mode MODE2.
1060 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1061 for any hard reg, then this must be 0 for correct output. */
1062 #define MODES_TIEABLE_P(MODE1, MODE2) \
1063 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1065 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1066 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1068 #define VALID_IWMMXT_REG_MODE(MODE) \
1069 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1071 /* The order in which register should be allocated. It is good to use ip
1072 since no saving is required (though calls clobber it) and it never contains
1073 function parameters. It is quite good to use lr since other calls may
1074 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1075 least likely to contain a function parameter; in addition results are
1078 #define REG_ALLOC_ORDER \
1080 3, 2, 1, 0, 12, 14, 4, 5, \
1081 6, 7, 8, 10, 9, 11, 13, 15, \
1082 16, 17, 18, 19, 20, 21, 22, 23, \
1083 27, 28, 29, 30, 31, 32, 33, 34, \
1084 35, 36, 37, 38, 39, 40, 41, 42, \
1085 43, 44, 45, 46, 47, 48, 49, 50, \
1086 51, 52, 53, 54, 55, 56, 57, 58, \
1089 78, 77, 76, 75, 74, 73, 72, 71, \
1090 70, 69, 68, 67, 66, 65, 64, 63, \
1091 79, 80, 81, 82, 83, 84, 85, 86, \
1092 87, 88, 89, 90, 91, 92, 93, 94, \
1096 /* Interrupt functions can only use registers that have already been
1097 saved by the prologue, even if they would normally be
1099 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1100 (! IS_INTERRUPT (cfun->machine->func_type) || \
1101 regs_ever_live[DST])
1103 /* Register and constant classes. */
1105 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1106 Now that the Thumb is involved it has become more complicated. */
1126 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1128 /* Give names of register classes as strings for dump file. */
1129 #define REG_CLASS_NAMES \
1147 /* Define which registers fit in which classes.
1148 This is an initializer for a vector of HARD_REG_SET
1149 of length N_REG_CLASSES. */
1150 #define REG_CLASS_CONTENTS \
1152 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1153 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1154 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1155 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1156 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1157 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1158 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1159 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1160 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1161 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1162 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1163 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1164 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1165 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1168 /* The same information, inverted:
1169 Return the class number of the smallest class containing
1170 reg number REGNO. This could be a conditional expression
1171 or could index an array. */
1172 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1174 /* FPA registers can't do subreg as all values are reformatted to internal
1175 precision. VFP registers may only be accessed in the mode they
1177 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1178 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1179 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1180 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1183 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1184 using r0-r4 for function arguments, r7 for the stack frame and don't
1185 have enough left over to do doubleword arithmetic. */
1186 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1187 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1188 || (CLASS) == CC_REG)
1190 /* The class value for index registers, and the one for base regs. */
1191 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1192 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1194 /* For the Thumb the high registers cannot be used as base registers
1195 when addressing quantities in QI or HI mode; if we don't know the
1196 mode, then we must be conservative. After reload we must also be
1197 conservative, since we can't support SP+reg addressing, and we
1198 can't fix up any bad substitutions. */
1199 #define MODE_BASE_REG_CLASS(MODE) \
1200 (TARGET_ARM ? GENERAL_REGS : \
1201 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1203 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1204 registers explicitly used in the rtl to be used as spill registers
1205 but prevents the compiler from extending the lifetime of these
1207 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1209 /* Get reg_class from a letter such as appears in the machine description.
1210 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1211 ARM, but several more letters for the Thumb. */
1212 #define REG_CLASS_FROM_LETTER(C) \
1213 ( (C) == 'f' ? FPA_REGS \
1214 : (C) == 'v' ? CIRRUS_REGS \
1215 : (C) == 'w' ? VFP_REGS \
1216 : (C) == 'y' ? IWMMXT_REGS \
1217 : (C) == 'z' ? IWMMXT_GR_REGS \
1218 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1219 : TARGET_ARM ? NO_REGS \
1220 : (C) == 'h' ? HI_REGS \
1221 : (C) == 'b' ? BASE_REGS \
1222 : (C) == 'k' ? STACK_REG \
1223 : (C) == 'c' ? CC_REG \
1226 /* The letters I, J, K, L and M in a register constraint string
1227 can be used to stand for particular ranges of immediate operands.
1228 This macro defines what the ranges are.
1229 C is the letter, and VALUE is a constant value.
1230 Return 1 if VALUE is in the range specified by C.
1231 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1232 J: valid indexing constants.
1233 K: ~value ok in rhs argument of data operand.
1234 L: -value ok in rhs argument of data operand.
1235 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1236 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1237 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1238 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1239 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1240 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1241 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1242 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1245 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1246 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1247 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1248 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1249 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1250 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1251 && ((VAL) & 3) == 0) : \
1252 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1253 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1256 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1258 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1260 /* Constant letter 'G' for the FP immediate constants.
1261 'H' means the same constant negated. */
1262 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1263 ((C) == 'G' ? arm_const_double_rtx (X) : \
1264 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1266 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1268 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1270 /* For the ARM, `Q' means that this is a memory operand that is just
1271 an offset from a register.
1272 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1273 address. This means that the symbol is in the text segment and can be
1274 accessed without using a load.
1275 'U' Prefixes an extended memory constraint where:
1276 'Uv' is an address valid for VFP load/store insns.
1277 'Uy' is an address valid for iwmmxt load/store insns.
1278 'Uq' is an address valid for ldrsb. */
1280 #define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
1281 (((C) == 'Q') ? (GET_CODE (OP) == MEM \
1282 && GET_CODE (XEXP (OP, 0)) == REG) : \
1283 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1284 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1285 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1286 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1287 ((C) == 'T') ? cirrus_memory_offset (OP) : \
1288 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1289 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
1290 ((C) == 'U' && (STR)[1] == 'q') \
1291 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1294 #define CONSTRAINT_LEN(C,STR) \
1295 ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
1297 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1298 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1299 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1301 #define EXTRA_CONSTRAINT_STR(X, C, STR) \
1303 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1304 : EXTRA_CONSTRAINT_THUMB (X, C))
1306 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1308 /* Given an rtx X being reloaded into a reg required to be
1309 in class CLASS, return the class of reg to actually use.
1310 In general this is just CLASS, but for the Thumb we prefer
1311 a LO_REGS class or a subset. */
1312 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1313 (TARGET_ARM ? (CLASS) : \
1314 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1316 /* Must leave BASE_REGS reloads alone */
1317 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1318 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1319 ? ((true_regnum (X) == -1 ? LO_REGS \
1320 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1324 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1325 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1326 ? ((true_regnum (X) == -1 ? LO_REGS \
1327 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1331 /* Return the register class of a scratch register needed to copy IN into
1332 or out of a register in CLASS in MODE. If it can be done directly,
1333 NO_REGS is returned. */
1334 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1335 /* Restrict which direct reloads are allowed for VFP regs. */ \
1336 ((TARGET_VFP && TARGET_HARD_FLOAT \
1337 && (CLASS) == VFP_REGS) \
1338 ? vfp_secondary_reload_class (MODE, X) \
1340 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1341 ? GENERAL_REGS : NO_REGS) \
1342 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1344 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1345 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1346 /* Restrict which direct reloads are allowed for VFP regs. */ \
1347 ((TARGET_VFP && TARGET_HARD_FLOAT \
1348 && (CLASS) == VFP_REGS) \
1349 ? vfp_secondary_reload_class (MODE, X) : \
1350 /* Cannot load constants into Cirrus registers. */ \
1351 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1352 && (CLASS) == CIRRUS_REGS \
1353 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1356 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1357 && CONSTANT_P (X)) \
1359 (((MODE) == HImode && ! arm_arch4 \
1360 && (GET_CODE (X) == MEM \
1361 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1362 && true_regnum (X) == -1))) \
1363 ? GENERAL_REGS : NO_REGS) \
1364 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1366 /* Try a machine-dependent way of reloading an illegitimate address
1367 operand. If we find one, push the reload and jump to WIN. This
1368 macro is used in only one place: `find_reloads_address' in reload.c.
1370 For the ARM, we wish to handle large displacements off a base
1371 register by splitting the addend across a MOV and the mem insn.
1372 This can cut the number of reloads needed. */
1373 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1376 if (GET_CODE (X) == PLUS \
1377 && GET_CODE (XEXP (X, 0)) == REG \
1378 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1379 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1380 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1382 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1383 HOST_WIDE_INT low, high; \
1385 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1386 low = ((val & 0xf) ^ 0x8) - 0x8; \
1387 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1388 /* Need to be careful, -256 is not a valid offset. */ \
1389 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1390 else if (MODE == SImode \
1391 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1392 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1393 /* Need to be careful, -4096 is not a valid offset. */ \
1394 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1395 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1396 /* Need to be careful, -256 is not a valid offset. */ \
1397 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1398 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1399 && TARGET_HARD_FLOAT && TARGET_FPA) \
1400 /* Need to be careful, -1024 is not a valid offset. */ \
1401 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1405 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1406 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1407 - (unsigned HOST_WIDE_INT) 0x80000000); \
1408 /* Check for overflow or zero */ \
1409 if (low == 0 || high == 0 || (high + low != val)) \
1412 /* Reload the high part into a base reg; leave the low part \
1414 X = gen_rtx_PLUS (GET_MODE (X), \
1415 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1418 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1419 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1420 VOIDmode, 0, 0, OPNUM, TYPE); \
1426 /* XXX If an HImode FP+large_offset address is converted to an HImode
1427 SP+large_offset address, then reload won't know how to fix it. It sees
1428 only that SP isn't valid for HImode, and so reloads the SP into an index
1429 register, but the resulting address is still invalid because the offset
1430 is too big. We fix it here instead by reloading the entire address. */
1431 /* We could probably achieve better results by defining PROMOTE_MODE to help
1432 cope with the variances between the Thumb's signed and unsigned byte and
1433 halfword load instructions. */
1434 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1436 if (GET_CODE (X) == PLUS \
1437 && GET_MODE_SIZE (MODE) < 4 \
1438 && GET_CODE (XEXP (X, 0)) == REG \
1439 && XEXP (X, 0) == stack_pointer_rtx \
1440 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1441 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1445 push_reload (orig_X, NULL_RTX, &X, NULL, \
1446 MODE_BASE_REG_CLASS (MODE), \
1447 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1452 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1454 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1456 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1458 /* Return the maximum number of consecutive registers
1459 needed to represent mode MODE in a register of class CLASS.
1460 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1461 #define CLASS_MAX_NREGS(CLASS, MODE) \
1462 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1464 /* If defined, gives a class of registers that cannot be used as the
1465 operand of a SUBREG that changes the mode of the object illegally. */
1467 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1468 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1470 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1471 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1472 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1473 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1474 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1475 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1476 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1477 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1478 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1481 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1483 /* Stack layout; function entry, exit and calling. */
1485 /* Define this if pushing a word on the stack
1486 makes the stack pointer a smaller address. */
1487 #define STACK_GROWS_DOWNWARD 1
1489 /* Define this if the nominal address of the stack frame
1490 is at the high-address end of the local variables;
1491 that is, each additional local variable allocated
1492 goes at a more negative offset in the frame. */
1493 #define FRAME_GROWS_DOWNWARD 1
1495 /* Offset within stack frame to start allocating local variables at.
1496 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1497 first local allocated. Otherwise, it is the offset to the BEGINNING
1498 of the first local allocated. */
1499 #define STARTING_FRAME_OFFSET 0
1501 /* If we generate an insn to push BYTES bytes,
1502 this says how many the stack pointer really advances by. */
1503 /* The push insns do not do this rounding implicitly.
1504 So don't define this. */
1505 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1507 /* Define this if the maximum size of all the outgoing args is to be
1508 accumulated and pushed during the prologue. The amount can be
1509 found in the variable current_function_outgoing_args_size. */
1510 #define ACCUMULATE_OUTGOING_ARGS 1
1512 /* Offset of first parameter from the argument pointer register value. */
1513 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1515 /* Value is the number of byte of arguments automatically
1516 popped when returning from a subroutine call.
1517 FUNDECL is the declaration node of the function (as a tree),
1518 FUNTYPE is the data type of the function (as a tree),
1519 or for a library call it is an identifier node for the subroutine name.
1520 SIZE is the number of bytes of arguments passed on the stack.
1522 On the ARM, the caller does not pop any of its arguments that were passed
1524 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1526 /* Define how to find the value returned by a library function
1527 assuming the value has mode MODE. */
1528 #define LIBCALL_VALUE(MODE) \
1529 (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
1530 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1531 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1532 : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
1533 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1534 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1535 : TARGET_IWMMXT_ABI && VECTOR_MODE_SUPPORTED_P (MODE) \
1536 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1537 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1539 /* Define how to find the value returned by a function.
1540 VALTYPE is the data type of the value (as a tree).
1541 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1542 otherwise, FUNC is 0. */
1543 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1544 arm_function_value (VALTYPE, FUNC);
1546 /* 1 if N is a possible register number for a function value.
1547 On the ARM, only r0 and f0 can return results. */
1548 /* On a Cirrus chip, mvf0 can return results. */
1549 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1550 ((REGNO) == ARG_REGISTER (1) \
1551 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1552 && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
1553 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1554 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1555 && TARGET_HARD_FLOAT && TARGET_FPA))
1557 /* How large values are returned */
1558 /* A C expression which can inhibit the returning of certain function values
1559 in registers, based on the type of value. */
1560 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1562 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1563 values must be in memory. On the ARM, they need only do so if larger
1564 than a word, or if they contain elements offset from zero in the struct. */
1565 #define DEFAULT_PCC_STRUCT_RETURN 0
1567 /* Flags for the call/call_value rtl operations set up by function_arg. */
1568 #define CALL_NORMAL 0x00000000 /* No special processing. */
1569 #define CALL_LONG 0x00000001 /* Always call indirect. */
1570 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1572 /* These bits describe the different types of function supported
1573 by the ARM backend. They are exclusive. ie a function cannot be both a
1574 normal function and an interworked function, for example. Knowing the
1575 type of a function is important for determining its prologue and
1577 Note value 7 is currently unassigned. Also note that the interrupt
1578 function types all have bit 2 set, so that they can be tested for easily.
1579 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1580 machine_function structure is initialized (to zero) func_type will
1581 default to unknown. This will force the first use of arm_current_func_type
1582 to call arm_compute_func_type. */
1583 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1584 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1585 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1586 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1587 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1588 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1589 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1591 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1593 /* In addition functions can have several type modifiers,
1594 outlined by these bit masks: */
1595 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1596 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1597 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1598 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1600 /* Some macros to test these flags. */
1601 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1602 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1603 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1604 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1605 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1608 /* Structure used to hold the function stack frame layout. Offsets are
1609 relative to the stack pointer on function entry. Positive offsets are
1610 in the direction of stack growth.
1611 Only soft_frame is used in thumb mode. */
1613 typedef struct arm_stack_offsets GTY(())
1615 int saved_args; /* ARG_POINTER_REGNUM. */
1616 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1618 int soft_frame; /* FRAME_POINTER_REGNUM. */
1619 int outgoing_args; /* STACK_POINTER_REGNUM. */
1623 /* A C structure for machine-specific, per-function data.
1624 This is added to the cfun structure. */
1625 typedef struct machine_function GTY(())
1627 /* Additional stack adjustment in __builtin_eh_throw. */
1628 rtx eh_epilogue_sp_ofs;
1629 /* Records if LR has to be saved for far jumps. */
1631 /* Records if ARG_POINTER was ever live. */
1632 int arg_pointer_live;
1633 /* Records if the save of LR has been eliminated. */
1634 int lr_save_eliminated;
1635 /* The size of the stack frame. Only valid after reload. */
1636 arm_stack_offsets stack_offsets;
1637 /* Records the type of the current function. */
1638 unsigned long func_type;
1639 /* Record if the function has a variable argument list. */
1640 int uses_anonymous_args;
1641 /* Records if sibcalls are blocked because an argument
1642 register is needed to preserve stack alignment. */
1643 int sibcall_blocked;
1647 /* A C type for declaring a variable that is used as the first argument of
1648 `FUNCTION_ARG' and other related values. For some target machines, the
1649 type `int' suffices and can hold the number of bytes of argument so far. */
1652 /* This is the number of registers of arguments scanned so far. */
1654 /* This is the number of iWMMXt register arguments scanned so far. */
1658 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1663 /* Define where to put the arguments to a function.
1664 Value is zero to push the argument on the stack,
1665 or a hard register in which to store the argument.
1667 MODE is the argument's machine mode.
1668 TYPE is the data type of the argument (as a tree).
1669 This is null for libcalls where that information may
1671 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1672 the preceding args and about the function being called.
1673 NAMED is nonzero if this argument is a named parameter
1674 (otherwise it is an extra parameter matching an ellipsis).
1676 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1677 other arguments are passed on the stack. If (NAMED == 0) (which happens
1678 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1679 defined), say it is passed in the stack (function_prologue will
1680 indeed make it pass in the stack if necessary). */
1681 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1682 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1684 /* For an arg passed partly in registers and partly in memory,
1685 this is the number of registers used.
1686 For args passed entirely in registers or entirely in memory, zero. */
1687 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1688 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1689 NUM_ARG_REGS > (CUM).nregs \
1690 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE)) \
1691 && (CUM).can_split) \
1692 ? NUM_ARG_REGS - (CUM).nregs : 0)
1694 /* A C expression that indicates when an argument must be passed by
1695 reference. If nonzero for an argument, a copy of that argument is
1696 made in memory and a pointer to the argument is passed instead of
1697 the argument itself. The pointer is passed in whatever way is
1698 appropriate for passing a pointer to that type. */
1699 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1700 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1702 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1703 for a call to a function whose data type is FNTYPE.
1704 For a library call, FNTYPE is 0.
1705 On the ARM, the offset starts at 0. */
1706 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1707 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1709 /* Update the data in CUM to advance over an argument
1710 of mode MODE and data type TYPE.
1711 (TYPE is null for libcalls where that information may not be available.) */
1712 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1714 if (VECTOR_MODE_SUPPORTED_P (MODE) \
1715 && (CUM).named_count > (CUM).nargs) \
1716 (CUM).iwmmxt_nregs += 1; \
1718 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1720 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1721 argument with the specified mode and type. If it is not defined,
1722 `PARM_BOUNDARY' is used for all arguments. */
1723 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1724 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1725 ? DOUBLEWORD_ALIGNMENT \
1728 /* 1 if N is a possible register number for function argument passing.
1729 On the ARM, r0-r3 are used to pass args. */
1730 #define FUNCTION_ARG_REGNO_P(REGNO) \
1731 (IN_RANGE ((REGNO), 0, 3) \
1732 || (TARGET_IWMMXT_ABI \
1733 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1735 /* Implement `va_arg'. */
1736 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1737 arm_va_arg (valist, type)
1740 /* If your target environment doesn't prefix user functions with an
1741 underscore, you may wish to re-define this to prevent any conflicts.
1742 e.g. AOF may prefix mcount with an underscore. */
1743 #ifndef ARM_MCOUNT_NAME
1744 #define ARM_MCOUNT_NAME "*mcount"
1747 /* Call the function profiler with a given profile label. The Acorn
1748 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1749 On the ARM the full profile code will look like:
1758 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1759 will output the .text section.
1761 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1762 ``prof'' doesn't seem to mind about this!
1764 Note - this version of the code is designed to work in both ARM and
1766 #ifndef ARM_FUNCTION_PROFILER
1767 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1772 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1773 IP_REGNUM, LR_REGNUM); \
1774 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1775 fputc ('\n', STREAM); \
1776 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1777 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1778 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1782 #ifdef THUMB_FUNCTION_PROFILER
1783 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1785 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1787 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1789 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1790 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1793 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1794 the stack pointer does not matter. The value is tested only in
1795 functions that have frame pointers.
1796 No definition is equivalent to always zero.
1798 On the ARM, the function epilogue recovers the stack pointer from the
1800 #define EXIT_IGNORE_STACK 1
1802 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1804 /* Determine if the epilogue should be output as RTL.
1805 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1806 #define USE_RETURN_INSN(ISCOND) \
1807 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1809 /* Definitions for register eliminations.
1811 This is an array of structures. Each structure initializes one pair
1812 of eliminable registers. The "from" register number is given first,
1813 followed by "to". Eliminations of the same "from" register are listed
1814 in order of preference.
1816 We have two registers that can be eliminated on the ARM. First, the
1817 arg pointer register can often be eliminated in favor of the stack
1818 pointer register. Secondly, the pseudo frame pointer register can always
1819 be eliminated; it is replaced with either the stack or the real frame
1820 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1821 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1823 #define ELIMINABLE_REGS \
1824 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1825 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1826 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1827 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1828 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1829 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1830 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1832 /* Given FROM and TO register numbers, say whether this elimination is
1833 allowed. Frame pointer elimination is automatically handled.
1835 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1836 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1837 pointer, we must eliminate FRAME_POINTER_REGNUM into
1838 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1839 ARG_POINTER_REGNUM. */
1840 #define CAN_ELIMINATE(FROM, TO) \
1841 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1842 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1843 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1844 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1847 #define THUMB_REG_PUSHED_P(reg) \
1848 (regs_ever_live [reg] \
1849 && (! call_used_regs [reg] \
1850 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1851 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1853 /* Define the offset between two registers, one to be eliminated, and the
1854 other its replacement, at the start of a routine. */
1855 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1857 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1859 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1861 /* Special case handling of the location of arguments passed on the stack. */
1862 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1864 /* Initialize data used by insn expanders. This is called from insn_emit,
1865 once for every function before code is generated. */
1866 #define INIT_EXPANDERS arm_init_expanders ()
1868 /* Output assembler code for a block containing the constant parts
1869 of a trampoline, leaving space for the variable parts.
1871 On the ARM, (if r8 is the static chain regnum, and remembering that
1872 referencing pc adds an offset of 8) the trampoline looks like:
1875 .word static chain value
1876 .word function's address
1877 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1878 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1880 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1881 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1882 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1883 PC_REGNUM, PC_REGNUM); \
1884 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1885 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1888 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1889 Why - because it is easier. This code will always be branched to via
1890 a BX instruction and since the compiler magically generates the address
1891 of the function the linker has no opportunity to ensure that the
1892 bottom bit is set. Thus the processor will be in ARM mode when it
1893 reaches this code. So we duplicate the ARM trampoline code and add
1894 a switch into Thumb mode as well. */
1895 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1897 fprintf (FILE, "\t.code 32\n"); \
1898 fprintf (FILE, ".Ltrampoline_start:\n"); \
1899 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1900 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1901 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1902 IP_REGNUM, PC_REGNUM); \
1903 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1904 IP_REGNUM, IP_REGNUM); \
1905 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1906 fprintf (FILE, "\t.word\t0\n"); \
1907 fprintf (FILE, "\t.word\t0\n"); \
1908 fprintf (FILE, "\t.code 16\n"); \
1911 #define TRAMPOLINE_TEMPLATE(FILE) \
1913 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1915 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1917 /* Length in units of the trampoline for entering a nested function. */
1918 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1920 /* Alignment required for a trampoline in bits. */
1921 #define TRAMPOLINE_ALIGNMENT 32
1923 /* Emit RTL insns to initialize the variable parts of a trampoline.
1924 FNADDR is an RTX for the address of the function's pure code.
1925 CXT is an RTX for the static chain value for the function. */
1926 #ifndef INITIALIZE_TRAMPOLINE
1927 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1929 emit_move_insn (gen_rtx_MEM (SImode, \
1930 plus_constant (TRAMP, \
1931 TARGET_ARM ? 8 : 16)), \
1933 emit_move_insn (gen_rtx_MEM (SImode, \
1934 plus_constant (TRAMP, \
1935 TARGET_ARM ? 12 : 20)), \
1941 /* Addressing modes, and classification of registers for them. */
1942 #define HAVE_POST_INCREMENT 1
1943 #define HAVE_PRE_INCREMENT TARGET_ARM
1944 #define HAVE_POST_DECREMENT TARGET_ARM
1945 #define HAVE_PRE_DECREMENT TARGET_ARM
1946 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1947 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1948 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1949 #define HAVE_POST_MODIFY_REG TARGET_ARM
1951 /* Macros to check register numbers against specific register classes. */
1953 /* These assume that REGNO is a hard or pseudo reg number.
1954 They give nonzero only if REGNO is a hard reg of the suitable class
1955 or a pseudo reg currently allocated to a suitable hard reg.
1956 Since they use reg_renumber, they are safe only once reg_renumber
1957 has been allocated, which happens in local-alloc.c. */
1958 #define TEST_REGNO(R, TEST, VALUE) \
1959 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1961 /* On the ARM, don't allow the pc to be used. */
1962 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1963 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1964 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1965 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1967 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1968 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1969 || (GET_MODE_SIZE (MODE) >= 4 \
1970 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1972 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1974 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1975 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1977 /* For ARM code, we don't care about the mode, but for Thumb, the index
1978 must be suitable for use in a QImode load. */
1979 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1980 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1982 /* Maximum number of registers that can appear in a valid memory address.
1983 Shifts in addresses can't be by a register. */
1984 #define MAX_REGS_PER_ADDRESS 2
1986 /* Recognize any constant value that is a valid address. */
1987 /* XXX We can address any constant, eventually... */
1989 #ifdef AOF_ASSEMBLER
1991 #define CONSTANT_ADDRESS_P(X) \
1992 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1996 #define CONSTANT_ADDRESS_P(X) \
1997 (GET_CODE (X) == SYMBOL_REF \
1998 && (CONSTANT_POOL_ADDRESS_P (X) \
1999 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2001 #endif /* AOF_ASSEMBLER */
2003 /* Nonzero if the constant value X is a legitimate general operand.
2004 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2006 On the ARM, allow any integer (invalid ones are removed later by insn
2007 patterns), nice doubles and symbol_refs which refer to the function's
2010 When generating pic allow anything. */
2011 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2013 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2014 ( GET_CODE (X) == CONST_INT \
2015 || GET_CODE (X) == CONST_DOUBLE \
2016 || CONSTANT_ADDRESS_P (X) \
2019 #define LEGITIMATE_CONSTANT_P(X) \
2020 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2022 /* Special characters prefixed to function names
2023 in order to encode attribute like information.
2024 Note, '@' and '*' have already been taken. */
2025 #define SHORT_CALL_FLAG_CHAR '^'
2026 #define LONG_CALL_FLAG_CHAR '#'
2028 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2029 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2031 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2032 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2034 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2035 #define SUBTARGET_NAME_ENCODING_LENGTHS
2038 /* This is a C fragment for the inside of a switch statement.
2039 Each case label should return the number of characters to
2040 be stripped from the start of a function's name, if that
2041 name starts with the indicated character. */
2042 #define ARM_NAME_ENCODING_LENGTHS \
2043 case SHORT_CALL_FLAG_CHAR: return 1; \
2044 case LONG_CALL_FLAG_CHAR: return 1; \
2045 case '*': return 1; \
2046 SUBTARGET_NAME_ENCODING_LENGTHS
2048 /* This is how to output a reference to a user-level label named NAME.
2049 `assemble_name' uses this. */
2050 #undef ASM_OUTPUT_LABELREF
2051 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2052 arm_asm_output_labelref (FILE, NAME)
2054 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2055 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2057 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2058 and check its validity for a certain class.
2059 We have two alternate definitions for each of them.
2060 The usual definition accepts all pseudo regs; the other rejects
2061 them unless they have been allocated suitable hard regs.
2062 The symbol REG_OK_STRICT causes the latter definition to be used. */
2063 #ifndef REG_OK_STRICT
2065 #define ARM_REG_OK_FOR_BASE_P(X) \
2066 (REGNO (X) <= LAST_ARM_REGNUM \
2067 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2068 || REGNO (X) == FRAME_POINTER_REGNUM \
2069 || REGNO (X) == ARG_POINTER_REGNUM)
2071 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2072 (REGNO (X) <= LAST_LO_REGNUM \
2073 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2074 || (GET_MODE_SIZE (MODE) >= 4 \
2075 && (REGNO (X) == STACK_POINTER_REGNUM \
2076 || (X) == hard_frame_pointer_rtx \
2077 || (X) == arg_pointer_rtx)))
2079 #define REG_STRICT_P 0
2081 #else /* REG_OK_STRICT */
2083 #define ARM_REG_OK_FOR_BASE_P(X) \
2084 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2086 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2087 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2089 #define REG_STRICT_P 1
2091 #endif /* REG_OK_STRICT */
2093 /* Now define some helpers in terms of the above. */
2095 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2097 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2098 : ARM_REG_OK_FOR_BASE_P (X))
2100 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2102 /* For Thumb, a valid index register is anything that can be used in
2103 a byte load instruction. */
2104 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2106 /* Nonzero if X is a hard reg that can be used as an index
2107 or if it is a pseudo reg. On the Thumb, the stack pointer
2109 #define REG_OK_FOR_INDEX_P(X) \
2111 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2112 : ARM_REG_OK_FOR_INDEX_P (X))
2115 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2116 that is a valid memory address for an instruction.
2117 The MODE argument is the machine mode for the MEM expression
2118 that wants to use this address. */
2120 #define ARM_BASE_REGISTER_RTX_P(X) \
2121 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2123 #define ARM_INDEX_REGISTER_RTX_P(X) \
2124 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2126 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2128 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2132 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2134 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2138 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2140 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2141 else /* if (TARGET_THUMB) */ \
2142 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2145 /* Try machine-dependent ways of modifying an illegitimate address
2146 to be legitimate. If we find one, return the new, valid address. */
2147 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2149 X = arm_legitimize_address (X, OLDX, MODE); \
2152 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2154 X = thumb_legitimize_address (X, OLDX, MODE); \
2157 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2160 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2162 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2164 if (memory_address_p (MODE, X)) \
2168 /* Go to LABEL if ADDR (a legitimate address expression)
2169 has an effect that depends on the machine mode it is used for. */
2170 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2172 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2173 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2177 /* Nothing helpful to do for the Thumb */
2178 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2180 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2183 /* Specify the machine mode that this machine uses
2184 for the index in the tablejump instruction. */
2185 #define CASE_VECTOR_MODE Pmode
2187 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2188 unsigned is probably best, but may break some code. */
2189 #ifndef DEFAULT_SIGNED_CHAR
2190 #define DEFAULT_SIGNED_CHAR 0
2193 /* Max number of bytes we can move from memory to memory
2194 in one reasonably fast instruction. */
2198 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2200 /* Define if operations between registers always perform the operation
2201 on the full register even if a narrower mode is specified. */
2202 #define WORD_REGISTER_OPERATIONS
2204 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2205 will either zero-extend or sign-extend. The value of this macro should
2206 be the code that says which one of the two operations is implicitly
2207 done, NIL if none. */
2208 #define LOAD_EXTEND_OP(MODE) \
2209 (TARGET_THUMB ? ZERO_EXTEND : \
2210 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2211 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2213 /* Nonzero if access to memory by bytes is slow and undesirable. */
2214 #define SLOW_BYTE_ACCESS 0
2216 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2218 /* Immediate shift counts are truncated by the output routines (or was it
2219 the assembler?). Shift counts in a register are truncated by ARM. Note
2220 that the native compiler puts too large (> 32) immediate shift counts
2221 into a register and shifts by the register, letting the ARM decide what
2222 to do instead of doing that itself. */
2223 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2224 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2225 On the arm, Y in a register is used modulo 256 for the shift. Only for
2226 rotates is modulo 32 used. */
2227 /* #define SHIFT_COUNT_TRUNCATED 1 */
2229 /* All integers have the same format so truncation is easy. */
2230 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2232 /* Calling from registers is a massive pain. */
2233 #define NO_FUNCTION_CSE 1
2235 /* The machine modes of pointers and functions */
2236 #define Pmode SImode
2237 #define FUNCTION_MODE Pmode
2239 #define ARM_FRAME_RTX(X) \
2240 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2241 || (X) == arg_pointer_rtx)
2243 /* Moves to and from memory are quite expensive */
2244 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2245 (TARGET_ARM ? 10 : \
2246 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2247 * (CLASS == LO_REGS ? 1 : 2)))
2249 /* Try to generate sequences that don't involve branches, we can then use
2250 conditional instructions */
2251 #define BRANCH_COST \
2252 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2254 /* Position Independent Code. */
2255 /* We decide which register to use based on the compilation options and
2256 the assembler in use; this is more general than the APCS restriction of
2257 using sb (r9) all the time. */
2258 extern int arm_pic_register;
2260 /* Used when parsing command line option -mpic-register=. */
2261 extern const char * arm_pic_register_string;
2263 /* The register number of the register used to address a table of static
2264 data addresses in memory. */
2265 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2267 #define FINALIZE_PIC arm_finalize_pic (1)
2269 /* We can't directly access anything that contains a symbol,
2270 nor can we indirect via the constant pool. */
2271 #define LEGITIMATE_PIC_OPERAND_P(X) \
2272 (!(symbol_mentioned_p (X) \
2273 || label_mentioned_p (X) \
2274 || (GET_CODE (X) == SYMBOL_REF \
2275 && CONSTANT_POOL_ADDRESS_P (X) \
2276 && (symbol_mentioned_p (get_pool_constant (X)) \
2277 || label_mentioned_p (get_pool_constant (X))))))
2279 /* We need to know when we are making a constant pool; this determines
2280 whether data needs to be in the GOT or can be referenced via a GOT
2282 extern int making_const_table;
2284 /* Handle pragmas for compatibility with Intel's compilers. */
2285 #define REGISTER_TARGET_PRAGMAS() do { \
2286 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2287 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2288 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2291 /* Condition code information. */
2292 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2293 return the mode to be used for the comparison. */
2295 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2297 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2299 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2302 if (GET_CODE (OP1) == CONST_INT \
2303 && ! (const_ok_for_arm (INTVAL (OP1)) \
2304 || (const_ok_for_arm (- INTVAL (OP1))))) \
2306 rtx const_op = OP1; \
2307 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2313 /* The arm5 clz instruction returns 32. */
2314 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2317 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2319 /* Output a push or a pop instruction (only used when profiling). */
2320 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2324 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2325 STACK_POINTER_REGNUM, REGNO); \
2327 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2331 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2335 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2336 STACK_POINTER_REGNUM, REGNO); \
2338 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2341 /* This is how to output a label which precedes a jumptable. Since
2342 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2343 #undef ASM_OUTPUT_CASE_LABEL
2344 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2348 ASM_OUTPUT_ALIGN (FILE, 2); \
2349 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2353 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2358 if (is_called_in_ARM_mode (DECL) \
2359 || current_function_is_thunk) \
2360 fprintf (STREAM, "\t.code 32\n") ; \
2362 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2364 if (TARGET_POKE_FUNCTION_NAME) \
2365 arm_poke_function_name (STREAM, (char *) NAME); \
2369 /* For aliases of functions we use .thumb_set instead. */
2370 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2373 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2374 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2376 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2378 fprintf (FILE, "\t.thumb_set "); \
2379 assemble_name (FILE, LABEL1); \
2380 fprintf (FILE, ","); \
2381 assemble_name (FILE, LABEL2); \
2382 fprintf (FILE, "\n"); \
2385 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2389 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2390 /* To support -falign-* switches we need to use .p2align so
2391 that alignment directives in code sections will be padded
2392 with no-op instructions, rather than zeroes. */
2393 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2396 if ((MAX_SKIP) == 0) \
2397 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2399 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2400 (int) (LOG), (int) (MAX_SKIP)); \
2404 /* Only perform branch elimination (by making instructions conditional) if
2405 we're optimizing. Otherwise it's of no use anyway. */
2406 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2407 if (TARGET_ARM && optimize) \
2408 arm_final_prescan_insn (INSN); \
2409 else if (TARGET_THUMB) \
2410 thumb_final_prescan_insn (INSN)
2412 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2413 (CODE == '@' || CODE == '|' \
2414 || (TARGET_ARM && (CODE == '?')) \
2415 || (TARGET_THUMB && (CODE == '_')))
2417 /* Output an operand of an instruction. */
2418 #define PRINT_OPERAND(STREAM, X, CODE) \
2419 arm_print_operand (STREAM, X, CODE)
2421 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2422 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2423 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2424 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2425 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2426 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2429 /* Output the address of an operand. */
2430 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2432 int is_minus = GET_CODE (X) == MINUS; \
2434 if (GET_CODE (X) == REG) \
2435 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2436 else if (GET_CODE (X) == PLUS || is_minus) \
2438 rtx base = XEXP (X, 0); \
2439 rtx index = XEXP (X, 1); \
2440 HOST_WIDE_INT offset = 0; \
2441 if (GET_CODE (base) != REG) \
2443 /* Ensure that BASE is a register. */ \
2444 /* (one of them must be). */ \
2449 switch (GET_CODE (index)) \
2452 offset = INTVAL (index); \
2455 asm_fprintf (STREAM, "[%r, #%wd]", \
2456 REGNO (base), offset); \
2460 asm_fprintf (STREAM, "[%r, %s%r]", \
2461 REGNO (base), is_minus ? "-" : "", \
2471 asm_fprintf (STREAM, "[%r, %s%r", \
2472 REGNO (base), is_minus ? "-" : "", \
2473 REGNO (XEXP (index, 0))); \
2474 arm_print_operand (STREAM, index, 'S'); \
2475 fputs ("]", STREAM); \
2483 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2484 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2486 extern enum machine_mode output_memory_reference_mode; \
2488 if (GET_CODE (XEXP (X, 0)) != REG) \
2491 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2492 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2493 REGNO (XEXP (X, 0)), \
2494 GET_CODE (X) == PRE_DEC ? "-" : "", \
2495 GET_MODE_SIZE (output_memory_reference_mode)); \
2497 asm_fprintf (STREAM, "[%r], #%s%d", \
2498 REGNO (XEXP (X, 0)), \
2499 GET_CODE (X) == POST_DEC ? "-" : "", \
2500 GET_MODE_SIZE (output_memory_reference_mode)); \
2502 else if (GET_CODE (X) == PRE_MODIFY) \
2504 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2505 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2506 asm_fprintf (STREAM, "#%wd]!", \
2507 INTVAL (XEXP (XEXP (X, 1), 1))); \
2509 asm_fprintf (STREAM, "%r]!", \
2510 REGNO (XEXP (XEXP (X, 1), 1))); \
2512 else if (GET_CODE (X) == POST_MODIFY) \
2514 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2515 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2516 asm_fprintf (STREAM, "#%wd", \
2517 INTVAL (XEXP (XEXP (X, 1), 1))); \
2519 asm_fprintf (STREAM, "%r", \
2520 REGNO (XEXP (XEXP (X, 1), 1))); \
2522 else output_addr_const (STREAM, X); \
2525 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2527 if (GET_CODE (X) == REG) \
2528 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2529 else if (GET_CODE (X) == POST_INC) \
2530 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2531 else if (GET_CODE (X) == PLUS) \
2533 if (GET_CODE (XEXP (X, 0)) != REG) \
2535 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2536 asm_fprintf (STREAM, "[%r, #%wd]", \
2537 REGNO (XEXP (X, 0)), \
2538 INTVAL (XEXP (X, 1))); \
2540 asm_fprintf (STREAM, "[%r, %r]", \
2541 REGNO (XEXP (X, 0)), \
2542 REGNO (XEXP (X, 1))); \
2545 output_addr_const (STREAM, X); \
2548 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2550 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2552 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2554 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2555 if (GET_CODE (X) != CONST_VECTOR \
2556 || ! arm_emit_vector_const (FILE, X)) \
2559 /* A C expression whose value is RTL representing the value of the return
2560 address for the frame COUNT steps up from the current frame. */
2562 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2563 arm_return_addr (COUNT, FRAME)
2565 /* Mask of the bits in the PC that contain the real return address
2566 when running in 26-bit mode. */
2567 #define RETURN_ADDR_MASK26 (0x03fffffc)
2569 /* Pick up the return address upon entry to a procedure. Used for
2570 dwarf2 unwind information. This also enables the table driven
2572 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2573 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2575 /* Used to mask out junk bits from the return address, such as
2576 processor state, interrupt status, condition codes and the like. */
2577 #define MASK_RETURN_ADDR \
2578 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2579 in 26 bit mode, the condition codes must be masked out of the \
2580 return address. This does not apply to ARM6 and later processors \
2581 when running in 32 bit mode. */ \
2582 ((arm_arch4 || TARGET_THUMB) \
2583 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2584 : arm_gen_return_addr_mask ())
2587 /* Define the codes that are matched by predicates in arm.c */
2588 #define PREDICATE_CODES \
2589 {"s_register_operand", {SUBREG, REG}}, \
2590 {"arm_general_register_operand", {SUBREG, REG}}, \
2591 {"arm_hard_register_operand", {REG}}, \
2592 {"f_register_operand", {SUBREG, REG}}, \
2593 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2594 {"arm_addimm_operand", {CONST_INT}}, \
2595 {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2596 {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2597 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2598 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2599 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2600 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2601 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2602 {"thumb_cmpneg_operand", {CONST_INT}}, \
2603 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2604 {"offsettable_memory_operand", {MEM}}, \
2605 {"alignable_memory_operand", {MEM}}, \
2606 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2607 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2608 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2609 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2610 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2611 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2612 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2613 {"load_multiple_operation", {PARALLEL}}, \
2614 {"store_multiple_operation", {PARALLEL}}, \
2615 {"equality_operator", {EQ, NE}}, \
2616 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2617 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2619 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2620 {"const_shift_operand", {CONST_INT}}, \
2621 {"multi_register_push", {PARALLEL}}, \
2622 {"cc_register", {REG}}, \
2623 {"logical_binary_operator", {AND, IOR, XOR}}, \
2624 {"cirrus_register_operand", {REG}}, \
2625 {"cirrus_fp_register", {REG}}, \
2626 {"cirrus_shift_const", {CONST_INT}}, \
2627 {"dominant_cc_register", {REG}}, \
2628 {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
2629 {"vfp_compare_operand", {REG, CONST_DOUBLE}},
2631 /* Define this if you have special predicates that know special things
2632 about modes. Genrecog will warn about certain forms of
2633 match_operand without a mode; if the operand predicate is listed in
2634 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2635 #define SPECIAL_MODE_PREDICATES \
2636 "cc_register", "dominant_cc_register",
2645 ARM_BUILTIN_WAVG2BR,
2646 ARM_BUILTIN_WAVG2HR,
2673 ARM_BUILTIN_TMOVMSKB,
2674 ARM_BUILTIN_TMOVMSKH,
2675 ARM_BUILTIN_TMOVMSKW,
2684 ARM_BUILTIN_WPACKHSS,
2685 ARM_BUILTIN_WPACKWSS,
2686 ARM_BUILTIN_WPACKDSS,
2687 ARM_BUILTIN_WPACKHUS,
2688 ARM_BUILTIN_WPACKWUS,
2689 ARM_BUILTIN_WPACKDUS,
2694 ARM_BUILTIN_WADDSSB,
2695 ARM_BUILTIN_WADDSSH,
2696 ARM_BUILTIN_WADDSSW,
2697 ARM_BUILTIN_WADDUSB,
2698 ARM_BUILTIN_WADDUSH,
2699 ARM_BUILTIN_WADDUSW,
2703 ARM_BUILTIN_WSUBSSB,
2704 ARM_BUILTIN_WSUBSSH,
2705 ARM_BUILTIN_WSUBSSW,
2706 ARM_BUILTIN_WSUBUSB,
2707 ARM_BUILTIN_WSUBUSH,
2708 ARM_BUILTIN_WSUBUSW,
2715 ARM_BUILTIN_WCMPEQB,
2716 ARM_BUILTIN_WCMPEQH,
2717 ARM_BUILTIN_WCMPEQW,
2718 ARM_BUILTIN_WCMPGTUB,
2719 ARM_BUILTIN_WCMPGTUH,
2720 ARM_BUILTIN_WCMPGTUW,
2721 ARM_BUILTIN_WCMPGTSB,
2722 ARM_BUILTIN_WCMPGTSH,
2723 ARM_BUILTIN_WCMPGTSW,
2725 ARM_BUILTIN_TEXTRMSB,
2726 ARM_BUILTIN_TEXTRMSH,
2727 ARM_BUILTIN_TEXTRMSW,
2728 ARM_BUILTIN_TEXTRMUB,
2729 ARM_BUILTIN_TEXTRMUH,
2730 ARM_BUILTIN_TEXTRMUW,
2780 ARM_BUILTIN_WUNPCKIHB,
2781 ARM_BUILTIN_WUNPCKIHH,
2782 ARM_BUILTIN_WUNPCKIHW,
2783 ARM_BUILTIN_WUNPCKILB,
2784 ARM_BUILTIN_WUNPCKILH,
2785 ARM_BUILTIN_WUNPCKILW,
2787 ARM_BUILTIN_WUNPCKEHSB,
2788 ARM_BUILTIN_WUNPCKEHSH,
2789 ARM_BUILTIN_WUNPCKEHSW,
2790 ARM_BUILTIN_WUNPCKEHUB,
2791 ARM_BUILTIN_WUNPCKEHUH,
2792 ARM_BUILTIN_WUNPCKEHUW,
2793 ARM_BUILTIN_WUNPCKELSB,
2794 ARM_BUILTIN_WUNPCKELSH,
2795 ARM_BUILTIN_WUNPCKELSW,
2796 ARM_BUILTIN_WUNPCKELUB,
2797 ARM_BUILTIN_WUNPCKELUH,
2798 ARM_BUILTIN_WUNPCKELUW,
2802 #endif /* ! GCC_ARM_H */
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