1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 #define TARGET_CPU_xscale 0x0100
52 /* Configure didn't specify. */
53 #define TARGET_CPU_generic 0x8000
55 typedef enum arm_cond_code
57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
62 extern arm_cc arm_current_cc;
63 extern const char * arm_condition_codes[];
65 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
67 extern int arm_target_label;
68 extern int arm_ccfsm_state;
69 extern struct rtx_def * arm_target_insn;
70 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 /* The floating point instruction architecture, can be 2 or 3 */
73 extern const char * target_fp_name;
74 /* Define the information needed to generate branch insns. This is
75 stored from the compare operation. Note that we can't use "rtx" here
76 since it hasn't been defined! */
77 extern struct rtx_def * arm_compare_op0;
78 extern struct rtx_def * arm_compare_op1;
79 /* The label of the current constant pool. */
80 extern struct rtx_def * pool_vector_label;
81 /* Set to 1 when a return insn is output, this means that the epilogue
83 extern int return_used_this_function;
84 /* Nonzero if the prologue must setup `fp'. */
85 extern int current_function_anonymous_args;
87 /* Just in case configure has failed to define anything. */
88 #ifndef TARGET_CPU_DEFAULT
89 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
92 /* If the configuration file doesn't specify the cpu, the subtarget may
93 override it. If it doesn't, then default to an ARM6. */
94 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
95 #undef TARGET_CPU_DEFAULT
97 #ifdef SUBTARGET_CPU_DEFAULT
98 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
107 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
108 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
110 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
111 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
113 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
114 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
116 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
117 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
119 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
120 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
122 Unrecognized value in TARGET_CPU_DEFAULT.
130 #ifndef CPP_PREDEFINES
131 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
135 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
136 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
138 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
140 /* Set the architecture define -- if -march= is set, then it overrides
141 the -mcpu= setting. */
142 #define CPP_CPU_ARCH_SPEC "\
143 %{march=arm2:-D__ARM_ARCH_2__} \
144 %{march=arm250:-D__ARM_ARCH_2__} \
145 %{march=arm3:-D__ARM_ARCH_2__} \
146 %{march=arm6:-D__ARM_ARCH_3__} \
147 %{march=arm600:-D__ARM_ARCH_3__} \
148 %{march=arm610:-D__ARM_ARCH_3__} \
149 %{march=arm7:-D__ARM_ARCH_3__} \
150 %{march=arm700:-D__ARM_ARCH_3__} \
151 %{march=arm710:-D__ARM_ARCH_3__} \
152 %{march=arm720:-D__ARM_ARCH_3__} \
153 %{march=arm7100:-D__ARM_ARCH_3__} \
154 %{march=arm7500:-D__ARM_ARCH_3__} \
155 %{march=arm7500fe:-D__ARM_ARCH_3__} \
156 %{march=arm7m:-D__ARM_ARCH_3M__} \
157 %{march=arm7dm:-D__ARM_ARCH_3M__} \
158 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
159 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
160 %{march=arm8:-D__ARM_ARCH_4__} \
161 %{march=arm810:-D__ARM_ARCH_4__} \
162 %{march=arm9:-D__ARM_ARCH_4T__} \
163 %{march=arm920:-D__ARM_ARCH_4__} \
164 %{march=arm920t:-D__ARM_ARCH_4T__} \
165 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
166 %{march=strongarm:-D__ARM_ARCH_4__} \
167 %{march=strongarm110:-D__ARM_ARCH_4__} \
168 %{march=strongarm1100:-D__ARM_ARCH_4__} \
169 %{march=xscale:-D__ARM_ARCH_5TE__} \
170 %{march=xscale:-D__XSCALE__} \
171 %{march=armv2:-D__ARM_ARCH_2__} \
172 %{march=armv2a:-D__ARM_ARCH_2__} \
173 %{march=armv3:-D__ARM_ARCH_3__} \
174 %{march=armv3m:-D__ARM_ARCH_3M__} \
175 %{march=armv4:-D__ARM_ARCH_4__} \
176 %{march=armv4t:-D__ARM_ARCH_4T__} \
177 %{march=armv5:-D__ARM_ARCH_5__} \
178 %{march=armv5t:-D__ARM_ARCH_5T__} \
179 %{march=armv5e:-D__ARM_ARCH_5E__} \
180 %{march=armv5te:-D__ARM_ARCH_5TE__} \
182 %{mcpu=arm2:-D__ARM_ARCH_2__} \
183 %{mcpu=arm250:-D__ARM_ARCH_2__} \
184 %{mcpu=arm3:-D__ARM_ARCH_2__} \
185 %{mcpu=arm6:-D__ARM_ARCH_3__} \
186 %{mcpu=arm600:-D__ARM_ARCH_3__} \
187 %{mcpu=arm610:-D__ARM_ARCH_3__} \
188 %{mcpu=arm7:-D__ARM_ARCH_3__} \
189 %{mcpu=arm700:-D__ARM_ARCH_3__} \
190 %{mcpu=arm710:-D__ARM_ARCH_3__} \
191 %{mcpu=arm720:-D__ARM_ARCH_3__} \
192 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
194 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
195 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
196 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
197 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
198 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
199 %{mcpu=arm8:-D__ARM_ARCH_4__} \
200 %{mcpu=arm810:-D__ARM_ARCH_4__} \
201 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
202 %{mcpu=arm920:-D__ARM_ARCH_4__} \
203 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
204 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
205 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
206 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
207 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
208 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
209 %{mcpu=xscale:-D__XSCALE__} \
210 %{!mcpu*:%(cpp_cpu_arch_default)}} \
213 /* Define __APCS_26__ if the PC also contains the PSR */
214 #define CPP_APCS_PC_SPEC "\
215 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
217 %{mapcs-26:-D__APCS_26__} \
218 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
221 #ifndef CPP_APCS_PC_DEFAULT_SPEC
222 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
225 #define CPP_FLOAT_SPEC "\
227 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
229 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
232 /* Default is hard float, which doesn't define anything */
233 #define CPP_FLOAT_DEFAULT_SPEC ""
235 #define CPP_ENDIAN_SPEC "\
238 %e-mbig-endian and -mlittle-endian may not be used together} \
239 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
240 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
241 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
244 /* Default is little endian. */
245 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
247 /* Add a define for interworking. Needed when building libgcc.a.
248 This must define __THUMB_INTERWORK__ to the pre-processor if
249 interworking is enabled by default. */
250 #ifndef CPP_INTERWORK_DEFAULT_SPEC
251 #define CPP_INTERWORK_DEFAULT_SPEC ""
254 #define CPP_INTERWORK_SPEC " \
255 %{mthumb-interwork: \
256 %{mno-thumb-interwork: %eIncompatible interworking options} \
257 -D__THUMB_INTERWORK__} \
258 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
263 /* This macro defines names of additional specifications to put in the specs
264 that can be used in various specifications like CC1_SPEC. Its definition
265 is an initializer with a subgrouping for each command option.
267 Each subgrouping contains a string constant, that defines the
268 specification name, and a string constant that used by the GNU CC driver
271 Do not define this macro if it does not need to do anything. */
272 #define EXTRA_SPECS \
273 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
274 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
275 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
276 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
277 { "cpp_float", CPP_FLOAT_SPEC }, \
278 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
279 { "cpp_endian", CPP_ENDIAN_SPEC }, \
280 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
281 { "cpp_isa", CPP_ISA_SPEC }, \
282 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
283 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
284 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
285 SUBTARGET_EXTRA_SPECS
287 #ifndef SUBTARGET_EXTRA_SPECS
288 #define SUBTARGET_EXTRA_SPECS
291 #ifndef SUBTARGET_CPP_SPEC
292 #define SUBTARGET_CPP_SPEC ""
295 /* Run-time Target Specification. */
296 #ifndef TARGET_VERSION
297 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
300 /* Nonzero if the function prologue (and epilogue) should obey
301 the ARM Procedure Call Standard. */
302 #define ARM_FLAG_APCS_FRAME (1 << 0)
304 /* Nonzero if the function prologue should output the function name to enable
305 the post mortem debugger to print a backtrace (very useful on RISCOS,
306 unused on RISCiX). Specifying this flag also enables
307 -fno-omit-frame-pointer.
308 XXX Must still be implemented in the prologue. */
309 #define ARM_FLAG_POKE (1 << 1)
311 /* Nonzero if floating point instructions are emulated by the FPE, in which
312 case instruction scheduling becomes very uninteresting. */
313 #define ARM_FLAG_FPE (1 << 2)
315 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
316 that assume restoration of the condition flags when returning from a
317 branch and link (ie a function). */
318 #define ARM_FLAG_APCS_32 (1 << 3)
320 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
322 /* Nonzero if stack checking should be performed on entry to each function
323 which allocates temporary variables on the stack. */
324 #define ARM_FLAG_APCS_STACK (1 << 4)
326 /* Nonzero if floating point parameters should be passed to functions in
327 floating point registers. */
328 #define ARM_FLAG_APCS_FLOAT (1 << 5)
330 /* Nonzero if re-entrant, position independent code should be generated.
331 This is equivalent to -fpic. */
332 #define ARM_FLAG_APCS_REENT (1 << 6)
334 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
335 be loaded using either LDRH or LDRB instructions. */
336 #define ARM_FLAG_MMU_TRAPS (1 << 7)
338 /* Nonzero if all floating point instructions are missing (and there is no
339 emulator either). Generate function calls for all ops in this case. */
340 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
342 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
343 #define ARM_FLAG_BIG_END (1 << 9)
345 /* Nonzero if we should compile for Thumb interworking. */
346 #define ARM_FLAG_INTERWORK (1 << 10)
348 /* Nonzero if we should have little-endian words even when compiling for
349 big-endian (for backwards compatibility with older versions of GCC). */
350 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
352 /* Nonzero if we need to protect the prolog from scheduling */
353 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
355 /* Nonzero if a call to abort should be generated if a noreturn
356 function tries to return. */
357 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
359 /* Nonzero if function prologues should not load the PIC register. */
360 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
362 /* Nonzero if all call instructions should be indirect. */
363 #define ARM_FLAG_LONG_CALLS (1 << 15)
365 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
366 #define ARM_FLAG_THUMB (1 << 16)
368 /* Set if a TPCS style stack frame should be generated, for non-leaf
369 functions, even if they do not need one. */
370 #define THUMB_FLAG_BACKTRACE (1 << 17)
372 /* Set if a TPCS style stack frame should be generated, for leaf
373 functions, even if they do not need one. */
374 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
376 /* Set if externally visible functions should assume that they
377 might be called in ARM mode, from a non-thumb aware code. */
378 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
380 /* Set if calls via function pointers should assume that their
381 destination is non-Thumb aware. */
382 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
384 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
385 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
386 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
387 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
388 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
389 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
390 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
391 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
392 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
393 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
394 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
395 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
396 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
397 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
398 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
399 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
400 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
401 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
402 #define TARGET_ARM (! TARGET_THUMB)
403 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
404 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
405 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
406 #define TARGET_BACKTRACE (leaf_function_p () \
407 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
408 : (target_flags & THUMB_FLAG_BACKTRACE))
410 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
411 Bit 31 is reserved. See riscix.h. */
412 #ifndef SUBTARGET_SWITCHES
413 #define SUBTARGET_SWITCHES
416 #define TARGET_SWITCHES \
418 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
419 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
420 N_("Generate APCS conformant stack frames") }, \
421 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
422 {"poke-function-name", ARM_FLAG_POKE, \
423 N_("Store function names in object code") }, \
424 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
425 {"fpe", ARM_FLAG_FPE, "" }, \
426 {"apcs-32", ARM_FLAG_APCS_32, \
427 N_("Use the 32bit version of the APCS") }, \
428 {"apcs-26", -ARM_FLAG_APCS_32, \
429 N_("Use the 26bit version of the APCS") }, \
430 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
431 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
432 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
433 N_("Pass FP arguments in FP registers") }, \
434 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
435 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
436 N_("Generate re-entrant, PIC code") }, \
437 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
438 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
439 N_("The MMU will trap on unaligned accesses") }, \
440 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
441 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
442 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
443 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
444 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
445 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
446 N_("Use library calls to perform FP operations") }, \
447 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
448 N_("Use hardware floating point instructions") }, \
449 {"big-endian", ARM_FLAG_BIG_END, \
450 N_("Assume target CPU is configured as big endian") }, \
451 {"little-endian", -ARM_FLAG_BIG_END, \
452 N_("Assume target CPU is configured as little endian") }, \
453 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
454 N_("Assume big endian bytes, little endian words") }, \
455 {"thumb-interwork", ARM_FLAG_INTERWORK, \
456 N_("Support calls between THUMB and ARM instructions sets") }, \
457 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
458 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
459 N_("Generate a call to abort if a noreturn function returns")}, \
460 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
461 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
462 N_("Do not move instructions into a function's prologue") }, \
463 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
464 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
465 N_("Do not load the PIC register in function prologues") }, \
466 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
467 {"long-calls", ARM_FLAG_LONG_CALLS, \
468 N_("Generate call insns as indirect calls, if necessary") }, \
469 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
470 {"thumb", ARM_FLAG_THUMB, \
471 N_("Compile for the Thumb not the ARM") }, \
472 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
473 {"arm", -ARM_FLAG_THUMB, "" }, \
474 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
475 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
476 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
477 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
478 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
479 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
480 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
481 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
482 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
484 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
485 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
486 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
489 {"", TARGET_DEFAULT, "" } \
492 #define TARGET_OPTIONS \
494 {"cpu=", & arm_select[0].string, \
495 N_("Specify the name of the target CPU") }, \
496 {"arch=", & arm_select[1].string, \
497 N_("Specify the name of the target architecture") }, \
498 {"tune=", & arm_select[2].string, "" }, \
499 {"fpe=", & target_fp_name, "" }, \
500 {"fp=", & target_fp_name, \
501 N_("Specify the version of the floating point emulator") }, \
502 {"structure-size-boundary=", & structure_size_string, \
503 N_("Specify the minimum bit alignment of structures") }, \
504 {"pic-register=", & arm_pic_register_string, \
505 N_("Specify the register to be used for PIC addressing") } \
508 struct arm_cpu_select
512 const struct processors * processors;
515 /* This is a magic array. If the user specifies a command line switch
516 which matches one of the entries in TARGET_OPTIONS then the corresponding
517 string pointer will be set to the value specified by the user. */
518 extern struct arm_cpu_select arm_select[];
526 /* Recast the program mode class to be the prog_mode attribute */
527 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
529 extern enum prog_mode_type arm_prgmode;
531 /* What sort of floating point unit do we have? Hardware or software.
532 If software, is it issue 2 or issue 3? */
533 enum floating_point_type
540 /* Recast the floating point class to be the floating point attribute. */
541 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
543 /* What type of floating point to tune for */
544 extern enum floating_point_type arm_fpu;
546 /* What type of floating point instructions are available */
547 extern enum floating_point_type arm_fpu_arch;
549 /* Default floating point architecture. Override in sub-target if
551 #define FP_DEFAULT FP_SOFT2
553 /* Nonzero if the processor has a fast multiply insn, and one that does
554 a 64-bit multiply of two 32-bit values. */
555 extern int arm_fast_multiply;
557 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
558 extern int arm_arch4;
560 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
561 extern int arm_arch5;
563 /* Nonzero if this chip can benefit from load scheduling. */
564 extern int arm_ld_sched;
566 /* Nonzero if generating thumb code. */
567 extern int thumb_code;
569 /* Nonzero if this chip is a StrongARM. */
570 extern int arm_is_strong;
572 /* Nonzero if this chip is an XScale. */
573 extern int arm_is_xscale;
575 /* Nonzero if this chip is a an ARM6 or an ARM7. */
576 extern int arm_is_6_or_7;
578 #ifndef TARGET_DEFAULT
579 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
582 /* The frame pointer register used in gcc has nothing to do with debugging;
583 that is controlled by the APCS-FRAME option. */
584 #define CAN_DEBUG_WITHOUT_FP
586 #define TARGET_MEM_FUNCTIONS 1
588 #define OVERRIDE_OPTIONS arm_override_options ()
590 /* Nonzero if PIC code requires explicit qualifiers to generate
591 PLT and GOT relocs rather than the assembler doing so implicitly.
592 Subtargets can override these if required. */
593 #ifndef NEED_GOT_RELOC
594 #define NEED_GOT_RELOC 0
596 #ifndef NEED_PLT_RELOC
597 #define NEED_PLT_RELOC 0
600 /* Nonzero if we need to refer to the GOT with a PC-relative
601 offset. In other words, generate
603 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
607 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
609 The default is true, which matches NetBSD. Subtargets can
610 override this if required. */
615 /* Target machine storage Layout. */
618 /* Define this macro if it is advisable to hold scalars in registers
619 in a wider mode than that declared by the program. In such cases,
620 the value is constrained to be within the bounds of the declared
621 type, but kept valid in the wider mode. The signedness of the
622 extension may differ from that of the type. */
624 /* It is far faster to zero extend chars than to sign extend them */
626 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
627 if (GET_MODE_CLASS (MODE) == MODE_INT \
628 && GET_MODE_SIZE (MODE) < 4) \
630 if (MODE == QImode) \
632 else if (MODE == HImode) \
633 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
637 /* Define this macro if the promotion described by `PROMOTE_MODE'
638 should also be done for outgoing function arguments. */
639 /* This is required to ensure that push insns always push a word. */
640 #define PROMOTE_FUNCTION_ARGS
642 /* Define for XFmode extended real floating point support.
643 This will automatically cause REAL_ARITHMETIC to be defined. */
645 I think I have added all the code to make this work. Unfortunately,
646 early releases of the floating point emulation code on RISCiX used a
647 different format for extended precision numbers. On my RISCiX box there
648 is a bug somewhere which causes the machine to lock up when running enquire
649 with long doubles. There is the additional aspect that Norcroft C
650 treats long doubles as doubles and we ought to remain compatible.
651 Perhaps someone with an FPA coprocessor and not running RISCiX would like
652 to try this someday. */
653 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
655 /* Disable XFmode patterns in md file */
656 #define ENABLE_XF_PATTERNS 0
658 /* Define if you don't want extended real, but do want to use the
659 software floating point emulator for REAL_ARITHMETIC and
660 decimal <-> binary conversion. */
661 /* See comment above */
662 #define REAL_ARITHMETIC
664 /* Define this if most significant bit is lowest numbered
665 in instructions that operate on numbered bit-fields. */
666 #define BITS_BIG_ENDIAN 0
668 /* Define this if most significant byte of a word is the lowest numbered.
669 Most ARM processors are run in little endian mode, so that is the default.
670 If you want to have it run-time selectable, change the definition in a
671 cover file to be TARGET_BIG_ENDIAN. */
672 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
674 /* Define this if most significant word of a multiword number is the lowest
676 This is always false, even when in big-endian mode. */
677 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
679 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
680 on processor pre-defineds when compiling libgcc2.c. */
681 #if defined(__ARMEB__) && !defined(__ARMWEL__)
682 #define LIBGCC2_WORDS_BIG_ENDIAN 1
684 #define LIBGCC2_WORDS_BIG_ENDIAN 0
687 /* Define this if most significant word of doubles is the lowest numbered.
688 This is always true, even when in little-endian mode. */
689 #define FLOAT_WORDS_BIG_ENDIAN 1
691 /* Number of bits in an addressable storage unit */
692 #define BITS_PER_UNIT 8
694 #define BITS_PER_WORD 32
696 #define UNITS_PER_WORD 4
698 #define POINTER_SIZE 32
700 #define PARM_BOUNDARY 32
702 #define STACK_BOUNDARY 32
704 #define FUNCTION_BOUNDARY 32
706 #define EMPTY_FIELD_BOUNDARY 32
708 #define BIGGEST_ALIGNMENT 32
710 /* Make strings word-aligned so strcpy from constants will be faster. */
711 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
713 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
714 ((TREE_CODE (EXP) == STRING_CST \
715 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
716 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
718 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
719 value set in previous versions of this toolchain was 8, which produces more
720 compact structures. The command line option -mstructure_size_boundary=<n>
721 can be used to change this value. For compatability with the ARM SDK
722 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
723 0020D) page 2-20 says "Structures are aligned on word boundaries". */
724 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
725 extern int arm_structure_size_boundary;
727 /* This is the value used to initialise arm_structure_size_boundary. If a
728 particular arm target wants to change the default value it should change
729 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
730 for an example of this. */
731 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
732 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
735 /* Used when parsing command line option -mstructure_size_boundary. */
736 extern const char * structure_size_string;
738 /* Non-zero if move instructions will actually fail to work
739 when given unaligned data. */
740 #define STRICT_ALIGNMENT 1
742 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
745 /* Standard register usage. */
747 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
748 (S - saved over call).
750 r0 * argument word/integer result
753 r4-r8 S register variable
754 r9 S (rfp) register variable (real frame pointer)
756 r10 F S (sl) stack limit (used by -mapcs-stack-check)
757 r11 F S (fp) argument pointer
758 r12 (ip) temp workspace
759 r13 F S (sp) lower end of current stack frame
760 r14 (lr) link address/workspace
761 r15 F (pc) program counter
763 f0 floating point result
764 f1-f3 floating point scratch
766 f4-f7 S floating point variable
768 cc This is NOT a real register, but is used internally
769 to represent things that use or set the condition
771 sfp This isn't either. It is used during rtl generation
772 since the offset between the frame pointer and the
773 auto's isn't known until after register allocation.
774 afp Nor this, we only need this because of non-local
775 goto. Without it fp appears to be used and the
776 elimination code won't get rid of sfp. It tracks
777 fp exactly at all times.
779 *: See CONDITIONAL_REGISTER_USAGE */
781 /* The stack backtrace structure is as follows:
782 fp points to here: | save code pointer | [fp]
783 | return link value | [fp, #-4]
784 | return sp value | [fp, #-8]
785 | return fp value | [fp, #-12]
786 [| saved r10 value |]
797 [| saved f7 value |] three words
798 [| saved f6 value |] three words
799 [| saved f5 value |] three words
800 [| saved f4 value |] three words
801 r0-r3 are not normally saved in a C function. */
803 /* 1 for registers that have pervasive standard uses
804 and are not available for the register allocator. */
805 #define FIXED_REGISTERS \
813 /* 1 for registers not available across function calls.
814 These must include the FIXED_REGISTERS and also any
815 registers that can be used without being saved.
816 The latter must include the registers where values are returned
817 and the register where structure-value addresses are passed.
818 Aside from that, you can include as many other registers as you like.
819 The CC is not preserved over function calls on the ARM 6, so it is
820 easier to assume this for all. SFP is preserved, since FP is. */
821 #define CALL_USED_REGISTERS \
829 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
830 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
833 #define CONDITIONAL_REGISTER_USAGE \
835 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
838 for (regno = FIRST_ARM_FP_REGNUM; \
839 regno <= LAST_ARM_FP_REGNUM; ++regno) \
840 fixed_regs[regno] = call_used_regs[regno] = 1; \
844 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
845 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
847 else if (TARGET_APCS_STACK) \
849 fixed_regs[10] = 1; \
850 call_used_regs[10] = 1; \
852 if (TARGET_APCS_FRAME) \
854 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
855 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
857 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
860 /* These are a couple of extensions to the formats accecpted
862 %@ prints out ASM_COMMENT_START
863 %r prints out REGISTER_PREFIX reg_names[arg] */
864 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
866 fputs (ASM_COMMENT_START, FILE); \
870 fputs (REGISTER_PREFIX, FILE); \
871 fputs (reg_names [va_arg (ARGS, int)], FILE); \
874 /* Round X up to the nearest word. */
875 #define ROUND_UP(X) (((X) + 3) & ~3)
877 /* Convert fron bytes to ints. */
878 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
880 /* The number of (integer) registers required to hold a quantity of type MODE. */
881 #define NUM_REGS(MODE) \
882 NUM_INTS (GET_MODE_SIZE (MODE))
884 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
885 #define NUM_REGS2(MODE, TYPE) \
886 NUM_INTS ((MODE) == BLKmode ? \
887 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
889 /* The number of (integer) argument register available. */
890 #define NUM_ARG_REGS 4
892 /* Return the regiser number of the N'th (integer) argument. */
893 #define ARG_REGISTER(N) (N - 1)
895 /* RTX for structure returns. NULL means use a hidden first argument. */
896 #define STRUCT_VALUE 0
898 /* Specify the registers used for certain standard purposes.
899 The values of these macros are register numbers. */
901 /* The number of the last argument register. */
902 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
904 /* The number of the last "lo" register (thumb). */
905 #define LAST_LO_REGNUM 7
907 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
908 as an invisible last argument (possible since varargs don't exist in
909 Pascal), so the following is not true. */
910 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
912 /* Define this to be where the real frame pointer is if it is not possible to
913 work out the offset between the frame pointer and the automatic variables
914 until after register allocation has taken place. FRAME_POINTER_REGNUM
915 should point to a special register that we will make sure is eliminated.
917 For the Thumb we have another problem. The TPCS defines the frame pointer
918 as r11, and GCC belives that it is always possible to use the frame pointer
919 as base register for addressing purposes. (See comments in
920 find_reloads_address()). But - the Thumb does not allow high registers,
921 including r11, to be used as base address registers. Hence our problem.
923 The solution used here, and in the old thumb port is to use r7 instead of
924 r11 as the hard frame pointer and to have special code to generate
925 backtrace structures on the stack (if required to do so via a command line
926 option) using r11. This is the only 'user visable' use of r11 as a frame
928 #define ARM_HARD_FRAME_POINTER_REGNUM 11
929 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
930 #define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
931 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
933 /* Scratch register - used in all kinds of places, eg trampolines. */
936 /* Register to use for pushing function arguments. */
937 #define STACK_POINTER_REGNUM 13
938 #define SP_REGNUM STACK_POINTER_REGNUM
940 /* Register which holds return address from a subroutine call. */
943 /* Define this if the program counter is overloaded on a register. */
946 /* The number of the last ARM (integer) register. */
947 #define LAST_ARM_REGNUM 15
949 /* ARM floating pointer registers. */
950 #define FIRST_ARM_FP_REGNUM 16
951 #define LAST_ARM_FP_REGNUM 23
953 /* Internal, so that we don't need to refer to a raw number */
956 /* Base register for access to local variables of the function. */
957 #define FRAME_POINTER_REGNUM 25
959 /* Base register for access to arguments of the function. */
960 #define ARG_POINTER_REGNUM 26
962 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
963 #define FIRST_PSEUDO_REGISTER 27
965 /* Value should be nonzero if functions must have frame pointers.
966 Zero means the frame pointer need not be set up (and parms may be accessed
967 via the stack pointer) in functions that seem suitable.
968 If we have to have a frame pointer we might as well make use of it.
969 APCS says that the frame pointer does not need to be pushed in leaf
970 functions, or simple tail call functions. */
971 #define FRAME_POINTER_REQUIRED \
972 (current_function_has_nonlocal_label \
973 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
975 /* Return number of consecutive hard regs needed starting at reg REGNO
976 to hold something of mode MODE.
977 This is ordinarily the length in words of a value of mode MODE
978 but can be less for certain modes in special long registers.
980 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
982 #define HARD_REGNO_NREGS(REGNO, MODE) \
984 && REGNO >= FIRST_ARM_FP_REGNUM \
985 && REGNO != FRAME_POINTER_REGNUM \
986 && REGNO != ARG_POINTER_REGNUM) \
987 ? 1 : NUM_REGS (MODE))
989 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
990 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
992 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
993 so that there is always a second lo register available to hold the upper
994 part of the value. Probably we ought to ensure that the register is the
995 start of an even numbered register pair. */
996 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
998 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
999 ( REGNO <= LAST_ARM_REGNUM \
1000 || REGNO == FRAME_POINTER_REGNUM \
1001 || REGNO == ARG_POINTER_REGNUM \
1002 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1004 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1005 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
1007 /* Value is 1 if it is a good idea to tie two pseudo registers
1008 when one has mode MODE1 and one has mode MODE2.
1009 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1010 for any hard reg, then this must be 0 for correct output. */
1011 #define MODES_TIEABLE_P(MODE1, MODE2) \
1012 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1014 /* The order in which register should be allocated. It is good to use ip
1015 since no saving is required (though calls clobber it) and it never contains
1016 function parameters. It is quite good to use lr since other calls may
1017 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1018 least likely to contain a function parameter; in addition results are
1020 #define REG_ALLOC_ORDER \
1022 3, 2, 1, 0, 12, 14, 4, 5, \
1023 6, 7, 8, 10, 9, 11, 13, 15, \
1024 16, 17, 18, 19, 20, 21, 22, 23, \
1028 /* Register and constant classes. */
1030 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1031 Now that the Thumb is involved it has become more compilcated. */
1046 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1048 /* Give names of register classes as strings for dump file. */
1049 #define REG_CLASS_NAMES \
1062 /* Define which registers fit in which classes.
1063 This is an initializer for a vector of HARD_REG_SET
1064 of length N_REG_CLASSES. */
1065 #define REG_CLASS_CONTENTS \
1067 { 0x0000000 }, /* NO_REGS */ \
1068 { 0x0FF0000 }, /* FPU_REGS */ \
1069 { 0x00000FF }, /* LO_REGS */ \
1070 { 0x0002000 }, /* STACK_REG */ \
1071 { 0x00020FF }, /* BASE_REGS */ \
1072 { 0x000FF00 }, /* HI_REGS */ \
1073 { 0x1000000 }, /* CC_REG */ \
1074 { 0x200FFFF }, /* GENERAL_REGS */ \
1075 { 0x2FFFFFF } /* ALL_REGS */ \
1078 /* The same information, inverted:
1079 Return the class number of the smallest class containing
1080 reg number REGNO. This could be a conditional expression
1081 or could index an array. */
1082 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1084 /* The class value for index registers, and the one for base regs. */
1085 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1086 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1088 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1089 registers explicitly used in the rtl to be used as spill registers
1090 but prevents the compiler from extending the lifetime of these
1092 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1094 /* Get reg_class from a letter such as appears in the machine description.
1095 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1096 ARM, but several more letters for the Thumb. */
1097 #define REG_CLASS_FROM_LETTER(C) \
1098 ( (C) == 'f' ? FPU_REGS \
1099 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1100 : TARGET_ARM ? NO_REGS \
1101 : (C) == 'h' ? HI_REGS \
1102 : (C) == 'b' ? BASE_REGS \
1103 : (C) == 'k' ? STACK_REG \
1104 : (C) == 'c' ? CC_REG \
1107 /* The letters I, J, K, L and M in a register constraint string
1108 can be used to stand for particular ranges of immediate operands.
1109 This macro defines what the ranges are.
1110 C is the letter, and VALUE is a constant value.
1111 Return 1 if VALUE is in the range specified by C.
1112 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1113 J: valid indexing constants.
1114 K: ~value ok in rhs argument of data operand.
1115 L: -value ok in rhs argument of data operand.
1116 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1117 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1118 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1119 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1120 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1121 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1122 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1123 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1126 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1127 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1128 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1129 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1130 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1131 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1132 && ((VAL) & 3) == 0) : \
1133 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1134 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1137 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1139 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1141 /* Constant letter 'G' for the FPU immediate constants.
1142 'H' means the same constant negated. */
1143 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1144 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1145 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1147 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1149 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1151 /* For the ARM, `Q' means that this is a memory operand that is just
1152 an offset from a register.
1153 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1154 address. This means that the symbol is in the text segment and can be
1155 accessed without using a load. */
1157 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1158 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1159 (C) == 'R' ? (GET_CODE (OP) == MEM \
1160 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1161 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1162 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1165 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1166 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1167 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1169 #define EXTRA_CONSTRAINT(X, C) \
1171 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1173 /* Given an rtx X being reloaded into a reg required to be
1174 in class CLASS, return the class of reg to actually use.
1175 In general this is just CLASS, but for the Thumb we prefer
1176 a LO_REGS class or a subset. */
1177 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1178 (TARGET_ARM ? (CLASS) : \
1179 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1181 /* Must leave BASE_REGS reloads alone */
1182 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1183 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1184 ? ((true_regnum (X) == -1 ? LO_REGS \
1185 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1189 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1190 ((CLASS) != LO_REGS \
1191 ? ((true_regnum (X) == -1 ? LO_REGS \
1192 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1196 /* Return the register class of a scratch register needed to copy IN into
1197 or out of a register in CLASS in MODE. If it can be done directly,
1198 NO_REGS is returned. */
1199 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1201 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1202 ? GENERAL_REGS : NO_REGS) \
1203 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1205 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1206 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1208 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1209 && (GET_CODE (X) == MEM \
1210 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1211 && true_regnum (X) == -1))) \
1212 ? GENERAL_REGS : NO_REGS) \
1213 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1215 /* Try a machine-dependent way of reloading an illegitimate address
1216 operand. If we find one, push the reload and jump to WIN. This
1217 macro is used in only one place: `find_reloads_address' in reload.c.
1219 For the ARM, we wish to handle large displacements off a base
1220 register by splitting the addend across a MOV and the mem insn.
1221 This can cut the number of reloads needed. */
1222 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1225 if (GET_CODE (X) == PLUS \
1226 && GET_CODE (XEXP (X, 0)) == REG \
1227 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1228 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1229 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1231 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1232 HOST_WIDE_INT low, high; \
1234 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1235 low = ((val & 0xf) ^ 0x8) - 0x8; \
1236 else if (MODE == SImode \
1237 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1238 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1239 /* Need to be careful, -4096 is not a valid offset. */ \
1240 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1241 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1242 /* Need to be careful, -256 is not a valid offset. */ \
1243 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1244 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1245 && TARGET_HARD_FLOAT) \
1246 /* Need to be careful, -1024 is not a valid offset. */ \
1247 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1251 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1252 ^ HOST_UINT (0x80000000)) \
1253 - HOST_UINT (0x80000000)); \
1254 /* Check for overflow or zero */ \
1255 if (low == 0 || high == 0 || (high + low != val)) \
1258 /* Reload the high part into a base reg; leave the low part \
1260 X = gen_rtx_PLUS (GET_MODE (X), \
1261 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1264 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1265 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1272 /* ??? If an HImode FP+large_offset address is converted to an HImode
1273 SP+large_offset address, then reload won't know how to fix it. It sees
1274 only that SP isn't valid for HImode, and so reloads the SP into an index
1275 register, but the resulting address is still invalid because the offset
1276 is too big. We fix it here instead by reloading the entire address. */
1277 /* We could probably achieve better results by defining PROMOTE_MODE to help
1278 cope with the variances between the Thumb's signed and unsigned byte and
1279 halfword load instructions. */
1280 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1282 if (GET_CODE (X) == PLUS \
1283 && GET_MODE_SIZE (MODE) < 4 \
1284 && GET_CODE (XEXP (X, 0)) == REG \
1285 && XEXP (X, 0) == stack_pointer_rtx \
1286 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1287 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1291 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1293 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1298 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1300 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1302 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1304 /* Return the maximum number of consecutive registers
1305 needed to represent mode MODE in a register of class CLASS.
1306 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1307 #define CLASS_MAX_NREGS(CLASS, MODE) \
1308 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1310 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1311 #define REGISTER_MOVE_COST(FROM, TO) \
1313 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1314 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1316 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1318 /* Stack layout; function entry, exit and calling. */
1320 /* Define this if pushing a word on the stack
1321 makes the stack pointer a smaller address. */
1322 #define STACK_GROWS_DOWNWARD 1
1324 /* Define this if the nominal address of the stack frame
1325 is at the high-address end of the local variables;
1326 that is, each additional local variable allocated
1327 goes at a more negative offset in the frame. */
1328 #define FRAME_GROWS_DOWNWARD 1
1330 /* Offset within stack frame to start allocating local variables at.
1331 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1332 first local allocated. Otherwise, it is the offset to the BEGINNING
1333 of the first local allocated. */
1334 #define STARTING_FRAME_OFFSET 0
1336 /* If we generate an insn to push BYTES bytes,
1337 this says how many the stack pointer really advances by. */
1338 /* The push insns do not do this rounding implicitly.
1339 So don't define this. */
1340 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1342 /* Define this if the maximum size of all the outgoing args is to be
1343 accumulated and pushed during the prologue. The amount can be
1344 found in the variable current_function_outgoing_args_size. */
1345 #define ACCUMULATE_OUTGOING_ARGS 1
1347 /* Offset of first parameter from the argument pointer register value. */
1348 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1350 /* Value is the number of byte of arguments automatically
1351 popped when returning from a subroutine call.
1352 FUNDECL is the declaration node of the function (as a tree),
1353 FUNTYPE is the data type of the function (as a tree),
1354 or for a library call it is an identifier node for the subroutine name.
1355 SIZE is the number of bytes of arguments passed on the stack.
1357 On the ARM, the caller does not pop any of its arguments that were passed
1359 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1361 /* Define how to find the value returned by a library function
1362 assuming the value has mode MODE. */
1363 #define LIBCALL_VALUE(MODE) \
1364 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1365 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1366 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1368 /* Define how to find the value returned by a function.
1369 VALTYPE is the data type of the value (as a tree).
1370 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1371 otherwise, FUNC is 0. */
1372 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1373 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1375 /* 1 if N is a possible register number for a function value.
1376 On the ARM, only r0 and f0 can return results. */
1377 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1378 ((REGNO) == ARG_REGISTER (1) \
1379 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1381 /* How large values are returned */
1382 /* A C expression which can inhibit the returning of certain function values
1383 in registers, based on the type of value. */
1384 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1386 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1387 values must be in memory. On the ARM, they need only do so if larger
1388 than a word, or if they contain elements offset from zero in the struct. */
1389 #define DEFAULT_PCC_STRUCT_RETURN 0
1391 /* Flags for the call/call_value rtl operations set up by function_arg. */
1392 #define CALL_NORMAL 0x00000000 /* No special processing. */
1393 #define CALL_LONG 0x00000001 /* Always call indirect. */
1394 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1396 /* A C structure for machine-specific, per-function data. This is added
1397 to the cfun structure. */
1398 struct machine_function
1400 /* Records __builtin_return address. */
1401 struct rtx_def *ra_rtx;
1402 /* Additionsl stack adjustment in __builtin_eh_throw. */
1403 struct rtx_def *eh_epilogue_sp_ofs;
1404 /* Records if LR has to be saved for far jumps. */
1406 /* Records if ARG_POINTER was ever live. */
1407 int arg_pointer_live;
1410 /* A C type for declaring a variable that is used as the first argument of
1411 `FUNCTION_ARG' and other related values. For some target machines, the
1412 type `int' suffices and can hold the number of bytes of argument so far. */
1415 /* This is the number of registers of arguments scanned so far. */
1417 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1421 /* Define where to put the arguments to a function.
1422 Value is zero to push the argument on the stack,
1423 or a hard register in which to store the argument.
1425 MODE is the argument's machine mode.
1426 TYPE is the data type of the argument (as a tree).
1427 This is null for libcalls where that information may
1429 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1430 the preceding args and about the function being called.
1431 NAMED is nonzero if this argument is a named parameter
1432 (otherwise it is an extra parameter matching an ellipsis).
1434 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1435 other arguments are passed on the stack. If (NAMED == 0) (which happens
1436 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1437 passed in the stack (function_prologue will indeed make it pass in the
1438 stack if necessary). */
1439 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1440 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1442 /* For an arg passed partly in registers and partly in memory,
1443 this is the number of registers used.
1444 For args passed entirely in registers or entirely in memory, zero. */
1445 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1446 ( NUM_ARG_REGS > (CUM).nregs \
1447 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1448 ? NUM_ARG_REGS - (CUM).nregs : 0)
1450 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1451 for a call to a function whose data type is FNTYPE.
1452 For a library call, FNTYPE is 0.
1453 On the ARM, the offset starts at 0. */
1454 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1455 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1457 /* Update the data in CUM to advance over an argument
1458 of mode MODE and data type TYPE.
1459 (TYPE is null for libcalls where that information may not be available.) */
1460 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1461 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1463 /* 1 if N is a possible register number for function argument passing.
1464 On the ARM, r0-r3 are used to pass args. */
1465 #define FUNCTION_ARG_REGNO_P(REGNO) \
1466 ((REGNO) >= 0 && (REGNO) <= 3)
1471 /* A C expression that evaluates to true if it is ok to perform a sibling
1473 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1475 /* Perform any actions needed for a function that is receiving a variable
1476 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1477 of the current parameter. PRETEND_SIZE is a variable that should be set to
1478 the amount of stack that must be pushed by the prolog to pretend that our
1481 Normally, this macro will push all remaining incoming registers on the
1482 stack and set PRETEND_SIZE to the length of the registers pushed.
1484 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1485 named arg and all anonymous args onto the stack.
1486 XXX I know the prologue shouldn't be pushing registers, but it is faster
1488 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1490 extern int current_function_anonymous_args; \
1491 current_function_anonymous_args = 1; \
1492 if ((CUM).nregs < NUM_ARG_REGS) \
1493 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1496 /* Generate assembly output for the start of a function. */
1497 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1501 output_arm_prologue (STREAM, SIZE); \
1503 output_thumb_prologue (STREAM); \
1507 /* If your target environment doesn't prefix user functions with an
1508 underscore, you may wish to re-define this to prevent any conflicts.
1509 e.g. AOF may prefix mcount with an underscore. */
1510 #ifndef ARM_MCOUNT_NAME
1511 #define ARM_MCOUNT_NAME "*mcount"
1514 /* Call the function profiler with a given profile label. The Acorn
1515 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1516 On the ARM the full profile code will look like:
1525 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1526 will output the .text section.
1528 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1529 ``prof'' doesn't seem to mind about this! */
1530 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1535 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1536 IP_REGNUM, LR_REGNUM); \
1537 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1538 fputc ('\n', STREAM); \
1539 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1540 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1541 ASM_OUTPUT_INT (STREAM, sym); \
1544 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1546 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1547 fprintf (STREAM, "\tbl\tmcount\n"); \
1548 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1551 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1553 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1555 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1557 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1558 the stack pointer does not matter. The value is tested only in
1559 functions that have frame pointers.
1560 No definition is equivalent to always zero.
1562 On the ARM, the function epilogue recovers the stack pointer from the
1564 #define EXIT_IGNORE_STACK 1
1566 /* Generate the assembly code for function exit. */
1567 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1568 output_func_epilogue (SIZE)
1570 /* Determine if the epilogue should be output as RTL.
1571 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1572 #define USE_RETURN_INSN(ISCOND) \
1573 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1575 /* Definitions for register eliminations.
1577 This is an array of structures. Each structure initializes one pair
1578 of eliminable registers. The "from" register number is given first,
1579 followed by "to". Eliminations of the same "from" register are listed
1580 in order of preference.
1582 We have two registers that can be eliminated on the ARM. First, the
1583 arg pointer register can often be eliminated in favor of the stack
1584 pointer register. Secondly, the pseudo frame pointer register can always
1585 be eliminated; it is replaced with either the stack or the real frame
1586 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1587 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1589 #define ELIMINABLE_REGS \
1590 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1591 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1592 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1593 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1594 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1595 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1596 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1598 /* Given FROM and TO register numbers, say whether this elimination is
1599 allowed. Frame pointer elimination is automatically handled.
1601 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1602 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1603 pointer, we must eliminate FRAME_POINTER_REGNUM into
1604 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1605 ARG_POINTER_REGNUM. */
1606 #define CAN_ELIMINATE(FROM, TO) \
1607 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1608 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1609 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1610 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1613 /* Define the offset between two registers, one to be eliminated, and the
1614 other its replacement, at the start of a routine. */
1615 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1617 int volatile_func = arm_volatile_func (); \
1618 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1620 if (! current_function_needs_context || ! frame_pointer_needed) \
1625 else if ((FROM) == FRAME_POINTER_REGNUM \
1626 && (TO) == STACK_POINTER_REGNUM) \
1627 (OFFSET) = current_function_outgoing_args_size \
1628 + ROUND_UP (get_frame_size ()); \
1633 int saved_hard_reg = 0; \
1635 if (! volatile_func) \
1637 for (regno = 0; regno <= 10; regno++) \
1638 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1639 saved_hard_reg = 1, offset += 4; \
1640 if (! TARGET_APCS_FRAME \
1641 && ! frame_pointer_needed \
1642 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1643 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1644 saved_hard_reg = 1, offset += 4; \
1645 /* PIC register is a fixed reg, so call_used_regs set. */ \
1646 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1647 saved_hard_reg = 1, offset += 4; \
1648 for (regno = FIRST_ARM_FP_REGNUM; \
1649 regno <= LAST_ARM_FP_REGNUM; regno++) \
1650 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1653 if ((FROM) == FRAME_POINTER_REGNUM) \
1654 (OFFSET) = - offset; \
1657 if (! frame_pointer_needed) \
1659 if (! volatile_func \
1660 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1662 offset += current_function_outgoing_args_size; \
1663 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1668 /* Note: This macro must match the code in thumb_function_prologue(). */
1669 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1672 if ((FROM) == ARG_POINTER_REGNUM) \
1674 int count_regs = 0; \
1676 for (regno = 8; regno < 13; regno ++) \
1677 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1680 (OFFSET) += 4 * count_regs; \
1682 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1683 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1685 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1686 (OFFSET) += 4 * (count_regs + 1); \
1687 if (TARGET_BACKTRACE) \
1689 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1695 if ((TO) == STACK_POINTER_REGNUM) \
1697 (OFFSET) += current_function_outgoing_args_size; \
1698 (OFFSET) += ROUND_UP (get_frame_size ()); \
1702 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1704 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1706 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1708 /* Special case handling of the location of arguments passed on the stack. */
1709 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1711 /* Initialize data used by insn expanders. This is called from insn_emit,
1712 once for every function before code is generated. */
1713 #define INIT_EXPANDERS arm_init_expanders ()
1715 /* Output assembler code for a block containing the constant parts
1716 of a trampoline, leaving space for the variable parts.
1718 On the ARM, (if r8 is the static chain regnum, and remembering that
1719 referencing pc adds an offset of 8) the trampoline looks like:
1722 .word static chain value
1723 .word function's address
1724 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1725 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1727 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1728 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1729 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1730 PC_REGNUM, PC_REGNUM); \
1731 ASM_OUTPUT_INT (FILE, const0_rtx); \
1732 ASM_OUTPUT_INT (FILE, const0_rtx); \
1735 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1736 Why - because it is easier. This code will always be branched to via
1737 a BX instruction and since the compiler magically generates the address
1738 of the function the linker has no opportunity to ensure that the
1739 bottom bit is set. Thus the processor will be in ARM mode when it
1740 reaches this code. So we duplicate the ARM trampoline code and add
1741 a switch into Thumb mode as well. */
1742 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1744 fprintf (FILE, "\t.code 32\n"); \
1745 fprintf (FILE, ".Ltrampoline_start:\n"); \
1746 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1747 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1748 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1749 IP_REGNUM, PC_REGNUM); \
1750 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1751 IP_REGNUM, IP_REGNUM); \
1752 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1753 fprintf (FILE, "\t.word\t0\n"); \
1754 fprintf (FILE, "\t.word\t0\n"); \
1755 fprintf (FILE, "\t.code 16\n"); \
1758 #define TRAMPOLINE_TEMPLATE(FILE) \
1760 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1762 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1764 /* Length in units of the trampoline for entering a nested function. */
1765 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1767 /* Alignment required for a trampoline in units. */
1768 #define TRAMPOLINE_ALIGN 4
1770 /* Emit RTL insns to initialize the variable parts of a trampoline.
1771 FNADDR is an RTX for the address of the function's pure code.
1772 CXT is an RTX for the static chain value for the function. */
1773 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1776 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1778 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1782 /* Addressing modes, and classification of registers for them. */
1783 #define HAVE_POST_INCREMENT 1
1784 #define HAVE_PRE_INCREMENT TARGET_ARM
1785 #define HAVE_POST_DECREMENT TARGET_ARM
1786 #define HAVE_PRE_DECREMENT TARGET_ARM
1788 /* Macros to check register numbers against specific register classes. */
1790 /* These assume that REGNO is a hard or pseudo reg number.
1791 They give nonzero only if REGNO is a hard reg of the suitable class
1792 or a pseudo reg currently allocated to a suitable hard reg.
1793 Since they use reg_renumber, they are safe only once reg_renumber
1794 has been allocated, which happens in local-alloc.c. */
1795 #define TEST_REGNO(R, TEST, VALUE) \
1796 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1798 /* On the ARM, don't allow the pc to be used. */
1799 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1800 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1801 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1802 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1804 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1805 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1806 || (GET_MODE_SIZE (MODE) >= 4 \
1807 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1809 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1811 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1812 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1814 /* For ARM code, we don't care about the mode, but for Thumb, the index
1815 must be suitable for use in a QImode load. */
1816 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1817 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1819 /* Maximum number of registers that can appear in a valid memory address.
1820 Shifts in addresses can't be by a register. */
1821 #define MAX_REGS_PER_ADDRESS 2
1823 /* Recognize any constant value that is a valid address. */
1824 /* XXX We can address any constant, eventually... */
1826 #ifdef AOF_ASSEMBLER
1828 #define CONSTANT_ADDRESS_P(X) \
1829 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1833 #define CONSTANT_ADDRESS_P(X) \
1834 (GET_CODE (X) == SYMBOL_REF \
1835 && (CONSTANT_POOL_ADDRESS_P (X) \
1836 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1838 #endif /* AOF_ASSEMBLER */
1840 /* Nonzero if the constant value X is a legitimate general operand.
1841 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1843 On the ARM, allow any integer (invalid ones are removed later by insn
1844 patterns), nice doubles and symbol_refs which refer to the function's
1847 When generating pic allow anything. */
1848 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1850 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1851 ( GET_CODE (X) == CONST_INT \
1852 || GET_CODE (X) == CONST_DOUBLE \
1853 || CONSTANT_ADDRESS_P (X))
1855 #define LEGITIMATE_CONSTANT_P(X) \
1856 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1858 /* Special characters prefixed to function names
1859 in order to encode attribute like information.
1860 Note, '@' and '*' have already been taken. */
1861 #define SHORT_CALL_FLAG_CHAR '^'
1862 #define LONG_CALL_FLAG_CHAR '#'
1864 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1865 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1867 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1868 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1870 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1871 #define SUBTARGET_NAME_ENCODING_LENGTHS
1874 /* This is a C fragement for the inside of a switch statement.
1875 Each case label should return the number of characters to
1876 be stripped from the start of a function's name, if that
1877 name starts with the indicated character. */
1878 #define ARM_NAME_ENCODING_LENGTHS \
1879 case SHORT_CALL_FLAG_CHAR: return 1; \
1880 case LONG_CALL_FLAG_CHAR: return 1; \
1881 case '*': return 1; \
1882 SUBTARGET_NAME_ENCODING_LENGTHS
1884 /* This has to be handled by a function because more than part of the
1885 ARM backend uses function name prefixes to encode attributes. */
1886 #undef STRIP_NAME_ENCODING
1887 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1888 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1890 /* This is how to output a reference to a user-level label named NAME.
1891 `assemble_name' uses this. */
1892 #undef ASM_OUTPUT_LABELREF
1893 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1894 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1896 /* If we are referencing a function that is weak then encode a long call
1897 flag in the function name, otherwise if the function is static or
1898 or known to be defined in this file then encode a short call flag.
1899 This macro is used inside the ENCODE_SECTION macro. */
1900 #define ARM_ENCODE_CALL_TYPE(decl) \
1901 if (TREE_CODE (decl) == FUNCTION_DECL) \
1903 if (DECL_WEAK (decl)) \
1904 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1905 else if (! TREE_PUBLIC (decl)) \
1906 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1909 /* Symbols in the text segment can be accessed without indirecting via the
1910 constant pool; it may take an extra binary operation, but this is still
1911 faster than indirecting via memory. Don't do this when not optimizing,
1912 since we won't be calculating al of the offsets necessary to do this
1914 /* This doesn't work with AOF syntax, since the string table may be in
1915 a different AREA. */
1916 #ifndef AOF_ASSEMBLER
1917 #define ENCODE_SECTION_INFO(decl) \
1919 if (optimize > 0 && TREE_CONSTANT (decl) \
1920 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1922 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1923 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1924 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1926 ARM_ENCODE_CALL_TYPE (decl) \
1929 #define ENCODE_SECTION_INFO(decl) \
1931 ARM_ENCODE_CALL_TYPE (decl) \
1935 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1936 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1938 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1939 and check its validity for a certain class.
1940 We have two alternate definitions for each of them.
1941 The usual definition accepts all pseudo regs; the other rejects
1942 them unless they have been allocated suitable hard regs.
1943 The symbol REG_OK_STRICT causes the latter definition to be used. */
1944 #ifndef REG_OK_STRICT
1946 #define ARM_REG_OK_FOR_BASE_P(X) \
1947 (REGNO (X) <= LAST_ARM_REGNUM \
1948 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1949 || REGNO (X) == FRAME_POINTER_REGNUM \
1950 || REGNO (X) == ARG_POINTER_REGNUM)
1952 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1953 (REGNO (X) <= LAST_LO_REGNUM \
1954 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1955 || (GET_MODE_SIZE (MODE) >= 4 \
1956 && (REGNO (X) == STACK_POINTER_REGNUM \
1957 || (X) == hard_frame_pointer_rtx \
1958 || (X) == arg_pointer_rtx)))
1960 #else /* REG_OK_STRICT */
1962 #define ARM_REG_OK_FOR_BASE_P(X) \
1963 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1965 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1966 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1968 #endif /* REG_OK_STRICT */
1970 /* Now define some helpers in terms of the above. */
1972 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1974 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1975 : ARM_REG_OK_FOR_BASE_P (X))
1977 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1979 /* For Thumb, a valid index register is anything that can be used in
1980 a byte load instruction. */
1981 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1983 /* Nonzero if X is a hard reg that can be used as an index
1984 or if it is a pseudo reg. On the Thumb, the stack pointer
1986 #define REG_OK_FOR_INDEX_P(X) \
1988 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1989 : ARM_REG_OK_FOR_INDEX_P (X))
1992 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1993 that is a valid memory address for an instruction.
1994 The MODE argument is the machine mode for the MEM expression
1995 that wants to use this address.
1997 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1999 /* --------------------------------arm version----------------------------- */
2000 #define ARM_BASE_REGISTER_RTX_P(X) \
2001 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2003 #define ARM_INDEX_REGISTER_RTX_P(X) \
2004 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2006 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2007 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2008 only be small constants. */
2009 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2012 HOST_WIDE_INT range; \
2013 enum rtx_code code = GET_CODE (INDEX); \
2015 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2017 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2018 && INTVAL (INDEX) > -1024 \
2019 && (INTVAL (INDEX) & 3) == 0) \
2024 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2025 && GET_MODE_SIZE (MODE) <= 4) \
2027 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2028 && (! arm_arch4 || (MODE) != HImode)) \
2030 rtx xiop0 = XEXP (INDEX, 0); \
2031 rtx xiop1 = XEXP (INDEX, 1); \
2032 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2033 && power_of_two_operand (xiop1, SImode)) \
2035 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2036 && power_of_two_operand (xiop0, SImode)) \
2039 if (GET_MODE_SIZE (MODE) <= 4 \
2040 && (code == LSHIFTRT || code == ASHIFTRT \
2041 || code == ASHIFT || code == ROTATERT) \
2042 && (! arm_arch4 || (MODE) != HImode)) \
2044 rtx op = XEXP (INDEX, 1); \
2045 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2046 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2047 && INTVAL (op) <= 31) \
2050 /* NASTY: Since this limits the addressing of unsigned \
2052 range = ((MODE) == HImode || (MODE) == QImode) \
2053 ? (arm_arch4 ? 256 : 4095) : 4096; \
2054 if (code == CONST_INT && INTVAL (INDEX) < range \
2055 && INTVAL (INDEX) > -range) \
2061 /* Jump to LABEL if X is a valid address RTX. This must take
2062 REG_OK_STRICT into account when deciding about valid registers.
2064 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2065 floating SYMBOL_REF to the constant pool. Allow REG-only and
2066 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2067 forced though a static cell to ensure addressability. */
2068 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2070 if (ARM_BASE_REGISTER_RTX_P (X)) \
2072 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2073 && GET_CODE (XEXP (X, 0)) == REG \
2074 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2076 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2077 && (GET_CODE (X) == LABEL_REF \
2078 || (GET_CODE (X) == CONST \
2079 && GET_CODE (XEXP ((X), 0)) == PLUS \
2080 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2081 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2083 else if ((MODE) == TImode) \
2085 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2087 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2088 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2090 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2091 if (val == 4 || val == -4 || val == -8) \
2095 else if (GET_CODE (X) == PLUS) \
2097 rtx xop0 = XEXP (X, 0); \
2098 rtx xop1 = XEXP (X, 1); \
2100 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2101 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2102 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2103 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2105 /* Reload currently can't handle MINUS, so disable this for now */ \
2106 /* else if (GET_CODE (X) == MINUS) \
2108 rtx xop0 = XEXP (X,0); \
2109 rtx xop1 = XEXP (X,1); \
2111 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2112 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2114 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2115 && GET_CODE (X) == SYMBOL_REF \
2116 && CONSTANT_POOL_ADDRESS_P (X) \
2118 && symbol_mentioned_p (get_pool_constant (X)))) \
2120 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2121 && (GET_MODE_SIZE (MODE) <= 4) \
2122 && GET_CODE (XEXP (X, 0)) == REG \
2123 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2127 /* ---------------------thumb version----------------------------------*/
2128 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2129 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2130 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2131 && ((VAL) & 1) == 0) \
2132 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2133 && ((VAL) & 3) == 0))
2135 /* The AP may be eliminated to either the SP or the FP, so we use the
2136 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2138 /* ??? Verify whether the above is the right approach. */
2140 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2141 needs special handling also. */
2143 /* ??? Look at how the mips16 port solves this problem. It probably uses
2144 better ways to solve some of these problems. */
2146 /* Although it is not incorrect, we don't accept QImode and HImode
2147 addresses based on the frame pointer or arg pointer until the
2148 reload pass starts. This is so that eliminating such addresses
2149 into stack based ones won't produce impossible code. */
2150 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2152 /* ??? Not clear if this is right. Experiment. */ \
2153 if (GET_MODE_SIZE (MODE) < 4 \
2154 && ! (reload_in_progress || reload_completed) \
2155 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2156 || reg_mentioned_p (arg_pointer_rtx, X) \
2157 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2158 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2159 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2160 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2162 /* Accept any base register. SP only in SImode or larger. */ \
2163 else if (GET_CODE (X) == REG \
2164 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2166 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2167 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2168 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2170 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2171 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2172 && (GET_CODE (X) == LABEL_REF \
2173 || (GET_CODE (X) == CONST \
2174 && GET_CODE (XEXP (X, 0)) == PLUS \
2175 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2176 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2178 /* Post-inc indexing only supported for SImode and larger. */ \
2179 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2180 && GET_CODE (XEXP (X, 0)) == REG \
2181 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2183 else if (GET_CODE (X) == PLUS) \
2185 /* REG+REG address can be any two index registers. */ \
2186 /* We disallow FRAME+REG addressing since we know that FRAME \
2187 will be replaced with STACK, and SP relative addressing only \
2188 permits SP+OFFSET. */ \
2189 if (GET_MODE_SIZE (MODE) <= 4 \
2190 && GET_CODE (XEXP (X, 0)) == REG \
2191 && GET_CODE (XEXP (X, 1)) == REG \
2192 && XEXP (X, 0) != frame_pointer_rtx \
2193 && XEXP (X, 1) != frame_pointer_rtx \
2194 && XEXP (X, 0) != virtual_stack_vars_rtx \
2195 && XEXP (X, 1) != virtual_stack_vars_rtx \
2196 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2197 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2199 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2200 else if (GET_CODE (XEXP (X, 0)) == REG \
2201 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2202 || XEXP (X, 0) == arg_pointer_rtx) \
2203 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2204 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2206 /* REG+const has 10 bit offset for SP, but only SImode and \
2207 larger is supported. */ \
2208 /* ??? Should probably check for DI/DFmode overflow here \
2209 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2210 else if (GET_CODE (XEXP (X, 0)) == REG \
2211 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2212 && GET_MODE_SIZE (MODE) >= 4 \
2213 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2214 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2215 + GET_MODE_SIZE (MODE)) <= 1024 \
2216 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2218 else if (GET_CODE (XEXP (X, 0)) == REG \
2219 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2220 && GET_MODE_SIZE (MODE) >= 4 \
2221 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2222 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2225 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2226 && GET_CODE (X) == SYMBOL_REF \
2227 && CONSTANT_POOL_ADDRESS_P (X) \
2229 && symbol_mentioned_p (get_pool_constant (X)))) \
2233 /* ------------------------------------------------------------------- */
2234 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2236 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2237 else /* if (TARGET_THUMB) */ \
2238 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2239 /* ------------------------------------------------------------------- */
2241 /* Try machine-dependent ways of modifying an illegitimate address
2242 to be legitimate. If we find one, return the new, valid address.
2243 This macro is used in only one place: `memory_address' in explow.c.
2245 OLDX is the address as it was before break_out_memory_refs was called.
2246 In some cases it is useful to look at this to decide what needs to be done.
2248 MODE and WIN are passed so that this macro can use
2249 GO_IF_LEGITIMATE_ADDRESS.
2251 It is always safe for this macro to do nothing. It exists to recognize
2252 opportunities to optimize the output.
2254 On the ARM, try to convert [REG, #BIGCONST]
2255 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2256 where VALIDCONST == 0 in case of TImode. */
2257 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2259 if (GET_CODE (X) == PLUS) \
2261 rtx xop0 = XEXP (X, 0); \
2262 rtx xop1 = XEXP (X, 1); \
2264 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2265 xop0 = force_reg (SImode, xop0); \
2266 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2267 xop1 = force_reg (SImode, xop1); \
2268 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2269 && GET_CODE (xop1) == CONST_INT) \
2271 HOST_WIDE_INT n, low_n; \
2272 rtx base_reg, val; \
2273 n = INTVAL (xop1); \
2275 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2287 low_n = ((MODE) == TImode ? 0 \
2288 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2291 base_reg = gen_reg_rtx (SImode); \
2292 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2293 GEN_INT (n)), NULL_RTX); \
2294 emit_move_insn (base_reg, val); \
2295 (X) = (low_n == 0 ? base_reg \
2296 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2298 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2299 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2301 else if (GET_CODE (X) == MINUS) \
2303 rtx xop0 = XEXP (X, 0); \
2304 rtx xop1 = XEXP (X, 1); \
2306 if (CONSTANT_P (xop0)) \
2307 xop0 = force_reg (SImode, xop0); \
2308 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2309 xop1 = force_reg (SImode, xop1); \
2310 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2311 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2314 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2315 if (memory_address_p (MODE, X)) \
2319 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2321 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2323 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2325 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2327 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2329 /* Go to LABEL if ADDR (a legitimate address expression)
2330 has an effect that depends on the machine mode it is used for. */
2331 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2333 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2334 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2338 /* Nothing helpful to do for the Thumb */
2339 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2341 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2344 /* Specify the machine mode that this machine uses
2345 for the index in the tablejump instruction. */
2346 #define CASE_VECTOR_MODE Pmode
2348 /* Define as C expression which evaluates to nonzero if the tablejump
2349 instruction expects the table to contain offsets from the address of the
2351 Do not define this if the table should contain absolute addresses. */
2352 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2354 /* Specify the tree operation to be used to convert reals to integers. */
2355 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2357 /* This is the kind of divide that is easiest to do in the general case. */
2358 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2360 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2361 unsigned is probably best, but may break some code. */
2362 #ifndef DEFAULT_SIGNED_CHAR
2363 #define DEFAULT_SIGNED_CHAR 0
2366 /* Don't cse the address of the function being compiled. */
2367 #define NO_RECURSIVE_FUNCTION_CSE 1
2369 /* Max number of bytes we can move from memory to memory
2370 in one reasonably fast instruction. */
2374 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2376 /* Define if operations between registers always perform the operation
2377 on the full register even if a narrower mode is specified. */
2378 #define WORD_REGISTER_OPERATIONS
2380 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2381 will either zero-extend or sign-extend. The value of this macro should
2382 be the code that says which one of the two operations is implicitly
2383 done, NIL if none. */
2384 #define LOAD_EXTEND_OP(MODE) \
2385 (TARGET_THUMB ? ZERO_EXTEND : \
2386 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2387 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2389 /* Define this if zero-extension is slow (more than one real instruction).
2390 On the ARM, it is more than one instruction only if not fetching from
2392 /* #define SLOW_ZERO_EXTEND */
2394 /* Nonzero if access to memory by bytes is slow and undesirable. */
2395 #define SLOW_BYTE_ACCESS 0
2397 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2399 /* Immediate shift counts are truncated by the output routines (or was it
2400 the assembler?). Shift counts in a register are truncated by ARM. Note
2401 that the native compiler puts too large (> 32) immediate shift counts
2402 into a register and shifts by the register, letting the ARM decide what
2403 to do instead of doing that itself. */
2404 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2405 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2406 On the arm, Y in a register is used modulo 256 for the shift. Only for
2407 rotates is modulo 32 used. */
2408 /* #define SHIFT_COUNT_TRUNCATED 1 */
2410 /* All integers have the same format so truncation is easy. */
2411 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2413 /* Calling from registers is a massive pain. */
2414 #define NO_FUNCTION_CSE 1
2416 /* Chars and shorts should be passed as ints. */
2417 #define PROMOTE_PROTOTYPES 1
2419 /* The machine modes of pointers and functions */
2420 #define Pmode SImode
2421 #define FUNCTION_MODE Pmode
2423 #define ARM_FRAME_RTX(X) \
2424 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2425 || (X) == arg_pointer_rtx)
2427 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2428 return arm_rtx_costs (X, CODE, OUTER_CODE);
2430 /* Moves to and from memory are quite expensive */
2431 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2432 (TARGET_ARM ? 10 : \
2433 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2434 * (CLASS == LO_REGS ? 1 : 2)))
2436 /* All address computations that can be done are free, but rtx cost returns
2437 the same for practically all of them. So we weight the different types
2438 of address here in the order (most pref first):
2439 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2440 #define ARM_ADDRESS_COST(X) \
2441 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2442 || GET_CODE (X) == SYMBOL_REF) \
2444 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2445 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2447 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2448 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2449 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2450 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2451 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2452 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2456 #define THUMB_ADDRESS_COST(X) \
2457 ((GET_CODE (X) == REG \
2458 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2459 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2462 #define ADDRESS_COST(X) \
2463 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2465 /* Try to generate sequences that don't involve branches, we can then use
2466 conditional instructions */
2467 #define BRANCH_COST \
2468 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2470 /* A C statement to update the variable COST based on the relationship
2471 between INSN that is dependent on DEP through dependence LINK. */
2472 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2473 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2475 /* Position Independent Code. */
2476 /* We decide which register to use based on the compilation options and
2477 the assembler in use; this is more general than the APCS restriction of
2478 using sb (r9) all the time. */
2479 extern int arm_pic_register;
2481 /* Used when parsing command line option -mpic-register=. */
2482 extern const char * arm_pic_register_string;
2484 /* The register number of the register used to address a table of static
2485 data addresses in memory. */
2486 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2488 #define FINALIZE_PIC arm_finalize_pic ()
2490 /* We can't directly access anything that contains a symbol,
2491 nor can we indirect via the constant pool. */
2492 #define LEGITIMATE_PIC_OPERAND_P(X) \
2493 ( ! symbol_mentioned_p (X) \
2494 && ! label_mentioned_p (X) \
2495 && (! CONSTANT_POOL_ADDRESS_P (X) \
2496 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2497 && ! label_mentioned_p (get_pool_constant (X)))))
2499 /* We need to know when we are making a constant pool; this determines
2500 whether data needs to be in the GOT or can be referenced via a GOT
2502 extern int making_const_table;
2504 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2505 with arguments ARGS is a valid machine specific attribute for TYPE.
2506 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2507 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2508 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2510 /* If defined, a C expression whose value is zero if the attributes on
2511 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2512 two if they are nearly compatible (which causes a warning to be
2514 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2515 (arm_comp_type_attributes (TYPE1, TYPE2))
2517 /* If defined, a C statement that assigns default attributes to newly
2519 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2520 arm_set_default_type_attributes (TYPE)
2522 /* Handle pragmas for compatibility with Intel's compilers. */
2523 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2524 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2525 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2526 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2529 /* Condition code information. */
2530 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2531 return the mode to be used for the comparison.
2532 CCFPEmode should be used with floating inequalities,
2533 CCFPmode should be used with floating equalities.
2534 CC_NOOVmode should be used with SImode integer equalities.
2535 CC_Zmode should be used if only the Z flag is set correctly
2536 CCmode should be used otherwise. */
2538 #define EXTRA_CC_MODES \
2539 CC(CC_NOOVmode, "CC_NOOV") \
2540 CC(CC_Zmode, "CC_Z") \
2541 CC(CC_SWPmode, "CC_SWP") \
2542 CC(CCFPmode, "CCFP") \
2543 CC(CCFPEmode, "CCFPE") \
2544 CC(CC_DNEmode, "CC_DNE") \
2545 CC(CC_DEQmode, "CC_DEQ") \
2546 CC(CC_DLEmode, "CC_DLE") \
2547 CC(CC_DLTmode, "CC_DLT") \
2548 CC(CC_DGEmode, "CC_DGE") \
2549 CC(CC_DGTmode, "CC_DGT") \
2550 CC(CC_DLEUmode, "CC_DLEU") \
2551 CC(CC_DLTUmode, "CC_DLTU") \
2552 CC(CC_DGEUmode, "CC_DGEU") \
2553 CC(CC_DGTUmode, "CC_DGTU") \
2554 CC(CC_Cmode, "CC_C")
2556 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2558 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2560 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2563 if (GET_CODE (OP1) == CONST_INT \
2564 && ! (const_ok_for_arm (INTVAL (OP1)) \
2565 || (const_ok_for_arm (- INTVAL (OP1))))) \
2567 rtx const_op = OP1; \
2568 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2574 #define STORE_FLAG_VALUE 1
2578 /* Gcc puts the pool in the wrong place for ARM, since we can only
2579 load addresses a limited distance around the pc. We do some
2580 special munging to move the constant pool values to the correct
2581 point in the code. */
2582 #define MACHINE_DEPENDENT_REORG(INSN) \
2586 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2588 /* Output an internal label definition. */
2589 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2590 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2593 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2595 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2596 && !strcmp (PREFIX, "L")) \
2598 arm_ccfsm_state = 0; \
2599 arm_target_insn = NULL; \
2601 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2602 ASM_OUTPUT_LABEL (STREAM, s); \
2607 /* Output a push or a pop instruction (only used when profiling). */
2608 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2610 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2611 STACK_POINTER_REGNUM, REGNO); \
2613 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2616 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2618 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2619 STACK_POINTER_REGNUM, REGNO); \
2621 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2623 /* This is how to output a label which precedes a jumptable. Since
2624 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2625 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2629 ASM_OUTPUT_ALIGN (FILE, 2); \
2630 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2634 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2639 if (is_called_in_ARM_mode (DECL)) \
2640 fprintf (STREAM, "\t.code 32\n") ; \
2642 fprintf (STREAM, "\t.thumb_func\n") ; \
2644 if (TARGET_POKE_FUNCTION_NAME) \
2645 arm_poke_function_name (STREAM, (char *) NAME); \
2649 /* For aliases of functions we use .thumb_set instead. */
2650 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2653 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2654 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2656 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2658 fprintf (FILE, "\t.thumb_set "); \
2659 assemble_name (FILE, LABEL1); \
2660 fprintf (FILE, ","); \
2661 assemble_name (FILE, LABEL2); \
2662 fprintf (FILE, "\n"); \
2665 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2669 /* Target characters. */
2670 #define TARGET_BELL 007
2671 #define TARGET_BS 010
2672 #define TARGET_TAB 011
2673 #define TARGET_NEWLINE 012
2674 #define TARGET_VT 013
2675 #define TARGET_FF 014
2676 #define TARGET_CR 015
2678 /* Only perform branch elimination (by making instructions conditional) if
2679 we're optimising. Otherwise it's of no use anyway. */
2680 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2681 if (TARGET_ARM && optimize) \
2682 arm_final_prescan_insn (INSN); \
2683 else if (TARGET_THUMB) \
2684 thumb_final_prescan_insn (INSN)
2686 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2687 (CODE == '@' || CODE == '|' \
2688 || (TARGET_ARM && (CODE == '?')) \
2689 || (TARGET_THUMB && (CODE == '_')))
2691 /* Output an operand of an instruction. */
2692 #define PRINT_OPERAND(STREAM, X, CODE) \
2693 arm_print_operand (STREAM, X, CODE)
2695 /* Create an [unsigned] host sized integer declaration that
2696 avoids compiler warnings. */
2698 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2699 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2701 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2702 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2705 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2706 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2707 : (((x) & HOST_UINT (0xffffffff)) | \
2708 (((x) & HOST_UINT (0x80000000)) \
2709 ? ((~ HOST_INT (0)) \
2710 & ~ HOST_UINT(0xffffffff)) \
2713 /* Output the address of an operand. */
2714 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2716 int is_minus = GET_CODE (X) == MINUS; \
2718 if (GET_CODE (X) == REG) \
2719 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2720 else if (GET_CODE (X) == PLUS || is_minus) \
2722 rtx base = XEXP (X, 0); \
2723 rtx index = XEXP (X, 1); \
2724 HOST_WIDE_INT offset = 0; \
2725 if (GET_CODE (base) != REG) \
2727 /* Ensure that BASE is a register */ \
2728 /* (one of them must be). */ \
2733 switch (GET_CODE (index)) \
2736 offset = INTVAL (index); \
2739 asm_fprintf (STREAM, "[%r, #%d]", \
2740 REGNO (base), offset); \
2744 asm_fprintf (STREAM, "[%r, %s%r]", \
2745 REGNO (base), is_minus ? "-" : "", \
2755 asm_fprintf (STREAM, "[%r, %s%r", \
2756 REGNO (base), is_minus ? "-" : "", \
2757 REGNO (XEXP (index, 0))); \
2758 arm_print_operand (STREAM, index, 'S'); \
2759 fputs ("]", STREAM); \
2767 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2768 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2770 extern int output_memory_reference_mode; \
2772 if (GET_CODE (XEXP (X, 0)) != REG) \
2775 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2776 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2777 REGNO (XEXP (X, 0)), \
2778 GET_CODE (X) == PRE_DEC ? "-" : "", \
2779 GET_MODE_SIZE (output_memory_reference_mode));\
2781 asm_fprintf (STREAM, "[%r], #%s%d", \
2782 REGNO (XEXP (X, 0)), \
2783 GET_CODE (X) == POST_DEC ? "-" : "", \
2784 GET_MODE_SIZE (output_memory_reference_mode));\
2786 else output_addr_const (STREAM, X); \
2789 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2791 if (GET_CODE (X) == REG) \
2792 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2793 else if (GET_CODE (X) == POST_INC) \
2794 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2795 else if (GET_CODE (X) == PLUS) \
2797 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2798 asm_fprintf (STREAM, "[%r, #%d]", \
2799 REGNO (XEXP (X, 0)), \
2800 (int) INTVAL (XEXP (X, 1))); \
2802 asm_fprintf (STREAM, "[%r, %r]", \
2803 REGNO (XEXP (X, 0)), \
2804 REGNO (XEXP (X, 1))); \
2807 output_addr_const (STREAM, X); \
2810 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2812 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2814 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2816 /* Handles PIC addr specially */
2817 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2819 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2821 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2822 fputs (" - (", STREAM); \
2823 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2824 fputs (")", STREAM); \
2827 output_addr_const (STREAM, X); \
2829 /* Mark symbols as position independent. We only do this in the \
2830 .text segment, not in the .data segment. */ \
2831 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2832 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2834 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2835 fprintf (STREAM, "(GOTOFF)"); \
2836 else if (GET_CODE (X) == LABEL_REF) \
2837 fprintf (STREAM, "(GOTOFF)"); \
2839 fprintf (STREAM, "(GOT)"); \
2843 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2844 Used for C++ multiple inheritance. */
2845 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2848 int mi_delta = (DELTA); \
2849 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2851 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2854 mi_delta = - mi_delta; \
2855 while (mi_delta != 0) \
2857 if ((mi_delta & (3 << shift)) == 0) \
2861 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2862 mi_op, this_regno, this_regno, \
2863 mi_delta & (0xff << shift)); \
2864 mi_delta &= ~(0xff << shift); \
2868 fputs ("\tb\t", FILE); \
2869 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2870 if (NEED_PLT_RELOC) \
2871 fputs ("(PLT)", FILE); \
2872 fputc ('\n', FILE); \
2876 /* A C expression whose value is RTL representing the value of the return
2877 address for the frame COUNT steps up from the current frame. */
2879 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2880 arm_return_addr (COUNT, FRAME)
2882 /* Mask of the bits in the PC that contain the real return address
2883 when running in 26-bit mode. */
2884 #define RETURN_ADDR_MASK26 (0x03fffffc)
2886 /* Pick up the return address upon entry to a procedure. Used for
2887 dwarf2 unwind information. This also enables the table driven
2889 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2890 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2892 /* Used to mask out junk bits from the return address, such as
2893 processor state, interrupt status, condition codes and the like. */
2894 #define MASK_RETURN_ADDR \
2895 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2896 in 26 bit mode, the condition codes must be masked out of the \
2897 return address. This does not apply to ARM6 and later processors \
2898 when running in 32 bit mode. */ \
2899 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2900 : (GEN_INT ((unsigned long)0xffffffff)))
2903 /* Define the codes that are matched by predicates in arm.c */
2904 #define PREDICATE_CODES \
2905 {"s_register_operand", {SUBREG, REG}}, \
2906 {"f_register_operand", {SUBREG, REG}}, \
2907 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2908 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2909 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2910 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2911 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2912 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2913 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2914 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2915 {"offsettable_memory_operand", {MEM}}, \
2916 {"bad_signed_byte_operand", {MEM}}, \
2917 {"alignable_memory_operand", {MEM}}, \
2918 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2919 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2920 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2921 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2922 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2923 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2924 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2925 {"load_multiple_operation", {PARALLEL}}, \
2926 {"store_multiple_operation", {PARALLEL}}, \
2927 {"equality_operator", {EQ, NE}}, \
2928 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2929 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2931 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2932 {"const_shift_operand", {CONST_INT}}, \
2933 {"multi_register_push", {PARALLEL}}, \
2934 {"cc_register", {REG}}, \
2935 {"logical_binary_operator", {AND, IOR, XOR}}, \
2936 {"dominant_cc_register", {REG}},
2938 /* Define this if you have special predicates that know special things
2939 about modes. Genrecog will warn about certain forms of
2940 match_operand without a mode; if the operand predicate is listed in
2941 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2942 #define SPECIAL_MODE_PREDICATES \
2943 "cc_register", "dominant_cc_register",
2948 ARM_BUILTIN_PREFETCH,
2952 #define MD_INIT_BUILTINS \
2955 arm_init_builtins (); \
2959 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
2960 arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
2961 #endif /* __ARM_H__ */
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