1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
68 /* Add a define for interworking. \
69 Needed when building libgcc.a. */ \
70 if (arm_cpp_interwork) \
71 builtin_define ("__THUMB_INTERWORK__"); \
73 builtin_assert ("cpu=arm"); \
74 builtin_assert ("machine=arm"); \
76 builtin_define (arm_arch_name); \
77 if (arm_arch_cirrus) \
78 builtin_define ("__MAVERICK__"); \
79 if (arm_arch_xscale) \
80 builtin_define ("__XSCALE__"); \
81 if (arm_arch_iwmmxt) \
82 builtin_define ("__IWMMXT__"); \
83 if (TARGET_AAPCS_BASED) \
84 builtin_define ("__ARM_EABI__"); \
87 /* The various ARM cores. */
90 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
92 #include "arm-cores.def"
94 /* Used to indicate that no processor has been specified. */
100 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
102 #include "arm-cores.def"
107 /* The processor for which instructions should be scheduled. */
108 extern enum processor_type arm_tune;
110 typedef enum arm_cond_code
112 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
113 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
117 extern arm_cc arm_current_cc;
119 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
121 extern int arm_target_label;
122 extern int arm_ccfsm_state;
123 extern GTY(()) rtx arm_target_insn;
124 /* Define the information needed to generate branch insns. This is
125 stored from the compare operation. */
126 extern GTY(()) rtx arm_compare_op0;
127 extern GTY(()) rtx arm_compare_op1;
128 /* The label of the current constant pool. */
129 extern rtx pool_vector_label;
130 /* Set to 1 when a return insn is output, this means that the epilogue
132 extern int return_used_this_function;
133 /* Used to produce AOF syntax assembler. */
134 extern GTY(()) rtx aof_pic_label;
136 /* Just in case configure has failed to define anything. */
137 #ifndef TARGET_CPU_DEFAULT
138 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
143 #define CPP_SPEC "%(subtarget_cpp_spec) \
144 %{msoft-float:%{mhard-float: \
145 %e-msoft-float and -mhard_float may not be used together}} \
146 %{mbig-endian:%{mlittle-endian: \
147 %e-mbig-endian and -mlittle-endian may not be used together}}"
153 /* This macro defines names of additional specifications to put in the specs
154 that can be used in various specifications like CC1_SPEC. Its definition
155 is an initializer with a subgrouping for each command option.
157 Each subgrouping contains a string constant, that defines the
158 specification name, and a string constant that used by the GCC driver
161 Do not define this macro if it does not need to do anything. */
162 #define EXTRA_SPECS \
163 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
164 SUBTARGET_EXTRA_SPECS
166 #ifndef SUBTARGET_EXTRA_SPECS
167 #define SUBTARGET_EXTRA_SPECS
170 #ifndef SUBTARGET_CPP_SPEC
171 #define SUBTARGET_CPP_SPEC ""
174 /* Run-time Target Specification. */
175 #ifndef TARGET_VERSION
176 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
179 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
180 /* Use hardware floating point instructions. */
181 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
182 /* Use hardware floating point calling convention. */
183 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
184 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
185 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
186 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
187 #define TARGET_IWMMXT (arm_arch_iwmmxt)
188 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
189 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
190 #define TARGET_ARM (! TARGET_THUMB)
191 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
192 #define TARGET_BACKTRACE (leaf_function_p () \
193 ? TARGET_TPCS_LEAF_FRAME \
195 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
196 #define TARGET_AAPCS_BASED \
197 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
199 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
200 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
202 /* Only 16-bit thumb code. */
203 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
204 /* Arm or Thumb-2 32-bit code. */
205 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
206 /* 32-bit Thumb-2 code. */
207 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
209 /* "DSP" multiply instructions, eg. SMULxy. */
210 #define TARGET_DSP_MULTIPLY \
211 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
212 /* Integer SIMD instructions, and extend-accumulate instructions. */
213 #define TARGET_INT_SIMD \
214 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
216 /* We could use unified syntax for arm mode, but for now we just use it
218 #define TARGET_UNIFIED_ASM TARGET_THUMB2
221 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
222 then TARGET_AAPCS_BASED must be true -- but the converse does not
223 hold. TARGET_BPABI implies the use of the BPABI runtime library,
224 etc., in addition to just the AAPCS calling conventions. */
226 #define TARGET_BPABI false
229 /* Support for a compile-time default CPU, et cetera. The rules are:
230 --with-arch is ignored if -march or -mcpu are specified.
231 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
233 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
235 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
237 --with-fpu is ignored if -mfpu is specified.
238 --with-abi is ignored is -mabi is specified. */
239 #define OPTION_DEFAULT_SPECS \
240 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
241 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
242 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
244 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
245 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
246 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
247 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
249 /* Which floating point model to use. */
252 ARM_FP_MODEL_UNKNOWN,
253 /* FPA model (Hardware or software). */
255 /* Cirrus Maverick floating point model. */
256 ARM_FP_MODEL_MAVERICK,
257 /* VFP floating point model. */
261 extern enum arm_fp_model arm_fp_model;
263 /* Which floating point hardware is available. Also update
264 fp_model_for_fpu in arm.c when adding entries to this list. */
267 /* No FP hardware. */
269 /* Full FPA support. */
271 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
273 /* Emulated FPA hardware, Issue 3 emulator. */
275 /* Cirrus Maverick floating point co-processor. */
281 /* Recast the floating point class to be the floating point attribute. */
282 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
284 /* What type of floating point to tune for */
285 extern enum fputype arm_fpu_tune;
287 /* What type of floating point instructions are available */
288 extern enum fputype arm_fpu_arch;
293 ARM_FLOAT_ABI_SOFTFP,
297 extern enum float_abi_type arm_float_abi;
299 #ifndef TARGET_DEFAULT_FLOAT_ABI
300 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
303 /* Which ABI to use. */
313 extern enum arm_abi_type arm_abi;
315 #ifndef ARM_DEFAULT_ABI
316 #define ARM_DEFAULT_ABI ARM_ABI_APCS
319 /* Which thread pointer access sequence to use. */
326 extern enum arm_tp_type target_thread_pointer;
328 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
329 extern int arm_arch3m;
331 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
332 extern int arm_arch4;
334 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
335 extern int arm_arch4t;
337 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
338 extern int arm_arch5;
340 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
341 extern int arm_arch5e;
343 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
344 extern int arm_arch6;
346 /* Nonzero if instructions not present in the 'M' profile can be used. */
347 extern int arm_arch_notm;
349 /* Nonzero if this chip can benefit from load scheduling. */
350 extern int arm_ld_sched;
352 /* Nonzero if generating thumb code. */
353 extern int thumb_code;
355 /* Nonzero if this chip is a StrongARM. */
356 extern int arm_tune_strongarm;
358 /* Nonzero if this chip is a Cirrus variant. */
359 extern int arm_arch_cirrus;
361 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
362 extern int arm_arch_iwmmxt;
364 /* Nonzero if this chip is an XScale. */
365 extern int arm_arch_xscale;
367 /* Nonzero if tuning for XScale. */
368 extern int arm_tune_xscale;
370 /* Nonzero if tuning for stores via the write buffer. */
371 extern int arm_tune_wbuf;
373 /* Nonzero if we should define __THUMB_INTERWORK__ in the
375 XXX This is a bit of a hack, it's intended to help work around
376 problems in GLD which doesn't understand that armv5t code is
377 interworking clean. */
378 extern int arm_cpp_interwork;
380 /* Nonzero if chip supports Thumb 2. */
381 extern int arm_arch_thumb2;
383 /* Nonzero if chip supports integer division instruction. */
384 extern int arm_arch_hwdiv;
386 #ifndef TARGET_DEFAULT
387 #define TARGET_DEFAULT (MASK_APCS_FRAME)
390 /* The frame pointer register used in gcc has nothing to do with debugging;
391 that is controlled by the APCS-FRAME option. */
392 #define CAN_DEBUG_WITHOUT_FP
394 #define OVERRIDE_OPTIONS arm_override_options ()
396 /* Nonzero if PIC code requires explicit qualifiers to generate
397 PLT and GOT relocs rather than the assembler doing so implicitly.
398 Subtargets can override these if required. */
399 #ifndef NEED_GOT_RELOC
400 #define NEED_GOT_RELOC 0
402 #ifndef NEED_PLT_RELOC
403 #define NEED_PLT_RELOC 0
406 /* Nonzero if we need to refer to the GOT with a PC-relative
407 offset. In other words, generate
409 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
413 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
415 The default is true, which matches NetBSD. Subtargets can
416 override this if required. */
421 /* Target machine storage Layout. */
424 /* Define this macro if it is advisable to hold scalars in registers
425 in a wider mode than that declared by the program. In such cases,
426 the value is constrained to be within the bounds of the declared
427 type, but kept valid in the wider mode. The signedness of the
428 extension may differ from that of the type. */
430 /* It is far faster to zero extend chars than to sign extend them */
432 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
433 if (GET_MODE_CLASS (MODE) == MODE_INT \
434 && GET_MODE_SIZE (MODE) < 4) \
436 if (MODE == QImode) \
438 else if (MODE == HImode) \
443 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
444 if ((GET_MODE_CLASS (MODE) == MODE_INT \
445 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
446 && GET_MODE_SIZE (MODE) < 4) \
449 /* Define this if most significant bit is lowest numbered
450 in instructions that operate on numbered bit-fields. */
451 #define BITS_BIG_ENDIAN 0
453 /* Define this if most significant byte of a word is the lowest numbered.
454 Most ARM processors are run in little endian mode, so that is the default.
455 If you want to have it run-time selectable, change the definition in a
456 cover file to be TARGET_BIG_ENDIAN. */
457 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
459 /* Define this if most significant word of a multiword number is the lowest
461 This is always false, even when in big-endian mode. */
462 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
464 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
465 on processor pre-defineds when compiling libgcc2.c. */
466 #if defined(__ARMEB__) && !defined(__ARMWEL__)
467 #define LIBGCC2_WORDS_BIG_ENDIAN 1
469 #define LIBGCC2_WORDS_BIG_ENDIAN 0
472 /* Define this if most significant word of doubles is the lowest numbered.
473 The rules are different based on whether or not we use FPA-format,
474 VFP-format or some other floating point co-processor's format doubles. */
475 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
477 #define UNITS_PER_WORD 4
479 /* True if natural alignment is used for doubleword types. */
480 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
482 #define DOUBLEWORD_ALIGNMENT 64
484 #define PARM_BOUNDARY 32
486 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
488 #define PREFERRED_STACK_BOUNDARY \
489 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
491 #define FUNCTION_BOUNDARY 32
493 /* The lowest bit is used to indicate Thumb-mode functions, so the
494 vbit must go into the delta field of pointers to member
496 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
498 #define EMPTY_FIELD_BOUNDARY 32
500 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
502 /* XXX Blah -- this macro is used directly by libobjc. Since it
503 supports no vector modes, cut out the complexity and fall back
504 on BIGGEST_FIELD_ALIGNMENT. */
505 #ifdef IN_TARGET_LIBS
506 #define BIGGEST_FIELD_ALIGNMENT 64
509 /* Make strings word-aligned so strcpy from constants will be faster. */
510 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
512 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
513 ((TREE_CODE (EXP) == STRING_CST \
515 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
516 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
518 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
519 value set in previous versions of this toolchain was 8, which produces more
520 compact structures. The command line option -mstructure_size_boundary=<n>
521 can be used to change this value. For compatibility with the ARM SDK
522 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
523 0020D) page 2-20 says "Structures are aligned on word boundaries".
524 The AAPCS specifies a value of 8. */
525 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
526 extern int arm_structure_size_boundary;
528 /* This is the value used to initialize arm_structure_size_boundary. If a
529 particular arm target wants to change the default value it should change
530 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
531 for an example of this. */
532 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
533 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
536 /* Nonzero if move instructions will actually fail to work
537 when given unaligned data. */
538 #define STRICT_ALIGNMENT 1
540 /* wchar_t is unsigned under the AAPCS. */
542 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
544 #define WCHAR_TYPE_SIZE BITS_PER_WORD
548 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
552 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
555 /* AAPCS requires that structure alignment is affected by bitfields. */
556 #ifndef PCC_BITFIELD_TYPE_MATTERS
557 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
561 /* Standard register usage. */
563 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
564 (S - saved over call).
566 r0 * argument word/integer result
569 r4-r8 S register variable
570 r9 S (rfp) register variable (real frame pointer)
572 r10 F S (sl) stack limit (used by -mapcs-stack-check)
573 r11 F S (fp) argument pointer
574 r12 (ip) temp workspace
575 r13 F S (sp) lower end of current stack frame
576 r14 (lr) link address/workspace
577 r15 F (pc) program counter
579 f0 floating point result
580 f1-f3 floating point scratch
582 f4-f7 S floating point variable
584 cc This is NOT a real register, but is used internally
585 to represent things that use or set the condition
587 sfp This isn't either. It is used during rtl generation
588 since the offset between the frame pointer and the
589 auto's isn't known until after register allocation.
590 afp Nor this, we only need this because of non-local
591 goto. Without it fp appears to be used and the
592 elimination code won't get rid of sfp. It tracks
593 fp exactly at all times.
595 *: See CONDITIONAL_REGISTER_USAGE */
598 mvf0 Cirrus floating point result
599 mvf1-mvf3 Cirrus floating point scratch
600 mvf4-mvf15 S Cirrus floating point variable. */
602 /* s0-s15 VFP scratch (aka d0-d7).
603 s16-s31 S VFP variable (aka d8-d15).
604 vfpcc Not a real register. Represents the VFP condition
607 /* The stack backtrace structure is as follows:
608 fp points to here: | save code pointer | [fp]
609 | return link value | [fp, #-4]
610 | return sp value | [fp, #-8]
611 | return fp value | [fp, #-12]
612 [| saved r10 value |]
623 [| saved f7 value |] three words
624 [| saved f6 value |] three words
625 [| saved f5 value |] three words
626 [| saved f4 value |] three words
627 r0-r3 are not normally saved in a C function. */
629 /* 1 for registers that have pervasive standard uses
630 and are not available for the register allocator. */
631 #define FIXED_REGISTERS \
649 /* 1 for registers not available across function calls.
650 These must include the FIXED_REGISTERS and also any
651 registers that can be used without being saved.
652 The latter must include the registers where values are returned
653 and the register where structure-value addresses are passed.
654 Aside from that, you can include as many other registers as you like.
655 The CC is not preserved over function calls on the ARM 6, so it is
656 easier to assume this for all. SFP is preserved, since FP is. */
657 #define CALL_USED_REGISTERS \
675 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
676 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
679 #define CONDITIONAL_REGISTER_USAGE \
683 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
685 for (regno = FIRST_FPA_REGNUM; \
686 regno <= LAST_FPA_REGNUM; ++regno) \
687 fixed_regs[regno] = call_used_regs[regno] = 1; \
690 if (TARGET_THUMB && optimize_size) \
692 /* When optimizing for size, it's better not to use \
693 the HI regs, because of the overhead of stacking \
695 /* ??? Is this still true for thumb2? */ \
696 for (regno = FIRST_HI_REGNUM; \
697 regno <= LAST_HI_REGNUM; ++regno) \
698 fixed_regs[regno] = call_used_regs[regno] = 1; \
701 /* The link register can be clobbered by any branch insn, \
702 but we have no way to track that at present, so mark \
703 it as unavailable. */ \
705 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
707 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
709 if (TARGET_MAVERICK) \
711 for (regno = FIRST_FPA_REGNUM; \
712 regno <= LAST_FPA_REGNUM; ++ regno) \
713 fixed_regs[regno] = call_used_regs[regno] = 1; \
714 for (regno = FIRST_CIRRUS_FP_REGNUM; \
715 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
717 fixed_regs[regno] = 0; \
718 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
723 for (regno = FIRST_VFP_REGNUM; \
724 regno <= LAST_VFP_REGNUM; ++ regno) \
726 fixed_regs[regno] = 0; \
727 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
732 if (TARGET_REALLY_IWMMXT) \
734 regno = FIRST_IWMMXT_GR_REGNUM; \
735 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
736 and wCG1 as call-preserved registers. The 2002/11/21 \
737 revision changed this so that all wCG registers are \
738 scratch registers. */ \
739 for (regno = FIRST_IWMMXT_GR_REGNUM; \
740 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
741 fixed_regs[regno] = 0; \
742 /* The XScale ABI has wR0 - wR9 as scratch registers, \
743 the rest as call-preserved registers. */ \
744 for (regno = FIRST_IWMMXT_REGNUM; \
745 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
747 fixed_regs[regno] = 0; \
748 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
752 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
754 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
755 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
757 else if (TARGET_APCS_STACK) \
759 fixed_regs[10] = 1; \
760 call_used_regs[10] = 1; \
762 /* -mcaller-super-interworking reserves r11 for calls to \
763 _interwork_r11_call_via_rN(). Making the register global \
764 is an easy way of ensuring that it remains valid for all \
766 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
767 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
769 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
770 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
771 if (TARGET_CALLER_INTERWORKING) \
772 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
774 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
777 /* These are a couple of extensions to the formats accepted
779 %@ prints out ASM_COMMENT_START
780 %r prints out REGISTER_PREFIX reg_names[arg] */
781 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
783 fputs (ASM_COMMENT_START, FILE); \
787 fputs (REGISTER_PREFIX, FILE); \
788 fputs (reg_names [va_arg (ARGS, int)], FILE); \
791 /* Round X up to the nearest word. */
792 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
794 /* Convert fron bytes to ints. */
795 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
797 /* The number of (integer) registers required to hold a quantity of type MODE.
798 Also used for VFP registers. */
799 #define ARM_NUM_REGS(MODE) \
800 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
802 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
803 #define ARM_NUM_REGS2(MODE, TYPE) \
804 ARM_NUM_INTS ((MODE) == BLKmode ? \
805 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
807 /* The number of (integer) argument register available. */
808 #define NUM_ARG_REGS 4
810 /* Return the register number of the N'th (integer) argument. */
811 #define ARG_REGISTER(N) (N - 1)
813 /* Specify the registers used for certain standard purposes.
814 The values of these macros are register numbers. */
816 /* The number of the last argument register. */
817 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
819 /* The numbers of the Thumb register ranges. */
820 #define FIRST_LO_REGNUM 0
821 #define LAST_LO_REGNUM 7
822 #define FIRST_HI_REGNUM 8
823 #define LAST_HI_REGNUM 11
825 #ifndef TARGET_UNWIND_INFO
826 /* We use sjlj exceptions for backwards compatibility. */
827 #define MUST_USE_SJLJ_EXCEPTIONS 1
830 /* We can generate DWARF2 Unwind info, even though we don't use it. */
831 #define DWARF2_UNWIND_INFO 1
833 /* Use r0 and r1 to pass exception handling information. */
834 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
836 /* The register that holds the return address in exception handlers. */
837 #define ARM_EH_STACKADJ_REGNUM 2
838 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
840 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
841 as an invisible last argument (possible since varargs don't exist in
842 Pascal), so the following is not true. */
843 #define STATIC_CHAIN_REGNUM 12
845 /* Define this to be where the real frame pointer is if it is not possible to
846 work out the offset between the frame pointer and the automatic variables
847 until after register allocation has taken place. FRAME_POINTER_REGNUM
848 should point to a special register that we will make sure is eliminated.
850 For the Thumb we have another problem. The TPCS defines the frame pointer
851 as r11, and GCC believes that it is always possible to use the frame pointer
852 as base register for addressing purposes. (See comments in
853 find_reloads_address()). But - the Thumb does not allow high registers,
854 including r11, to be used as base address registers. Hence our problem.
856 The solution used here, and in the old thumb port is to use r7 instead of
857 r11 as the hard frame pointer and to have special code to generate
858 backtrace structures on the stack (if required to do so via a command line
859 option) using r11. This is the only 'user visible' use of r11 as a frame
861 #define ARM_HARD_FRAME_POINTER_REGNUM 11
862 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
864 #define HARD_FRAME_POINTER_REGNUM \
866 ? ARM_HARD_FRAME_POINTER_REGNUM \
867 : THUMB_HARD_FRAME_POINTER_REGNUM)
869 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
871 /* Register to use for pushing function arguments. */
872 #define STACK_POINTER_REGNUM SP_REGNUM
874 /* ARM floating pointer registers. */
875 #define FIRST_FPA_REGNUM 16
876 #define LAST_FPA_REGNUM 23
877 #define IS_FPA_REGNUM(REGNUM) \
878 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
880 #define FIRST_IWMMXT_GR_REGNUM 43
881 #define LAST_IWMMXT_GR_REGNUM 46
882 #define FIRST_IWMMXT_REGNUM 47
883 #define LAST_IWMMXT_REGNUM 62
884 #define IS_IWMMXT_REGNUM(REGNUM) \
885 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
886 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
887 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
889 /* Base register for access to local variables of the function. */
890 #define FRAME_POINTER_REGNUM 25
892 /* Base register for access to arguments of the function. */
893 #define ARG_POINTER_REGNUM 26
895 #define FIRST_CIRRUS_FP_REGNUM 27
896 #define LAST_CIRRUS_FP_REGNUM 42
897 #define IS_CIRRUS_REGNUM(REGNUM) \
898 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
900 #define FIRST_VFP_REGNUM 63
901 #define LAST_VFP_REGNUM 94
902 #define IS_VFP_REGNUM(REGNUM) \
903 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
905 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
906 /* + 16 Cirrus registers take us up to 43. */
907 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
908 /* VFP adds 32 + 1 more. */
909 #define FIRST_PSEUDO_REGISTER 96
911 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
913 /* Value should be nonzero if functions must have frame pointers.
914 Zero means the frame pointer need not be set up (and parms may be accessed
915 via the stack pointer) in functions that seem suitable.
916 If we have to have a frame pointer we might as well make use of it.
917 APCS says that the frame pointer does not need to be pushed in leaf
918 functions, or simple tail call functions. */
920 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
921 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
924 #define FRAME_POINTER_REQUIRED \
925 (current_function_has_nonlocal_label \
926 || SUBTARGET_FRAME_POINTER_REQUIRED \
927 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
929 /* Return number of consecutive hard regs needed starting at reg REGNO
930 to hold something of mode MODE.
931 This is ordinarily the length in words of a value of mode MODE
932 but can be less for certain modes in special long registers.
934 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
936 #define HARD_REGNO_NREGS(REGNO, MODE) \
938 && REGNO >= FIRST_FPA_REGNUM \
939 && REGNO != FRAME_POINTER_REGNUM \
940 && REGNO != ARG_POINTER_REGNUM) \
941 && !IS_VFP_REGNUM (REGNO) \
942 ? 1 : ARM_NUM_REGS (MODE))
944 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
945 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
946 arm_hard_regno_mode_ok ((REGNO), (MODE))
948 /* Value is 1 if it is a good idea to tie two pseudo registers
949 when one has mode MODE1 and one has mode MODE2.
950 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
951 for any hard reg, then this must be 0 for correct output. */
952 #define MODES_TIEABLE_P(MODE1, MODE2) \
953 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
955 #define VALID_IWMMXT_REG_MODE(MODE) \
956 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
958 /* The order in which register should be allocated. It is good to use ip
959 since no saving is required (though calls clobber it) and it never contains
960 function parameters. It is quite good to use lr since other calls may
961 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
962 least likely to contain a function parameter; in addition results are
965 #define REG_ALLOC_ORDER \
967 3, 2, 1, 0, 12, 14, 4, 5, \
968 6, 7, 8, 10, 9, 11, 13, 15, \
969 16, 17, 18, 19, 20, 21, 22, 23, \
970 27, 28, 29, 30, 31, 32, 33, 34, \
971 35, 36, 37, 38, 39, 40, 41, 42, \
972 43, 44, 45, 46, 47, 48, 49, 50, \
973 51, 52, 53, 54, 55, 56, 57, 58, \
976 78, 77, 76, 75, 74, 73, 72, 71, \
977 70, 69, 68, 67, 66, 65, 64, 63, \
978 79, 80, 81, 82, 83, 84, 85, 86, \
979 87, 88, 89, 90, 91, 92, 93, 94, \
983 /* Interrupt functions can only use registers that have already been
984 saved by the prologue, even if they would normally be
986 #define HARD_REGNO_RENAME_OK(SRC, DST) \
987 (! IS_INTERRUPT (cfun->machine->func_type) || \
988 df_regs_ever_live_p (DST))
990 /* Register and constant classes. */
992 /* Register classes: used to be simple, just all ARM regs or all FPA regs
993 Now that the Thumb is involved it has become more complicated. */
1013 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1015 /* Give names of register classes as strings for dump file. */
1016 #define REG_CLASS_NAMES \
1034 /* Define which registers fit in which classes.
1035 This is an initializer for a vector of HARD_REG_SET
1036 of length N_REG_CLASSES. */
1037 #define REG_CLASS_CONTENTS \
1039 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1040 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1041 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1042 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1043 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1044 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1045 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1046 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1047 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1048 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1049 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1050 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1051 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1052 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1055 /* The same information, inverted:
1056 Return the class number of the smallest class containing
1057 reg number REGNO. This could be a conditional expression
1058 or could index an array. */
1059 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1061 /* FPA registers can't do subreg as all values are reformatted to internal
1062 precision. VFP registers may only be accessed in the mode they
1064 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1065 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1066 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1067 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1070 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1071 using r0-r4 for function arguments, r7 for the stack frame and don't
1072 have enough left over to do doubleword arithmetic. */
1073 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1074 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1075 || (CLASS) == CC_REG)
1077 /* The class value for index registers, and the one for base regs. */
1078 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1079 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1081 /* For the Thumb the high registers cannot be used as base registers
1082 when addressing quantities in QI or HI mode; if we don't know the
1083 mode, then we must be conservative. */
1084 #define MODE_BASE_REG_CLASS(MODE) \
1085 (TARGET_32BIT ? GENERAL_REGS : \
1086 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1088 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1089 instead of BASE_REGS. */
1090 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1092 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1093 registers explicitly used in the rtl to be used as spill registers
1094 but prevents the compiler from extending the lifetime of these
1096 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1098 /* Given an rtx X being reloaded into a reg required to be
1099 in class CLASS, return the class of reg to actually use.
1100 In general this is just CLASS, but for the Thumb core registers and
1101 immediate constants we prefer a LO_REGS class or a subset. */
1102 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1103 (TARGET_ARM ? (CLASS) : \
1104 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1105 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1107 /* Must leave BASE_REGS reloads alone */
1108 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1109 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1110 ? ((true_regnum (X) == -1 ? LO_REGS \
1111 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1115 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1116 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1117 ? ((true_regnum (X) == -1 ? LO_REGS \
1118 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1122 /* Return the register class of a scratch register needed to copy IN into
1123 or out of a register in CLASS in MODE. If it can be done directly,
1124 NO_REGS is returned. */
1125 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1126 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1127 ((TARGET_VFP && TARGET_HARD_FLOAT \
1128 && (CLASS) == VFP_REGS) \
1129 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1130 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1131 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1133 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1134 ? GENERAL_REGS : NO_REGS) \
1135 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1137 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1138 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1139 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1140 ((TARGET_VFP && TARGET_HARD_FLOAT \
1141 && (CLASS) == VFP_REGS) \
1142 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1143 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1144 coproc_secondary_reload_class (MODE, X, TRUE) : \
1145 /* Cannot load constants into Cirrus registers. */ \
1146 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1147 && (CLASS) == CIRRUS_REGS \
1148 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1151 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1152 && CONSTANT_P (X)) \
1154 (((MODE) == HImode && ! arm_arch4 \
1155 && (GET_CODE (X) == MEM \
1156 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1157 && true_regnum (X) == -1))) \
1158 ? GENERAL_REGS : NO_REGS) \
1159 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1161 /* Try a machine-dependent way of reloading an illegitimate address
1162 operand. If we find one, push the reload and jump to WIN. This
1163 macro is used in only one place: `find_reloads_address' in reload.c.
1165 For the ARM, we wish to handle large displacements off a base
1166 register by splitting the addend across a MOV and the mem insn.
1167 This can cut the number of reloads needed. */
1168 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1171 if (GET_CODE (X) == PLUS \
1172 && GET_CODE (XEXP (X, 0)) == REG \
1173 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1174 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1175 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1177 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1178 HOST_WIDE_INT low, high; \
1180 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1181 low = ((val & 0xf) ^ 0x8) - 0x8; \
1182 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1183 /* Need to be careful, -256 is not a valid offset. */ \
1184 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1185 else if (MODE == SImode \
1186 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1187 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1188 /* Need to be careful, -4096 is not a valid offset. */ \
1189 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1190 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1191 /* Need to be careful, -256 is not a valid offset. */ \
1192 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1193 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1194 && TARGET_HARD_FLOAT && TARGET_FPA) \
1195 /* Need to be careful, -1024 is not a valid offset. */ \
1196 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1200 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1201 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1202 - (unsigned HOST_WIDE_INT) 0x80000000); \
1203 /* Check for overflow or zero */ \
1204 if (low == 0 || high == 0 || (high + low != val)) \
1207 /* Reload the high part into a base reg; leave the low part \
1209 X = gen_rtx_PLUS (GET_MODE (X), \
1210 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1213 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1214 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1215 VOIDmode, 0, 0, OPNUM, TYPE); \
1221 /* XXX If an HImode FP+large_offset address is converted to an HImode
1222 SP+large_offset address, then reload won't know how to fix it. It sees
1223 only that SP isn't valid for HImode, and so reloads the SP into an index
1224 register, but the resulting address is still invalid because the offset
1225 is too big. We fix it here instead by reloading the entire address. */
1226 /* We could probably achieve better results by defining PROMOTE_MODE to help
1227 cope with the variances between the Thumb's signed and unsigned byte and
1228 halfword load instructions. */
1229 /* ??? This should be safe for thumb2, but we may be able to do better. */
1230 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1232 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1240 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1242 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1244 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1246 /* Return the maximum number of consecutive registers
1247 needed to represent mode MODE in a register of class CLASS.
1248 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1249 #define CLASS_MAX_NREGS(CLASS, MODE) \
1250 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1252 /* If defined, gives a class of registers that cannot be used as the
1253 operand of a SUBREG that changes the mode of the object illegally. */
1255 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1256 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1258 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1259 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1260 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1261 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1262 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1263 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1264 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1265 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1266 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1269 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1271 /* Stack layout; function entry, exit and calling. */
1273 /* Define this if pushing a word on the stack
1274 makes the stack pointer a smaller address. */
1275 #define STACK_GROWS_DOWNWARD 1
1277 /* Define this to nonzero if the nominal address of the stack frame
1278 is at the high-address end of the local variables;
1279 that is, each additional local variable allocated
1280 goes at a more negative offset in the frame. */
1281 #define FRAME_GROWS_DOWNWARD 1
1283 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1284 When present, it is one word in size, and sits at the top of the frame,
1285 between the soft frame pointer and either r7 or r11.
1287 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1288 and only then if some outgoing arguments are passed on the stack. It would
1289 be tempting to also check whether the stack arguments are passed by indirect
1290 calls, but there seems to be no reason in principle why a post-reload pass
1291 couldn't convert a direct call into an indirect one. */
1292 #define CALLER_INTERWORKING_SLOT_SIZE \
1293 (TARGET_CALLER_INTERWORKING \
1294 && current_function_outgoing_args_size != 0 \
1295 ? UNITS_PER_WORD : 0)
1297 /* Offset within stack frame to start allocating local variables at.
1298 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1299 first local allocated. Otherwise, it is the offset to the BEGINNING
1300 of the first local allocated. */
1301 #define STARTING_FRAME_OFFSET 0
1303 /* If we generate an insn to push BYTES bytes,
1304 this says how many the stack pointer really advances by. */
1305 /* The push insns do not do this rounding implicitly.
1306 So don't define this. */
1307 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1309 /* Define this if the maximum size of all the outgoing args is to be
1310 accumulated and pushed during the prologue. The amount can be
1311 found in the variable current_function_outgoing_args_size. */
1312 #define ACCUMULATE_OUTGOING_ARGS 1
1314 /* Offset of first parameter from the argument pointer register value. */
1315 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1317 /* Value is the number of byte of arguments automatically
1318 popped when returning from a subroutine call.
1319 FUNDECL is the declaration node of the function (as a tree),
1320 FUNTYPE is the data type of the function (as a tree),
1321 or for a library call it is an identifier node for the subroutine name.
1322 SIZE is the number of bytes of arguments passed on the stack.
1324 On the ARM, the caller does not pop any of its arguments that were passed
1326 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1328 /* Define how to find the value returned by a library function
1329 assuming the value has mode MODE. */
1330 #define LIBCALL_VALUE(MODE) \
1331 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1332 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1333 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1334 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1335 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1336 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1337 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1338 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1339 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1341 /* Define how to find the value returned by a function.
1342 VALTYPE is the data type of the value (as a tree).
1343 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1344 otherwise, FUNC is 0. */
1345 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1346 arm_function_value (VALTYPE, FUNC);
1348 /* 1 if N is a possible register number for a function value.
1349 On the ARM, only r0 and f0 can return results. */
1350 /* On a Cirrus chip, mvf0 can return results. */
1351 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1352 ((REGNO) == ARG_REGISTER (1) \
1353 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1354 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1355 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1356 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1357 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1359 /* Amount of memory needed for an untyped call to save all possible return
1361 #define APPLY_RESULT_SIZE arm_apply_result_size()
1363 /* How large values are returned */
1364 /* A C expression which can inhibit the returning of certain function values
1365 in registers, based on the type of value. */
1366 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1368 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1369 values must be in memory. On the ARM, they need only do so if larger
1370 than a word, or if they contain elements offset from zero in the struct. */
1371 #define DEFAULT_PCC_STRUCT_RETURN 0
1373 /* These bits describe the different types of function supported
1374 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1375 normal function and an interworked function, for example. Knowing the
1376 type of a function is important for determining its prologue and
1378 Note value 7 is currently unassigned. Also note that the interrupt
1379 function types all have bit 2 set, so that they can be tested for easily.
1380 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1381 machine_function structure is initialized (to zero) func_type will
1382 default to unknown. This will force the first use of arm_current_func_type
1383 to call arm_compute_func_type. */
1384 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1385 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1386 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1387 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1388 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1389 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1391 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1393 /* In addition functions can have several type modifiers,
1394 outlined by these bit masks: */
1395 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1396 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1397 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1398 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1399 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1401 /* Some macros to test these flags. */
1402 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1403 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1404 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1405 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1406 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1407 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1410 /* Structure used to hold the function stack frame layout. Offsets are
1411 relative to the stack pointer on function entry. Positive offsets are
1412 in the direction of stack growth.
1413 Only soft_frame is used in thumb mode. */
1415 typedef struct arm_stack_offsets GTY(())
1417 int saved_args; /* ARG_POINTER_REGNUM. */
1418 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1420 int soft_frame; /* FRAME_POINTER_REGNUM. */
1421 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1422 int outgoing_args; /* STACK_POINTER_REGNUM. */
1426 /* A C structure for machine-specific, per-function data.
1427 This is added to the cfun structure. */
1428 typedef struct machine_function GTY(())
1430 /* Additional stack adjustment in __builtin_eh_throw. */
1431 rtx eh_epilogue_sp_ofs;
1432 /* Records if LR has to be saved for far jumps. */
1434 /* Records if ARG_POINTER was ever live. */
1435 int arg_pointer_live;
1436 /* Records if the save of LR has been eliminated. */
1437 int lr_save_eliminated;
1438 /* The size of the stack frame. Only valid after reload. */
1439 arm_stack_offsets stack_offsets;
1440 /* Records the type of the current function. */
1441 unsigned long func_type;
1442 /* Record if the function has a variable argument list. */
1443 int uses_anonymous_args;
1444 /* Records if sibcalls are blocked because an argument
1445 register is needed to preserve stack alignment. */
1446 int sibcall_blocked;
1447 /* The PIC register for this function. This might be a pseudo. */
1449 /* Labels for per-function Thumb call-via stubs. One per potential calling
1450 register. We can never call via LR or PC. We can call via SP if a
1451 trampoline happens to be on the top of the stack. */
1456 /* As in the machine_function, a global set of call-via labels, for code
1457 that is in text_section. */
1458 extern GTY(()) rtx thumb_call_via_label[14];
1460 /* A C type for declaring a variable that is used as the first argument of
1461 `FUNCTION_ARG' and other related values. For some target machines, the
1462 type `int' suffices and can hold the number of bytes of argument so far. */
1465 /* This is the number of registers of arguments scanned so far. */
1467 /* This is the number of iWMMXt register arguments scanned so far. */
1474 /* Define where to put the arguments to a function.
1475 Value is zero to push the argument on the stack,
1476 or a hard register in which to store the argument.
1478 MODE is the argument's machine mode.
1479 TYPE is the data type of the argument (as a tree).
1480 This is null for libcalls where that information may
1482 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1483 the preceding args and about the function being called.
1484 NAMED is nonzero if this argument is a named parameter
1485 (otherwise it is an extra parameter matching an ellipsis).
1487 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1488 other arguments are passed on the stack. If (NAMED == 0) (which happens
1489 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1490 defined), say it is passed in the stack (function_prologue will
1491 indeed make it pass in the stack if necessary). */
1492 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1493 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1495 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1496 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1498 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1499 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1501 /* For AAPCS, padding should never be below the argument. For other ABIs,
1502 * mimic the default. */
1503 #define PAD_VARARGS_DOWN \
1504 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1506 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1507 for a call to a function whose data type is FNTYPE.
1508 For a library call, FNTYPE is 0.
1509 On the ARM, the offset starts at 0. */
1510 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1511 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1513 /* Update the data in CUM to advance over an argument
1514 of mode MODE and data type TYPE.
1515 (TYPE is null for libcalls where that information may not be available.) */
1516 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1518 if (arm_vector_mode_supported_p (MODE) \
1519 && (CUM).named_count > (CUM).nargs \
1520 && TARGET_IWMMXT_ABI) \
1521 (CUM).iwmmxt_nregs += 1; \
1523 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1525 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1526 argument with the specified mode and type. If it is not defined,
1527 `PARM_BOUNDARY' is used for all arguments. */
1528 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1529 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1530 ? DOUBLEWORD_ALIGNMENT \
1533 /* 1 if N is a possible register number for function argument passing.
1534 On the ARM, r0-r3 are used to pass args. */
1535 #define FUNCTION_ARG_REGNO_P(REGNO) \
1536 (IN_RANGE ((REGNO), 0, 3) \
1537 || (TARGET_IWMMXT_ABI \
1538 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1541 /* If your target environment doesn't prefix user functions with an
1542 underscore, you may wish to re-define this to prevent any conflicts.
1543 e.g. AOF may prefix mcount with an underscore. */
1544 #ifndef ARM_MCOUNT_NAME
1545 #define ARM_MCOUNT_NAME "*mcount"
1548 /* Call the function profiler with a given profile label. The Acorn
1549 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1550 On the ARM the full profile code will look like:
1559 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1560 will output the .text section.
1562 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1563 ``prof'' doesn't seem to mind about this!
1565 Note - this version of the code is designed to work in both ARM and
1567 #ifndef ARM_FUNCTION_PROFILER
1568 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1573 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1574 IP_REGNUM, LR_REGNUM); \
1575 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1576 fputc ('\n', STREAM); \
1577 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1578 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1579 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1583 #ifdef THUMB_FUNCTION_PROFILER
1584 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1586 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1588 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1590 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1591 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1594 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1595 the stack pointer does not matter. The value is tested only in
1596 functions that have frame pointers.
1597 No definition is equivalent to always zero.
1599 On the ARM, the function epilogue recovers the stack pointer from the
1601 #define EXIT_IGNORE_STACK 1
1603 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1605 /* Determine if the epilogue should be output as RTL.
1606 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1607 /* This is disabled for Thumb-2 because it will confuse the
1608 conditional insn counter. */
1609 #define USE_RETURN_INSN(ISCOND) \
1610 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1612 /* Definitions for register eliminations.
1614 This is an array of structures. Each structure initializes one pair
1615 of eliminable registers. The "from" register number is given first,
1616 followed by "to". Eliminations of the same "from" register are listed
1617 in order of preference.
1619 We have two registers that can be eliminated on the ARM. First, the
1620 arg pointer register can often be eliminated in favor of the stack
1621 pointer register. Secondly, the pseudo frame pointer register can always
1622 be eliminated; it is replaced with either the stack or the real frame
1623 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1624 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1626 #define ELIMINABLE_REGS \
1627 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1628 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1629 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1630 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1631 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1632 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1633 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1635 /* Given FROM and TO register numbers, say whether this elimination is
1636 allowed. Frame pointer elimination is automatically handled.
1638 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1639 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1640 pointer, we must eliminate FRAME_POINTER_REGNUM into
1641 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1642 ARG_POINTER_REGNUM. */
1643 #define CAN_ELIMINATE(FROM, TO) \
1644 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1645 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1646 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1647 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1650 /* Define the offset between two registers, one to be eliminated, and the
1651 other its replacement, at the start of a routine. */
1652 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1654 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1656 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1658 /* Special case handling of the location of arguments passed on the stack. */
1659 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1661 /* Initialize data used by insn expanders. This is called from insn_emit,
1662 once for every function before code is generated. */
1663 #define INIT_EXPANDERS arm_init_expanders ()
1665 /* Output assembler code for a block containing the constant parts
1666 of a trampoline, leaving space for the variable parts.
1668 On the ARM, (if r8 is the static chain regnum, and remembering that
1669 referencing pc adds an offset of 8) the trampoline looks like:
1672 .word static chain value
1673 .word function's address
1674 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1675 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1677 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1678 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1679 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1680 PC_REGNUM, PC_REGNUM); \
1681 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1682 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1685 /* The Thumb-2 trampoline is similar to the arm implementation.
1686 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1687 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1689 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1690 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1691 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1692 PC_REGNUM, PC_REGNUM); \
1693 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1694 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1697 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1699 ASM_OUTPUT_ALIGN(FILE, 2); \
1700 fprintf (FILE, "\t.code\t16\n"); \
1701 fprintf (FILE, ".Ltrampoline_start:\n"); \
1702 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1703 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1705 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1706 STATIC_CHAIN_REGNUM); \
1707 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1709 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1711 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1713 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1714 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1717 #define TRAMPOLINE_TEMPLATE(FILE) \
1719 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1720 else if (TARGET_THUMB2) \
1721 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1723 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1725 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1727 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1730 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1731 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1734 /* Length in units of the trampoline for entering a nested function. */
1735 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1737 /* Alignment required for a trampoline in bits. */
1738 #define TRAMPOLINE_ALIGNMENT 32
1741 /* Emit RTL insns to initialize the variable parts of a trampoline.
1742 FNADDR is an RTX for the address of the function's pure code.
1743 CXT is an RTX for the static chain value for the function. */
1744 #ifndef INITIALIZE_TRAMPOLINE
1745 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1747 emit_move_insn (gen_rtx_MEM (SImode, \
1748 plus_constant (TRAMP, \
1749 TARGET_32BIT ? 8 : 12)), \
1751 emit_move_insn (gen_rtx_MEM (SImode, \
1752 plus_constant (TRAMP, \
1753 TARGET_32BIT ? 12 : 16)), \
1755 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1756 0, VOIDmode, 2, TRAMP, Pmode, \
1757 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1762 /* Addressing modes, and classification of registers for them. */
1763 #define HAVE_POST_INCREMENT 1
1764 #define HAVE_PRE_INCREMENT TARGET_32BIT
1765 #define HAVE_POST_DECREMENT TARGET_32BIT
1766 #define HAVE_PRE_DECREMENT TARGET_32BIT
1767 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1768 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1769 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1770 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1772 /* Macros to check register numbers against specific register classes. */
1774 /* These assume that REGNO is a hard or pseudo reg number.
1775 They give nonzero only if REGNO is a hard reg of the suitable class
1776 or a pseudo reg currently allocated to a suitable hard reg.
1777 Since they use reg_renumber, they are safe only once reg_renumber
1778 has been allocated, which happens in local-alloc.c. */
1779 #define TEST_REGNO(R, TEST, VALUE) \
1780 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1782 /* Don't allow the pc to be used. */
1783 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1784 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1785 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1786 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1788 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1789 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1790 || (GET_MODE_SIZE (MODE) >= 4 \
1791 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1793 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1795 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1796 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1798 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1799 For Thumb, we can not use SP + reg, so reject SP. */
1800 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1801 REGNO_OK_FOR_INDEX_P (X)
1803 /* For ARM code, we don't care about the mode, but for Thumb, the index
1804 must be suitable for use in a QImode load. */
1805 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1806 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1808 /* Maximum number of registers that can appear in a valid memory address.
1809 Shifts in addresses can't be by a register. */
1810 #define MAX_REGS_PER_ADDRESS 2
1812 /* Recognize any constant value that is a valid address. */
1813 /* XXX We can address any constant, eventually... */
1815 #ifdef AOF_ASSEMBLER
1817 #define CONSTANT_ADDRESS_P(X) \
1818 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1822 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1823 #define CONSTANT_ADDRESS_P(X) \
1824 (GET_CODE (X) == SYMBOL_REF \
1825 && (CONSTANT_POOL_ADDRESS_P (X) \
1826 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1828 #endif /* AOF_ASSEMBLER */
1830 /* Nonzero if the constant value X is a legitimate general operand.
1831 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1833 On the ARM, allow any integer (invalid ones are removed later by insn
1834 patterns), nice doubles and symbol_refs which refer to the function's
1837 When generating pic allow anything. */
1838 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1840 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1841 ( GET_CODE (X) == CONST_INT \
1842 || GET_CODE (X) == CONST_DOUBLE \
1843 || CONSTANT_ADDRESS_P (X) \
1846 #define LEGITIMATE_CONSTANT_P(X) \
1847 (!arm_tls_referenced_p (X) \
1848 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1849 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1851 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1852 #define SUBTARGET_NAME_ENCODING_LENGTHS
1855 /* This is a C fragment for the inside of a switch statement.
1856 Each case label should return the number of characters to
1857 be stripped from the start of a function's name, if that
1858 name starts with the indicated character. */
1859 #define ARM_NAME_ENCODING_LENGTHS \
1860 case '*': return 1; \
1861 SUBTARGET_NAME_ENCODING_LENGTHS
1863 /* This is how to output a reference to a user-level label named NAME.
1864 `assemble_name' uses this. */
1865 #undef ASM_OUTPUT_LABELREF
1866 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1867 arm_asm_output_labelref (FILE, NAME)
1869 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1870 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1871 if (TARGET_THUMB2) \
1872 thumb2_asm_output_opcode (STREAM);
1874 /* The EABI specifies that constructors should go in .init_array.
1875 Other targets use .ctors for compatibility. */
1876 #ifndef ARM_EABI_CTORS_SECTION_OP
1877 #define ARM_EABI_CTORS_SECTION_OP \
1878 "\t.section\t.init_array,\"aw\",%init_array"
1880 #ifndef ARM_EABI_DTORS_SECTION_OP
1881 #define ARM_EABI_DTORS_SECTION_OP \
1882 "\t.section\t.fini_array,\"aw\",%fini_array"
1884 #define ARM_CTORS_SECTION_OP \
1885 "\t.section\t.ctors,\"aw\",%progbits"
1886 #define ARM_DTORS_SECTION_OP \
1887 "\t.section\t.dtors,\"aw\",%progbits"
1889 /* Define CTORS_SECTION_ASM_OP. */
1890 #undef CTORS_SECTION_ASM_OP
1891 #undef DTORS_SECTION_ASM_OP
1893 # define CTORS_SECTION_ASM_OP \
1894 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1895 # define DTORS_SECTION_ASM_OP \
1896 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1897 #else /* !defined (IN_LIBGCC2) */
1898 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1899 so we cannot use the definition above. */
1900 # ifdef __ARM_EABI__
1901 /* The .ctors section is not part of the EABI, so we do not define
1902 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1903 from trying to use it. We do define it when doing normal
1904 compilation, as .init_array can be used instead of .ctors. */
1905 /* There is no need to emit begin or end markers when using
1906 init_array; the dynamic linker will compute the size of the
1907 array itself based on special symbols created by the static
1908 linker. However, we do need to arrange to set up
1909 exception-handling here. */
1910 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1911 # define CTOR_LIST_END /* empty */
1912 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1913 # define DTOR_LIST_END /* empty */
1914 # else /* !defined (__ARM_EABI__) */
1915 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1916 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1917 # endif /* !defined (__ARM_EABI__) */
1918 #endif /* !defined (IN_LIBCC2) */
1920 /* True if the operating system can merge entities with vague linkage
1921 (e.g., symbols in COMDAT group) during dynamic linking. */
1922 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1923 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1926 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1928 #ifdef TARGET_UNWIND_INFO
1929 #define ARM_EABI_UNWIND_TABLES \
1930 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1932 #define ARM_EABI_UNWIND_TABLES 0
1935 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1936 and check its validity for a certain class.
1937 We have two alternate definitions for each of them.
1938 The usual definition accepts all pseudo regs; the other rejects
1939 them unless they have been allocated suitable hard regs.
1940 The symbol REG_OK_STRICT causes the latter definition to be used.
1941 Thumb-2 has the same restrictions as arm. */
1942 #ifndef REG_OK_STRICT
1944 #define ARM_REG_OK_FOR_BASE_P(X) \
1945 (REGNO (X) <= LAST_ARM_REGNUM \
1946 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1947 || REGNO (X) == FRAME_POINTER_REGNUM \
1948 || REGNO (X) == ARG_POINTER_REGNUM)
1950 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1951 (REGNO (X) <= LAST_LO_REGNUM \
1952 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1953 || (GET_MODE_SIZE (MODE) >= 4 \
1954 && (REGNO (X) == STACK_POINTER_REGNUM \
1955 || (X) == hard_frame_pointer_rtx \
1956 || (X) == arg_pointer_rtx)))
1958 #define REG_STRICT_P 0
1960 #else /* REG_OK_STRICT */
1962 #define ARM_REG_OK_FOR_BASE_P(X) \
1963 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1965 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1966 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1968 #define REG_STRICT_P 1
1970 #endif /* REG_OK_STRICT */
1972 /* Now define some helpers in terms of the above. */
1974 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1976 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1977 : ARM_REG_OK_FOR_BASE_P (X))
1979 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1981 /* For 16-bit Thumb, a valid index register is anything that can be used in
1982 a byte load instruction. */
1983 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1984 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1986 /* Nonzero if X is a hard reg that can be used as an index
1987 or if it is a pseudo reg. On the Thumb, the stack pointer
1989 #define REG_OK_FOR_INDEX_P(X) \
1991 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1992 : ARM_REG_OK_FOR_INDEX_P (X))
1994 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1995 For Thumb, we can not use SP + reg, so reject SP. */
1996 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1997 REG_OK_FOR_INDEX_P (X)
1999 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2000 that is a valid memory address for an instruction.
2001 The MODE argument is the machine mode for the MEM expression
2002 that wants to use this address. */
2004 #define ARM_BASE_REGISTER_RTX_P(X) \
2005 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2007 #define ARM_INDEX_REGISTER_RTX_P(X) \
2008 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2010 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2012 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2016 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2018 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2022 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2024 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2028 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2030 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2031 else if (TARGET_THUMB2) \
2032 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2033 else /* if (TARGET_THUMB1) */ \
2034 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2037 /* Try machine-dependent ways of modifying an illegitimate address
2038 to be legitimate. If we find one, return the new, valid address. */
2039 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2041 X = arm_legitimize_address (X, OLDX, MODE); \
2044 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2045 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2049 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2051 X = thumb_legitimize_address (X, OLDX, MODE); \
2054 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2057 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2058 else if (TARGET_THUMB2) \
2059 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2061 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2063 if (memory_address_p (MODE, X)) \
2067 /* Go to LABEL if ADDR (a legitimate address expression)
2068 has an effect that depends on the machine mode it is used for. */
2069 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2071 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2072 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2076 /* Nothing helpful to do for the Thumb */
2077 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2079 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2082 /* Specify the machine mode that this machine uses
2083 for the index in the tablejump instruction. */
2084 #define CASE_VECTOR_MODE Pmode
2086 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2088 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2089 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2090 : (max >= 0x200) ? HImode \
2093 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2094 unsigned is probably best, but may break some code. */
2095 #ifndef DEFAULT_SIGNED_CHAR
2096 #define DEFAULT_SIGNED_CHAR 0
2099 /* Max number of bytes we can move from memory to memory
2100 in one reasonably fast instruction. */
2104 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2106 /* Define if operations between registers always perform the operation
2107 on the full register even if a narrower mode is specified. */
2108 #define WORD_REGISTER_OPERATIONS
2110 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2111 will either zero-extend or sign-extend. The value of this macro should
2112 be the code that says which one of the two operations is implicitly
2113 done, UNKNOWN if none. */
2114 #define LOAD_EXTEND_OP(MODE) \
2115 (TARGET_THUMB ? ZERO_EXTEND : \
2116 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2117 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2119 /* Nonzero if access to memory by bytes is slow and undesirable. */
2120 #define SLOW_BYTE_ACCESS 0
2122 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2124 /* Immediate shift counts are truncated by the output routines (or was it
2125 the assembler?). Shift counts in a register are truncated by ARM. Note
2126 that the native compiler puts too large (> 32) immediate shift counts
2127 into a register and shifts by the register, letting the ARM decide what
2128 to do instead of doing that itself. */
2129 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2130 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2131 On the arm, Y in a register is used modulo 256 for the shift. Only for
2132 rotates is modulo 32 used. */
2133 /* #define SHIFT_COUNT_TRUNCATED 1 */
2135 /* All integers have the same format so truncation is easy. */
2136 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2138 /* Calling from registers is a massive pain. */
2139 #define NO_FUNCTION_CSE 1
2141 /* The machine modes of pointers and functions */
2142 #define Pmode SImode
2143 #define FUNCTION_MODE Pmode
2145 #define ARM_FRAME_RTX(X) \
2146 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2147 || (X) == arg_pointer_rtx)
2149 /* Moves to and from memory are quite expensive */
2150 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2151 (TARGET_32BIT ? 10 : \
2152 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2153 * (CLASS == LO_REGS ? 1 : 2)))
2155 /* Try to generate sequences that don't involve branches, we can then use
2156 conditional instructions */
2157 #define BRANCH_COST \
2158 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2160 /* Position Independent Code. */
2161 /* We decide which register to use based on the compilation options and
2162 the assembler in use; this is more general than the APCS restriction of
2163 using sb (r9) all the time. */
2164 extern unsigned arm_pic_register;
2166 /* The register number of the register used to address a table of static
2167 data addresses in memory. */
2168 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2170 /* We can't directly access anything that contains a symbol,
2171 nor can we indirect via the constant pool. One exception is
2172 UNSPEC_TLS, which is always PIC. */
2173 #define LEGITIMATE_PIC_OPERAND_P(X) \
2174 (!(symbol_mentioned_p (X) \
2175 || label_mentioned_p (X) \
2176 || (GET_CODE (X) == SYMBOL_REF \
2177 && CONSTANT_POOL_ADDRESS_P (X) \
2178 && (symbol_mentioned_p (get_pool_constant (X)) \
2179 || label_mentioned_p (get_pool_constant (X))))) \
2180 || tls_mentioned_p (X))
2182 /* We need to know when we are making a constant pool; this determines
2183 whether data needs to be in the GOT or can be referenced via a GOT
2185 extern int making_const_table;
2187 /* Handle pragmas for compatibility with Intel's compilers. */
2188 #define REGISTER_TARGET_PRAGMAS() do { \
2189 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2190 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2191 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2194 /* Condition code information. */
2195 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2196 return the mode to be used for the comparison. */
2198 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2200 #define REVERSIBLE_CC_MODE(MODE) 1
2202 #define REVERSE_CONDITION(CODE,MODE) \
2203 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2204 ? reverse_condition_maybe_unordered (code) \
2205 : reverse_condition (code))
2207 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2210 if (GET_CODE (OP1) == CONST_INT \
2211 && ! (const_ok_for_arm (INTVAL (OP1)) \
2212 || (const_ok_for_arm (- INTVAL (OP1))))) \
2214 rtx const_op = OP1; \
2215 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2222 /* The arm5 clz instruction returns 32. */
2223 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2226 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2227 TARGET_THUMB2 ? "\t.thumb\n" : "")
2229 /* Output a push or a pop instruction (only used when profiling). */
2230 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2234 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2235 STACK_POINTER_REGNUM, REGNO); \
2237 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2241 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2245 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2246 STACK_POINTER_REGNUM, REGNO); \
2248 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2251 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2252 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2254 /* This is how to output a label which precedes a jumptable. Since
2255 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2256 #undef ASM_OUTPUT_CASE_LABEL
2257 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2260 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2261 ASM_OUTPUT_ALIGN (FILE, 2); \
2262 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2266 /* Make sure subsequent insns are aligned after a TBB. */
2267 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2270 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2271 ASM_OUTPUT_ALIGN (FILE, 1); \
2275 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2280 if (is_called_in_ARM_mode (DECL) \
2281 || (TARGET_THUMB1 && current_function_is_thunk)) \
2282 fprintf (STREAM, "\t.code 32\n") ; \
2283 else if (TARGET_THUMB1) \
2284 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2286 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2288 if (TARGET_POKE_FUNCTION_NAME) \
2289 arm_poke_function_name (STREAM, (char *) NAME); \
2293 /* For aliases of functions we use .thumb_set instead. */
2294 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2297 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2298 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2300 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2302 fprintf (FILE, "\t.thumb_set "); \
2303 assemble_name (FILE, LABEL1); \
2304 fprintf (FILE, ","); \
2305 assemble_name (FILE, LABEL2); \
2306 fprintf (FILE, "\n"); \
2309 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2313 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2314 /* To support -falign-* switches we need to use .p2align so
2315 that alignment directives in code sections will be padded
2316 with no-op instructions, rather than zeroes. */
2317 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2320 if ((MAX_SKIP) == 0) \
2321 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2323 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2324 (int) (LOG), (int) (MAX_SKIP)); \
2328 /* Add two bytes to the length of conditionally executed Thumb-2
2329 instructions for the IT instruction. */
2330 #define ADJUST_INSN_LENGTH(insn, length) \
2331 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2334 /* Only perform branch elimination (by making instructions conditional) if
2335 we're optimizing. For Thumb-2 check if any IT instructions need
2337 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2338 if (TARGET_ARM && optimize) \
2339 arm_final_prescan_insn (INSN); \
2340 else if (TARGET_THUMB2) \
2341 thumb2_final_prescan_insn (INSN); \
2342 else if (TARGET_THUMB1) \
2343 thumb1_final_prescan_insn (INSN)
2345 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2346 (CODE == '@' || CODE == '|' || CODE == '.' \
2347 || CODE == '(' || CODE == ')' \
2348 || (TARGET_32BIT && (CODE == '?')) \
2349 || (TARGET_THUMB2 && (CODE == '!')) \
2350 || (TARGET_THUMB && (CODE == '_')))
2352 /* Output an operand of an instruction. */
2353 #define PRINT_OPERAND(STREAM, X, CODE) \
2354 arm_print_operand (STREAM, X, CODE)
2356 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2357 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2358 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2359 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2360 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2361 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2364 /* Output the address of an operand. */
2365 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2367 int is_minus = GET_CODE (X) == MINUS; \
2369 if (GET_CODE (X) == REG) \
2370 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2371 else if (GET_CODE (X) == PLUS || is_minus) \
2373 rtx base = XEXP (X, 0); \
2374 rtx index = XEXP (X, 1); \
2375 HOST_WIDE_INT offset = 0; \
2376 if (GET_CODE (base) != REG) \
2378 /* Ensure that BASE is a register. */ \
2379 /* (one of them must be). */ \
2384 switch (GET_CODE (index)) \
2387 offset = INTVAL (index); \
2390 asm_fprintf (STREAM, "[%r, #%wd]", \
2391 REGNO (base), offset); \
2395 asm_fprintf (STREAM, "[%r, %s%r]", \
2396 REGNO (base), is_minus ? "-" : "", \
2406 asm_fprintf (STREAM, "[%r, %s%r", \
2407 REGNO (base), is_minus ? "-" : "", \
2408 REGNO (XEXP (index, 0))); \
2409 arm_print_operand (STREAM, index, 'S'); \
2410 fputs ("]", STREAM); \
2415 gcc_unreachable (); \
2418 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2419 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2421 extern enum machine_mode output_memory_reference_mode; \
2423 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2425 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2426 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2427 REGNO (XEXP (X, 0)), \
2428 GET_CODE (X) == PRE_DEC ? "-" : "", \
2429 GET_MODE_SIZE (output_memory_reference_mode)); \
2431 asm_fprintf (STREAM, "[%r], #%s%d", \
2432 REGNO (XEXP (X, 0)), \
2433 GET_CODE (X) == POST_DEC ? "-" : "", \
2434 GET_MODE_SIZE (output_memory_reference_mode)); \
2436 else if (GET_CODE (X) == PRE_MODIFY) \
2438 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2439 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2440 asm_fprintf (STREAM, "#%wd]!", \
2441 INTVAL (XEXP (XEXP (X, 1), 1))); \
2443 asm_fprintf (STREAM, "%r]!", \
2444 REGNO (XEXP (XEXP (X, 1), 1))); \
2446 else if (GET_CODE (X) == POST_MODIFY) \
2448 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2449 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2450 asm_fprintf (STREAM, "#%wd", \
2451 INTVAL (XEXP (XEXP (X, 1), 1))); \
2453 asm_fprintf (STREAM, "%r", \
2454 REGNO (XEXP (XEXP (X, 1), 1))); \
2456 else output_addr_const (STREAM, X); \
2459 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2461 if (GET_CODE (X) == REG) \
2462 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2463 else if (GET_CODE (X) == POST_INC) \
2464 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2465 else if (GET_CODE (X) == PLUS) \
2467 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2468 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2469 asm_fprintf (STREAM, "[%r, #%wd]", \
2470 REGNO (XEXP (X, 0)), \
2471 INTVAL (XEXP (X, 1))); \
2473 asm_fprintf (STREAM, "[%r, %r]", \
2474 REGNO (XEXP (X, 0)), \
2475 REGNO (XEXP (X, 1))); \
2478 output_addr_const (STREAM, X); \
2481 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2483 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2485 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2487 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2488 if (arm_output_addr_const_extra (file, x) == FALSE) \
2491 /* A C expression whose value is RTL representing the value of the return
2492 address for the frame COUNT steps up from the current frame. */
2494 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2495 arm_return_addr (COUNT, FRAME)
2497 /* Mask of the bits in the PC that contain the real return address
2498 when running in 26-bit mode. */
2499 #define RETURN_ADDR_MASK26 (0x03fffffc)
2501 /* Pick up the return address upon entry to a procedure. Used for
2502 dwarf2 unwind information. This also enables the table driven
2504 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2505 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2507 /* Used to mask out junk bits from the return address, such as
2508 processor state, interrupt status, condition codes and the like. */
2509 #define MASK_RETURN_ADDR \
2510 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2511 in 26 bit mode, the condition codes must be masked out of the \
2512 return address. This does not apply to ARM6 and later processors \
2513 when running in 32 bit mode. */ \
2514 ((arm_arch4 || TARGET_THUMB) \
2515 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2516 : arm_gen_return_addr_mask ())
2526 ARM_BUILTIN_WAVG2BR,
2527 ARM_BUILTIN_WAVG2HR,
2554 ARM_BUILTIN_TMOVMSKB,
2555 ARM_BUILTIN_TMOVMSKH,
2556 ARM_BUILTIN_TMOVMSKW,
2565 ARM_BUILTIN_WPACKHSS,
2566 ARM_BUILTIN_WPACKWSS,
2567 ARM_BUILTIN_WPACKDSS,
2568 ARM_BUILTIN_WPACKHUS,
2569 ARM_BUILTIN_WPACKWUS,
2570 ARM_BUILTIN_WPACKDUS,
2575 ARM_BUILTIN_WADDSSB,
2576 ARM_BUILTIN_WADDSSH,
2577 ARM_BUILTIN_WADDSSW,
2578 ARM_BUILTIN_WADDUSB,
2579 ARM_BUILTIN_WADDUSH,
2580 ARM_BUILTIN_WADDUSW,
2584 ARM_BUILTIN_WSUBSSB,
2585 ARM_BUILTIN_WSUBSSH,
2586 ARM_BUILTIN_WSUBSSW,
2587 ARM_BUILTIN_WSUBUSB,
2588 ARM_BUILTIN_WSUBUSH,
2589 ARM_BUILTIN_WSUBUSW,
2596 ARM_BUILTIN_WCMPEQB,
2597 ARM_BUILTIN_WCMPEQH,
2598 ARM_BUILTIN_WCMPEQW,
2599 ARM_BUILTIN_WCMPGTUB,
2600 ARM_BUILTIN_WCMPGTUH,
2601 ARM_BUILTIN_WCMPGTUW,
2602 ARM_BUILTIN_WCMPGTSB,
2603 ARM_BUILTIN_WCMPGTSH,
2604 ARM_BUILTIN_WCMPGTSW,
2606 ARM_BUILTIN_TEXTRMSB,
2607 ARM_BUILTIN_TEXTRMSH,
2608 ARM_BUILTIN_TEXTRMSW,
2609 ARM_BUILTIN_TEXTRMUB,
2610 ARM_BUILTIN_TEXTRMUH,
2611 ARM_BUILTIN_TEXTRMUW,
2661 ARM_BUILTIN_WUNPCKIHB,
2662 ARM_BUILTIN_WUNPCKIHH,
2663 ARM_BUILTIN_WUNPCKIHW,
2664 ARM_BUILTIN_WUNPCKILB,
2665 ARM_BUILTIN_WUNPCKILH,
2666 ARM_BUILTIN_WUNPCKILW,
2668 ARM_BUILTIN_WUNPCKEHSB,
2669 ARM_BUILTIN_WUNPCKEHSH,
2670 ARM_BUILTIN_WUNPCKEHSW,
2671 ARM_BUILTIN_WUNPCKEHUB,
2672 ARM_BUILTIN_WUNPCKEHUH,
2673 ARM_BUILTIN_WUNPCKEHUW,
2674 ARM_BUILTIN_WUNPCKELSB,
2675 ARM_BUILTIN_WUNPCKELSH,
2676 ARM_BUILTIN_WUNPCKELSW,
2677 ARM_BUILTIN_WUNPCKELUB,
2678 ARM_BUILTIN_WUNPCKELUH,
2679 ARM_BUILTIN_WUNPCKELUW,
2681 ARM_BUILTIN_THREAD_POINTER,
2686 /* Do not emit .note.GNU-stack by default. */
2687 #ifndef NEED_INDICATE_EXEC_STACK
2688 #define NEED_INDICATE_EXEC_STACK 0
2691 #endif /* ! GCC_ARM_H */
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