1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
36 #define TARGET_CPU_arm2 0x0000
37 #define TARGET_CPU_arm250 0x0000
38 #define TARGET_CPU_arm3 0x0000
39 #define TARGET_CPU_arm6 0x0001
40 #define TARGET_CPU_arm600 0x0001
41 #define TARGET_CPU_arm610 0x0002
42 #define TARGET_CPU_arm7 0x0001
43 #define TARGET_CPU_arm7m 0x0004
44 #define TARGET_CPU_arm7dm 0x0004
45 #define TARGET_CPU_arm7dmi 0x0004
46 #define TARGET_CPU_arm700 0x0001
47 #define TARGET_CPU_arm710 0x0002
48 #define TARGET_CPU_arm7100 0x0002
49 #define TARGET_CPU_arm7500 0x0002
50 #define TARGET_CPU_arm7500fe 0x1001
51 #define TARGET_CPU_arm7tdmi 0x0008
52 #define TARGET_CPU_arm8 0x0010
53 #define TARGET_CPU_arm810 0x0020
54 #define TARGET_CPU_strongarm 0x0040
55 #define TARGET_CPU_strongarm110 0x0040
56 #define TARGET_CPU_strongarm1100 0x0040
57 #define TARGET_CPU_arm9 0x0080
58 #define TARGET_CPU_arm9tdmi 0x0080
59 /* Configure didn't specify */
60 #define TARGET_CPU_generic 0x8000
64 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
65 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
67 extern enum arm_cond_code arm_current_cc;
68 extern char *arm_condition_codes[];
70 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
72 /* This is needed by the tail-calling peepholes */
73 extern int frame_pointer_needed;
76 /* Just in case configure has failed to define anything. */
77 #ifndef TARGET_CPU_DEFAULT
78 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
81 /* If the configuration file doesn't specify the cpu, the subtarget may
82 override it. If it doesn't, then default to an ARM6. */
83 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
84 #undef TARGET_CPU_DEFAULT
85 #ifdef SUBTARGET_CPU_DEFAULT
86 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
93 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
96 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
99 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
102 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 Unrecognized value in TARGET_CPU_DEFAULT.
114 #ifndef CPP_PREDEFINES
115 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
119 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
120 %(cpp_endian) %(subtarget_cpp_spec)"
122 /* Set the architecture define -- if -march= is set, then it overrides
123 the -mcpu= setting. */
124 #define CPP_CPU_ARCH_SPEC "\
125 %{march=arm2:-D__ARM_ARCH_2__} \
126 %{march=arm250:-D__ARM_ARCH_2__} \
127 %{march=arm3:-D__ARM_ARCH_2__} \
128 %{march=arm6:-D__ARM_ARCH_3__} \
129 %{march=arm600:-D__ARM_ARCH_3__} \
130 %{march=arm610:-D__ARM_ARCH_3__} \
131 %{march=arm7:-D__ARM_ARCH_3__} \
132 %{march=arm700:-D__ARM_ARCH_3__} \
133 %{march=arm710:-D__ARM_ARCH_3__} \
134 %{march=arm7100:-D__ARM_ARCH_3__} \
135 %{march=arm7500:-D__ARM_ARCH_3__} \
136 %{march=arm7500fe:-D__ARM_ARCH_3__} \
137 %{march=arm7m:-D__ARM_ARCH_3M__} \
138 %{march=arm7dm:-D__ARM_ARCH_3M__} \
139 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
140 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
141 %{march=arm8:-D__ARM_ARCH_4__} \
142 %{march=arm810:-D__ARM_ARCH_4__} \
143 %{march=arm9:-D__ARM_ARCH_4T__} \
144 %{march=arm920:-D__ARM_ARCH_4__} \
145 %{march=arm920t:-D__ARM_ARCH_4T__} \
146 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
147 %{march=strongarm:-D__ARM_ARCH_4__} \
148 %{march=strongarm110:-D__ARM_ARCH_4__} \
149 %{march=strongarm1100:-D__ARM_ARCH_4__} \
150 %{march=armv2:-D__ARM_ARCH_2__} \
151 %{march=armv2a:-D__ARM_ARCH_2__} \
152 %{march=armv3:-D__ARM_ARCH_3__} \
153 %{march=armv3m:-D__ARM_ARCH_3M__} \
154 %{march=armv4:-D__ARM_ARCH_4__} \
155 %{march=armv4t:-D__ARM_ARCH_4T__} \
157 %{mcpu=arm2:-D__ARM_ARCH_2__} \
158 %{mcpu=arm250:-D__ARM_ARCH_2__} \
159 %{mcpu=arm3:-D__ARM_ARCH_2__} \
160 %{mcpu=arm6:-D__ARM_ARCH_3__} \
161 %{mcpu=arm600:-D__ARM_ARCH_3__} \
162 %{mcpu=arm610:-D__ARM_ARCH_3__} \
163 %{mcpu=arm7:-D__ARM_ARCH_3__} \
164 %{mcpu=arm700:-D__ARM_ARCH_3__} \
165 %{mcpu=arm710:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
167 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
168 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
169 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
170 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
171 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
172 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
173 %{mcpu=arm8:-D__ARM_ARCH_4__} \
174 %{mcpu=arm810:-D__ARM_ARCH_4__} \
175 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
176 %{mcpu=arm920:-D__ARM_ARCH_4__} \
177 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
178 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
179 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
180 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
181 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
182 %{!mcpu*:%(cpp_cpu_arch_default)}} \
185 /* Define __APCS_26__ if the PC also contains the PSR */
186 #define CPP_APCS_PC_SPEC "\
187 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
189 %{mapcs-26:-D__APCS_26__} \
190 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
193 #ifndef CPP_APCS_PC_DEFAULT_SPEC
194 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
197 #define CPP_FLOAT_SPEC "\
199 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
201 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
204 /* Default is hard float, which doesn't define anything */
205 #define CPP_FLOAT_DEFAULT_SPEC ""
207 #define CPP_ENDIAN_SPEC "\
210 %e-mbig-endian and -mlittle-endian may not be used together} \
211 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
212 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
215 /* Default is little endian, which doesn't define anything. */
216 #define CPP_ENDIAN_DEFAULT_SPEC ""
220 /* This macro defines names of additional specifications to put in the specs
221 that can be used in various specifications like CC1_SPEC. Its definition
222 is an initializer with a subgrouping for each command option.
224 Each subgrouping contains a string constant, that defines the
225 specification name, and a string constant that used by the GNU CC driver
228 Do not define this macro if it does not need to do anything. */
229 #define EXTRA_SPECS \
230 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
231 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
232 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
233 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
234 { "cpp_float", CPP_FLOAT_SPEC }, \
235 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
236 { "cpp_endian", CPP_ENDIAN_SPEC }, \
237 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
238 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
239 SUBTARGET_EXTRA_SPECS
241 #define SUBTARGET_EXTRA_SPECS
242 #define SUBTARGET_CPP_SPEC ""
245 /* Run-time Target Specification. */
246 #ifndef TARGET_VERSION
247 #define TARGET_VERSION \
248 fputs (" (ARM/generic)", stderr);
251 /* Run-time compilation parameters selecting different hardware subsets. */
252 extern int target_flags;
254 /* The floating point instruction architecture, can be 2 or 3 */
255 extern const char * target_fp_name;
257 /* Nonzero if the function prologue (and epilogue) should obey
258 the ARM Procedure Call Standard. */
259 #define ARM_FLAG_APCS_FRAME (0x0001)
261 /* Nonzero if the function prologue should output the function name to enable
262 the post mortem debugger to print a backtrace (very useful on RISCOS,
263 unused on RISCiX). Specifying this flag also enables
264 -fno-omit-frame-pointer.
265 XXX Must still be implemented in the prologue. */
266 #define ARM_FLAG_POKE (0x0002)
268 /* Nonzero if floating point instructions are emulated by the FPE, in which
269 case instruction scheduling becomes very uninteresting. */
270 #define ARM_FLAG_FPE (0x0004)
272 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
273 that assume restoration of the condition flags when returning from a
274 branch and link (ie a function). */
275 #define ARM_FLAG_APCS_32 (0x0020)
277 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
279 /* Nonzero if stack checking should be performed on entry to each function
280 which allocates temporary variables on the stack. */
281 #define ARM_FLAG_APCS_STACK (0x0040)
283 /* Nonzero if floating point parameters should be passed to functions in
284 floating point registers. */
285 #define ARM_FLAG_APCS_FLOAT (0x0080)
287 /* Nonzero if re-entrant, position independent code should be generated.
288 This is equivalent to -fpic. */
289 #define ARM_FLAG_APCS_REENT (0x0100)
291 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
292 loaded byte-at-a-time. */
293 #define ARM_FLAG_SHORT_BYTE (0x0200)
295 /* Nonzero if all floating point instructions are missing (and there is no
296 emulator either). Generate function calls for all ops in this case. */
297 #define ARM_FLAG_SOFT_FLOAT (0x0400)
299 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
300 #define ARM_FLAG_BIG_END (0x0800)
302 /* Nonzero if we should compile for Thumb interworking. */
303 #define ARM_FLAG_THUMB (0x1000)
305 /* Nonzero if we should have little-endian words even when compiling for
306 big-endian (for backwards compatibility with older versions of GCC). */
307 #define ARM_FLAG_LITTLE_WORDS (0x2000)
309 /* Nonzero if we need to protect the prolog from scheduling */
310 #define ARM_FLAG_NO_SCHED_PRO (0x4000)
312 /* Nonzero if a call to abort should be generated if a noreturn
313 function tries to return. */
314 #define ARM_FLAG_ABORT_NORETURN (0x8000)
316 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
317 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
318 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
319 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
320 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
321 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
322 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
323 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
324 that short values should not be accessed using word load instructions
325 as there is a possibility that they may not be word aligned and this
326 would generate an MMU fault. On processors which do not have a 16 bit
327 load instruction therefore, short values must be loaded by individual
328 byte accesses rather than loading a word and then shifting the desired
330 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
331 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
332 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
333 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
334 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
335 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
336 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
337 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
339 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
340 Bit 31 is reserved. See riscix.h. */
341 #ifndef SUBTARGET_SWITCHES
342 #define SUBTARGET_SWITCHES
345 #define TARGET_SWITCHES \
347 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
348 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
349 "Generate APCS conformant stack frames" }, \
350 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
351 {"poke-function-name", ARM_FLAG_POKE, \
352 "Store function names in object code" }, \
353 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
354 {"fpe", ARM_FLAG_FPE, "" }, \
355 {"apcs-32", ARM_FLAG_APCS_32, \
356 "Use the 32bit version of the APCS" }, \
357 {"apcs-26", -ARM_FLAG_APCS_32, \
358 "Use the 26bit version of the APCS" }, \
359 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
360 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
361 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
362 "Pass FP arguments in FP registers" }, \
363 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
364 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
365 "Generate re-entrant, PIC code" }, \
366 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
367 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
368 "Load shorts a byte at a time" }, \
369 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
370 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
371 "Load words a byte at a time" }, \
372 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
373 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
374 "Use library calls to perform FP operations" }, \
375 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
376 "Use hardware floating point instructions" }, \
377 {"big-endian", ARM_FLAG_BIG_END, \
378 "Assume target CPU is configured as big endian" }, \
379 {"little-endian", -ARM_FLAG_BIG_END, \
380 "Assume target CPU is configured as little endian" }, \
381 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
382 "Assume big endian bytes, little endian words" }, \
383 {"thumb-interwork", ARM_FLAG_THUMB, \
384 "Support calls between THUMB and ARM instructions sets" }, \
385 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \
386 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
387 "Generate a call to abort if a noreturn function returns"}, \
388 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
389 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
390 "Do not move instructions into a function's prologue" }, \
391 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
393 {"", TARGET_DEFAULT } \
396 #define TARGET_OPTIONS \
398 {"cpu=", & arm_select[0].string, \
399 "Specify the name of the target CPU" }, \
400 {"arch=", & arm_select[1].string, \
401 "Specify the name of the target architecture" }, \
402 {"tune=", & arm_select[2].string, "" }, \
403 {"fpe=", & target_fp_name, "" }, \
404 {"fp=", & target_fp_name, \
405 "Specify the version of the floating point emulator" }, \
406 { "structure-size-boundary=", & structure_size_string, \
407 "Specify the minumum bit alignment of structures" } \
410 struct arm_cpu_select
414 const struct processors * processors;
417 /* This is a magic array. If the user specifies a command line switch
418 which matches one of the entries in TARGET_OPTIONS then the corresponding
419 string pointer will be set to the value specified by the user. */
420 extern struct arm_cpu_select arm_select[];
428 /* Recast the program mode class to be the prog_mode attribute */
429 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
431 extern enum prog_mode_type arm_prgmode;
433 /* What sort of floating point unit do we have? Hardware or software.
434 If software, is it issue 2 or issue 3? */
435 enum floating_point_type
442 /* Recast the floating point class to be the floating point attribute. */
443 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
445 /* What type of floating point to tune for */
446 extern enum floating_point_type arm_fpu;
448 /* What type of floating point instructions are available */
449 extern enum floating_point_type arm_fpu_arch;
451 /* Default floating point architecture. Override in sub-target if
453 #define FP_DEFAULT FP_SOFT2
455 /* Nonzero if the processor has a fast multiply insn, and one that does
456 a 64-bit multiply of two 32-bit values. */
457 extern int arm_fast_multiply;
459 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
460 extern int arm_arch4;
462 /* Nonzero if this chip can benefit from load scheduling. */
463 extern int arm_ld_sched;
465 /* Nonzero if this chip is a StrongARM. */
466 extern int arm_is_strong;
468 /* Nonzero if this chip is a an ARM6 or an ARM7. */
469 extern int arm_is_6_or_7;
471 #ifndef TARGET_DEFAULT
472 #define TARGET_DEFAULT 0
475 /* The frame pointer register used in gcc has nothing to do with debugging;
476 that is controlled by the APCS-FRAME option. */
477 /* Not fully implemented yet */
478 /* #define CAN_DEBUG_WITHOUT_FP 1 */
480 #define TARGET_MEM_FUNCTIONS 1
482 #define OVERRIDE_OPTIONS arm_override_options ()
484 /* Nonzero if PIC code requires explicit qualifiers to generate
485 PLT and GOT relocs rather than the assembler doing so implicitly.
486 Subtargets can override this if required. */
488 #define NEED_PLT_GOT 0
491 /* Nonzero if we need to refer to the GOT with a PC-relative
492 offset. In other words, generate
494 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
498 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
500 The default is true, which matches NetBSD. Subtargets can
501 override this if required. */
506 /* Target machine storage Layout. */
509 /* Define this macro if it is advisable to hold scalars in registers
510 in a wider mode than that declared by the program. In such cases,
511 the value is constrained to be within the bounds of the declared
512 type, but kept valid in the wider mode. The signedness of the
513 extension may differ from that of the type. */
515 /* It is far faster to zero extend chars than to sign extend them */
517 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
518 if (GET_MODE_CLASS (MODE) == MODE_INT \
519 && GET_MODE_SIZE (MODE) < 4) \
521 if (MODE == QImode) \
523 else if (MODE == HImode) \
524 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
528 /* Define this macro if the promotion described by `PROMOTE_MODE'
529 should also be done for outgoing function arguments. */
530 /* This is required to ensure that push insns always push a word. */
531 #define PROMOTE_FUNCTION_ARGS
533 /* Define for XFmode extended real floating point support.
534 This will automatically cause REAL_ARITHMETIC to be defined. */
536 I think I have added all the code to make this work. Unfortunately,
537 early releases of the floating point emulation code on RISCiX used a
538 different format for extended precision numbers. On my RISCiX box there
539 is a bug somewhere which causes the machine to lock up when running enquire
540 with long doubles. There is the additional aspect that Norcroft C
541 treats long doubles as doubles and we ought to remain compatible.
542 Perhaps someone with an FPA coprocessor and not running RISCiX would like
543 to try this someday. */
544 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
546 /* Disable XFmode patterns in md file */
547 #define ENABLE_XF_PATTERNS 0
549 /* Define if you don't want extended real, but do want to use the
550 software floating point emulator for REAL_ARITHMETIC and
551 decimal <-> binary conversion. */
552 /* See comment above */
553 #define REAL_ARITHMETIC
555 /* Define this if most significant bit is lowest numbered
556 in instructions that operate on numbered bit-fields. */
557 #define BITS_BIG_ENDIAN 0
559 /* Define this if most significant byte of a word is the lowest numbered.
560 Most ARM processors are run in little endian mode, so that is the default.
561 If you want to have it run-time selectable, change the definition in a
562 cover file to be TARGET_BIG_ENDIAN. */
563 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
565 /* Define this if most significant word of a multiword number is the lowest
567 This is always false, even when in big-endian mode. */
568 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
570 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
571 on processor pre-defineds when compiling libgcc2.c. */
572 #if defined(__ARMEB__) && !defined(__ARMWEL__)
573 #define LIBGCC2_WORDS_BIG_ENDIAN 1
575 #define LIBGCC2_WORDS_BIG_ENDIAN 0
578 /* Define this if most significant word of doubles is the lowest numbered.
579 This is always true, even when in little-endian mode. */
580 #define FLOAT_WORDS_BIG_ENDIAN 1
582 /* Number of bits in an addressable storage unit */
583 #define BITS_PER_UNIT 8
585 #define BITS_PER_WORD 32
587 #define UNITS_PER_WORD 4
589 #define POINTER_SIZE 32
591 #define PARM_BOUNDARY 32
593 #define STACK_BOUNDARY 32
595 #define FUNCTION_BOUNDARY 32
597 #define EMPTY_FIELD_BOUNDARY 32
599 #define BIGGEST_ALIGNMENT 32
601 /* Make strings word-aligned so strcpy from constants will be faster. */
602 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
603 (TREE_CODE (EXP) == STRING_CST \
604 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
606 /* Every structures size must be a multiple of 32 bits. */
607 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
608 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
610 #ifndef STRUCTURE_SIZE_BOUNDARY
611 #define STRUCTURE_SIZE_BOUNDARY 32
614 /* Used when parsing command line option -mstructure_size_boundary. */
615 extern const char * structure_size_string;
617 /* Non-zero if move instructions will actually fail to work
618 when given unaligned data. */
619 #define STRICT_ALIGNMENT 1
621 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
624 /* Standard register usage. */
626 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
627 (S - saved over call).
629 r0 * argument word/integer result
632 r4-r8 S register variable
633 r9 S (rfp) register variable (real frame pointer)
635 r10 F S (sl) stack limit (used by -mapcs-stack-check)
636 r11 F S (fp) argument pointer
637 r12 (ip) temp workspace
638 r13 F S (sp) lower end of current stack frame
639 r14 (lr) link address/workspace
640 r15 F (pc) program counter
642 f0 floating point result
643 f1-f3 floating point scratch
645 f4-f7 S floating point variable
647 cc This is NOT a real register, but is used internally
648 to represent things that use or set the condition
650 sfp This isn't either. It is used during rtl generation
651 since the offset between the frame pointer and the
652 auto's isn't known until after register allocation.
653 afp Nor this, we only need this because of non-local
654 goto. Without it fp appears to be used and the
655 elimination code won't get rid of sfp. It tracks
656 fp exactly at all times.
658 *: See CONDITIONAL_REGISTER_USAGE */
660 /* The stack backtrace structure is as follows:
661 fp points to here: | save code pointer | [fp]
662 | return link value | [fp, #-4]
663 | return sp value | [fp, #-8]
664 | return fp value | [fp, #-12]
665 [| saved r10 value |]
676 [| saved f7 value |] three words
677 [| saved f6 value |] three words
678 [| saved f5 value |] three words
679 [| saved f4 value |] three words
680 r0-r3 are not normally saved in a C function. */
682 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
683 #define FIRST_PSEUDO_REGISTER 27
685 /* 1 for registers that have pervasive standard uses
686 and are not available for the register allocator. */
687 #define FIXED_REGISTERS \
695 /* 1 for registers not available across function calls.
696 These must include the FIXED_REGISTERS and also any
697 registers that can be used without being saved.
698 The latter must include the registers where values are returned
699 and the register where structure-value addresses are passed.
700 Aside from that, you can include as many other registers as you like.
701 The CC is not preserved over function calls on the ARM 6, so it is
702 easier to assume this for all. SFP is preserved, since FP is. */
703 #define CALL_USED_REGISTERS \
711 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
712 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
715 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
716 trampled. This effectively reduces the number of available registers by 1.
717 XXX It is a hack, I know.
718 XXX Is this still needed? */
719 #define CONDITIONAL_REGISTER_USAGE \
723 if (TARGET_SOFT_FLOAT) \
726 for (regno = 16; regno < 24; ++regno) \
727 fixed_regs[regno] = call_used_regs[regno] = 1; \
731 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
732 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
734 else if (TARGET_APCS_STACK) \
736 fixed_regs[10] = 1; \
737 call_used_regs[10] = 1; \
739 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
742 /* Return number of consecutive hard regs needed starting at reg REGNO
743 to hold something of mode MODE.
744 This is ordinarily the length in words of a value of mode MODE
745 but can be less for certain modes in special long registers.
747 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
749 #define HARD_REGNO_NREGS(REGNO, MODE) \
750 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
751 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
752 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
754 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
755 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
757 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
758 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
759 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
760 || REGNO == ARG_POINTER_REGNUM \
761 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
763 /* Value is 1 if it is a good idea to tie two pseudo registers
764 when one has mode MODE1 and one has mode MODE2.
765 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
766 for any hard reg, then this must be 0 for correct output. */
767 #define MODES_TIEABLE_P(MODE1, MODE2) \
768 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
770 /* Specify the registers used for certain standard purposes.
771 The values of these macros are register numbers. */
773 /* Define this if the program counter is overloaded on a register. */
776 /* Register to use for pushing function arguments. */
777 #define STACK_POINTER_REGNUM 13
779 /* Base register for access to local variables of the function. */
780 #define FRAME_POINTER_REGNUM 25
782 /* Define this to be where the real frame pointer is if it is not possible to
783 work out the offset between the frame pointer and the automatic variables
784 until after register allocation has taken place. FRAME_POINTER_REGNUM
785 should point to a special register that we will make sure is eliminated. */
786 #define HARD_FRAME_POINTER_REGNUM 11
788 /* Value should be nonzero if functions must have frame pointers.
789 Zero means the frame pointer need not be set up (and parms may be accessed
790 via the stack pointer) in functions that seem suitable.
791 If we have to have a frame pointer we might as well make use of it.
792 APCS says that the frame pointer does not need to be pushed in leaf
793 functions, or simple tail call functions. */
794 #define FRAME_POINTER_REQUIRED \
795 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
797 /* Base register for access to arguments of the function. */
798 #define ARG_POINTER_REGNUM 26
800 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
801 as an invisible last argument (possible since varargs don't exist in
802 Pascal), so the following is not true. */
803 #define STATIC_CHAIN_REGNUM 8
805 /* Register in which address to store a structure value
806 is passed to a function. */
807 #define STRUCT_VALUE_REGNUM 0
809 /* Internal, so that we don't need to refer to a raw number */
812 /* The order in which register should be allocated. It is good to use ip
813 since no saving is required (though calls clobber it) and it never contains
814 function parameters. It is quite good to use lr since other calls may
815 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
816 least likely to contain a function parameter; in addition results are
819 #define REG_ALLOC_ORDER \
821 3, 2, 1, 0, 12, 14, 4, 5, \
822 6, 7, 8, 10, 9, 11, 13, 15, \
823 16, 17, 18, 19, 20, 21, 22, 23, \
827 /* Register and constant classes. */
829 /* Register classes: all ARM regs or all FPU regs---simple! */
839 #define N_REG_CLASSES (int) LIM_REG_CLASSES
841 /* Give names of register classes as strings for dump file. */
842 #define REG_CLASS_NAMES \
850 /* Define which registers fit in which classes.
851 This is an initializer for a vector of HARD_REG_SET
852 of length N_REG_CLASSES. */
853 #define REG_CLASS_CONTENTS \
855 { 0x0000000 }, /* NO_REGS */ \
856 { 0x0FF0000 }, /* FPU_REGS */ \
857 { 0x200FFFF }, /* GENERAL_REGS */ \
858 { 0x2FFFFFF } /* ALL_REGS */ \
861 /* The same information, inverted:
862 Return the class number of the smallest class containing
863 reg number REGNO. This could be a conditional expression
864 or could index an array. */
865 #define REGNO_REG_CLASS(REGNO) \
866 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
867 || REGNO == ARG_POINTER_REGNUM) \
868 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
869 ? NO_REGS : FPU_REGS)
871 /* The class value for index registers, and the one for base regs. */
872 #define INDEX_REG_CLASS GENERAL_REGS
873 #define BASE_REG_CLASS GENERAL_REGS
875 /* Get reg_class from a letter such as appears in the machine description.
876 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
877 #define REG_CLASS_FROM_LETTER(C) \
878 ((C)=='f' ? FPU_REGS : NO_REGS)
880 /* The letters I, J, K, L and M in a register constraint string
881 can be used to stand for particular ranges of immediate operands.
882 This macro defines what the ranges are.
883 C is the letter, and VALUE is a constant value.
884 Return 1 if VALUE is in the range specified by C.
885 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
886 J: valid indexing constants.
887 K: ~value ok in rhs argument of data operand.
888 L: -value ok in rhs argument of data operand.
889 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
890 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
891 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
892 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
893 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
894 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
895 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
896 || (((VALUE) & ((VALUE) - 1)) == 0)) \
899 /* For the ARM, `Q' means that this is a memory operand that is just
900 an offset from a register.
901 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
902 address. This means that the symbol is in the text segment and can be
903 accessed without using a load. */
905 #define EXTRA_CONSTRAINT(OP, C) \
906 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
907 : (C) == 'R' ? (GET_CODE (OP) == MEM \
908 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
909 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
910 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
913 /* Constant letter 'G' for the FPU immediate constants.
914 'H' means the same constant negated. */
915 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
916 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
917 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
919 /* Given an rtx X being reloaded into a reg required to be
920 in class CLASS, return the class of reg to actually use.
921 In general this is just CLASS; but on some machines
922 in some cases it is preferable to use a more restrictive class. */
923 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
925 /* Return the register class of a scratch register needed to copy IN into
926 or out of a register in CLASS in MODE. If it can be done directly,
927 NO_REGS is returned. */
928 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
929 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
930 ? GENERAL_REGS : NO_REGS)
932 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
933 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
934 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
935 && (GET_CODE (X) == MEM \
936 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
937 && true_regnum (X) == -1))) \
938 ? GENERAL_REGS : NO_REGS)
940 /* Try a machine-dependent way of reloading an illegitimate address
941 operand. If we find one, push the reload and jump to WIN. This
942 macro is used in only one place: `find_reloads_address' in reload.c.
944 For the ARM, we wish to handle large displacements off a base
945 register by splitting the addend across a MOV and the mem insn.
946 This can cut the number of reloads needed. */
947 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
949 if (GET_CODE (X) == PLUS \
950 && GET_CODE (XEXP (X, 0)) == REG \
951 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
952 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
953 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
955 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
956 HOST_WIDE_INT low, high; \
958 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
959 low = ((val & 0xf) ^ 0x8) - 0x8; \
960 else if (MODE == SImode || MODE == QImode \
961 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
962 || (MODE == HImode && ! arm_arch4)) \
963 /* Need to be careful, -4096 is not a valid offset */ \
964 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
965 else if (MODE == HImode && arm_arch4) \
966 /* Need to be careful, -256 is not a valid offset */ \
967 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
968 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
969 && TARGET_HARD_FLOAT) \
970 /* Need to be careful, -1024 is not a valid offset */ \
971 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
975 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
976 /* Check for overflow or zero */ \
977 if (low == 0 || high == 0 || (high + low != val)) \
980 /* Reload the high part into a base reg; leave the low part \
982 X = gen_rtx_PLUS (GET_MODE (X), \
983 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
986 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
987 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
993 /* Return the maximum number of consecutive registers
994 needed to represent mode MODE in a register of class CLASS.
995 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
996 #define CLASS_MAX_NREGS(CLASS, MODE) \
997 ((CLASS) == FPU_REGS ? 1 \
998 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1000 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1001 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1002 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1003 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1006 /* Stack layout; function entry, exit and calling. */
1008 /* Define this if pushing a word on the stack
1009 makes the stack pointer a smaller address. */
1010 #define STACK_GROWS_DOWNWARD 1
1012 /* Define this if the nominal address of the stack frame
1013 is at the high-address end of the local variables;
1014 that is, each additional local variable allocated
1015 goes at a more negative offset in the frame. */
1016 #define FRAME_GROWS_DOWNWARD 1
1018 /* Offset within stack frame to start allocating local variables at.
1019 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1020 first local allocated. Otherwise, it is the offset to the BEGINNING
1021 of the first local allocated. */
1022 #define STARTING_FRAME_OFFSET 0
1024 /* If we generate an insn to push BYTES bytes,
1025 this says how many the stack pointer really advances by. */
1026 /* The push insns do not do this rounding implicitly. So don't define this. */
1027 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1029 /* Define this if the maximum size of all the outgoing args is to be
1030 accumulated and pushed during the prologue. The amount can be
1031 found in the variable current_function_outgoing_args_size. */
1032 #define ACCUMULATE_OUTGOING_ARGS
1034 /* Offset of first parameter from the argument pointer register value. */
1035 #define FIRST_PARM_OFFSET(FNDECL) 4
1037 /* Value is the number of byte of arguments automatically
1038 popped when returning from a subroutine call.
1039 FUNDECL is the declaration node of the function (as a tree),
1040 FUNTYPE is the data type of the function (as a tree),
1041 or for a library call it is an identifier node for the subroutine name.
1042 SIZE is the number of bytes of arguments passed on the stack.
1044 On the ARM, the caller does not pop any of its arguments that were passed
1046 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1048 /* Define how to find the value returned by a function.
1049 VALTYPE is the data type of the value (as a tree).
1050 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1051 otherwise, FUNC is 0. */
1052 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1053 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
1054 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
1055 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))
1057 /* Define how to find the value returned by a library function
1058 assuming the value has mode MODE. */
1059 #define LIBCALL_VALUE(MODE) \
1060 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1061 ? gen_rtx_REG (MODE, 16) \
1062 : gen_rtx_REG (MODE, 0))
1064 /* 1 if N is a possible register number for a function value.
1065 On the ARM, only r0 and f0 can return results. */
1066 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1067 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1069 /* How large values are returned */
1070 /* A C expression which can inhibit the returning of certain function values
1071 in registers, based on the type of value. */
1072 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1074 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1075 values must be in memory. On the ARM, they need only do so if larger
1076 than a word, or if they contain elements offset from zero in the struct. */
1077 #define DEFAULT_PCC_STRUCT_RETURN 0
1079 /* Define where to put the arguments to a function.
1080 Value is zero to push the argument on the stack,
1081 or a hard register in which to store the argument.
1083 MODE is the argument's machine mode.
1084 TYPE is the data type of the argument (as a tree).
1085 This is null for libcalls where that information may
1087 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1088 the preceding args and about the function being called.
1089 NAMED is nonzero if this argument is a named parameter
1090 (otherwise it is an extra parameter matching an ellipsis).
1092 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1093 other arguments are passed on the stack. If (NAMED == 0) (which happens
1094 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1095 passed in the stack (function_prologue will indeed make it pass in the
1096 stack if necessary). */
1097 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1099 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \
1102 /* For an arg passed partly in registers and partly in memory,
1103 this is the number of registers used.
1104 For args passed entirely in registers or entirely in memory, zero. */
1105 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1106 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
1107 ? GET_MODE_SIZE (MODE) \
1108 : int_size_in_bytes (TYPE)) \
1109 ? 4 - (CUM) / 4 : 0)
1111 /* A C type for declaring a variable that is used as the first argument of
1112 `FUNCTION_ARG' and other related values. For some target machines, the
1113 type `int' suffices and can hold the number of bytes of argument so far.
1115 On the ARM, this is the number of bytes of arguments scanned so far. */
1116 #define CUMULATIVE_ARGS int
1118 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1119 for a call to a function whose data type is FNTYPE.
1120 For a library call, FNTYPE is 0.
1121 On the ARM, the offset starts at 0. */
1122 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1123 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1125 /* Update the data in CUM to advance over an argument
1126 of mode MODE and data type TYPE.
1127 (TYPE is null for libcalls where that information may not be available.) */
1128 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1129 (CUM) += ((MODE) != BLKmode \
1130 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1131 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1133 /* 1 if N is a possible register number for function argument passing.
1134 On the ARM, r0-r3 are used to pass args. */
1135 #define FUNCTION_ARG_REGNO_P(REGNO) \
1136 ((REGNO) >= 0 && (REGNO) <= 3)
1138 /* Perform any actions needed for a function that is receiving a variable
1139 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1140 of the current parameter. PRETEND_SIZE is a variable that should be set to
1141 the amount of stack that must be pushed by the prolog to pretend that our
1144 Normally, this macro will push all remaining incoming registers on the
1145 stack and set PRETEND_SIZE to the length of the registers pushed.
1147 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1148 named arg and all anonymous args onto the stack.
1149 XXX I know the prologue shouldn't be pushing registers, but it is faster
1151 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1153 extern int current_function_anonymous_args; \
1154 current_function_anonymous_args = 1; \
1156 (PRETEND_SIZE) = 16 - (CUM); \
1159 /* Generate assembly output for the start of a function. */
1160 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1161 output_func_prologue ((STREAM), (SIZE))
1163 /* If your target environment doesn't prefix user functions with an
1164 underscore, you may wish to re-define this to prevent any conflicts.
1165 e.g. AOF may prefix mcount with an underscore. */
1166 #ifndef ARM_MCOUNT_NAME
1167 #define ARM_MCOUNT_NAME "*mcount"
1170 /* Call the function profiler with a given profile label. The Acorn
1171 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1172 On the ARM the full profile code will look like:
1181 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1182 will output the .text section.
1184 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1185 ``prof'' doesn't seem to mind about this! */
1186 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1191 fprintf ((STREAM), "\tmov\t%s%s, %s%s\n\tbl\t", \
1192 REGISTER_PREFIX, reg_names[12] /* ip */, \
1193 REGISTER_PREFIX, reg_names[14] /* lr */); \
1194 assemble_name ((STREAM), ARM_MCOUNT_NAME); \
1195 fputc ('\n', (STREAM)); \
1196 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", (LABELNO)); \
1197 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1198 ASM_OUTPUT_INT ((STREAM), sym); \
1201 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1202 the stack pointer does not matter. The value is tested only in
1203 functions that have frame pointers.
1204 No definition is equivalent to always zero.
1206 On the ARM, the function epilogue recovers the stack pointer from the
1208 #define EXIT_IGNORE_STACK 1
1210 /* Generate the assembly code for function exit. */
1211 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1212 output_func_epilogue ((STREAM), (SIZE))
1214 /* Determine if the epilogue should be output as RTL.
1215 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1216 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1218 /* Definitions for register eliminations.
1220 This is an array of structures. Each structure initializes one pair
1221 of eliminable registers. The "from" register number is given first,
1222 followed by "to". Eliminations of the same "from" register are listed
1223 in order of preference.
1225 We have two registers that can be eliminated on the ARM. First, the
1226 arg pointer register can often be eliminated in favor of the stack
1227 pointer register. Secondly, the pseudo frame pointer register can always
1228 be eliminated; it is replaced with either the stack or the real frame
1231 #define ELIMINABLE_REGS \
1232 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1233 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1234 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1235 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1237 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1238 Frame pointer elimination is automatically handled.
1240 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1241 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1242 pointer, we must eliminate FRAME_POINTER_REGNUM into
1243 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1244 #define CAN_ELIMINATE(FROM, TO) \
1245 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1247 /* Define the offset between two registers, one to be eliminated, and the other
1248 its replacement, at the start of a routine. */
1249 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1251 int volatile_func = arm_volatile_func (); \
1252 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1254 else if ((FROM) == FRAME_POINTER_REGNUM \
1255 && (TO) == STACK_POINTER_REGNUM) \
1256 (OFFSET) = (current_function_outgoing_args_size \
1257 + ((get_frame_size () + 3) & ~3)); \
1262 int saved_hard_reg = 0; \
1264 if (! volatile_func) \
1266 for (regno = 0; regno <= 10; regno++) \
1267 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1268 saved_hard_reg = 1, offset += 4; \
1269 /* PIC register is a fixed reg, so call_used_regs set. */ \
1270 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1271 saved_hard_reg = 1, offset += 4; \
1272 for (regno = 16; regno <=23; regno++) \
1273 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1276 if ((FROM) == FRAME_POINTER_REGNUM) \
1277 (OFFSET) = -offset; \
1280 if (! frame_pointer_needed) \
1282 if (! volatile_func \
1283 && (regs_ever_live[14] || saved_hard_reg)) \
1285 offset += current_function_outgoing_args_size; \
1286 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1291 /* Output assembler code for a block containing the constant parts
1292 of a trampoline, leaving space for the variable parts.
1294 On the ARM, (if r8 is the static chain regnum, and remembering that
1295 referencing pc adds an offset of 8) the trampoline looks like:
1298 .word static chain value
1299 .word function's address
1300 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1301 #define TRAMPOLINE_TEMPLATE(FILE) \
1303 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1304 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1305 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1306 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1307 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1308 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1309 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1310 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1313 /* Length in units of the trampoline for entering a nested function. */
1314 #define TRAMPOLINE_SIZE 16
1316 /* Alignment required for a trampoline in units. */
1317 #define TRAMPOLINE_ALIGN 4
1319 /* Emit RTL insns to initialize the variable parts of a trampoline.
1320 FNADDR is an RTX for the address of the function's pure code.
1321 CXT is an RTX for the static chain value for the function. */
1322 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1324 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1326 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1331 /* Addressing modes, and classification of registers for them. */
1333 #define HAVE_POST_INCREMENT 1
1334 #define HAVE_PRE_INCREMENT 1
1335 #define HAVE_POST_DECREMENT 1
1336 #define HAVE_PRE_DECREMENT 1
1338 /* Macros to check register numbers against specific register classes. */
1340 /* These assume that REGNO is a hard or pseudo reg number.
1341 They give nonzero only if REGNO is a hard reg of the suitable class
1342 or a pseudo reg currently allocated to a suitable hard reg.
1343 Since they use reg_renumber, they are safe only once reg_renumber
1344 has been allocated, which happens in local-alloc.c.
1346 On the ARM, don't allow the pc to be used. */
1347 #define REGNO_OK_FOR_BASE_P(REGNO) \
1348 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1349 || (REGNO) == ARG_POINTER_REGNUM \
1350 || (unsigned) reg_renumber[(REGNO)] < 15 \
1351 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1352 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1353 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1354 REGNO_OK_FOR_BASE_P(REGNO)
1356 /* Maximum number of registers that can appear in a valid memory address.
1357 Shifts in addresses can't be by a register. */
1359 #define MAX_REGS_PER_ADDRESS 2
1361 /* Recognize any constant value that is a valid address. */
1362 /* XXX We can address any constant, eventually... */
1364 #ifdef AOF_ASSEMBLER
1366 #define CONSTANT_ADDRESS_P(X) \
1367 (GET_CODE (X) == SYMBOL_REF \
1368 && CONSTANT_POOL_ADDRESS_P (X))
1372 #define CONSTANT_ADDRESS_P(X) \
1373 (GET_CODE (X) == SYMBOL_REF \
1374 && (CONSTANT_POOL_ADDRESS_P (X) \
1375 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1377 #endif /* AOF_ASSEMBLER */
1379 /* Nonzero if the constant value X is a legitimate general operand.
1380 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1382 On the ARM, allow any integer (invalid ones are removed later by insn
1383 patterns), nice doubles and symbol_refs which refer to the function's
1384 constant pool XXX. */
1385 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1387 /* Symbols in the text segment can be accessed without indirecting via the
1388 constant pool; it may take an extra binary operation, but this is still
1389 faster than indirecting via memory. Don't do this when not optimizing,
1390 since we won't be calculating al of the offsets necessary to do this
1392 /* This doesn't work with AOF syntax, since the string table may be in
1393 a different AREA. */
1394 #ifndef AOF_ASSEMBLER
1395 #define ENCODE_SECTION_INFO(decl) \
1397 if (optimize > 0 && TREE_CONSTANT (decl) \
1398 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1400 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1401 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1402 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1407 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1408 and check its validity for a certain class.
1409 We have two alternate definitions for each of them.
1410 The usual definition accepts all pseudo regs; the other rejects
1411 them unless they have been allocated suitable hard regs.
1412 The symbol REG_OK_STRICT causes the latter definition to be used. */
1413 #ifndef REG_OK_STRICT
1415 /* Nonzero if X is a hard reg that can be used as a base reg
1416 or if it is a pseudo reg. */
1417 #define REG_OK_FOR_BASE_P(X) \
1418 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1419 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1421 /* Nonzero if X is a hard reg that can be used as an index
1422 or if it is a pseudo reg. */
1423 #define REG_OK_FOR_INDEX_P(X) \
1424 REG_OK_FOR_BASE_P(X)
1426 #define REG_OK_FOR_PRE_POST_P(X) \
1427 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1428 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1432 /* Nonzero if X is a hard reg that can be used as a base reg. */
1433 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1435 /* Nonzero if X is a hard reg that can be used as an index. */
1436 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1438 #define REG_OK_FOR_PRE_POST_P(X) \
1439 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1440 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1441 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1442 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1446 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1447 that is a valid memory address for an instruction.
1448 The MODE argument is the machine mode for the MEM expression
1449 that wants to use this address.
1451 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1452 #define BASE_REGISTER_RTX_P(X) \
1453 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1455 #define INDEX_REGISTER_RTX_P(X) \
1456 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1458 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1459 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1460 only be small constants. */
1461 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1464 HOST_WIDE_INT range; \
1465 enum rtx_code code = GET_CODE (INDEX); \
1467 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1469 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1470 && INTVAL (INDEX) > -1024 \
1471 && (INTVAL (INDEX) & 3) == 0) \
1476 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1478 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1479 && (! arm_arch4 || (MODE) != HImode)) \
1481 rtx xiop0 = XEXP (INDEX, 0); \
1482 rtx xiop1 = XEXP (INDEX, 1); \
1483 if (INDEX_REGISTER_RTX_P (xiop0) \
1484 && power_of_two_operand (xiop1, SImode)) \
1486 if (INDEX_REGISTER_RTX_P (xiop1) \
1487 && power_of_two_operand (xiop0, SImode)) \
1490 if (GET_MODE_SIZE (MODE) <= 4 \
1491 && (code == LSHIFTRT || code == ASHIFTRT \
1492 || code == ASHIFT || code == ROTATERT) \
1493 && (! arm_arch4 || (MODE) != HImode)) \
1495 rtx op = XEXP (INDEX, 1); \
1496 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1497 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1498 && INTVAL (op) <= 31) \
1501 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1502 range = ((MODE) == HImode || (MODE) == QImode) \
1503 ? (arm_arch4 ? 256 : 4095) : 4096; \
1504 if (code == CONST_INT && INTVAL (INDEX) < range \
1505 && INTVAL (INDEX) > -range) \
1510 /* Jump to LABEL if X is a valid address RTX. This must also take
1511 REG_OK_STRICT into account when deciding about valid registers, but it uses
1512 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1513 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1514 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1515 refs must be forced though a static cell to ensure addressability. */
1516 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1518 if (BASE_REGISTER_RTX_P (X)) \
1520 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1521 && GET_CODE (XEXP (X, 0)) == REG \
1522 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1524 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1525 && (GET_CODE (X) == LABEL_REF \
1526 || (GET_CODE (X) == CONST \
1527 && GET_CODE (XEXP ((X), 0)) == PLUS \
1528 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1529 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1531 else if ((MODE) == TImode) \
1533 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1535 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1536 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1538 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1539 if (val == 4 || val == -4 || val == -8) \
1543 else if (GET_CODE (X) == PLUS) \
1545 rtx xop0 = XEXP(X,0); \
1546 rtx xop1 = XEXP(X,1); \
1548 if (BASE_REGISTER_RTX_P (xop0)) \
1549 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1550 else if (BASE_REGISTER_RTX_P (xop1)) \
1551 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1553 /* Reload currently can't handle MINUS, so disable this for now */ \
1554 /* else if (GET_CODE (X) == MINUS) \
1556 rtx xop0 = XEXP (X,0); \
1557 rtx xop1 = XEXP (X,1); \
1559 if (BASE_REGISTER_RTX_P (xop0)) \
1560 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1562 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1563 && GET_CODE (X) == SYMBOL_REF \
1564 && CONSTANT_POOL_ADDRESS_P (X) \
1566 && symbol_mentioned_p (get_pool_constant (X)))) \
1568 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1569 && (GET_MODE_SIZE (MODE) <= 4) \
1570 && GET_CODE (XEXP (X, 0)) == REG \
1571 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1575 /* Try machine-dependent ways of modifying an illegitimate address
1576 to be legitimate. If we find one, return the new, valid address.
1577 This macro is used in only one place: `memory_address' in explow.c.
1579 OLDX is the address as it was before break_out_memory_refs was called.
1580 In some cases it is useful to look at this to decide what needs to be done.
1582 MODE and WIN are passed so that this macro can use
1583 GO_IF_LEGITIMATE_ADDRESS.
1585 It is always safe for this macro to do nothing. It exists to recognize
1586 opportunities to optimize the output.
1588 On the ARM, try to convert [REG, #BIGCONST]
1589 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1590 where VALIDCONST == 0 in case of TImode. */
1591 extern struct rtx_def *legitimize_pic_address ();
1592 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1594 if (GET_CODE (X) == PLUS) \
1596 rtx xop0 = XEXP (X, 0); \
1597 rtx xop1 = XEXP (X, 1); \
1599 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1600 xop0 = force_reg (SImode, xop0); \
1601 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1602 xop1 = force_reg (SImode, xop1); \
1603 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1605 HOST_WIDE_INT n, low_n; \
1606 rtx base_reg, val; \
1607 n = INTVAL (xop1); \
1609 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1621 low_n = ((MODE) == TImode ? 0 \
1622 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1625 base_reg = gen_reg_rtx (SImode); \
1626 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1627 GEN_INT (n)), NULL_RTX); \
1628 emit_move_insn (base_reg, val); \
1629 (X) = (low_n == 0 ? base_reg \
1630 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1632 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1633 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1635 else if (GET_CODE (X) == MINUS) \
1637 rtx xop0 = XEXP (X, 0); \
1638 rtx xop1 = XEXP (X, 1); \
1640 if (CONSTANT_P (xop0)) \
1641 xop0 = force_reg (SImode, xop0); \
1642 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1643 xop1 = force_reg (SImode, xop1); \
1644 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1645 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1648 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1649 if (memory_address_p (MODE, X)) \
1653 /* Go to LABEL if ADDR (a legitimate address expression)
1654 has an effect that depends on the machine mode it is used for. */
1655 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1657 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1658 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1662 /* Specify the machine mode that this machine uses
1663 for the index in the tablejump instruction. */
1664 #define CASE_VECTOR_MODE SImode
1666 /* Define as C expression which evaluates to nonzero if the tablejump
1667 instruction expects the table to contain offsets from the address of the
1669 Do not define this if the table should contain absolute addresses. */
1670 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1672 /* Specify the tree operation to be used to convert reals to integers. */
1673 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1675 /* This is the kind of divide that is easiest to do in the general case. */
1676 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1678 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1679 unsigned is probably best, but may break some code. */
1680 #ifndef DEFAULT_SIGNED_CHAR
1681 #define DEFAULT_SIGNED_CHAR 0
1684 /* Don't cse the address of the function being compiled. */
1685 #define NO_RECURSIVE_FUNCTION_CSE 1
1687 /* Max number of bytes we can move from memory to memory
1688 in one reasonably fast instruction. */
1691 /* Define if operations between registers always perform the operation
1692 on the full register even if a narrower mode is specified. */
1693 #define WORD_REGISTER_OPERATIONS
1695 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1696 will either zero-extend or sign-extend. The value of this macro should
1697 be the code that says which one of the two operations is implicitly
1698 done, NIL if none. */
1699 #define LOAD_EXTEND_OP(MODE) \
1700 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1701 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1703 /* Define this if zero-extension is slow (more than one real instruction).
1704 On the ARM, it is more than one instruction only if not fetching from
1706 /* #define SLOW_ZERO_EXTEND */
1708 /* Nonzero if access to memory by bytes is slow and undesirable. */
1709 #define SLOW_BYTE_ACCESS 0
1711 /* Immediate shift counts are truncated by the output routines (or was it
1712 the assembler?). Shift counts in a register are truncated by ARM. Note
1713 that the native compiler puts too large (> 32) immediate shift counts
1714 into a register and shifts by the register, letting the ARM decide what
1715 to do instead of doing that itself. */
1716 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1717 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1718 On the arm, Y in a register is used modulo 256 for the shift. Only for
1719 rotates is modulo 32 used. */
1720 /* #define SHIFT_COUNT_TRUNCATED 1 */
1722 /* All integers have the same format so truncation is easy. */
1723 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1725 /* Calling from registers is a massive pain. */
1726 #define NO_FUNCTION_CSE 1
1728 /* Chars and shorts should be passed as ints. */
1729 #define PROMOTE_PROTOTYPES 1
1731 /* The machine modes of pointers and functions */
1732 #define Pmode SImode
1733 #define FUNCTION_MODE Pmode
1735 /* The structure type of the machine dependent info field of insns
1736 No uses for this yet. */
1737 /* #define INSN_MACHINE_INFO struct machine_info */
1739 /* The relative costs of various types of constants. Note that cse.c defines
1740 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1741 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1743 if (const_ok_for_arm (INTVAL (RTX))) \
1744 return (OUTER_CODE) == SET ? 2 : -1; \
1745 else if (OUTER_CODE == AND \
1746 && const_ok_for_arm (~INTVAL (RTX))) \
1748 else if ((OUTER_CODE == COMPARE \
1749 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1750 && const_ok_for_arm (-INTVAL (RTX))) \
1758 case CONST_DOUBLE: \
1759 if (const_double_rtx_ok_for_fpu (RTX)) \
1760 return (OUTER_CODE) == SET ? 2 : -1; \
1761 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1762 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1766 #define ARM_FRAME_RTX(X) \
1767 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1768 || (X) == arg_pointer_rtx)
1770 #define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
1771 return arm_rtx_costs (X, CODE);
1773 /* Moves to and from memory are quite expensive */
1774 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1776 /* All address computations that can be done are free, but rtx cost returns
1777 the same for practically all of them. So we weight the different types
1778 of address here in the order (most pref first):
1779 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1780 #define ADDRESS_COST(X) \
1781 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1782 || GET_CODE (X) == SYMBOL_REF) \
1784 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1785 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1787 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1788 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1789 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1790 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1791 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1792 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1798 /* Try to generate sequences that don't involve branches, we can then use
1799 conditional instructions */
1800 #define BRANCH_COST 4
1802 /* A C statement to update the variable COST based on the relationship
1803 between INSN that is dependent on DEP through dependence LINK. */
1804 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1805 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1807 /* Position Independent Code. */
1808 /* We decide which register to use based on the compilation options and
1809 the assembler in use; this is more general than the APCS restriction of
1810 using sb (r9) all the time. */
1811 extern int arm_pic_register;
1813 /* The register number of the register used to address a table of static
1814 data addresses in memory. */
1815 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1817 #define FINALIZE_PIC arm_finalize_pic ()
1819 /* We can't directly access anything that contains a symbol,
1820 nor can we indirect via the constant pool. */
1821 #define LEGITIMATE_PIC_OPERAND_P(X) \
1822 (! symbol_mentioned_p (X) \
1823 && (! CONSTANT_POOL_ADDRESS_P (X) \
1824 || ! symbol_mentioned_p (get_pool_constant (X))))
1826 /* We need to know when we are making a constant pool; this determines
1827 whether data needs to be in the GOT or can be referenced via a GOT
1829 extern int making_const_table;
1832 /* Condition code information. */
1833 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1834 return the mode to be used for the comparison.
1835 CCFPEmode should be used with floating inequalities,
1836 CCFPmode should be used with floating equalities.
1837 CC_NOOVmode should be used with SImode integer equalities.
1838 CC_Zmode should be used if only the Z flag is set correctly
1839 CCmode should be used otherwise. */
1841 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1842 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1843 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1844 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1846 #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \
1847 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \
1848 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C"
1850 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1852 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1854 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1857 if (GET_CODE (OP1) == CONST_INT \
1858 && ! (const_ok_for_arm (INTVAL (OP1)) \
1859 || (const_ok_for_arm (- INTVAL (OP1))))) \
1861 rtx const_op = OP1; \
1862 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1867 #define STORE_FLAG_VALUE 1
1869 /* Define the information needed to generate branch insns. This is
1870 stored from the compare operation. Note that we can't use "rtx" here
1871 since it hasn't been defined! */
1873 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1875 /* Define the codes that are matched by predicates in arm.c */
1876 #define PREDICATE_CODES \
1877 {"s_register_operand", {SUBREG, REG}}, \
1878 {"f_register_operand", {SUBREG, REG}}, \
1879 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1880 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1881 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1882 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1883 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1884 {"offsettable_memory_operand", {MEM}}, \
1885 {"bad_signed_byte_operand", {MEM}}, \
1886 {"alignable_memory_operand", {MEM}}, \
1887 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1888 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1889 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1890 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1891 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1892 {"load_multiple_operation", {PARALLEL}}, \
1893 {"store_multiple_operation", {PARALLEL}}, \
1894 {"equality_operator", {EQ, NE}}, \
1895 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1896 {"const_shift_operand", {CONST_INT}}, \
1897 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1898 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1899 {"multi_register_push", {PARALLEL}}, \
1900 {"cc_register", {REG}}, \
1901 {"dominant_cc_register", {REG}},
1905 /* Gcc puts the pool in the wrong place for ARM, since we can only
1906 load addresses a limited distance around the pc. We do some
1907 special munging to move the constant pool values to the correct
1908 point in the code. */
1909 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1911 /* The pool is empty, since we have moved everything into the code. */
1912 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1915 /* Output an internal label definition. */
1916 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1917 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1920 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1921 extern int arm_target_label, arm_ccfsm_state; \
1922 extern rtx arm_target_insn; \
1924 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1925 && !strcmp (PREFIX, "L")) \
1927 arm_ccfsm_state = 0; \
1928 arm_target_insn = NULL; \
1930 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1931 ASM_OUTPUT_LABEL (STREAM, s); \
1935 /* Output a push or a pop instruction (only used when profiling). */
1936 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1937 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1938 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1940 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1941 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1942 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1944 /* Target characters. */
1945 #define TARGET_BELL 007
1946 #define TARGET_BS 010
1947 #define TARGET_TAB 011
1948 #define TARGET_NEWLINE 012
1949 #define TARGET_VT 013
1950 #define TARGET_FF 014
1951 #define TARGET_CR 015
1953 /* Only perform branch elimination (by making instructions conditional) if
1954 we're optimising. Otherwise it's of no use anyway. */
1955 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1957 arm_final_prescan_insn (INSN)
1959 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1960 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1961 /* Output an operand of an instruction. */
1962 #define PRINT_OPERAND(STREAM, X, CODE) \
1963 arm_print_operand (STREAM, X, CODE)
1965 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1966 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1967 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1968 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1969 ? ((~ (HOST_WIDE_INT) 0) \
1970 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1973 /* Output the address of an operand. */
1974 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1976 int is_minus = GET_CODE (X) == MINUS; \
1978 if (GET_CODE (X) == REG) \
1979 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1980 reg_names[REGNO (X)]); \
1981 else if (GET_CODE (X) == PLUS || is_minus) \
1983 rtx base = XEXP (X, 0); \
1984 rtx index = XEXP (X, 1); \
1985 char * base_reg_name; \
1986 HOST_WIDE_INT offset = 0; \
1987 if (GET_CODE (base) != REG) \
1989 /* Ensure that BASE is a register (one of them must be). */ \
1994 base_reg_name = reg_names[REGNO (base)]; \
1995 switch (GET_CODE (index)) \
1998 offset = INTVAL (index); \
2001 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
2002 base_reg_name, offset); \
2006 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
2007 base_reg_name, is_minus ? "-" : "", \
2008 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
2017 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
2018 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
2019 reg_names[REGNO (XEXP (index, 0))]); \
2020 arm_print_operand (STREAM, index, 'S'); \
2021 fputs ("]", STREAM); \
2029 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2030 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2032 extern int output_memory_reference_mode; \
2034 if (GET_CODE (XEXP (X, 0)) != REG) \
2037 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2038 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
2039 reg_names[REGNO (XEXP (X, 0))], \
2040 GET_CODE (X) == PRE_DEC ? "-" : "", \
2041 GET_MODE_SIZE (output_memory_reference_mode)); \
2043 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
2044 reg_names[REGNO (XEXP (X, 0))], \
2045 GET_CODE (X) == POST_DEC ? "-" : "", \
2046 GET_MODE_SIZE (output_memory_reference_mode)); \
2048 else output_addr_const (STREAM, X); \
2051 /* Handles PIC addr specially */
2052 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2054 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2056 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2057 fputs (" - (", STREAM); \
2058 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2059 fputs (")", STREAM); \
2061 else output_addr_const (STREAM, X); \
2063 /* Mark symbols as position independent. We only do this in the \
2064 .text segment, not in the .data segment. */ \
2065 if (NEED_PLT_GOT && flag_pic && making_const_table && \
2066 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2068 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2069 fprintf (STREAM, "(GOTOFF)"); \
2070 else if (GET_CODE (X) == LABEL_REF) \
2071 fprintf (STREAM, "(GOTOFF)"); \
2073 fprintf (STREAM, "(GOT)"); \
2077 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2078 Used for C++ multiple inheritance. */
2079 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2081 int mi_delta = (DELTA); \
2082 char *mi_op = mi_delta < 0 ? "sub" : "add"; \
2084 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))\
2086 if (mi_delta < 0) mi_delta = -mi_delta; \
2087 while (mi_delta != 0) \
2089 if (mi_delta & (3 << shift) == 0) \
2093 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \
2094 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
2095 REGISTER_PREFIX, reg_names[this_regno], \
2096 mi_delta & (0xff << shift)); \
2097 mi_delta &= ~(0xff << shift); \
2101 fputs ("\tb\t", FILE); \
2102 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2104 fputs ("(PLT)", FILE); \
2105 fputc ('\n', FILE); \
2108 /* A C expression whose value is RTL representing the value of the return
2109 address for the frame COUNT steps up from the current frame. */
2111 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2113 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2116 /* Used to mask out junk bits from the return address, such as
2117 processor state, interrupt status, condition codes and the like. */
2118 #define MASK_RETURN_ADDR \
2119 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2120 in 26 bit mode, the condition codes must be masked out of the \
2121 return address. This does not apply to ARM6 and later processors \
2122 when running in 32 bit mode. */ \
2123 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2125 /* The remainder of this file is only needed for building the compiler
2126 itself, not for the collateral. */
2127 #ifdef HAVE_CONFIG_H
2129 /* Prototypes for functions in arm.c */
2131 #ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */
2132 #define STDIO_PROTO(ARGS) PROTO (ARGS)
2134 #define STDIO_PROTO(ARGS) ()
2139 #define Tree union tree_node *
2146 #define Rtx struct rtx_def *
2151 #ifndef HOST_WIDE_INT
2154 #define Hint HOST_WIDE_INT
2156 #ifndef HAVE_MACHINE_MODES
2157 #include "machmode.h"
2159 #define Mmode enum machine_mode
2162 #define RTX_CODE_PROTO(ARGS) PROTO (ARGS)
2164 #define RTX_CODE_PROTO(ARGS) ()
2166 #define Rcode enum rtx_code
2168 void arm_override_options PROTO ((void));
2169 int use_return_insn PROTO ((int));
2170 int const_ok_for_arm PROTO ((Hint));
2171 int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, Hint, Rtx, Rtx, int));
2172 Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
2173 int arm_return_in_memory PROTO ((Tree));
2174 int legitimate_pic_operand_p PROTO ((Rtx));
2175 Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
2176 int is_pic PROTO ((Rtx));
2177 void arm_finalize_pic PROTO ((void));
2178 int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
2179 int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
2180 int const_double_rtx_ok_for_fpu PROTO ((Rtx));
2181 int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx));
2182 int s_register_operand PROTO ((Rtx, Mmode));
2183 int f_register_operand PROTO ((Rtx, Mmode));
2184 int reg_or_int_operand PROTO ((Rtx, Mmode));
2185 int reload_memory_operand PROTO ((Rtx, Mmode));
2186 int arm_rhs_operand PROTO ((Rtx, Mmode));
2187 int arm_rhsm_operand PROTO ((Rtx, Mmode));
2188 int arm_add_operand PROTO ((Rtx, Mmode));
2189 int arm_not_operand PROTO ((Rtx, Mmode));
2190 int offsettable_memory_operand PROTO ((Rtx, Mmode));
2191 int alignable_memory_operand PROTO ((Rtx, Mmode));
2192 int bad_signed_byte_operand PROTO ((Rtx, Mmode));
2193 int fpu_rhs_operand PROTO ((Rtx, Mmode));
2194 int fpu_add_operand PROTO ((Rtx, Mmode));
2195 int power_of_two_operand PROTO ((Rtx, Mmode));
2196 int di_operand PROTO ((Rtx, Mmode));
2197 int soft_df_operand PROTO ((Rtx, Mmode));
2198 int index_operand PROTO ((Rtx, Mmode));
2199 int const_shift_operand PROTO ((Rtx, Mmode));
2200 int shiftable_operator PROTO ((Rtx, Mmode));
2201 int shift_operator PROTO ((Rtx, Mmode));
2202 int equality_operator PROTO ((Rtx, Mmode));
2203 int minmax_operator PROTO ((Rtx, Mmode));
2204 int cc_register PROTO ((Rtx, Mmode));
2205 int dominant_cc_register PROTO ((Rtx, Mmode));
2206 int symbol_mentioned_p PROTO ((Rtx));
2207 int label_mentioned_p PROTO ((Rtx));
2208 Rcode minmax_code PROTO ((Rtx));
2209 int adjacent_mem_locations PROTO ((Rtx, Rtx));
2210 int load_multiple_operation PROTO ((Rtx, Mmode));
2211 int store_multiple_operation PROTO ((Rtx, Mmode));
2212 int load_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
2213 char * emit_ldm_seq PROTO ((Rtx *, int));
2214 int store_multiple_sequence PROTO ((Rtx *, int, int *, int *, Hint *));
2215 char * emit_stm_seq PROTO ((Rtx *, int));
2216 int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
2217 Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2218 Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2219 int arm_gen_movstrqi PROTO ((Rtx *));
2220 Rtx gen_rotated_half_load PROTO ((Rtx));
2221 Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx));
2222 Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int));
2223 void arm_reload_in_hi PROTO ((Rtx *));
2224 void arm_reload_out_hi PROTO ((Rtx *));
2225 void arm_reorg PROTO ((Rtx));
2226 char * fp_immediate_constant PROTO ((Rtx));
2227 void print_multi_reg STDIO_PROTO ((FILE *, char *, int, int));
2228 char * output_call PROTO ((Rtx *));
2229 char * output_call_mem PROTO ((Rtx *));
2230 char * output_mov_long_double_fpu_from_arm PROTO ((Rtx *));
2231 char * output_mov_long_double_arm_from_fpu PROTO ((Rtx *));
2232 char * output_mov_long_double_arm_from_arm PROTO ((Rtx *));
2233 char * output_mov_double_fpu_from_arm PROTO ((Rtx *));
2234 char * output_mov_double_arm_from_fpu PROTO ((Rtx *));
2235 char * output_move_double PROTO ((Rtx *));
2236 char * output_mov_immediate PROTO ((Rtx *));
2237 char * output_add_immediate PROTO ((Rtx *));
2238 char * arithmetic_instr PROTO ((Rtx, int));
2239 void output_ascii_pseudo_op STDIO_PROTO ((FILE *, unsigned char *, int));
2240 char * output_return_instruction PROTO ((Rtx, int, int));
2241 int arm_volatile_func PROTO ((void));
2242 void arm_poke_function_name STDIO_PROTO ((FILE *, char *));
2243 void output_func_prologue STDIO_PROTO ((FILE *, int));
2244 void output_func_epilogue STDIO_PROTO ((FILE *, int));
2245 void arm_expand_prologue PROTO ((void));
2246 void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int));
2247 void arm_final_prescan_insn PROTO ((Rtx));
2248 int short_branch PROTO ((int, int));
2249 void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */
2250 int multi_register_push PROTO ((Rtx, Mmode));
2251 #ifdef AOF_ASSEMBLER
2252 Rtx aof_pic_entry PROTO ((Rtx));
2253 void aof_dump_pic_table STDIO_PROTO ((FILE *));
2254 char * aof_text_section PROTO ((void));
2255 char * aof_data_section PROTO ((void));
2256 void aof_add_import PROTO ((char *));
2257 void aof_delete_import PROTO ((char *));
2258 void aof_dump_imports STDIO_PROTO ((FILE *));
2260 #endif /* HAVE_CONFIG_H */
2262 #endif /* __ARM_H__ */
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