1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify. */
52 #define TARGET_CPU_generic 0x8000
54 typedef enum arm_cond_code
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
61 extern arm_cc arm_current_cc;
62 extern const char * arm_condition_codes[];
64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
66 extern int arm_target_label;
67 extern int arm_ccfsm_state;
68 extern struct rtx_def * arm_target_insn;
69 /* Run-time compilation parameters selecting different hardware subsets. */
70 extern int target_flags;
71 /* The floating point instruction architecture, can be 2 or 3 */
72 extern const char * target_fp_name;
73 /* Define the information needed to generate branch insns. This is
74 stored from the compare operation. Note that we can't use "rtx" here
75 since it hasn't been defined! */
76 extern struct rtx_def * arm_compare_op0;
77 extern struct rtx_def * arm_compare_op1;
78 /* The label of the current constant pool. */
79 extern struct rtx_def * pool_vector_label;
80 /* Set to 1 when a return insn is output, this means that the epilogue
82 extern int return_used_this_function;
83 /* Nonzero if the prologue must setup `fp'. */
84 extern int current_function_anonymous_args;
86 /* Just in case configure has failed to define anything. */
87 #ifndef TARGET_CPU_DEFAULT
88 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
91 /* If the configuration file doesn't specify the cpu, the subtarget may
92 override it. If it doesn't, then default to an ARM6. */
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
94 #undef TARGET_CPU_DEFAULT
96 #ifdef SUBTARGET_CPU_DEFAULT
97 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
99 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
103 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
104 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
106 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
107 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
109 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
110 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
112 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
113 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
115 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
116 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
118 Unrecognized value in TARGET_CPU_DEFAULT.
125 #ifndef CPP_PREDEFINES
126 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
130 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
131 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
133 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
135 /* Set the architecture define -- if -march= is set, then it overrides
136 the -mcpu= setting. */
137 #define CPP_CPU_ARCH_SPEC "\
138 %{march=arm2:-D__ARM_ARCH_2__} \
139 %{march=arm250:-D__ARM_ARCH_2__} \
140 %{march=arm3:-D__ARM_ARCH_2__} \
141 %{march=arm6:-D__ARM_ARCH_3__} \
142 %{march=arm600:-D__ARM_ARCH_3__} \
143 %{march=arm610:-D__ARM_ARCH_3__} \
144 %{march=arm7:-D__ARM_ARCH_3__} \
145 %{march=arm700:-D__ARM_ARCH_3__} \
146 %{march=arm710:-D__ARM_ARCH_3__} \
147 %{march=arm720:-D__ARM_ARCH_3__} \
148 %{march=arm7100:-D__ARM_ARCH_3__} \
149 %{march=arm7500:-D__ARM_ARCH_3__} \
150 %{march=arm7500fe:-D__ARM_ARCH_3__} \
151 %{march=arm7m:-D__ARM_ARCH_3M__} \
152 %{march=arm7dm:-D__ARM_ARCH_3M__} \
153 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
154 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
155 %{march=arm8:-D__ARM_ARCH_4__} \
156 %{march=arm810:-D__ARM_ARCH_4__} \
157 %{march=arm9:-D__ARM_ARCH_4T__} \
158 %{march=arm920:-D__ARM_ARCH_4__} \
159 %{march=arm920t:-D__ARM_ARCH_4T__} \
160 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
161 %{march=strongarm:-D__ARM_ARCH_4__} \
162 %{march=strongarm110:-D__ARM_ARCH_4__} \
163 %{march=strongarm1100:-D__ARM_ARCH_4__} \
164 %{march=armv2:-D__ARM_ARCH_2__} \
165 %{march=armv2a:-D__ARM_ARCH_2__} \
166 %{march=armv3:-D__ARM_ARCH_3__} \
167 %{march=armv3m:-D__ARM_ARCH_3M__} \
168 %{march=armv4:-D__ARM_ARCH_4__} \
169 %{march=armv4t:-D__ARM_ARCH_4T__} \
170 %{march=armv5:-D__ARM_ARCH_5__} \
171 %{march=armv5t:-D__ARM_ARCH_5T__} \
172 %{march=armv5e:-D__ARM_ARCH_5E__} \
173 %{march=armv5te:-D__ARM_ARCH_5TE__} \
175 %{mcpu=arm2:-D__ARM_ARCH_2__} \
176 %{mcpu=arm250:-D__ARM_ARCH_2__} \
177 %{mcpu=arm3:-D__ARM_ARCH_2__} \
178 %{mcpu=arm6:-D__ARM_ARCH_3__} \
179 %{mcpu=arm600:-D__ARM_ARCH_3__} \
180 %{mcpu=arm610:-D__ARM_ARCH_3__} \
181 %{mcpu=arm7:-D__ARM_ARCH_3__} \
182 %{mcpu=arm700:-D__ARM_ARCH_3__} \
183 %{mcpu=arm710:-D__ARM_ARCH_3__} \
184 %{mcpu=arm720:-D__ARM_ARCH_3__} \
185 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
186 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
187 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
188 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
189 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
190 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
191 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
192 %{mcpu=arm8:-D__ARM_ARCH_4__} \
193 %{mcpu=arm810:-D__ARM_ARCH_4__} \
194 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
195 %{mcpu=arm920:-D__ARM_ARCH_4__} \
196 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
197 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
198 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
199 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
200 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
201 %{!mcpu*:%(cpp_cpu_arch_default)}} \
204 /* Define __APCS_26__ if the PC also contains the PSR */
205 #define CPP_APCS_PC_SPEC "\
206 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
208 %{mapcs-26:-D__APCS_26__} \
209 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
212 #ifndef CPP_APCS_PC_DEFAULT_SPEC
213 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
216 #define CPP_FLOAT_SPEC "\
218 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
220 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
223 /* Default is hard float, which doesn't define anything */
224 #define CPP_FLOAT_DEFAULT_SPEC ""
226 #define CPP_ENDIAN_SPEC "\
229 %e-mbig-endian and -mlittle-endian may not be used together} \
230 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
231 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
232 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
235 /* Default is little endian. */
236 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
238 /* Add a define for interworking. Needed when building libgcc.a.
239 This must define __THUMB_INTERWORK__ to the pre-processor if
240 interworking is enabled by default. */
241 #ifndef CPP_INTERWORK_DEFAULT_SPEC
242 #define CPP_INTERWORK_DEFAULT_SPEC ""
245 #define CPP_INTERWORK_SPEC " \
246 %{mthumb-interwork: \
247 %{mno-thumb-interwork: %eIncompatible interworking options} \
248 -D__THUMB_INTERWORK__} \
249 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
254 /* This macro defines names of additional specifications to put in the specs
255 that can be used in various specifications like CC1_SPEC. Its definition
256 is an initializer with a subgrouping for each command option.
258 Each subgrouping contains a string constant, that defines the
259 specification name, and a string constant that used by the GNU CC driver
262 Do not define this macro if it does not need to do anything. */
263 #define EXTRA_SPECS \
264 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
265 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
266 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
267 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
268 { "cpp_float", CPP_FLOAT_SPEC }, \
269 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
270 { "cpp_endian", CPP_ENDIAN_SPEC }, \
271 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
272 { "cpp_isa", CPP_ISA_SPEC }, \
273 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
274 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
275 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
276 SUBTARGET_EXTRA_SPECS
278 #ifndef SUBTARGET_EXTRA_SPECS
279 #define SUBTARGET_EXTRA_SPECS
282 #ifndef SUBTARGET_CPP_SPEC
283 #define SUBTARGET_CPP_SPEC ""
286 /* Run-time Target Specification. */
287 #ifndef TARGET_VERSION
288 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
291 /* Nonzero if the function prologue (and epilogue) should obey
292 the ARM Procedure Call Standard. */
293 #define ARM_FLAG_APCS_FRAME (1 << 0)
295 /* Nonzero if the function prologue should output the function name to enable
296 the post mortem debugger to print a backtrace (very useful on RISCOS,
297 unused on RISCiX). Specifying this flag also enables
298 -fno-omit-frame-pointer.
299 XXX Must still be implemented in the prologue. */
300 #define ARM_FLAG_POKE (1 << 1)
302 /* Nonzero if floating point instructions are emulated by the FPE, in which
303 case instruction scheduling becomes very uninteresting. */
304 #define ARM_FLAG_FPE (1 << 2)
306 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
307 that assume restoration of the condition flags when returning from a
308 branch and link (ie a function). */
309 #define ARM_FLAG_APCS_32 (1 << 3)
311 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
313 /* Nonzero if stack checking should be performed on entry to each function
314 which allocates temporary variables on the stack. */
315 #define ARM_FLAG_APCS_STACK (1 << 4)
317 /* Nonzero if floating point parameters should be passed to functions in
318 floating point registers. */
319 #define ARM_FLAG_APCS_FLOAT (1 << 5)
321 /* Nonzero if re-entrant, position independent code should be generated.
322 This is equivalent to -fpic. */
323 #define ARM_FLAG_APCS_REENT (1 << 6)
325 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
326 be loaded using either LDRH or LDRB instructions. */
327 #define ARM_FLAG_MMU_TRAPS (1 << 7)
329 /* Nonzero if all floating point instructions are missing (and there is no
330 emulator either). Generate function calls for all ops in this case. */
331 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
333 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
334 #define ARM_FLAG_BIG_END (1 << 9)
336 /* Nonzero if we should compile for Thumb interworking. */
337 #define ARM_FLAG_INTERWORK (1 << 10)
339 /* Nonzero if we should have little-endian words even when compiling for
340 big-endian (for backwards compatibility with older versions of GCC). */
341 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
343 /* Nonzero if we need to protect the prolog from scheduling */
344 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
346 /* Nonzero if a call to abort should be generated if a noreturn
347 function tries to return. */
348 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
350 /* Nonzero if function prologues should not load the PIC register. */
351 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
353 /* Nonzero if all call instructions should be indirect. */
354 #define ARM_FLAG_LONG_CALLS (1 << 15)
356 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
357 #define ARM_FLAG_THUMB (1 << 16)
359 /* Set if a TPCS style stack frame should be generated, for non-leaf
360 functions, even if they do not need one. */
361 #define THUMB_FLAG_BACKTRACE (1 << 17)
363 /* Set if a TPCS style stack frame should be generated, for leaf
364 functions, even if they do not need one. */
365 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
367 /* Set if externally visible functions should assume that they
368 might be called in ARM mode, from a non-thumb aware code. */
369 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
371 /* Set if calls via function pointers should assume that their
372 destination is non-Thumb aware. */
373 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
375 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
376 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
377 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
378 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
379 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
380 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
381 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
382 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
383 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
384 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
385 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
386 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
387 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
388 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
389 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
390 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
391 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
392 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
393 #define TARGET_ARM (! TARGET_THUMB)
394 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
395 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
396 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
397 #define TARGET_BACKTRACE (leaf_function_p () \
398 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
399 : (target_flags & THUMB_FLAG_BACKTRACE))
401 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
402 Bit 31 is reserved. See riscix.h. */
403 #ifndef SUBTARGET_SWITCHES
404 #define SUBTARGET_SWITCHES
407 #define TARGET_SWITCHES \
409 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
410 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
411 N_("Generate APCS conformant stack frames") }, \
412 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
413 {"poke-function-name", ARM_FLAG_POKE, \
414 N_("Store function names in object code") }, \
415 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
416 {"fpe", ARM_FLAG_FPE, "" }, \
417 {"apcs-32", ARM_FLAG_APCS_32, \
418 N_("Use the 32bit version of the APCS") }, \
419 {"apcs-26", -ARM_FLAG_APCS_32, \
420 N_("Use the 26bit version of the APCS") }, \
421 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
422 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
423 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
424 N_("Pass FP arguments in FP registers") }, \
425 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
426 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
427 N_("Generate re-entrant, PIC code") }, \
428 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
429 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
430 N_("The MMU will trap on unaligned accesses") }, \
431 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
432 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
433 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
434 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
435 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
436 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
437 N_("Use library calls to perform FP operations") }, \
438 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
439 N_("Use hardware floating point instructions") }, \
440 {"big-endian", ARM_FLAG_BIG_END, \
441 N_("Assume target CPU is configured as big endian") }, \
442 {"little-endian", -ARM_FLAG_BIG_END, \
443 N_("Assume target CPU is configured as little endian") }, \
444 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
445 N_("Assume big endian bytes, little endian words") }, \
446 {"thumb-interwork", ARM_FLAG_INTERWORK, \
447 N_("Support calls between THUMB and ARM instructions sets") }, \
448 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
449 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
450 N_("Generate a call to abort if a noreturn function returns")}, \
451 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
452 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
453 N_("Do not move instructions into a function's prologue") }, \
454 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
455 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
456 N_("Do not load the PIC register in function prologues") }, \
457 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
458 {"long-calls", ARM_FLAG_LONG_CALLS, \
459 N_("Generate call insns as indirect calls, if necessary") }, \
460 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
461 {"thumb", ARM_FLAG_THUMB, \
462 N_("Compile for the Thumb not the ARM") }, \
463 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
464 {"arm", -ARM_FLAG_THUMB, "" }, \
465 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
466 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
467 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
468 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
469 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
470 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
471 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
472 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
473 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
475 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
476 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
477 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
480 {"", TARGET_DEFAULT, "" } \
483 #define TARGET_OPTIONS \
485 {"cpu=", & arm_select[0].string, \
486 N_("Specify the name of the target CPU") }, \
487 {"arch=", & arm_select[1].string, \
488 N_("Specify the name of the target architecture") }, \
489 {"tune=", & arm_select[2].string, "" }, \
490 {"fpe=", & target_fp_name, "" }, \
491 {"fp=", & target_fp_name, \
492 N_("Specify the version of the floating point emulator") }, \
493 {"structure-size-boundary=", & structure_size_string, \
494 N_("Specify the minimum bit alignment of structures") }, \
495 {"pic-register=", & arm_pic_register_string, \
496 N_("Specify the register to be used for PIC addressing") } \
499 struct arm_cpu_select
503 const struct processors * processors;
506 /* This is a magic array. If the user specifies a command line switch
507 which matches one of the entries in TARGET_OPTIONS then the corresponding
508 string pointer will be set to the value specified by the user. */
509 extern struct arm_cpu_select arm_select[];
517 /* Recast the program mode class to be the prog_mode attribute */
518 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
520 extern enum prog_mode_type arm_prgmode;
522 /* What sort of floating point unit do we have? Hardware or software.
523 If software, is it issue 2 or issue 3? */
524 enum floating_point_type
531 /* Recast the floating point class to be the floating point attribute. */
532 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
534 /* What type of floating point to tune for */
535 extern enum floating_point_type arm_fpu;
537 /* What type of floating point instructions are available */
538 extern enum floating_point_type arm_fpu_arch;
540 /* Default floating point architecture. Override in sub-target if
542 #define FP_DEFAULT FP_SOFT2
544 /* Nonzero if the processor has a fast multiply insn, and one that does
545 a 64-bit multiply of two 32-bit values. */
546 extern int arm_fast_multiply;
548 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
549 extern int arm_arch4;
551 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
552 extern int arm_arch5;
554 /* Nonzero if this chip can benefit from load scheduling. */
555 extern int arm_ld_sched;
557 /* Nonzero if generating thumb code. */
558 extern int thumb_code;
560 /* Nonzero if this chip is a StrongARM. */
561 extern int arm_is_strong;
563 /* Nonzero if this chip is a an ARM6 or an ARM7. */
564 extern int arm_is_6_or_7;
566 #ifndef TARGET_DEFAULT
567 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
570 /* The frame pointer register used in gcc has nothing to do with debugging;
571 that is controlled by the APCS-FRAME option. */
572 #define CAN_DEBUG_WITHOUT_FP
574 #define TARGET_MEM_FUNCTIONS 1
576 #define OVERRIDE_OPTIONS arm_override_options ()
578 /* Nonzero if PIC code requires explicit qualifiers to generate
579 PLT and GOT relocs rather than the assembler doing so implicitly.
580 Subtargets can override these if required. */
581 #ifndef NEED_GOT_RELOC
582 #define NEED_GOT_RELOC 0
584 #ifndef NEED_PLT_RELOC
585 #define NEED_PLT_RELOC 0
588 /* Nonzero if we need to refer to the GOT with a PC-relative
589 offset. In other words, generate
591 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
595 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
597 The default is true, which matches NetBSD. Subtargets can
598 override this if required. */
603 /* Target machine storage Layout. */
606 /* Define this macro if it is advisable to hold scalars in registers
607 in a wider mode than that declared by the program. In such cases,
608 the value is constrained to be within the bounds of the declared
609 type, but kept valid in the wider mode. The signedness of the
610 extension may differ from that of the type. */
612 /* It is far faster to zero extend chars than to sign extend them */
614 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
615 if (GET_MODE_CLASS (MODE) == MODE_INT \
616 && GET_MODE_SIZE (MODE) < 4) \
618 if (MODE == QImode) \
620 else if (MODE == HImode) \
621 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
625 /* Define this macro if the promotion described by `PROMOTE_MODE'
626 should also be done for outgoing function arguments. */
627 /* This is required to ensure that push insns always push a word. */
628 #define PROMOTE_FUNCTION_ARGS
630 /* Define for XFmode extended real floating point support.
631 This will automatically cause REAL_ARITHMETIC to be defined. */
633 I think I have added all the code to make this work. Unfortunately,
634 early releases of the floating point emulation code on RISCiX used a
635 different format for extended precision numbers. On my RISCiX box there
636 is a bug somewhere which causes the machine to lock up when running enquire
637 with long doubles. There is the additional aspect that Norcroft C
638 treats long doubles as doubles and we ought to remain compatible.
639 Perhaps someone with an FPA coprocessor and not running RISCiX would like
640 to try this someday. */
641 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
643 /* Disable XFmode patterns in md file */
644 #define ENABLE_XF_PATTERNS 0
646 /* Define if you don't want extended real, but do want to use the
647 software floating point emulator for REAL_ARITHMETIC and
648 decimal <-> binary conversion. */
649 /* See comment above */
650 #define REAL_ARITHMETIC
652 /* Define this if most significant bit is lowest numbered
653 in instructions that operate on numbered bit-fields. */
654 #define BITS_BIG_ENDIAN 0
656 /* Define this if most significant byte of a word is the lowest numbered.
657 Most ARM processors are run in little endian mode, so that is the default.
658 If you want to have it run-time selectable, change the definition in a
659 cover file to be TARGET_BIG_ENDIAN. */
660 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
662 /* Define this if most significant word of a multiword number is the lowest
664 This is always false, even when in big-endian mode. */
665 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
667 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
668 on processor pre-defineds when compiling libgcc2.c. */
669 #if defined(__ARMEB__) && !defined(__ARMWEL__)
670 #define LIBGCC2_WORDS_BIG_ENDIAN 1
672 #define LIBGCC2_WORDS_BIG_ENDIAN 0
675 /* Define this if most significant word of doubles is the lowest numbered.
676 This is always true, even when in little-endian mode. */
677 #define FLOAT_WORDS_BIG_ENDIAN 1
679 /* Number of bits in an addressable storage unit */
680 #define BITS_PER_UNIT 8
682 #define BITS_PER_WORD 32
684 #define UNITS_PER_WORD 4
686 #define POINTER_SIZE 32
688 #define PARM_BOUNDARY 32
690 #define STACK_BOUNDARY 32
692 #define FUNCTION_BOUNDARY 32
694 #define EMPTY_FIELD_BOUNDARY 32
696 #define BIGGEST_ALIGNMENT 32
698 /* Make strings word-aligned so strcpy from constants will be faster. */
699 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
700 (TREE_CODE (EXP) == STRING_CST \
701 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
703 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
704 value set in previous versions of this toolchain was 8, which produces more
705 compact structures. The command line option -mstructure_size_boundary=<n>
706 can be used to change this value. For compatability with the ARM SDK
707 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
708 0020D) page 2-20 says "Structures are aligned on word boundaries". */
709 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
710 extern int arm_structure_size_boundary;
712 /* This is the value used to initialise arm_structure_size_boundary. If a
713 particular arm target wants to change the default value it should change
714 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
715 for an example of this. */
716 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
717 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
720 /* Used when parsing command line option -mstructure_size_boundary. */
721 extern const char * structure_size_string;
723 /* Non-zero if move instructions will actually fail to work
724 when given unaligned data. */
725 #define STRICT_ALIGNMENT 1
727 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
730 /* Standard register usage. */
732 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
733 (S - saved over call).
735 r0 * argument word/integer result
738 r4-r8 S register variable
739 r9 S (rfp) register variable (real frame pointer)
741 r10 F S (sl) stack limit (used by -mapcs-stack-check)
742 r11 F S (fp) argument pointer
743 r12 (ip) temp workspace
744 r13 F S (sp) lower end of current stack frame
745 r14 (lr) link address/workspace
746 r15 F (pc) program counter
748 f0 floating point result
749 f1-f3 floating point scratch
751 f4-f7 S floating point variable
753 cc This is NOT a real register, but is used internally
754 to represent things that use or set the condition
756 sfp This isn't either. It is used during rtl generation
757 since the offset between the frame pointer and the
758 auto's isn't known until after register allocation.
759 afp Nor this, we only need this because of non-local
760 goto. Without it fp appears to be used and the
761 elimination code won't get rid of sfp. It tracks
762 fp exactly at all times.
764 *: See CONDITIONAL_REGISTER_USAGE */
766 /* The stack backtrace structure is as follows:
767 fp points to here: | save code pointer | [fp]
768 | return link value | [fp, #-4]
769 | return sp value | [fp, #-8]
770 | return fp value | [fp, #-12]
771 [| saved r10 value |]
782 [| saved f7 value |] three words
783 [| saved f6 value |] three words
784 [| saved f5 value |] three words
785 [| saved f4 value |] three words
786 r0-r3 are not normally saved in a C function. */
788 /* 1 for registers that have pervasive standard uses
789 and are not available for the register allocator. */
790 #define FIXED_REGISTERS \
798 /* 1 for registers not available across function calls.
799 These must include the FIXED_REGISTERS and also any
800 registers that can be used without being saved.
801 The latter must include the registers where values are returned
802 and the register where structure-value addresses are passed.
803 Aside from that, you can include as many other registers as you like.
804 The CC is not preserved over function calls on the ARM 6, so it is
805 easier to assume this for all. SFP is preserved, since FP is. */
806 #define CALL_USED_REGISTERS \
814 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
815 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
818 #define CONDITIONAL_REGISTER_USAGE \
820 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
823 for (regno = FIRST_ARM_FP_REGNUM; \
824 regno <= LAST_ARM_FP_REGNUM; ++regno) \
825 fixed_regs[regno] = call_used_regs[regno] = 1; \
829 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
830 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
832 else if (TARGET_APCS_STACK) \
834 fixed_regs[10] = 1; \
835 call_used_regs[10] = 1; \
837 if (TARGET_APCS_FRAME) \
839 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
840 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
842 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
845 /* These are a couple of extensions to the formats accecpted
847 %@ prints out ASM_COMMENT_START
848 %r prints out REGISTER_PREFIX reg_names[arg] */
849 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
851 fputs (ASM_COMMENT_START, FILE); \
855 fputs (REGISTER_PREFIX, FILE); \
856 fputs (reg_names [va_arg (ARGS, int)], FILE); \
859 /* Round X up to the nearest word. */
860 #define ROUND_UP(X) (((X) + 3) & ~3)
862 /* Convert fron bytes to ints. */
863 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
865 /* The number of (integer) registers required to hold a quantity of type MODE. */
866 #define NUM_REGS(MODE) \
867 NUM_INTS (GET_MODE_SIZE (MODE))
869 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
870 #define NUM_REGS2(MODE, TYPE) \
871 NUM_INTS ((MODE) == BLKmode ? \
872 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
874 /* The number of (integer) argument register available. */
875 #define NUM_ARG_REGS 4
877 /* Return the regiser number of the N'th (integer) argument. */
878 #define ARG_REGISTER(N) (N - 1)
880 /* RTX for structure returns. NULL means use a hidden first argument. */
881 #define STRUCT_VALUE 0
883 /* Specify the registers used for certain standard purposes.
884 The values of these macros are register numbers. */
886 /* The number of the last argument register. */
887 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
889 /* The number of the last "lo" register (thumb). */
890 #define LAST_LO_REGNUM 7
892 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
893 as an invisible last argument (possible since varargs don't exist in
894 Pascal), so the following is not true. */
895 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
897 /* Define this to be where the real frame pointer is if it is not possible to
898 work out the offset between the frame pointer and the automatic variables
899 until after register allocation has taken place. FRAME_POINTER_REGNUM
900 should point to a special register that we will make sure is eliminated.
902 For the Thumb we have another problem. The TPCS defines the frame pointer
903 as r11, and GCC belives that it is always possible to use the frame pointer
904 as base register for addressing purposes. (See comments in
905 find_reloads_address()). But - the Thumb does not allow high registers,
906 including r11, to be used as base address registers. Hence our problem.
908 The solution used here, and in the old thumb port is to use r7 instead of
909 r11 as the hard frame pointer and to have special code to generate
910 backtrace structures on the stack (if required to do so via a command line
911 option) using r11. This is the only 'user visable' use of r11 as a frame
913 #define ARM_HARD_FRAME_POINTER_REGNUM 11
914 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
915 #define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
916 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
918 /* Scratch register - used in all kinds of places, eg trampolines. */
921 /* Register to use for pushing function arguments. */
922 #define STACK_POINTER_REGNUM 13
923 #define SP_REGNUM STACK_POINTER_REGNUM
925 /* Register which holds return address from a subroutine call. */
928 /* Define this if the program counter is overloaded on a register. */
931 /* The number of the last ARM (integer) register. */
932 #define LAST_ARM_REGNUM 15
934 /* ARM floating pointer registers. */
935 #define FIRST_ARM_FP_REGNUM 16
936 #define LAST_ARM_FP_REGNUM 23
938 /* Internal, so that we don't need to refer to a raw number */
941 /* Base register for access to local variables of the function. */
942 #define FRAME_POINTER_REGNUM 25
944 /* Base register for access to arguments of the function. */
945 #define ARG_POINTER_REGNUM 26
947 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
948 #define FIRST_PSEUDO_REGISTER 27
950 /* Value should be nonzero if functions must have frame pointers.
951 Zero means the frame pointer need not be set up (and parms may be accessed
952 via the stack pointer) in functions that seem suitable.
953 If we have to have a frame pointer we might as well make use of it.
954 APCS says that the frame pointer does not need to be pushed in leaf
955 functions, or simple tail call functions. */
956 #define FRAME_POINTER_REQUIRED \
957 (current_function_has_nonlocal_label \
958 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
960 /* Return number of consecutive hard regs needed starting at reg REGNO
961 to hold something of mode MODE.
962 This is ordinarily the length in words of a value of mode MODE
963 but can be less for certain modes in special long registers.
965 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
967 #define HARD_REGNO_NREGS(REGNO, MODE) \
969 && REGNO >= FIRST_ARM_FP_REGNUM \
970 && REGNO != FRAME_POINTER_REGNUM \
971 && REGNO != ARG_POINTER_REGNUM) \
972 ? 1 : NUM_REGS (MODE))
974 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
975 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
977 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
978 so that there is always a second lo register available to hold the upper
979 part of the value. Probably we ought to ensure that the register is the
980 start of an even numbered register pair. */
981 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
983 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
984 ( REGNO <= LAST_ARM_REGNUM \
985 || REGNO == FRAME_POINTER_REGNUM \
986 || REGNO == ARG_POINTER_REGNUM \
987 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
989 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
990 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
992 /* Value is 1 if it is a good idea to tie two pseudo registers
993 when one has mode MODE1 and one has mode MODE2.
994 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
995 for any hard reg, then this must be 0 for correct output. */
996 #define MODES_TIEABLE_P(MODE1, MODE2) \
997 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
999 /* The order in which register should be allocated. It is good to use ip
1000 since no saving is required (though calls clobber it) and it never contains
1001 function parameters. It is quite good to use lr since other calls may
1002 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1003 least likely to contain a function parameter; in addition results are
1005 #define REG_ALLOC_ORDER \
1007 3, 2, 1, 0, 12, 14, 4, 5, \
1008 6, 7, 8, 10, 9, 11, 13, 15, \
1009 16, 17, 18, 19, 20, 21, 22, 23, \
1013 /* Register and constant classes. */
1015 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1016 Now that the Thumb is involved it has become more compilcated. */
1031 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1033 /* Give names of register classes as strings for dump file. */
1034 #define REG_CLASS_NAMES \
1047 /* Define which registers fit in which classes.
1048 This is an initializer for a vector of HARD_REG_SET
1049 of length N_REG_CLASSES. */
1050 #define REG_CLASS_CONTENTS \
1052 { 0x0000000 }, /* NO_REGS */ \
1053 { 0x0FF0000 }, /* FPU_REGS */ \
1054 { 0x00000FF }, /* LO_REGS */ \
1055 { 0x0002000 }, /* STACK_REG */ \
1056 { 0x00020FF }, /* BASE_REGS */ \
1057 { 0x000FF00 }, /* HI_REGS */ \
1058 { 0x1000000 }, /* CC_REG */ \
1059 { 0x200FFFF }, /* GENERAL_REGS */ \
1060 { 0x2FFFFFF } /* ALL_REGS */ \
1063 /* The same information, inverted:
1064 Return the class number of the smallest class containing
1065 reg number REGNO. This could be a conditional expression
1066 or could index an array. */
1067 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1069 /* The class value for index registers, and the one for base regs. */
1070 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1071 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1073 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1074 registers explicitly used in the rtl to be used as spill registers
1075 but prevents the compiler from extending the lifetime of these
1077 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1079 /* Get reg_class from a letter such as appears in the machine description.
1080 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1081 ARM, but several more letters for the Thumb. */
1082 #define REG_CLASS_FROM_LETTER(C) \
1083 ( (C) == 'f' ? FPU_REGS \
1084 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1085 : TARGET_ARM ? NO_REGS \
1086 : (C) == 'h' ? HI_REGS \
1087 : (C) == 'b' ? BASE_REGS \
1088 : (C) == 'k' ? STACK_REG \
1089 : (C) == 'c' ? CC_REG \
1092 /* The letters I, J, K, L and M in a register constraint string
1093 can be used to stand for particular ranges of immediate operands.
1094 This macro defines what the ranges are.
1095 C is the letter, and VALUE is a constant value.
1096 Return 1 if VALUE is in the range specified by C.
1097 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1098 J: valid indexing constants.
1099 K: ~value ok in rhs argument of data operand.
1100 L: -value ok in rhs argument of data operand.
1101 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1102 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1103 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1104 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1105 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1106 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1107 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1108 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1111 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1112 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1113 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1114 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1115 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1116 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1117 && ((VAL) & 3) == 0) : \
1118 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1119 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1122 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1124 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1126 /* Constant letter 'G' for the FPU immediate constants.
1127 'H' means the same constant negated. */
1128 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1129 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1130 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1132 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1134 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1136 /* For the ARM, `Q' means that this is a memory operand that is just
1137 an offset from a register.
1138 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1139 address. This means that the symbol is in the text segment and can be
1140 accessed without using a load. */
1142 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1143 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1144 (C) == 'R' ? (GET_CODE (OP) == MEM \
1145 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1146 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1147 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1150 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1151 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1152 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1154 #define EXTRA_CONSTRAINT(X, C) \
1156 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1158 /* Given an rtx X being reloaded into a reg required to be
1159 in class CLASS, return the class of reg to actually use.
1160 In general this is just CLASS, but for the Thumb we prefer
1161 a LO_REGS class or a subset. */
1162 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1163 (TARGET_ARM ? (CLASS) : \
1164 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1166 /* Must leave BASE_REGS reloads alone */
1167 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1168 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1169 ? ((true_regnum (X) == -1 ? LO_REGS \
1170 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1174 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1175 ((CLASS) != LO_REGS \
1176 ? ((true_regnum (X) == -1 ? LO_REGS \
1177 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1181 /* Return the register class of a scratch register needed to copy IN into
1182 or out of a register in CLASS in MODE. If it can be done directly,
1183 NO_REGS is returned. */
1184 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1186 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1187 ? GENERAL_REGS : NO_REGS) \
1188 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1190 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1191 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1193 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1194 && (GET_CODE (X) == MEM \
1195 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1196 && true_regnum (X) == -1))) \
1197 ? GENERAL_REGS : NO_REGS) \
1198 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1200 /* Try a machine-dependent way of reloading an illegitimate address
1201 operand. If we find one, push the reload and jump to WIN. This
1202 macro is used in only one place: `find_reloads_address' in reload.c.
1204 For the ARM, we wish to handle large displacements off a base
1205 register by splitting the addend across a MOV and the mem insn.
1206 This can cut the number of reloads needed. */
1207 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1210 if (GET_CODE (X) == PLUS \
1211 && GET_CODE (XEXP (X, 0)) == REG \
1212 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1213 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1214 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1216 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1217 HOST_WIDE_INT low, high; \
1219 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1220 low = ((val & 0xf) ^ 0x8) - 0x8; \
1221 else if (MODE == SImode \
1222 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1223 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1224 /* Need to be careful, -4096 is not a valid offset. */ \
1225 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1226 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1227 /* Need to be careful, -256 is not a valid offset. */ \
1228 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1229 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1230 && TARGET_HARD_FLOAT) \
1231 /* Need to be careful, -1024 is not a valid offset. */ \
1232 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1236 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1237 ^ HOST_UINT (0x80000000)) \
1238 - HOST_UINT (0x80000000)); \
1239 /* Check for overflow or zero */ \
1240 if (low == 0 || high == 0 || (high + low != val)) \
1243 /* Reload the high part into a base reg; leave the low part \
1245 X = gen_rtx_PLUS (GET_MODE (X), \
1246 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1249 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1250 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1257 /* ??? If an HImode FP+large_offset address is converted to an HImode
1258 SP+large_offset address, then reload won't know how to fix it. It sees
1259 only that SP isn't valid for HImode, and so reloads the SP into an index
1260 register, but the resulting address is still invalid because the offset
1261 is too big. We fix it here instead by reloading the entire address. */
1262 /* We could probably achieve better results by defining PROMOTE_MODE to help
1263 cope with the variances between the Thumb's signed and unsigned byte and
1264 halfword load instructions. */
1265 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1267 if (GET_CODE (X) == PLUS \
1268 && GET_MODE_SIZE (MODE) < 4 \
1269 && GET_CODE (XEXP (X, 0)) == REG \
1270 && XEXP (X, 0) == stack_pointer_rtx \
1271 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1272 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1276 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1278 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1283 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1285 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1287 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1289 /* Return the maximum number of consecutive registers
1290 needed to represent mode MODE in a register of class CLASS.
1291 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1292 #define CLASS_MAX_NREGS(CLASS, MODE) \
1293 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1295 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1296 #define REGISTER_MOVE_COST(FROM, TO) \
1298 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1299 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1301 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1303 /* Stack layout; function entry, exit and calling. */
1305 /* Define this if pushing a word on the stack
1306 makes the stack pointer a smaller address. */
1307 #define STACK_GROWS_DOWNWARD 1
1309 /* Define this if the nominal address of the stack frame
1310 is at the high-address end of the local variables;
1311 that is, each additional local variable allocated
1312 goes at a more negative offset in the frame. */
1313 #define FRAME_GROWS_DOWNWARD 1
1315 /* Offset within stack frame to start allocating local variables at.
1316 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1317 first local allocated. Otherwise, it is the offset to the BEGINNING
1318 of the first local allocated. */
1319 #define STARTING_FRAME_OFFSET 0
1321 /* If we generate an insn to push BYTES bytes,
1322 this says how many the stack pointer really advances by. */
1323 /* The push insns do not do this rounding implicitly.
1324 So don't define this. */
1325 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1327 /* Define this if the maximum size of all the outgoing args is to be
1328 accumulated and pushed during the prologue. The amount can be
1329 found in the variable current_function_outgoing_args_size. */
1330 #define ACCUMULATE_OUTGOING_ARGS 1
1332 /* Offset of first parameter from the argument pointer register value. */
1333 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1335 /* Value is the number of byte of arguments automatically
1336 popped when returning from a subroutine call.
1337 FUNDECL is the declaration node of the function (as a tree),
1338 FUNTYPE is the data type of the function (as a tree),
1339 or for a library call it is an identifier node for the subroutine name.
1340 SIZE is the number of bytes of arguments passed on the stack.
1342 On the ARM, the caller does not pop any of its arguments that were passed
1344 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1346 /* Define how to find the value returned by a library function
1347 assuming the value has mode MODE. */
1348 #define LIBCALL_VALUE(MODE) \
1349 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1350 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1351 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1353 /* Define how to find the value returned by a function.
1354 VALTYPE is the data type of the value (as a tree).
1355 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1356 otherwise, FUNC is 0. */
1357 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1358 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1360 /* 1 if N is a possible register number for a function value.
1361 On the ARM, only r0 and f0 can return results. */
1362 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1363 ((REGNO) == ARG_REGISTER (1) \
1364 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1366 /* How large values are returned */
1367 /* A C expression which can inhibit the returning of certain function values
1368 in registers, based on the type of value. */
1369 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1371 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1372 values must be in memory. On the ARM, they need only do so if larger
1373 than a word, or if they contain elements offset from zero in the struct. */
1374 #define DEFAULT_PCC_STRUCT_RETURN 0
1376 /* Flags for the call/call_value rtl operations set up by function_arg. */
1377 #define CALL_NORMAL 0x00000000 /* No special processing. */
1378 #define CALL_LONG 0x00000001 /* Always call indirect. */
1379 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1381 /* A C structure for machine-specific, per-function data. This is added
1382 to the cfun structure. */
1383 struct machine_function
1385 /* Records __builtin_return address. */
1386 struct rtx_def *ra_rtx;
1387 /* Additionsl stack adjustment in __builtin_eh_throw. */
1388 struct rtx_def *eh_epilogue_sp_ofs;
1389 /* Records if LR has to be saved for far jumps. */
1391 /* Records if ARG_POINTER was ever live. */
1392 int arg_pointer_live;
1395 /* A C type for declaring a variable that is used as the first argument of
1396 `FUNCTION_ARG' and other related values. For some target machines, the
1397 type `int' suffices and can hold the number of bytes of argument so far. */
1400 /* This is the number of registers of arguments scanned so far. */
1402 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1406 /* Define where to put the arguments to a function.
1407 Value is zero to push the argument on the stack,
1408 or a hard register in which to store the argument.
1410 MODE is the argument's machine mode.
1411 TYPE is the data type of the argument (as a tree).
1412 This is null for libcalls where that information may
1414 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1415 the preceding args and about the function being called.
1416 NAMED is nonzero if this argument is a named parameter
1417 (otherwise it is an extra parameter matching an ellipsis).
1419 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1420 other arguments are passed on the stack. If (NAMED == 0) (which happens
1421 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1422 passed in the stack (function_prologue will indeed make it pass in the
1423 stack if necessary). */
1424 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1425 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1427 /* For an arg passed partly in registers and partly in memory,
1428 this is the number of registers used.
1429 For args passed entirely in registers or entirely in memory, zero. */
1430 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1431 ( NUM_ARG_REGS > (CUM).nregs \
1432 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1433 ? NUM_ARG_REGS - (CUM).nregs : 0)
1435 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1436 for a call to a function whose data type is FNTYPE.
1437 For a library call, FNTYPE is 0.
1438 On the ARM, the offset starts at 0. */
1439 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1440 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1442 /* Update the data in CUM to advance over an argument
1443 of mode MODE and data type TYPE.
1444 (TYPE is null for libcalls where that information may not be available.) */
1445 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1446 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1448 /* 1 if N is a possible register number for function argument passing.
1449 On the ARM, r0-r3 are used to pass args. */
1450 #define FUNCTION_ARG_REGNO_P(REGNO) \
1451 ((REGNO) >= 0 && (REGNO) <= 3)
1456 /* A C expression that evaluates to true if it is ok to perform a sibling
1458 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1460 /* Perform any actions needed for a function that is receiving a variable
1461 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1462 of the current parameter. PRETEND_SIZE is a variable that should be set to
1463 the amount of stack that must be pushed by the prolog to pretend that our
1466 Normally, this macro will push all remaining incoming registers on the
1467 stack and set PRETEND_SIZE to the length of the registers pushed.
1469 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1470 named arg and all anonymous args onto the stack.
1471 XXX I know the prologue shouldn't be pushing registers, but it is faster
1473 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1475 extern int current_function_anonymous_args; \
1476 current_function_anonymous_args = 1; \
1477 if ((CUM).nregs < NUM_ARG_REGS) \
1478 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1481 /* Generate assembly output for the start of a function. */
1482 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1486 output_arm_prologue (STREAM, SIZE); \
1488 output_thumb_prologue (STREAM); \
1492 /* If your target environment doesn't prefix user functions with an
1493 underscore, you may wish to re-define this to prevent any conflicts.
1494 e.g. AOF may prefix mcount with an underscore. */
1495 #ifndef ARM_MCOUNT_NAME
1496 #define ARM_MCOUNT_NAME "*mcount"
1499 /* Call the function profiler with a given profile label. The Acorn
1500 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1501 On the ARM the full profile code will look like:
1510 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1511 will output the .text section.
1513 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1514 ``prof'' doesn't seem to mind about this! */
1515 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1520 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1521 IP_REGNUM, LR_REGNUM); \
1522 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1523 fputc ('\n', STREAM); \
1524 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1525 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1526 ASM_OUTPUT_INT (STREAM, sym); \
1529 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1531 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1532 fprintf (STREAM, "\tbl\tmcount\n"); \
1533 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1536 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1538 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1540 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1542 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1543 the stack pointer does not matter. The value is tested only in
1544 functions that have frame pointers.
1545 No definition is equivalent to always zero.
1547 On the ARM, the function epilogue recovers the stack pointer from the
1549 #define EXIT_IGNORE_STACK 1
1551 /* Generate the assembly code for function exit. */
1552 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1553 output_func_epilogue (SIZE)
1555 /* Determine if the epilogue should be output as RTL.
1556 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1557 #define USE_RETURN_INSN(ISCOND) \
1558 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1560 /* Definitions for register eliminations.
1562 This is an array of structures. Each structure initializes one pair
1563 of eliminable registers. The "from" register number is given first,
1564 followed by "to". Eliminations of the same "from" register are listed
1565 in order of preference.
1567 We have two registers that can be eliminated on the ARM. First, the
1568 arg pointer register can often be eliminated in favor of the stack
1569 pointer register. Secondly, the pseudo frame pointer register can always
1570 be eliminated; it is replaced with either the stack or the real frame
1571 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1572 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1574 #define ELIMINABLE_REGS \
1575 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1576 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1577 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1578 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1579 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1580 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1581 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1583 /* Given FROM and TO register numbers, say whether this elimination is
1584 allowed. Frame pointer elimination is automatically handled.
1586 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1587 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1588 pointer, we must eliminate FRAME_POINTER_REGNUM into
1589 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1590 ARG_POINTER_REGNUM. */
1591 #define CAN_ELIMINATE(FROM, TO) \
1592 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1593 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1594 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1595 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1598 /* Define the offset between two registers, one to be eliminated, and the
1599 other its replacement, at the start of a routine. */
1600 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1602 int volatile_func = arm_volatile_func (); \
1603 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1605 if (! current_function_needs_context || ! frame_pointer_needed) \
1610 else if ((FROM) == FRAME_POINTER_REGNUM \
1611 && (TO) == STACK_POINTER_REGNUM) \
1612 (OFFSET) = current_function_outgoing_args_size \
1613 + ROUND_UP (get_frame_size ()); \
1618 int saved_hard_reg = 0; \
1620 if (! volatile_func) \
1622 for (regno = 0; regno <= 10; regno++) \
1623 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1624 saved_hard_reg = 1, offset += 4; \
1625 if (! TARGET_APCS_FRAME \
1626 && ! frame_pointer_needed \
1627 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1628 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1629 saved_hard_reg = 1, offset += 4; \
1630 /* PIC register is a fixed reg, so call_used_regs set. */ \
1631 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1632 saved_hard_reg = 1, offset += 4; \
1633 for (regno = FIRST_ARM_FP_REGNUM; \
1634 regno <= LAST_ARM_FP_REGNUM; regno++) \
1635 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1638 if ((FROM) == FRAME_POINTER_REGNUM) \
1639 (OFFSET) = - offset; \
1642 if (! frame_pointer_needed) \
1644 if (! volatile_func \
1645 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1647 offset += current_function_outgoing_args_size; \
1648 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1653 /* Note: This macro must match the code in thumb_function_prologue(). */
1654 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1657 if ((FROM) == ARG_POINTER_REGNUM) \
1659 int count_regs = 0; \
1661 for (regno = 8; regno < 13; regno ++) \
1662 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1665 (OFFSET) += 4 * count_regs; \
1667 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1668 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1670 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1671 (OFFSET) += 4 * (count_regs + 1); \
1672 if (TARGET_BACKTRACE) \
1674 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1680 if ((TO) == STACK_POINTER_REGNUM) \
1682 (OFFSET) += current_function_outgoing_args_size; \
1683 (OFFSET) += ROUND_UP (get_frame_size ()); \
1687 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1689 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1691 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1693 /* Special case handling of the location of arguments passed on the stack. */
1694 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1696 /* Initialize data used by insn expanders. This is called from insn_emit,
1697 once for every function before code is generated. */
1698 #define INIT_EXPANDERS arm_init_expanders ()
1700 /* Output assembler code for a block containing the constant parts
1701 of a trampoline, leaving space for the variable parts.
1703 On the ARM, (if r8 is the static chain regnum, and remembering that
1704 referencing pc adds an offset of 8) the trampoline looks like:
1707 .word static chain value
1708 .word function's address
1709 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1710 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1712 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1713 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1714 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1715 PC_REGNUM, PC_REGNUM); \
1716 ASM_OUTPUT_INT (FILE, const0_rtx); \
1717 ASM_OUTPUT_INT (FILE, const0_rtx); \
1720 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1721 Why - because it is easier. This code will always be branched to via
1722 a BX instruction and since the compiler magically generates the address
1723 of the function the linker has no opportunity to ensure that the
1724 bottom bit is set. Thus the processor will be in ARM mode when it
1725 reaches this code. So we duplicate the ARM trampoline code and add
1726 a switch into Thumb mode as well. */
1727 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1729 fprintf (FILE, "\t.code 32\n"); \
1730 fprintf (FILE, ".Ltrampoline_start:\n"); \
1731 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1732 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1733 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1734 IP_REGNUM, PC_REGNUM); \
1735 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1736 IP_REGNUM, IP_REGNUM); \
1737 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1738 fprintf (FILE, "\t.word\t0\n"); \
1739 fprintf (FILE, "\t.word\t0\n"); \
1740 fprintf (FILE, "\t.code 16\n"); \
1743 #define TRAMPOLINE_TEMPLATE(FILE) \
1745 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1747 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1749 /* Length in units of the trampoline for entering a nested function. */
1750 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1752 /* Alignment required for a trampoline in units. */
1753 #define TRAMPOLINE_ALIGN 4
1755 /* Emit RTL insns to initialize the variable parts of a trampoline.
1756 FNADDR is an RTX for the address of the function's pure code.
1757 CXT is an RTX for the static chain value for the function. */
1758 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1761 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1763 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1767 /* Addressing modes, and classification of registers for them. */
1768 #define HAVE_POST_INCREMENT 1
1769 #define HAVE_PRE_INCREMENT TARGET_ARM
1770 #define HAVE_POST_DECREMENT TARGET_ARM
1771 #define HAVE_PRE_DECREMENT TARGET_ARM
1773 /* Macros to check register numbers against specific register classes. */
1775 /* These assume that REGNO is a hard or pseudo reg number.
1776 They give nonzero only if REGNO is a hard reg of the suitable class
1777 or a pseudo reg currently allocated to a suitable hard reg.
1778 Since they use reg_renumber, they are safe only once reg_renumber
1779 has been allocated, which happens in local-alloc.c. */
1780 #define TEST_REGNO(R, TEST, VALUE) \
1781 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1783 /* On the ARM, don't allow the pc to be used. */
1784 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1785 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1786 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1787 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1789 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1790 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1791 || (GET_MODE_SIZE (MODE) >= 4 \
1792 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1794 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1796 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1797 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1799 /* For ARM code, we don't care about the mode, but for Thumb, the index
1800 must be suitable for use in a QImode load. */
1801 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1802 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1804 /* Maximum number of registers that can appear in a valid memory address.
1805 Shifts in addresses can't be by a register. */
1806 #define MAX_REGS_PER_ADDRESS 2
1808 /* Recognize any constant value that is a valid address. */
1809 /* XXX We can address any constant, eventually... */
1811 #ifdef AOF_ASSEMBLER
1813 #define CONSTANT_ADDRESS_P(X) \
1814 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1818 #define CONSTANT_ADDRESS_P(X) \
1819 (GET_CODE (X) == SYMBOL_REF \
1820 && (CONSTANT_POOL_ADDRESS_P (X) \
1821 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1823 #endif /* AOF_ASSEMBLER */
1825 /* Nonzero if the constant value X is a legitimate general operand.
1826 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1828 On the ARM, allow any integer (invalid ones are removed later by insn
1829 patterns), nice doubles and symbol_refs which refer to the function's
1832 When generating pic allow anything. */
1833 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1835 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1836 ( GET_CODE (X) == CONST_INT \
1837 || GET_CODE (X) == CONST_DOUBLE \
1838 || CONSTANT_ADDRESS_P (X))
1840 #define LEGITIMATE_CONSTANT_P(X) \
1841 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1843 /* Special characters prefixed to function names
1844 in order to encode attribute like information.
1845 Note, '@' and '*' have already been taken. */
1846 #define SHORT_CALL_FLAG_CHAR '^'
1847 #define LONG_CALL_FLAG_CHAR '#'
1849 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1850 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1852 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1853 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1855 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1856 #define SUBTARGET_NAME_ENCODING_LENGTHS
1859 /* This is a C fragement for the inside of a switch statement.
1860 Each case label should return the number of characters to
1861 be stripped from the start of a function's name, if that
1862 name starts with the indicated character. */
1863 #define ARM_NAME_ENCODING_LENGTHS \
1864 case SHORT_CALL_FLAG_CHAR: return 1; \
1865 case LONG_CALL_FLAG_CHAR: return 1; \
1866 case '*': return 1; \
1867 SUBTARGET_NAME_ENCODING_LENGTHS
1869 /* This has to be handled by a function because more than part of the
1870 ARM backend uses function name prefixes to encode attributes. */
1871 #undef STRIP_NAME_ENCODING
1872 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1873 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1875 /* This is how to output a reference to a user-level label named NAME.
1876 `assemble_name' uses this. */
1877 #undef ASM_OUTPUT_LABELREF
1878 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1879 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1881 /* If we are referencing a function that is weak then encode a long call
1882 flag in the function name, otherwise if the function is static or
1883 or known to be defined in this file then encode a short call flag.
1884 This macro is used inside the ENCODE_SECTION macro. */
1885 #define ARM_ENCODE_CALL_TYPE(decl) \
1886 if (TREE_CODE (decl) == FUNCTION_DECL) \
1888 if (DECL_WEAK (decl)) \
1889 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1890 else if (! TREE_PUBLIC (decl)) \
1891 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1894 /* Symbols in the text segment can be accessed without indirecting via the
1895 constant pool; it may take an extra binary operation, but this is still
1896 faster than indirecting via memory. Don't do this when not optimizing,
1897 since we won't be calculating al of the offsets necessary to do this
1899 /* This doesn't work with AOF syntax, since the string table may be in
1900 a different AREA. */
1901 #ifndef AOF_ASSEMBLER
1902 #define ENCODE_SECTION_INFO(decl) \
1904 if (optimize > 0 && TREE_CONSTANT (decl) \
1905 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1907 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1908 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1909 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1911 ARM_ENCODE_CALL_TYPE (decl) \
1914 #define ENCODE_SECTION_INFO(decl) \
1916 ARM_ENCODE_CALL_TYPE (decl) \
1920 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1921 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1923 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1924 and check its validity for a certain class.
1925 We have two alternate definitions for each of them.
1926 The usual definition accepts all pseudo regs; the other rejects
1927 them unless they have been allocated suitable hard regs.
1928 The symbol REG_OK_STRICT causes the latter definition to be used. */
1929 #ifndef REG_OK_STRICT
1931 #define ARM_REG_OK_FOR_BASE_P(X) \
1932 (REGNO (X) <= LAST_ARM_REGNUM \
1933 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1934 || REGNO (X) == FRAME_POINTER_REGNUM \
1935 || REGNO (X) == ARG_POINTER_REGNUM)
1937 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1938 (REGNO (X) <= LAST_LO_REGNUM \
1939 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1940 || (GET_MODE_SIZE (MODE) >= 4 \
1941 && (REGNO (X) == STACK_POINTER_REGNUM \
1942 || (X) == hard_frame_pointer_rtx \
1943 || (X) == arg_pointer_rtx)))
1945 #else /* REG_OK_STRICT */
1947 #define ARM_REG_OK_FOR_BASE_P(X) \
1948 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1950 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1951 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1953 #endif /* REG_OK_STRICT */
1955 /* Now define some helpers in terms of the above. */
1957 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1959 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1960 : ARM_REG_OK_FOR_BASE_P (X))
1962 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1964 /* For Thumb, a valid index register is anything that can be used in
1965 a byte load instruction. */
1966 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1968 /* Nonzero if X is a hard reg that can be used as an index
1969 or if it is a pseudo reg. On the Thumb, the stack pointer
1971 #define REG_OK_FOR_INDEX_P(X) \
1973 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1974 : ARM_REG_OK_FOR_INDEX_P (X))
1977 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1978 that is a valid memory address for an instruction.
1979 The MODE argument is the machine mode for the MEM expression
1980 that wants to use this address.
1982 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1984 /* --------------------------------arm version----------------------------- */
1985 #define ARM_BASE_REGISTER_RTX_P(X) \
1986 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1988 #define ARM_INDEX_REGISTER_RTX_P(X) \
1989 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1991 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1992 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1993 only be small constants. */
1994 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1997 HOST_WIDE_INT range; \
1998 enum rtx_code code = GET_CODE (INDEX); \
2000 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2002 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2003 && INTVAL (INDEX) > -1024 \
2004 && (INTVAL (INDEX) & 3) == 0) \
2009 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2010 && GET_MODE_SIZE (MODE) <= 4) \
2012 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2013 && (! arm_arch4 || (MODE) != HImode)) \
2015 rtx xiop0 = XEXP (INDEX, 0); \
2016 rtx xiop1 = XEXP (INDEX, 1); \
2017 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2018 && power_of_two_operand (xiop1, SImode)) \
2020 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2021 && power_of_two_operand (xiop0, SImode)) \
2024 if (GET_MODE_SIZE (MODE) <= 4 \
2025 && (code == LSHIFTRT || code == ASHIFTRT \
2026 || code == ASHIFT || code == ROTATERT) \
2027 && (! arm_arch4 || (MODE) != HImode)) \
2029 rtx op = XEXP (INDEX, 1); \
2030 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2031 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2032 && INTVAL (op) <= 31) \
2035 /* NASTY: Since this limits the addressing of unsigned \
2037 range = ((MODE) == HImode || (MODE) == QImode) \
2038 ? (arm_arch4 ? 256 : 4095) : 4096; \
2039 if (code == CONST_INT && INTVAL (INDEX) < range \
2040 && INTVAL (INDEX) > -range) \
2046 /* Jump to LABEL if X is a valid address RTX. This must take
2047 REG_OK_STRICT into account when deciding about valid registers.
2049 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2050 floating SYMBOL_REF to the constant pool. Allow REG-only and
2051 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2052 forced though a static cell to ensure addressability. */
2053 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2055 if (ARM_BASE_REGISTER_RTX_P (X)) \
2057 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2058 && GET_CODE (XEXP (X, 0)) == REG \
2059 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2061 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2062 && (GET_CODE (X) == LABEL_REF \
2063 || (GET_CODE (X) == CONST \
2064 && GET_CODE (XEXP ((X), 0)) == PLUS \
2065 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2066 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT))) \
2068 else if ((MODE) == TImode) \
2070 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2072 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2073 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2075 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2076 if (val == 4 || val == -4 || val == -8) \
2080 else if (GET_CODE (X) == PLUS) \
2082 rtx xop0 = XEXP (X, 0); \
2083 rtx xop1 = XEXP (X, 1); \
2085 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2086 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2087 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2088 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2090 /* Reload currently can't handle MINUS, so disable this for now */ \
2091 /* else if (GET_CODE (X) == MINUS) \
2093 rtx xop0 = XEXP (X,0); \
2094 rtx xop1 = XEXP (X,1); \
2096 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2097 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2099 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2100 && GET_CODE (X) == SYMBOL_REF \
2101 && CONSTANT_POOL_ADDRESS_P (X) \
2103 && symbol_mentioned_p (get_pool_constant (X)))) \
2105 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2106 && (GET_MODE_SIZE (MODE) <= 4) \
2107 && GET_CODE (XEXP (X, 0)) == REG \
2108 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2112 /* ---------------------thumb version----------------------------------*/
2113 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2114 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2115 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2116 && ((VAL) & 1) == 0) \
2117 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2118 && ((VAL) & 3) == 0))
2120 /* The AP may be eliminated to either the SP or the FP, so we use the
2121 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2123 /* ??? Verify whether the above is the right approach. */
2125 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2126 needs special handling also. */
2128 /* ??? Look at how the mips16 port solves this problem. It probably uses
2129 better ways to solve some of these problems. */
2131 /* Although it is not incorrect, we don't accept QImode and HImode
2132 addresses based on the frame pointer or arg pointer until the
2133 reload pass starts. This is so that eliminating such addresses
2134 into stack based ones won't produce impossible code. */
2135 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2137 /* ??? Not clear if this is right. Experiment. */ \
2138 if (GET_MODE_SIZE (MODE) < 4 \
2139 && ! (reload_in_progress || reload_completed) \
2140 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2141 || reg_mentioned_p (arg_pointer_rtx, X) \
2142 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2143 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2144 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2145 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2147 /* Accept any base register. SP only in SImode or larger. */ \
2148 else if (GET_CODE (X) == REG \
2149 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2151 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2152 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2153 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2155 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2156 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2157 && (GET_CODE (X) == LABEL_REF \
2158 || (GET_CODE (X) == CONST \
2159 && GET_CODE (XEXP (X, 0)) == PLUS \
2160 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2161 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2163 /* Post-inc indexing only supported for SImode and larger. */ \
2164 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2165 && GET_CODE (XEXP (X, 0)) == REG \
2166 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2168 else if (GET_CODE (X) == PLUS) \
2170 /* REG+REG address can be any two index registers. */ \
2171 /* We disallow FRAME+REG addressing since we know that FRAME \
2172 will be replaced with STACK, and SP relative addressing only \
2173 permits SP+OFFSET. */ \
2174 if (GET_MODE_SIZE (MODE) <= 4 \
2175 && GET_CODE (XEXP (X, 0)) == REG \
2176 && GET_CODE (XEXP (X, 1)) == REG \
2177 && XEXP (X, 0) != frame_pointer_rtx \
2178 && XEXP (X, 1) != frame_pointer_rtx \
2179 && XEXP (X, 0) != virtual_stack_vars_rtx \
2180 && XEXP (X, 1) != virtual_stack_vars_rtx \
2181 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2182 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2184 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2185 else if (GET_CODE (XEXP (X, 0)) == REG \
2186 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2187 || XEXP (X, 0) == arg_pointer_rtx) \
2188 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2189 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2191 /* REG+const has 10 bit offset for SP, but only SImode and \
2192 larger is supported. */ \
2193 /* ??? Should probably check for DI/DFmode overflow here \
2194 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2195 else if (GET_CODE (XEXP (X, 0)) == REG \
2196 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2197 && GET_MODE_SIZE (MODE) >= 4 \
2198 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2199 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2200 + GET_MODE_SIZE (MODE)) <= 1024 \
2201 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2203 else if (GET_CODE (XEXP (X, 0)) == REG \
2204 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2205 && GET_MODE_SIZE (MODE) >= 4 \
2206 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2207 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2210 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2211 && GET_CODE (X) == SYMBOL_REF \
2212 && CONSTANT_POOL_ADDRESS_P (X) \
2214 && symbol_mentioned_p (get_pool_constant (X)))) \
2218 /* ------------------------------------------------------------------- */
2219 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2221 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2222 else /* if (TARGET_THUMB) */ \
2223 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2224 /* ------------------------------------------------------------------- */
2226 /* Try machine-dependent ways of modifying an illegitimate address
2227 to be legitimate. If we find one, return the new, valid address.
2228 This macro is used in only one place: `memory_address' in explow.c.
2230 OLDX is the address as it was before break_out_memory_refs was called.
2231 In some cases it is useful to look at this to decide what needs to be done.
2233 MODE and WIN are passed so that this macro can use
2234 GO_IF_LEGITIMATE_ADDRESS.
2236 It is always safe for this macro to do nothing. It exists to recognize
2237 opportunities to optimize the output.
2239 On the ARM, try to convert [REG, #BIGCONST]
2240 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2241 where VALIDCONST == 0 in case of TImode. */
2242 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2244 if (GET_CODE (X) == PLUS) \
2246 rtx xop0 = XEXP (X, 0); \
2247 rtx xop1 = XEXP (X, 1); \
2249 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2250 xop0 = force_reg (SImode, xop0); \
2251 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2252 xop1 = force_reg (SImode, xop1); \
2253 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2254 && GET_CODE (xop1) == CONST_INT) \
2256 HOST_WIDE_INT n, low_n; \
2257 rtx base_reg, val; \
2258 n = INTVAL (xop1); \
2260 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2272 low_n = ((MODE) == TImode ? 0 \
2273 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2276 base_reg = gen_reg_rtx (SImode); \
2277 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2278 GEN_INT (n)), NULL_RTX); \
2279 emit_move_insn (base_reg, val); \
2280 (X) = (low_n == 0 ? base_reg \
2281 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2283 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2284 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2286 else if (GET_CODE (X) == MINUS) \
2288 rtx xop0 = XEXP (X, 0); \
2289 rtx xop1 = XEXP (X, 1); \
2291 if (CONSTANT_P (xop0)) \
2292 xop0 = force_reg (SImode, xop0); \
2293 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2294 xop1 = force_reg (SImode, xop1); \
2295 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2296 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2299 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2300 if (memory_address_p (MODE, X)) \
2304 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2306 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2308 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2310 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2312 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2314 /* Go to LABEL if ADDR (a legitimate address expression)
2315 has an effect that depends on the machine mode it is used for. */
2316 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2318 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2319 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2323 /* Nothing helpful to do for the Thumb */
2324 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2326 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2329 /* Specify the machine mode that this machine uses
2330 for the index in the tablejump instruction. */
2331 #define CASE_VECTOR_MODE Pmode
2333 /* Define as C expression which evaluates to nonzero if the tablejump
2334 instruction expects the table to contain offsets from the address of the
2336 Do not define this if the table should contain absolute addresses. */
2337 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2339 /* Specify the tree operation to be used to convert reals to integers. */
2340 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2342 /* This is the kind of divide that is easiest to do in the general case. */
2343 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2345 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2346 unsigned is probably best, but may break some code. */
2347 #ifndef DEFAULT_SIGNED_CHAR
2348 #define DEFAULT_SIGNED_CHAR 0
2351 /* Don't cse the address of the function being compiled. */
2352 #define NO_RECURSIVE_FUNCTION_CSE 1
2354 /* Max number of bytes we can move from memory to memory
2355 in one reasonably fast instruction. */
2358 /* Define if operations between registers always perform the operation
2359 on the full register even if a narrower mode is specified. */
2360 #define WORD_REGISTER_OPERATIONS
2362 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2363 will either zero-extend or sign-extend. The value of this macro should
2364 be the code that says which one of the two operations is implicitly
2365 done, NIL if none. */
2366 #define LOAD_EXTEND_OP(MODE) \
2367 (TARGET_THUMB ? ZERO_EXTEND : \
2368 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2369 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2371 /* Define this if zero-extension is slow (more than one real instruction).
2372 On the ARM, it is more than one instruction only if not fetching from
2374 /* #define SLOW_ZERO_EXTEND */
2376 /* Nonzero if access to memory by bytes is slow and undesirable. */
2377 #define SLOW_BYTE_ACCESS 0
2379 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2381 /* Immediate shift counts are truncated by the output routines (or was it
2382 the assembler?). Shift counts in a register are truncated by ARM. Note
2383 that the native compiler puts too large (> 32) immediate shift counts
2384 into a register and shifts by the register, letting the ARM decide what
2385 to do instead of doing that itself. */
2386 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2387 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2388 On the arm, Y in a register is used modulo 256 for the shift. Only for
2389 rotates is modulo 32 used. */
2390 /* #define SHIFT_COUNT_TRUNCATED 1 */
2392 /* All integers have the same format so truncation is easy. */
2393 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2395 /* Calling from registers is a massive pain. */
2396 #define NO_FUNCTION_CSE 1
2398 /* Chars and shorts should be passed as ints. */
2399 #define PROMOTE_PROTOTYPES 1
2401 /* The machine modes of pointers and functions */
2402 #define Pmode SImode
2403 #define FUNCTION_MODE Pmode
2405 #define ARM_FRAME_RTX(X) \
2406 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2407 || (X) == arg_pointer_rtx)
2409 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2410 return arm_rtx_costs (X, CODE, OUTER_CODE);
2412 /* Moves to and from memory are quite expensive */
2413 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2414 (TARGET_ARM ? 10 : \
2415 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2416 * (CLASS == LO_REGS ? 1 : 2)))
2418 /* All address computations that can be done are free, but rtx cost returns
2419 the same for practically all of them. So we weight the different types
2420 of address here in the order (most pref first):
2421 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2422 #define ARM_ADDRESS_COST(X) \
2423 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2424 || GET_CODE (X) == SYMBOL_REF) \
2426 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2427 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2429 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2430 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2431 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2432 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2433 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2434 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2438 #define THUMB_ADDRESS_COST(X) \
2439 ((GET_CODE (X) == REG \
2440 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2441 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2444 #define ADDRESS_COST(X) \
2445 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2447 /* Try to generate sequences that don't involve branches, we can then use
2448 conditional instructions */
2449 #define BRANCH_COST \
2450 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2452 /* A C statement to update the variable COST based on the relationship
2453 between INSN that is dependent on DEP through dependence LINK. */
2454 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2455 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2457 /* Position Independent Code. */
2458 /* We decide which register to use based on the compilation options and
2459 the assembler in use; this is more general than the APCS restriction of
2460 using sb (r9) all the time. */
2461 extern int arm_pic_register;
2463 /* Used when parsing command line option -mpic-register=. */
2464 extern const char * arm_pic_register_string;
2466 /* The register number of the register used to address a table of static
2467 data addresses in memory. */
2468 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2470 #define FINALIZE_PIC arm_finalize_pic ()
2472 /* We can't directly access anything that contains a symbol,
2473 nor can we indirect via the constant pool. */
2474 #define LEGITIMATE_PIC_OPERAND_P(X) \
2475 ( ! symbol_mentioned_p (X) \
2476 && ! label_mentioned_p (X) \
2477 && (! CONSTANT_POOL_ADDRESS_P (X) \
2478 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2479 && ! label_mentioned_p (get_pool_constant (X)))))
2481 /* We need to know when we are making a constant pool; this determines
2482 whether data needs to be in the GOT or can be referenced via a GOT
2484 extern int making_const_table;
2486 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2487 with arguments ARGS is a valid machine specific attribute for TYPE.
2488 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2489 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2490 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2492 /* If defined, a C expression whose value is zero if the attributes on
2493 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2494 two if they are nearly compatible (which causes a warning to be
2496 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2497 (arm_comp_type_attributes (TYPE1, TYPE2))
2499 /* If defined, a C statement that assigns default attributes to newly
2501 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2502 arm_set_default_type_attributes (TYPE)
2504 /* Handle pragmas for compatibility with Intel's compilers. */
2505 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2506 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2507 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2508 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2511 /* Condition code information. */
2512 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2513 return the mode to be used for the comparison.
2514 CCFPEmode should be used with floating inequalities,
2515 CCFPmode should be used with floating equalities.
2516 CC_NOOVmode should be used with SImode integer equalities.
2517 CC_Zmode should be used if only the Z flag is set correctly
2518 CCmode should be used otherwise. */
2520 #define EXTRA_CC_MODES \
2521 CC(CC_NOOVmode, "CC_NOOV") \
2522 CC(CC_Zmode, "CC_Z") \
2523 CC(CC_SWPmode, "CC_SWP") \
2524 CC(CCFPmode, "CCFP") \
2525 CC(CCFPEmode, "CCFPE") \
2526 CC(CC_DNEmode, "CC_DNE") \
2527 CC(CC_DEQmode, "CC_DEQ") \
2528 CC(CC_DLEmode, "CC_DLE") \
2529 CC(CC_DLTmode, "CC_DLT") \
2530 CC(CC_DGEmode, "CC_DGE") \
2531 CC(CC_DGTmode, "CC_DGT") \
2532 CC(CC_DLEUmode, "CC_DLEU") \
2533 CC(CC_DLTUmode, "CC_DLTU") \
2534 CC(CC_DGEUmode, "CC_DGEU") \
2535 CC(CC_DGTUmode, "CC_DGTU") \
2536 CC(CC_Cmode, "CC_C")
2538 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2540 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2542 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2545 if (GET_CODE (OP1) == CONST_INT \
2546 && ! (const_ok_for_arm (INTVAL (OP1)) \
2547 || (const_ok_for_arm (- INTVAL (OP1))))) \
2549 rtx const_op = OP1; \
2550 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2556 #define STORE_FLAG_VALUE 1
2560 /* Gcc puts the pool in the wrong place for ARM, since we can only
2561 load addresses a limited distance around the pc. We do some
2562 special munging to move the constant pool values to the correct
2563 point in the code. */
2564 #define MACHINE_DEPENDENT_REORG(INSN) \
2568 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2570 /* Output an internal label definition. */
2571 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2572 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2575 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2577 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2578 && !strcmp (PREFIX, "L")) \
2580 arm_ccfsm_state = 0; \
2581 arm_target_insn = NULL; \
2583 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2584 ASM_OUTPUT_LABEL (STREAM, s); \
2589 /* Output a push or a pop instruction (only used when profiling). */
2590 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2592 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2593 STACK_POINTER_REGNUM, REGNO); \
2595 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2598 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2600 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2601 STACK_POINTER_REGNUM, REGNO); \
2603 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2605 /* This is how to output a label which precedes a jumptable. Since
2606 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2607 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2611 ASM_OUTPUT_ALIGN (FILE, 2); \
2612 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2616 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2621 if (is_called_in_ARM_mode (DECL)) \
2622 fprintf (STREAM, "\t.code 32\n") ; \
2624 fprintf (STREAM, "\t.thumb_func\n") ; \
2626 if (TARGET_POKE_FUNCTION_NAME) \
2627 arm_poke_function_name (STREAM, (char *) NAME); \
2631 /* For aliases of functions we use .thumb_set instead. */
2632 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2635 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2636 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2638 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2640 fprintf (FILE, "\t.thumb_set "); \
2641 assemble_name (FILE, LABEL1); \
2642 fprintf (FILE, ","); \
2643 assemble_name (FILE, LABEL2); \
2644 fprintf (FILE, "\n"); \
2647 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2651 /* Target characters. */
2652 #define TARGET_BELL 007
2653 #define TARGET_BS 010
2654 #define TARGET_TAB 011
2655 #define TARGET_NEWLINE 012
2656 #define TARGET_VT 013
2657 #define TARGET_FF 014
2658 #define TARGET_CR 015
2660 /* Only perform branch elimination (by making instructions conditional) if
2661 we're optimising. Otherwise it's of no use anyway. */
2662 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2663 if (TARGET_ARM && optimize) \
2664 arm_final_prescan_insn (INSN); \
2665 else if (TARGET_THUMB) \
2666 thumb_final_prescan_insn (INSN)
2668 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2669 (CODE == '@' || CODE == '|' \
2670 || (TARGET_ARM && (CODE == '?')) \
2671 || (TARGET_THUMB && (CODE == '_')))
2673 /* Output an operand of an instruction. */
2674 #define PRINT_OPERAND(STREAM, X, CODE) \
2675 arm_print_operand (STREAM, X, CODE)
2677 /* Create an [unsigned] host sized integer declaration that
2678 avoids compiler warnings. */
2680 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2681 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2683 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2684 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2687 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2688 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2689 : (((x) & HOST_UINT (0xffffffff)) | \
2690 (((x) & HOST_UINT (0x80000000)) \
2691 ? ((~ HOST_INT (0)) \
2692 & ~ HOST_UINT(0xffffffff)) \
2695 /* Output the address of an operand. */
2696 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2698 int is_minus = GET_CODE (X) == MINUS; \
2700 if (GET_CODE (X) == REG) \
2701 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2702 else if (GET_CODE (X) == PLUS || is_minus) \
2704 rtx base = XEXP (X, 0); \
2705 rtx index = XEXP (X, 1); \
2706 HOST_WIDE_INT offset = 0; \
2707 if (GET_CODE (base) != REG) \
2709 /* Ensure that BASE is a register */ \
2710 /* (one of them must be). */ \
2715 switch (GET_CODE (index)) \
2718 offset = INTVAL (index); \
2721 asm_fprintf (STREAM, "[%r, #%d]", \
2722 REGNO (base), offset); \
2726 asm_fprintf (STREAM, "[%r, %s%r]", \
2727 REGNO (base), is_minus ? "-" : "", \
2737 asm_fprintf (STREAM, "[%r, %s%r", \
2738 REGNO (base), is_minus ? "-" : "", \
2739 REGNO (XEXP (index, 0))); \
2740 arm_print_operand (STREAM, index, 'S'); \
2741 fputs ("]", STREAM); \
2749 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2750 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2752 extern int output_memory_reference_mode; \
2754 if (GET_CODE (XEXP (X, 0)) != REG) \
2757 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2758 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2759 REGNO (XEXP (X, 0)), \
2760 GET_CODE (X) == PRE_DEC ? "-" : "", \
2761 GET_MODE_SIZE (output_memory_reference_mode));\
2763 asm_fprintf (STREAM, "[%r], #%s%d", \
2764 REGNO (XEXP (X, 0)), \
2765 GET_CODE (X) == POST_DEC ? "-" : "", \
2766 GET_MODE_SIZE (output_memory_reference_mode));\
2768 else output_addr_const (STREAM, X); \
2771 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2773 if (GET_CODE (X) == REG) \
2774 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2775 else if (GET_CODE (X) == POST_INC) \
2776 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2777 else if (GET_CODE (X) == PLUS) \
2779 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2780 asm_fprintf (STREAM, "[%r, #%d]", \
2781 REGNO (XEXP (X, 0)), \
2782 (int) INTVAL (XEXP (X, 1))); \
2784 asm_fprintf (STREAM, "[%r, %r]", \
2785 REGNO (XEXP (X, 0)), \
2786 REGNO (XEXP (X, 1))); \
2789 output_addr_const (STREAM, X); \
2792 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2794 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2796 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2798 /* Handles PIC addr specially */
2799 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2801 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2803 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2804 fputs (" - (", STREAM); \
2805 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2806 fputs (")", STREAM); \
2809 output_addr_const (STREAM, X); \
2811 /* Mark symbols as position independent. We only do this in the \
2812 .text segment, not in the .data segment. */ \
2813 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2814 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2816 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2817 fprintf (STREAM, "(GOTOFF)"); \
2818 else if (GET_CODE (X) == LABEL_REF) \
2819 fprintf (STREAM, "(GOTOFF)"); \
2821 fprintf (STREAM, "(GOT)"); \
2825 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2826 Used for C++ multiple inheritance. */
2827 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2830 int mi_delta = (DELTA); \
2831 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2833 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2836 mi_delta = - mi_delta; \
2837 while (mi_delta != 0) \
2839 if ((mi_delta & (3 << shift)) == 0) \
2843 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2844 mi_op, this_regno, this_regno, \
2845 mi_delta & (0xff << shift)); \
2846 mi_delta &= ~(0xff << shift); \
2850 fputs ("\tb\t", FILE); \
2851 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2852 if (NEED_PLT_RELOC) \
2853 fputs ("(PLT)", FILE); \
2854 fputc ('\n', FILE); \
2858 /* A C expression whose value is RTL representing the value of the return
2859 address for the frame COUNT steps up from the current frame. */
2861 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2862 arm_return_addr (COUNT, FRAME)
2864 /* Mask of the bits in the PC that contain the real return address
2865 when running in 26-bit mode. */
2866 #define RETURN_ADDR_MASK26 (0x03fffffc)
2868 /* Pick up the return address upon entry to a procedure. Used for
2869 dwarf2 unwind information. This also enables the table driven
2871 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2872 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2874 /* Used to mask out junk bits from the return address, such as
2875 processor state, interrupt status, condition codes and the like. */
2876 #define MASK_RETURN_ADDR \
2877 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2878 in 26 bit mode, the condition codes must be masked out of the \
2879 return address. This does not apply to ARM6 and later processors \
2880 when running in 32 bit mode. */ \
2881 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2882 : (GEN_INT ((unsigned long)0xffffffff)))
2885 /* Define the codes that are matched by predicates in arm.c */
2886 #define PREDICATE_CODES \
2887 {"s_register_operand", {SUBREG, REG}}, \
2888 {"f_register_operand", {SUBREG, REG}}, \
2889 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2890 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2891 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2892 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2893 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2894 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2895 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2896 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2897 {"offsettable_memory_operand", {MEM}}, \
2898 {"bad_signed_byte_operand", {MEM}}, \
2899 {"alignable_memory_operand", {MEM}}, \
2900 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2901 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2902 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2903 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2904 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2905 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2906 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2907 {"load_multiple_operation", {PARALLEL}}, \
2908 {"store_multiple_operation", {PARALLEL}}, \
2909 {"equality_operator", {EQ, NE}}, \
2910 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2911 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2913 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2914 {"const_shift_operand", {CONST_INT}}, \
2915 {"multi_register_push", {PARALLEL}}, \
2916 {"cc_register", {REG}}, \
2917 {"logical_binary_operator", {AND, IOR, XOR}}, \
2918 {"dominant_cc_register", {REG}},
2920 /* Define this if you have special predicates that know special things
2921 about modes. Genrecog will warn about certain forms of
2922 match_operand without a mode; if the operand predicate is listed in
2923 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2924 #define SPECIAL_MODE_PREDICATES \
2925 "cc_register", "dominant_cc_register",
2927 #endif /* __ARM_H__ */
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