1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
56 typedef enum arm_cond_code
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
63 extern arm_cc arm_current_cc;
65 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
67 extern int arm_target_label;
68 extern int arm_ccfsm_state;
69 extern struct rtx_def * arm_target_insn;
70 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 /* The floating point instruction architecture, can be 2 or 3 */
73 extern const char * target_fp_name;
74 /* Define the information needed to generate branch insns. This is
75 stored from the compare operation. Note that we can't use "rtx" here
76 since it hasn't been defined! */
77 extern struct rtx_def * arm_compare_op0;
78 extern struct rtx_def * arm_compare_op1;
79 /* The label of the current constant pool. */
80 extern struct rtx_def * pool_vector_label;
81 /* Set to 1 when a return insn is output, this means that the epilogue
83 extern int return_used_this_function;
85 /* Just in case configure has failed to define anything. */
86 #ifndef TARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
90 /* If the configuration file doesn't specify the cpu, the subtarget may
91 override it. If it doesn't, then default to an ARM6. */
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
93 #undef TARGET_CPU_DEFAULT
95 #ifdef SUBTARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
98 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
117 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
118 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
120 Unrecognized value in TARGET_CPU_DEFAULT.
130 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
131 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
133 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
135 /* Set the architecture define -- if -march= is set, then it overrides
136 the -mcpu= setting. */
137 #define CPP_CPU_ARCH_SPEC "\
138 -Acpu=arm -Amachine=arm \
139 %{march=arm2:-D__ARM_ARCH_2__} \
140 %{march=arm250:-D__ARM_ARCH_2__} \
141 %{march=arm3:-D__ARM_ARCH_2__} \
142 %{march=arm6:-D__ARM_ARCH_3__} \
143 %{march=arm600:-D__ARM_ARCH_3__} \
144 %{march=arm610:-D__ARM_ARCH_3__} \
145 %{march=arm7:-D__ARM_ARCH_3__} \
146 %{march=arm700:-D__ARM_ARCH_3__} \
147 %{march=arm710:-D__ARM_ARCH_3__} \
148 %{march=arm720:-D__ARM_ARCH_3__} \
149 %{march=arm7100:-D__ARM_ARCH_3__} \
150 %{march=arm7500:-D__ARM_ARCH_3__} \
151 %{march=arm7500fe:-D__ARM_ARCH_3__} \
152 %{march=arm7m:-D__ARM_ARCH_3M__} \
153 %{march=arm7dm:-D__ARM_ARCH_3M__} \
154 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
155 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
156 %{march=arm8:-D__ARM_ARCH_4__} \
157 %{march=arm810:-D__ARM_ARCH_4__} \
158 %{march=arm9:-D__ARM_ARCH_4T__} \
159 %{march=arm920:-D__ARM_ARCH_4__} \
160 %{march=arm920t:-D__ARM_ARCH_4T__} \
161 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
162 %{march=strongarm:-D__ARM_ARCH_4__} \
163 %{march=strongarm110:-D__ARM_ARCH_4__} \
164 %{march=strongarm1100:-D__ARM_ARCH_4__} \
165 %{march=xscale:-D__ARM_ARCH_5TE__} \
166 %{march=xscale:-D__XSCALE__} \
167 %{march=armv2:-D__ARM_ARCH_2__} \
168 %{march=armv2a:-D__ARM_ARCH_2__} \
169 %{march=armv3:-D__ARM_ARCH_3__} \
170 %{march=armv3m:-D__ARM_ARCH_3M__} \
171 %{march=armv4:-D__ARM_ARCH_4__} \
172 %{march=armv4t:-D__ARM_ARCH_4T__} \
173 %{march=armv5:-D__ARM_ARCH_5__} \
174 %{march=armv5t:-D__ARM_ARCH_5T__} \
175 %{march=armv5e:-D__ARM_ARCH_5E__} \
176 %{march=armv5te:-D__ARM_ARCH_5TE__} \
178 %{mcpu=arm2:-D__ARM_ARCH_2__} \
179 %{mcpu=arm250:-D__ARM_ARCH_2__} \
180 %{mcpu=arm3:-D__ARM_ARCH_2__} \
181 %{mcpu=arm6:-D__ARM_ARCH_3__} \
182 %{mcpu=arm600:-D__ARM_ARCH_3__} \
183 %{mcpu=arm610:-D__ARM_ARCH_3__} \
184 %{mcpu=arm7:-D__ARM_ARCH_3__} \
185 %{mcpu=arm700:-D__ARM_ARCH_3__} \
186 %{mcpu=arm710:-D__ARM_ARCH_3__} \
187 %{mcpu=arm720:-D__ARM_ARCH_3__} \
188 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
189 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
190 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
191 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
192 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
193 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
194 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
195 %{mcpu=arm8:-D__ARM_ARCH_4__} \
196 %{mcpu=arm810:-D__ARM_ARCH_4__} \
197 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
198 %{mcpu=arm920:-D__ARM_ARCH_4__} \
199 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
201 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
202 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
203 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
204 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
205 %{mcpu=xscale:-D__XSCALE__} \
206 %{!mcpu*:%(cpp_cpu_arch_default)}} \
209 /* Define __APCS_26__ if the PC also contains the PSR */
210 #define CPP_APCS_PC_SPEC "\
211 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
213 %{mapcs-26:-D__APCS_26__} \
214 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
217 #ifndef CPP_APCS_PC_DEFAULT_SPEC
218 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
221 #define CPP_FLOAT_SPEC "\
223 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
225 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
228 /* Default is hard float, which doesn't define anything */
229 #define CPP_FLOAT_DEFAULT_SPEC ""
231 #define CPP_ENDIAN_SPEC "\
234 %e-mbig-endian and -mlittle-endian may not be used together} \
235 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
236 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
237 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
240 /* Default is little endian. */
241 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
243 /* Add a define for interworking. Needed when building libgcc.a.
244 This must define __THUMB_INTERWORK__ to the pre-processor if
245 interworking is enabled by default. */
246 #ifndef CPP_INTERWORK_DEFAULT_SPEC
247 #define CPP_INTERWORK_DEFAULT_SPEC ""
250 #define CPP_INTERWORK_SPEC " \
251 %{mthumb-interwork: \
252 %{mno-thumb-interwork: %eincompatible interworking options} \
253 -D__THUMB_INTERWORK__} \
254 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
257 #ifndef CPP_PREDEFINES
258 #define CPP_PREDEFINES ""
265 /* This macro defines names of additional specifications to put in the specs
266 that can be used in various specifications like CC1_SPEC. Its definition
267 is an initializer with a subgrouping for each command option.
269 Each subgrouping contains a string constant, that defines the
270 specification name, and a string constant that used by the GNU CC driver
273 Do not define this macro if it does not need to do anything. */
274 #define EXTRA_SPECS \
275 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
276 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
277 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
278 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
279 { "cpp_float", CPP_FLOAT_SPEC }, \
280 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
281 { "cpp_endian", CPP_ENDIAN_SPEC }, \
282 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
283 { "cpp_isa", CPP_ISA_SPEC }, \
284 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
285 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
286 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
287 SUBTARGET_EXTRA_SPECS
289 #ifndef SUBTARGET_EXTRA_SPECS
290 #define SUBTARGET_EXTRA_SPECS
293 #ifndef SUBTARGET_CPP_SPEC
294 #define SUBTARGET_CPP_SPEC ""
297 /* Run-time Target Specification. */
298 #ifndef TARGET_VERSION
299 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
302 /* Nonzero if the function prologue (and epilogue) should obey
303 the ARM Procedure Call Standard. */
304 #define ARM_FLAG_APCS_FRAME (1 << 0)
306 /* Nonzero if the function prologue should output the function name to enable
307 the post mortem debugger to print a backtrace (very useful on RISCOS,
308 unused on RISCiX). Specifying this flag also enables
309 -fno-omit-frame-pointer.
310 XXX Must still be implemented in the prologue. */
311 #define ARM_FLAG_POKE (1 << 1)
313 /* Nonzero if floating point instructions are emulated by the FPE, in which
314 case instruction scheduling becomes very uninteresting. */
315 #define ARM_FLAG_FPE (1 << 2)
317 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
318 that assume restoration of the condition flags when returning from a
319 branch and link (ie a function). */
320 #define ARM_FLAG_APCS_32 (1 << 3)
322 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
324 /* Nonzero if stack checking should be performed on entry to each function
325 which allocates temporary variables on the stack. */
326 #define ARM_FLAG_APCS_STACK (1 << 4)
328 /* Nonzero if floating point parameters should be passed to functions in
329 floating point registers. */
330 #define ARM_FLAG_APCS_FLOAT (1 << 5)
332 /* Nonzero if re-entrant, position independent code should be generated.
333 This is equivalent to -fpic. */
334 #define ARM_FLAG_APCS_REENT (1 << 6)
336 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
337 be loaded using either LDRH or LDRB instructions. */
338 #define ARM_FLAG_MMU_TRAPS (1 << 7)
340 /* Nonzero if all floating point instructions are missing (and there is no
341 emulator either). Generate function calls for all ops in this case. */
342 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
344 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
345 #define ARM_FLAG_BIG_END (1 << 9)
347 /* Nonzero if we should compile for Thumb interworking. */
348 #define ARM_FLAG_INTERWORK (1 << 10)
350 /* Nonzero if we should have little-endian words even when compiling for
351 big-endian (for backwards compatibility with older versions of GCC). */
352 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
354 /* Nonzero if we need to protect the prolog from scheduling */
355 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
357 /* Nonzero if a call to abort should be generated if a noreturn
358 function tries to return. */
359 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
361 /* Nonzero if function prologues should not load the PIC register. */
362 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
364 /* Nonzero if all call instructions should be indirect. */
365 #define ARM_FLAG_LONG_CALLS (1 << 15)
367 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
368 #define ARM_FLAG_THUMB (1 << 16)
370 /* Set if a TPCS style stack frame should be generated, for non-leaf
371 functions, even if they do not need one. */
372 #define THUMB_FLAG_BACKTRACE (1 << 17)
374 /* Set if a TPCS style stack frame should be generated, for leaf
375 functions, even if they do not need one. */
376 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
378 /* Set if externally visible functions should assume that they
379 might be called in ARM mode, from a non-thumb aware code. */
380 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
382 /* Set if calls via function pointers should assume that their
383 destination is non-Thumb aware. */
384 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
386 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
387 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
388 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
389 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
390 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
391 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
392 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
393 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
394 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
395 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
396 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
397 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
398 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
399 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
400 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
401 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
402 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
403 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
404 #define TARGET_ARM (! TARGET_THUMB)
405 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
406 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
407 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
408 #define TARGET_BACKTRACE (leaf_function_p () \
409 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
410 : (target_flags & THUMB_FLAG_BACKTRACE))
412 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
413 Bit 31 is reserved. See riscix.h. */
414 #ifndef SUBTARGET_SWITCHES
415 #define SUBTARGET_SWITCHES
418 #define TARGET_SWITCHES \
420 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
421 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
422 N_("Generate APCS conformant stack frames") }, \
423 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
424 {"poke-function-name", ARM_FLAG_POKE, \
425 N_("Store function names in object code") }, \
426 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
427 {"fpe", ARM_FLAG_FPE, "" }, \
428 {"apcs-32", ARM_FLAG_APCS_32, \
429 N_("Use the 32-bit version of the APCS") }, \
430 {"apcs-26", -ARM_FLAG_APCS_32, \
431 N_("Use the 26-bit version of the APCS") }, \
432 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
433 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
434 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
435 N_("Pass FP arguments in FP registers") }, \
436 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
437 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
438 N_("Generate re-entrant, PIC code") }, \
439 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
440 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
441 N_("The MMU will trap on unaligned accesses") }, \
442 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
443 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
444 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
446 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
447 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
448 N_("Use library calls to perform FP operations") }, \
449 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
450 N_("Use hardware floating point instructions") }, \
451 {"big-endian", ARM_FLAG_BIG_END, \
452 N_("Assume target CPU is configured as big endian") }, \
453 {"little-endian", -ARM_FLAG_BIG_END, \
454 N_("Assume target CPU is configured as little endian") }, \
455 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
456 N_("Assume big endian bytes, little endian words") }, \
457 {"thumb-interwork", ARM_FLAG_INTERWORK, \
458 N_("Support calls between Thumb and ARM instruction sets") }, \
459 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
460 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
461 N_("Generate a call to abort if a noreturn function returns")}, \
462 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
463 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
464 N_("Do not move instructions into a function's prologue") }, \
465 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
466 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
467 N_("Do not load the PIC register in function prologues") }, \
468 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
469 {"long-calls", ARM_FLAG_LONG_CALLS, \
470 N_("Generate call insns as indirect calls, if necessary") }, \
471 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
472 {"thumb", ARM_FLAG_THUMB, \
473 N_("Compile for the Thumb not the ARM") }, \
474 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
475 {"arm", -ARM_FLAG_THUMB, "" }, \
476 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
477 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
478 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
479 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
480 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
481 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
482 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
483 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
484 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
486 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
487 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
488 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
491 {"", TARGET_DEFAULT, "" } \
494 #define TARGET_OPTIONS \
496 {"cpu=", & arm_select[0].string, \
497 N_("Specify the name of the target CPU") }, \
498 {"arch=", & arm_select[1].string, \
499 N_("Specify the name of the target architecture") }, \
500 {"tune=", & arm_select[2].string, "" }, \
501 {"fpe=", & target_fp_name, "" }, \
502 {"fp=", & target_fp_name, \
503 N_("Specify the version of the floating point emulator") }, \
504 {"structure-size-boundary=", & structure_size_string, \
505 N_("Specify the minimum bit alignment of structures") }, \
506 {"pic-register=", & arm_pic_register_string, \
507 N_("Specify the register to be used for PIC addressing") } \
510 struct arm_cpu_select
514 const struct processors * processors;
517 /* This is a magic array. If the user specifies a command line switch
518 which matches one of the entries in TARGET_OPTIONS then the corresponding
519 string pointer will be set to the value specified by the user. */
520 extern struct arm_cpu_select arm_select[];
528 /* Recast the program mode class to be the prog_mode attribute */
529 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
531 extern enum prog_mode_type arm_prgmode;
533 /* What sort of floating point unit do we have? Hardware or software.
534 If software, is it issue 2 or issue 3? */
535 enum floating_point_type
542 /* Recast the floating point class to be the floating point attribute. */
543 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
545 /* What type of floating point to tune for */
546 extern enum floating_point_type arm_fpu;
548 /* What type of floating point instructions are available */
549 extern enum floating_point_type arm_fpu_arch;
551 /* Default floating point architecture. Override in sub-target if
554 #define FP_DEFAULT FP_SOFT2
557 /* Nonzero if the processor has a fast multiply insn, and one that does
558 a 64-bit multiply of two 32-bit values. */
559 extern int arm_fast_multiply;
561 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
562 extern int arm_arch4;
564 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
565 extern int arm_arch5;
567 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
568 extern int arm_arch5e;
570 /* Nonzero if this chip can benefit from load scheduling. */
571 extern int arm_ld_sched;
573 /* Nonzero if generating thumb code. */
574 extern int thumb_code;
576 /* Nonzero if this chip is a StrongARM. */
577 extern int arm_is_strong;
579 /* Nonzero if this chip is an XScale. */
580 extern int arm_is_xscale;
582 /* Nonzero if this chip is an ARM6 or an ARM7. */
583 extern int arm_is_6_or_7;
585 #ifndef TARGET_DEFAULT
586 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
589 /* The frame pointer register used in gcc has nothing to do with debugging;
590 that is controlled by the APCS-FRAME option. */
591 #define CAN_DEBUG_WITHOUT_FP
593 #undef TARGET_MEM_FUNCTIONS
594 #define TARGET_MEM_FUNCTIONS 1
596 #define OVERRIDE_OPTIONS arm_override_options ()
598 /* Nonzero if PIC code requires explicit qualifiers to generate
599 PLT and GOT relocs rather than the assembler doing so implicitly.
600 Subtargets can override these if required. */
601 #ifndef NEED_GOT_RELOC
602 #define NEED_GOT_RELOC 0
604 #ifndef NEED_PLT_RELOC
605 #define NEED_PLT_RELOC 0
608 /* Nonzero if we need to refer to the GOT with a PC-relative
609 offset. In other words, generate
611 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
615 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
617 The default is true, which matches NetBSD. Subtargets can
618 override this if required. */
623 /* Target machine storage Layout. */
626 /* Define this macro if it is advisable to hold scalars in registers
627 in a wider mode than that declared by the program. In such cases,
628 the value is constrained to be within the bounds of the declared
629 type, but kept valid in the wider mode. The signedness of the
630 extension may differ from that of the type. */
632 /* It is far faster to zero extend chars than to sign extend them */
634 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
635 if (GET_MODE_CLASS (MODE) == MODE_INT \
636 && GET_MODE_SIZE (MODE) < 4) \
638 if (MODE == QImode) \
640 else if (MODE == HImode) \
641 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
645 /* Define this macro if the promotion described by `PROMOTE_MODE'
646 should also be done for outgoing function arguments. */
647 /* This is required to ensure that push insns always push a word. */
648 #define PROMOTE_FUNCTION_ARGS
650 /* Define for XFmode extended real floating point support.
651 This will automatically cause REAL_ARITHMETIC to be defined. */
653 I think I have added all the code to make this work. Unfortunately,
654 early releases of the floating point emulation code on RISCiX used a
655 different format for extended precision numbers. On my RISCiX box there
656 is a bug somewhere which causes the machine to lock up when running enquire
657 with long doubles. There is the additional aspect that Norcroft C
658 treats long doubles as doubles and we ought to remain compatible.
659 Perhaps someone with an FPA coprocessor and not running RISCiX would like
660 to try this someday. */
661 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
663 /* Disable XFmode patterns in md file */
664 #define ENABLE_XF_PATTERNS 0
666 /* Define if you don't want extended real, but do want to use the
667 software floating point emulator for REAL_ARITHMETIC and
668 decimal <-> binary conversion. */
669 /* See comment above */
670 #define REAL_ARITHMETIC
672 /* Define this if most significant bit is lowest numbered
673 in instructions that operate on numbered bit-fields. */
674 #define BITS_BIG_ENDIAN 0
676 /* Define this if most significant byte of a word is the lowest numbered.
677 Most ARM processors are run in little endian mode, so that is the default.
678 If you want to have it run-time selectable, change the definition in a
679 cover file to be TARGET_BIG_ENDIAN. */
680 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
682 /* Define this if most significant word of a multiword number is the lowest
684 This is always false, even when in big-endian mode. */
685 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
687 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
688 on processor pre-defineds when compiling libgcc2.c. */
689 #if defined(__ARMEB__) && !defined(__ARMWEL__)
690 #define LIBGCC2_WORDS_BIG_ENDIAN 1
692 #define LIBGCC2_WORDS_BIG_ENDIAN 0
695 /* Define this if most significant word of doubles is the lowest numbered.
696 This is always true, even when in little-endian mode. */
697 #define FLOAT_WORDS_BIG_ENDIAN 1
699 /* Number of bits in an addressable storage unit */
700 #define BITS_PER_UNIT 8
702 #define BITS_PER_WORD 32
704 #define UNITS_PER_WORD 4
706 #define POINTER_SIZE 32
708 #define PARM_BOUNDARY 32
710 #define STACK_BOUNDARY 32
712 #define FUNCTION_BOUNDARY 32
714 /* The lowest bit is used to indicate Thumb-mode functions, so the
715 vbit must go into the delta field of pointers to member
717 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
719 #define EMPTY_FIELD_BOUNDARY 32
721 #define BIGGEST_ALIGNMENT 32
723 /* Make strings word-aligned so strcpy from constants will be faster. */
724 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
726 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
727 ((TREE_CODE (EXP) == STRING_CST \
728 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
729 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
731 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
732 value set in previous versions of this toolchain was 8, which produces more
733 compact structures. The command line option -mstructure_size_boundary=<n>
734 can be used to change this value. For compatibility with the ARM SDK
735 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
736 0020D) page 2-20 says "Structures are aligned on word boundaries". */
737 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
738 extern int arm_structure_size_boundary;
740 /* This is the value used to initialise arm_structure_size_boundary. If a
741 particular arm target wants to change the default value it should change
742 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
743 for an example of this. */
744 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
745 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
748 /* Used when parsing command line option -mstructure_size_boundary. */
749 extern const char * structure_size_string;
751 /* Non-zero if move instructions will actually fail to work
752 when given unaligned data. */
753 #define STRICT_ALIGNMENT 1
755 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
758 /* Standard register usage. */
760 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
761 (S - saved over call).
763 r0 * argument word/integer result
766 r4-r8 S register variable
767 r9 S (rfp) register variable (real frame pointer)
769 r10 F S (sl) stack limit (used by -mapcs-stack-check)
770 r11 F S (fp) argument pointer
771 r12 (ip) temp workspace
772 r13 F S (sp) lower end of current stack frame
773 r14 (lr) link address/workspace
774 r15 F (pc) program counter
776 f0 floating point result
777 f1-f3 floating point scratch
779 f4-f7 S floating point variable
781 cc This is NOT a real register, but is used internally
782 to represent things that use or set the condition
784 sfp This isn't either. It is used during rtl generation
785 since the offset between the frame pointer and the
786 auto's isn't known until after register allocation.
787 afp Nor this, we only need this because of non-local
788 goto. Without it fp appears to be used and the
789 elimination code won't get rid of sfp. It tracks
790 fp exactly at all times.
792 *: See CONDITIONAL_REGISTER_USAGE */
794 /* The stack backtrace structure is as follows:
795 fp points to here: | save code pointer | [fp]
796 | return link value | [fp, #-4]
797 | return sp value | [fp, #-8]
798 | return fp value | [fp, #-12]
799 [| saved r10 value |]
810 [| saved f7 value |] three words
811 [| saved f6 value |] three words
812 [| saved f5 value |] three words
813 [| saved f4 value |] three words
814 r0-r3 are not normally saved in a C function. */
816 /* 1 for registers that have pervasive standard uses
817 and are not available for the register allocator. */
818 #define FIXED_REGISTERS \
826 /* 1 for registers not available across function calls.
827 These must include the FIXED_REGISTERS and also any
828 registers that can be used without being saved.
829 The latter must include the registers where values are returned
830 and the register where structure-value addresses are passed.
831 Aside from that, you can include as many other registers as you like.
832 The CC is not preserved over function calls on the ARM 6, so it is
833 easier to assume this for all. SFP is preserved, since FP is. */
834 #define CALL_USED_REGISTERS \
842 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
843 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
846 #define CONDITIONAL_REGISTER_USAGE \
850 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
852 for (regno = FIRST_ARM_FP_REGNUM; \
853 regno <= LAST_ARM_FP_REGNUM; ++regno) \
854 fixed_regs[regno] = call_used_regs[regno] = 1; \
858 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
859 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
861 else if (TARGET_APCS_STACK) \
863 fixed_regs[10] = 1; \
864 call_used_regs[10] = 1; \
866 if (TARGET_APCS_FRAME) \
868 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
869 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
871 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
874 /* These are a couple of extensions to the formats accecpted
876 %@ prints out ASM_COMMENT_START
877 %r prints out REGISTER_PREFIX reg_names[arg] */
878 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
880 fputs (ASM_COMMENT_START, FILE); \
884 fputs (REGISTER_PREFIX, FILE); \
885 fputs (reg_names [va_arg (ARGS, int)], FILE); \
888 /* Round X up to the nearest word. */
889 #define ROUND_UP(X) (((X) + 3) & ~3)
891 /* Convert fron bytes to ints. */
892 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
894 /* The number of (integer) registers required to hold a quantity of type MODE. */
895 #define NUM_REGS(MODE) \
896 NUM_INTS (GET_MODE_SIZE (MODE))
898 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
899 #define NUM_REGS2(MODE, TYPE) \
900 NUM_INTS ((MODE) == BLKmode ? \
901 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
903 /* The number of (integer) argument register available. */
904 #define NUM_ARG_REGS 4
906 /* Return the regiser number of the N'th (integer) argument. */
907 #define ARG_REGISTER(N) (N - 1)
909 #if 0 /* FIXME: The ARM backend has special code to handle structure
910 returns, and will reserve its own hidden first argument. So
911 if this macro is enabled a *second* hidden argument will be
912 reserved, which will break binary compatibility with old
913 toolchains and also thunk handling. One day this should be
915 /* RTX for structure returns. NULL means use a hidden first argument. */
916 #define STRUCT_VALUE 0
918 /* Register in which address to store a structure value
919 is passed to a function. */
920 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
923 /* Specify the registers used for certain standard purposes.
924 The values of these macros are register numbers. */
926 /* The number of the last argument register. */
927 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
929 /* The number of the last "lo" register (thumb). */
930 #define LAST_LO_REGNUM 7
932 /* The register that holds the return address in exception handlers. */
933 #define EXCEPTION_LR_REGNUM 2
935 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
936 as an invisible last argument (possible since varargs don't exist in
937 Pascal), so the following is not true. */
938 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
940 /* Define this to be where the real frame pointer is if it is not possible to
941 work out the offset between the frame pointer and the automatic variables
942 until after register allocation has taken place. FRAME_POINTER_REGNUM
943 should point to a special register that we will make sure is eliminated.
945 For the Thumb we have another problem. The TPCS defines the frame pointer
946 as r11, and GCC belives that it is always possible to use the frame pointer
947 as base register for addressing purposes. (See comments in
948 find_reloads_address()). But - the Thumb does not allow high registers,
949 including r11, to be used as base address registers. Hence our problem.
951 The solution used here, and in the old thumb port is to use r7 instead of
952 r11 as the hard frame pointer and to have special code to generate
953 backtrace structures on the stack (if required to do so via a command line
954 option) using r11. This is the only 'user visable' use of r11 as a frame
956 #define ARM_HARD_FRAME_POINTER_REGNUM 11
957 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
959 #define HARD_FRAME_POINTER_REGNUM \
961 ? ARM_HARD_FRAME_POINTER_REGNUM \
962 : THUMB_HARD_FRAME_POINTER_REGNUM)
964 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
966 /* Register to use for pushing function arguments. */
967 #define STACK_POINTER_REGNUM SP_REGNUM
969 /* ARM floating pointer registers. */
970 #define FIRST_ARM_FP_REGNUM 16
971 #define LAST_ARM_FP_REGNUM 23
973 /* Base register for access to local variables of the function. */
974 #define FRAME_POINTER_REGNUM 25
976 /* Base register for access to arguments of the function. */
977 #define ARG_POINTER_REGNUM 26
979 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
980 #define FIRST_PSEUDO_REGISTER 27
982 /* Value should be nonzero if functions must have frame pointers.
983 Zero means the frame pointer need not be set up (and parms may be accessed
984 via the stack pointer) in functions that seem suitable.
985 If we have to have a frame pointer we might as well make use of it.
986 APCS says that the frame pointer does not need to be pushed in leaf
987 functions, or simple tail call functions. */
988 #define FRAME_POINTER_REQUIRED \
989 (current_function_has_nonlocal_label \
990 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
992 /* Return number of consecutive hard regs needed starting at reg REGNO
993 to hold something of mode MODE.
994 This is ordinarily the length in words of a value of mode MODE
995 but can be less for certain modes in special long registers.
997 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
999 #define HARD_REGNO_NREGS(REGNO, MODE) \
1001 && REGNO >= FIRST_ARM_FP_REGNUM \
1002 && REGNO != FRAME_POINTER_REGNUM \
1003 && REGNO != ARG_POINTER_REGNUM) \
1004 ? 1 : NUM_REGS (MODE))
1006 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1007 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1008 arm_hard_regno_mode_ok ((REGNO), (MODE))
1010 /* Value is 1 if it is a good idea to tie two pseudo registers
1011 when one has mode MODE1 and one has mode MODE2.
1012 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1013 for any hard reg, then this must be 0 for correct output. */
1014 #define MODES_TIEABLE_P(MODE1, MODE2) \
1015 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1017 /* The order in which register should be allocated. It is good to use ip
1018 since no saving is required (though calls clobber it) and it never contains
1019 function parameters. It is quite good to use lr since other calls may
1020 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1021 least likely to contain a function parameter; in addition results are
1023 #define REG_ALLOC_ORDER \
1025 3, 2, 1, 0, 12, 14, 4, 5, \
1026 6, 7, 8, 10, 9, 11, 13, 15, \
1027 16, 17, 18, 19, 20, 21, 22, 23, \
1031 /* Interrupt functions can only use registers that have already been
1032 saved by the prologue, even if they would normally be
1034 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1035 (! IS_INTERRUPT (cfun->machine->func_type) || \
1036 regs_ever_live[DST])
1038 /* Register and constant classes. */
1040 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1041 Now that the Thumb is involved it has become more complicated. */
1056 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1058 /* Give names of register classes as strings for dump file. */
1059 #define REG_CLASS_NAMES \
1072 /* Define which registers fit in which classes.
1073 This is an initializer for a vector of HARD_REG_SET
1074 of length N_REG_CLASSES. */
1075 #define REG_CLASS_CONTENTS \
1077 { 0x0000000 }, /* NO_REGS */ \
1078 { 0x0FF0000 }, /* FPU_REGS */ \
1079 { 0x00000FF }, /* LO_REGS */ \
1080 { 0x0002000 }, /* STACK_REG */ \
1081 { 0x00020FF }, /* BASE_REGS */ \
1082 { 0x000FF00 }, /* HI_REGS */ \
1083 { 0x1000000 }, /* CC_REG */ \
1084 { 0x200FFFF }, /* GENERAL_REGS */ \
1085 { 0x2FFFFFF } /* ALL_REGS */ \
1088 /* The same information, inverted:
1089 Return the class number of the smallest class containing
1090 reg number REGNO. This could be a conditional expression
1091 or could index an array. */
1092 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1094 /* The class value for index registers, and the one for base regs. */
1095 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1096 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1098 /* For the Thumb the high registers cannot be used as base
1099 registers when addressing quanitities in QI or HI mode. */
1100 #define MODE_BASE_REG_CLASS(MODE) \
1101 (TARGET_ARM ? BASE_REGS : \
1102 (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \
1103 ? LO_REGS : BASE_REGS))
1105 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1106 registers explicitly used in the rtl to be used as spill registers
1107 but prevents the compiler from extending the lifetime of these
1109 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1111 /* Get reg_class from a letter such as appears in the machine description.
1112 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1113 ARM, but several more letters for the Thumb. */
1114 #define REG_CLASS_FROM_LETTER(C) \
1115 ( (C) == 'f' ? FPU_REGS \
1116 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1117 : TARGET_ARM ? NO_REGS \
1118 : (C) == 'h' ? HI_REGS \
1119 : (C) == 'b' ? BASE_REGS \
1120 : (C) == 'k' ? STACK_REG \
1121 : (C) == 'c' ? CC_REG \
1124 /* The letters I, J, K, L and M in a register constraint string
1125 can be used to stand for particular ranges of immediate operands.
1126 This macro defines what the ranges are.
1127 C is the letter, and VALUE is a constant value.
1128 Return 1 if VALUE is in the range specified by C.
1129 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1130 J: valid indexing constants.
1131 K: ~value ok in rhs argument of data operand.
1132 L: -value ok in rhs argument of data operand.
1133 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1134 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1135 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1136 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1137 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1138 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1139 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1140 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1143 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1144 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1145 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1146 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1147 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1148 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1149 && ((VAL) & 3) == 0) : \
1150 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1151 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1154 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1156 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1158 /* Constant letter 'G' for the FPU immediate constants.
1159 'H' means the same constant negated. */
1160 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1161 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1162 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1164 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1166 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1168 /* For the ARM, `Q' means that this is a memory operand that is just
1169 an offset from a register.
1170 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1171 address. This means that the symbol is in the text segment and can be
1172 accessed without using a load. */
1174 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1175 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1176 (C) == 'R' ? (GET_CODE (OP) == MEM \
1177 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1178 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1179 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1182 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1183 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1184 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1186 #define EXTRA_CONSTRAINT(X, C) \
1188 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1190 /* Given an rtx X being reloaded into a reg required to be
1191 in class CLASS, return the class of reg to actually use.
1192 In general this is just CLASS, but for the Thumb we prefer
1193 a LO_REGS class or a subset. */
1194 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1195 (TARGET_ARM ? (CLASS) : \
1196 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1198 /* Must leave BASE_REGS reloads alone */
1199 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1200 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1201 ? ((true_regnum (X) == -1 ? LO_REGS \
1202 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1206 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1207 ((CLASS) != LO_REGS \
1208 ? ((true_regnum (X) == -1 ? LO_REGS \
1209 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1213 /* Return the register class of a scratch register needed to copy IN into
1214 or out of a register in CLASS in MODE. If it can be done directly,
1215 NO_REGS is returned. */
1216 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1218 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1219 ? GENERAL_REGS : NO_REGS) \
1220 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1222 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1223 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1225 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1226 && (GET_CODE (X) == MEM \
1227 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1228 && true_regnum (X) == -1))) \
1229 ? GENERAL_REGS : NO_REGS) \
1230 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1232 /* Try a machine-dependent way of reloading an illegitimate address
1233 operand. If we find one, push the reload and jump to WIN. This
1234 macro is used in only one place: `find_reloads_address' in reload.c.
1236 For the ARM, we wish to handle large displacements off a base
1237 register by splitting the addend across a MOV and the mem insn.
1238 This can cut the number of reloads needed. */
1239 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1242 if (GET_CODE (X) == PLUS \
1243 && GET_CODE (XEXP (X, 0)) == REG \
1244 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1245 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1246 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1248 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1249 HOST_WIDE_INT low, high; \
1251 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1252 low = ((val & 0xf) ^ 0x8) - 0x8; \
1253 else if (MODE == SImode \
1254 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1255 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1256 /* Need to be careful, -4096 is not a valid offset. */ \
1257 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1258 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1259 /* Need to be careful, -256 is not a valid offset. */ \
1260 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1261 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1262 && TARGET_HARD_FLOAT) \
1263 /* Need to be careful, -1024 is not a valid offset. */ \
1264 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1268 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1269 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1270 - (unsigned HOST_WIDE_INT) 0x80000000); \
1271 /* Check for overflow or zero */ \
1272 if (low == 0 || high == 0 || (high + low != val)) \
1275 /* Reload the high part into a base reg; leave the low part \
1277 X = gen_rtx_PLUS (GET_MODE (X), \
1278 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1281 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1282 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1283 VOIDmode, 0, 0, OPNUM, TYPE); \
1289 /* ??? If an HImode FP+large_offset address is converted to an HImode
1290 SP+large_offset address, then reload won't know how to fix it. It sees
1291 only that SP isn't valid for HImode, and so reloads the SP into an index
1292 register, but the resulting address is still invalid because the offset
1293 is too big. We fix it here instead by reloading the entire address. */
1294 /* We could probably achieve better results by defining PROMOTE_MODE to help
1295 cope with the variances between the Thumb's signed and unsigned byte and
1296 halfword load instructions. */
1297 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1299 if (GET_CODE (X) == PLUS \
1300 && GET_MODE_SIZE (MODE) < 4 \
1301 && GET_CODE (XEXP (X, 0)) == REG \
1302 && XEXP (X, 0) == stack_pointer_rtx \
1303 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1304 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1308 push_reload (orig_X, NULL_RTX, &X, NULL, \
1309 MODE_BASE_REG_CLASS (MODE), \
1310 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1315 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1317 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1319 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1321 /* Return the maximum number of consecutive registers
1322 needed to represent mode MODE in a register of class CLASS.
1323 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1324 #define CLASS_MAX_NREGS(CLASS, MODE) \
1325 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1327 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1328 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1330 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1331 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1333 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1335 /* Stack layout; function entry, exit and calling. */
1337 /* Define this if pushing a word on the stack
1338 makes the stack pointer a smaller address. */
1339 #define STACK_GROWS_DOWNWARD 1
1341 /* Define this if the nominal address of the stack frame
1342 is at the high-address end of the local variables;
1343 that is, each additional local variable allocated
1344 goes at a more negative offset in the frame. */
1345 #define FRAME_GROWS_DOWNWARD 1
1347 /* Offset within stack frame to start allocating local variables at.
1348 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1349 first local allocated. Otherwise, it is the offset to the BEGINNING
1350 of the first local allocated. */
1351 #define STARTING_FRAME_OFFSET 0
1353 /* If we generate an insn to push BYTES bytes,
1354 this says how many the stack pointer really advances by. */
1355 /* The push insns do not do this rounding implicitly.
1356 So don't define this. */
1357 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1359 /* Define this if the maximum size of all the outgoing args is to be
1360 accumulated and pushed during the prologue. The amount can be
1361 found in the variable current_function_outgoing_args_size. */
1362 #define ACCUMULATE_OUTGOING_ARGS 1
1364 /* Offset of first parameter from the argument pointer register value. */
1365 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1367 /* Value is the number of byte of arguments automatically
1368 popped when returning from a subroutine call.
1369 FUNDECL is the declaration node of the function (as a tree),
1370 FUNTYPE is the data type of the function (as a tree),
1371 or for a library call it is an identifier node for the subroutine name.
1372 SIZE is the number of bytes of arguments passed on the stack.
1374 On the ARM, the caller does not pop any of its arguments that were passed
1376 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1378 /* Define how to find the value returned by a library function
1379 assuming the value has mode MODE. */
1380 #define LIBCALL_VALUE(MODE) \
1381 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1382 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1383 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1385 /* Define how to find the value returned by a function.
1386 VALTYPE is the data type of the value (as a tree).
1387 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1388 otherwise, FUNC is 0. */
1389 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1390 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1392 /* 1 if N is a possible register number for a function value.
1393 On the ARM, only r0 and f0 can return results. */
1394 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1395 ((REGNO) == ARG_REGISTER (1) \
1396 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1398 /* How large values are returned */
1399 /* A C expression which can inhibit the returning of certain function values
1400 in registers, based on the type of value. */
1401 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1403 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1404 values must be in memory. On the ARM, they need only do so if larger
1405 than a word, or if they contain elements offset from zero in the struct. */
1406 #define DEFAULT_PCC_STRUCT_RETURN 0
1408 /* Flags for the call/call_value rtl operations set up by function_arg. */
1409 #define CALL_NORMAL 0x00000000 /* No special processing. */
1410 #define CALL_LONG 0x00000001 /* Always call indirect. */
1411 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1413 /* These bits describe the different types of function supported
1414 by the ARM backend. They are exclusive. ie a function cannot be both a
1415 normal function and an interworked function, for example. Knowing the
1416 type of a function is important for determining its prologue and
1418 Note value 7 is currently unassigned. Also note that the interrupt
1419 function types all have bit 2 set, so that they can be tested for easily.
1420 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1421 machine_function structure is initialised (to zero) func_type will
1422 default to unknown. This will force the first use of arm_current_func_type
1423 to call arm_compute_func_type. */
1424 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1425 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1426 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1427 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1428 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1429 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1430 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1432 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1434 /* In addition functions can have several type modifiers,
1435 outlined by these bit masks: */
1436 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1437 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1438 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1439 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1441 /* Some macros to test these flags. */
1442 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1443 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1444 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1445 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1446 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1448 /* A C structure for machine-specific, per-function data.
1449 This is added to the cfun structure. */
1450 typedef struct machine_function
1452 /* Additionsl stack adjustment in __builtin_eh_throw. */
1453 struct rtx_def *eh_epilogue_sp_ofs;
1454 /* Records if LR has to be saved for far jumps. */
1456 /* Records if ARG_POINTER was ever live. */
1457 int arg_pointer_live;
1458 /* Records if the save of LR has been eliminated. */
1459 int lr_save_eliminated;
1460 /* Records the type of the current function. */
1461 unsigned long func_type;
1462 /* Record if the function has a variable argument list. */
1463 int uses_anonymous_args;
1467 /* A C type for declaring a variable that is used as the first argument of
1468 `FUNCTION_ARG' and other related values. For some target machines, the
1469 type `int' suffices and can hold the number of bytes of argument so far. */
1472 /* This is the number of registers of arguments scanned so far. */
1474 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1478 /* Define where to put the arguments to a function.
1479 Value is zero to push the argument on the stack,
1480 or a hard register in which to store the argument.
1482 MODE is the argument's machine mode.
1483 TYPE is the data type of the argument (as a tree).
1484 This is null for libcalls where that information may
1486 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1487 the preceding args and about the function being called.
1488 NAMED is nonzero if this argument is a named parameter
1489 (otherwise it is an extra parameter matching an ellipsis).
1491 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1492 other arguments are passed on the stack. If (NAMED == 0) (which happens
1493 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1494 passed in the stack (function_prologue will indeed make it pass in the
1495 stack if necessary). */
1496 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1497 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1499 /* For an arg passed partly in registers and partly in memory,
1500 this is the number of registers used.
1501 For args passed entirely in registers or entirely in memory, zero. */
1502 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1503 ( NUM_ARG_REGS > (CUM).nregs \
1504 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1505 ? NUM_ARG_REGS - (CUM).nregs : 0)
1507 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1508 for a call to a function whose data type is FNTYPE.
1509 For a library call, FNTYPE is 0.
1510 On the ARM, the offset starts at 0. */
1511 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1512 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1514 /* Update the data in CUM to advance over an argument
1515 of mode MODE and data type TYPE.
1516 (TYPE is null for libcalls where that information may not be available.) */
1517 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1518 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1520 /* 1 if N is a possible register number for function argument passing.
1521 On the ARM, r0-r3 are used to pass args. */
1522 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1527 /* A C expression that evaluates to true if it is ok to perform a sibling
1529 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1531 /* Perform any actions needed for a function that is receiving a variable
1532 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1533 of the current parameter. PRETEND_SIZE is a variable that should be set to
1534 the amount of stack that must be pushed by the prolog to pretend that our
1537 Normally, this macro will push all remaining incoming registers on the
1538 stack and set PRETEND_SIZE to the length of the registers pushed.
1540 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1541 named arg and all anonymous args onto the stack.
1542 XXX I know the prologue shouldn't be pushing registers, but it is faster
1544 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1546 cfun->machine->uses_anonymous_args = 1; \
1547 if ((CUM).nregs < NUM_ARG_REGS) \
1548 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1551 /* If your target environment doesn't prefix user functions with an
1552 underscore, you may wish to re-define this to prevent any conflicts.
1553 e.g. AOF may prefix mcount with an underscore. */
1554 #ifndef ARM_MCOUNT_NAME
1555 #define ARM_MCOUNT_NAME "*mcount"
1558 /* Call the function profiler with a given profile label. The Acorn
1559 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1560 On the ARM the full profile code will look like:
1569 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1570 will output the .text section.
1572 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1573 ``prof'' doesn't seem to mind about this! */
1574 #ifndef ARM_FUNCTION_PROFILER
1575 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1580 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1581 IP_REGNUM, LR_REGNUM); \
1582 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1583 fputc ('\n', STREAM); \
1584 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1585 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1586 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1590 #ifndef THUMB_FUNCTION_PROFILER
1591 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1593 fprintf (STREAM, "\tmov\tip, lr\n"); \
1594 fprintf (STREAM, "\tbl\tmcount\n"); \
1595 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1599 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1601 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1603 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1605 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1606 the stack pointer does not matter. The value is tested only in
1607 functions that have frame pointers.
1608 No definition is equivalent to always zero.
1610 On the ARM, the function epilogue recovers the stack pointer from the
1612 #define EXIT_IGNORE_STACK 1
1614 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1616 /* Determine if the epilogue should be output as RTL.
1617 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1618 #define USE_RETURN_INSN(ISCOND) \
1619 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1621 /* Definitions for register eliminations.
1623 This is an array of structures. Each structure initializes one pair
1624 of eliminable registers. The "from" register number is given first,
1625 followed by "to". Eliminations of the same "from" register are listed
1626 in order of preference.
1628 We have two registers that can be eliminated on the ARM. First, the
1629 arg pointer register can often be eliminated in favor of the stack
1630 pointer register. Secondly, the pseudo frame pointer register can always
1631 be eliminated; it is replaced with either the stack or the real frame
1632 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1633 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1635 #define ELIMINABLE_REGS \
1636 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1637 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1638 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1639 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1640 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1641 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1642 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1644 /* Given FROM and TO register numbers, say whether this elimination is
1645 allowed. Frame pointer elimination is automatically handled.
1647 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1648 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1649 pointer, we must eliminate FRAME_POINTER_REGNUM into
1650 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1651 ARG_POINTER_REGNUM. */
1652 #define CAN_ELIMINATE(FROM, TO) \
1653 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1654 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1655 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1656 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1659 /* Define the offset between two registers, one to be eliminated, and the
1660 other its replacement, at the start of a routine. */
1661 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1664 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1668 /* Note: This macro must match the code in thumb_function_prologue(). */
1669 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1672 if ((FROM) == ARG_POINTER_REGNUM) \
1674 int count_regs = 0; \
1676 for (regno = 8; regno < 13; regno ++) \
1677 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1680 (OFFSET) += 4 * count_regs; \
1682 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1683 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1685 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1686 (OFFSET) += 4 * (count_regs + 1); \
1687 if (TARGET_BACKTRACE) \
1689 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1695 if ((TO) == STACK_POINTER_REGNUM) \
1697 (OFFSET) += current_function_outgoing_args_size; \
1698 (OFFSET) += ROUND_UP (get_frame_size ()); \
1702 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1704 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1706 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1708 /* Special case handling of the location of arguments passed on the stack. */
1709 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1711 /* Initialize data used by insn expanders. This is called from insn_emit,
1712 once for every function before code is generated. */
1713 #define INIT_EXPANDERS arm_init_expanders ()
1715 /* Output assembler code for a block containing the constant parts
1716 of a trampoline, leaving space for the variable parts.
1718 On the ARM, (if r8 is the static chain regnum, and remembering that
1719 referencing pc adds an offset of 8) the trampoline looks like:
1722 .word static chain value
1723 .word function's address
1724 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1725 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1727 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1728 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1729 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1730 PC_REGNUM, PC_REGNUM); \
1731 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1732 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1735 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1736 Why - because it is easier. This code will always be branched to via
1737 a BX instruction and since the compiler magically generates the address
1738 of the function the linker has no opportunity to ensure that the
1739 bottom bit is set. Thus the processor will be in ARM mode when it
1740 reaches this code. So we duplicate the ARM trampoline code and add
1741 a switch into Thumb mode as well. */
1742 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1744 fprintf (FILE, "\t.code 32\n"); \
1745 fprintf (FILE, ".Ltrampoline_start:\n"); \
1746 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1747 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1748 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1749 IP_REGNUM, PC_REGNUM); \
1750 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1751 IP_REGNUM, IP_REGNUM); \
1752 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1753 fprintf (FILE, "\t.word\t0\n"); \
1754 fprintf (FILE, "\t.word\t0\n"); \
1755 fprintf (FILE, "\t.code 16\n"); \
1758 #define TRAMPOLINE_TEMPLATE(FILE) \
1760 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1762 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1764 /* Length in units of the trampoline for entering a nested function. */
1765 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1767 /* Alignment required for a trampoline in bits. */
1768 #define TRAMPOLINE_ALIGNMENT 32
1770 /* Emit RTL insns to initialize the variable parts of a trampoline.
1771 FNADDR is an RTX for the address of the function's pure code.
1772 CXT is an RTX for the static chain value for the function. */
1773 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1776 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1778 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1782 /* Addressing modes, and classification of registers for them. */
1783 #define HAVE_POST_INCREMENT 1
1784 #define HAVE_PRE_INCREMENT TARGET_ARM
1785 #define HAVE_POST_DECREMENT TARGET_ARM
1786 #define HAVE_PRE_DECREMENT TARGET_ARM
1788 /* Macros to check register numbers against specific register classes. */
1790 /* These assume that REGNO is a hard or pseudo reg number.
1791 They give nonzero only if REGNO is a hard reg of the suitable class
1792 or a pseudo reg currently allocated to a suitable hard reg.
1793 Since they use reg_renumber, they are safe only once reg_renumber
1794 has been allocated, which happens in local-alloc.c. */
1795 #define TEST_REGNO(R, TEST, VALUE) \
1796 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1798 /* On the ARM, don't allow the pc to be used. */
1799 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1800 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1801 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1802 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1804 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1805 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1806 || (GET_MODE_SIZE (MODE) >= 4 \
1807 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1809 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1811 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1812 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1814 /* For ARM code, we don't care about the mode, but for Thumb, the index
1815 must be suitable for use in a QImode load. */
1816 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1817 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1819 /* Maximum number of registers that can appear in a valid memory address.
1820 Shifts in addresses can't be by a register. */
1821 #define MAX_REGS_PER_ADDRESS 2
1823 /* Recognize any constant value that is a valid address. */
1824 /* XXX We can address any constant, eventually... */
1826 #ifdef AOF_ASSEMBLER
1828 #define CONSTANT_ADDRESS_P(X) \
1829 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1833 #define CONSTANT_ADDRESS_P(X) \
1834 (GET_CODE (X) == SYMBOL_REF \
1835 && (CONSTANT_POOL_ADDRESS_P (X) \
1836 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1838 #endif /* AOF_ASSEMBLER */
1840 /* Nonzero if the constant value X is a legitimate general operand.
1841 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1843 On the ARM, allow any integer (invalid ones are removed later by insn
1844 patterns), nice doubles and symbol_refs which refer to the function's
1847 When generating pic allow anything. */
1848 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1850 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1851 ( GET_CODE (X) == CONST_INT \
1852 || GET_CODE (X) == CONST_DOUBLE \
1853 || CONSTANT_ADDRESS_P (X) \
1856 #define LEGITIMATE_CONSTANT_P(X) \
1857 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1859 /* Special characters prefixed to function names
1860 in order to encode attribute like information.
1861 Note, '@' and '*' have already been taken. */
1862 #define SHORT_CALL_FLAG_CHAR '^'
1863 #define LONG_CALL_FLAG_CHAR '#'
1865 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1866 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1868 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1869 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1871 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1872 #define SUBTARGET_NAME_ENCODING_LENGTHS
1875 /* This is a C fragement for the inside of a switch statement.
1876 Each case label should return the number of characters to
1877 be stripped from the start of a function's name, if that
1878 name starts with the indicated character. */
1879 #define ARM_NAME_ENCODING_LENGTHS \
1880 case SHORT_CALL_FLAG_CHAR: return 1; \
1881 case LONG_CALL_FLAG_CHAR: return 1; \
1882 case '*': return 1; \
1883 SUBTARGET_NAME_ENCODING_LENGTHS
1885 /* This has to be handled by a function because more than part of the
1886 ARM backend uses function name prefixes to encode attributes. */
1887 #undef STRIP_NAME_ENCODING
1888 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1889 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1891 /* This is how to output a reference to a user-level label named NAME.
1892 `assemble_name' uses this. */
1893 #undef ASM_OUTPUT_LABELREF
1894 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1895 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1897 /* If we are referencing a function that is weak then encode a long call
1898 flag in the function name, otherwise if the function is static or
1899 or known to be defined in this file then encode a short call flag.
1900 This macro is used inside the ENCODE_SECTION macro. */
1901 #define ARM_ENCODE_CALL_TYPE(decl) \
1902 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd') \
1904 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) \
1905 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1906 else if (! TREE_PUBLIC (decl)) \
1907 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1910 /* Symbols in the text segment can be accessed without indirecting via the
1911 constant pool; it may take an extra binary operation, but this is still
1912 faster than indirecting via memory. Don't do this when not optimizing,
1913 since we won't be calculating al of the offsets necessary to do this
1915 /* This doesn't work with AOF syntax, since the string table may be in
1916 a different AREA. */
1917 #ifndef AOF_ASSEMBLER
1918 #define ENCODE_SECTION_INFO(decl) \
1920 if (optimize > 0 && TREE_CONSTANT (decl) \
1921 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1923 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1924 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1925 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1927 ARM_ENCODE_CALL_TYPE (decl) \
1930 #define ENCODE_SECTION_INFO(decl) \
1932 ARM_ENCODE_CALL_TYPE (decl) \
1936 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1937 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1939 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1940 and check its validity for a certain class.
1941 We have two alternate definitions for each of them.
1942 The usual definition accepts all pseudo regs; the other rejects
1943 them unless they have been allocated suitable hard regs.
1944 The symbol REG_OK_STRICT causes the latter definition to be used. */
1945 #ifndef REG_OK_STRICT
1947 #define ARM_REG_OK_FOR_BASE_P(X) \
1948 (REGNO (X) <= LAST_ARM_REGNUM \
1949 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1950 || REGNO (X) == FRAME_POINTER_REGNUM \
1951 || REGNO (X) == ARG_POINTER_REGNUM)
1953 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1954 (REGNO (X) <= LAST_LO_REGNUM \
1955 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1956 || (GET_MODE_SIZE (MODE) >= 4 \
1957 && (REGNO (X) == STACK_POINTER_REGNUM \
1958 || (X) == hard_frame_pointer_rtx \
1959 || (X) == arg_pointer_rtx)))
1961 #else /* REG_OK_STRICT */
1963 #define ARM_REG_OK_FOR_BASE_P(X) \
1964 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1966 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1967 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1969 #endif /* REG_OK_STRICT */
1971 /* Now define some helpers in terms of the above. */
1973 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1975 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1976 : ARM_REG_OK_FOR_BASE_P (X))
1978 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1980 /* For Thumb, a valid index register is anything that can be used in
1981 a byte load instruction. */
1982 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1984 /* Nonzero if X is a hard reg that can be used as an index
1985 or if it is a pseudo reg. On the Thumb, the stack pointer
1987 #define REG_OK_FOR_INDEX_P(X) \
1989 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1990 : ARM_REG_OK_FOR_INDEX_P (X))
1993 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1994 that is a valid memory address for an instruction.
1995 The MODE argument is the machine mode for the MEM expression
1996 that wants to use this address.
1998 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
2000 /* --------------------------------arm version----------------------------- */
2001 #define ARM_BASE_REGISTER_RTX_P(X) \
2002 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2004 #define ARM_INDEX_REGISTER_RTX_P(X) \
2005 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2007 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2008 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2009 only be small constants. */
2010 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2013 HOST_WIDE_INT range; \
2014 enum rtx_code code = GET_CODE (INDEX); \
2016 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2018 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2019 && INTVAL (INDEX) > -1024 \
2020 && (INTVAL (INDEX) & 3) == 0) \
2025 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2026 && GET_MODE_SIZE (MODE) <= 4) \
2028 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2029 && (! arm_arch4 || (MODE) != HImode)) \
2031 rtx xiop0 = XEXP (INDEX, 0); \
2032 rtx xiop1 = XEXP (INDEX, 1); \
2033 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2034 && power_of_two_operand (xiop1, SImode)) \
2036 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2037 && power_of_two_operand (xiop0, SImode)) \
2040 if (GET_MODE_SIZE (MODE) <= 4 \
2041 && (code == LSHIFTRT || code == ASHIFTRT \
2042 || code == ASHIFT || code == ROTATERT) \
2043 && (! arm_arch4 || (MODE) != HImode)) \
2045 rtx op = XEXP (INDEX, 1); \
2046 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2047 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2048 && INTVAL (op) <= 31) \
2051 /* NASTY: Since this limits the addressing of unsigned \
2053 range = ((MODE) == HImode || (MODE) == QImode) \
2054 ? (arm_arch4 ? 256 : 4095) : 4096; \
2055 if (code == CONST_INT && INTVAL (INDEX) < range \
2056 && INTVAL (INDEX) > -range) \
2062 /* Jump to LABEL if X is a valid address RTX. This must take
2063 REG_OK_STRICT into account when deciding about valid registers.
2065 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2066 floating SYMBOL_REF to the constant pool. Allow REG-only and
2067 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2068 forced though a static cell to ensure addressability. */
2069 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2071 if (ARM_BASE_REGISTER_RTX_P (X)) \
2073 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2074 && GET_CODE (XEXP (X, 0)) == REG \
2075 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2077 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2078 && (GET_CODE (X) == LABEL_REF \
2079 || (GET_CODE (X) == CONST \
2080 && GET_CODE (XEXP ((X), 0)) == PLUS \
2081 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2082 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2084 else if ((MODE) == TImode) \
2086 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2088 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2089 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2091 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2092 if (val == 4 || val == -4 || val == -8) \
2096 else if (GET_CODE (X) == PLUS) \
2098 rtx xop0 = XEXP (X, 0); \
2099 rtx xop1 = XEXP (X, 1); \
2101 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2102 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2103 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2104 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2106 /* Reload currently can't handle MINUS, so disable this for now */ \
2107 /* else if (GET_CODE (X) == MINUS) \
2109 rtx xop0 = XEXP (X,0); \
2110 rtx xop1 = XEXP (X,1); \
2112 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2113 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2115 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2116 && GET_CODE (X) == SYMBOL_REF \
2117 && CONSTANT_POOL_ADDRESS_P (X) \
2119 && symbol_mentioned_p (get_pool_constant (X)))) \
2121 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2122 && (GET_MODE_SIZE (MODE) <= 4) \
2123 && GET_CODE (XEXP (X, 0)) == REG \
2124 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2128 /* ---------------------thumb version----------------------------------*/
2129 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2130 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2131 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2132 && ((VAL) & 1) == 0) \
2133 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2134 && ((VAL) & 3) == 0))
2136 /* The AP may be eliminated to either the SP or the FP, so we use the
2137 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2139 /* ??? Verify whether the above is the right approach. */
2141 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2142 needs special handling also. */
2144 /* ??? Look at how the mips16 port solves this problem. It probably uses
2145 better ways to solve some of these problems. */
2147 /* Although it is not incorrect, we don't accept QImode and HImode
2148 addresses based on the frame pointer or arg pointer until the
2149 reload pass starts. This is so that eliminating such addresses
2150 into stack based ones won't produce impossible code. */
2151 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2153 /* ??? Not clear if this is right. Experiment. */ \
2154 if (GET_MODE_SIZE (MODE) < 4 \
2155 && ! (reload_in_progress || reload_completed) \
2156 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2157 || reg_mentioned_p (arg_pointer_rtx, X) \
2158 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2159 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2160 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2161 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2163 /* Accept any base register. SP only in SImode or larger. */ \
2164 else if (GET_CODE (X) == REG \
2165 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2167 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2168 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2169 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2171 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2172 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2173 && (GET_CODE (X) == LABEL_REF \
2174 || (GET_CODE (X) == CONST \
2175 && GET_CODE (XEXP (X, 0)) == PLUS \
2176 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2177 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2179 /* Post-inc indexing only supported for SImode and larger. */ \
2180 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2181 && GET_CODE (XEXP (X, 0)) == REG \
2182 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2184 else if (GET_CODE (X) == PLUS) \
2186 /* REG+REG address can be any two index registers. */ \
2187 /* We disallow FRAME+REG addressing since we know that FRAME \
2188 will be replaced with STACK, and SP relative addressing only \
2189 permits SP+OFFSET. */ \
2190 if (GET_MODE_SIZE (MODE) <= 4 \
2191 && GET_CODE (XEXP (X, 0)) == REG \
2192 && GET_CODE (XEXP (X, 1)) == REG \
2193 && XEXP (X, 0) != frame_pointer_rtx \
2194 && XEXP (X, 1) != frame_pointer_rtx \
2195 && XEXP (X, 0) != virtual_stack_vars_rtx \
2196 && XEXP (X, 1) != virtual_stack_vars_rtx \
2197 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2198 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2200 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2201 else if (GET_CODE (XEXP (X, 0)) == REG \
2202 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2203 || XEXP (X, 0) == arg_pointer_rtx) \
2204 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2205 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2207 /* REG+const has 10 bit offset for SP, but only SImode and \
2208 larger is supported. */ \
2209 /* ??? Should probably check for DI/DFmode overflow here \
2210 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2211 else if (GET_CODE (XEXP (X, 0)) == REG \
2212 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2213 && GET_MODE_SIZE (MODE) >= 4 \
2214 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2215 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2216 + GET_MODE_SIZE (MODE)) <= 1024 \
2217 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2219 else if (GET_CODE (XEXP (X, 0)) == REG \
2220 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2221 && GET_MODE_SIZE (MODE) >= 4 \
2222 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2223 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2226 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2227 && GET_CODE (X) == SYMBOL_REF \
2228 && CONSTANT_POOL_ADDRESS_P (X) \
2230 && symbol_mentioned_p (get_pool_constant (X)))) \
2234 /* ------------------------------------------------------------------- */
2235 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2237 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2238 else /* if (TARGET_THUMB) */ \
2239 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2240 /* ------------------------------------------------------------------- */
2242 /* Try machine-dependent ways of modifying an illegitimate address
2243 to be legitimate. If we find one, return the new, valid address.
2244 This macro is used in only one place: `memory_address' in explow.c.
2246 OLDX is the address as it was before break_out_memory_refs was called.
2247 In some cases it is useful to look at this to decide what needs to be done.
2249 MODE and WIN are passed so that this macro can use
2250 GO_IF_LEGITIMATE_ADDRESS.
2252 It is always safe for this macro to do nothing. It exists to recognize
2253 opportunities to optimize the output.
2255 On the ARM, try to convert [REG, #BIGCONST]
2256 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2257 where VALIDCONST == 0 in case of TImode. */
2258 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2260 if (GET_CODE (X) == PLUS) \
2262 rtx xop0 = XEXP (X, 0); \
2263 rtx xop1 = XEXP (X, 1); \
2265 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2266 xop0 = force_reg (SImode, xop0); \
2267 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2268 xop1 = force_reg (SImode, xop1); \
2269 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2270 && GET_CODE (xop1) == CONST_INT) \
2272 HOST_WIDE_INT n, low_n; \
2273 rtx base_reg, val; \
2274 n = INTVAL (xop1); \
2276 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2288 low_n = ((MODE) == TImode ? 0 \
2289 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2292 base_reg = gen_reg_rtx (SImode); \
2293 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2294 GEN_INT (n)), NULL_RTX); \
2295 emit_move_insn (base_reg, val); \
2296 (X) = (low_n == 0 ? base_reg \
2297 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2299 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2300 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2302 else if (GET_CODE (X) == MINUS) \
2304 rtx xop0 = XEXP (X, 0); \
2305 rtx xop1 = XEXP (X, 1); \
2307 if (CONSTANT_P (xop0)) \
2308 xop0 = force_reg (SImode, xop0); \
2309 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2310 xop1 = force_reg (SImode, xop1); \
2311 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2312 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2315 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2316 if (memory_address_p (MODE, X)) \
2320 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2322 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2324 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2326 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2328 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2330 /* Go to LABEL if ADDR (a legitimate address expression)
2331 has an effect that depends on the machine mode it is used for. */
2332 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2334 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2335 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2339 /* Nothing helpful to do for the Thumb */
2340 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2342 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2345 /* Specify the machine mode that this machine uses
2346 for the index in the tablejump instruction. */
2347 #define CASE_VECTOR_MODE Pmode
2349 /* Define as C expression which evaluates to nonzero if the tablejump
2350 instruction expects the table to contain offsets from the address of the
2352 Do not define this if the table should contain absolute addresses. */
2353 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2355 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2356 unsigned is probably best, but may break some code. */
2357 #ifndef DEFAULT_SIGNED_CHAR
2358 #define DEFAULT_SIGNED_CHAR 0
2361 /* Don't cse the address of the function being compiled. */
2362 #define NO_RECURSIVE_FUNCTION_CSE 1
2364 /* Max number of bytes we can move from memory to memory
2365 in one reasonably fast instruction. */
2369 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2371 /* Define if operations between registers always perform the operation
2372 on the full register even if a narrower mode is specified. */
2373 #define WORD_REGISTER_OPERATIONS
2375 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2376 will either zero-extend or sign-extend. The value of this macro should
2377 be the code that says which one of the two operations is implicitly
2378 done, NIL if none. */
2379 #define LOAD_EXTEND_OP(MODE) \
2380 (TARGET_THUMB ? ZERO_EXTEND : \
2381 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2382 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2384 /* Nonzero if access to memory by bytes is slow and undesirable. */
2385 #define SLOW_BYTE_ACCESS 0
2387 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2389 /* Immediate shift counts are truncated by the output routines (or was it
2390 the assembler?). Shift counts in a register are truncated by ARM. Note
2391 that the native compiler puts too large (> 32) immediate shift counts
2392 into a register and shifts by the register, letting the ARM decide what
2393 to do instead of doing that itself. */
2394 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2395 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2396 On the arm, Y in a register is used modulo 256 for the shift. Only for
2397 rotates is modulo 32 used. */
2398 /* #define SHIFT_COUNT_TRUNCATED 1 */
2400 /* All integers have the same format so truncation is easy. */
2401 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2403 /* Calling from registers is a massive pain. */
2404 #define NO_FUNCTION_CSE 1
2406 /* Chars and shorts should be passed as ints. */
2407 #define PROMOTE_PROTOTYPES 1
2409 /* The machine modes of pointers and functions */
2410 #define Pmode SImode
2411 #define FUNCTION_MODE Pmode
2413 #define ARM_FRAME_RTX(X) \
2414 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2415 || (X) == arg_pointer_rtx)
2417 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2418 return arm_rtx_costs (X, CODE, OUTER_CODE);
2420 /* Moves to and from memory are quite expensive */
2421 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2422 (TARGET_ARM ? 10 : \
2423 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2424 * (CLASS == LO_REGS ? 1 : 2)))
2426 /* All address computations that can be done are free, but rtx cost returns
2427 the same for practically all of them. So we weight the different types
2428 of address here in the order (most pref first):
2429 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2430 #define ARM_ADDRESS_COST(X) \
2431 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2432 || GET_CODE (X) == SYMBOL_REF) \
2434 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2435 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2437 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2438 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2439 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2440 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2441 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2442 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2446 #define THUMB_ADDRESS_COST(X) \
2447 ((GET_CODE (X) == REG \
2448 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2449 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2452 #define ADDRESS_COST(X) \
2453 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2455 /* Try to generate sequences that don't involve branches, we can then use
2456 conditional instructions */
2457 #define BRANCH_COST \
2458 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2460 /* Position Independent Code. */
2461 /* We decide which register to use based on the compilation options and
2462 the assembler in use; this is more general than the APCS restriction of
2463 using sb (r9) all the time. */
2464 extern int arm_pic_register;
2466 /* Used when parsing command line option -mpic-register=. */
2467 extern const char * arm_pic_register_string;
2469 /* The register number of the register used to address a table of static
2470 data addresses in memory. */
2471 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2473 #define FINALIZE_PIC arm_finalize_pic (1)
2475 /* We can't directly access anything that contains a symbol,
2476 nor can we indirect via the constant pool. */
2477 #define LEGITIMATE_PIC_OPERAND_P(X) \
2478 ( ! symbol_mentioned_p (X) \
2479 && ! label_mentioned_p (X) \
2480 && (! CONSTANT_POOL_ADDRESS_P (X) \
2481 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2482 && ! label_mentioned_p (get_pool_constant (X)))))
2484 /* We need to know when we are making a constant pool; this determines
2485 whether data needs to be in the GOT or can be referenced via a GOT
2487 extern int making_const_table;
2489 /* Handle pragmas for compatibility with Intel's compilers. */
2490 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2491 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2492 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2493 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2496 /* Condition code information. */
2497 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2498 return the mode to be used for the comparison.
2499 CCFPEmode should be used with floating inequalities,
2500 CCFPmode should be used with floating equalities.
2501 CC_NOOVmode should be used with SImode integer equalities.
2502 CC_Zmode should be used if only the Z flag is set correctly
2503 CCmode should be used otherwise. */
2505 #define EXTRA_CC_MODES \
2506 CC(CC_NOOVmode, "CC_NOOV") \
2507 CC(CC_Zmode, "CC_Z") \
2508 CC(CC_SWPmode, "CC_SWP") \
2509 CC(CCFPmode, "CCFP") \
2510 CC(CCFPEmode, "CCFPE") \
2511 CC(CC_DNEmode, "CC_DNE") \
2512 CC(CC_DEQmode, "CC_DEQ") \
2513 CC(CC_DLEmode, "CC_DLE") \
2514 CC(CC_DLTmode, "CC_DLT") \
2515 CC(CC_DGEmode, "CC_DGE") \
2516 CC(CC_DGTmode, "CC_DGT") \
2517 CC(CC_DLEUmode, "CC_DLEU") \
2518 CC(CC_DLTUmode, "CC_DLTU") \
2519 CC(CC_DGEUmode, "CC_DGEU") \
2520 CC(CC_DGTUmode, "CC_DGTU") \
2521 CC(CC_Cmode, "CC_C")
2523 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2525 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2527 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2530 if (GET_CODE (OP1) == CONST_INT \
2531 && ! (const_ok_for_arm (INTVAL (OP1)) \
2532 || (const_ok_for_arm (- INTVAL (OP1))))) \
2534 rtx const_op = OP1; \
2535 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2541 #define STORE_FLAG_VALUE 1
2545 /* Gcc puts the pool in the wrong place for ARM, since we can only
2546 load addresses a limited distance around the pc. We do some
2547 special munging to move the constant pool values to the correct
2548 point in the code. */
2549 #define MACHINE_DEPENDENT_REORG(INSN) \
2553 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2555 /* Output an internal label definition. */
2556 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2557 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2560 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2562 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2563 && !strcmp (PREFIX, "L")) \
2565 arm_ccfsm_state = 0; \
2566 arm_target_insn = NULL; \
2568 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2569 ASM_OUTPUT_LABEL (STREAM, s); \
2574 /* Output a push or a pop instruction (only used when profiling). */
2575 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2577 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2578 STACK_POINTER_REGNUM, REGNO); \
2580 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2583 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2585 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2586 STACK_POINTER_REGNUM, REGNO); \
2588 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2590 /* This is how to output a label which precedes a jumptable. Since
2591 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2592 #undef ASM_OUTPUT_CASE_LABEL
2593 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2597 ASM_OUTPUT_ALIGN (FILE, 2); \
2598 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2602 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2607 if (is_called_in_ARM_mode (DECL)) \
2608 fprintf (STREAM, "\t.code 32\n") ; \
2610 fprintf (STREAM, "\t.thumb_func\n") ; \
2612 if (TARGET_POKE_FUNCTION_NAME) \
2613 arm_poke_function_name (STREAM, (char *) NAME); \
2617 /* For aliases of functions we use .thumb_set instead. */
2618 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2621 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2622 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2624 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2626 fprintf (FILE, "\t.thumb_set "); \
2627 assemble_name (FILE, LABEL1); \
2628 fprintf (FILE, ","); \
2629 assemble_name (FILE, LABEL2); \
2630 fprintf (FILE, "\n"); \
2633 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2637 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2638 /* To support -falign-* switches we need to use .p2align so
2639 that alignment directives in code sections will be padded
2640 with no-op instructions, rather than zeroes. */
2641 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2644 if ((MAX_SKIP) == 0) \
2645 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2647 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2648 (LOG), (MAX_SKIP)); \
2652 /* Only perform branch elimination (by making instructions conditional) if
2653 we're optimising. Otherwise it's of no use anyway. */
2654 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2655 if (TARGET_ARM && optimize) \
2656 arm_final_prescan_insn (INSN); \
2657 else if (TARGET_THUMB) \
2658 thumb_final_prescan_insn (INSN)
2660 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2661 (CODE == '@' || CODE == '|' \
2662 || (TARGET_ARM && (CODE == '?')) \
2663 || (TARGET_THUMB && (CODE == '_')))
2665 /* Output an operand of an instruction. */
2666 #define PRINT_OPERAND(STREAM, X, CODE) \
2667 arm_print_operand (STREAM, X, CODE)
2669 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2670 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2671 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2672 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2673 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2674 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2677 /* Output the address of an operand. */
2678 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2680 int is_minus = GET_CODE (X) == MINUS; \
2682 if (GET_CODE (X) == REG) \
2683 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2684 else if (GET_CODE (X) == PLUS || is_minus) \
2686 rtx base = XEXP (X, 0); \
2687 rtx index = XEXP (X, 1); \
2688 HOST_WIDE_INT offset = 0; \
2689 if (GET_CODE (base) != REG) \
2691 /* Ensure that BASE is a register */ \
2692 /* (one of them must be). */ \
2697 switch (GET_CODE (index)) \
2700 offset = INTVAL (index); \
2703 asm_fprintf (STREAM, "[%r, #%d]", \
2704 REGNO (base), offset); \
2708 asm_fprintf (STREAM, "[%r, %s%r]", \
2709 REGNO (base), is_minus ? "-" : "", \
2719 asm_fprintf (STREAM, "[%r, %s%r", \
2720 REGNO (base), is_minus ? "-" : "", \
2721 REGNO (XEXP (index, 0))); \
2722 arm_print_operand (STREAM, index, 'S'); \
2723 fputs ("]", STREAM); \
2731 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2732 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2734 extern int output_memory_reference_mode; \
2736 if (GET_CODE (XEXP (X, 0)) != REG) \
2739 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2740 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2741 REGNO (XEXP (X, 0)), \
2742 GET_CODE (X) == PRE_DEC ? "-" : "", \
2743 GET_MODE_SIZE (output_memory_reference_mode));\
2745 asm_fprintf (STREAM, "[%r], #%s%d", \
2746 REGNO (XEXP (X, 0)), \
2747 GET_CODE (X) == POST_DEC ? "-" : "", \
2748 GET_MODE_SIZE (output_memory_reference_mode));\
2750 else output_addr_const (STREAM, X); \
2753 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2755 if (GET_CODE (X) == REG) \
2756 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2757 else if (GET_CODE (X) == POST_INC) \
2758 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2759 else if (GET_CODE (X) == PLUS) \
2761 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2762 asm_fprintf (STREAM, "[%r, #%d]", \
2763 REGNO (XEXP (X, 0)), \
2764 (int) INTVAL (XEXP (X, 1))); \
2766 asm_fprintf (STREAM, "[%r, %r]", \
2767 REGNO (XEXP (X, 0)), \
2768 REGNO (XEXP (X, 1))); \
2771 output_addr_const (STREAM, X); \
2774 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2776 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2778 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2780 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2781 Used for C++ multiple inheritance. */
2782 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2785 int mi_delta = (DELTA); \
2786 const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \
2788 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2791 mi_delta = - mi_delta; \
2792 while (mi_delta != 0) \
2794 if ((mi_delta & (3 << shift)) == 0) \
2798 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2799 mi_op, this_regno, this_regno, \
2800 mi_delta & (0xff << shift)); \
2801 mi_delta &= ~(0xff << shift); \
2805 fputs ("\tb\t", FILE); \
2806 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2807 if (NEED_PLT_RELOC) \
2808 fputs ("(PLT)", FILE); \
2809 fputc ('\n', FILE); \
2813 /* A C expression whose value is RTL representing the value of the return
2814 address for the frame COUNT steps up from the current frame. */
2816 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2817 arm_return_addr (COUNT, FRAME)
2819 /* Mask of the bits in the PC that contain the real return address
2820 when running in 26-bit mode. */
2821 #define RETURN_ADDR_MASK26 (0x03fffffc)
2823 /* Pick up the return address upon entry to a procedure. Used for
2824 dwarf2 unwind information. This also enables the table driven
2826 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2827 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2829 /* Used to mask out junk bits from the return address, such as
2830 processor state, interrupt status, condition codes and the like. */
2831 #define MASK_RETURN_ADDR \
2832 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2833 in 26 bit mode, the condition codes must be masked out of the \
2834 return address. This does not apply to ARM6 and later processors \
2835 when running in 32 bit mode. */ \
2836 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2837 : (GEN_INT ((unsigned long)0xffffffff)))
2840 /* Define the codes that are matched by predicates in arm.c */
2841 #define PREDICATE_CODES \
2842 {"s_register_operand", {SUBREG, REG}}, \
2843 {"arm_hard_register_operand", {REG}}, \
2844 {"f_register_operand", {SUBREG, REG}}, \
2845 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2846 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2847 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2848 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2849 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2850 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2851 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2852 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2853 {"offsettable_memory_operand", {MEM}}, \
2854 {"bad_signed_byte_operand", {MEM}}, \
2855 {"alignable_memory_operand", {MEM}}, \
2856 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2857 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2858 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2859 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2860 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2861 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2862 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2863 {"load_multiple_operation", {PARALLEL}}, \
2864 {"store_multiple_operation", {PARALLEL}}, \
2865 {"equality_operator", {EQ, NE}}, \
2866 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2867 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2869 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2870 {"const_shift_operand", {CONST_INT}}, \
2871 {"multi_register_push", {PARALLEL}}, \
2872 {"cc_register", {REG}}, \
2873 {"logical_binary_operator", {AND, IOR, XOR}}, \
2874 {"dominant_cc_register", {REG}},
2876 /* Define this if you have special predicates that know special things
2877 about modes. Genrecog will warn about certain forms of
2878 match_operand without a mode; if the operand predicate is listed in
2879 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2880 #define SPECIAL_MODE_PREDICATES \
2881 "cc_register", "dominant_cc_register",
2888 #endif /* ! GCC_ARM_H */
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