1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
69 builtin_define ("__ARM_NEON__"); \
71 /* Add a define for interworking. \
72 Needed when building libgcc.a. */ \
73 if (arm_cpp_interwork) \
74 builtin_define ("__THUMB_INTERWORK__"); \
76 builtin_assert ("cpu=arm"); \
77 builtin_assert ("machine=arm"); \
79 builtin_define (arm_arch_name); \
80 if (arm_arch_cirrus) \
81 builtin_define ("__MAVERICK__"); \
82 if (arm_arch_xscale) \
83 builtin_define ("__XSCALE__"); \
84 if (arm_arch_iwmmxt) \
85 builtin_define ("__IWMMXT__"); \
86 if (TARGET_AAPCS_BASED) \
87 builtin_define ("__ARM_EABI__"); \
90 /* The various ARM cores. */
93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
95 #include "arm-cores.def"
97 /* Used to indicate that no processor has been specified. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
110 /* The processor for which instructions should be scheduled. */
111 extern enum processor_type arm_tune;
113 typedef enum arm_cond_code
115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
120 extern arm_cc arm_current_cc;
122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
124 extern int arm_target_label;
125 extern int arm_ccfsm_state;
126 extern GTY(()) rtx arm_target_insn;
127 /* Define the information needed to generate branch insns. This is
128 stored from the compare operation. */
129 extern GTY(()) rtx arm_compare_op0;
130 extern GTY(()) rtx arm_compare_op1;
131 /* The label of the current constant pool. */
132 extern rtx pool_vector_label;
133 /* Set to 1 when a return insn is output, this means that the epilogue
135 extern int return_used_this_function;
136 /* Callback to output language specific object attributes. */
137 extern void (*arm_lang_output_object_attributes_hook)(void);
139 /* Just in case configure has failed to define anything. */
140 #ifndef TARGET_CPU_DEFAULT
141 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
146 #define CPP_SPEC "%(subtarget_cpp_spec) \
147 %{msoft-float:%{mhard-float: \
148 %e-msoft-float and -mhard_float may not be used together}} \
149 %{mbig-endian:%{mlittle-endian: \
150 %e-mbig-endian and -mlittle-endian may not be used together}}"
156 /* This macro defines names of additional specifications to put in the specs
157 that can be used in various specifications like CC1_SPEC. Its definition
158 is an initializer with a subgrouping for each command option.
160 Each subgrouping contains a string constant, that defines the
161 specification name, and a string constant that used by the GCC driver
164 Do not define this macro if it does not need to do anything. */
165 #define EXTRA_SPECS \
166 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
167 SUBTARGET_EXTRA_SPECS
169 #ifndef SUBTARGET_EXTRA_SPECS
170 #define SUBTARGET_EXTRA_SPECS
173 #ifndef SUBTARGET_CPP_SPEC
174 #define SUBTARGET_CPP_SPEC ""
177 /* Run-time Target Specification. */
178 #ifndef TARGET_VERSION
179 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
182 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
183 /* Use hardware floating point instructions. */
184 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
185 /* Use hardware floating point calling convention. */
186 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
187 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
188 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
189 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
190 #define TARGET_IWMMXT (arm_arch_iwmmxt)
191 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
192 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
193 #define TARGET_ARM (! TARGET_THUMB)
194 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
195 #define TARGET_BACKTRACE (leaf_function_p () \
196 ? TARGET_TPCS_LEAF_FRAME \
198 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
199 #define TARGET_AAPCS_BASED \
200 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
202 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
203 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
205 /* Only 16-bit thumb code. */
206 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
207 /* Arm or Thumb-2 32-bit code. */
208 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
209 /* 32-bit Thumb-2 code. */
210 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
212 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
214 /* The following two macros concern the ability to execute coprocessor
215 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
216 only ever tested when we know we are generating for VFP hardware; we need
217 to be more careful with TARGET_NEON as noted below. */
219 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
220 #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \
221 && (arm_fpu_arch == FPUTYPE_VFP3 \
222 || arm_fpu_arch == FPUTYPE_NEON))
224 /* FPU supports VFPv3 instructions. */
225 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
226 && (arm_fpu_arch == FPUTYPE_VFP3D16 \
229 /* FPU supports Neon instructions. The setting of this macro gets
230 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
231 and TARGET_HARD_FLOAT to ensure that NEON instructions are
233 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
234 && arm_fp_model == ARM_FP_MODEL_VFP \
235 && arm_fpu_arch == FPUTYPE_NEON)
237 /* "DSP" multiply instructions, eg. SMULxy. */
238 #define TARGET_DSP_MULTIPLY \
239 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
240 /* Integer SIMD instructions, and extend-accumulate instructions. */
241 #define TARGET_INT_SIMD \
242 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
244 /* Should MOVW/MOVT be used in preference to a constant pool. */
245 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
247 /* We could use unified syntax for arm mode, but for now we just use it
249 #define TARGET_UNIFIED_ASM TARGET_THUMB2
252 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
253 then TARGET_AAPCS_BASED must be true -- but the converse does not
254 hold. TARGET_BPABI implies the use of the BPABI runtime library,
255 etc., in addition to just the AAPCS calling conventions. */
257 #define TARGET_BPABI false
260 /* Support for a compile-time default CPU, et cetera. The rules are:
261 --with-arch is ignored if -march or -mcpu are specified.
262 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
264 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
266 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
268 --with-fpu is ignored if -mfpu is specified.
269 --with-abi is ignored is -mabi is specified. */
270 #define OPTION_DEFAULT_SPECS \
271 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
272 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
273 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
275 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
276 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
277 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
278 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
280 /* Which floating point model to use. */
283 ARM_FP_MODEL_UNKNOWN,
284 /* FPA model (Hardware or software). */
286 /* Cirrus Maverick floating point model. */
287 ARM_FP_MODEL_MAVERICK,
288 /* VFP floating point model. */
292 extern enum arm_fp_model arm_fp_model;
294 /* Which floating point hardware is available. Also update
295 fp_model_for_fpu in arm.c when adding entries to this list. */
298 /* No FP hardware. */
300 /* Full FPA support. */
302 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
304 /* Emulated FPA hardware, Issue 3 emulator. */
306 /* Cirrus Maverick floating point co-processor. */
318 /* Recast the floating point class to be the floating point attribute. */
319 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
321 /* What type of floating point to tune for */
322 extern enum fputype arm_fpu_tune;
324 /* What type of floating point instructions are available */
325 extern enum fputype arm_fpu_arch;
330 ARM_FLOAT_ABI_SOFTFP,
334 extern enum float_abi_type arm_float_abi;
336 #ifndef TARGET_DEFAULT_FLOAT_ABI
337 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
340 /* Which ABI to use. */
350 extern enum arm_abi_type arm_abi;
352 #ifndef ARM_DEFAULT_ABI
353 #define ARM_DEFAULT_ABI ARM_ABI_APCS
356 /* Which thread pointer access sequence to use. */
363 extern enum arm_tp_type target_thread_pointer;
365 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
366 extern int arm_arch3m;
368 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
369 extern int arm_arch4;
371 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
372 extern int arm_arch4t;
374 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
375 extern int arm_arch5;
377 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
378 extern int arm_arch5e;
380 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
381 extern int arm_arch6;
383 /* Nonzero if instructions not present in the 'M' profile can be used. */
384 extern int arm_arch_notm;
386 /* Nonzero if this chip can benefit from load scheduling. */
387 extern int arm_ld_sched;
389 /* Nonzero if generating thumb code. */
390 extern int thumb_code;
392 /* Nonzero if this chip is a StrongARM. */
393 extern int arm_tune_strongarm;
395 /* Nonzero if this chip is a Cirrus variant. */
396 extern int arm_arch_cirrus;
398 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
399 extern int arm_arch_iwmmxt;
401 /* Nonzero if this chip is an XScale. */
402 extern int arm_arch_xscale;
404 /* Nonzero if tuning for XScale. */
405 extern int arm_tune_xscale;
407 /* Nonzero if tuning for stores via the write buffer. */
408 extern int arm_tune_wbuf;
410 /* Nonzero if tuning for Cortex-A9. */
411 extern int arm_tune_cortex_a9;
413 /* Nonzero if we should define __THUMB_INTERWORK__ in the
415 XXX This is a bit of a hack, it's intended to help work around
416 problems in GLD which doesn't understand that armv5t code is
417 interworking clean. */
418 extern int arm_cpp_interwork;
420 /* Nonzero if chip supports Thumb 2. */
421 extern int arm_arch_thumb2;
423 /* Nonzero if chip supports integer division instruction. */
424 extern int arm_arch_hwdiv;
426 #ifndef TARGET_DEFAULT
427 #define TARGET_DEFAULT (MASK_APCS_FRAME)
430 /* The frame pointer register used in gcc has nothing to do with debugging;
431 that is controlled by the APCS-FRAME option. */
432 #define CAN_DEBUG_WITHOUT_FP
434 #define OVERRIDE_OPTIONS arm_override_options ()
436 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
437 arm_optimization_options ((LEVEL), (SIZE))
439 /* Nonzero if PIC code requires explicit qualifiers to generate
440 PLT and GOT relocs rather than the assembler doing so implicitly.
441 Subtargets can override these if required. */
442 #ifndef NEED_GOT_RELOC
443 #define NEED_GOT_RELOC 0
445 #ifndef NEED_PLT_RELOC
446 #define NEED_PLT_RELOC 0
449 /* Nonzero if we need to refer to the GOT with a PC-relative
450 offset. In other words, generate
452 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
456 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
458 The default is true, which matches NetBSD. Subtargets can
459 override this if required. */
464 /* Target machine storage Layout. */
467 /* Define this macro if it is advisable to hold scalars in registers
468 in a wider mode than that declared by the program. In such cases,
469 the value is constrained to be within the bounds of the declared
470 type, but kept valid in the wider mode. The signedness of the
471 extension may differ from that of the type. */
473 /* It is far faster to zero extend chars than to sign extend them */
475 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
476 if (GET_MODE_CLASS (MODE) == MODE_INT \
477 && GET_MODE_SIZE (MODE) < 4) \
479 if (MODE == QImode) \
481 else if (MODE == HImode) \
486 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
487 if ((GET_MODE_CLASS (MODE) == MODE_INT \
488 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
489 && GET_MODE_SIZE (MODE) < 4) \
492 /* Define this if most significant bit is lowest numbered
493 in instructions that operate on numbered bit-fields. */
494 #define BITS_BIG_ENDIAN 0
496 /* Define this if most significant byte of a word is the lowest numbered.
497 Most ARM processors are run in little endian mode, so that is the default.
498 If you want to have it run-time selectable, change the definition in a
499 cover file to be TARGET_BIG_ENDIAN. */
500 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
502 /* Define this if most significant word of a multiword number is the lowest
504 This is always false, even when in big-endian mode. */
505 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
507 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
508 on processor pre-defineds when compiling libgcc2.c. */
509 #if defined(__ARMEB__) && !defined(__ARMWEL__)
510 #define LIBGCC2_WORDS_BIG_ENDIAN 1
512 #define LIBGCC2_WORDS_BIG_ENDIAN 0
515 /* Define this if most significant word of doubles is the lowest numbered.
516 The rules are different based on whether or not we use FPA-format,
517 VFP-format or some other floating point co-processor's format doubles. */
518 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
520 #define UNITS_PER_WORD 4
522 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
523 registers when autovectorizing for Neon, at least until multiple vector
524 widths are supported properly by the middle-end. */
525 #define UNITS_PER_SIMD_WORD(MODE) \
526 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
528 /* True if natural alignment is used for doubleword types. */
529 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
531 #define DOUBLEWORD_ALIGNMENT 64
533 #define PARM_BOUNDARY 32
535 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
537 #define PREFERRED_STACK_BOUNDARY \
538 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
540 #define FUNCTION_BOUNDARY 32
542 /* The lowest bit is used to indicate Thumb-mode functions, so the
543 vbit must go into the delta field of pointers to member
545 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
547 #define EMPTY_FIELD_BOUNDARY 32
549 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
551 /* XXX Blah -- this macro is used directly by libobjc. Since it
552 supports no vector modes, cut out the complexity and fall back
553 on BIGGEST_FIELD_ALIGNMENT. */
554 #ifdef IN_TARGET_LIBS
555 #define BIGGEST_FIELD_ALIGNMENT 64
558 /* Make strings word-aligned so strcpy from constants will be faster. */
559 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
561 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
562 ((TREE_CODE (EXP) == STRING_CST \
564 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
565 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
567 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
568 value set in previous versions of this toolchain was 8, which produces more
569 compact structures. The command line option -mstructure_size_boundary=<n>
570 can be used to change this value. For compatibility with the ARM SDK
571 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
572 0020D) page 2-20 says "Structures are aligned on word boundaries".
573 The AAPCS specifies a value of 8. */
574 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
575 extern int arm_structure_size_boundary;
577 /* This is the value used to initialize arm_structure_size_boundary. If a
578 particular arm target wants to change the default value it should change
579 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
580 for an example of this. */
581 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
582 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
585 /* Nonzero if move instructions will actually fail to work
586 when given unaligned data. */
587 #define STRICT_ALIGNMENT 1
589 /* wchar_t is unsigned under the AAPCS. */
591 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
593 #define WCHAR_TYPE_SIZE BITS_PER_WORD
597 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
601 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
604 /* AAPCS requires that structure alignment is affected by bitfields. */
605 #ifndef PCC_BITFIELD_TYPE_MATTERS
606 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
610 /* Standard register usage. */
612 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
613 (S - saved over call).
615 r0 * argument word/integer result
618 r4-r8 S register variable
619 r9 S (rfp) register variable (real frame pointer)
621 r10 F S (sl) stack limit (used by -mapcs-stack-check)
622 r11 F S (fp) argument pointer
623 r12 (ip) temp workspace
624 r13 F S (sp) lower end of current stack frame
625 r14 (lr) link address/workspace
626 r15 F (pc) program counter
628 f0 floating point result
629 f1-f3 floating point scratch
631 f4-f7 S floating point variable
633 cc This is NOT a real register, but is used internally
634 to represent things that use or set the condition
636 sfp This isn't either. It is used during rtl generation
637 since the offset between the frame pointer and the
638 auto's isn't known until after register allocation.
639 afp Nor this, we only need this because of non-local
640 goto. Without it fp appears to be used and the
641 elimination code won't get rid of sfp. It tracks
642 fp exactly at all times.
644 *: See CONDITIONAL_REGISTER_USAGE */
647 mvf0 Cirrus floating point result
648 mvf1-mvf3 Cirrus floating point scratch
649 mvf4-mvf15 S Cirrus floating point variable. */
651 /* s0-s15 VFP scratch (aka d0-d7).
652 s16-s31 S VFP variable (aka d8-d15).
653 vfpcc Not a real register. Represents the VFP condition
656 /* The stack backtrace structure is as follows:
657 fp points to here: | save code pointer | [fp]
658 | return link value | [fp, #-4]
659 | return sp value | [fp, #-8]
660 | return fp value | [fp, #-12]
661 [| saved r10 value |]
672 [| saved f7 value |] three words
673 [| saved f6 value |] three words
674 [| saved f5 value |] three words
675 [| saved f4 value |] three words
676 r0-r3 are not normally saved in a C function. */
678 /* 1 for registers that have pervasive standard uses
679 and are not available for the register allocator. */
680 #define FIXED_REGISTERS \
702 /* 1 for registers not available across function calls.
703 These must include the FIXED_REGISTERS and also any
704 registers that can be used without being saved.
705 The latter must include the registers where values are returned
706 and the register where structure-value addresses are passed.
707 Aside from that, you can include as many other registers as you like.
708 The CC is not preserved over function calls on the ARM 6, so it is
709 easier to assume this for all. SFP is preserved, since FP is. */
710 #define CALL_USED_REGISTERS \
732 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
733 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
736 #define CONDITIONAL_REGISTER_USAGE \
740 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
742 for (regno = FIRST_FPA_REGNUM; \
743 regno <= LAST_FPA_REGNUM; ++regno) \
744 fixed_regs[regno] = call_used_regs[regno] = 1; \
747 if (TARGET_THUMB && optimize_size) \
749 /* When optimizing for size, it's better not to use \
750 the HI regs, because of the overhead of stacking \
752 /* ??? Is this still true for thumb2? */ \
753 for (regno = FIRST_HI_REGNUM; \
754 regno <= LAST_HI_REGNUM; ++regno) \
755 fixed_regs[regno] = call_used_regs[regno] = 1; \
758 /* The link register can be clobbered by any branch insn, \
759 but we have no way to track that at present, so mark \
760 it as unavailable. */ \
762 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
764 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
766 if (TARGET_MAVERICK) \
768 for (regno = FIRST_FPA_REGNUM; \
769 regno <= LAST_FPA_REGNUM; ++ regno) \
770 fixed_regs[regno] = call_used_regs[regno] = 1; \
771 for (regno = FIRST_CIRRUS_FP_REGNUM; \
772 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
774 fixed_regs[regno] = 0; \
775 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
780 /* VFPv3 registers are disabled when earlier VFP \
781 versions are selected due to the definition of \
782 LAST_VFP_REGNUM. */ \
783 for (regno = FIRST_VFP_REGNUM; \
784 regno <= LAST_VFP_REGNUM; ++ regno) \
786 fixed_regs[regno] = 0; \
787 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
788 || regno >= FIRST_VFP_REGNUM + 32; \
793 if (TARGET_REALLY_IWMMXT) \
795 regno = FIRST_IWMMXT_GR_REGNUM; \
796 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
797 and wCG1 as call-preserved registers. The 2002/11/21 \
798 revision changed this so that all wCG registers are \
799 scratch registers. */ \
800 for (regno = FIRST_IWMMXT_GR_REGNUM; \
801 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
802 fixed_regs[regno] = 0; \
803 /* The XScale ABI has wR0 - wR9 as scratch registers, \
804 the rest as call-preserved registers. */ \
805 for (regno = FIRST_IWMMXT_REGNUM; \
806 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
808 fixed_regs[regno] = 0; \
809 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
813 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
815 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
816 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
818 else if (TARGET_APCS_STACK) \
820 fixed_regs[10] = 1; \
821 call_used_regs[10] = 1; \
823 /* -mcaller-super-interworking reserves r11 for calls to \
824 _interwork_r11_call_via_rN(). Making the register global \
825 is an easy way of ensuring that it remains valid for all \
827 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
828 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
830 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
831 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
832 if (TARGET_CALLER_INTERWORKING) \
833 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
835 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
838 /* These are a couple of extensions to the formats accepted
840 %@ prints out ASM_COMMENT_START
841 %r prints out REGISTER_PREFIX reg_names[arg] */
842 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
844 fputs (ASM_COMMENT_START, FILE); \
848 fputs (REGISTER_PREFIX, FILE); \
849 fputs (reg_names [va_arg (ARGS, int)], FILE); \
852 /* Round X up to the nearest word. */
853 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
855 /* Convert fron bytes to ints. */
856 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
858 /* The number of (integer) registers required to hold a quantity of type MODE.
859 Also used for VFP registers. */
860 #define ARM_NUM_REGS(MODE) \
861 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
863 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
864 #define ARM_NUM_REGS2(MODE, TYPE) \
865 ARM_NUM_INTS ((MODE) == BLKmode ? \
866 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
868 /* The number of (integer) argument register available. */
869 #define NUM_ARG_REGS 4
871 /* Return the register number of the N'th (integer) argument. */
872 #define ARG_REGISTER(N) (N - 1)
874 /* Specify the registers used for certain standard purposes.
875 The values of these macros are register numbers. */
877 /* The number of the last argument register. */
878 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
880 /* The numbers of the Thumb register ranges. */
881 #define FIRST_LO_REGNUM 0
882 #define LAST_LO_REGNUM 7
883 #define FIRST_HI_REGNUM 8
884 #define LAST_HI_REGNUM 11
886 #ifndef TARGET_UNWIND_INFO
887 /* We use sjlj exceptions for backwards compatibility. */
888 #define MUST_USE_SJLJ_EXCEPTIONS 1
891 /* We can generate DWARF2 Unwind info, even though we don't use it. */
892 #define DWARF2_UNWIND_INFO 1
894 /* Use r0 and r1 to pass exception handling information. */
895 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
897 /* The register that holds the return address in exception handlers. */
898 #define ARM_EH_STACKADJ_REGNUM 2
899 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
901 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
902 as an invisible last argument (possible since varargs don't exist in
903 Pascal), so the following is not true. */
904 #define STATIC_CHAIN_REGNUM 12
906 /* Define this to be where the real frame pointer is if it is not possible to
907 work out the offset between the frame pointer and the automatic variables
908 until after register allocation has taken place. FRAME_POINTER_REGNUM
909 should point to a special register that we will make sure is eliminated.
911 For the Thumb we have another problem. The TPCS defines the frame pointer
912 as r11, and GCC believes that it is always possible to use the frame pointer
913 as base register for addressing purposes. (See comments in
914 find_reloads_address()). But - the Thumb does not allow high registers,
915 including r11, to be used as base address registers. Hence our problem.
917 The solution used here, and in the old thumb port is to use r7 instead of
918 r11 as the hard frame pointer and to have special code to generate
919 backtrace structures on the stack (if required to do so via a command line
920 option) using r11. This is the only 'user visible' use of r11 as a frame
922 #define ARM_HARD_FRAME_POINTER_REGNUM 11
923 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
925 #define HARD_FRAME_POINTER_REGNUM \
927 ? ARM_HARD_FRAME_POINTER_REGNUM \
928 : THUMB_HARD_FRAME_POINTER_REGNUM)
930 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
932 /* Register to use for pushing function arguments. */
933 #define STACK_POINTER_REGNUM SP_REGNUM
935 /* ARM floating pointer registers. */
936 #define FIRST_FPA_REGNUM 16
937 #define LAST_FPA_REGNUM 23
938 #define IS_FPA_REGNUM(REGNUM) \
939 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
941 #define FIRST_IWMMXT_GR_REGNUM 43
942 #define LAST_IWMMXT_GR_REGNUM 46
943 #define FIRST_IWMMXT_REGNUM 47
944 #define LAST_IWMMXT_REGNUM 62
945 #define IS_IWMMXT_REGNUM(REGNUM) \
946 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
947 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
948 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
950 /* Base register for access to local variables of the function. */
951 #define FRAME_POINTER_REGNUM 25
953 /* Base register for access to arguments of the function. */
954 #define ARG_POINTER_REGNUM 26
956 #define FIRST_CIRRUS_FP_REGNUM 27
957 #define LAST_CIRRUS_FP_REGNUM 42
958 #define IS_CIRRUS_REGNUM(REGNUM) \
959 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
961 #define FIRST_VFP_REGNUM 63
962 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
963 #define LAST_VFP_REGNUM \
964 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
966 #define IS_VFP_REGNUM(REGNUM) \
967 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
969 /* VFP registers are split into two types: those defined by VFP versions < 3
970 have D registers overlaid on consecutive pairs of S registers. VFP version 3
971 defines 16 new D registers (d16-d31) which, for simplicity and correctness
972 in various parts of the backend, we implement as "fake" single-precision
973 registers (which would be S32-S63, but cannot be used in that way). The
974 following macros define these ranges of registers. */
975 #define LAST_LO_VFP_REGNUM 94
976 #define FIRST_HI_VFP_REGNUM 95
977 #define LAST_HI_VFP_REGNUM 126
979 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
980 ((REGNUM) <= LAST_LO_VFP_REGNUM)
982 /* DFmode values are only valid in even register pairs. */
983 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
984 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
986 /* Neon Quad values must start at a multiple of four registers. */
987 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
988 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
990 /* Neon structures of vectors must be in even register pairs and there
991 must be enough registers available. Because of various patterns
992 requiring quad registers, we require them to start at a multiple of
994 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
995 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
996 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
998 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
999 /* + 16 Cirrus registers take us up to 43. */
1000 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1001 /* VFP (VFP3) adds 32 (64) + 1 more. */
1002 #define FIRST_PSEUDO_REGISTER 128
1004 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1006 /* Value should be nonzero if functions must have frame pointers.
1007 Zero means the frame pointer need not be set up (and parms may be accessed
1008 via the stack pointer) in functions that seem suitable.
1009 If we have to have a frame pointer we might as well make use of it.
1010 APCS says that the frame pointer does not need to be pushed in leaf
1011 functions, or simple tail call functions. */
1013 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1014 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1017 #define FRAME_POINTER_REQUIRED \
1018 (cfun->has_nonlocal_label \
1019 || SUBTARGET_FRAME_POINTER_REQUIRED \
1020 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1022 /* Return number of consecutive hard regs needed starting at reg REGNO
1023 to hold something of mode MODE.
1024 This is ordinarily the length in words of a value of mode MODE
1025 but can be less for certain modes in special long registers.
1027 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1029 #define HARD_REGNO_NREGS(REGNO, MODE) \
1031 && REGNO >= FIRST_FPA_REGNUM \
1032 && REGNO != FRAME_POINTER_REGNUM \
1033 && REGNO != ARG_POINTER_REGNUM) \
1034 && !IS_VFP_REGNUM (REGNO) \
1035 ? 1 : ARM_NUM_REGS (MODE))
1037 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1038 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1039 arm_hard_regno_mode_ok ((REGNO), (MODE))
1041 /* Value is 1 if it is a good idea to tie two pseudo registers
1042 when one has mode MODE1 and one has mode MODE2.
1043 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1044 for any hard reg, then this must be 0 for correct output. */
1045 #define MODES_TIEABLE_P(MODE1, MODE2) \
1046 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1048 #define VALID_IWMMXT_REG_MODE(MODE) \
1049 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1051 /* Modes valid for Neon D registers. */
1052 #define VALID_NEON_DREG_MODE(MODE) \
1053 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1054 || (MODE) == V2SFmode || (MODE) == DImode)
1056 /* Modes valid for Neon Q registers. */
1057 #define VALID_NEON_QREG_MODE(MODE) \
1058 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1059 || (MODE) == V4SFmode || (MODE) == V2DImode)
1061 /* Structure modes valid for Neon registers. */
1062 #define VALID_NEON_STRUCT_MODE(MODE) \
1063 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1064 || (MODE) == CImode || (MODE) == XImode)
1066 /* The order in which register should be allocated. It is good to use ip
1067 since no saving is required (though calls clobber it) and it never contains
1068 function parameters. It is quite good to use lr since other calls may
1069 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1070 least likely to contain a function parameter; in addition results are
1072 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1073 then D8-D15. The reason for doing this is to attempt to reduce register
1074 pressure when both single- and double-precision registers are used in a
1077 #define REG_ALLOC_ORDER \
1079 3, 2, 1, 0, 12, 14, 4, 5, \
1080 6, 7, 8, 10, 9, 11, 13, 15, \
1081 16, 17, 18, 19, 20, 21, 22, 23, \
1082 27, 28, 29, 30, 31, 32, 33, 34, \
1083 35, 36, 37, 38, 39, 40, 41, 42, \
1084 43, 44, 45, 46, 47, 48, 49, 50, \
1085 51, 52, 53, 54, 55, 56, 57, 58, \
1088 95, 96, 97, 98, 99, 100, 101, 102, \
1089 103, 104, 105, 106, 107, 108, 109, 110, \
1090 111, 112, 113, 114, 115, 116, 117, 118, \
1091 119, 120, 121, 122, 123, 124, 125, 126, \
1092 78, 77, 76, 75, 74, 73, 72, 71, \
1093 70, 69, 68, 67, 66, 65, 64, 63, \
1094 79, 80, 81, 82, 83, 84, 85, 86, \
1095 87, 88, 89, 90, 91, 92, 93, 94, \
1099 /* Use different register alloc ordering for Thumb. */
1100 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
1102 /* Interrupt functions can only use registers that have already been
1103 saved by the prologue, even if they would normally be
1105 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1106 (! IS_INTERRUPT (cfun->machine->func_type) || \
1107 df_regs_ever_live_p (DST))
1109 /* Register and constant classes. */
1111 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1112 Now that the Thumb is involved it has become more complicated. */
1136 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1138 /* Give names of register classes as strings for dump file. */
1139 #define REG_CLASS_NAMES \
1161 /* Define which registers fit in which classes.
1162 This is an initializer for a vector of HARD_REG_SET
1163 of length N_REG_CLASSES. */
1164 #define REG_CLASS_CONTENTS \
1166 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1167 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1168 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1169 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1170 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1171 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1172 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1173 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1174 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1175 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1176 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1177 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1178 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1179 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1180 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1181 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1182 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1183 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1186 /* Any of the VFP register classes. */
1187 #define IS_VFP_CLASS(X) \
1188 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1189 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1191 /* The same information, inverted:
1192 Return the class number of the smallest class containing
1193 reg number REGNO. This could be a conditional expression
1194 or could index an array. */
1195 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1197 /* The following macro defines cover classes for Integrated Register
1198 Allocator. Cover classes is a set of non-intersected register
1199 classes covering all hard registers used for register allocation
1200 purpose. Any move between two registers of a cover class should be
1201 cheaper than load or store of the registers. The macro value is
1202 array of register classes with LIM_REG_CLASSES used as the end
1205 #define IRA_COVER_CLASSES \
1207 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1211 /* FPA registers can't do subreg as all values are reformatted to internal
1212 precision. VFP registers may only be accessed in the mode they
1214 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1215 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1216 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1217 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1220 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1221 using r0-r4 for function arguments, r7 for the stack frame and don't
1222 have enough left over to do doubleword arithmetic. */
1223 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1224 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1225 || (CLASS) == CC_REG)
1227 /* The class value for index registers, and the one for base regs. */
1228 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1229 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1231 /* For the Thumb the high registers cannot be used as base registers
1232 when addressing quantities in QI or HI mode; if we don't know the
1233 mode, then we must be conservative. */
1234 #define MODE_BASE_REG_CLASS(MODE) \
1235 (TARGET_32BIT ? CORE_REGS : \
1236 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1238 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1239 instead of BASE_REGS. */
1240 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1242 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1243 registers explicitly used in the rtl to be used as spill registers
1244 but prevents the compiler from extending the lifetime of these
1246 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1248 /* Given an rtx X being reloaded into a reg required to be
1249 in class CLASS, return the class of reg to actually use.
1250 In general this is just CLASS, but for the Thumb core registers and
1251 immediate constants we prefer a LO_REGS class or a subset. */
1252 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1253 (TARGET_ARM ? (CLASS) : \
1254 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1255 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1256 ? LO_REGS : (CLASS)))
1258 /* Must leave BASE_REGS reloads alone */
1259 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1260 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1261 ? ((true_regnum (X) == -1 ? LO_REGS \
1262 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1266 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1267 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1268 ? ((true_regnum (X) == -1 ? LO_REGS \
1269 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1273 /* Return the register class of a scratch register needed to copy IN into
1274 or out of a register in CLASS in MODE. If it can be done directly,
1275 NO_REGS is returned. */
1276 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1277 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1278 ((TARGET_VFP && TARGET_HARD_FLOAT \
1279 && IS_VFP_CLASS (CLASS)) \
1280 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1281 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1282 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1284 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1285 ? GENERAL_REGS : NO_REGS) \
1286 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1288 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1289 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1290 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1291 ((TARGET_VFP && TARGET_HARD_FLOAT \
1292 && IS_VFP_CLASS (CLASS)) \
1293 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1294 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1295 coproc_secondary_reload_class (MODE, X, TRUE) : \
1296 /* Cannot load constants into Cirrus registers. */ \
1297 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1298 && (CLASS) == CIRRUS_REGS \
1299 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1302 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1303 && CONSTANT_P (X)) \
1305 (((MODE) == HImode && ! arm_arch4 \
1306 && (GET_CODE (X) == MEM \
1307 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1308 && true_regnum (X) == -1))) \
1309 ? GENERAL_REGS : NO_REGS) \
1310 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1312 /* Try a machine-dependent way of reloading an illegitimate address
1313 operand. If we find one, push the reload and jump to WIN. This
1314 macro is used in only one place: `find_reloads_address' in reload.c.
1316 For the ARM, we wish to handle large displacements off a base
1317 register by splitting the addend across a MOV and the mem insn.
1318 This can cut the number of reloads needed. */
1319 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1322 if (GET_CODE (X) == PLUS \
1323 && GET_CODE (XEXP (X, 0)) == REG \
1324 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1325 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1326 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1328 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1329 HOST_WIDE_INT low, high; \
1331 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1332 low = ((val & 0xf) ^ 0x8) - 0x8; \
1333 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1334 /* Need to be careful, -256 is not a valid offset. */ \
1335 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1336 else if (MODE == SImode \
1337 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1338 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1339 /* Need to be careful, -4096 is not a valid offset. */ \
1340 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1341 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1342 /* Need to be careful, -256 is not a valid offset. */ \
1343 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1344 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1345 && TARGET_HARD_FLOAT && TARGET_FPA) \
1346 /* Need to be careful, -1024 is not a valid offset. */ \
1347 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1351 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1352 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1353 - (unsigned HOST_WIDE_INT) 0x80000000); \
1354 /* Check for overflow or zero */ \
1355 if (low == 0 || high == 0 || (high + low != val)) \
1358 /* Reload the high part into a base reg; leave the low part \
1360 X = gen_rtx_PLUS (GET_MODE (X), \
1361 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1364 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1365 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1366 VOIDmode, 0, 0, OPNUM, TYPE); \
1372 /* XXX If an HImode FP+large_offset address is converted to an HImode
1373 SP+large_offset address, then reload won't know how to fix it. It sees
1374 only that SP isn't valid for HImode, and so reloads the SP into an index
1375 register, but the resulting address is still invalid because the offset
1376 is too big. We fix it here instead by reloading the entire address. */
1377 /* We could probably achieve better results by defining PROMOTE_MODE to help
1378 cope with the variances between the Thumb's signed and unsigned byte and
1379 halfword load instructions. */
1380 /* ??? This should be safe for thumb2, but we may be able to do better. */
1381 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1383 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1391 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1393 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1395 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1397 /* Return the maximum number of consecutive registers
1398 needed to represent mode MODE in a register of class CLASS.
1399 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1400 #define CLASS_MAX_NREGS(CLASS, MODE) \
1401 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1403 /* If defined, gives a class of registers that cannot be used as the
1404 operand of a SUBREG that changes the mode of the object illegally. */
1406 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1407 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1409 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1410 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1411 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1412 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1413 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1414 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1415 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1416 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1417 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1420 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1422 /* Stack layout; function entry, exit and calling. */
1424 /* Define this if pushing a word on the stack
1425 makes the stack pointer a smaller address. */
1426 #define STACK_GROWS_DOWNWARD 1
1428 /* Define this to nonzero if the nominal address of the stack frame
1429 is at the high-address end of the local variables;
1430 that is, each additional local variable allocated
1431 goes at a more negative offset in the frame. */
1432 #define FRAME_GROWS_DOWNWARD 1
1434 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1435 When present, it is one word in size, and sits at the top of the frame,
1436 between the soft frame pointer and either r7 or r11.
1438 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1439 and only then if some outgoing arguments are passed on the stack. It would
1440 be tempting to also check whether the stack arguments are passed by indirect
1441 calls, but there seems to be no reason in principle why a post-reload pass
1442 couldn't convert a direct call into an indirect one. */
1443 #define CALLER_INTERWORKING_SLOT_SIZE \
1444 (TARGET_CALLER_INTERWORKING \
1445 && crtl->outgoing_args_size != 0 \
1446 ? UNITS_PER_WORD : 0)
1448 /* Offset within stack frame to start allocating local variables at.
1449 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1450 first local allocated. Otherwise, it is the offset to the BEGINNING
1451 of the first local allocated. */
1452 #define STARTING_FRAME_OFFSET 0
1454 /* If we generate an insn to push BYTES bytes,
1455 this says how many the stack pointer really advances by. */
1456 /* The push insns do not do this rounding implicitly.
1457 So don't define this. */
1458 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1460 /* Define this if the maximum size of all the outgoing args is to be
1461 accumulated and pushed during the prologue. The amount can be
1462 found in the variable crtl->outgoing_args_size. */
1463 #define ACCUMULATE_OUTGOING_ARGS 1
1465 /* Offset of first parameter from the argument pointer register value. */
1466 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1468 /* Value is the number of byte of arguments automatically
1469 popped when returning from a subroutine call.
1470 FUNDECL is the declaration node of the function (as a tree),
1471 FUNTYPE is the data type of the function (as a tree),
1472 or for a library call it is an identifier node for the subroutine name.
1473 SIZE is the number of bytes of arguments passed on the stack.
1475 On the ARM, the caller does not pop any of its arguments that were passed
1477 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1479 /* Define how to find the value returned by a library function
1480 assuming the value has mode MODE. */
1481 #define LIBCALL_VALUE(MODE) \
1482 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1483 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1484 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1485 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1486 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1487 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1488 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1489 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1490 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1492 /* Define how to find the value returned by a function.
1493 VALTYPE is the data type of the value (as a tree).
1494 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1495 otherwise, FUNC is 0. */
1496 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1497 arm_function_value (VALTYPE, FUNC);
1499 /* 1 if N is a possible register number for a function value.
1500 On the ARM, only r0 and f0 can return results. */
1501 /* On a Cirrus chip, mvf0 can return results. */
1502 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1503 ((REGNO) == ARG_REGISTER (1) \
1504 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1505 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1506 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1507 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1508 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1510 /* Amount of memory needed for an untyped call to save all possible return
1512 #define APPLY_RESULT_SIZE arm_apply_result_size()
1514 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1515 values must be in memory. On the ARM, they need only do so if larger
1516 than a word, or if they contain elements offset from zero in the struct. */
1517 #define DEFAULT_PCC_STRUCT_RETURN 0
1519 /* These bits describe the different types of function supported
1520 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1521 normal function and an interworked function, for example. Knowing the
1522 type of a function is important for determining its prologue and
1524 Note value 7 is currently unassigned. Also note that the interrupt
1525 function types all have bit 2 set, so that they can be tested for easily.
1526 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1527 machine_function structure is initialized (to zero) func_type will
1528 default to unknown. This will force the first use of arm_current_func_type
1529 to call arm_compute_func_type. */
1530 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1531 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1532 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1533 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1534 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1535 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1537 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1539 /* In addition functions can have several type modifiers,
1540 outlined by these bit masks: */
1541 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1542 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1543 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1544 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1545 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1547 /* Some macros to test these flags. */
1548 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1549 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1550 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1551 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1552 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1553 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1556 /* Structure used to hold the function stack frame layout. Offsets are
1557 relative to the stack pointer on function entry. Positive offsets are
1558 in the direction of stack growth.
1559 Only soft_frame is used in thumb mode. */
1561 typedef struct arm_stack_offsets GTY(())
1563 int saved_args; /* ARG_POINTER_REGNUM. */
1564 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1566 int soft_frame; /* FRAME_POINTER_REGNUM. */
1567 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1568 int outgoing_args; /* STACK_POINTER_REGNUM. */
1569 unsigned int saved_regs_mask;
1573 /* A C structure for machine-specific, per-function data.
1574 This is added to the cfun structure. */
1575 typedef struct machine_function GTY(())
1577 /* Additional stack adjustment in __builtin_eh_throw. */
1578 rtx eh_epilogue_sp_ofs;
1579 /* Records if LR has to be saved for far jumps. */
1581 /* Records if ARG_POINTER was ever live. */
1582 int arg_pointer_live;
1583 /* Records if the save of LR has been eliminated. */
1584 int lr_save_eliminated;
1585 /* The size of the stack frame. Only valid after reload. */
1586 arm_stack_offsets stack_offsets;
1587 /* Records the type of the current function. */
1588 unsigned long func_type;
1589 /* Record if the function has a variable argument list. */
1590 int uses_anonymous_args;
1591 /* Records if sibcalls are blocked because an argument
1592 register is needed to preserve stack alignment. */
1593 int sibcall_blocked;
1594 /* The PIC register for this function. This might be a pseudo. */
1596 /* Labels for per-function Thumb call-via stubs. One per potential calling
1597 register. We can never call via LR or PC. We can call via SP if a
1598 trampoline happens to be on the top of the stack. */
1603 /* As in the machine_function, a global set of call-via labels, for code
1604 that is in text_section. */
1605 extern GTY(()) rtx thumb_call_via_label[14];
1607 /* A C type for declaring a variable that is used as the first argument of
1608 `FUNCTION_ARG' and other related values. For some target machines, the
1609 type `int' suffices and can hold the number of bytes of argument so far. */
1612 /* This is the number of registers of arguments scanned so far. */
1614 /* This is the number of iWMMXt register arguments scanned so far. */
1621 /* Define where to put the arguments to a function.
1622 Value is zero to push the argument on the stack,
1623 or a hard register in which to store the argument.
1625 MODE is the argument's machine mode.
1626 TYPE is the data type of the argument (as a tree).
1627 This is null for libcalls where that information may
1629 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1630 the preceding args and about the function being called.
1631 NAMED is nonzero if this argument is a named parameter
1632 (otherwise it is an extra parameter matching an ellipsis).
1634 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1635 other arguments are passed on the stack. If (NAMED == 0) (which happens
1636 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1637 defined), say it is passed in the stack (function_prologue will
1638 indeed make it pass in the stack if necessary). */
1639 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1640 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1642 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1643 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1645 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1646 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1648 /* For AAPCS, padding should never be below the argument. For other ABIs,
1649 * mimic the default. */
1650 #define PAD_VARARGS_DOWN \
1651 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1653 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1654 for a call to a function whose data type is FNTYPE.
1655 For a library call, FNTYPE is 0.
1656 On the ARM, the offset starts at 0. */
1657 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1658 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1660 /* Update the data in CUM to advance over an argument
1661 of mode MODE and data type TYPE.
1662 (TYPE is null for libcalls where that information may not be available.) */
1663 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1665 if (arm_vector_mode_supported_p (MODE) \
1666 && (CUM).named_count > (CUM).nargs \
1667 && TARGET_IWMMXT_ABI) \
1668 (CUM).iwmmxt_nregs += 1; \
1670 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1672 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1673 argument with the specified mode and type. If it is not defined,
1674 `PARM_BOUNDARY' is used for all arguments. */
1675 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1676 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1677 ? DOUBLEWORD_ALIGNMENT \
1680 /* 1 if N is a possible register number for function argument passing.
1681 On the ARM, r0-r3 are used to pass args. */
1682 #define FUNCTION_ARG_REGNO_P(REGNO) \
1683 (IN_RANGE ((REGNO), 0, 3) \
1684 || (TARGET_IWMMXT_ABI \
1685 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1688 /* If your target environment doesn't prefix user functions with an
1689 underscore, you may wish to re-define this to prevent any conflicts. */
1690 #ifndef ARM_MCOUNT_NAME
1691 #define ARM_MCOUNT_NAME "*mcount"
1694 /* Call the function profiler with a given profile label. The Acorn
1695 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1696 On the ARM the full profile code will look like:
1705 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1706 will output the .text section.
1708 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1709 ``prof'' doesn't seem to mind about this!
1711 Note - this version of the code is designed to work in both ARM and
1713 #ifndef ARM_FUNCTION_PROFILER
1714 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1719 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1720 IP_REGNUM, LR_REGNUM); \
1721 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1722 fputc ('\n', STREAM); \
1723 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1724 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1725 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1729 #ifdef THUMB_FUNCTION_PROFILER
1730 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1732 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1734 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1736 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1737 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1740 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1741 the stack pointer does not matter. The value is tested only in
1742 functions that have frame pointers.
1743 No definition is equivalent to always zero.
1745 On the ARM, the function epilogue recovers the stack pointer from the
1747 #define EXIT_IGNORE_STACK 1
1749 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1751 /* Determine if the epilogue should be output as RTL.
1752 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1753 /* This is disabled for Thumb-2 because it will confuse the
1754 conditional insn counter. */
1755 #define USE_RETURN_INSN(ISCOND) \
1756 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1758 /* Definitions for register eliminations.
1760 This is an array of structures. Each structure initializes one pair
1761 of eliminable registers. The "from" register number is given first,
1762 followed by "to". Eliminations of the same "from" register are listed
1763 in order of preference.
1765 We have two registers that can be eliminated on the ARM. First, the
1766 arg pointer register can often be eliminated in favor of the stack
1767 pointer register. Secondly, the pseudo frame pointer register can always
1768 be eliminated; it is replaced with either the stack or the real frame
1769 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1770 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1772 #define ELIMINABLE_REGS \
1773 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1774 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1775 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1776 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1777 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1778 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1779 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1781 /* Given FROM and TO register numbers, say whether this elimination is
1782 allowed. Frame pointer elimination is automatically handled.
1784 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1785 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1786 pointer, we must eliminate FRAME_POINTER_REGNUM into
1787 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1788 ARG_POINTER_REGNUM. */
1789 #define CAN_ELIMINATE(FROM, TO) \
1790 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1791 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1792 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1793 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1796 /* Define the offset between two registers, one to be eliminated, and the
1797 other its replacement, at the start of a routine. */
1798 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1800 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1802 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1804 /* Special case handling of the location of arguments passed on the stack. */
1805 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1807 /* Initialize data used by insn expanders. This is called from insn_emit,
1808 once for every function before code is generated. */
1809 #define INIT_EXPANDERS arm_init_expanders ()
1811 /* Output assembler code for a block containing the constant parts
1812 of a trampoline, leaving space for the variable parts.
1814 On the ARM, (if r8 is the static chain regnum, and remembering that
1815 referencing pc adds an offset of 8) the trampoline looks like:
1818 .word static chain value
1819 .word function's address
1820 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1821 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1823 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1824 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1825 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1826 PC_REGNUM, PC_REGNUM); \
1827 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1828 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1831 /* The Thumb-2 trampoline is similar to the arm implementation.
1832 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1833 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1835 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1836 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1837 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1838 PC_REGNUM, PC_REGNUM); \
1839 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1840 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1843 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1845 ASM_OUTPUT_ALIGN(FILE, 2); \
1846 fprintf (FILE, "\t.code\t16\n"); \
1847 fprintf (FILE, ".Ltrampoline_start:\n"); \
1848 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1849 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1851 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1852 STATIC_CHAIN_REGNUM); \
1853 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1855 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1857 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1859 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1860 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1863 #define TRAMPOLINE_TEMPLATE(FILE) \
1865 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1866 else if (TARGET_THUMB2) \
1867 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1869 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1871 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1873 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1876 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1877 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1880 /* Length in units of the trampoline for entering a nested function. */
1881 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1883 /* Alignment required for a trampoline in bits. */
1884 #define TRAMPOLINE_ALIGNMENT 32
1887 /* Emit RTL insns to initialize the variable parts of a trampoline.
1888 FNADDR is an RTX for the address of the function's pure code.
1889 CXT is an RTX for the static chain value for the function. */
1890 #ifndef INITIALIZE_TRAMPOLINE
1891 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1893 emit_move_insn (gen_rtx_MEM (SImode, \
1894 plus_constant (TRAMP, \
1895 TARGET_32BIT ? 8 : 12)), \
1897 emit_move_insn (gen_rtx_MEM (SImode, \
1898 plus_constant (TRAMP, \
1899 TARGET_32BIT ? 12 : 16)), \
1901 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1902 0, VOIDmode, 2, TRAMP, Pmode, \
1903 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1908 /* Addressing modes, and classification of registers for them. */
1909 #define HAVE_POST_INCREMENT 1
1910 #define HAVE_PRE_INCREMENT TARGET_32BIT
1911 #define HAVE_POST_DECREMENT TARGET_32BIT
1912 #define HAVE_PRE_DECREMENT TARGET_32BIT
1913 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1914 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1915 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1916 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1918 /* Macros to check register numbers against specific register classes. */
1920 /* These assume that REGNO is a hard or pseudo reg number.
1921 They give nonzero only if REGNO is a hard reg of the suitable class
1922 or a pseudo reg currently allocated to a suitable hard reg.
1923 Since they use reg_renumber, they are safe only once reg_renumber
1924 has been allocated, which happens in local-alloc.c. */
1925 #define TEST_REGNO(R, TEST, VALUE) \
1926 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1928 /* Don't allow the pc to be used. */
1929 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1930 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1931 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1932 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1934 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1935 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1936 || (GET_MODE_SIZE (MODE) >= 4 \
1937 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1939 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1941 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1942 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1944 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1945 For Thumb, we can not use SP + reg, so reject SP. */
1946 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1947 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1949 /* For ARM code, we don't care about the mode, but for Thumb, the index
1950 must be suitable for use in a QImode load. */
1951 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1952 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1953 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1955 /* Maximum number of registers that can appear in a valid memory address.
1956 Shifts in addresses can't be by a register. */
1957 #define MAX_REGS_PER_ADDRESS 2
1959 /* Recognize any constant value that is a valid address. */
1960 /* XXX We can address any constant, eventually... */
1961 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1962 #define CONSTANT_ADDRESS_P(X) \
1963 (GET_CODE (X) == SYMBOL_REF \
1964 && (CONSTANT_POOL_ADDRESS_P (X) \
1965 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1967 /* True if SYMBOL + OFFSET constants must refer to something within
1968 SYMBOL's section. */
1969 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1971 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1972 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1973 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1976 /* Nonzero if the constant value X is a legitimate general operand.
1977 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1979 On the ARM, allow any integer (invalid ones are removed later by insn
1980 patterns), nice doubles and symbol_refs which refer to the function's
1983 When generating pic allow anything. */
1984 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1986 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1987 ( GET_CODE (X) == CONST_INT \
1988 || GET_CODE (X) == CONST_DOUBLE \
1989 || CONSTANT_ADDRESS_P (X) \
1992 #define LEGITIMATE_CONSTANT_P(X) \
1993 (!arm_cannot_force_const_mem (X) \
1994 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1995 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1997 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1998 #define SUBTARGET_NAME_ENCODING_LENGTHS
2001 /* This is a C fragment for the inside of a switch statement.
2002 Each case label should return the number of characters to
2003 be stripped from the start of a function's name, if that
2004 name starts with the indicated character. */
2005 #define ARM_NAME_ENCODING_LENGTHS \
2006 case '*': return 1; \
2007 SUBTARGET_NAME_ENCODING_LENGTHS
2009 /* This is how to output a reference to a user-level label named NAME.
2010 `assemble_name' uses this. */
2011 #undef ASM_OUTPUT_LABELREF
2012 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2013 arm_asm_output_labelref (FILE, NAME)
2015 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
2016 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2017 if (TARGET_THUMB2) \
2018 thumb2_asm_output_opcode (STREAM);
2020 /* The EABI specifies that constructors should go in .init_array.
2021 Other targets use .ctors for compatibility. */
2022 #ifndef ARM_EABI_CTORS_SECTION_OP
2023 #define ARM_EABI_CTORS_SECTION_OP \
2024 "\t.section\t.init_array,\"aw\",%init_array"
2026 #ifndef ARM_EABI_DTORS_SECTION_OP
2027 #define ARM_EABI_DTORS_SECTION_OP \
2028 "\t.section\t.fini_array,\"aw\",%fini_array"
2030 #define ARM_CTORS_SECTION_OP \
2031 "\t.section\t.ctors,\"aw\",%progbits"
2032 #define ARM_DTORS_SECTION_OP \
2033 "\t.section\t.dtors,\"aw\",%progbits"
2035 /* Define CTORS_SECTION_ASM_OP. */
2036 #undef CTORS_SECTION_ASM_OP
2037 #undef DTORS_SECTION_ASM_OP
2039 # define CTORS_SECTION_ASM_OP \
2040 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2041 # define DTORS_SECTION_ASM_OP \
2042 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2043 #else /* !defined (IN_LIBGCC2) */
2044 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2045 so we cannot use the definition above. */
2046 # ifdef __ARM_EABI__
2047 /* The .ctors section is not part of the EABI, so we do not define
2048 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2049 from trying to use it. We do define it when doing normal
2050 compilation, as .init_array can be used instead of .ctors. */
2051 /* There is no need to emit begin or end markers when using
2052 init_array; the dynamic linker will compute the size of the
2053 array itself based on special symbols created by the static
2054 linker. However, we do need to arrange to set up
2055 exception-handling here. */
2056 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2057 # define CTOR_LIST_END /* empty */
2058 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2059 # define DTOR_LIST_END /* empty */
2060 # else /* !defined (__ARM_EABI__) */
2061 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2062 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2063 # endif /* !defined (__ARM_EABI__) */
2064 #endif /* !defined (IN_LIBCC2) */
2066 /* True if the operating system can merge entities with vague linkage
2067 (e.g., symbols in COMDAT group) during dynamic linking. */
2068 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2069 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2072 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2074 #ifdef TARGET_UNWIND_INFO
2075 #define ARM_EABI_UNWIND_TABLES \
2076 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2078 #define ARM_EABI_UNWIND_TABLES 0
2081 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2082 and check its validity for a certain class.
2083 We have two alternate definitions for each of them.
2084 The usual definition accepts all pseudo regs; the other rejects
2085 them unless they have been allocated suitable hard regs.
2086 The symbol REG_OK_STRICT causes the latter definition to be used.
2087 Thumb-2 has the same restrictions as arm. */
2088 #ifndef REG_OK_STRICT
2090 #define ARM_REG_OK_FOR_BASE_P(X) \
2091 (REGNO (X) <= LAST_ARM_REGNUM \
2092 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2093 || REGNO (X) == FRAME_POINTER_REGNUM \
2094 || REGNO (X) == ARG_POINTER_REGNUM)
2096 #define ARM_REG_OK_FOR_INDEX_P(X) \
2097 ((REGNO (X) <= LAST_ARM_REGNUM \
2098 && REGNO (X) != STACK_POINTER_REGNUM) \
2099 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2100 || REGNO (X) == FRAME_POINTER_REGNUM \
2101 || REGNO (X) == ARG_POINTER_REGNUM)
2103 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2104 (REGNO (X) <= LAST_LO_REGNUM \
2105 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2106 || (GET_MODE_SIZE (MODE) >= 4 \
2107 && (REGNO (X) == STACK_POINTER_REGNUM \
2108 || (X) == hard_frame_pointer_rtx \
2109 || (X) == arg_pointer_rtx)))
2111 #define REG_STRICT_P 0
2113 #else /* REG_OK_STRICT */
2115 #define ARM_REG_OK_FOR_BASE_P(X) \
2116 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2118 #define ARM_REG_OK_FOR_INDEX_P(X) \
2119 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2121 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2122 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2124 #define REG_STRICT_P 1
2126 #endif /* REG_OK_STRICT */
2128 /* Now define some helpers in terms of the above. */
2130 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2132 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2133 : ARM_REG_OK_FOR_BASE_P (X))
2135 /* For 16-bit Thumb, a valid index register is anything that can be used in
2136 a byte load instruction. */
2137 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2138 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2140 /* Nonzero if X is a hard reg that can be used as an index
2141 or if it is a pseudo reg. On the Thumb, the stack pointer
2143 #define REG_OK_FOR_INDEX_P(X) \
2145 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2146 : ARM_REG_OK_FOR_INDEX_P (X))
2148 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2149 For Thumb, we can not use SP + reg, so reject SP. */
2150 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2151 REG_OK_FOR_INDEX_P (X)
2153 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2154 that is a valid memory address for an instruction.
2155 The MODE argument is the machine mode for the MEM expression
2156 that wants to use this address. */
2158 #define ARM_BASE_REGISTER_RTX_P(X) \
2159 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2161 #define ARM_INDEX_REGISTER_RTX_P(X) \
2162 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2164 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2166 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2170 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2172 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2176 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2178 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2182 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2184 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2185 else if (TARGET_THUMB2) \
2186 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2187 else /* if (TARGET_THUMB1) */ \
2188 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2191 /* Try machine-dependent ways of modifying an illegitimate address
2192 to be legitimate. If we find one, return the new, valid address. */
2193 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2195 X = arm_legitimize_address (X, OLDX, MODE); \
2198 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2199 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2203 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2205 X = thumb_legitimize_address (X, OLDX, MODE); \
2208 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2211 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2212 else if (TARGET_THUMB2) \
2213 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2215 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2217 if (memory_address_p (MODE, X)) \
2221 /* Go to LABEL if ADDR (a legitimate address expression)
2222 has an effect that depends on the machine mode it is used for. */
2223 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2225 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2226 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2230 /* Nothing helpful to do for the Thumb */
2231 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2233 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2236 /* Specify the machine mode that this machine uses
2237 for the index in the tablejump instruction. */
2238 #define CASE_VECTOR_MODE Pmode
2240 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2242 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2243 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2244 : (max >= 0x200) ? HImode \
2247 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2248 unsigned is probably best, but may break some code. */
2249 #ifndef DEFAULT_SIGNED_CHAR
2250 #define DEFAULT_SIGNED_CHAR 0
2253 /* Max number of bytes we can move from memory to memory
2254 in one reasonably fast instruction. */
2258 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2260 /* Define if operations between registers always perform the operation
2261 on the full register even if a narrower mode is specified. */
2262 #define WORD_REGISTER_OPERATIONS
2264 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2265 will either zero-extend or sign-extend. The value of this macro should
2266 be the code that says which one of the two operations is implicitly
2267 done, UNKNOWN if none. */
2268 #define LOAD_EXTEND_OP(MODE) \
2269 (TARGET_THUMB ? ZERO_EXTEND : \
2270 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2271 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2273 /* Nonzero if access to memory by bytes is slow and undesirable. */
2274 #define SLOW_BYTE_ACCESS 0
2276 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2278 /* Immediate shift counts are truncated by the output routines (or was it
2279 the assembler?). Shift counts in a register are truncated by ARM. Note
2280 that the native compiler puts too large (> 32) immediate shift counts
2281 into a register and shifts by the register, letting the ARM decide what
2282 to do instead of doing that itself. */
2283 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2284 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2285 On the arm, Y in a register is used modulo 256 for the shift. Only for
2286 rotates is modulo 32 used. */
2287 /* #define SHIFT_COUNT_TRUNCATED 1 */
2289 /* All integers have the same format so truncation is easy. */
2290 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2292 /* Calling from registers is a massive pain. */
2293 #define NO_FUNCTION_CSE 1
2295 /* The machine modes of pointers and functions */
2296 #define Pmode SImode
2297 #define FUNCTION_MODE Pmode
2299 #define ARM_FRAME_RTX(X) \
2300 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2301 || (X) == arg_pointer_rtx)
2303 /* Moves to and from memory are quite expensive */
2304 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2305 (TARGET_32BIT ? 10 : \
2306 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2307 * (CLASS == LO_REGS ? 1 : 2)))
2309 /* Try to generate sequences that don't involve branches, we can then use
2310 conditional instructions */
2311 #define BRANCH_COST(speed_p, predictable_p) \
2312 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2314 /* Position Independent Code. */
2315 /* We decide which register to use based on the compilation options and
2316 the assembler in use; this is more general than the APCS restriction of
2317 using sb (r9) all the time. */
2318 extern unsigned arm_pic_register;
2320 /* The register number of the register used to address a table of static
2321 data addresses in memory. */
2322 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2324 /* We can't directly access anything that contains a symbol,
2325 nor can we indirect via the constant pool. One exception is
2326 UNSPEC_TLS, which is always PIC. */
2327 #define LEGITIMATE_PIC_OPERAND_P(X) \
2328 (!(symbol_mentioned_p (X) \
2329 || label_mentioned_p (X) \
2330 || (GET_CODE (X) == SYMBOL_REF \
2331 && CONSTANT_POOL_ADDRESS_P (X) \
2332 && (symbol_mentioned_p (get_pool_constant (X)) \
2333 || label_mentioned_p (get_pool_constant (X))))) \
2334 || tls_mentioned_p (X))
2336 /* We need to know when we are making a constant pool; this determines
2337 whether data needs to be in the GOT or can be referenced via a GOT
2339 extern int making_const_table;
2341 /* Handle pragmas for compatibility with Intel's compilers. */
2342 /* Also abuse this to register additional C specific EABI attributes. */
2343 #define REGISTER_TARGET_PRAGMAS() do { \
2344 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2345 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2346 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2347 arm_lang_object_attributes_init(); \
2350 /* Condition code information. */
2351 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2352 return the mode to be used for the comparison. */
2354 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2356 #define REVERSIBLE_CC_MODE(MODE) 1
2358 #define REVERSE_CONDITION(CODE,MODE) \
2359 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2360 ? reverse_condition_maybe_unordered (code) \
2361 : reverse_condition (code))
2363 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2366 if (GET_CODE (OP1) == CONST_INT \
2367 && ! (const_ok_for_arm (INTVAL (OP1)) \
2368 || (const_ok_for_arm (- INTVAL (OP1))))) \
2370 rtx const_op = OP1; \
2371 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2378 /* The arm5 clz instruction returns 32. */
2379 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2382 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2383 TARGET_THUMB2 ? "\t.thumb\n" : "")
2385 /* Output a push or a pop instruction (only used when profiling). */
2386 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2390 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2391 STACK_POINTER_REGNUM, REGNO); \
2393 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2397 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2401 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2402 STACK_POINTER_REGNUM, REGNO); \
2404 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2407 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2408 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2410 /* This is how to output a label which precedes a jumptable. Since
2411 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2412 #undef ASM_OUTPUT_CASE_LABEL
2413 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2416 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2417 ASM_OUTPUT_ALIGN (FILE, 2); \
2418 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2422 /* Make sure subsequent insns are aligned after a TBB. */
2423 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2426 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2427 ASM_OUTPUT_ALIGN (FILE, 1); \
2431 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2436 if (is_called_in_ARM_mode (DECL) \
2437 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2438 && crtl->is_thunk)) \
2439 fprintf (STREAM, "\t.code 32\n") ; \
2440 else if (TARGET_THUMB1) \
2441 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2443 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2445 if (TARGET_POKE_FUNCTION_NAME) \
2446 arm_poke_function_name (STREAM, (const char *) NAME); \
2450 /* For aliases of functions we use .thumb_set instead. */
2451 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2454 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2455 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2457 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2459 fprintf (FILE, "\t.thumb_set "); \
2460 assemble_name (FILE, LABEL1); \
2461 fprintf (FILE, ","); \
2462 assemble_name (FILE, LABEL2); \
2463 fprintf (FILE, "\n"); \
2466 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2470 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2471 /* To support -falign-* switches we need to use .p2align so
2472 that alignment directives in code sections will be padded
2473 with no-op instructions, rather than zeroes. */
2474 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2477 if ((MAX_SKIP) == 0) \
2478 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2480 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2481 (int) (LOG), (int) (MAX_SKIP)); \
2485 /* Add two bytes to the length of conditionally executed Thumb-2
2486 instructions for the IT instruction. */
2487 #define ADJUST_INSN_LENGTH(insn, length) \
2488 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2491 /* Only perform branch elimination (by making instructions conditional) if
2492 we're optimizing. For Thumb-2 check if any IT instructions need
2494 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2495 if (TARGET_ARM && optimize) \
2496 arm_final_prescan_insn (INSN); \
2497 else if (TARGET_THUMB2) \
2498 thumb2_final_prescan_insn (INSN); \
2499 else if (TARGET_THUMB1) \
2500 thumb1_final_prescan_insn (INSN)
2502 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2503 (CODE == '@' || CODE == '|' || CODE == '.' \
2504 || CODE == '(' || CODE == ')' || CODE == '#' \
2505 || (TARGET_32BIT && (CODE == '?')) \
2506 || (TARGET_THUMB2 && (CODE == '!')) \
2507 || (TARGET_THUMB && (CODE == '_')))
2509 /* Output an operand of an instruction. */
2510 #define PRINT_OPERAND(STREAM, X, CODE) \
2511 arm_print_operand (STREAM, X, CODE)
2513 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2514 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2515 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2516 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2517 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2518 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2521 /* Output the address of an operand. */
2522 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2524 int is_minus = GET_CODE (X) == MINUS; \
2526 if (GET_CODE (X) == REG) \
2527 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2528 else if (GET_CODE (X) == PLUS || is_minus) \
2530 rtx base = XEXP (X, 0); \
2531 rtx index = XEXP (X, 1); \
2532 HOST_WIDE_INT offset = 0; \
2533 if (GET_CODE (base) != REG \
2534 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2536 /* Ensure that BASE is a register. */ \
2537 /* (one of them must be). */ \
2538 /* Also ensure the SP is not used as in index register. */ \
2543 switch (GET_CODE (index)) \
2546 offset = INTVAL (index); \
2549 asm_fprintf (STREAM, "[%r, #%wd]", \
2550 REGNO (base), offset); \
2554 asm_fprintf (STREAM, "[%r, %s%r]", \
2555 REGNO (base), is_minus ? "-" : "", \
2565 asm_fprintf (STREAM, "[%r, %s%r", \
2566 REGNO (base), is_minus ? "-" : "", \
2567 REGNO (XEXP (index, 0))); \
2568 arm_print_operand (STREAM, index, 'S'); \
2569 fputs ("]", STREAM); \
2574 gcc_unreachable (); \
2577 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2578 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2580 extern enum machine_mode output_memory_reference_mode; \
2582 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2584 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2585 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2586 REGNO (XEXP (X, 0)), \
2587 GET_CODE (X) == PRE_DEC ? "-" : "", \
2588 GET_MODE_SIZE (output_memory_reference_mode)); \
2590 asm_fprintf (STREAM, "[%r], #%s%d", \
2591 REGNO (XEXP (X, 0)), \
2592 GET_CODE (X) == POST_DEC ? "-" : "", \
2593 GET_MODE_SIZE (output_memory_reference_mode)); \
2595 else if (GET_CODE (X) == PRE_MODIFY) \
2597 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2598 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2599 asm_fprintf (STREAM, "#%wd]!", \
2600 INTVAL (XEXP (XEXP (X, 1), 1))); \
2602 asm_fprintf (STREAM, "%r]!", \
2603 REGNO (XEXP (XEXP (X, 1), 1))); \
2605 else if (GET_CODE (X) == POST_MODIFY) \
2607 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2608 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2609 asm_fprintf (STREAM, "#%wd", \
2610 INTVAL (XEXP (XEXP (X, 1), 1))); \
2612 asm_fprintf (STREAM, "%r", \
2613 REGNO (XEXP (XEXP (X, 1), 1))); \
2615 else output_addr_const (STREAM, X); \
2618 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2620 if (GET_CODE (X) == REG) \
2621 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2622 else if (GET_CODE (X) == POST_INC) \
2623 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2624 else if (GET_CODE (X) == PLUS) \
2626 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2627 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2628 asm_fprintf (STREAM, "[%r, #%wd]", \
2629 REGNO (XEXP (X, 0)), \
2630 INTVAL (XEXP (X, 1))); \
2632 asm_fprintf (STREAM, "[%r, %r]", \
2633 REGNO (XEXP (X, 0)), \
2634 REGNO (XEXP (X, 1))); \
2637 output_addr_const (STREAM, X); \
2640 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2642 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2644 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2646 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2647 if (arm_output_addr_const_extra (file, x) == FALSE) \
2650 /* A C expression whose value is RTL representing the value of the return
2651 address for the frame COUNT steps up from the current frame. */
2653 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2654 arm_return_addr (COUNT, FRAME)
2656 /* Mask of the bits in the PC that contain the real return address
2657 when running in 26-bit mode. */
2658 #define RETURN_ADDR_MASK26 (0x03fffffc)
2660 /* Pick up the return address upon entry to a procedure. Used for
2661 dwarf2 unwind information. This also enables the table driven
2663 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2664 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2666 /* Used to mask out junk bits from the return address, such as
2667 processor state, interrupt status, condition codes and the like. */
2668 #define MASK_RETURN_ADDR \
2669 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2670 in 26 bit mode, the condition codes must be masked out of the \
2671 return address. This does not apply to ARM6 and later processors \
2672 when running in 32 bit mode. */ \
2673 ((arm_arch4 || TARGET_THUMB) \
2674 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2675 : arm_gen_return_addr_mask ())
2678 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2679 symbolic names defined here (which would require too much duplication).
2688 ARM_BUILTIN_WAVG2BR,
2689 ARM_BUILTIN_WAVG2HR,
2716 ARM_BUILTIN_TMOVMSKB,
2717 ARM_BUILTIN_TMOVMSKH,
2718 ARM_BUILTIN_TMOVMSKW,
2727 ARM_BUILTIN_WPACKHSS,
2728 ARM_BUILTIN_WPACKWSS,
2729 ARM_BUILTIN_WPACKDSS,
2730 ARM_BUILTIN_WPACKHUS,
2731 ARM_BUILTIN_WPACKWUS,
2732 ARM_BUILTIN_WPACKDUS,
2737 ARM_BUILTIN_WADDSSB,
2738 ARM_BUILTIN_WADDSSH,
2739 ARM_BUILTIN_WADDSSW,
2740 ARM_BUILTIN_WADDUSB,
2741 ARM_BUILTIN_WADDUSH,
2742 ARM_BUILTIN_WADDUSW,
2746 ARM_BUILTIN_WSUBSSB,
2747 ARM_BUILTIN_WSUBSSH,
2748 ARM_BUILTIN_WSUBSSW,
2749 ARM_BUILTIN_WSUBUSB,
2750 ARM_BUILTIN_WSUBUSH,
2751 ARM_BUILTIN_WSUBUSW,
2758 ARM_BUILTIN_WCMPEQB,
2759 ARM_BUILTIN_WCMPEQH,
2760 ARM_BUILTIN_WCMPEQW,
2761 ARM_BUILTIN_WCMPGTUB,
2762 ARM_BUILTIN_WCMPGTUH,
2763 ARM_BUILTIN_WCMPGTUW,
2764 ARM_BUILTIN_WCMPGTSB,
2765 ARM_BUILTIN_WCMPGTSH,
2766 ARM_BUILTIN_WCMPGTSW,
2768 ARM_BUILTIN_TEXTRMSB,
2769 ARM_BUILTIN_TEXTRMSH,
2770 ARM_BUILTIN_TEXTRMSW,
2771 ARM_BUILTIN_TEXTRMUB,
2772 ARM_BUILTIN_TEXTRMUH,
2773 ARM_BUILTIN_TEXTRMUW,
2823 ARM_BUILTIN_WUNPCKIHB,
2824 ARM_BUILTIN_WUNPCKIHH,
2825 ARM_BUILTIN_WUNPCKIHW,
2826 ARM_BUILTIN_WUNPCKILB,
2827 ARM_BUILTIN_WUNPCKILH,
2828 ARM_BUILTIN_WUNPCKILW,
2830 ARM_BUILTIN_WUNPCKEHSB,
2831 ARM_BUILTIN_WUNPCKEHSH,
2832 ARM_BUILTIN_WUNPCKEHSW,
2833 ARM_BUILTIN_WUNPCKEHUB,
2834 ARM_BUILTIN_WUNPCKEHUH,
2835 ARM_BUILTIN_WUNPCKEHUW,
2836 ARM_BUILTIN_WUNPCKELSB,
2837 ARM_BUILTIN_WUNPCKELSH,
2838 ARM_BUILTIN_WUNPCKELSW,
2839 ARM_BUILTIN_WUNPCKELUB,
2840 ARM_BUILTIN_WUNPCKELUH,
2841 ARM_BUILTIN_WUNPCKELUW,
2843 ARM_BUILTIN_THREAD_POINTER,
2845 ARM_BUILTIN_NEON_BASE,
2847 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2850 /* Do not emit .note.GNU-stack by default. */
2851 #ifndef NEED_INDICATE_EXEC_STACK
2852 #define NEED_INDICATE_EXEC_STACK 0
2855 #endif /* ! GCC_ARM_H */
OSDN Git Service
