1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
39 #include "config/vxworks-dummy.h"
41 /* The architecture define. */
42 extern char arm_arch_name[];
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
51 builtin_define ("__APCS_32__"); \
53 builtin_define ("__thumb__"); \
55 builtin_define ("__thumb2__"); \
59 builtin_define ("__ARMEB__"); \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
67 builtin_define ("__ARMEL__"); \
69 builtin_define ("__THUMBEL__"); \
72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
76 builtin_define ("__VFP_FP__"); \
79 builtin_define ("__ARM_NEON__"); \
81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
83 if (arm_cpp_interwork) \
84 builtin_define ("__THUMB_INTERWORK__"); \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
96 if (TARGET_AAPCS_BASED) \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
99 builtin_define ("__ARM_PCS_VFP"); \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
101 builtin_define ("__ARM_PCS"); \
102 builtin_define ("__ARM_EABI__"); \
106 /* The various ARM cores. */
109 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
111 #include "arm-cores.def"
113 /* Used to indicate that no processor has been specified. */
119 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
121 #include "arm-cores.def"
126 /* The processor for which instructions should be scheduled. */
127 extern enum processor_type arm_tune;
129 enum arm_sync_generator_tag
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
135 /* Wrapper to pass around a polymorphic pointer to a sync instruction
137 struct arm_sync_generator
139 enum arm_sync_generator_tag op;
142 rtx (* omn) (rtx, rtx, rtx);
143 rtx (* omrn) (rtx, rtx, rtx, rtx);
147 typedef enum arm_cond_code
149 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
150 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
154 extern arm_cc arm_current_cc;
156 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
158 extern int arm_target_label;
159 extern int arm_ccfsm_state;
160 extern GTY(()) rtx arm_target_insn;
161 /* The label of the current constant pool. */
162 extern rtx pool_vector_label;
163 /* Set to 1 when a return insn is output, this means that the epilogue
165 extern int return_used_this_function;
166 /* Callback to output language specific object attributes. */
167 extern void (*arm_lang_output_object_attributes_hook)(void);
169 /* Just in case configure has failed to define anything. */
170 #ifndef TARGET_CPU_DEFAULT
171 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
176 #define CPP_SPEC "%(subtarget_cpp_spec) \
177 %{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179 %{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
186 /* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
190 Each subgrouping contains a string constant, that defines the
191 specification name, and a string constant that used by the GCC driver
194 Do not define this macro if it does not need to do anything. */
195 #define EXTRA_SPECS \
196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
197 SUBTARGET_EXTRA_SPECS
199 #ifndef SUBTARGET_EXTRA_SPECS
200 #define SUBTARGET_EXTRA_SPECS
203 #ifndef SUBTARGET_CPP_SPEC
204 #define SUBTARGET_CPP_SPEC ""
207 /* Run-time Target Specification. */
208 #ifndef TARGET_VERSION
209 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
212 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
213 /* Use hardware floating point instructions. */
214 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215 /* Use hardware floating point calling convention. */
216 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
217 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
220 #define TARGET_IWMMXT (arm_arch_iwmmxt)
221 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
223 #define TARGET_ARM (! TARGET_THUMB)
224 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
225 #define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
228 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
229 #define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
232 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
235 /* Only 16-bit thumb code. */
236 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237 /* Arm or Thumb-2 32-bit code. */
238 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239 /* 32-bit Thumb-2 code. */
240 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
242 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
243 /* FPA emulator without LFM. */
244 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
246 /* The following two macros concern the ability to execute coprocessor
247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
251 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
252 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
254 /* FPU supports VFPv3 instructions. */
255 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
257 /* FPU only supports VFP single-precision instructions. */
258 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
260 /* FPU supports VFP double-precision instructions. */
261 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
263 /* FPU supports half-precision floating-point with NEON element load/store. */
264 #define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
267 /* FPU supports VFP half-precision floating-point. */
268 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
270 /* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
274 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
275 && TARGET_VFP && arm_fpu_desc->neon)
277 /* "DSP" multiply instructions, eg. SMULxy. */
278 #define TARGET_DSP_MULTIPLY \
279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
280 /* Integer SIMD instructions, and extend-accumulate instructions. */
281 #define TARGET_INT_SIMD \
282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
284 /* Should MOVW/MOVT be used in preference to a constant pool. */
285 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
287 /* We could use unified syntax for arm mode, but for now we just use it
289 #define TARGET_UNIFIED_ASM TARGET_THUMB2
291 /* Nonzero if this chip provides the DMB instruction. */
292 #define TARGET_HAVE_DMB (arm_arch7)
294 /* Nonzero if this chip implements a memory barrier via CP15. */
295 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
297 /* Nonzero if this chip implements a memory barrier instruction. */
298 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
300 /* Nonzero if this chip supports ldrex and strex */
301 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
303 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
306 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
311 #define TARGET_BPABI false
314 /* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
324 #define OPTION_DEFAULT_SPECS \
325 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
326 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
327 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
329 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
330 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
331 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
332 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
334 /* Which floating point model to use. */
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
354 extern const struct arm_fpu_desc
357 enum arm_fp_model model;
359 enum vfp_reg_type regs;
364 /* Which floating point hardware to schedule for. */
365 extern int arm_fpu_attr;
370 ARM_FLOAT_ABI_SOFTFP,
374 extern enum float_abi_type arm_float_abi;
376 #ifndef TARGET_DEFAULT_FLOAT_ABI
377 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
380 /* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
384 enum arm_fp16_format_type
386 ARM_FP16_FORMAT_NONE = 0,
387 ARM_FP16_FORMAT_IEEE = 1,
388 ARM_FP16_FORMAT_ALTERNATIVE = 2
391 extern enum arm_fp16_format_type arm_fp16_format;
392 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
395 /* Which ABI to use. */
405 extern enum arm_abi_type arm_abi;
407 #ifndef ARM_DEFAULT_ABI
408 #define ARM_DEFAULT_ABI ARM_ABI_APCS
411 /* Which thread pointer access sequence to use. */
418 extern enum arm_tp_type target_thread_pointer;
420 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
421 extern int arm_arch3m;
423 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
424 extern int arm_arch4;
426 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
427 extern int arm_arch4t;
429 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
430 extern int arm_arch5;
432 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
433 extern int arm_arch5e;
435 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
436 extern int arm_arch6;
438 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
439 extern int arm_arch6k;
441 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
442 extern int arm_arch7;
444 /* Nonzero if instructions not present in the 'M' profile can be used. */
445 extern int arm_arch_notm;
447 /* Nonzero if instructions present in ARMv7E-M can be used. */
448 extern int arm_arch7em;
450 /* Nonzero if this chip can benefit from load scheduling. */
451 extern int arm_ld_sched;
453 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
454 extern int thumb_code;
456 /* Nonzero if generating Thumb-1 code. */
457 extern int thumb1_code;
459 /* Nonzero if this chip is a StrongARM. */
460 extern int arm_tune_strongarm;
462 /* Nonzero if this chip is a Cirrus variant. */
463 extern int arm_arch_cirrus;
465 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
466 extern int arm_arch_iwmmxt;
468 /* Nonzero if this chip is an XScale. */
469 extern int arm_arch_xscale;
471 /* Nonzero if tuning for XScale. */
472 extern int arm_tune_xscale;
474 /* Nonzero if tuning for stores via the write buffer. */
475 extern int arm_tune_wbuf;
477 /* Nonzero if tuning for Cortex-A9. */
478 extern int arm_tune_cortex_a9;
480 /* Nonzero if we should define __THUMB_INTERWORK__ in the
482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
485 extern int arm_cpp_interwork;
487 /* Nonzero if chip supports Thumb 2. */
488 extern int arm_arch_thumb2;
490 /* Nonzero if chip supports integer division instruction. */
491 extern int arm_arch_hwdiv;
493 #ifndef TARGET_DEFAULT
494 #define TARGET_DEFAULT (MASK_APCS_FRAME)
497 /* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
499 #define CAN_DEBUG_WITHOUT_FP
501 /* Nonzero if PIC code requires explicit qualifiers to generate
502 PLT and GOT relocs rather than the assembler doing so implicitly.
503 Subtargets can override these if required. */
504 #ifndef NEED_GOT_RELOC
505 #define NEED_GOT_RELOC 0
507 #ifndef NEED_PLT_RELOC
508 #define NEED_PLT_RELOC 0
511 /* Nonzero if we need to refer to the GOT with a PC-relative
512 offset. In other words, generate
514 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
518 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
520 The default is true, which matches NetBSD. Subtargets can
521 override this if required. */
526 /* Target machine storage Layout. */
529 /* Define this macro if it is advisable to hold scalars in registers
530 in a wider mode than that declared by the program. In such cases,
531 the value is constrained to be within the bounds of the declared
532 type, but kept valid in the wider mode. The signedness of the
533 extension may differ from that of the type. */
535 /* It is far faster to zero extend chars than to sign extend them */
537 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
538 if (GET_MODE_CLASS (MODE) == MODE_INT \
539 && GET_MODE_SIZE (MODE) < 4) \
541 if (MODE == QImode) \
543 else if (MODE == HImode) \
548 /* Define this if most significant bit is lowest numbered
549 in instructions that operate on numbered bit-fields. */
550 #define BITS_BIG_ENDIAN 0
552 /* Define this if most significant byte of a word is the lowest numbered.
553 Most ARM processors are run in little endian mode, so that is the default.
554 If you want to have it run-time selectable, change the definition in a
555 cover file to be TARGET_BIG_ENDIAN. */
556 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
558 /* Define this if most significant word of a multiword number is the lowest
560 This is always false, even when in big-endian mode. */
561 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
563 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
564 on processor pre-defineds when compiling libgcc2.c. */
565 #if defined(__ARMEB__) && !defined(__ARMWEL__)
566 #define LIBGCC2_WORDS_BIG_ENDIAN 1
568 #define LIBGCC2_WORDS_BIG_ENDIAN 0
571 /* Define this if most significant word of doubles is the lowest numbered.
572 The rules are different based on whether or not we use FPA-format,
573 VFP-format or some other floating point co-processor's format doubles. */
574 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
576 #define UNITS_PER_WORD 4
578 /* True if natural alignment is used for doubleword types. */
579 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
581 #define DOUBLEWORD_ALIGNMENT 64
583 #define PARM_BOUNDARY 32
585 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
587 #define PREFERRED_STACK_BOUNDARY \
588 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
590 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
592 /* The lowest bit is used to indicate Thumb-mode functions, so the
593 vbit must go into the delta field of pointers to member
595 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
597 #define EMPTY_FIELD_BOUNDARY 32
599 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
601 /* XXX Blah -- this macro is used directly by libobjc. Since it
602 supports no vector modes, cut out the complexity and fall back
603 on BIGGEST_FIELD_ALIGNMENT. */
604 #ifdef IN_TARGET_LIBS
605 #define BIGGEST_FIELD_ALIGNMENT 64
608 /* Make strings word-aligned so strcpy from constants will be faster. */
609 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
611 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
612 ((TREE_CODE (EXP) == STRING_CST \
614 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
615 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
617 /* Align definitions of arrays, unions and structures so that
618 initializations and copies can be made more efficient. This is not
619 ABI-changing, so it only affects places where we can see the
620 definition. Increasing the alignment tends to introduce padding,
621 so don't do this when optimizing for size/conserving stack space. */
622 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
623 (((COND) && ((ALIGN) < BITS_PER_WORD) \
624 && (TREE_CODE (EXP) == ARRAY_TYPE \
625 || TREE_CODE (EXP) == UNION_TYPE \
626 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
628 /* Align global data. */
629 #define DATA_ALIGNMENT(EXP, ALIGN) \
630 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
632 /* Similarly, make sure that objects on the stack are sensibly aligned. */
633 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
634 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
636 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
637 value set in previous versions of this toolchain was 8, which produces more
638 compact structures. The command line option -mstructure_size_boundary=<n>
639 can be used to change this value. For compatibility with the ARM SDK
640 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
641 0020D) page 2-20 says "Structures are aligned on word boundaries".
642 The AAPCS specifies a value of 8. */
643 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
644 extern int arm_structure_size_boundary;
646 /* This is the value used to initialize arm_structure_size_boundary. If a
647 particular arm target wants to change the default value it should change
648 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
649 for an example of this. */
650 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
651 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
654 /* Nonzero if move instructions will actually fail to work
655 when given unaligned data. */
656 #define STRICT_ALIGNMENT 1
658 /* wchar_t is unsigned under the AAPCS. */
660 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
662 #define WCHAR_TYPE_SIZE BITS_PER_WORD
666 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
670 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
673 /* AAPCS requires that structure alignment is affected by bitfields. */
674 #ifndef PCC_BITFIELD_TYPE_MATTERS
675 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
679 /* Standard register usage. */
681 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
682 (S - saved over call).
684 r0 * argument word/integer result
687 r4-r8 S register variable
688 r9 S (rfp) register variable (real frame pointer)
690 r10 F S (sl) stack limit (used by -mapcs-stack-check)
691 r11 F S (fp) argument pointer
692 r12 (ip) temp workspace
693 r13 F S (sp) lower end of current stack frame
694 r14 (lr) link address/workspace
695 r15 F (pc) program counter
697 f0 floating point result
698 f1-f3 floating point scratch
700 f4-f7 S floating point variable
702 cc This is NOT a real register, but is used internally
703 to represent things that use or set the condition
705 sfp This isn't either. It is used during rtl generation
706 since the offset between the frame pointer and the
707 auto's isn't known until after register allocation.
708 afp Nor this, we only need this because of non-local
709 goto. Without it fp appears to be used and the
710 elimination code won't get rid of sfp. It tracks
711 fp exactly at all times.
713 *: See CONDITIONAL_REGISTER_USAGE */
716 mvf0 Cirrus floating point result
717 mvf1-mvf3 Cirrus floating point scratch
718 mvf4-mvf15 S Cirrus floating point variable. */
720 /* s0-s15 VFP scratch (aka d0-d7).
721 s16-s31 S VFP variable (aka d8-d15).
722 vfpcc Not a real register. Represents the VFP condition
725 /* The stack backtrace structure is as follows:
726 fp points to here: | save code pointer | [fp]
727 | return link value | [fp, #-4]
728 | return sp value | [fp, #-8]
729 | return fp value | [fp, #-12]
730 [| saved r10 value |]
741 [| saved f7 value |] three words
742 [| saved f6 value |] three words
743 [| saved f5 value |] three words
744 [| saved f4 value |] three words
745 r0-r3 are not normally saved in a C function. */
747 /* 1 for registers that have pervasive standard uses
748 and are not available for the register allocator. */
749 #define FIXED_REGISTERS \
771 /* 1 for registers not available across function calls.
772 These must include the FIXED_REGISTERS and also any
773 registers that can be used without being saved.
774 The latter must include the registers where values are returned
775 and the register where structure-value addresses are passed.
776 Aside from that, you can include as many other registers as you like.
777 The CC is not preserved over function calls on the ARM 6, so it is
778 easier to assume this for all. SFP is preserved, since FP is. */
779 #define CALL_USED_REGISTERS \
801 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
802 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
805 #define CONDITIONAL_REGISTER_USAGE \
809 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
811 for (regno = FIRST_FPA_REGNUM; \
812 regno <= LAST_FPA_REGNUM; ++regno) \
813 fixed_regs[regno] = call_used_regs[regno] = 1; \
816 if (TARGET_THUMB1 && optimize_size) \
818 /* When optimizing for size on Thumb-1, it's better not \
819 to use the HI regs, because of the overhead of \
821 for (regno = FIRST_HI_REGNUM; \
822 regno <= LAST_HI_REGNUM; ++regno) \
823 fixed_regs[regno] = call_used_regs[regno] = 1; \
826 /* The link register can be clobbered by any branch insn, \
827 but we have no way to track that at present, so mark \
828 it as unavailable. */ \
830 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
832 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
834 if (TARGET_MAVERICK) \
836 for (regno = FIRST_FPA_REGNUM; \
837 regno <= LAST_FPA_REGNUM; ++ regno) \
838 fixed_regs[regno] = call_used_regs[regno] = 1; \
839 for (regno = FIRST_CIRRUS_FP_REGNUM; \
840 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
842 fixed_regs[regno] = 0; \
843 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
848 /* VFPv3 registers are disabled when earlier VFP \
849 versions are selected due to the definition of \
850 LAST_VFP_REGNUM. */ \
851 for (regno = FIRST_VFP_REGNUM; \
852 regno <= LAST_VFP_REGNUM; ++ regno) \
854 fixed_regs[regno] = 0; \
855 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
856 || regno >= FIRST_VFP_REGNUM + 32; \
861 if (TARGET_REALLY_IWMMXT) \
863 regno = FIRST_IWMMXT_GR_REGNUM; \
864 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
865 and wCG1 as call-preserved registers. The 2002/11/21 \
866 revision changed this so that all wCG registers are \
867 scratch registers. */ \
868 for (regno = FIRST_IWMMXT_GR_REGNUM; \
869 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
870 fixed_regs[regno] = 0; \
871 /* The XScale ABI has wR0 - wR9 as scratch registers, \
872 the rest as call-preserved registers. */ \
873 for (regno = FIRST_IWMMXT_REGNUM; \
874 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
876 fixed_regs[regno] = 0; \
877 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
881 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
883 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
884 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
886 else if (TARGET_APCS_STACK) \
888 fixed_regs[10] = 1; \
889 call_used_regs[10] = 1; \
891 /* -mcaller-super-interworking reserves r11 for calls to \
892 _interwork_r11_call_via_rN(). Making the register global \
893 is an easy way of ensuring that it remains valid for all \
895 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
896 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
898 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
899 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
900 if (TARGET_CALLER_INTERWORKING) \
901 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
903 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
906 /* These are a couple of extensions to the formats accepted
908 %@ prints out ASM_COMMENT_START
909 %r prints out REGISTER_PREFIX reg_names[arg] */
910 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
912 fputs (ASM_COMMENT_START, FILE); \
916 fputs (REGISTER_PREFIX, FILE); \
917 fputs (reg_names [va_arg (ARGS, int)], FILE); \
920 /* Round X up to the nearest word. */
921 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
923 /* Convert fron bytes to ints. */
924 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
926 /* The number of (integer) registers required to hold a quantity of type MODE.
927 Also used for VFP registers. */
928 #define ARM_NUM_REGS(MODE) \
929 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
931 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
932 #define ARM_NUM_REGS2(MODE, TYPE) \
933 ARM_NUM_INTS ((MODE) == BLKmode ? \
934 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
936 /* The number of (integer) argument register available. */
937 #define NUM_ARG_REGS 4
939 /* And similarly for the VFP. */
940 #define NUM_VFP_ARG_REGS 16
942 /* Return the register number of the N'th (integer) argument. */
943 #define ARG_REGISTER(N) (N - 1)
945 /* Specify the registers used for certain standard purposes.
946 The values of these macros are register numbers. */
948 /* The number of the last argument register. */
949 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
951 /* The numbers of the Thumb register ranges. */
952 #define FIRST_LO_REGNUM 0
953 #define LAST_LO_REGNUM 7
954 #define FIRST_HI_REGNUM 8
955 #define LAST_HI_REGNUM 11
957 /* Overridden by config/arm/bpabi.h. */
958 #ifndef ARM_UNWIND_INFO
959 #define ARM_UNWIND_INFO 0
962 /* Use r0 and r1 to pass exception handling information. */
963 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
965 /* The register that holds the return address in exception handlers. */
966 #define ARM_EH_STACKADJ_REGNUM 2
967 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
969 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
970 as an invisible last argument (possible since varargs don't exist in
971 Pascal), so the following is not true. */
972 #define STATIC_CHAIN_REGNUM 12
974 /* Define this to be where the real frame pointer is if it is not possible to
975 work out the offset between the frame pointer and the automatic variables
976 until after register allocation has taken place. FRAME_POINTER_REGNUM
977 should point to a special register that we will make sure is eliminated.
979 For the Thumb we have another problem. The TPCS defines the frame pointer
980 as r11, and GCC believes that it is always possible to use the frame pointer
981 as base register for addressing purposes. (See comments in
982 find_reloads_address()). But - the Thumb does not allow high registers,
983 including r11, to be used as base address registers. Hence our problem.
985 The solution used here, and in the old thumb port is to use r7 instead of
986 r11 as the hard frame pointer and to have special code to generate
987 backtrace structures on the stack (if required to do so via a command line
988 option) using r11. This is the only 'user visible' use of r11 as a frame
990 #define ARM_HARD_FRAME_POINTER_REGNUM 11
991 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
993 #define HARD_FRAME_POINTER_REGNUM \
995 ? ARM_HARD_FRAME_POINTER_REGNUM \
996 : THUMB_HARD_FRAME_POINTER_REGNUM)
998 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
999 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1001 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1003 /* Register to use for pushing function arguments. */
1004 #define STACK_POINTER_REGNUM SP_REGNUM
1006 /* ARM floating pointer registers. */
1007 #define FIRST_FPA_REGNUM 16
1008 #define LAST_FPA_REGNUM 23
1009 #define IS_FPA_REGNUM(REGNUM) \
1010 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
1012 #define FIRST_IWMMXT_GR_REGNUM 43
1013 #define LAST_IWMMXT_GR_REGNUM 46
1014 #define FIRST_IWMMXT_REGNUM 47
1015 #define LAST_IWMMXT_REGNUM 62
1016 #define IS_IWMMXT_REGNUM(REGNUM) \
1017 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1018 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1019 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1021 /* Base register for access to local variables of the function. */
1022 #define FRAME_POINTER_REGNUM 25
1024 /* Base register for access to arguments of the function. */
1025 #define ARG_POINTER_REGNUM 26
1027 #define FIRST_CIRRUS_FP_REGNUM 27
1028 #define LAST_CIRRUS_FP_REGNUM 42
1029 #define IS_CIRRUS_REGNUM(REGNUM) \
1030 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1032 #define FIRST_VFP_REGNUM 63
1033 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
1034 #define LAST_VFP_REGNUM \
1035 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1037 #define IS_VFP_REGNUM(REGNUM) \
1038 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1040 /* VFP registers are split into two types: those defined by VFP versions < 3
1041 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1042 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1043 in various parts of the backend, we implement as "fake" single-precision
1044 registers (which would be S32-S63, but cannot be used in that way). The
1045 following macros define these ranges of registers. */
1046 #define LAST_LO_VFP_REGNUM 94
1047 #define FIRST_HI_VFP_REGNUM 95
1048 #define LAST_HI_VFP_REGNUM 126
1050 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1051 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1053 /* DFmode values are only valid in even register pairs. */
1054 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1055 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1057 /* Neon Quad values must start at a multiple of four registers. */
1058 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1059 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1061 /* Neon structures of vectors must be in even register pairs and there
1062 must be enough registers available. Because of various patterns
1063 requiring quad registers, we require them to start at a multiple of
1065 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1066 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1067 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1069 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1070 /* + 16 Cirrus registers take us up to 43. */
1071 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1072 /* VFP (VFP3) adds 32 (64) + 1 more. */
1073 #define FIRST_PSEUDO_REGISTER 128
1075 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1077 /* Value should be nonzero if functions must have frame pointers.
1078 Zero means the frame pointer need not be set up (and parms may be accessed
1079 via the stack pointer) in functions that seem suitable.
1080 If we have to have a frame pointer we might as well make use of it.
1081 APCS says that the frame pointer does not need to be pushed in leaf
1082 functions, or simple tail call functions. */
1084 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1085 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1088 /* Return number of consecutive hard regs needed starting at reg REGNO
1089 to hold something of mode MODE.
1090 This is ordinarily the length in words of a value of mode MODE
1091 but can be less for certain modes in special long registers.
1093 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1095 #define HARD_REGNO_NREGS(REGNO, MODE) \
1097 && REGNO >= FIRST_FPA_REGNUM \
1098 && REGNO != FRAME_POINTER_REGNUM \
1099 && REGNO != ARG_POINTER_REGNUM) \
1100 && !IS_VFP_REGNUM (REGNO) \
1101 ? 1 : ARM_NUM_REGS (MODE))
1103 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1104 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1105 arm_hard_regno_mode_ok ((REGNO), (MODE))
1107 /* Value is 1 if it is a good idea to tie two pseudo registers
1108 when one has mode MODE1 and one has mode MODE2.
1109 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1110 for any hard reg, then this must be 0 for correct output. */
1111 #define MODES_TIEABLE_P(MODE1, MODE2) \
1112 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1114 #define VALID_IWMMXT_REG_MODE(MODE) \
1115 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1117 /* Modes valid for Neon D registers. */
1118 #define VALID_NEON_DREG_MODE(MODE) \
1119 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1120 || (MODE) == V2SFmode || (MODE) == DImode)
1122 /* Modes valid for Neon Q registers. */
1123 #define VALID_NEON_QREG_MODE(MODE) \
1124 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1125 || (MODE) == V4SFmode || (MODE) == V2DImode)
1127 /* Structure modes valid for Neon registers. */
1128 #define VALID_NEON_STRUCT_MODE(MODE) \
1129 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1130 || (MODE) == CImode || (MODE) == XImode)
1132 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1133 extern int arm_regs_in_sequence[];
1135 /* The order in which register should be allocated. It is good to use ip
1136 since no saving is required (though calls clobber it) and it never contains
1137 function parameters. It is quite good to use lr since other calls may
1138 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1139 least likely to contain a function parameter; in addition results are
1141 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1142 then D8-D15. The reason for doing this is to attempt to reduce register
1143 pressure when both single- and double-precision registers are used in a
1146 #define REG_ALLOC_ORDER \
1148 3, 2, 1, 0, 12, 14, 4, 5, \
1149 6, 7, 8, 10, 9, 11, 13, 15, \
1150 16, 17, 18, 19, 20, 21, 22, 23, \
1151 27, 28, 29, 30, 31, 32, 33, 34, \
1152 35, 36, 37, 38, 39, 40, 41, 42, \
1153 43, 44, 45, 46, 47, 48, 49, 50, \
1154 51, 52, 53, 54, 55, 56, 57, 58, \
1157 95, 96, 97, 98, 99, 100, 101, 102, \
1158 103, 104, 105, 106, 107, 108, 109, 110, \
1159 111, 112, 113, 114, 115, 116, 117, 118, \
1160 119, 120, 121, 122, 123, 124, 125, 126, \
1161 78, 77, 76, 75, 74, 73, 72, 71, \
1162 70, 69, 68, 67, 66, 65, 64, 63, \
1163 79, 80, 81, 82, 83, 84, 85, 86, \
1164 87, 88, 89, 90, 91, 92, 93, 94, \
1168 /* Use different register alloc ordering for Thumb. */
1169 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1171 /* Tell IRA to use the order we define rather than messing it up with its
1172 own cost calculations. */
1173 #define HONOR_REG_ALLOC_ORDER
1175 /* Interrupt functions can only use registers that have already been
1176 saved by the prologue, even if they would normally be
1178 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1179 (! IS_INTERRUPT (cfun->machine->func_type) || \
1180 df_regs_ever_live_p (DST))
1182 /* Register and constant classes. */
1184 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1185 Now that the Thumb is involved it has become more complicated. */
1209 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1211 /* Give names of register classes as strings for dump file. */
1212 #define REG_CLASS_NAMES \
1234 /* Define which registers fit in which classes.
1235 This is an initializer for a vector of HARD_REG_SET
1236 of length N_REG_CLASSES. */
1237 #define REG_CLASS_CONTENTS \
1239 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1240 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1241 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1242 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1243 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1244 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1245 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1246 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1247 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1248 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1249 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1250 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1251 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1252 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1253 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1254 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1255 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1256 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1259 /* Any of the VFP register classes. */
1260 #define IS_VFP_CLASS(X) \
1261 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1262 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1264 /* The same information, inverted:
1265 Return the class number of the smallest class containing
1266 reg number REGNO. This could be a conditional expression
1267 or could index an array. */
1268 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1270 /* The following macro defines cover classes for Integrated Register
1271 Allocator. Cover classes is a set of non-intersected register
1272 classes covering all hard registers used for register allocation
1273 purpose. Any move between two registers of a cover class should be
1274 cheaper than load or store of the registers. The macro value is
1275 array of register classes with LIM_REG_CLASSES used as the end
1278 #define IRA_COVER_CLASSES \
1280 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1284 /* FPA registers can't do subreg as all values are reformatted to internal
1285 precision. VFP registers may only be accessed in the mode they
1287 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1288 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1289 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1290 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1293 /* The class value for index registers, and the one for base regs. */
1294 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1295 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1297 /* For the Thumb the high registers cannot be used as base registers
1298 when addressing quantities in QI or HI mode; if we don't know the
1299 mode, then we must be conservative. */
1300 #define MODE_BASE_REG_CLASS(MODE) \
1301 (TARGET_32BIT ? CORE_REGS : \
1302 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1304 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1305 instead of BASE_REGS. */
1306 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1308 /* When this hook returns true for MODE, the compiler allows
1309 registers explicitly used in the rtl to be used as spill registers
1310 but prevents the compiler from extending the lifetime of these
1312 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1313 arm_small_register_classes_for_mode_p
1315 /* Given an rtx X being reloaded into a reg required to be
1316 in class CLASS, return the class of reg to actually use.
1317 In general this is just CLASS, but for the Thumb core registers and
1318 immediate constants we prefer a LO_REGS class or a subset. */
1319 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1320 (TARGET_32BIT ? (CLASS) : \
1321 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1322 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1323 ? LO_REGS : (CLASS)))
1325 /* Must leave BASE_REGS reloads alone */
1326 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1327 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1328 ? ((true_regnum (X) == -1 ? LO_REGS \
1329 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1333 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1334 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1335 ? ((true_regnum (X) == -1 ? LO_REGS \
1336 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1340 /* Return the register class of a scratch register needed to copy IN into
1341 or out of a register in CLASS in MODE. If it can be done directly,
1342 NO_REGS is returned. */
1343 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1344 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1345 ((TARGET_VFP && TARGET_HARD_FLOAT \
1346 && IS_VFP_CLASS (CLASS)) \
1347 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1348 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1349 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1351 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1352 ? GENERAL_REGS : NO_REGS) \
1353 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1355 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1356 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1357 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1358 ((TARGET_VFP && TARGET_HARD_FLOAT \
1359 && IS_VFP_CLASS (CLASS)) \
1360 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1361 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1362 coproc_secondary_reload_class (MODE, X, TRUE) : \
1363 /* Cannot load constants into Cirrus registers. */ \
1364 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1365 && (CLASS) == CIRRUS_REGS \
1366 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1369 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1370 && CONSTANT_P (X)) \
1372 (((MODE) == HImode && ! arm_arch4 \
1373 && (GET_CODE (X) == MEM \
1374 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1375 && true_regnum (X) == -1))) \
1376 ? GENERAL_REGS : NO_REGS) \
1377 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1379 /* Try a machine-dependent way of reloading an illegitimate address
1380 operand. If we find one, push the reload and jump to WIN. This
1381 macro is used in only one place: `find_reloads_address' in reload.c.
1383 For the ARM, we wish to handle large displacements off a base
1384 register by splitting the addend across a MOV and the mem insn.
1385 This can cut the number of reloads needed. */
1386 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1389 if (GET_CODE (X) == PLUS \
1390 && GET_CODE (XEXP (X, 0)) == REG \
1391 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1392 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1393 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1395 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1396 HOST_WIDE_INT low, high; \
1398 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1399 low = ((val & 0xf) ^ 0x8) - 0x8; \
1400 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1401 /* Need to be careful, -256 is not a valid offset. */ \
1402 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1403 else if (MODE == SImode \
1404 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1405 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1406 /* Need to be careful, -4096 is not a valid offset. */ \
1407 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1408 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1409 /* Need to be careful, -256 is not a valid offset. */ \
1410 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1411 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1412 && TARGET_HARD_FLOAT && TARGET_FPA) \
1413 /* Need to be careful, -1024 is not a valid offset. */ \
1414 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1418 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1419 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1420 - (unsigned HOST_WIDE_INT) 0x80000000); \
1421 /* Check for overflow or zero */ \
1422 if (low == 0 || high == 0 || (high + low != val)) \
1425 /* Reload the high part into a base reg; leave the low part \
1427 X = gen_rtx_PLUS (GET_MODE (X), \
1428 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1431 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1432 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1433 VOIDmode, 0, 0, OPNUM, TYPE); \
1439 /* XXX If an HImode FP+large_offset address is converted to an HImode
1440 SP+large_offset address, then reload won't know how to fix it. It sees
1441 only that SP isn't valid for HImode, and so reloads the SP into an index
1442 register, but the resulting address is still invalid because the offset
1443 is too big. We fix it here instead by reloading the entire address. */
1444 /* We could probably achieve better results by defining PROMOTE_MODE to help
1445 cope with the variances between the Thumb's signed and unsigned byte and
1446 halfword load instructions. */
1447 /* ??? This should be safe for thumb2, but we may be able to do better. */
1448 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1450 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1458 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1460 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1462 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1464 /* Return the maximum number of consecutive registers
1465 needed to represent mode MODE in a register of class CLASS.
1466 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1467 #define CLASS_MAX_NREGS(CLASS, MODE) \
1468 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1470 /* If defined, gives a class of registers that cannot be used as the
1471 operand of a SUBREG that changes the mode of the object illegally. */
1473 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1474 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1475 it is typically more expensive than a single memory access. We set
1476 the cost to less than two memory accesses so that floating
1477 point to integer conversion does not go through memory. */
1478 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1480 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1481 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1482 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1483 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1484 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1485 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1486 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1487 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1488 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1491 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1493 /* Stack layout; function entry, exit and calling. */
1495 /* Define this if pushing a word on the stack
1496 makes the stack pointer a smaller address. */
1497 #define STACK_GROWS_DOWNWARD 1
1499 /* Define this to nonzero if the nominal address of the stack frame
1500 is at the high-address end of the local variables;
1501 that is, each additional local variable allocated
1502 goes at a more negative offset in the frame. */
1503 #define FRAME_GROWS_DOWNWARD 1
1505 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1506 When present, it is one word in size, and sits at the top of the frame,
1507 between the soft frame pointer and either r7 or r11.
1509 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1510 and only then if some outgoing arguments are passed on the stack. It would
1511 be tempting to also check whether the stack arguments are passed by indirect
1512 calls, but there seems to be no reason in principle why a post-reload pass
1513 couldn't convert a direct call into an indirect one. */
1514 #define CALLER_INTERWORKING_SLOT_SIZE \
1515 (TARGET_CALLER_INTERWORKING \
1516 && crtl->outgoing_args_size != 0 \
1517 ? UNITS_PER_WORD : 0)
1519 /* Offset within stack frame to start allocating local variables at.
1520 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1521 first local allocated. Otherwise, it is the offset to the BEGINNING
1522 of the first local allocated. */
1523 #define STARTING_FRAME_OFFSET 0
1525 /* If we generate an insn to push BYTES bytes,
1526 this says how many the stack pointer really advances by. */
1527 /* The push insns do not do this rounding implicitly.
1528 So don't define this. */
1529 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1531 /* Define this if the maximum size of all the outgoing args is to be
1532 accumulated and pushed during the prologue. The amount can be
1533 found in the variable crtl->outgoing_args_size. */
1534 #define ACCUMULATE_OUTGOING_ARGS 1
1536 /* Offset of first parameter from the argument pointer register value. */
1537 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1539 /* Define how to find the value returned by a library function
1540 assuming the value has mode MODE. */
1541 #define LIBCALL_VALUE(MODE) \
1542 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1543 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1544 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1545 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1546 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1547 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1548 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1549 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1550 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1551 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1553 /* 1 if REGNO is a possible register number for a function value. */
1554 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1555 ((REGNO) == ARG_REGISTER (1) \
1556 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1557 && TARGET_VFP && TARGET_HARD_FLOAT \
1558 && (REGNO) == FIRST_VFP_REGNUM) \
1559 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1560 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1561 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1562 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1563 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1565 /* Amount of memory needed for an untyped call to save all possible return
1567 #define APPLY_RESULT_SIZE arm_apply_result_size()
1569 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1570 values must be in memory. On the ARM, they need only do so if larger
1571 than a word, or if they contain elements offset from zero in the struct. */
1572 #define DEFAULT_PCC_STRUCT_RETURN 0
1574 /* These bits describe the different types of function supported
1575 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1576 normal function and an interworked function, for example. Knowing the
1577 type of a function is important for determining its prologue and
1579 Note value 7 is currently unassigned. Also note that the interrupt
1580 function types all have bit 2 set, so that they can be tested for easily.
1581 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1582 machine_function structure is initialized (to zero) func_type will
1583 default to unknown. This will force the first use of arm_current_func_type
1584 to call arm_compute_func_type. */
1585 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1586 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1587 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1588 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1589 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1590 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1592 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1594 /* In addition functions can have several type modifiers,
1595 outlined by these bit masks: */
1596 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1597 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1598 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1599 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1600 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1602 /* Some macros to test these flags. */
1603 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1604 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1605 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1606 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1607 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1608 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1611 /* Structure used to hold the function stack frame layout. Offsets are
1612 relative to the stack pointer on function entry. Positive offsets are
1613 in the direction of stack growth.
1614 Only soft_frame is used in thumb mode. */
1616 typedef struct GTY(()) arm_stack_offsets
1618 int saved_args; /* ARG_POINTER_REGNUM. */
1619 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1621 int soft_frame; /* FRAME_POINTER_REGNUM. */
1622 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1623 int outgoing_args; /* STACK_POINTER_REGNUM. */
1624 unsigned int saved_regs_mask;
1628 #ifndef GENERATOR_FILE
1629 /* A C structure for machine-specific, per-function data.
1630 This is added to the cfun structure. */
1631 typedef struct GTY(()) machine_function
1633 /* Additional stack adjustment in __builtin_eh_throw. */
1634 rtx eh_epilogue_sp_ofs;
1635 /* Records if LR has to be saved for far jumps. */
1637 /* Records if ARG_POINTER was ever live. */
1638 int arg_pointer_live;
1639 /* Records if the save of LR has been eliminated. */
1640 int lr_save_eliminated;
1641 /* The size of the stack frame. Only valid after reload. */
1642 arm_stack_offsets stack_offsets;
1643 /* Records the type of the current function. */
1644 unsigned long func_type;
1645 /* Record if the function has a variable argument list. */
1646 int uses_anonymous_args;
1647 /* Records if sibcalls are blocked because an argument
1648 register is needed to preserve stack alignment. */
1649 int sibcall_blocked;
1650 /* The PIC register for this function. This might be a pseudo. */
1652 /* Labels for per-function Thumb call-via stubs. One per potential calling
1653 register. We can never call via LR or PC. We can call via SP if a
1654 trampoline happens to be on the top of the stack. */
1656 /* Set to 1 when a return insn is output, this means that the epilogue
1658 int return_used_this_function;
1659 /* When outputting Thumb-1 code, record the last insn that provides
1660 information about condition codes, and the comparison operands. */
1664 /* Also record the CC mode that is supported. */
1665 enum machine_mode thumb1_cc_mode;
1670 /* As in the machine_function, a global set of call-via labels, for code
1671 that is in text_section. */
1672 extern GTY(()) rtx thumb_call_via_label[14];
1674 /* The number of potential ways of assigning to a co-processor. */
1675 #define ARM_NUM_COPROC_SLOTS 1
1677 /* Enumeration of procedure calling standard variants. We don't really
1678 support all of these yet. */
1681 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1682 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1683 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1684 /* This must be the last AAPCS variant. */
1685 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1686 ARM_PCS_ATPCS, /* ATPCS. */
1687 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1691 /* Default procedure calling standard of current compilation unit. */
1692 extern enum arm_pcs arm_pcs_default;
1694 /* A C type for declaring a variable that is used as the first argument of
1695 `FUNCTION_ARG' and other related values. */
1698 /* This is the number of registers of arguments scanned so far. */
1700 /* This is the number of iWMMXt register arguments scanned so far. */
1704 /* Which procedure call variant to use for this call. */
1705 enum arm_pcs pcs_variant;
1707 /* AAPCS related state tracking. */
1708 int aapcs_arg_processed; /* No need to lay out this argument again. */
1709 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1710 this argument, or -1 if using core
1713 int aapcs_next_ncrn;
1714 rtx aapcs_reg; /* Register assigned to this argument. */
1715 int aapcs_partial; /* How many bytes are passed in regs (if
1716 split between core regs and stack.
1718 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1719 int can_split; /* Argument can be split between core regs
1721 /* Private data for tracking VFP register allocation */
1722 unsigned aapcs_vfp_regs_free;
1723 unsigned aapcs_vfp_reg_alloc;
1724 int aapcs_vfp_rcount;
1725 MACHMODE aapcs_vfp_rmode;
1728 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1729 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1731 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1732 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1734 /* For AAPCS, padding should never be below the argument. For other ABIs,
1735 * mimic the default. */
1736 #define PAD_VARARGS_DOWN \
1737 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1739 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1740 for a call to a function whose data type is FNTYPE.
1741 For a library call, FNTYPE is 0.
1742 On the ARM, the offset starts at 0. */
1743 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1744 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1746 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1747 argument with the specified mode and type. If it is not defined,
1748 `PARM_BOUNDARY' is used for all arguments. */
1749 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1750 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1751 ? DOUBLEWORD_ALIGNMENT \
1754 /* 1 if N is a possible register number for function argument passing.
1755 On the ARM, r0-r3 are used to pass args. */
1756 #define FUNCTION_ARG_REGNO_P(REGNO) \
1757 (IN_RANGE ((REGNO), 0, 3) \
1758 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1759 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1760 || (TARGET_IWMMXT_ABI \
1761 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1764 /* If your target environment doesn't prefix user functions with an
1765 underscore, you may wish to re-define this to prevent any conflicts. */
1766 #ifndef ARM_MCOUNT_NAME
1767 #define ARM_MCOUNT_NAME "*mcount"
1770 /* Call the function profiler with a given profile label. The Acorn
1771 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1772 On the ARM the full profile code will look like:
1781 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1782 will output the .text section.
1784 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1785 ``prof'' doesn't seem to mind about this!
1787 Note - this version of the code is designed to work in both ARM and
1789 #ifndef ARM_FUNCTION_PROFILER
1790 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1795 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1796 IP_REGNUM, LR_REGNUM); \
1797 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1798 fputc ('\n', STREAM); \
1799 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1800 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1801 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1805 #ifdef THUMB_FUNCTION_PROFILER
1806 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1808 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1810 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1812 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1813 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1816 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1817 the stack pointer does not matter. The value is tested only in
1818 functions that have frame pointers.
1819 No definition is equivalent to always zero.
1821 On the ARM, the function epilogue recovers the stack pointer from the
1823 #define EXIT_IGNORE_STACK 1
1825 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1827 /* Determine if the epilogue should be output as RTL.
1828 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1829 #define USE_RETURN_INSN(ISCOND) \
1830 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1832 /* Definitions for register eliminations.
1834 This is an array of structures. Each structure initializes one pair
1835 of eliminable registers. The "from" register number is given first,
1836 followed by "to". Eliminations of the same "from" register are listed
1837 in order of preference.
1839 We have two registers that can be eliminated on the ARM. First, the
1840 arg pointer register can often be eliminated in favor of the stack
1841 pointer register. Secondly, the pseudo frame pointer register can always
1842 be eliminated; it is replaced with either the stack or the real frame
1843 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1844 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1846 #define ELIMINABLE_REGS \
1847 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1848 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1849 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1850 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1851 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1852 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1853 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1855 /* Define the offset between two registers, one to be eliminated, and the
1856 other its replacement, at the start of a routine. */
1857 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1859 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1861 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1863 /* Special case handling of the location of arguments passed on the stack. */
1864 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1866 /* Initialize data used by insn expanders. This is called from insn_emit,
1867 once for every function before code is generated. */
1868 #define INIT_EXPANDERS arm_init_expanders ()
1870 /* Length in units of the trampoline for entering a nested function. */
1871 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1873 /* Alignment required for a trampoline in bits. */
1874 #define TRAMPOLINE_ALIGNMENT 32
1876 /* Addressing modes, and classification of registers for them. */
1877 #define HAVE_POST_INCREMENT 1
1878 #define HAVE_PRE_INCREMENT TARGET_32BIT
1879 #define HAVE_POST_DECREMENT TARGET_32BIT
1880 #define HAVE_PRE_DECREMENT TARGET_32BIT
1881 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1882 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1883 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1884 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1886 /* Macros to check register numbers against specific register classes. */
1888 /* These assume that REGNO is a hard or pseudo reg number.
1889 They give nonzero only if REGNO is a hard reg of the suitable class
1890 or a pseudo reg currently allocated to a suitable hard reg.
1891 Since they use reg_renumber, they are safe only once reg_renumber
1892 has been allocated, which happens in local-alloc.c. */
1893 #define TEST_REGNO(R, TEST, VALUE) \
1894 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1896 /* Don't allow the pc to be used. */
1897 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1898 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1899 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1900 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1902 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1903 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1904 || (GET_MODE_SIZE (MODE) >= 4 \
1905 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1907 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1909 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1910 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1912 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1913 For Thumb, we can not use SP + reg, so reject SP. */
1914 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1915 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1917 /* For ARM code, we don't care about the mode, but for Thumb, the index
1918 must be suitable for use in a QImode load. */
1919 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1920 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1921 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1923 /* Maximum number of registers that can appear in a valid memory address.
1924 Shifts in addresses can't be by a register. */
1925 #define MAX_REGS_PER_ADDRESS 2
1927 /* Recognize any constant value that is a valid address. */
1928 /* XXX We can address any constant, eventually... */
1929 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1930 #define CONSTANT_ADDRESS_P(X) \
1931 (GET_CODE (X) == SYMBOL_REF \
1932 && (CONSTANT_POOL_ADDRESS_P (X) \
1933 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1935 /* True if SYMBOL + OFFSET constants must refer to something within
1936 SYMBOL's section. */
1937 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1939 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1940 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1941 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1944 /* Nonzero if the constant value X is a legitimate general operand.
1945 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1947 On the ARM, allow any integer (invalid ones are removed later by insn
1948 patterns), nice doubles and symbol_refs which refer to the function's
1951 When generating pic allow anything. */
1952 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1954 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1955 ( GET_CODE (X) == CONST_INT \
1956 || GET_CODE (X) == CONST_DOUBLE \
1957 || CONSTANT_ADDRESS_P (X) \
1960 #define LEGITIMATE_CONSTANT_P(X) \
1961 (!arm_cannot_force_const_mem (X) \
1962 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1963 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1965 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1966 #define SUBTARGET_NAME_ENCODING_LENGTHS
1969 /* This is a C fragment for the inside of a switch statement.
1970 Each case label should return the number of characters to
1971 be stripped from the start of a function's name, if that
1972 name starts with the indicated character. */
1973 #define ARM_NAME_ENCODING_LENGTHS \
1974 case '*': return 1; \
1975 SUBTARGET_NAME_ENCODING_LENGTHS
1977 /* This is how to output a reference to a user-level label named NAME.
1978 `assemble_name' uses this. */
1979 #undef ASM_OUTPUT_LABELREF
1980 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1981 arm_asm_output_labelref (FILE, NAME)
1983 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1984 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1985 if (TARGET_THUMB2) \
1986 thumb2_asm_output_opcode (STREAM);
1988 /* The EABI specifies that constructors should go in .init_array.
1989 Other targets use .ctors for compatibility. */
1990 #ifndef ARM_EABI_CTORS_SECTION_OP
1991 #define ARM_EABI_CTORS_SECTION_OP \
1992 "\t.section\t.init_array,\"aw\",%init_array"
1994 #ifndef ARM_EABI_DTORS_SECTION_OP
1995 #define ARM_EABI_DTORS_SECTION_OP \
1996 "\t.section\t.fini_array,\"aw\",%fini_array"
1998 #define ARM_CTORS_SECTION_OP \
1999 "\t.section\t.ctors,\"aw\",%progbits"
2000 #define ARM_DTORS_SECTION_OP \
2001 "\t.section\t.dtors,\"aw\",%progbits"
2003 /* Define CTORS_SECTION_ASM_OP. */
2004 #undef CTORS_SECTION_ASM_OP
2005 #undef DTORS_SECTION_ASM_OP
2007 # define CTORS_SECTION_ASM_OP \
2008 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2009 # define DTORS_SECTION_ASM_OP \
2010 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2011 #else /* !defined (IN_LIBGCC2) */
2012 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2013 so we cannot use the definition above. */
2014 # ifdef __ARM_EABI__
2015 /* The .ctors section is not part of the EABI, so we do not define
2016 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2017 from trying to use it. We do define it when doing normal
2018 compilation, as .init_array can be used instead of .ctors. */
2019 /* There is no need to emit begin or end markers when using
2020 init_array; the dynamic linker will compute the size of the
2021 array itself based on special symbols created by the static
2022 linker. However, we do need to arrange to set up
2023 exception-handling here. */
2024 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2025 # define CTOR_LIST_END /* empty */
2026 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2027 # define DTOR_LIST_END /* empty */
2028 # else /* !defined (__ARM_EABI__) */
2029 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2030 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2031 # endif /* !defined (__ARM_EABI__) */
2032 #endif /* !defined (IN_LIBCC2) */
2034 /* True if the operating system can merge entities with vague linkage
2035 (e.g., symbols in COMDAT group) during dynamic linking. */
2036 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2037 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2040 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2042 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2043 and check its validity for a certain class.
2044 We have two alternate definitions for each of them.
2045 The usual definition accepts all pseudo regs; the other rejects
2046 them unless they have been allocated suitable hard regs.
2047 The symbol REG_OK_STRICT causes the latter definition to be used.
2048 Thumb-2 has the same restrictions as arm. */
2049 #ifndef REG_OK_STRICT
2051 #define ARM_REG_OK_FOR_BASE_P(X) \
2052 (REGNO (X) <= LAST_ARM_REGNUM \
2053 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2054 || REGNO (X) == FRAME_POINTER_REGNUM \
2055 || REGNO (X) == ARG_POINTER_REGNUM)
2057 #define ARM_REG_OK_FOR_INDEX_P(X) \
2058 ((REGNO (X) <= LAST_ARM_REGNUM \
2059 && REGNO (X) != STACK_POINTER_REGNUM) \
2060 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2061 || REGNO (X) == FRAME_POINTER_REGNUM \
2062 || REGNO (X) == ARG_POINTER_REGNUM)
2064 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2065 (REGNO (X) <= LAST_LO_REGNUM \
2066 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2067 || (GET_MODE_SIZE (MODE) >= 4 \
2068 && (REGNO (X) == STACK_POINTER_REGNUM \
2069 || (X) == hard_frame_pointer_rtx \
2070 || (X) == arg_pointer_rtx)))
2072 #define REG_STRICT_P 0
2074 #else /* REG_OK_STRICT */
2076 #define ARM_REG_OK_FOR_BASE_P(X) \
2077 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2079 #define ARM_REG_OK_FOR_INDEX_P(X) \
2080 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2082 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2083 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2085 #define REG_STRICT_P 1
2087 #endif /* REG_OK_STRICT */
2089 /* Now define some helpers in terms of the above. */
2091 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2093 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2094 : ARM_REG_OK_FOR_BASE_P (X))
2096 /* For 16-bit Thumb, a valid index register is anything that can be used in
2097 a byte load instruction. */
2098 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2099 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2101 /* Nonzero if X is a hard reg that can be used as an index
2102 or if it is a pseudo reg. On the Thumb, the stack pointer
2104 #define REG_OK_FOR_INDEX_P(X) \
2106 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2107 : ARM_REG_OK_FOR_INDEX_P (X))
2109 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2110 For Thumb, we can not use SP + reg, so reject SP. */
2111 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2112 REG_OK_FOR_INDEX_P (X)
2114 #define ARM_BASE_REGISTER_RTX_P(X) \
2115 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2117 #define ARM_INDEX_REGISTER_RTX_P(X) \
2118 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2120 /* Define this for compatibility reasons. */
2121 #define HANDLE_PRAGMA_PACK_PUSH_POP
2123 /* Specify the machine mode that this machine uses
2124 for the index in the tablejump instruction. */
2125 #define CASE_VECTOR_MODE Pmode
2127 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2129 && (optimize_size || flag_pic)))
2131 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2133 ? (min >= 0 && max < 512 \
2134 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2135 : min >= -256 && max < 256 \
2136 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2137 : min >= 0 && max < 8192 \
2138 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2139 : min >= -4096 && max < 4096 \
2140 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2142 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2143 : (max >= 0x200) ? HImode \
2146 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2147 unsigned is probably best, but may break some code. */
2148 #ifndef DEFAULT_SIGNED_CHAR
2149 #define DEFAULT_SIGNED_CHAR 0
2152 /* Max number of bytes we can move from memory to memory
2153 in one reasonably fast instruction. */
2157 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2159 /* Define if operations between registers always perform the operation
2160 on the full register even if a narrower mode is specified. */
2161 #define WORD_REGISTER_OPERATIONS
2163 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2164 will either zero-extend or sign-extend. The value of this macro should
2165 be the code that says which one of the two operations is implicitly
2166 done, UNKNOWN if none. */
2167 #define LOAD_EXTEND_OP(MODE) \
2168 (TARGET_THUMB ? ZERO_EXTEND : \
2169 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2170 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2172 /* Nonzero if access to memory by bytes is slow and undesirable. */
2173 #define SLOW_BYTE_ACCESS 0
2175 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2177 /* Immediate shift counts are truncated by the output routines (or was it
2178 the assembler?). Shift counts in a register are truncated by ARM. Note
2179 that the native compiler puts too large (> 32) immediate shift counts
2180 into a register and shifts by the register, letting the ARM decide what
2181 to do instead of doing that itself. */
2182 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2183 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2184 On the arm, Y in a register is used modulo 256 for the shift. Only for
2185 rotates is modulo 32 used. */
2186 /* #define SHIFT_COUNT_TRUNCATED 1 */
2188 /* All integers have the same format so truncation is easy. */
2189 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2191 /* Calling from registers is a massive pain. */
2192 #define NO_FUNCTION_CSE 1
2194 /* The machine modes of pointers and functions */
2195 #define Pmode SImode
2196 #define FUNCTION_MODE Pmode
2198 #define ARM_FRAME_RTX(X) \
2199 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2200 || (X) == arg_pointer_rtx)
2202 /* Moves to and from memory are quite expensive */
2203 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2204 (TARGET_32BIT ? 10 : \
2205 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2206 * (CLASS == LO_REGS ? 1 : 2)))
2208 /* Try to generate sequences that don't involve branches, we can then use
2209 conditional instructions */
2210 #define BRANCH_COST(speed_p, predictable_p) \
2211 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2213 /* Position Independent Code. */
2214 /* We decide which register to use based on the compilation options and
2215 the assembler in use; this is more general than the APCS restriction of
2216 using sb (r9) all the time. */
2217 extern unsigned arm_pic_register;
2219 /* The register number of the register used to address a table of static
2220 data addresses in memory. */
2221 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2223 /* We can't directly access anything that contains a symbol,
2224 nor can we indirect via the constant pool. One exception is
2225 UNSPEC_TLS, which is always PIC. */
2226 #define LEGITIMATE_PIC_OPERAND_P(X) \
2227 (!(symbol_mentioned_p (X) \
2228 || label_mentioned_p (X) \
2229 || (GET_CODE (X) == SYMBOL_REF \
2230 && CONSTANT_POOL_ADDRESS_P (X) \
2231 && (symbol_mentioned_p (get_pool_constant (X)) \
2232 || label_mentioned_p (get_pool_constant (X))))) \
2233 || tls_mentioned_p (X))
2235 /* We need to know when we are making a constant pool; this determines
2236 whether data needs to be in the GOT or can be referenced via a GOT
2238 extern int making_const_table;
2240 /* Handle pragmas for compatibility with Intel's compilers. */
2241 /* Also abuse this to register additional C specific EABI attributes. */
2242 #define REGISTER_TARGET_PRAGMAS() do { \
2243 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2244 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2245 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2246 arm_lang_object_attributes_init(); \
2249 /* Condition code information. */
2250 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2251 return the mode to be used for the comparison. */
2253 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2255 #define REVERSIBLE_CC_MODE(MODE) 1
2257 #define REVERSE_CONDITION(CODE,MODE) \
2258 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2259 ? reverse_condition_maybe_unordered (code) \
2260 : reverse_condition (code))
2262 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2263 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2265 /* The arm5 clz instruction returns 32. */
2266 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2267 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2269 #define CC_STATUS_INIT \
2270 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2273 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2274 TARGET_THUMB2 ? "\t.thumb\n" : "")
2276 /* Output a push or a pop instruction (only used when profiling).
2277 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2278 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2279 that r7 isn't used by the function profiler, so we can use it as a
2280 scratch reg. WARNING: This isn't safe in the general case! It may be
2281 sensitive to future changes in final.c:profile_function. */
2282 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2286 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2287 STACK_POINTER_REGNUM, REGNO); \
2288 else if (TARGET_THUMB1 \
2289 && (REGNO) == STATIC_CHAIN_REGNUM) \
2291 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2292 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2293 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2296 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2300 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2301 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2305 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2306 STACK_POINTER_REGNUM, REGNO); \
2307 else if (TARGET_THUMB1 \
2308 && (REGNO) == STATIC_CHAIN_REGNUM) \
2310 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2311 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2312 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2315 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2318 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2319 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2321 /* This is how to output a label which precedes a jumptable. Since
2322 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2323 #undef ASM_OUTPUT_CASE_LABEL
2324 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2327 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2328 ASM_OUTPUT_ALIGN (FILE, 2); \
2329 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2333 /* Make sure subsequent insns are aligned after a TBB. */
2334 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2337 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2338 ASM_OUTPUT_ALIGN (FILE, 1); \
2342 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2347 if (is_called_in_ARM_mode (DECL) \
2348 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2349 && cfun->is_thunk)) \
2350 fprintf (STREAM, "\t.code 32\n") ; \
2351 else if (TARGET_THUMB1) \
2352 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2354 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2356 if (TARGET_POKE_FUNCTION_NAME) \
2357 arm_poke_function_name (STREAM, (const char *) NAME); \
2361 /* For aliases of functions we use .thumb_set instead. */
2362 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2365 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2366 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2368 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2370 fprintf (FILE, "\t.thumb_set "); \
2371 assemble_name (FILE, LABEL1); \
2372 fprintf (FILE, ","); \
2373 assemble_name (FILE, LABEL2); \
2374 fprintf (FILE, "\n"); \
2377 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2381 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2382 /* To support -falign-* switches we need to use .p2align so
2383 that alignment directives in code sections will be padded
2384 with no-op instructions, rather than zeroes. */
2385 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2388 if ((MAX_SKIP) == 0) \
2389 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2391 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2392 (int) (LOG), (int) (MAX_SKIP)); \
2396 /* Add two bytes to the length of conditionally executed Thumb-2
2397 instructions for the IT instruction. */
2398 #define ADJUST_INSN_LENGTH(insn, length) \
2399 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2402 /* Only perform branch elimination (by making instructions conditional) if
2403 we're optimizing. For Thumb-2 check if any IT instructions need
2405 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2406 if (TARGET_ARM && optimize) \
2407 arm_final_prescan_insn (INSN); \
2408 else if (TARGET_THUMB2) \
2409 thumb2_final_prescan_insn (INSN); \
2410 else if (TARGET_THUMB1) \
2411 thumb1_final_prescan_insn (INSN)
2413 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2414 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2415 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2416 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2417 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2418 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2421 /* A C expression whose value is RTL representing the value of the return
2422 address for the frame COUNT steps up from the current frame. */
2424 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2425 arm_return_addr (COUNT, FRAME)
2427 /* Mask of the bits in the PC that contain the real return address
2428 when running in 26-bit mode. */
2429 #define RETURN_ADDR_MASK26 (0x03fffffc)
2431 /* Pick up the return address upon entry to a procedure. Used for
2432 dwarf2 unwind information. This also enables the table driven
2434 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2435 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2437 /* Used to mask out junk bits from the return address, such as
2438 processor state, interrupt status, condition codes and the like. */
2439 #define MASK_RETURN_ADDR \
2440 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2441 in 26 bit mode, the condition codes must be masked out of the \
2442 return address. This does not apply to ARM6 and later processors \
2443 when running in 32 bit mode. */ \
2444 ((arm_arch4 || TARGET_THUMB) \
2445 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2446 : arm_gen_return_addr_mask ())
2449 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2450 symbolic names defined here (which would require too much duplication).
2459 ARM_BUILTIN_WAVG2BR,
2460 ARM_BUILTIN_WAVG2HR,
2487 ARM_BUILTIN_TMOVMSKB,
2488 ARM_BUILTIN_TMOVMSKH,
2489 ARM_BUILTIN_TMOVMSKW,
2498 ARM_BUILTIN_WPACKHSS,
2499 ARM_BUILTIN_WPACKWSS,
2500 ARM_BUILTIN_WPACKDSS,
2501 ARM_BUILTIN_WPACKHUS,
2502 ARM_BUILTIN_WPACKWUS,
2503 ARM_BUILTIN_WPACKDUS,
2508 ARM_BUILTIN_WADDSSB,
2509 ARM_BUILTIN_WADDSSH,
2510 ARM_BUILTIN_WADDSSW,
2511 ARM_BUILTIN_WADDUSB,
2512 ARM_BUILTIN_WADDUSH,
2513 ARM_BUILTIN_WADDUSW,
2517 ARM_BUILTIN_WSUBSSB,
2518 ARM_BUILTIN_WSUBSSH,
2519 ARM_BUILTIN_WSUBSSW,
2520 ARM_BUILTIN_WSUBUSB,
2521 ARM_BUILTIN_WSUBUSH,
2522 ARM_BUILTIN_WSUBUSW,
2529 ARM_BUILTIN_WCMPEQB,
2530 ARM_BUILTIN_WCMPEQH,
2531 ARM_BUILTIN_WCMPEQW,
2532 ARM_BUILTIN_WCMPGTUB,
2533 ARM_BUILTIN_WCMPGTUH,
2534 ARM_BUILTIN_WCMPGTUW,
2535 ARM_BUILTIN_WCMPGTSB,
2536 ARM_BUILTIN_WCMPGTSH,
2537 ARM_BUILTIN_WCMPGTSW,
2539 ARM_BUILTIN_TEXTRMSB,
2540 ARM_BUILTIN_TEXTRMSH,
2541 ARM_BUILTIN_TEXTRMSW,
2542 ARM_BUILTIN_TEXTRMUB,
2543 ARM_BUILTIN_TEXTRMUH,
2544 ARM_BUILTIN_TEXTRMUW,
2594 ARM_BUILTIN_WUNPCKIHB,
2595 ARM_BUILTIN_WUNPCKIHH,
2596 ARM_BUILTIN_WUNPCKIHW,
2597 ARM_BUILTIN_WUNPCKILB,
2598 ARM_BUILTIN_WUNPCKILH,
2599 ARM_BUILTIN_WUNPCKILW,
2601 ARM_BUILTIN_WUNPCKEHSB,
2602 ARM_BUILTIN_WUNPCKEHSH,
2603 ARM_BUILTIN_WUNPCKEHSW,
2604 ARM_BUILTIN_WUNPCKEHUB,
2605 ARM_BUILTIN_WUNPCKEHUH,
2606 ARM_BUILTIN_WUNPCKEHUW,
2607 ARM_BUILTIN_WUNPCKELSB,
2608 ARM_BUILTIN_WUNPCKELSH,
2609 ARM_BUILTIN_WUNPCKELSW,
2610 ARM_BUILTIN_WUNPCKELUB,
2611 ARM_BUILTIN_WUNPCKELUH,
2612 ARM_BUILTIN_WUNPCKELUW,
2614 ARM_BUILTIN_THREAD_POINTER,
2616 ARM_BUILTIN_NEON_BASE,
2618 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2621 /* Do not emit .note.GNU-stack by default. */
2622 #ifndef NEED_INDICATE_EXEC_STACK
2623 #define NEED_INDICATE_EXEC_STACK 0
2626 /* The maximum number of parallel loads or stores we support in an ldm/stm
2628 #define MAX_LDM_STM_OPS 4
2630 #endif /* ! GCC_ARM_H */
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