1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
39 #include "config/vxworks-dummy.h"
41 /* The architecture define. */
42 extern char arm_arch_name[];
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 if (TARGET_DSP_MULTIPLY) \
49 builtin_define ("__ARM_FEATURE_DSP"); \
50 /* Define __arm__ even when in thumb mode, for \
51 consistency with armcc. */ \
52 builtin_define ("__arm__"); \
53 builtin_define ("__APCS_32__"); \
55 builtin_define ("__thumb__"); \
57 builtin_define ("__thumb2__"); \
61 builtin_define ("__ARMEB__"); \
63 builtin_define ("__THUMBEB__"); \
64 if (TARGET_LITTLE_WORDS) \
65 builtin_define ("__ARMWEL__"); \
69 builtin_define ("__ARMEL__"); \
71 builtin_define ("__THUMBEL__"); \
74 if (TARGET_SOFT_FLOAT) \
75 builtin_define ("__SOFTFP__"); \
78 builtin_define ("__VFP_FP__"); \
81 builtin_define ("__ARM_NEON__"); \
83 /* Add a define for interworking. \
84 Needed when building libgcc.a. */ \
85 if (arm_cpp_interwork) \
86 builtin_define ("__THUMB_INTERWORK__"); \
88 builtin_assert ("cpu=arm"); \
89 builtin_assert ("machine=arm"); \
91 builtin_define (arm_arch_name); \
92 if (arm_arch_cirrus) \
93 builtin_define ("__MAVERICK__"); \
94 if (arm_arch_xscale) \
95 builtin_define ("__XSCALE__"); \
96 if (arm_arch_iwmmxt) \
97 builtin_define ("__IWMMXT__"); \
98 if (TARGET_AAPCS_BASED) \
100 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
101 builtin_define ("__ARM_PCS_VFP"); \
102 else if (arm_pcs_default == ARM_PCS_AAPCS) \
103 builtin_define ("__ARM_PCS"); \
104 builtin_define ("__ARM_EABI__"); \
107 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
110 #include "config/arm/arm-opts.h"
114 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
116 #include "arm-cores.def"
121 /* The processor for which instructions should be scheduled. */
122 extern enum processor_type arm_tune;
124 enum arm_sync_generator_tag
126 arm_sync_generator_omn,
127 arm_sync_generator_omrn
130 /* Wrapper to pass around a polymorphic pointer to a sync instruction
132 struct arm_sync_generator
134 enum arm_sync_generator_tag op;
137 rtx (* omn) (rtx, rtx, rtx);
138 rtx (* omrn) (rtx, rtx, rtx, rtx);
142 typedef enum arm_cond_code
144 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
145 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
149 extern arm_cc arm_current_cc;
151 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
153 extern int arm_target_label;
154 extern int arm_ccfsm_state;
155 extern GTY(()) rtx arm_target_insn;
156 /* The label of the current constant pool. */
157 extern rtx pool_vector_label;
158 /* Set to 1 when a return insn is output, this means that the epilogue
160 extern int return_used_this_function;
161 /* Callback to output language specific object attributes. */
162 extern void (*arm_lang_output_object_attributes_hook)(void);
164 /* Just in case configure has failed to define anything. */
165 #ifndef TARGET_CPU_DEFAULT
166 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
171 #define CPP_SPEC "%(subtarget_cpp_spec) \
172 %{mfloat-abi=soft:%{mfloat-abi=hard: \
173 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
174 %{mbig-endian:%{mlittle-endian: \
175 %e-mbig-endian and -mlittle-endian may not be used together}}"
181 /* This macro defines names of additional specifications to put in the specs
182 that can be used in various specifications like CC1_SPEC. Its definition
183 is an initializer with a subgrouping for each command option.
185 Each subgrouping contains a string constant, that defines the
186 specification name, and a string constant that used by the GCC driver
189 Do not define this macro if it does not need to do anything. */
190 #define EXTRA_SPECS \
191 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
192 { "asm_cpu_spec", ASM_CPU_SPEC }, \
193 SUBTARGET_EXTRA_SPECS
195 #ifndef SUBTARGET_EXTRA_SPECS
196 #define SUBTARGET_EXTRA_SPECS
199 #ifndef SUBTARGET_CPP_SPEC
200 #define SUBTARGET_CPP_SPEC ""
203 /* Run-time Target Specification. */
204 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
205 /* Use hardware floating point instructions. */
206 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
207 /* Use hardware floating point calling convention. */
208 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
209 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
210 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
211 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
212 #define TARGET_IWMMXT (arm_arch_iwmmxt)
213 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
214 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
215 #define TARGET_ARM (! TARGET_THUMB)
216 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
217 #define TARGET_BACKTRACE (leaf_function_p () \
218 ? TARGET_TPCS_LEAF_FRAME \
220 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
221 #define TARGET_AAPCS_BASED \
222 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
224 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
225 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
226 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
228 /* Only 16-bit thumb code. */
229 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
230 /* Arm or Thumb-2 32-bit code. */
231 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
232 /* 32-bit Thumb-2 code. */
233 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
235 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
236 /* FPA emulator without LFM. */
237 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
239 /* The following two macros concern the ability to execute coprocessor
240 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
241 only ever tested when we know we are generating for VFP hardware; we need
242 to be more careful with TARGET_NEON as noted below. */
244 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
245 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
247 /* FPU supports VFPv3 instructions. */
248 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
250 /* FPU only supports VFP single-precision instructions. */
251 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
253 /* FPU supports VFP double-precision instructions. */
254 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
256 /* FPU supports half-precision floating-point with NEON element load/store. */
257 #define TARGET_NEON_FP16 \
258 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
260 /* FPU supports VFP half-precision floating-point. */
261 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
263 /* FPU supports Neon instructions. The setting of this macro gets
264 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
265 and TARGET_HARD_FLOAT to ensure that NEON instructions are
267 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
268 && TARGET_VFP && arm_fpu_desc->neon)
270 /* "DSP" multiply instructions, eg. SMULxy. */
271 #define TARGET_DSP_MULTIPLY \
272 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
273 /* Integer SIMD instructions, and extend-accumulate instructions. */
274 #define TARGET_INT_SIMD \
275 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
277 /* Should MOVW/MOVT be used in preference to a constant pool. */
278 #define TARGET_USE_MOVT \
279 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
281 /* We could use unified syntax for arm mode, but for now we just use it
283 #define TARGET_UNIFIED_ASM TARGET_THUMB2
285 /* Nonzero if this chip provides the DMB instruction. */
286 #define TARGET_HAVE_DMB (arm_arch7)
288 /* Nonzero if this chip implements a memory barrier via CP15. */
289 #define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
291 /* Nonzero if this chip implements a memory barrier instruction. */
292 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
294 /* Nonzero if this chip supports ldrex and strex */
295 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
297 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
298 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
300 /* Nonzero if integer division instructions supported. */
301 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
302 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
304 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
305 then TARGET_AAPCS_BASED must be true -- but the converse does not
306 hold. TARGET_BPABI implies the use of the BPABI runtime library,
307 etc., in addition to just the AAPCS calling conventions. */
309 #define TARGET_BPABI false
312 /* Support for a compile-time default CPU, et cetera. The rules are:
313 --with-arch is ignored if -march or -mcpu are specified.
314 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
316 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
318 --with-float is ignored if -mfloat-abi is specified.
319 --with-fpu is ignored if -mfpu is specified.
320 --with-abi is ignored if -mabi is specified.
321 --with-tls is ignored if -mtls-dialect is specified. */
322 #define OPTION_DEFAULT_SPECS \
323 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
324 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
325 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
326 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
327 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
328 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
329 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
330 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
332 /* Which floating point model to use. */
335 ARM_FP_MODEL_UNKNOWN,
336 /* FPA model (Hardware or software). */
338 /* Cirrus Maverick floating point model. */
339 ARM_FP_MODEL_MAVERICK,
340 /* VFP floating point model. */
352 extern const struct arm_fpu_desc
355 enum arm_fp_model model;
357 enum vfp_reg_type regs;
362 /* Which floating point hardware to schedule for. */
363 extern int arm_fpu_attr;
365 #ifndef TARGET_DEFAULT_FLOAT_ABI
366 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
369 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
370 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
372 #ifndef ARM_DEFAULT_ABI
373 #define ARM_DEFAULT_ABI ARM_ABI_APCS
376 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
377 extern int arm_arch3m;
379 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
380 extern int arm_arch4;
382 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
383 extern int arm_arch4t;
385 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
386 extern int arm_arch5;
388 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
389 extern int arm_arch5e;
391 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
392 extern int arm_arch6;
394 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
395 extern int arm_arch6k;
397 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
398 extern int arm_arch7;
400 /* Nonzero if instructions not present in the 'M' profile can be used. */
401 extern int arm_arch_notm;
403 /* Nonzero if instructions present in ARMv7E-M can be used. */
404 extern int arm_arch7em;
406 /* Nonzero if this chip can benefit from load scheduling. */
407 extern int arm_ld_sched;
409 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
410 extern int thumb_code;
412 /* Nonzero if generating Thumb-1 code. */
413 extern int thumb1_code;
415 /* Nonzero if this chip is a StrongARM. */
416 extern int arm_tune_strongarm;
418 /* Nonzero if this chip is a Cirrus variant. */
419 extern int arm_arch_cirrus;
421 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
422 extern int arm_arch_iwmmxt;
424 /* Nonzero if this chip is an XScale. */
425 extern int arm_arch_xscale;
427 /* Nonzero if tuning for XScale. */
428 extern int arm_tune_xscale;
430 /* Nonzero if tuning for stores via the write buffer. */
431 extern int arm_tune_wbuf;
433 /* Nonzero if tuning for Cortex-A9. */
434 extern int arm_tune_cortex_a9;
436 /* Nonzero if we should define __THUMB_INTERWORK__ in the
438 XXX This is a bit of a hack, it's intended to help work around
439 problems in GLD which doesn't understand that armv5t code is
440 interworking clean. */
441 extern int arm_cpp_interwork;
443 /* Nonzero if chip supports Thumb 2. */
444 extern int arm_arch_thumb2;
446 /* Nonzero if chip supports integer division instruction in ARM mode. */
447 extern int arm_arch_arm_hwdiv;
449 /* Nonzero if chip supports integer division instruction in Thumb mode. */
450 extern int arm_arch_thumb_hwdiv;
452 #ifndef TARGET_DEFAULT
453 #define TARGET_DEFAULT (MASK_APCS_FRAME)
456 /* Nonzero if PIC code requires explicit qualifiers to generate
457 PLT and GOT relocs rather than the assembler doing so implicitly.
458 Subtargets can override these if required. */
459 #ifndef NEED_GOT_RELOC
460 #define NEED_GOT_RELOC 0
462 #ifndef NEED_PLT_RELOC
463 #define NEED_PLT_RELOC 0
466 /* Nonzero if we need to refer to the GOT with a PC-relative
467 offset. In other words, generate
469 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
473 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
475 The default is true, which matches NetBSD. Subtargets can
476 override this if required. */
481 /* Target machine storage Layout. */
484 /* Define this macro if it is advisable to hold scalars in registers
485 in a wider mode than that declared by the program. In such cases,
486 the value is constrained to be within the bounds of the declared
487 type, but kept valid in the wider mode. The signedness of the
488 extension may differ from that of the type. */
490 /* It is far faster to zero extend chars than to sign extend them */
492 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
493 if (GET_MODE_CLASS (MODE) == MODE_INT \
494 && GET_MODE_SIZE (MODE) < 4) \
496 if (MODE == QImode) \
498 else if (MODE == HImode) \
503 /* Define this if most significant bit is lowest numbered
504 in instructions that operate on numbered bit-fields. */
505 #define BITS_BIG_ENDIAN 0
507 /* Define this if most significant byte of a word is the lowest numbered.
508 Most ARM processors are run in little endian mode, so that is the default.
509 If you want to have it run-time selectable, change the definition in a
510 cover file to be TARGET_BIG_ENDIAN. */
511 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
513 /* Define this if most significant word of a multiword number is the lowest
515 This is always false, even when in big-endian mode. */
516 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
518 /* Define this if most significant word of doubles is the lowest numbered.
519 The rules are different based on whether or not we use FPA-format,
520 VFP-format or some other floating point co-processor's format doubles. */
521 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
523 #define UNITS_PER_WORD 4
525 /* True if natural alignment is used for doubleword types. */
526 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
528 #define DOUBLEWORD_ALIGNMENT 64
530 #define PARM_BOUNDARY 32
532 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
534 #define PREFERRED_STACK_BOUNDARY \
535 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
537 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
539 /* The lowest bit is used to indicate Thumb-mode functions, so the
540 vbit must go into the delta field of pointers to member
542 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
544 #define EMPTY_FIELD_BOUNDARY 32
546 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
548 /* XXX Blah -- this macro is used directly by libobjc. Since it
549 supports no vector modes, cut out the complexity and fall back
550 on BIGGEST_FIELD_ALIGNMENT. */
551 #ifdef IN_TARGET_LIBS
552 #define BIGGEST_FIELD_ALIGNMENT 64
555 /* Make strings word-aligned so strcpy from constants will be faster. */
556 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
558 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
559 ((TREE_CODE (EXP) == STRING_CST \
561 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
562 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
564 /* Align definitions of arrays, unions and structures so that
565 initializations and copies can be made more efficient. This is not
566 ABI-changing, so it only affects places where we can see the
567 definition. Increasing the alignment tends to introduce padding,
568 so don't do this when optimizing for size/conserving stack space. */
569 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
570 (((COND) && ((ALIGN) < BITS_PER_WORD) \
571 && (TREE_CODE (EXP) == ARRAY_TYPE \
572 || TREE_CODE (EXP) == UNION_TYPE \
573 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
575 /* Align global data. */
576 #define DATA_ALIGNMENT(EXP, ALIGN) \
577 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
579 /* Similarly, make sure that objects on the stack are sensibly aligned. */
580 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
581 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
583 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
584 value set in previous versions of this toolchain was 8, which produces more
585 compact structures. The command line option -mstructure_size_boundary=<n>
586 can be used to change this value. For compatibility with the ARM SDK
587 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
588 0020D) page 2-20 says "Structures are aligned on word boundaries".
589 The AAPCS specifies a value of 8. */
590 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
592 /* This is the value used to initialize arm_structure_size_boundary. If a
593 particular arm target wants to change the default value it should change
594 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
595 for an example of this. */
596 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
597 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
600 /* Nonzero if move instructions will actually fail to work
601 when given unaligned data. */
602 #define STRICT_ALIGNMENT 1
604 /* wchar_t is unsigned under the AAPCS. */
606 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
608 #define WCHAR_TYPE_SIZE BITS_PER_WORD
611 /* Sized for fixed-point types. */
613 #define SHORT_FRACT_TYPE_SIZE 8
614 #define FRACT_TYPE_SIZE 16
615 #define LONG_FRACT_TYPE_SIZE 32
616 #define LONG_LONG_FRACT_TYPE_SIZE 64
618 #define SHORT_ACCUM_TYPE_SIZE 16
619 #define ACCUM_TYPE_SIZE 32
620 #define LONG_ACCUM_TYPE_SIZE 64
621 #define LONG_LONG_ACCUM_TYPE_SIZE 64
623 #define MAX_FIXED_MODE_SIZE 64
626 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
630 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
633 /* AAPCS requires that structure alignment is affected by bitfields. */
634 #ifndef PCC_BITFIELD_TYPE_MATTERS
635 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
639 /* Standard register usage. */
641 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
642 (S - saved over call).
644 r0 * argument word/integer result
647 r4-r8 S register variable
648 r9 S (rfp) register variable (real frame pointer)
650 r10 F S (sl) stack limit (used by -mapcs-stack-check)
651 r11 F S (fp) argument pointer
652 r12 (ip) temp workspace
653 r13 F S (sp) lower end of current stack frame
654 r14 (lr) link address/workspace
655 r15 F (pc) program counter
657 f0 floating point result
658 f1-f3 floating point scratch
660 f4-f7 S floating point variable
662 cc This is NOT a real register, but is used internally
663 to represent things that use or set the condition
665 sfp This isn't either. It is used during rtl generation
666 since the offset between the frame pointer and the
667 auto's isn't known until after register allocation.
668 afp Nor this, we only need this because of non-local
669 goto. Without it fp appears to be used and the
670 elimination code won't get rid of sfp. It tracks
671 fp exactly at all times.
673 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
676 mvf0 Cirrus floating point result
677 mvf1-mvf3 Cirrus floating point scratch
678 mvf4-mvf15 S Cirrus floating point variable. */
680 /* s0-s15 VFP scratch (aka d0-d7).
681 s16-s31 S VFP variable (aka d8-d15).
682 vfpcc Not a real register. Represents the VFP condition
685 /* The stack backtrace structure is as follows:
686 fp points to here: | save code pointer | [fp]
687 | return link value | [fp, #-4]
688 | return sp value | [fp, #-8]
689 | return fp value | [fp, #-12]
690 [| saved r10 value |]
701 [| saved f7 value |] three words
702 [| saved f6 value |] three words
703 [| saved f5 value |] three words
704 [| saved f4 value |] three words
705 r0-r3 are not normally saved in a C function. */
707 /* 1 for registers that have pervasive standard uses
708 and are not available for the register allocator. */
709 #define FIXED_REGISTERS \
731 /* 1 for registers not available across function calls.
732 These must include the FIXED_REGISTERS and also any
733 registers that can be used without being saved.
734 The latter must include the registers where values are returned
735 and the register where structure-value addresses are passed.
736 Aside from that, you can include as many other registers as you like.
737 The CC is not preserved over function calls on the ARM 6, so it is
738 easier to assume this for all. SFP is preserved, since FP is. */
739 #define CALL_USED_REGISTERS \
761 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
762 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
765 /* These are a couple of extensions to the formats accepted
767 %@ prints out ASM_COMMENT_START
768 %r prints out REGISTER_PREFIX reg_names[arg] */
769 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
771 fputs (ASM_COMMENT_START, FILE); \
775 fputs (REGISTER_PREFIX, FILE); \
776 fputs (reg_names [va_arg (ARGS, int)], FILE); \
779 /* Round X up to the nearest word. */
780 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
782 /* Convert fron bytes to ints. */
783 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
785 /* The number of (integer) registers required to hold a quantity of type MODE.
786 Also used for VFP registers. */
787 #define ARM_NUM_REGS(MODE) \
788 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
790 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
791 #define ARM_NUM_REGS2(MODE, TYPE) \
792 ARM_NUM_INTS ((MODE) == BLKmode ? \
793 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
795 /* The number of (integer) argument register available. */
796 #define NUM_ARG_REGS 4
798 /* And similarly for the VFP. */
799 #define NUM_VFP_ARG_REGS 16
801 /* Return the register number of the N'th (integer) argument. */
802 #define ARG_REGISTER(N) (N - 1)
804 /* Specify the registers used for certain standard purposes.
805 The values of these macros are register numbers. */
807 /* The number of the last argument register. */
808 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
810 /* The numbers of the Thumb register ranges. */
811 #define FIRST_LO_REGNUM 0
812 #define LAST_LO_REGNUM 7
813 #define FIRST_HI_REGNUM 8
814 #define LAST_HI_REGNUM 11
816 /* Overridden by config/arm/bpabi.h. */
817 #ifndef ARM_UNWIND_INFO
818 #define ARM_UNWIND_INFO 0
821 /* Use r0 and r1 to pass exception handling information. */
822 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
824 /* The register that holds the return address in exception handlers. */
825 #define ARM_EH_STACKADJ_REGNUM 2
826 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
828 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
829 as an invisible last argument (possible since varargs don't exist in
830 Pascal), so the following is not true. */
831 #define STATIC_CHAIN_REGNUM 12
833 /* Define this to be where the real frame pointer is if it is not possible to
834 work out the offset between the frame pointer and the automatic variables
835 until after register allocation has taken place. FRAME_POINTER_REGNUM
836 should point to a special register that we will make sure is eliminated.
838 For the Thumb we have another problem. The TPCS defines the frame pointer
839 as r11, and GCC believes that it is always possible to use the frame pointer
840 as base register for addressing purposes. (See comments in
841 find_reloads_address()). But - the Thumb does not allow high registers,
842 including r11, to be used as base address registers. Hence our problem.
844 The solution used here, and in the old thumb port is to use r7 instead of
845 r11 as the hard frame pointer and to have special code to generate
846 backtrace structures on the stack (if required to do so via a command line
847 option) using r11. This is the only 'user visible' use of r11 as a frame
849 #define ARM_HARD_FRAME_POINTER_REGNUM 11
850 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
852 #define HARD_FRAME_POINTER_REGNUM \
854 ? ARM_HARD_FRAME_POINTER_REGNUM \
855 : THUMB_HARD_FRAME_POINTER_REGNUM)
857 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
858 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
860 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
862 /* Register to use for pushing function arguments. */
863 #define STACK_POINTER_REGNUM SP_REGNUM
865 /* ARM floating pointer registers. */
866 #define FIRST_FPA_REGNUM 16
867 #define LAST_FPA_REGNUM 23
868 #define IS_FPA_REGNUM(REGNUM) \
869 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
871 #define FIRST_IWMMXT_GR_REGNUM 43
872 #define LAST_IWMMXT_GR_REGNUM 46
873 #define FIRST_IWMMXT_REGNUM 47
874 #define LAST_IWMMXT_REGNUM 62
875 #define IS_IWMMXT_REGNUM(REGNUM) \
876 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
877 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
878 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
880 /* Base register for access to local variables of the function. */
881 #define FRAME_POINTER_REGNUM 25
883 /* Base register for access to arguments of the function. */
884 #define ARG_POINTER_REGNUM 26
886 #define FIRST_CIRRUS_FP_REGNUM 27
887 #define LAST_CIRRUS_FP_REGNUM 42
888 #define IS_CIRRUS_REGNUM(REGNUM) \
889 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
891 #define FIRST_VFP_REGNUM 63
892 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
893 #define LAST_VFP_REGNUM \
894 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
896 #define IS_VFP_REGNUM(REGNUM) \
897 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
899 /* VFP registers are split into two types: those defined by VFP versions < 3
900 have D registers overlaid on consecutive pairs of S registers. VFP version 3
901 defines 16 new D registers (d16-d31) which, for simplicity and correctness
902 in various parts of the backend, we implement as "fake" single-precision
903 registers (which would be S32-S63, but cannot be used in that way). The
904 following macros define these ranges of registers. */
905 #define LAST_LO_VFP_REGNUM 94
906 #define FIRST_HI_VFP_REGNUM 95
907 #define LAST_HI_VFP_REGNUM 126
909 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
910 ((REGNUM) <= LAST_LO_VFP_REGNUM)
912 /* DFmode values are only valid in even register pairs. */
913 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
914 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
916 /* Neon Quad values must start at a multiple of four registers. */
917 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
918 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
920 /* Neon structures of vectors must be in even register pairs and there
921 must be enough registers available. Because of various patterns
922 requiring quad registers, we require them to start at a multiple of
924 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
925 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
926 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
928 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
929 /* + 16 Cirrus registers take us up to 43. */
930 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
931 /* VFP (VFP3) adds 32 (64) + 1 more. */
932 #define FIRST_PSEUDO_REGISTER 128
934 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
936 /* Value should be nonzero if functions must have frame pointers.
937 Zero means the frame pointer need not be set up (and parms may be accessed
938 via the stack pointer) in functions that seem suitable.
939 If we have to have a frame pointer we might as well make use of it.
940 APCS says that the frame pointer does not need to be pushed in leaf
941 functions, or simple tail call functions. */
943 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
944 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
947 /* Return number of consecutive hard regs needed starting at reg REGNO
948 to hold something of mode MODE.
949 This is ordinarily the length in words of a value of mode MODE
950 but can be less for certain modes in special long registers.
952 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
954 #define HARD_REGNO_NREGS(REGNO, MODE) \
956 && REGNO >= FIRST_FPA_REGNUM \
957 && REGNO != FRAME_POINTER_REGNUM \
958 && REGNO != ARG_POINTER_REGNUM) \
959 && !IS_VFP_REGNUM (REGNO) \
960 ? 1 : ARM_NUM_REGS (MODE))
962 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
963 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
964 arm_hard_regno_mode_ok ((REGNO), (MODE))
966 /* Value is 1 if it is a good idea to tie two pseudo registers
967 when one has mode MODE1 and one has mode MODE2.
968 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
969 for any hard reg, then this must be 0 for correct output. */
970 #define MODES_TIEABLE_P(MODE1, MODE2) \
971 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
973 #define VALID_IWMMXT_REG_MODE(MODE) \
974 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
976 /* Modes valid for Neon D registers. */
977 #define VALID_NEON_DREG_MODE(MODE) \
978 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
979 || (MODE) == V2SFmode || (MODE) == DImode)
981 /* Modes valid for Neon Q registers. */
982 #define VALID_NEON_QREG_MODE(MODE) \
983 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
984 || (MODE) == V4SFmode || (MODE) == V2DImode)
986 /* Structure modes valid for Neon registers. */
987 #define VALID_NEON_STRUCT_MODE(MODE) \
988 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
989 || (MODE) == CImode || (MODE) == XImode)
991 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
992 extern int arm_regs_in_sequence[];
994 /* The order in which register should be allocated. It is good to use ip
995 since no saving is required (though calls clobber it) and it never contains
996 function parameters. It is quite good to use lr since other calls may
997 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
998 least likely to contain a function parameter; in addition results are
1000 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1001 then D8-D15. The reason for doing this is to attempt to reduce register
1002 pressure when both single- and double-precision registers are used in a
1005 #define REG_ALLOC_ORDER \
1007 3, 2, 1, 0, 12, 14, 4, 5, \
1008 6, 7, 8, 10, 9, 11, 13, 15, \
1009 16, 17, 18, 19, 20, 21, 22, 23, \
1010 27, 28, 29, 30, 31, 32, 33, 34, \
1011 35, 36, 37, 38, 39, 40, 41, 42, \
1012 43, 44, 45, 46, 47, 48, 49, 50, \
1013 51, 52, 53, 54, 55, 56, 57, 58, \
1016 95, 96, 97, 98, 99, 100, 101, 102, \
1017 103, 104, 105, 106, 107, 108, 109, 110, \
1018 111, 112, 113, 114, 115, 116, 117, 118, \
1019 119, 120, 121, 122, 123, 124, 125, 126, \
1020 78, 77, 76, 75, 74, 73, 72, 71, \
1021 70, 69, 68, 67, 66, 65, 64, 63, \
1022 79, 80, 81, 82, 83, 84, 85, 86, \
1023 87, 88, 89, 90, 91, 92, 93, 94, \
1027 /* Use different register alloc ordering for Thumb. */
1028 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1030 /* Tell IRA to use the order we define rather than messing it up with its
1031 own cost calculations. */
1032 #define HONOR_REG_ALLOC_ORDER
1034 /* Interrupt functions can only use registers that have already been
1035 saved by the prologue, even if they would normally be
1037 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1038 (! IS_INTERRUPT (cfun->machine->func_type) || \
1039 df_regs_ever_live_p (DST))
1041 /* Register and constant classes. */
1043 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1044 Now that the Thumb is involved it has become more complicated. */
1068 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1070 /* Give names of register classes as strings for dump file. */
1071 #define REG_CLASS_NAMES \
1093 /* Define which registers fit in which classes.
1094 This is an initializer for a vector of HARD_REG_SET
1095 of length N_REG_CLASSES. */
1096 #define REG_CLASS_CONTENTS \
1098 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1099 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1100 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1101 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1102 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1103 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1104 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1105 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1106 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1107 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1108 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1109 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1110 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1111 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1112 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1113 { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1114 { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1115 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1118 /* Any of the VFP register classes. */
1119 #define IS_VFP_CLASS(X) \
1120 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1121 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1123 /* The same information, inverted:
1124 Return the class number of the smallest class containing
1125 reg number REGNO. This could be a conditional expression
1126 or could index an array. */
1127 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1129 /* FPA registers can't do subreg as all values are reformatted to internal
1130 precision. In VFPv1, VFP registers could only be accessed in the mode
1131 they were set, so subregs would be invalid there too. However, we don't
1132 support VFPv1 at the moment, and the restriction was lifted in VFPv2. */
1133 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1134 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1135 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1138 /* The class value for index registers, and the one for base regs. */
1139 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1140 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1142 /* For the Thumb the high registers cannot be used as base registers
1143 when addressing quantities in QI or HI mode; if we don't know the
1144 mode, then we must be conservative. */
1145 #define MODE_BASE_REG_CLASS(MODE) \
1146 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
1147 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1149 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1150 instead of BASE_REGS. */
1151 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1153 /* When this hook returns true for MODE, the compiler allows
1154 registers explicitly used in the rtl to be used as spill registers
1155 but prevents the compiler from extending the lifetime of these
1157 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1158 arm_small_register_classes_for_mode_p
1160 /* Given an rtx X being reloaded into a reg required to be
1161 in class CLASS, return the class of reg to actually use.
1162 In general this is just CLASS, but for the Thumb core registers and
1163 immediate constants we prefer a LO_REGS class or a subset. */
1164 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1165 (TARGET_32BIT ? (CLASS) : \
1166 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1167 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1168 ? LO_REGS : (CLASS)))
1170 /* Must leave BASE_REGS reloads alone */
1171 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1172 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1173 ? ((true_regnum (X) == -1 ? LO_REGS \
1174 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1178 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1179 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1180 ? ((true_regnum (X) == -1 ? LO_REGS \
1181 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1185 /* Return the register class of a scratch register needed to copy IN into
1186 or out of a register in CLASS in MODE. If it can be done directly,
1187 NO_REGS is returned. */
1188 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1189 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1190 ((TARGET_VFP && TARGET_HARD_FLOAT \
1191 && IS_VFP_CLASS (CLASS)) \
1192 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1193 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1194 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1196 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1197 ? GENERAL_REGS : NO_REGS) \
1198 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1200 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1201 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1202 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1203 ((TARGET_VFP && TARGET_HARD_FLOAT \
1204 && IS_VFP_CLASS (CLASS)) \
1205 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1206 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1207 coproc_secondary_reload_class (MODE, X, TRUE) : \
1208 /* Cannot load constants into Cirrus registers. */ \
1209 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1210 && (CLASS) == CIRRUS_REGS \
1211 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1214 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1215 && CONSTANT_P (X)) \
1217 (((MODE) == HImode && ! arm_arch4 \
1218 && (GET_CODE (X) == MEM \
1219 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1220 && true_regnum (X) == -1))) \
1221 ? GENERAL_REGS : NO_REGS) \
1222 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1224 /* Try a machine-dependent way of reloading an illegitimate address
1225 operand. If we find one, push the reload and jump to WIN. This
1226 macro is used in only one place: `find_reloads_address' in reload.c.
1228 For the ARM, we wish to handle large displacements off a base
1229 register by splitting the addend across a MOV and the mem insn.
1230 This can cut the number of reloads needed. */
1231 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1234 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1239 /* XXX If an HImode FP+large_offset address is converted to an HImode
1240 SP+large_offset address, then reload won't know how to fix it. It sees
1241 only that SP isn't valid for HImode, and so reloads the SP into an index
1242 register, but the resulting address is still invalid because the offset
1243 is too big. We fix it here instead by reloading the entire address. */
1244 /* We could probably achieve better results by defining PROMOTE_MODE to help
1245 cope with the variances between the Thumb's signed and unsigned byte and
1246 halfword load instructions. */
1247 /* ??? This should be safe for thumb2, but we may be able to do better. */
1248 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1250 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1258 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1260 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1262 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1264 /* Return the maximum number of consecutive registers
1265 needed to represent mode MODE in a register of class CLASS.
1266 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1267 #define CLASS_MAX_NREGS(CLASS, MODE) \
1268 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1270 /* If defined, gives a class of registers that cannot be used as the
1271 operand of a SUBREG that changes the mode of the object illegally. */
1273 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1274 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1275 it is typically more expensive than a single memory access. We set
1276 the cost to less than two memory accesses so that floating
1277 point to integer conversion does not go through memory. */
1278 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1280 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1281 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1282 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1283 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
1284 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1285 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1286 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1287 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1288 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1291 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1293 /* Stack layout; function entry, exit and calling. */
1295 /* Define this if pushing a word on the stack
1296 makes the stack pointer a smaller address. */
1297 #define STACK_GROWS_DOWNWARD 1
1299 /* Define this to nonzero if the nominal address of the stack frame
1300 is at the high-address end of the local variables;
1301 that is, each additional local variable allocated
1302 goes at a more negative offset in the frame. */
1303 #define FRAME_GROWS_DOWNWARD 1
1305 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1306 When present, it is one word in size, and sits at the top of the frame,
1307 between the soft frame pointer and either r7 or r11.
1309 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1310 and only then if some outgoing arguments are passed on the stack. It would
1311 be tempting to also check whether the stack arguments are passed by indirect
1312 calls, but there seems to be no reason in principle why a post-reload pass
1313 couldn't convert a direct call into an indirect one. */
1314 #define CALLER_INTERWORKING_SLOT_SIZE \
1315 (TARGET_CALLER_INTERWORKING \
1316 && crtl->outgoing_args_size != 0 \
1317 ? UNITS_PER_WORD : 0)
1319 /* Offset within stack frame to start allocating local variables at.
1320 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1321 first local allocated. Otherwise, it is the offset to the BEGINNING
1322 of the first local allocated. */
1323 #define STARTING_FRAME_OFFSET 0
1325 /* If we generate an insn to push BYTES bytes,
1326 this says how many the stack pointer really advances by. */
1327 /* The push insns do not do this rounding implicitly.
1328 So don't define this. */
1329 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1331 /* Define this if the maximum size of all the outgoing args is to be
1332 accumulated and pushed during the prologue. The amount can be
1333 found in the variable crtl->outgoing_args_size. */
1334 #define ACCUMULATE_OUTGOING_ARGS 1
1336 /* Offset of first parameter from the argument pointer register value. */
1337 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1339 /* Define how to find the value returned by a library function
1340 assuming the value has mode MODE. */
1341 #define LIBCALL_VALUE(MODE) \
1342 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1343 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1344 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1345 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1346 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1347 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1348 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1349 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1350 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1351 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1353 /* 1 if REGNO is a possible register number for a function value. */
1354 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1355 ((REGNO) == ARG_REGISTER (1) \
1356 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1357 && TARGET_VFP && TARGET_HARD_FLOAT \
1358 && (REGNO) == FIRST_VFP_REGNUM) \
1359 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1360 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1361 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1362 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1363 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1365 /* Amount of memory needed for an untyped call to save all possible return
1367 #define APPLY_RESULT_SIZE arm_apply_result_size()
1369 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1370 values must be in memory. On the ARM, they need only do so if larger
1371 than a word, or if they contain elements offset from zero in the struct. */
1372 #define DEFAULT_PCC_STRUCT_RETURN 0
1374 /* These bits describe the different types of function supported
1375 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1376 normal function and an interworked function, for example. Knowing the
1377 type of a function is important for determining its prologue and
1379 Note value 7 is currently unassigned. Also note that the interrupt
1380 function types all have bit 2 set, so that they can be tested for easily.
1381 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1382 machine_function structure is initialized (to zero) func_type will
1383 default to unknown. This will force the first use of arm_current_func_type
1384 to call arm_compute_func_type. */
1385 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1386 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1387 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1388 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1389 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1390 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1392 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1394 /* In addition functions can have several type modifiers,
1395 outlined by these bit masks: */
1396 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1397 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1398 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1399 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1400 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1402 /* Some macros to test these flags. */
1403 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1404 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1405 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1406 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1407 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1408 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1411 /* Structure used to hold the function stack frame layout. Offsets are
1412 relative to the stack pointer on function entry. Positive offsets are
1413 in the direction of stack growth.
1414 Only soft_frame is used in thumb mode. */
1416 typedef struct GTY(()) arm_stack_offsets
1418 int saved_args; /* ARG_POINTER_REGNUM. */
1419 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1421 int soft_frame; /* FRAME_POINTER_REGNUM. */
1422 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1423 int outgoing_args; /* STACK_POINTER_REGNUM. */
1424 unsigned int saved_regs_mask;
1428 #ifndef GENERATOR_FILE
1429 /* A C structure for machine-specific, per-function data.
1430 This is added to the cfun structure. */
1431 typedef struct GTY(()) machine_function
1433 /* Additional stack adjustment in __builtin_eh_throw. */
1434 rtx eh_epilogue_sp_ofs;
1435 /* Records if LR has to be saved for far jumps. */
1437 /* Records if ARG_POINTER was ever live. */
1438 int arg_pointer_live;
1439 /* Records if the save of LR has been eliminated. */
1440 int lr_save_eliminated;
1441 /* The size of the stack frame. Only valid after reload. */
1442 arm_stack_offsets stack_offsets;
1443 /* Records the type of the current function. */
1444 unsigned long func_type;
1445 /* Record if the function has a variable argument list. */
1446 int uses_anonymous_args;
1447 /* Records if sibcalls are blocked because an argument
1448 register is needed to preserve stack alignment. */
1449 int sibcall_blocked;
1450 /* The PIC register for this function. This might be a pseudo. */
1452 /* Labels for per-function Thumb call-via stubs. One per potential calling
1453 register. We can never call via LR or PC. We can call via SP if a
1454 trampoline happens to be on the top of the stack. */
1456 /* Set to 1 when a return insn is output, this means that the epilogue
1458 int return_used_this_function;
1459 /* When outputting Thumb-1 code, record the last insn that provides
1460 information about condition codes, and the comparison operands. */
1464 /* Also record the CC mode that is supported. */
1465 enum machine_mode thumb1_cc_mode;
1470 /* As in the machine_function, a global set of call-via labels, for code
1471 that is in text_section. */
1472 extern GTY(()) rtx thumb_call_via_label[14];
1474 /* The number of potential ways of assigning to a co-processor. */
1475 #define ARM_NUM_COPROC_SLOTS 1
1477 /* Enumeration of procedure calling standard variants. We don't really
1478 support all of these yet. */
1481 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1482 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1483 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1484 /* This must be the last AAPCS variant. */
1485 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1486 ARM_PCS_ATPCS, /* ATPCS. */
1487 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1491 /* Default procedure calling standard of current compilation unit. */
1492 extern enum arm_pcs arm_pcs_default;
1494 /* A C type for declaring a variable that is used as the first argument of
1495 `FUNCTION_ARG' and other related values. */
1498 /* This is the number of registers of arguments scanned so far. */
1500 /* This is the number of iWMMXt register arguments scanned so far. */
1504 /* Which procedure call variant to use for this call. */
1505 enum arm_pcs pcs_variant;
1507 /* AAPCS related state tracking. */
1508 int aapcs_arg_processed; /* No need to lay out this argument again. */
1509 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1510 this argument, or -1 if using core
1513 int aapcs_next_ncrn;
1514 rtx aapcs_reg; /* Register assigned to this argument. */
1515 int aapcs_partial; /* How many bytes are passed in regs (if
1516 split between core regs and stack.
1518 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1519 int can_split; /* Argument can be split between core regs
1521 /* Private data for tracking VFP register allocation */
1522 unsigned aapcs_vfp_regs_free;
1523 unsigned aapcs_vfp_reg_alloc;
1524 int aapcs_vfp_rcount;
1525 MACHMODE aapcs_vfp_rmode;
1528 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1529 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1531 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1532 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1534 /* For AAPCS, padding should never be below the argument. For other ABIs,
1535 * mimic the default. */
1536 #define PAD_VARARGS_DOWN \
1537 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1539 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1540 for a call to a function whose data type is FNTYPE.
1541 For a library call, FNTYPE is 0.
1542 On the ARM, the offset starts at 0. */
1543 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1544 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1546 /* 1 if N is a possible register number for function argument passing.
1547 On the ARM, r0-r3 are used to pass args. */
1548 #define FUNCTION_ARG_REGNO_P(REGNO) \
1549 (IN_RANGE ((REGNO), 0, 3) \
1550 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1551 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1552 || (TARGET_IWMMXT_ABI \
1553 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1556 /* If your target environment doesn't prefix user functions with an
1557 underscore, you may wish to re-define this to prevent any conflicts. */
1558 #ifndef ARM_MCOUNT_NAME
1559 #define ARM_MCOUNT_NAME "*mcount"
1562 /* Call the function profiler with a given profile label. The Acorn
1563 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1564 On the ARM the full profile code will look like:
1573 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1574 will output the .text section.
1576 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1577 ``prof'' doesn't seem to mind about this!
1579 Note - this version of the code is designed to work in both ARM and
1581 #ifndef ARM_FUNCTION_PROFILER
1582 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1587 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1588 IP_REGNUM, LR_REGNUM); \
1589 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1590 fputc ('\n', STREAM); \
1591 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1592 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1593 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1597 #ifdef THUMB_FUNCTION_PROFILER
1598 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1600 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1602 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1604 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1605 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1608 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1609 the stack pointer does not matter. The value is tested only in
1610 functions that have frame pointers.
1611 No definition is equivalent to always zero.
1613 On the ARM, the function epilogue recovers the stack pointer from the
1615 #define EXIT_IGNORE_STACK 1
1617 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1619 /* Determine if the epilogue should be output as RTL.
1620 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1621 #define USE_RETURN_INSN(ISCOND) \
1622 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1624 /* Definitions for register eliminations.
1626 This is an array of structures. Each structure initializes one pair
1627 of eliminable registers. The "from" register number is given first,
1628 followed by "to". Eliminations of the same "from" register are listed
1629 in order of preference.
1631 We have two registers that can be eliminated on the ARM. First, the
1632 arg pointer register can often be eliminated in favor of the stack
1633 pointer register. Secondly, the pseudo frame pointer register can always
1634 be eliminated; it is replaced with either the stack or the real frame
1635 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1636 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1638 #define ELIMINABLE_REGS \
1639 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1640 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1641 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1642 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1643 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1644 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1645 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1647 /* Define the offset between two registers, one to be eliminated, and the
1648 other its replacement, at the start of a routine. */
1649 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1651 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1653 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1655 /* Special case handling of the location of arguments passed on the stack. */
1656 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1658 /* Initialize data used by insn expanders. This is called from insn_emit,
1659 once for every function before code is generated. */
1660 #define INIT_EXPANDERS arm_init_expanders ()
1662 /* Length in units of the trampoline for entering a nested function. */
1663 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1665 /* Alignment required for a trampoline in bits. */
1666 #define TRAMPOLINE_ALIGNMENT 32
1668 /* Addressing modes, and classification of registers for them. */
1669 #define HAVE_POST_INCREMENT 1
1670 #define HAVE_PRE_INCREMENT TARGET_32BIT
1671 #define HAVE_POST_DECREMENT TARGET_32BIT
1672 #define HAVE_PRE_DECREMENT TARGET_32BIT
1673 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1674 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1675 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1676 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1678 /* Macros to check register numbers against specific register classes. */
1680 /* These assume that REGNO is a hard or pseudo reg number.
1681 They give nonzero only if REGNO is a hard reg of the suitable class
1682 or a pseudo reg currently allocated to a suitable hard reg.
1683 Since they use reg_renumber, they are safe only once reg_renumber
1684 has been allocated, which happens in local-alloc.c. */
1685 #define TEST_REGNO(R, TEST, VALUE) \
1686 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1688 /* Don't allow the pc to be used. */
1689 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1690 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1691 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1692 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1694 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1695 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1696 || (GET_MODE_SIZE (MODE) >= 4 \
1697 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1699 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1701 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1702 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1704 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1705 For Thumb, we can not use SP + reg, so reject SP. */
1706 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1707 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1709 /* For ARM code, we don't care about the mode, but for Thumb, the index
1710 must be suitable for use in a QImode load. */
1711 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1712 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1713 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1715 /* Maximum number of registers that can appear in a valid memory address.
1716 Shifts in addresses can't be by a register. */
1717 #define MAX_REGS_PER_ADDRESS 2
1719 /* Recognize any constant value that is a valid address. */
1720 /* XXX We can address any constant, eventually... */
1721 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1722 #define CONSTANT_ADDRESS_P(X) \
1723 (GET_CODE (X) == SYMBOL_REF \
1724 && (CONSTANT_POOL_ADDRESS_P (X) \
1725 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1727 /* True if SYMBOL + OFFSET constants must refer to something within
1728 SYMBOL's section. */
1729 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1731 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1732 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1733 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1736 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1737 #define SUBTARGET_NAME_ENCODING_LENGTHS
1740 /* This is a C fragment for the inside of a switch statement.
1741 Each case label should return the number of characters to
1742 be stripped from the start of a function's name, if that
1743 name starts with the indicated character. */
1744 #define ARM_NAME_ENCODING_LENGTHS \
1745 case '*': return 1; \
1746 SUBTARGET_NAME_ENCODING_LENGTHS
1748 /* This is how to output a reference to a user-level label named NAME.
1749 `assemble_name' uses this. */
1750 #undef ASM_OUTPUT_LABELREF
1751 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1752 arm_asm_output_labelref (FILE, NAME)
1754 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1755 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1756 if (TARGET_THUMB2) \
1757 thumb2_asm_output_opcode (STREAM);
1759 /* The EABI specifies that constructors should go in .init_array.
1760 Other targets use .ctors for compatibility. */
1761 #ifndef ARM_EABI_CTORS_SECTION_OP
1762 #define ARM_EABI_CTORS_SECTION_OP \
1763 "\t.section\t.init_array,\"aw\",%init_array"
1765 #ifndef ARM_EABI_DTORS_SECTION_OP
1766 #define ARM_EABI_DTORS_SECTION_OP \
1767 "\t.section\t.fini_array,\"aw\",%fini_array"
1769 #define ARM_CTORS_SECTION_OP \
1770 "\t.section\t.ctors,\"aw\",%progbits"
1771 #define ARM_DTORS_SECTION_OP \
1772 "\t.section\t.dtors,\"aw\",%progbits"
1774 /* Define CTORS_SECTION_ASM_OP. */
1775 #undef CTORS_SECTION_ASM_OP
1776 #undef DTORS_SECTION_ASM_OP
1778 # define CTORS_SECTION_ASM_OP \
1779 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1780 # define DTORS_SECTION_ASM_OP \
1781 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1782 #else /* !defined (IN_LIBGCC2) */
1783 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1784 so we cannot use the definition above. */
1785 # ifdef __ARM_EABI__
1786 /* The .ctors section is not part of the EABI, so we do not define
1787 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1788 from trying to use it. We do define it when doing normal
1789 compilation, as .init_array can be used instead of .ctors. */
1790 /* There is no need to emit begin or end markers when using
1791 init_array; the dynamic linker will compute the size of the
1792 array itself based on special symbols created by the static
1793 linker. However, we do need to arrange to set up
1794 exception-handling here. */
1795 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1796 # define CTOR_LIST_END /* empty */
1797 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1798 # define DTOR_LIST_END /* empty */
1799 # else /* !defined (__ARM_EABI__) */
1800 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1801 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1802 # endif /* !defined (__ARM_EABI__) */
1803 #endif /* !defined (IN_LIBCC2) */
1805 /* True if the operating system can merge entities with vague linkage
1806 (e.g., symbols in COMDAT group) during dynamic linking. */
1807 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1808 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1811 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1813 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1814 and check its validity for a certain class.
1815 We have two alternate definitions for each of them.
1816 The usual definition accepts all pseudo regs; the other rejects
1817 them unless they have been allocated suitable hard regs.
1818 The symbol REG_OK_STRICT causes the latter definition to be used.
1819 Thumb-2 has the same restrictions as arm. */
1820 #ifndef REG_OK_STRICT
1822 #define ARM_REG_OK_FOR_BASE_P(X) \
1823 (REGNO (X) <= LAST_ARM_REGNUM \
1824 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1825 || REGNO (X) == FRAME_POINTER_REGNUM \
1826 || REGNO (X) == ARG_POINTER_REGNUM)
1828 #define ARM_REG_OK_FOR_INDEX_P(X) \
1829 ((REGNO (X) <= LAST_ARM_REGNUM \
1830 && REGNO (X) != STACK_POINTER_REGNUM) \
1831 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1832 || REGNO (X) == FRAME_POINTER_REGNUM \
1833 || REGNO (X) == ARG_POINTER_REGNUM)
1835 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1836 (REGNO (X) <= LAST_LO_REGNUM \
1837 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1838 || (GET_MODE_SIZE (MODE) >= 4 \
1839 && (REGNO (X) == STACK_POINTER_REGNUM \
1840 || (X) == hard_frame_pointer_rtx \
1841 || (X) == arg_pointer_rtx)))
1843 #define REG_STRICT_P 0
1845 #else /* REG_OK_STRICT */
1847 #define ARM_REG_OK_FOR_BASE_P(X) \
1848 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1850 #define ARM_REG_OK_FOR_INDEX_P(X) \
1851 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1853 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1854 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1856 #define REG_STRICT_P 1
1858 #endif /* REG_OK_STRICT */
1860 /* Now define some helpers in terms of the above. */
1862 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1864 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1865 : ARM_REG_OK_FOR_BASE_P (X))
1867 /* For 16-bit Thumb, a valid index register is anything that can be used in
1868 a byte load instruction. */
1869 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1870 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1872 /* Nonzero if X is a hard reg that can be used as an index
1873 or if it is a pseudo reg. On the Thumb, the stack pointer
1875 #define REG_OK_FOR_INDEX_P(X) \
1877 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1878 : ARM_REG_OK_FOR_INDEX_P (X))
1880 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1881 For Thumb, we can not use SP + reg, so reject SP. */
1882 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1883 REG_OK_FOR_INDEX_P (X)
1885 #define ARM_BASE_REGISTER_RTX_P(X) \
1886 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1888 #define ARM_INDEX_REGISTER_RTX_P(X) \
1889 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1891 /* Specify the machine mode that this machine uses
1892 for the index in the tablejump instruction. */
1893 #define CASE_VECTOR_MODE Pmode
1895 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
1897 && (optimize_size || flag_pic)))
1899 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1901 ? (min >= 0 && max < 512 \
1902 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1903 : min >= -256 && max < 256 \
1904 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1905 : min >= 0 && max < 8192 \
1906 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1907 : min >= -4096 && max < 4096 \
1908 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1910 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
1911 : (max >= 0x200) ? HImode \
1914 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1915 unsigned is probably best, but may break some code. */
1916 #ifndef DEFAULT_SIGNED_CHAR
1917 #define DEFAULT_SIGNED_CHAR 0
1920 /* Max number of bytes we can move from memory to memory
1921 in one reasonably fast instruction. */
1925 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
1927 /* Define if operations between registers always perform the operation
1928 on the full register even if a narrower mode is specified. */
1929 #define WORD_REGISTER_OPERATIONS
1931 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1932 will either zero-extend or sign-extend. The value of this macro should
1933 be the code that says which one of the two operations is implicitly
1934 done, UNKNOWN if none. */
1935 #define LOAD_EXTEND_OP(MODE) \
1936 (TARGET_THUMB ? ZERO_EXTEND : \
1937 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1938 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
1940 /* Nonzero if access to memory by bytes is slow and undesirable. */
1941 #define SLOW_BYTE_ACCESS 0
1943 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
1945 /* Immediate shift counts are truncated by the output routines (or was it
1946 the assembler?). Shift counts in a register are truncated by ARM. Note
1947 that the native compiler puts too large (> 32) immediate shift counts
1948 into a register and shifts by the register, letting the ARM decide what
1949 to do instead of doing that itself. */
1950 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1951 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1952 On the arm, Y in a register is used modulo 256 for the shift. Only for
1953 rotates is modulo 32 used. */
1954 /* #define SHIFT_COUNT_TRUNCATED 1 */
1956 /* All integers have the same format so truncation is easy. */
1957 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1959 /* Calling from registers is a massive pain. */
1960 #define NO_FUNCTION_CSE 1
1962 /* The machine modes of pointers and functions */
1963 #define Pmode SImode
1964 #define FUNCTION_MODE Pmode
1966 #define ARM_FRAME_RTX(X) \
1967 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1968 || (X) == arg_pointer_rtx)
1970 /* Moves to and from memory are quite expensive */
1971 #define MEMORY_MOVE_COST(M, CLASS, IN) \
1972 (TARGET_32BIT ? 10 : \
1973 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
1974 * (CLASS == LO_REGS ? 1 : 2)))
1976 /* Try to generate sequences that don't involve branches, we can then use
1977 conditional instructions */
1978 #define BRANCH_COST(speed_p, predictable_p) \
1979 (current_tune->branch_cost (speed_p, predictable_p))
1982 /* Position Independent Code. */
1983 /* We decide which register to use based on the compilation options and
1984 the assembler in use; this is more general than the APCS restriction of
1985 using sb (r9) all the time. */
1986 extern unsigned arm_pic_register;
1988 /* The register number of the register used to address a table of static
1989 data addresses in memory. */
1990 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1992 /* We can't directly access anything that contains a symbol,
1993 nor can we indirect via the constant pool. One exception is
1994 UNSPEC_TLS, which is always PIC. */
1995 #define LEGITIMATE_PIC_OPERAND_P(X) \
1996 (!(symbol_mentioned_p (X) \
1997 || label_mentioned_p (X) \
1998 || (GET_CODE (X) == SYMBOL_REF \
1999 && CONSTANT_POOL_ADDRESS_P (X) \
2000 && (symbol_mentioned_p (get_pool_constant (X)) \
2001 || label_mentioned_p (get_pool_constant (X))))) \
2002 || tls_mentioned_p (X))
2004 /* We need to know when we are making a constant pool; this determines
2005 whether data needs to be in the GOT or can be referenced via a GOT
2007 extern int making_const_table;
2009 /* Handle pragmas for compatibility with Intel's compilers. */
2010 /* Also abuse this to register additional C specific EABI attributes. */
2011 #define REGISTER_TARGET_PRAGMAS() do { \
2012 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2013 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2014 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2015 arm_lang_object_attributes_init(); \
2018 /* Condition code information. */
2019 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2020 return the mode to be used for the comparison. */
2022 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2024 #define REVERSIBLE_CC_MODE(MODE) 1
2026 #define REVERSE_CONDITION(CODE,MODE) \
2027 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2028 ? reverse_condition_maybe_unordered (code) \
2029 : reverse_condition (code))
2031 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2032 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2034 /* The arm5 clz instruction returns 32. */
2035 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2036 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2038 #define CC_STATUS_INIT \
2039 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2042 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2043 TARGET_THUMB2 ? "\t.thumb\n" : "")
2045 /* Output a push or a pop instruction (only used when profiling).
2046 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2047 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2048 that r7 isn't used by the function profiler, so we can use it as a
2049 scratch reg. WARNING: This isn't safe in the general case! It may be
2050 sensitive to future changes in final.c:profile_function. */
2051 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2055 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2056 STACK_POINTER_REGNUM, REGNO); \
2057 else if (TARGET_THUMB1 \
2058 && (REGNO) == STATIC_CHAIN_REGNUM) \
2060 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2061 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2062 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2065 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2069 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2070 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2074 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2075 STACK_POINTER_REGNUM, REGNO); \
2076 else if (TARGET_THUMB1 \
2077 && (REGNO) == STATIC_CHAIN_REGNUM) \
2079 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2080 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2081 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2084 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2087 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2088 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2090 /* This is how to output a label which precedes a jumptable. Since
2091 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2092 #undef ASM_OUTPUT_CASE_LABEL
2093 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2096 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2097 ASM_OUTPUT_ALIGN (FILE, 2); \
2098 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2102 /* Make sure subsequent insns are aligned after a TBB. */
2103 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2106 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2107 ASM_OUTPUT_ALIGN (FILE, 1); \
2111 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2116 if (is_called_in_ARM_mode (DECL) \
2117 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2118 && cfun->is_thunk)) \
2119 fprintf (STREAM, "\t.code 32\n") ; \
2120 else if (TARGET_THUMB1) \
2121 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2123 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2125 if (TARGET_POKE_FUNCTION_NAME) \
2126 arm_poke_function_name (STREAM, (const char *) NAME); \
2130 /* For aliases of functions we use .thumb_set instead. */
2131 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2134 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2135 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2137 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2139 fprintf (FILE, "\t.thumb_set "); \
2140 assemble_name (FILE, LABEL1); \
2141 fprintf (FILE, ","); \
2142 assemble_name (FILE, LABEL2); \
2143 fprintf (FILE, "\n"); \
2146 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2150 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2151 /* To support -falign-* switches we need to use .p2align so
2152 that alignment directives in code sections will be padded
2153 with no-op instructions, rather than zeroes. */
2154 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2157 if ((MAX_SKIP) == 0) \
2158 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2160 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2161 (int) (LOG), (int) (MAX_SKIP)); \
2165 /* Add two bytes to the length of conditionally executed Thumb-2
2166 instructions for the IT instruction. */
2167 #define ADJUST_INSN_LENGTH(insn, length) \
2168 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2171 /* Only perform branch elimination (by making instructions conditional) if
2172 we're optimizing. For Thumb-2 check if any IT instructions need
2174 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2175 if (TARGET_ARM && optimize) \
2176 arm_final_prescan_insn (INSN); \
2177 else if (TARGET_THUMB2) \
2178 thumb2_final_prescan_insn (INSN); \
2179 else if (TARGET_THUMB1) \
2180 thumb1_final_prescan_insn (INSN)
2182 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2183 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2184 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2185 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2186 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2187 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2190 /* A C expression whose value is RTL representing the value of the return
2191 address for the frame COUNT steps up from the current frame. */
2193 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2194 arm_return_addr (COUNT, FRAME)
2196 /* Mask of the bits in the PC that contain the real return address
2197 when running in 26-bit mode. */
2198 #define RETURN_ADDR_MASK26 (0x03fffffc)
2200 /* Pick up the return address upon entry to a procedure. Used for
2201 dwarf2 unwind information. This also enables the table driven
2203 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2204 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2206 /* Used to mask out junk bits from the return address, such as
2207 processor state, interrupt status, condition codes and the like. */
2208 #define MASK_RETURN_ADDR \
2209 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2210 in 26 bit mode, the condition codes must be masked out of the \
2211 return address. This does not apply to ARM6 and later processors \
2212 when running in 32 bit mode. */ \
2213 ((arm_arch4 || TARGET_THUMB) \
2214 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2215 : arm_gen_return_addr_mask ())
2218 /* Do not emit .note.GNU-stack by default. */
2219 #ifndef NEED_INDICATE_EXEC_STACK
2220 #define NEED_INDICATE_EXEC_STACK 0
2223 /* The maximum number of parallel loads or stores we support in an ldm/stm
2225 #define MAX_LDM_STM_OPS 4
2227 #define ASM_CPU_SPEC \
2228 " %{mcpu=generic-*:-march=%*;" \
2229 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
2231 #endif /* ! GCC_ARM_H */
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