1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
43 #include "arm-protos.h"
45 /* The maximum number of insns skipped which will be conditionalised if
47 static int max_insns_skipped = 5;
49 extern FILE * asm_out_file;
50 /* Some function declarations. */
53 #define Mmode enum machine_mode
56 static HOST_WIDE_INT int_log2 PARAMS ((HOST_WIDE_INT));
57 static char * output_multi_immediate PARAMS ((rtx *, char *, char *, int, HOST_WIDE_INT));
58 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, HOST_WIDE_INT, rtx, rtx, int, int));
59 static int arm_naked_function_p PARAMS ((tree));
60 static void init_fpa_table PARAMS ((void));
61 static enum machine_mode select_dominance_cc_mode PARAMS ((rtx, rtx, HOST_WIDE_INT));
62 static HOST_WIDE_INT add_minipool_constant PARAMS ((rtx, Mmode));
63 static void dump_minipool PARAMS ((rtx));
64 static rtx find_barrier PARAMS ((rtx, int));
65 static void push_minipool_fix PARAMS ((rtx, int, rtx *, Mmode, rtx));
66 static void push_minipool_barrier PARAMS ((rtx, int));
67 static void note_invalid_constants PARAMS ((rtx, int));
68 static char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
69 static int eliminate_lr2ip PARAMS ((rtx *));
70 static char * shift_op PARAMS ((rtx, HOST_WIDE_INT *));
71 static int pattern_really_clobbers_lr PARAMS ((rtx));
72 static int function_really_clobbers_lr PARAMS ((rtx));
73 static void emit_multi_reg_push PARAMS ((int));
74 static void emit_sfm PARAMS ((int, int));
75 static enum arm_cond_code get_arm_condition_code PARAMS ((rtx));
76 static int const_ok_for_op PARAMS ((HOST_WIDE_INT, enum rtx_code));
77 static void arm_add_gc_roots PARAMS ((void));
79 /* True if we are currently building a constant table. */
80 int making_const_table;
82 /* Define the information needed to generate branch insns. This is
83 stored from the compare operation. */
84 rtx arm_compare_op0, arm_compare_op1;
86 /* What type of floating point are we tuning for? */
87 enum floating_point_type arm_fpu;
89 /* What type of floating point instructions are available? */
90 enum floating_point_type arm_fpu_arch;
92 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
93 enum prog_mode_type arm_prgmode;
95 /* Set by the -mfp=... option */
96 const char * target_fp_name = NULL;
98 /* Used to parse -mstructure_size_boundary command line option. */
99 const char * structure_size_string = NULL;
100 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
102 /* Bit values used to identify processor capabilities. */
103 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
104 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
105 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
106 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
107 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
108 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
109 #define FL_THUMB (1 << 6) /* Thumb aware */
110 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
111 #define FL_STRONG (1 << 8) /* StrongARM */
113 /* The bits in this mask specify which instructions we are allowed to
115 static int insn_flags = 0;
116 /* The bits in this mask specify which instruction scheduling options should
117 be used. Note - there is an overlap with the FL_FAST_MULT. For some
118 hardware we want to be able to generate the multiply instructions, but to
119 tune as if they were not present in the architecture. */
120 static int tune_flags = 0;
122 /* The following are used in the arm.md file as equivalents to bits
123 in the above two flag variables. */
125 /* Nonzero if this is an "M" variant of the processor. */
126 int arm_fast_multiply = 0;
128 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
131 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
134 /* Nonzero if this chip can benefit from load scheduling. */
135 int arm_ld_sched = 0;
137 /* Nonzero if this chip is a StrongARM. */
138 int arm_is_strong = 0;
140 /* Nonzero if this chip is a an ARM6 or an ARM7. */
141 int arm_is_6_or_7 = 0;
143 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
144 must report the mode of the memory reference from PRINT_OPERAND to
145 PRINT_OPERAND_ADDRESS. */
146 enum machine_mode output_memory_reference_mode;
148 /* Nonzero if the prologue must setup `fp'. */
149 int current_function_anonymous_args;
151 /* The register number to be used for the PIC offset register. */
152 const char * arm_pic_register_string = NULL;
153 int arm_pic_register = 9;
155 /* Set to one if we think that lr is only saved because of subroutine calls,
156 but all of these can be `put after' return insns */
157 int lr_save_eliminated;
159 /* Set to 1 when a return insn is output, this means that the epilogue
161 static int return_used_this_function;
163 /* Set to 1 after arm_reorg has started. Reset to start at the start of
164 the next function. */
165 static int after_arm_reorg = 0;
167 /* The maximum number of insns to be used when loading a constant. */
168 static int arm_constant_limit = 3;
170 /* For an explanation of these variables, see final_prescan_insn below. */
172 enum arm_cond_code arm_current_cc;
174 int arm_target_label;
176 /* The condition codes of the ARM, and the inverse function. */
177 char * arm_condition_codes[] =
179 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
180 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
183 static enum arm_cond_code get_arm_condition_code ();
185 #define streq(string1, string2) (strcmp (string1, string2) == 0)
187 /* Initialization code */
195 /* Not all of these give usefully different compilation alternatives,
196 but there is no simple way of generalizing them. */
197 static struct processors all_cores[] =
201 {"arm2", FL_CO_PROC | FL_MODE26 },
202 {"arm250", FL_CO_PROC | FL_MODE26 },
203 {"arm3", FL_CO_PROC | FL_MODE26 },
204 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
205 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
206 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm610", FL_MODE26 | FL_MODE32 },
208 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
210 /* arm7m doesn't exist on its own, but only with D, (and I), but
211 those don't alter the code, so arm7m is sometimes used. */
212 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
213 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
214 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
215 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
216 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
217 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
218 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
219 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
220 {"arm710", FL_MODE26 | FL_MODE32 },
221 {"arm720", FL_MODE26 | FL_MODE32 },
222 {"arm710c", FL_MODE26 | FL_MODE32 },
223 {"arm7100", FL_MODE26 | FL_MODE32 },
224 {"arm7500", FL_MODE26 | FL_MODE32 },
225 /* Doesn't have an external co-proc, but does have embedded fpu. */
226 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
227 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
228 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
229 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
230 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
231 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
232 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
233 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
234 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
235 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
236 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
241 static struct processors all_architectures[] =
243 /* ARM Architectures */
245 { "armv2", FL_CO_PROC | FL_MODE26 },
246 { "armv2a", FL_CO_PROC | FL_MODE26 },
247 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
248 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
249 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
250 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
251 implementations that support it, so we will leave it out for now. */
252 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
253 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
257 /* This is a magic stucture. The 'string' field is magically filled in
258 with a pointer to the value specified by the user on the command line
259 assuming that the user has specified such a value. */
261 struct arm_cpu_select arm_select[] =
263 /* string name processors */
264 { NULL, "-mcpu=", all_cores },
265 { NULL, "-march=", all_architectures },
266 { NULL, "-mtune=", all_cores }
269 /* Return the number of bits set in value' */
274 unsigned int count = 0;
278 value &= ~(value & - value);
285 /* Fix up any incompatible options that the user has specified.
286 This has now turned into a maze. */
288 arm_override_options ()
292 /* Set up the flags based on the cpu/architecture selected by the user. */
293 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
295 struct arm_cpu_select * ptr = arm_select + i;
297 if (ptr->string != NULL && ptr->string[0] != '\0')
299 const struct processors * sel;
301 for (sel = ptr->processors; sel->name != NULL; sel ++)
302 if (streq (ptr->string, sel->name))
305 tune_flags = sel->flags;
308 /* If we have been given an architecture and a processor
309 make sure that they are compatible. We only generate
310 a warning though, and we prefer the CPU over the
312 if (insn_flags != 0 && (insn_flags ^ sel->flags))
313 warning ("switch -mcpu=%s conflicts with -march= switch",
316 insn_flags = sel->flags;
322 if (sel->name == NULL)
323 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
327 /* If the user did not specify a processor, choose one for them. */
330 struct processors * sel;
332 static struct cpu_default
339 { TARGET_CPU_arm2, "arm2" },
340 { TARGET_CPU_arm6, "arm6" },
341 { TARGET_CPU_arm610, "arm610" },
342 { TARGET_CPU_arm710, "arm710" },
343 { TARGET_CPU_arm7m, "arm7m" },
344 { TARGET_CPU_arm7500fe, "arm7500fe" },
345 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
346 { TARGET_CPU_arm8, "arm8" },
347 { TARGET_CPU_arm810, "arm810" },
348 { TARGET_CPU_arm9, "arm9" },
349 { TARGET_CPU_strongarm, "strongarm" },
350 { TARGET_CPU_generic, "arm" },
353 struct cpu_default * def;
355 /* Find the default. */
356 for (def = cpu_defaults; def->name; def ++)
357 if (def->cpu == TARGET_CPU_DEFAULT)
360 /* Make sure we found the default CPU. */
361 if (def->name == NULL)
364 /* Find the default CPU's flags. */
365 for (sel = all_cores; sel->name != NULL; sel ++)
366 if (streq (def->name, sel->name))
369 if (sel->name == NULL)
372 insn_flags = sel->flags;
374 /* Now check to see if the user has specified some command line
375 switch that require certain abilities from the cpu. */
378 if (TARGET_INTERWORK)
380 sought |= (FL_THUMB | FL_MODE32);
382 /* Force apcs-32 to be used for interworking. */
383 target_flags |= ARM_FLAG_APCS_32;
385 /* There are no ARM processor that supports both APCS-26 and
386 interworking. Therefore we force FL_MODE26 to be removed
387 from insn_flags here (if it was set), so that the search
388 below will always be able to find a compatible processor. */
389 insn_flags &= ~ FL_MODE26;
392 if (! TARGET_APCS_32)
395 if (sought != 0 && ((sought & insn_flags) != sought))
397 /* Try to locate a CPU type that supports all of the abilities
398 of the default CPU, plus the extra abilities requested by
400 for (sel = all_cores; sel->name != NULL; sel ++)
401 if ((sel->flags & sought) == (sought | insn_flags))
404 if (sel->name == NULL)
406 unsigned int current_bit_count = 0;
407 struct processors * best_fit = NULL;
409 /* Ideally we would like to issue an error message here
410 saying that it was not possible to find a CPU compatible
411 with the default CPU, but which also supports the command
412 line options specified by the programmer, and so they
413 ought to use the -mcpu=<name> command line option to
414 override the default CPU type.
416 Unfortunately this does not work with multilibing. We
417 need to be able to support multilibs for -mapcs-26 and for
418 -mthumb-interwork and there is no CPU that can support both
419 options. Instead if we cannot find a cpu that has both the
420 characteristics of the default cpu and the given command line
421 options we scan the array again looking for a best match. */
422 for (sel = all_cores; sel->name != NULL; sel ++)
423 if ((sel->flags & sought) == sought)
427 count = bit_count (sel->flags & insn_flags);
429 if (count >= current_bit_count)
432 current_bit_count = count;
436 if (best_fit == NULL)
442 insn_flags = sel->flags;
446 /* If tuning has not been specified, tune for whichever processor or
447 architecture has been selected. */
449 tune_flags = insn_flags;
451 /* Make sure that the processor choice does not conflict with any of the
452 other command line choices. */
453 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
455 /* If APCS-32 was not the default then it must have been set by the
456 user, so issue a warning message. If the user has specified
457 "-mapcs-32 -mcpu=arm2" then we loose here. */
458 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
459 warning ("target CPU does not support APCS-32" );
460 target_flags &= ~ ARM_FLAG_APCS_32;
462 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
464 warning ("target CPU does not support APCS-26" );
465 target_flags |= ARM_FLAG_APCS_32;
468 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
470 warning ("target CPU does not support interworking" );
471 target_flags &= ~ARM_FLAG_INTERWORK;
474 /* If interworking is enabled then APCS-32 must be selected as well. */
475 if (TARGET_INTERWORK)
477 if (! TARGET_APCS_32)
478 warning ("interworking forces APCS-32 to be used" );
479 target_flags |= ARM_FLAG_APCS_32;
482 if (TARGET_APCS_STACK && ! TARGET_APCS)
484 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
485 target_flags |= ARM_FLAG_APCS_FRAME;
488 if (TARGET_POKE_FUNCTION_NAME)
489 target_flags |= ARM_FLAG_APCS_FRAME;
491 if (TARGET_APCS_REENT && flag_pic)
492 fatal ("-fpic and -mapcs-reent are incompatible");
494 if (TARGET_APCS_REENT)
495 warning ("APCS reentrant code not supported. Ignored");
497 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
498 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
500 /* If stack checking is disabled, we can use r10 as the PIC register,
501 which keeps r9 available. */
502 if (flag_pic && ! TARGET_APCS_STACK)
503 arm_pic_register = 10;
505 if (TARGET_APCS_FLOAT)
506 warning ("Passing floating point arguments in fp regs not yet supported");
508 /* Initialise boolean versions of the flags, for use in the arm.md file. */
509 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
510 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
511 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
513 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
514 arm_is_strong = (tune_flags & FL_STRONG) != 0;
515 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
516 && !(tune_flags & FL_ARCH4)) != 0;
518 /* Default value for floating point code... if no co-processor
519 bus, then schedule for emulated floating point. Otherwise,
520 assume the user has an FPA.
521 Note: this does not prevent use of floating point instructions,
522 -msoft-float does that. */
523 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
527 if (streq (target_fp_name, "2"))
528 arm_fpu_arch = FP_SOFT2;
529 else if (streq (target_fp_name, "3"))
530 arm_fpu_arch = FP_SOFT3;
532 fatal ("Invalid floating point emulation option: -mfpe-%s",
536 arm_fpu_arch = FP_DEFAULT;
538 if (TARGET_FPE && arm_fpu != FP_HARD)
541 /* For arm2/3 there is no need to do any scheduling if there is only
542 a floating point emulator, or we are doing software floating-point. */
543 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
544 && (tune_flags & FL_MODE32) == 0)
545 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
547 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
549 if (structure_size_string != NULL)
551 int size = strtol (structure_size_string, NULL, 0);
553 if (size == 8 || size == 32)
554 arm_structure_size_boundary = size;
556 warning ("Structure size boundary can only be set to 8 or 32");
559 if (arm_pic_register_string != NULL)
564 warning ("-mpic-register= is useless without -fpic");
566 pic_register = decode_reg_name (arm_pic_register_string);
568 /* Prevent the user from choosing an obviously stupid PIC register. */
569 if (pic_register < 0 || call_used_regs[pic_register]
570 || pic_register == HARD_FRAME_POINTER_REGNUM
571 || pic_register == STACK_POINTER_REGNUM
572 || pic_register >= PC_REGNUM)
573 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
575 arm_pic_register = pic_register;
578 /* If optimizing for space, don't synthesize constants.
579 For processors with load scheduling, it never costs more than 2 cycles
580 to load a constant, and the load scheduler may well reduce that to 1. */
581 if (optimize_size || (tune_flags & FL_LDSCHED))
582 arm_constant_limit = 1;
584 /* If optimizing for size, bump the number of instructions that we
585 are prepared to conditionally execute (even on a StrongARM).
586 Otherwise for the StrongARM, which has early execution of branches,
587 a sequence that is worth skipping is shorter. */
589 max_insns_skipped = 6;
590 else if (arm_is_strong)
591 max_insns_skipped = 3;
593 /* Register global variables with the garbage collector. */
600 ggc_add_rtx_root (&arm_compare_op0, 1);
601 ggc_add_rtx_root (&arm_compare_op1, 1);
602 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
603 /* XXX: What about the minipool tables? */
607 /* Return 1 if it is possible to return using a single instruction */
610 use_return_insn (iscond)
615 if (!reload_completed
616 || current_function_pretend_args_size
617 || current_function_anonymous_args
618 || ((get_frame_size () + current_function_outgoing_args_size != 0)
619 && !(TARGET_APCS && frame_pointer_needed)))
622 /* Can't be done if interworking with Thumb, and any registers have been
623 stacked. Similarly, on StrongARM, conditional returns are expensive
624 if they aren't taken and registers have been stacked. */
625 if (iscond && arm_is_strong && frame_pointer_needed)
627 if ((iscond && arm_is_strong)
630 for (regno = 0; regno < 16; regno++)
631 if (regs_ever_live[regno] && ! call_used_regs[regno])
634 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
638 /* Can't be done if any of the FPU regs are pushed, since this also
640 for (regno = 16; regno < 24; regno++)
641 if (regs_ever_live[regno] && ! call_used_regs[regno])
644 /* If a function is naked, don't use the "return" insn. */
645 if (arm_naked_function_p (current_function_decl))
651 /* Return TRUE if int I is a valid immediate ARM constant. */
657 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
659 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
660 be all zero, or all one. */
661 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
662 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
663 != ((~(unsigned HOST_WIDE_INT) 0)
664 & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
667 /* Fast return for 0 and powers of 2 */
668 if ((i & (i - 1)) == 0)
673 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
676 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
677 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
678 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
683 /* Return true if I is a valid constant for the operation CODE. */
685 const_ok_for_op (i, code)
689 if (const_ok_for_arm (i))
695 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
697 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
703 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
710 /* Emit a sequence of insns to handle a large constant.
711 CODE is the code of the operation required, it can be any of SET, PLUS,
712 IOR, AND, XOR, MINUS;
713 MODE is the mode in which the operation is being performed;
714 VAL is the integer to operate on;
715 SOURCE is the other operand (a register, or a null-pointer for SET);
716 SUBTARGETS means it is safe to create scratch registers if that will
717 either produce a simpler sequence, or we will want to cse the values.
718 Return value is the number of insns emitted. */
721 arm_split_constant (code, mode, val, target, source, subtargets)
723 enum machine_mode mode;
729 if (subtargets || code == SET
730 || (GET_CODE (target) == REG && GET_CODE (source) == REG
731 && REGNO (target) != REGNO (source)))
733 /* After arm_reorg has been called, we can't fix up expensive
734 constants by pushing them into memory so we must synthesise
735 them in-line, regardless of the cost. This is only likely to
736 be more costly on chips that have load delay slots and we are
737 compiling without running the scheduler (so no splitting
738 occurred before the final instruction emission).
740 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
742 if (! after_arm_reorg
743 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
744 > arm_constant_limit + (code != SET)))
748 /* Currently SET is the only monadic value for CODE, all
749 the rest are diadic. */
750 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
755 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
757 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
758 /* For MINUS, the value is subtracted from, since we never
759 have subtraction of a constant. */
761 emit_insn (gen_rtx_SET (VOIDmode, target,
762 gen_rtx (code, mode, temp, source)));
764 emit_insn (gen_rtx_SET (VOIDmode, target,
765 gen_rtx (code, mode, source, temp)));
771 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
774 /* As above, but extra parameter GENERATE which, if clear, suppresses
777 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
779 enum machine_mode mode;
788 int can_negate_initial = 0;
791 int num_bits_set = 0;
792 int set_sign_bit_copies = 0;
793 int clear_sign_bit_copies = 0;
794 int clear_zero_bit_copies = 0;
795 int set_zero_bit_copies = 0;
797 unsigned HOST_WIDE_INT temp1, temp2;
798 unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
800 /* find out which operations are safe for a given CODE. Also do a quick
801 check for degenerate cases; these can occur when DImode operations
813 can_negate_initial = 1;
817 if (remainder == 0xffffffffUL)
820 emit_insn (gen_rtx_SET (VOIDmode, target,
821 GEN_INT (ARM_SIGN_EXTEND (val))));
826 if (reload_completed && rtx_equal_p (target, source))
829 emit_insn (gen_rtx_SET (VOIDmode, target, source));
838 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
841 if (remainder == 0xffffffffUL)
843 if (reload_completed && rtx_equal_p (target, source))
846 emit_insn (gen_rtx_SET (VOIDmode, target, source));
855 if (reload_completed && rtx_equal_p (target, source))
858 emit_insn (gen_rtx_SET (VOIDmode, target, source));
861 if (remainder == 0xffffffffUL)
864 emit_insn (gen_rtx_SET (VOIDmode, target,
865 gen_rtx_NOT (mode, source)));
869 /* We don't know how to handle this yet below. */
873 /* We treat MINUS as (val - source), since (source - val) is always
874 passed as (source + (-val)). */
878 emit_insn (gen_rtx_SET (VOIDmode, target,
879 gen_rtx_NEG (mode, source)));
882 if (const_ok_for_arm (val))
885 emit_insn (gen_rtx_SET (VOIDmode, target,
886 gen_rtx_MINUS (mode, GEN_INT (val),
898 /* If we can do it in one insn get out quickly */
899 if (const_ok_for_arm (val)
900 || (can_negate_initial && const_ok_for_arm (-val))
901 || (can_invert && const_ok_for_arm (~val)))
904 emit_insn (gen_rtx_SET (VOIDmode, target,
905 (source ? gen_rtx (code, mode, source,
912 /* Calculate a few attributes that may be useful for specific
915 for (i = 31; i >= 0; i--)
917 if ((remainder & (1 << i)) == 0)
918 clear_sign_bit_copies++;
923 for (i = 31; i >= 0; i--)
925 if ((remainder & (1 << i)) != 0)
926 set_sign_bit_copies++;
931 for (i = 0; i <= 31; i++)
933 if ((remainder & (1 << i)) == 0)
934 clear_zero_bit_copies++;
939 for (i = 0; i <= 31; i++)
941 if ((remainder & (1 << i)) != 0)
942 set_zero_bit_copies++;
950 /* See if we can do this by sign_extending a constant that is known
951 to be negative. This is a good, way of doing it, since the shift
952 may well merge into a subsequent insn. */
953 if (set_sign_bit_copies > 1)
956 (temp1 = ARM_SIGN_EXTEND (remainder
957 << (set_sign_bit_copies - 1))))
961 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
962 emit_insn (gen_rtx_SET (VOIDmode, new_src,
964 emit_insn (gen_ashrsi3 (target, new_src,
965 GEN_INT (set_sign_bit_copies - 1)));
969 /* For an inverted constant, we will need to set the low bits,
970 these will be shifted out of harm's way. */
971 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
972 if (const_ok_for_arm (~temp1))
976 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
977 emit_insn (gen_rtx_SET (VOIDmode, new_src,
979 emit_insn (gen_ashrsi3 (target, new_src,
980 GEN_INT (set_sign_bit_copies - 1)));
986 /* See if we can generate this by setting the bottom (or the top)
987 16 bits, and then shifting these into the other half of the
988 word. We only look for the simplest cases, to do more would cost
989 too much. Be careful, however, not to generate this when the
990 alternative would take fewer insns. */
991 if (val & 0xffff0000UL)
993 temp1 = remainder & 0xffff0000UL;
994 temp2 = remainder & 0x0000ffff;
996 /* Overlaps outside this range are best done using other methods. */
997 for (i = 9; i < 24; i++)
999 if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
1000 && ! const_ok_for_arm (temp2))
1002 rtx new_src = (subtargets
1003 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1005 insns = arm_gen_constant (code, mode, temp2, new_src,
1006 source, subtargets, generate);
1009 emit_insn (gen_rtx_SET
1012 gen_rtx_ASHIFT (mode, source,
1019 /* Don't duplicate cases already considered. */
1020 for (i = 17; i < 24; i++)
1022 if (((temp1 | (temp1 >> i)) == remainder)
1023 && ! const_ok_for_arm (temp1))
1025 rtx new_src = (subtargets
1026 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1028 insns = arm_gen_constant (code, mode, temp1, new_src,
1029 source, subtargets, generate);
1033 (gen_rtx_SET (VOIDmode, target,
1036 gen_rtx_LSHIFTRT (mode, source,
1047 /* If we have IOR or XOR, and the constant can be loaded in a
1048 single instruction, and we can find a temporary to put it in,
1049 then this can be done in two instructions instead of 3-4. */
1051 /* TARGET can't be NULL if SUBTARGETS is 0 */
1052 || (reload_completed && ! reg_mentioned_p (target, source)))
1054 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1058 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1060 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1061 emit_insn (gen_rtx_SET (VOIDmode, target,
1062 gen_rtx (code, mode, source, sub)));
1071 if (set_sign_bit_copies > 8
1072 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1076 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1077 rtx shift = GEN_INT (set_sign_bit_copies);
1079 emit_insn (gen_rtx_SET (VOIDmode, sub,
1081 gen_rtx_ASHIFT (mode,
1084 emit_insn (gen_rtx_SET (VOIDmode, target,
1086 gen_rtx_LSHIFTRT (mode, sub,
1092 if (set_zero_bit_copies > 8
1093 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1097 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1098 rtx shift = GEN_INT (set_zero_bit_copies);
1100 emit_insn (gen_rtx_SET (VOIDmode, sub,
1102 gen_rtx_LSHIFTRT (mode,
1105 emit_insn (gen_rtx_SET (VOIDmode, target,
1107 gen_rtx_ASHIFT (mode, sub,
1113 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1117 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1118 emit_insn (gen_rtx_SET (VOIDmode, sub,
1119 gen_rtx_NOT (mode, source)));
1122 sub = gen_reg_rtx (mode);
1123 emit_insn (gen_rtx_SET (VOIDmode, sub,
1124 gen_rtx_AND (mode, source,
1126 emit_insn (gen_rtx_SET (VOIDmode, target,
1127 gen_rtx_NOT (mode, sub)));
1134 /* See if two shifts will do 2 or more insn's worth of work. */
1135 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1137 HOST_WIDE_INT shift_mask = ((0xffffffffUL
1138 << (32 - clear_sign_bit_copies))
1141 if ((remainder | shift_mask) != 0xffffffffUL)
1145 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1146 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1147 new_src, source, subtargets, 1);
1152 rtx targ = subtargets ? NULL_RTX : target;
1153 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1154 targ, source, subtargets, 0);
1160 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1161 rtx shift = GEN_INT (clear_sign_bit_copies);
1163 emit_insn (gen_ashlsi3 (new_src, source, shift));
1164 emit_insn (gen_lshrsi3 (target, new_src, shift));
1170 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1172 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1174 if ((remainder | shift_mask) != 0xffffffffUL)
1178 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1180 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1181 new_src, source, subtargets, 1);
1186 rtx targ = subtargets ? NULL_RTX : target;
1188 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1189 targ, source, subtargets, 0);
1195 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1196 rtx shift = GEN_INT (clear_zero_bit_copies);
1198 emit_insn (gen_lshrsi3 (new_src, source, shift));
1199 emit_insn (gen_ashlsi3 (target, new_src, shift));
1211 for (i = 0; i < 32; i++)
1212 if (remainder & (1 << i))
1215 if (code == AND || (can_invert && num_bits_set > 16))
1216 remainder = (~remainder) & 0xffffffffUL;
1217 else if (code == PLUS && num_bits_set > 16)
1218 remainder = (-remainder) & 0xffffffffUL;
1225 /* Now try and find a way of doing the job in either two or three
1227 We start by looking for the largest block of zeros that are aligned on
1228 a 2-bit boundary, we then fill up the temps, wrapping around to the
1229 top of the word when we drop off the bottom.
1230 In the worst case this code should produce no more than four insns. */
1233 int best_consecutive_zeros = 0;
1235 for (i = 0; i < 32; i += 2)
1237 int consecutive_zeros = 0;
1239 if (! (remainder & (3 << i)))
1241 while ((i < 32) && ! (remainder & (3 << i)))
1243 consecutive_zeros += 2;
1246 if (consecutive_zeros > best_consecutive_zeros)
1248 best_consecutive_zeros = consecutive_zeros;
1249 best_start = i - consecutive_zeros;
1255 /* Now start emitting the insns, starting with the one with the highest
1256 bit set: we do this so that the smallest number will be emitted last;
1257 this is more likely to be combinable with addressing insns. */
1265 if (remainder & (3 << (i - 2)))
1270 temp1 = remainder & ((0x0ff << end)
1271 | ((i < end) ? (0xff >> (32 - end)) : 0));
1272 remainder &= ~temp1;
1279 emit_insn (gen_rtx_SET (VOIDmode,
1280 new_src = (subtargets
1281 ? gen_reg_rtx (mode)
1284 ? ~temp1 : temp1)));
1285 else if (code == MINUS)
1286 emit_insn (gen_rtx_SET (VOIDmode,
1287 new_src = (subtargets
1288 ? gen_reg_rtx (mode)
1290 gen_rtx (code, mode, GEN_INT (temp1),
1293 emit_insn (gen_rtx_SET (VOIDmode,
1294 new_src = (remainder
1296 ? gen_reg_rtx (mode)
1299 gen_rtx (code, mode, source,
1300 GEN_INT (can_invert ? ~temp1
1312 else if (code == MINUS)
1319 } while (remainder);
1324 /* Canonicalize a comparison so that we are more likely to recognize it.
1325 This can be done for a few constant compares, where we can make the
1326 immediate value easier to load. */
1328 arm_canonicalize_comparison (code, op1)
1332 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1342 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1344 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1346 *op1 = GEN_INT (i+1);
1347 return code == GT ? GE : LT;
1353 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1354 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1356 *op1 = GEN_INT (i-1);
1357 return code == GE ? GT : LE;
1363 if (i != ~((unsigned HOST_WIDE_INT) 0)
1364 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1366 *op1 = GEN_INT (i + 1);
1367 return code == GTU ? GEU : LTU;
1374 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1376 *op1 = GEN_INT (i - 1);
1377 return code == GEU ? GTU : LEU;
1388 /* Decide whether a type should be returned in memory (true)
1389 or in a register (false). This is called by the macro
1390 RETURN_IN_MEMORY. */
1392 arm_return_in_memory (type)
1395 if (! AGGREGATE_TYPE_P (type))
1397 /* All simple types are returned in registers. */
1400 else if (int_size_in_bytes (type) > 4)
1402 /* All structures/unions bigger than one word are returned in memory. */
1405 else if (TREE_CODE (type) == RECORD_TYPE)
1409 /* For a struct the APCS says that we only return in a register
1410 if the type is 'integer like' and every addressable element
1411 has an offset of zero. For practical purposes this means
1412 that the structure can have at most one non bit-field element
1413 and that this element must be the first one in the structure. */
1415 /* Find the first field, ignoring non FIELD_DECL things which will
1416 have been created by C++. */
1417 for (field = TYPE_FIELDS (type);
1418 field && TREE_CODE (field) != FIELD_DECL;
1419 field = TREE_CHAIN (field))
1423 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1425 /* Check that the first field is valid for returning in a register... */
1427 /* ... Floats are not allowed */
1428 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1431 /* ... Aggregates that are not themselves valid for returning in
1432 a register are not allowed. */
1433 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1436 /* Now check the remaining fields, if any. Only bitfields are allowed,
1437 since they are not addressable. */
1438 for (field = TREE_CHAIN (field);
1440 field = TREE_CHAIN (field))
1442 if (TREE_CODE (field) != FIELD_DECL)
1445 if (! DECL_BIT_FIELD_TYPE (field))
1451 else if (TREE_CODE (type) == UNION_TYPE)
1455 /* Unions can be returned in registers if every element is
1456 integral, or can be returned in an integer register. */
1457 for (field = TYPE_FIELDS (type);
1459 field = TREE_CHAIN (field))
1461 if (TREE_CODE (field) != FIELD_DECL)
1464 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1467 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1474 /* XXX Not sure what should be done for other aggregates, so put them in
1479 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1480 for a call to a function whose data type is FNTYPE.
1481 For a library call, FNTYPE is NULL. */
1483 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1484 CUMULATIVE_ARGS * pcum;
1486 rtx libname ATTRIBUTE_UNUSED;
1487 int indirect ATTRIBUTE_UNUSED;
1489 /* On the ARM, the offset starts at 0. */
1490 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype)))
1493 pcum->call_cookie = CALL_NORMAL;
1495 if (TARGET_LONG_CALLS)
1496 pcum->call_cookie = CALL_LONG;
1498 /* Check for long call/short call attributes. The attributes
1499 override any command line option. */
1502 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1503 pcum->call_cookie = CALL_SHORT;
1504 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1505 pcum->call_cookie = CALL_LONG;
1509 /* Determine where to put an argument to a function.
1510 Value is zero to push the argument on the stack,
1511 or a hard register in which to store the argument.
1513 MODE is the argument's machine mode.
1514 TYPE is the data type of the argument (as a tree).
1515 This is null for libcalls where that information may
1517 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1518 the preceding args and about the function being called.
1519 NAMED is nonzero if this argument is a named parameter
1520 (otherwise it is an extra parameter matching an ellipsis). */
1522 arm_function_arg (pcum, mode, type, named)
1523 CUMULATIVE_ARGS * pcum;
1524 enum machine_mode mode;
1525 tree type ATTRIBUTE_UNUSED;
1528 if (mode == VOIDmode)
1529 /* Compute operand 2 of the call insn. */
1530 return GEN_INT (pcum->call_cookie);
1532 if (! named || pcum->nregs >= NUM_ARG_REGS)
1535 return gen_rtx_REG (mode, pcum->nregs);
1539 /* Return 1 if the operand is a SYMBOL_REF for a function
1540 known to be defined in the current compilation unit. */
1542 current_file_function_operand (sym_ref)
1545 /* XXX FIXME - we need some way to determine if SYMREF has already been
1546 compiled. We wanted to used SYMBOL_REF_FLAG but this is already in use
1547 by the constant pool generation code. */
1549 GET_CODE (sym_ref) == SYMBOL_REF
1550 && sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
1551 && ! DECL_WEAK (current_function_decl);
1554 /* Return non-zero if a 32 bit "long call" should be generated for this
1557 We generate a long call if the function is not declared
1558 __attribute__ ((short_call),
1562 (1) the function is declared __attribute__ ((long_call))
1566 (2) -mlong-calls is enabled and we don't know whether the target
1567 function is declared in this file.
1569 This function will typically be called by C fragments in the machine
1570 description file. CALL_REF is the matched rtl operand. CALL_COOKIE
1571 describes the value of the long_call and short_call attributes for
1572 the called functiion. CALL_SYMBOL is used to distinguish between
1573 two different callers of the function. It is set to 1 in the "call_symbol"
1574 and "call_symbol_value" patterns in arm.md and to 0 in the "call" and
1575 "call_value" patterns. This is because of the difference of SYM_REFs passed
1576 from "call_symbol" and "call" patterns. */
1578 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
1585 if (GET_CODE (sym_ref) != MEM)
1588 sym_ref = XEXP (sym_ref, 0);
1591 if (GET_CODE (sym_ref) != SYMBOL_REF)
1594 if (call_cookie & CALL_SHORT)
1597 if (TARGET_LONG_CALLS && flag_function_sections)
1600 if (current_file_function_operand (sym_ref, VOIDmode))
1603 return (call_cookie & CALL_LONG) || TARGET_LONG_CALLS;
1606 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1607 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1608 assigned to TYPE. */
1610 arm_valid_type_attribute_p (type, attributes, identifier, args)
1612 tree attributes ATTRIBUTE_UNUSED;
1616 if ( TREE_CODE (type) != FUNCTION_TYPE
1617 && TREE_CODE (type) != METHOD_TYPE
1618 && TREE_CODE (type) != FIELD_DECL
1619 && TREE_CODE (type) != TYPE_DECL)
1622 /* Function calls made to this symbol must be done indirectly, because
1623 it may lie outside of the 26 bit addressing range of a normal function
1625 if (is_attribute_p ("long_call", identifier))
1626 return (args == NULL_TREE);
1628 /* Whereas these functions are always known to reside within the 26 bit
1629 addressing range. */
1630 if (is_attribute_p ("short_call", identifier))
1631 return (args == NULL_TREE);
1636 /* Return 0 if the attributes for two types are incompatible, 1 if they
1637 are compatible, and 2 if they are nearly compatible (which causes a
1638 warning to be generated). */
1640 arm_comp_type_attributes (type1, type2)
1646 /* Check for mismatch of non-default calling convention. */
1647 if (TREE_CODE (type1) != FUNCTION_TYPE)
1650 /* Check for mismatched call attributes. */
1651 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1));
1652 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2));
1653 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1));
1654 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2));
1656 /* Only bother to check if an attribute is defined. */
1657 if (l1 | l2 | s1 | s2)
1659 /* If one type has an attribute, the other must have the same attribute. */
1660 if ((!l1 != !l2) || (!s1 != !s2))
1663 /* Disallow mixed attributes. */
1664 if ((l1 & s2) || (l2 & s1))
1673 legitimate_pic_operand_p (x)
1676 if (CONSTANT_P (x) && flag_pic
1677 && (GET_CODE (x) == SYMBOL_REF
1678 || (GET_CODE (x) == CONST
1679 && GET_CODE (XEXP (x, 0)) == PLUS
1680 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1687 legitimize_pic_address (orig, mode, reg)
1689 enum machine_mode mode;
1692 if (GET_CODE (orig) == SYMBOL_REF)
1694 rtx pic_ref, address;
1700 if (reload_in_progress || reload_completed)
1703 reg = gen_reg_rtx (Pmode);
1708 #ifdef AOF_ASSEMBLER
1709 /* The AOF assembler can generate relocations for these directly, and
1710 understands that the PIC register has to be added into the offset.
1712 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1715 address = gen_reg_rtx (Pmode);
1719 emit_insn (gen_pic_load_addr (address, orig));
1721 pic_ref = gen_rtx_MEM (Pmode,
1722 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1724 RTX_UNCHANGING_P (pic_ref) = 1;
1725 insn = emit_move_insn (reg, pic_ref);
1727 current_function_uses_pic_offset_table = 1;
1728 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1730 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1734 else if (GET_CODE (orig) == CONST)
1738 if (GET_CODE (XEXP (orig, 0)) == PLUS
1739 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1744 if (reload_in_progress || reload_completed)
1747 reg = gen_reg_rtx (Pmode);
1750 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1752 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1753 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1754 base == reg ? 0 : reg);
1759 if (GET_CODE (offset) == CONST_INT)
1761 /* The base register doesn't really matter, we only want to
1762 test the index for the appropriate mode. */
1763 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1765 if (! reload_in_progress && ! reload_completed)
1766 offset = force_reg (Pmode, offset);
1771 if (GET_CODE (offset) == CONST_INT)
1772 return plus_constant_for_output (base, INTVAL (offset));
1775 if (GET_MODE_SIZE (mode) > 4
1776 && (GET_MODE_CLASS (mode) == MODE_INT
1777 || TARGET_SOFT_FLOAT))
1779 emit_insn (gen_addsi3 (reg, base, offset));
1783 return gen_rtx_PLUS (Pmode, base, offset);
1785 else if (GET_CODE (orig) == LABEL_REF)
1787 current_function_uses_pic_offset_table = 1;
1791 rtx pic_ref, address = gen_reg_rtx (Pmode);
1793 emit_insn (gen_pic_load_addr (address, orig));
1794 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
1796 emit_move_insn (address, pic_ref);
1818 #ifndef AOF_ASSEMBLER
1819 rtx l1, pic_tmp, pic_tmp2, seq;
1820 rtx global_offset_table;
1822 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
1829 l1 = gen_label_rtx ();
1831 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1832 /* On the ARM the PC register contains 'dot + 8' at the time of the
1834 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1836 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1837 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1839 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1841 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1843 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1844 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1846 seq = gen_sequence ();
1848 emit_insn_after (seq, get_insns ());
1850 /* Need to emit this whether or not we obey regdecls,
1851 since setjmp/longjmp can cause life info to screw up. */
1852 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1853 #endif /* AOF_ASSEMBLER */
1856 #define REG_OR_SUBREG_REG(X) \
1857 (GET_CODE (X) == REG \
1858 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1860 #define REG_OR_SUBREG_RTX(X) \
1861 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1863 #define ARM_FRAME_RTX(X) \
1864 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1865 || (X) == arg_pointer_rtx)
1868 arm_rtx_costs (x, code)
1872 enum machine_mode mode = GET_MODE (x);
1873 enum rtx_code subcode;
1879 /* Memory costs quite a lot for the first word, but subsequent words
1880 load at the equivalent of a single insn each. */
1881 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1882 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1889 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1896 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1898 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1899 + ((GET_CODE (XEXP (x, 0)) == REG
1900 || (GET_CODE (XEXP (x, 0)) == SUBREG
1901 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1903 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1904 || (GET_CODE (XEXP (x, 0)) == SUBREG
1905 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1907 + ((GET_CODE (XEXP (x, 1)) == REG
1908 || (GET_CODE (XEXP (x, 1)) == SUBREG
1909 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1910 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1915 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1916 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1917 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1918 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1921 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1922 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1923 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1924 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1926 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1927 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1928 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1931 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1932 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1933 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1934 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1935 || subcode == ASHIFTRT || subcode == LSHIFTRT
1936 || subcode == ROTATE || subcode == ROTATERT
1938 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1939 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1940 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1941 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1942 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1943 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1944 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1949 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1950 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1951 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1952 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1953 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1957 case AND: case XOR: case IOR:
1960 /* Normally the frame registers will be spilt into reg+const during
1961 reload, so it is a bad idea to combine them with other instructions,
1962 since then they might not be moved outside of loops. As a compromise
1963 we allow integration with ops that have a constant as their second
1965 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1966 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1967 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1968 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1969 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1973 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1974 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1975 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1976 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1979 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1980 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1981 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1982 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1983 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1986 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1987 return (1 + extra_cost
1988 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1989 || subcode == LSHIFTRT || subcode == ASHIFTRT
1990 || subcode == ROTATE || subcode == ROTATERT
1992 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1993 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1994 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1995 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1996 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1997 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2003 /* There is no point basing this on the tuning, since it is always the
2004 fast variant if it exists at all */
2005 if (arm_fast_multiply && mode == DImode
2006 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2007 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2008 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2011 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2015 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2017 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2018 & (unsigned HOST_WIDE_INT) 0xffffffffUL);
2019 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2021 /* Tune as appropriate */
2022 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2024 for (j = 0; i && j < 32; j += booth_unit_size)
2026 i >>= booth_unit_size;
2033 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2034 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2035 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2038 if (arm_fast_multiply && mode == SImode
2039 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2040 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2041 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2042 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2043 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2044 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2049 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2050 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2054 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2056 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2059 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2067 return 4 + (mode == DImode ? 4 : 0);
2070 if (GET_MODE (XEXP (x, 0)) == QImode)
2071 return (4 + (mode == DImode ? 4 : 0)
2072 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2075 switch (GET_MODE (XEXP (x, 0)))
2078 return (1 + (mode == DImode ? 4 : 0)
2079 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2082 return (4 + (mode == DImode ? 4 : 0)
2083 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2086 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2099 arm_adjust_cost (insn, link, dep, cost)
2107 /* XXX This is not strictly true for the FPA. */
2108 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
2109 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
2112 if ((i_pat = single_set (insn)) != NULL
2113 && GET_CODE (SET_SRC (i_pat)) == MEM
2114 && (d_pat = single_set (dep)) != NULL
2115 && GET_CODE (SET_DEST (d_pat)) == MEM)
2117 /* This is a load after a store, there is no conflict if the load reads
2118 from a cached area. Assume that loads from the stack, and from the
2119 constant pool are cached, and that others will miss. This is a
2122 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2123 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2124 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2125 || reg_mentioned_p (hard_frame_pointer_rtx,
2126 XEXP (SET_SRC (i_pat), 0)))
2133 /* This code has been fixed for cross compilation. */
2135 static int fpa_consts_inited = 0;
2137 char * strings_fpa[8] =
2140 "4", "5", "0.5", "10"
2143 static REAL_VALUE_TYPE values_fpa[8];
2151 for (i = 0; i < 8; i++)
2153 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2157 fpa_consts_inited = 1;
2160 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2163 const_double_rtx_ok_for_fpu (x)
2169 if (!fpa_consts_inited)
2172 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2173 if (REAL_VALUE_MINUS_ZERO (r))
2176 for (i = 0; i < 8; i++)
2177 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2183 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2186 neg_const_double_rtx_ok_for_fpu (x)
2192 if (!fpa_consts_inited)
2195 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2196 r = REAL_VALUE_NEGATE (r);
2197 if (REAL_VALUE_MINUS_ZERO (r))
2200 for (i = 0; i < 8; i++)
2201 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2207 /* Predicates for `match_operand' and `match_operator'. */
2209 /* s_register_operand is the same as register_operand, but it doesn't accept
2212 This function exists because at the time it was put in it led to better
2213 code. SUBREG(MEM) always needs a reload in the places where
2214 s_register_operand is used, and this seemed to lead to excessive
2218 s_register_operand (op, mode)
2220 enum machine_mode mode;
2222 if (GET_MODE (op) != mode && mode != VOIDmode)
2225 if (GET_CODE (op) == SUBREG)
2226 op = SUBREG_REG (op);
2228 /* We don't consider registers whose class is NO_REGS
2229 to be a register operand. */
2230 return (GET_CODE (op) == REG
2231 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2232 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2235 /* Only accept reg, subreg(reg), const_int. */
2238 reg_or_int_operand (op, mode)
2240 enum machine_mode mode;
2242 if (GET_CODE (op) == CONST_INT)
2245 if (GET_MODE (op) != mode && mode != VOIDmode)
2248 if (GET_CODE (op) == SUBREG)
2249 op = SUBREG_REG (op);
2251 /* We don't consider registers whose class is NO_REGS
2252 to be a register operand. */
2253 return (GET_CODE (op) == REG
2254 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2255 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2258 /* Return 1 if OP is an item in memory, given that we are in reload. */
2261 reload_memory_operand (op, mode)
2263 enum machine_mode mode ATTRIBUTE_UNUSED;
2265 int regno = true_regnum (op);
2267 return (! CONSTANT_P (op)
2269 || (GET_CODE (op) == REG
2270 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2273 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2274 memory access (architecture V4) */
2276 bad_signed_byte_operand (op, mode)
2278 enum machine_mode mode;
2280 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2285 /* A sum of anything more complex than reg + reg or reg + const is bad */
2286 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2287 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2288 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2289 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2292 /* Big constants are also bad */
2293 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2294 && (INTVAL (XEXP (op, 1)) > 0xff
2295 || -INTVAL (XEXP (op, 1)) > 0xff))
2298 /* Everything else is good, or can will automatically be made so. */
2302 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2305 arm_rhs_operand (op, mode)
2307 enum machine_mode mode;
2309 return (s_register_operand (op, mode)
2310 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2313 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2317 arm_rhsm_operand (op, mode)
2319 enum machine_mode mode;
2321 return (s_register_operand (op, mode)
2322 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2323 || memory_operand (op, mode));
2326 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2327 constant that is valid when negated. */
2330 arm_add_operand (op, mode)
2332 enum machine_mode mode;
2334 return (s_register_operand (op, mode)
2335 || (GET_CODE (op) == CONST_INT
2336 && (const_ok_for_arm (INTVAL (op))
2337 || const_ok_for_arm (-INTVAL (op)))));
2341 arm_not_operand (op, mode)
2343 enum machine_mode mode;
2345 return (s_register_operand (op, mode)
2346 || (GET_CODE (op) == CONST_INT
2347 && (const_ok_for_arm (INTVAL (op))
2348 || const_ok_for_arm (~INTVAL (op)))));
2351 /* Return TRUE if the operand is a memory reference which contains an
2352 offsettable address. */
2354 offsettable_memory_operand (op, mode)
2356 enum machine_mode mode;
2358 if (mode == VOIDmode)
2359 mode = GET_MODE (op);
2361 return (mode == GET_MODE (op)
2362 && GET_CODE (op) == MEM
2363 && offsettable_address_p (reload_completed | reload_in_progress,
2364 mode, XEXP (op, 0)));
2367 /* Return TRUE if the operand is a memory reference which is, or can be
2368 made word aligned by adjusting the offset. */
2370 alignable_memory_operand (op, mode)
2372 enum machine_mode mode;
2376 if (mode == VOIDmode)
2377 mode = GET_MODE (op);
2379 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2384 return ((GET_CODE (reg = op) == REG
2385 || (GET_CODE (op) == SUBREG
2386 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2387 || (GET_CODE (op) == PLUS
2388 && GET_CODE (XEXP (op, 1)) == CONST_INT
2389 && (GET_CODE (reg = XEXP (op, 0)) == REG
2390 || (GET_CODE (XEXP (op, 0)) == SUBREG
2391 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2392 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2395 /* Similar to s_register_operand, but does not allow hard integer
2398 f_register_operand (op, mode)
2400 enum machine_mode mode;
2402 if (GET_MODE (op) != mode && mode != VOIDmode)
2405 if (GET_CODE (op) == SUBREG)
2406 op = SUBREG_REG (op);
2408 /* We don't consider registers whose class is NO_REGS
2409 to be a register operand. */
2410 return (GET_CODE (op) == REG
2411 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2412 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2415 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2418 fpu_rhs_operand (op, mode)
2420 enum machine_mode mode;
2422 if (s_register_operand (op, mode))
2425 if (GET_MODE (op) != mode && mode != VOIDmode)
2428 if (GET_CODE (op) == CONST_DOUBLE)
2429 return const_double_rtx_ok_for_fpu (op);
2435 fpu_add_operand (op, mode)
2437 enum machine_mode mode;
2439 if (s_register_operand (op, mode))
2442 if (GET_MODE (op) != mode && mode != VOIDmode)
2445 if (GET_CODE (op) == CONST_DOUBLE)
2446 return (const_double_rtx_ok_for_fpu (op)
2447 || neg_const_double_rtx_ok_for_fpu (op));
2452 /* Return nonzero if OP is a constant power of two. */
2455 power_of_two_operand (op, mode)
2457 enum machine_mode mode ATTRIBUTE_UNUSED;
2459 if (GET_CODE (op) == CONST_INT)
2461 HOST_WIDE_INT value = INTVAL(op);
2462 return value != 0 && (value & (value - 1)) == 0;
2467 /* Return TRUE for a valid operand of a DImode operation.
2468 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2469 Note that this disallows MEM(REG+REG), but allows
2470 MEM(PRE/POST_INC/DEC(REG)). */
2473 di_operand (op, mode)
2475 enum machine_mode mode;
2477 if (s_register_operand (op, mode))
2480 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2483 if (GET_CODE (op) == SUBREG)
2484 op = SUBREG_REG (op);
2486 switch (GET_CODE (op))
2493 return memory_address_p (DImode, XEXP (op, 0));
2500 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2501 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2502 Note that this disallows MEM(REG+REG), but allows
2503 MEM(PRE/POST_INC/DEC(REG)). */
2506 soft_df_operand (op, mode)
2508 enum machine_mode mode;
2510 if (s_register_operand (op, mode))
2513 if (mode != VOIDmode && GET_MODE (op) != mode)
2516 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
2519 if (GET_CODE (op) == SUBREG)
2520 op = SUBREG_REG (op);
2522 switch (GET_CODE (op))
2528 return memory_address_p (DFmode, XEXP (op, 0));
2535 /* Return TRUE for valid index operands. */
2538 index_operand (op, mode)
2540 enum machine_mode mode;
2542 return (s_register_operand(op, mode)
2543 || (immediate_operand (op, mode)
2544 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2547 /* Return TRUE for valid shifts by a constant. This also accepts any
2548 power of two on the (somewhat overly relaxed) assumption that the
2549 shift operator in this case was a mult. */
2552 const_shift_operand (op, mode)
2554 enum machine_mode mode;
2556 return (power_of_two_operand (op, mode)
2557 || (immediate_operand (op, mode)
2558 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2561 /* Return TRUE for arithmetic operators which can be combined with a multiply
2565 shiftable_operator (x, mode)
2567 enum machine_mode mode;
2569 if (GET_MODE (x) != mode)
2573 enum rtx_code code = GET_CODE (x);
2575 return (code == PLUS || code == MINUS
2576 || code == IOR || code == XOR || code == AND);
2580 /* Return TRUE for binary logical operators. */
2583 logical_binary_operator (x, mode)
2585 enum machine_mode mode;
2587 if (GET_MODE (x) != mode)
2591 enum rtx_code code = GET_CODE (x);
2593 return (code == IOR || code == XOR || code == AND);
2597 /* Return TRUE for shift operators. */
2600 shift_operator (x, mode)
2602 enum machine_mode mode;
2604 if (GET_MODE (x) != mode)
2608 enum rtx_code code = GET_CODE (x);
2611 return power_of_two_operand (XEXP (x, 1), mode);
2613 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2614 || code == ROTATERT);
2618 int equality_operator (x, mode)
2620 enum machine_mode mode ATTRIBUTE_UNUSED;
2622 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2625 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2628 minmax_operator (x, mode)
2630 enum machine_mode mode;
2632 enum rtx_code code = GET_CODE (x);
2634 if (GET_MODE (x) != mode)
2637 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2640 /* return TRUE if x is EQ or NE */
2642 /* Return TRUE if this is the condition code register, if we aren't given
2643 a mode, accept any class CCmode register */
2646 cc_register (x, mode)
2648 enum machine_mode mode;
2650 if (mode == VOIDmode)
2652 mode = GET_MODE (x);
2653 if (GET_MODE_CLASS (mode) != MODE_CC)
2657 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2663 /* Return TRUE if this is the condition code register, if we aren't given
2664 a mode, accept any class CCmode register which indicates a dominance
2668 dominant_cc_register (x, mode)
2670 enum machine_mode mode;
2672 if (mode == VOIDmode)
2674 mode = GET_MODE (x);
2675 if (GET_MODE_CLASS (mode) != MODE_CC)
2679 if (mode != CC_DNEmode && mode != CC_DEQmode
2680 && mode != CC_DLEmode && mode != CC_DLTmode
2681 && mode != CC_DGEmode && mode != CC_DGTmode
2682 && mode != CC_DLEUmode && mode != CC_DLTUmode
2683 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2686 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2692 /* Return TRUE if X references a SYMBOL_REF. */
2694 symbol_mentioned_p (x)
2697 register const char * fmt;
2700 if (GET_CODE (x) == SYMBOL_REF)
2703 fmt = GET_RTX_FORMAT (GET_CODE (x));
2704 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2710 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2711 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2714 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2721 /* Return TRUE if X references a LABEL_REF. */
2723 label_mentioned_p (x)
2726 register const char * fmt;
2729 if (GET_CODE (x) == LABEL_REF)
2732 fmt = GET_RTX_FORMAT (GET_CODE (x));
2733 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2739 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2740 if (label_mentioned_p (XVECEXP (x, i, j)))
2743 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2754 enum rtx_code code = GET_CODE (x);
2758 else if (code == SMIN)
2760 else if (code == UMIN)
2762 else if (code == UMAX)
2768 /* Return 1 if memory locations are adjacent */
2771 adjacent_mem_locations (a, b)
2774 int val0 = 0, val1 = 0;
2777 if ((GET_CODE (XEXP (a, 0)) == REG
2778 || (GET_CODE (XEXP (a, 0)) == PLUS
2779 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2780 && (GET_CODE (XEXP (b, 0)) == REG
2781 || (GET_CODE (XEXP (b, 0)) == PLUS
2782 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2784 if (GET_CODE (XEXP (a, 0)) == PLUS)
2786 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2787 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2790 reg0 = REGNO (XEXP (a, 0));
2791 if (GET_CODE (XEXP (b, 0)) == PLUS)
2793 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2794 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2797 reg1 = REGNO (XEXP (b, 0));
2798 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2803 /* Return 1 if OP is a load multiple operation. It is known to be
2804 parallel and the first section will be tested. */
2807 load_multiple_operation (op, mode)
2809 enum machine_mode mode ATTRIBUTE_UNUSED;
2811 HOST_WIDE_INT count = XVECLEN (op, 0);
2814 HOST_WIDE_INT i = 1, base = 0;
2818 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2821 /* Check to see if this might be a write-back */
2822 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2827 /* Now check it more carefully */
2828 if (GET_CODE (SET_DEST (elt)) != REG
2829 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2830 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2831 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2832 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2833 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2834 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2835 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2836 != REGNO (SET_DEST (elt)))
2842 /* Perform a quick check so we don't blow up below. */
2844 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2845 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2846 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2849 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2850 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2852 for (; i < count; i++)
2854 elt = XVECEXP (op, 0, i);
2856 if (GET_CODE (elt) != SET
2857 || GET_CODE (SET_DEST (elt)) != REG
2858 || GET_MODE (SET_DEST (elt)) != SImode
2859 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2860 || GET_CODE (SET_SRC (elt)) != MEM
2861 || GET_MODE (SET_SRC (elt)) != SImode
2862 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2863 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2864 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2865 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2872 /* Return 1 if OP is a store multiple operation. It is known to be
2873 parallel and the first section will be tested. */
2876 store_multiple_operation (op, mode)
2878 enum machine_mode mode ATTRIBUTE_UNUSED;
2880 HOST_WIDE_INT count = XVECLEN (op, 0);
2883 HOST_WIDE_INT i = 1, base = 0;
2887 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2890 /* Check to see if this might be a write-back */
2891 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2896 /* Now check it more carefully */
2897 if (GET_CODE (SET_DEST (elt)) != REG
2898 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2899 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2900 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2901 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2902 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2903 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2904 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2905 != REGNO (SET_DEST (elt)))
2911 /* Perform a quick check so we don't blow up below. */
2913 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2914 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2915 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2918 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2919 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2921 for (; i < count; i++)
2923 elt = XVECEXP (op, 0, i);
2925 if (GET_CODE (elt) != SET
2926 || GET_CODE (SET_SRC (elt)) != REG
2927 || GET_MODE (SET_SRC (elt)) != SImode
2928 || REGNO (SET_SRC (elt)) != src_regno + i - base
2929 || GET_CODE (SET_DEST (elt)) != MEM
2930 || GET_MODE (SET_DEST (elt)) != SImode
2931 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2932 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2933 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2934 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2942 load_multiple_sequence (operands, nops, regs, base, load_offset)
2947 HOST_WIDE_INT * load_offset;
2949 int unsorted_regs[4];
2950 HOST_WIDE_INT unsorted_offsets[4];
2955 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2956 extended if required. */
2957 if (nops < 2 || nops > 4)
2960 /* Loop over the operands and check that the memory references are
2961 suitable (ie immediate offsets from the same base register). At
2962 the same time, extract the target register, and the memory
2964 for (i = 0; i < nops; i++)
2969 /* Convert a subreg of a mem into the mem itself. */
2970 if (GET_CODE (operands[nops + i]) == SUBREG)
2971 operands[nops + i] = alter_subreg(operands[nops + i]);
2973 if (GET_CODE (operands[nops + i]) != MEM)
2976 /* Don't reorder volatile memory references; it doesn't seem worth
2977 looking for the case where the order is ok anyway. */
2978 if (MEM_VOLATILE_P (operands[nops + i]))
2981 offset = const0_rtx;
2983 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2984 || (GET_CODE (reg) == SUBREG
2985 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2986 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2987 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2989 || (GET_CODE (reg) == SUBREG
2990 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2991 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2996 base_reg = REGNO(reg);
2997 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2998 ? REGNO (operands[i])
2999 : REGNO (SUBREG_REG (operands[i])));
3004 if (base_reg != REGNO (reg))
3005 /* Not addressed from the same base register. */
3008 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3009 ? REGNO (operands[i])
3010 : REGNO (SUBREG_REG (operands[i])));
3011 if (unsorted_regs[i] < unsorted_regs[order[0]])
3015 /* If it isn't an integer register, or if it overwrites the
3016 base register but isn't the last insn in the list, then
3017 we can't do this. */
3018 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3019 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3022 unsorted_offsets[i] = INTVAL (offset);
3025 /* Not a suitable memory address. */
3029 /* All the useful information has now been extracted from the
3030 operands into unsorted_regs and unsorted_offsets; additionally,
3031 order[0] has been set to the lowest numbered register in the
3032 list. Sort the registers into order, and check that the memory
3033 offsets are ascending and adjacent. */
3035 for (i = 1; i < nops; i++)
3039 order[i] = order[i - 1];
3040 for (j = 0; j < nops; j++)
3041 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3042 && (order[i] == order[i - 1]
3043 || unsorted_regs[j] < unsorted_regs[order[i]]))
3046 /* Have we found a suitable register? if not, one must be used more
3048 if (order[i] == order[i - 1])
3051 /* Is the memory address adjacent and ascending? */
3052 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3060 for (i = 0; i < nops; i++)
3061 regs[i] = unsorted_regs[order[i]];
3063 *load_offset = unsorted_offsets[order[0]];
3066 if (unsorted_offsets[order[0]] == 0)
3067 return 1; /* ldmia */
3069 if (unsorted_offsets[order[0]] == 4)
3070 return 2; /* ldmib */
3072 if (unsorted_offsets[order[nops - 1]] == 0)
3073 return 3; /* ldmda */
3075 if (unsorted_offsets[order[nops - 1]] == -4)
3076 return 4; /* ldmdb */
3078 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3079 if the offset isn't small enough. The reason 2 ldrs are faster
3080 is because these ARMs are able to do more than one cache access
3081 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3082 whilst the ARM8 has a double bandwidth cache. This means that
3083 these cores can do both an instruction fetch and a data fetch in
3084 a single cycle, so the trick of calculating the address into a
3085 scratch register (one of the result regs) and then doing a load
3086 multiple actually becomes slower (and no smaller in code size).
3087 That is the transformation
3089 ldr rd1, [rbase + offset]
3090 ldr rd2, [rbase + offset + 4]
3094 add rd1, rbase, offset
3095 ldmia rd1, {rd1, rd2}
3097 produces worse code -- '3 cycles + any stalls on rd2' instead of
3098 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3099 access per cycle, the first sequence could never complete in less
3100 than 6 cycles, whereas the ldm sequence would only take 5 and
3101 would make better use of sequential accesses if not hitting the
3104 We cheat here and test 'arm_ld_sched' which we currently know to
3105 only be true for the ARM8, ARM9 and StrongARM. If this ever
3106 changes, then the test below needs to be reworked. */
3107 if (nops == 2 && arm_ld_sched)
3110 /* Can't do it without setting up the offset, only do this if it takes
3111 no more than one insn. */
3112 return (const_ok_for_arm (unsorted_offsets[order[0]])
3113 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3117 emit_ldm_seq (operands, nops)
3123 HOST_WIDE_INT offset;
3127 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3130 strcpy (buf, "ldm%?ia\t");
3134 strcpy (buf, "ldm%?ib\t");
3138 strcpy (buf, "ldm%?da\t");
3142 strcpy (buf, "ldm%?db\t");
3147 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3148 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3151 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3152 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3154 output_asm_insn (buf, operands);
3156 strcpy (buf, "ldm%?ia\t");
3163 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3164 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3166 for (i = 1; i < nops; i++)
3167 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3168 reg_names[regs[i]]);
3170 strcat (buf, "}\t%@ phole ldm");
3172 output_asm_insn (buf, operands);
3177 store_multiple_sequence (operands, nops, regs, base, load_offset)
3182 HOST_WIDE_INT * load_offset;
3184 int unsorted_regs[4];
3185 HOST_WIDE_INT unsorted_offsets[4];
3190 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3191 extended if required. */
3192 if (nops < 2 || nops > 4)
3195 /* Loop over the operands and check that the memory references are
3196 suitable (ie immediate offsets from the same base register). At
3197 the same time, extract the target register, and the memory
3199 for (i = 0; i < nops; i++)
3204 /* Convert a subreg of a mem into the mem itself. */
3205 if (GET_CODE (operands[nops + i]) == SUBREG)
3206 operands[nops + i] = alter_subreg(operands[nops + i]);
3208 if (GET_CODE (operands[nops + i]) != MEM)
3211 /* Don't reorder volatile memory references; it doesn't seem worth
3212 looking for the case where the order is ok anyway. */
3213 if (MEM_VOLATILE_P (operands[nops + i]))
3216 offset = const0_rtx;
3218 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3219 || (GET_CODE (reg) == SUBREG
3220 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3221 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3222 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3224 || (GET_CODE (reg) == SUBREG
3225 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3226 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3231 base_reg = REGNO (reg);
3232 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3233 ? REGNO (operands[i])
3234 : REGNO (SUBREG_REG (operands[i])));
3239 if (base_reg != REGNO (reg))
3240 /* Not addressed from the same base register. */
3243 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3244 ? REGNO (operands[i])
3245 : REGNO (SUBREG_REG (operands[i])));
3246 if (unsorted_regs[i] < unsorted_regs[order[0]])
3250 /* If it isn't an integer register, then we can't do this. */
3251 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3254 unsorted_offsets[i] = INTVAL (offset);
3257 /* Not a suitable memory address. */
3261 /* All the useful information has now been extracted from the
3262 operands into unsorted_regs and unsorted_offsets; additionally,
3263 order[0] has been set to the lowest numbered register in the
3264 list. Sort the registers into order, and check that the memory
3265 offsets are ascending and adjacent. */
3267 for (i = 1; i < nops; i++)
3271 order[i] = order[i - 1];
3272 for (j = 0; j < nops; j++)
3273 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3274 && (order[i] == order[i - 1]
3275 || unsorted_regs[j] < unsorted_regs[order[i]]))
3278 /* Have we found a suitable register? if not, one must be used more
3280 if (order[i] == order[i - 1])
3283 /* Is the memory address adjacent and ascending? */
3284 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3292 for (i = 0; i < nops; i++)
3293 regs[i] = unsorted_regs[order[i]];
3295 *load_offset = unsorted_offsets[order[0]];
3298 if (unsorted_offsets[order[0]] == 0)
3299 return 1; /* stmia */
3301 if (unsorted_offsets[order[0]] == 4)
3302 return 2; /* stmib */
3304 if (unsorted_offsets[order[nops - 1]] == 0)
3305 return 3; /* stmda */
3307 if (unsorted_offsets[order[nops - 1]] == -4)
3308 return 4; /* stmdb */
3314 emit_stm_seq (operands, nops)
3320 HOST_WIDE_INT offset;
3324 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3327 strcpy (buf, "stm%?ia\t");
3331 strcpy (buf, "stm%?ib\t");
3335 strcpy (buf, "stm%?da\t");
3339 strcpy (buf, "stm%?db\t");
3346 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3347 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3349 for (i = 1; i < nops; i++)
3350 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3351 reg_names[regs[i]]);
3353 strcat (buf, "}\t%@ phole stm");
3355 output_asm_insn (buf, operands);
3360 multi_register_push (op, mode)
3362 enum machine_mode mode ATTRIBUTE_UNUSED;
3364 if (GET_CODE (op) != PARALLEL
3365 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3366 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3367 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3374 /* Routines for use with attributes */
3376 /* Return nonzero if ATTR is a valid attribute for DECL.
3377 ATTRIBUTES are any existing attributes and ARGS are the arguments
3380 Supported attributes:
3382 naked: don't output any prologue or epilogue code, the user is assumed
3383 to do the right thing. */
3386 arm_valid_machine_decl_attribute (decl, attr, args)
3391 if (args != NULL_TREE)
3394 if (is_attribute_p ("naked", attr))
3395 return TREE_CODE (decl) == FUNCTION_DECL;
3399 /* Return non-zero if FUNC is a naked function. */
3402 arm_naked_function_p (func)
3407 if (TREE_CODE (func) != FUNCTION_DECL)
3410 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3411 return a != NULL_TREE;
3414 /* Routines for use in generating RTL */
3417 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3418 in_struct_p, scalar_p)
3430 int sign = up ? 1 : -1;
3433 result = gen_rtx_PARALLEL (VOIDmode,
3434 rtvec_alloc (count + (write_back ? 2 : 0)));
3437 XVECEXP (result, 0, 0)
3438 = gen_rtx_SET (GET_MODE (from), from,
3439 plus_constant (from, count * 4 * sign));
3444 for (j = 0; i < count; i++, j++)
3446 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3447 RTX_UNCHANGING_P (mem) = unchanging_p;
3448 MEM_IN_STRUCT_P (mem) = in_struct_p;
3449 MEM_SCALAR_P (mem) = scalar_p;
3450 XVECEXP (result, 0, i)
3451 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3455 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3461 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3462 in_struct_p, scalar_p)
3474 int sign = up ? 1 : -1;
3477 result = gen_rtx_PARALLEL (VOIDmode,
3478 rtvec_alloc (count + (write_back ? 2 : 0)));
3481 XVECEXP (result, 0, 0)
3482 = gen_rtx_SET (GET_MODE (to), to,
3483 plus_constant (to, count * 4 * sign));
3488 for (j = 0; i < count; i++, j++)
3490 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3491 RTX_UNCHANGING_P (mem) = unchanging_p;
3492 MEM_IN_STRUCT_P (mem) = in_struct_p;
3493 MEM_SCALAR_P (mem) = scalar_p;
3495 XVECEXP (result, 0, i)
3496 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3500 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3506 arm_gen_movstrqi (operands)
3509 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3512 rtx st_src, st_dst, fin_src, fin_dst;
3513 rtx part_bytes_reg = NULL;
3515 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3516 int dst_scalar_p, src_scalar_p;
3518 if (GET_CODE (operands[2]) != CONST_INT
3519 || GET_CODE (operands[3]) != CONST_INT
3520 || INTVAL (operands[2]) > 64
3521 || INTVAL (operands[3]) & 3)
3524 st_dst = XEXP (operands[0], 0);
3525 st_src = XEXP (operands[1], 0);
3527 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3528 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3529 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3530 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3531 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3532 src_scalar_p = MEM_SCALAR_P (operands[1]);
3534 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3535 fin_src = src = copy_to_mode_reg (SImode, st_src);
3537 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3538 out_words_to_go = INTVAL (operands[2]) / 4;
3539 last_bytes = INTVAL (operands[2]) & 3;
3541 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3542 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3544 for (i = 0; in_words_to_go >= 2; i+=4)
3546 if (in_words_to_go > 4)
3547 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3552 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3553 FALSE, src_unchanging_p,
3554 src_in_struct_p, src_scalar_p));
3556 if (out_words_to_go)
3558 if (out_words_to_go > 4)
3559 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3563 else if (out_words_to_go != 1)
3564 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3573 mem = gen_rtx_MEM (SImode, dst);
3574 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3575 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3576 MEM_SCALAR_P (mem) = dst_scalar_p;
3577 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3578 if (last_bytes != 0)
3579 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3583 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3584 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3587 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3588 if (out_words_to_go)
3592 mem = gen_rtx_MEM (SImode, src);
3593 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3594 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3595 MEM_SCALAR_P (mem) = src_scalar_p;
3596 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3597 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3599 mem = gen_rtx_MEM (SImode, dst);
3600 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3601 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3602 MEM_SCALAR_P (mem) = dst_scalar_p;
3603 emit_move_insn (mem, sreg);
3604 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3607 if (in_words_to_go) /* Sanity check */
3613 if (in_words_to_go < 0)
3616 mem = gen_rtx_MEM (SImode, src);
3617 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3618 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3619 MEM_SCALAR_P (mem) = src_scalar_p;
3620 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3623 if (BYTES_BIG_ENDIAN && last_bytes)
3625 rtx tmp = gen_reg_rtx (SImode);
3627 if (part_bytes_reg == NULL)
3630 /* The bytes we want are in the top end of the word */
3631 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3632 GEN_INT (8 * (4 - last_bytes))));
3633 part_bytes_reg = tmp;
3637 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3638 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3639 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3640 MEM_SCALAR_P (mem) = dst_scalar_p;
3641 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3645 tmp = gen_reg_rtx (SImode);
3646 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3647 part_bytes_reg = tmp;
3656 if (part_bytes_reg == NULL)
3659 mem = gen_rtx_MEM (QImode, dst);
3660 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3661 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3662 MEM_SCALAR_P (mem) = dst_scalar_p;
3663 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3667 rtx tmp = gen_reg_rtx (SImode);
3669 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3670 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3671 part_bytes_reg = tmp;
3679 /* Generate a memory reference for a half word, such that it will be loaded
3680 into the top 16 bits of the word. We can assume that the address is
3681 known to be alignable and of the form reg, or plus (reg, const). */
3683 gen_rotated_half_load (memref)
3686 HOST_WIDE_INT offset = 0;
3687 rtx base = XEXP (memref, 0);
3689 if (GET_CODE (base) == PLUS)
3691 offset = INTVAL (XEXP (base, 1));
3692 base = XEXP (base, 0);
3695 /* If we aren't allowed to generate unaligned addresses, then fail. */
3696 if (TARGET_MMU_TRAPS
3697 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3700 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3702 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3705 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3708 static enum machine_mode
3709 select_dominance_cc_mode (x, y, cond_or)
3712 HOST_WIDE_INT cond_or;
3714 enum rtx_code cond1, cond2;
3717 /* Currently we will probably get the wrong result if the individual
3718 comparisons are not simple. This also ensures that it is safe to
3719 reverse a comparison if necessary. */
3720 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3722 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3727 cond1 = reverse_condition (cond1);
3729 /* If the comparisons are not equal, and one doesn't dominate the other,
3730 then we can't do this. */
3732 && ! comparison_dominates_p (cond1, cond2)
3733 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3738 enum rtx_code temp = cond1;
3746 if (cond2 == EQ || ! cond_or)
3751 case LE: return CC_DLEmode;
3752 case LEU: return CC_DLEUmode;
3753 case GE: return CC_DGEmode;
3754 case GEU: return CC_DGEUmode;
3761 if (cond2 == LT || ! cond_or)
3770 if (cond2 == GT || ! cond_or)
3779 if (cond2 == LTU || ! cond_or)
3788 if (cond2 == GTU || ! cond_or)
3796 /* The remaining cases only occur when both comparisons are the
3821 arm_select_cc_mode (op, x, y)
3826 /* All floating point compares return CCFP if it is an equality
3827 comparison, and CCFPE otherwise. */
3828 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3829 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3831 /* A compare with a shifted operand. Because of canonicalization, the
3832 comparison will have to be swapped when we emit the assembler. */
3833 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3834 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3835 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3836 || GET_CODE (x) == ROTATERT))
3839 /* This is a special case that is used by combine to allow a
3840 comparison of a shifted byte load to be split into a zero-extend
3841 followed by a comparison of the shifted integer (only valid for
3842 equalities and unsigned inequalities). */
3843 if (GET_MODE (x) == SImode
3844 && GET_CODE (x) == ASHIFT
3845 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3846 && GET_CODE (XEXP (x, 0)) == SUBREG
3847 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3848 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3849 && (op == EQ || op == NE
3850 || op == GEU || op == GTU || op == LTU || op == LEU)
3851 && GET_CODE (y) == CONST_INT)
3854 /* An operation that sets the condition codes as a side-effect, the
3855 V flag is not set correctly, so we can only use comparisons where
3856 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3858 if (GET_MODE (x) == SImode
3860 && (op == EQ || op == NE || op == LT || op == GE)
3861 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3862 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3863 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3864 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3865 || GET_CODE (x) == LSHIFTRT
3866 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3867 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3870 /* A construct for a conditional compare, if the false arm contains
3871 0, then both conditions must be true, otherwise either condition
3872 must be true. Not all conditions are possible, so CCmode is
3873 returned if it can't be done. */
3874 if (GET_CODE (x) == IF_THEN_ELSE
3875 && (XEXP (x, 2) == const0_rtx
3876 || XEXP (x, 2) == const1_rtx)
3877 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3878 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3879 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3880 INTVAL (XEXP (x, 2)));
3882 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3885 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3886 && GET_CODE (x) == PLUS
3887 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3893 /* X and Y are two things to compare using CODE. Emit the compare insn and
3894 return the rtx for register 0 in the proper mode. FP means this is a
3895 floating point compare: I don't think that it is needed on the arm. */
3898 gen_compare_reg (code, x, y)
3902 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3903 rtx cc_reg = gen_rtx_REG (mode, 24);
3905 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
3906 gen_rtx_COMPARE (mode, x, y)));
3912 arm_reload_in_hi (operands)
3915 rtx ref = operands[1];
3917 HOST_WIDE_INT offset = 0;
3919 if (GET_CODE (ref) == SUBREG)
3921 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3922 if (BYTES_BIG_ENDIAN)
3923 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3924 - MIN (UNITS_PER_WORD,
3925 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3926 ref = SUBREG_REG (ref);
3929 if (GET_CODE (ref) == REG)
3931 /* We have a pseudo which has been spilt onto the stack; there
3932 are two cases here: the first where there is a simple
3933 stack-slot replacement and a second where the stack-slot is
3934 out of range, or is used as a subreg. */
3935 if (reg_equiv_mem[REGNO (ref)])
3937 ref = reg_equiv_mem[REGNO (ref)];
3938 base = find_replacement (&XEXP (ref, 0));
3941 /* The slot is out of range, or was dressed up in a SUBREG */
3942 base = reg_equiv_address[REGNO (ref)];
3945 base = find_replacement (&XEXP (ref, 0));
3947 /* Handle the case where the address is too complex to be offset by 1. */
3948 if (GET_CODE (base) == MINUS
3949 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3951 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3953 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3956 else if (GET_CODE (base) == PLUS)
3958 /* The addend must be CONST_INT, or we would have dealt with it above */
3959 HOST_WIDE_INT hi, lo;
3961 offset += INTVAL (XEXP (base, 1));
3962 base = XEXP (base, 0);
3964 /* Rework the address into a legal sequence of insns */
3965 /* Valid range for lo is -4095 -> 4095 */
3968 : -((-offset) & 0xfff));
3970 /* Corner case, if lo is the max offset then we would be out of range
3971 once we have added the additional 1 below, so bump the msb into the
3972 pre-loading insn(s). */
3976 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
3977 ^ (HOST_WIDE_INT) 0x80000000UL)
3978 - (HOST_WIDE_INT) 0x80000000UL);
3980 if (hi + lo != offset)
3985 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3987 /* Get the base address; addsi3 knows how to handle constants
3988 that require more than one insn */
3989 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3995 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3996 emit_insn (gen_zero_extendqisi2 (scratch,
3997 gen_rtx_MEM (QImode,
3998 plus_constant (base,
4000 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4001 gen_rtx_MEM (QImode,
4002 plus_constant (base,
4004 if (! BYTES_BIG_ENDIAN)
4005 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4006 gen_rtx_IOR (SImode,
4009 gen_rtx_SUBREG (SImode, operands[0], 0),
4013 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4014 gen_rtx_IOR (SImode,
4015 gen_rtx_ASHIFT (SImode, scratch,
4017 gen_rtx_SUBREG (SImode, operands[0],
4021 /* Handle storing a half-word to memory during reload by synthesising as two
4022 byte stores. Take care not to clobber the input values until after we
4023 have moved them somewhere safe. This code assumes that if the DImode
4024 scratch in operands[2] overlaps either the input value or output address
4025 in some way, then that value must die in this insn (we absolutely need
4026 two scratch registers for some corner cases). */
4028 arm_reload_out_hi (operands)
4031 rtx ref = operands[0];
4032 rtx outval = operands[1];
4034 HOST_WIDE_INT offset = 0;
4036 if (GET_CODE (ref) == SUBREG)
4038 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4039 if (BYTES_BIG_ENDIAN)
4040 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4041 - MIN (UNITS_PER_WORD,
4042 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4043 ref = SUBREG_REG (ref);
4047 if (GET_CODE (ref) == REG)
4049 /* We have a pseudo which has been spilt onto the stack; there
4050 are two cases here: the first where there is a simple
4051 stack-slot replacement and a second where the stack-slot is
4052 out of range, or is used as a subreg. */
4053 if (reg_equiv_mem[REGNO (ref)])
4055 ref = reg_equiv_mem[REGNO (ref)];
4056 base = find_replacement (&XEXP (ref, 0));
4059 /* The slot is out of range, or was dressed up in a SUBREG */
4060 base = reg_equiv_address[REGNO (ref)];
4063 base = find_replacement (&XEXP (ref, 0));
4065 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4067 /* Handle the case where the address is too complex to be offset by 1. */
4068 if (GET_CODE (base) == MINUS
4069 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4071 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4073 /* Be careful not to destroy OUTVAL. */
4074 if (reg_overlap_mentioned_p (base_plus, outval))
4076 /* Updating base_plus might destroy outval, see if we can
4077 swap the scratch and base_plus. */
4078 if (! reg_overlap_mentioned_p (scratch, outval))
4081 scratch = base_plus;
4086 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4088 /* Be conservative and copy OUTVAL into the scratch now,
4089 this should only be necessary if outval is a subreg
4090 of something larger than a word. */
4091 /* XXX Might this clobber base? I can't see how it can,
4092 since scratch is known to overlap with OUTVAL, and
4093 must be wider than a word. */
4094 emit_insn (gen_movhi (scratch_hi, outval));
4095 outval = scratch_hi;
4099 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4102 else if (GET_CODE (base) == PLUS)
4104 /* The addend must be CONST_INT, or we would have dealt with it above */
4105 HOST_WIDE_INT hi, lo;
4107 offset += INTVAL (XEXP (base, 1));
4108 base = XEXP (base, 0);
4110 /* Rework the address into a legal sequence of insns */
4111 /* Valid range for lo is -4095 -> 4095 */
4114 : -((-offset) & 0xfff));
4116 /* Corner case, if lo is the max offset then we would be out of range
4117 once we have added the additional 1 below, so bump the msb into the
4118 pre-loading insn(s). */
4122 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4123 ^ (HOST_WIDE_INT) 0x80000000UL)
4124 - (HOST_WIDE_INT) 0x80000000UL);
4126 if (hi + lo != offset)
4131 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4133 /* Be careful not to destroy OUTVAL. */
4134 if (reg_overlap_mentioned_p (base_plus, outval))
4136 /* Updating base_plus might destroy outval, see if we
4137 can swap the scratch and base_plus. */
4138 if (! reg_overlap_mentioned_p (scratch, outval))
4141 scratch = base_plus;
4146 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4148 /* Be conservative and copy outval into scratch now,
4149 this should only be necessary if outval is a
4150 subreg of something larger than a word. */
4151 /* XXX Might this clobber base? I can't see how it
4152 can, since scratch is known to overlap with
4154 emit_insn (gen_movhi (scratch_hi, outval));
4155 outval = scratch_hi;
4159 /* Get the base address; addsi3 knows how to handle constants
4160 that require more than one insn */
4161 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4167 if (BYTES_BIG_ENDIAN)
4169 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4170 plus_constant (base, offset + 1)),
4171 gen_rtx_SUBREG (QImode, outval, 0)));
4172 emit_insn (gen_lshrsi3 (scratch,
4173 gen_rtx_SUBREG (SImode, outval, 0),
4175 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4176 gen_rtx_SUBREG (QImode, scratch, 0)));
4180 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4181 gen_rtx_SUBREG (QImode, outval, 0)));
4182 emit_insn (gen_lshrsi3 (scratch,
4183 gen_rtx_SUBREG (SImode, outval, 0),
4185 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4186 plus_constant (base, offset + 1)),
4187 gen_rtx_SUBREG (QImode, scratch, 0)));
4191 /* Routines for manipulation of the constant pool. */
4193 /* Arm instructions cannot load a large constant directly into a
4194 register; they have to come from a pc relative load. The constant
4195 must therefore be placed in the addressable range of the pc
4196 relative load. Depending on the precise pc relative load
4197 instruction the range is somewhere between 256 bytes and 4k. This
4198 means that we often have to dump a constant inside a function, and
4199 generate code to branch around it.
4201 It is important to minimize this, since the branches will slow
4202 things down and make the code larger.
4204 Normally we can hide the table after an existing unconditional
4205 branch so that there is no interruption of the flow, but in the
4206 worst case the code looks like this:
4224 We fix this by performing a scan after scheduling, which notices
4225 which instructions need to have their operands fetched from the
4226 constant table and builds the table.
4228 The algorithm starts by building a table of all the constants that
4229 need fixing up and all the natural barriers in the function (places
4230 where a constant table can be dropped without breaking the flow).
4231 For each fixup we note how far the pc-relative replacement will be
4232 able to reach and the offset of the instruction into the function.
4234 Having built the table we then group the fixes together to form
4235 tables that are as large as possible (subject to addressing
4236 constraints) and emit each table of constants after the last
4237 barrier that is within range of all the instructions in the group.
4238 If a group does not contain a barrier, then we forcibly create one
4239 by inserting a jump instruction into the flow. Once the table has
4240 been inserted, the insns are then modified to reference the
4241 relevant entry in the pool.
4243 Possible enhancements to the alogorithm (not implemented) are:
4245 1) ARM instructions (but not thumb) can use negative offsets, so we
4246 could reference back to a previous pool rather than forwards to a
4247 new one. For large functions this may reduce the number of pools
4250 2) For some processors and object formats, there may be benefit in
4251 aligning the pools to the start of cache lines; this alignment
4252 would need to be taken into account when calculating addressability
4259 rtx value; /* Value in table */
4260 HOST_WIDE_INT next_offset;
4261 enum machine_mode mode; /* Mode of value */
4264 /* The maximum number of constants that can fit into one pool, since
4265 the pc relative range is 0...4092 bytes and constants are at least 4
4268 #define MAX_MINIPOOL_SIZE (4092/4)
4269 static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
4270 static int minipool_size;
4271 static rtx minipool_vector_label;
4273 /* Add a constant to the pool and return its offset within the current
4276 X is the rtx we want to replace. MODE is its mode. On return,
4277 ADDRESS_ONLY will be non-zero if we really want the address of such
4278 a constant, not the constant itself. */
4279 static HOST_WIDE_INT
4280 add_minipool_constant (x, mode)
4282 enum machine_mode mode;
4285 HOST_WIDE_INT offset;
4287 /* First, see if we've already got it. */
4288 for (i = 0; i < minipool_size; i++)
4290 if (GET_CODE (x) == minipool_vector[i].value->code
4291 && mode == minipool_vector[i].mode)
4293 if (GET_CODE (x) == CODE_LABEL)
4295 if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
4298 if (rtx_equal_p (x, minipool_vector[i].value))
4299 return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
4303 /* Need a new one */
4304 minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
4306 if (minipool_size == 0)
4307 minipool_vector_label = gen_label_rtx ();
4309 minipool_vector[minipool_size].next_offset
4310 += (offset = minipool_vector[minipool_size - 1].next_offset);
4312 minipool_vector[minipool_size].value = x;
4313 minipool_vector[minipool_size].mode = mode;
4318 /* Output the literal table */
4320 dump_minipool (scan)
4325 scan = emit_label_after (gen_label_rtx (), scan);
4326 scan = emit_insn_after (gen_align_4 (), scan);
4327 scan = emit_label_after (minipool_vector_label, scan);
4329 for (i = 0; i < minipool_size; i++)
4331 minipool_node *p = minipool_vector + i;
4333 switch (GET_MODE_SIZE (p->mode))
4336 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4340 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4349 scan = emit_insn_after (gen_consttable_end (), scan);
4350 scan = emit_barrier_after (scan);
4354 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4357 find_barrier (from, max_count)
4362 rtx found_barrier = 0;
4365 while (from && count < max_count)
4369 if (GET_CODE (from) == BARRIER)
4370 found_barrier = from;
4372 /* Count the length of this insn */
4373 if (GET_CODE (from) == JUMP_INSN
4374 && JUMP_LABEL (from) != 0
4375 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4376 == next_real_insn (from))
4378 && GET_CODE (tmp) == JUMP_INSN
4379 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4380 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4382 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4383 count += (get_attr_length (from)
4384 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4385 /* Continue after the dispatch table. */
4387 from = NEXT_INSN (tmp);
4391 count += get_attr_length (from);
4394 from = NEXT_INSN (from);
4397 if (! found_barrier)
4399 /* We didn't find a barrier in time to
4400 dump our stuff, so we'll make one. */
4401 rtx label = gen_label_rtx ();
4404 from = PREV_INSN (last);
4406 from = get_last_insn ();
4408 /* Walk back to be just before any jump. */
4409 while (GET_CODE (from) == JUMP_INSN
4410 || GET_CODE (from) == NOTE
4411 || GET_CODE (from) == CODE_LABEL)
4412 from = PREV_INSN (from);
4414 from = emit_jump_insn_after (gen_jump (label), from);
4415 JUMP_LABEL (from) = label;
4416 found_barrier = emit_barrier_after (from);
4417 emit_label_after (label, found_barrier);
4420 return found_barrier;
4423 struct minipool_fixup
4425 struct minipool_fixup *next;
4429 enum machine_mode mode;
4434 struct minipool_fixup *minipool_fix_head;
4435 struct minipool_fixup *minipool_fix_tail;
4438 push_minipool_barrier (insn, address)
4442 struct minipool_fixup *fix
4443 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4446 fix->address = address;
4449 if (minipool_fix_head != NULL)
4450 minipool_fix_tail->next = fix;
4452 minipool_fix_head = fix;
4454 minipool_fix_tail = fix;
4458 push_minipool_fix (insn, address, loc, mode, value)
4462 enum machine_mode mode;
4465 struct minipool_fixup *fix
4466 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4468 #ifdef AOF_ASSEMBLER
4469 /* PIC symbol refereneces need to be converted into offsets into the
4471 if (flag_pic && GET_MODE == SYMBOL_REF)
4472 value = aof_pic_entry (value);
4473 #endif /* AOF_ASSEMBLER */
4476 fix->address = address;
4480 fix->range = get_attr_pool_range (insn);
4482 /* If an insn doesn't have a range defined for it, then it isn't
4483 expecting to be reworked by this code. Better to abort now than
4484 to generate duff assembly code. */
4485 if (fix->range == 0)
4488 /* Add it to the chain of fixes */
4490 if (minipool_fix_head != NULL)
4491 minipool_fix_tail->next = fix;
4493 minipool_fix_head = fix;
4495 minipool_fix_tail = fix;
4499 note_invalid_constants (insn, address)
4505 /* Extract the operands of the insn */
4508 /* Find the alternative selected */
4509 if (! constrain_operands (1))
4510 fatal_insn_not_found (insn);
4512 /* Preprocess the constraints, to extract some useful information. */
4513 preprocess_constraints ();
4515 for (opno = 0; opno < recog_data.n_operands; opno++)
4517 /* Things we need to fix can only occur in inputs */
4518 if (recog_data.operand_type[opno] != OP_IN)
4521 /* If this alternative is a memory reference, then any mention
4522 of constants in this alternative is really to fool reload
4523 into allowing us to accept one there. We need to fix them up
4524 now so that we output the right code. */
4525 if (recog_op_alt[opno][which_alternative].memory_ok)
4527 rtx op = recog_data.operand[opno];
4529 if (CONSTANT_P (op))
4530 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4531 recog_data.operand_mode[opno], op);
4532 #ifndef AOF_ASSEMBLER
4533 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
4534 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4535 recog_data.operand_mode[opno],
4536 XVECEXP (op, 0, 0));
4538 else if (recog_data.operand_mode[opno] == SImode
4539 && GET_CODE (op) == MEM
4540 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
4541 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4542 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4543 recog_data.operand_mode[opno],
4544 get_pool_constant (XEXP (op, 0)));
4555 struct minipool_fixup *fix;
4557 minipool_fix_head = minipool_fix_tail = NULL;
4559 /* The first insn must always be a note, or the code below won't
4560 scan it properly. */
4561 if (GET_CODE (first) != NOTE)
4564 /* Scan all the insns and record the operands that will need fixing. */
4565 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
4568 if (GET_CODE (insn) == BARRIER)
4569 push_minipool_barrier(insn, address);
4570 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
4571 || GET_CODE (insn) == JUMP_INSN)
4575 note_invalid_constants (insn, address);
4576 address += get_attr_length (insn);
4577 /* If the insn is a vector jump, add the size of the table
4578 and skip the table. */
4579 if (GET_CODE (insn) == JUMP_INSN
4580 && JUMP_LABEL (insn) != NULL
4581 && ((table = next_real_insn (JUMP_LABEL (insn)))
4582 == next_real_insn (insn))
4584 && GET_CODE (table) == JUMP_INSN
4585 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4586 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4588 int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
4590 address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
4597 /* Now scan the fixups and perform the required changes. */
4598 for (fix = minipool_fix_head; fix; fix = fix->next)
4600 struct minipool_fixup *ftmp;
4601 struct minipool_fixup *last_barrier = NULL;
4604 struct minipool_fixup *this_fix;
4605 int new_minipool_size = 0;
4607 /* Skip any further barriers before the next fix. */
4608 while (fix && GET_CODE (fix->insn) == BARRIER)
4615 max_range = fix->address + fix->range;
4617 /* Find all the other fixes that can live in the same pool. */
4618 while (ftmp->next && ftmp->next->address < max_range
4619 && (GET_CODE (ftmp->next->insn) == BARRIER
4620 /* Ensure we can reach the constant inside the pool. */
4621 || ftmp->next->range > new_minipool_size))
4624 if (GET_CODE (ftmp->insn) == BARRIER)
4625 last_barrier = ftmp;
4628 /* Does this fix constrain the range we can search? */
4629 if (ftmp->address + ftmp->range - new_minipool_size < max_range)
4630 max_range = ftmp->address + ftmp->range - new_minipool_size;
4632 new_minipool_size += GET_MODE_SIZE (ftmp->mode);
4636 /* If we found a barrier, drop back to that; any fixes that we could
4637 have reached but come after the barrier will now go in the next
4639 if (last_barrier != NULL)
4641 barrier = last_barrier->insn;
4642 ftmp = last_barrier;
4644 /* ftmp is last fix that we can fit into this pool and we
4645 failed to find a barrier that we could use. Insert a new
4646 barrier in the code and arrange to jump around it. */
4649 /* Check that there isn't another fix that is in range that
4650 we couldn't fit into this pool because the pool was
4651 already too large: we need to put the pool before such an
4653 if (ftmp->next && ftmp->next->address < max_range)
4654 max_range = ftmp->address;
4656 barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
4659 /* Scan over the fixes we have identified for this pool, fixing them
4660 up and adding the constants to the pool itself. */
4661 for (this_fix = fix; this_fix && ftmp->next != this_fix;
4662 this_fix = this_fix->next)
4663 if (GET_CODE (this_fix->insn) != BARRIER)
4665 int offset = add_minipool_constant (this_fix->value,
4668 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4669 minipool_vector_label),
4671 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
4674 dump_minipool (barrier);
4678 /* From now on we must synthesize any constants that we can't handle
4679 directly. This can happen if the RTL gets split during final
4680 instruction generation. */
4681 after_arm_reorg = 1;
4685 /* Routines to output assembly language. */
4687 /* If the rtx is the correct value then return the string of the number.
4688 In this way we can ensure that valid double constants are generated even
4689 when cross compiling. */
4691 fp_immediate_constant (x)
4697 if (!fpa_consts_inited)
4700 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4701 for (i = 0; i < 8; i++)
4702 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4703 return strings_fpa[i];
4708 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4710 fp_const_from_val (r)
4711 REAL_VALUE_TYPE * r;
4715 if (! fpa_consts_inited)
4718 for (i = 0; i < 8; i++)
4719 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4720 return strings_fpa[i];
4725 /* Output the operands of a LDM/STM instruction to STREAM.
4726 MASK is the ARM register set mask of which only bits 0-15 are important.
4727 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4728 must follow the register list. */
4731 print_multi_reg (stream, instr, reg, mask, hat)
4739 int not_first = FALSE;
4741 fputc ('\t', stream);
4742 asm_fprintf (stream, instr, reg);
4743 fputs (", {", stream);
4745 for (i = 0; i < 16; i++)
4746 if (mask & (1 << i))
4749 fprintf (stream, ", ");
4751 asm_fprintf (stream, "%r", i);
4755 fprintf (stream, "}%s\n", hat ? "^" : "");
4758 /* Output a 'call' insn. */
4761 output_call (operands)
4764 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4766 if (REGNO (operands[0]) == LR_REGNUM)
4768 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
4769 output_asm_insn ("mov%?\t%0, %|lr", operands);
4772 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4774 if (TARGET_INTERWORK)
4775 output_asm_insn ("bx%?\t%0", operands);
4777 output_asm_insn ("mov%?\t%|pc, %0", operands);
4786 int something_changed = 0;
4788 int code = GET_CODE (x0);
4790 register const char * fmt;
4795 if (REGNO (x0) == LR_REGNUM)
4797 *x = gen_rtx_REG (SImode, IP_REGNUM);
4802 /* Scan through the sub-elements and change any references there */
4803 fmt = GET_RTX_FORMAT (code);
4805 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4807 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4808 else if (fmt[i] == 'E')
4809 for (j = 0; j < XVECLEN (x0, i); j++)
4810 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4812 return something_changed;
4816 /* Output a 'call' insn that is a reference in memory. */
4819 output_call_mem (operands)
4822 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4823 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4825 if (eliminate_lr2ip (&operands[0]))
4826 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4828 if (TARGET_INTERWORK)
4830 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4831 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4832 output_asm_insn ("bx%?\t%|ip", operands);
4836 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4837 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4844 /* Output a move from arm registers to an fpu registers.
4845 OPERANDS[0] is an fpu register.
4846 OPERANDS[1] is the first registers of an arm register pair. */
4849 output_mov_long_double_fpu_from_arm (operands)
4852 int arm_reg0 = REGNO (operands[1]);
4855 if (arm_reg0 == IP_REGNUM)
4858 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4859 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4860 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4862 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4863 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4868 /* Output a move from an fpu register to arm registers.
4869 OPERANDS[0] is the first registers of an arm register pair.
4870 OPERANDS[1] is an fpu register. */
4873 output_mov_long_double_arm_from_fpu (operands)
4876 int arm_reg0 = REGNO (operands[0]);
4879 if (arm_reg0 == IP_REGNUM)
4882 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4883 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4884 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4886 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4887 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4891 /* Output a move from arm registers to arm registers of a long double
4892 OPERANDS[0] is the destination.
4893 OPERANDS[1] is the source. */
4895 output_mov_long_double_arm_from_arm (operands)
4898 /* We have to be careful here because the two might overlap */
4899 int dest_start = REGNO (operands[0]);
4900 int src_start = REGNO (operands[1]);
4904 if (dest_start < src_start)
4906 for (i = 0; i < 3; i++)
4908 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4909 ops[1] = gen_rtx_REG (SImode, src_start + i);
4910 output_asm_insn ("mov%?\t%0, %1", ops);
4915 for (i = 2; i >= 0; i--)
4917 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4918 ops[1] = gen_rtx_REG (SImode, src_start + i);
4919 output_asm_insn ("mov%?\t%0, %1", ops);
4927 /* Output a move from arm registers to an fpu registers.
4928 OPERANDS[0] is an fpu register.
4929 OPERANDS[1] is the first registers of an arm register pair. */
4932 output_mov_double_fpu_from_arm (operands)
4935 int arm_reg0 = REGNO (operands[1]);
4938 if (arm_reg0 == IP_REGNUM)
4941 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4942 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4943 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4944 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4948 /* Output a move from an fpu register to arm registers.
4949 OPERANDS[0] is the first registers of an arm register pair.
4950 OPERANDS[1] is an fpu register. */
4953 output_mov_double_arm_from_fpu (operands)
4956 int arm_reg0 = REGNO (operands[0]);
4959 if (arm_reg0 == IP_REGNUM)
4962 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4963 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4964 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4965 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4969 /* Output a move between double words.
4970 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4971 or MEM<-REG and all MEMs must be offsettable addresses. */
4974 output_move_double (operands)
4977 enum rtx_code code0 = GET_CODE (operands[0]);
4978 enum rtx_code code1 = GET_CODE (operands[1]);
4983 int reg0 = REGNO (operands[0]);
4985 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
4989 int reg1 = REGNO (operands[1]);
4990 if (reg1 == IP_REGNUM)
4993 /* Ensure the second source is not overwritten */
4994 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4995 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4997 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4999 else if (code1 == CONST_DOUBLE)
5001 if (GET_MODE (operands[1]) == DFmode)
5004 union real_extract u;
5006 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
5008 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
5009 otherops[1] = GEN_INT(l[1]);
5010 operands[1] = GEN_INT(l[0]);
5012 else if (GET_MODE (operands[1]) != VOIDmode)
5014 else if (WORDS_BIG_ENDIAN)
5017 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5018 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5023 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5024 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5027 output_mov_immediate (operands);
5028 output_mov_immediate (otherops);
5030 else if (code1 == CONST_INT)
5032 #if HOST_BITS_PER_WIDE_INT > 32
5033 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5034 what the upper word is. */
5035 if (WORDS_BIG_ENDIAN)
5037 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5038 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5042 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5043 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5046 /* Sign extend the intval into the high-order word */
5047 if (WORDS_BIG_ENDIAN)
5049 otherops[1] = operands[1];
5050 operands[1] = (INTVAL (operands[1]) < 0
5051 ? constm1_rtx : const0_rtx);
5054 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
5056 output_mov_immediate (otherops);
5057 output_mov_immediate (operands);
5059 else if (code1 == MEM)
5061 switch (GET_CODE (XEXP (operands[1], 0)))
5064 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
5068 abort (); /* Should never happen now */
5072 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
5076 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
5080 abort (); /* Should never happen now */
5085 output_asm_insn ("adr%?\t%0, %1", operands);
5086 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
5090 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
5091 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
5093 otherops[0] = operands[0];
5094 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
5095 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
5096 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
5098 if (GET_CODE (otherops[2]) == CONST_INT)
5100 switch (INTVAL (otherops[2]))
5103 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
5106 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
5109 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
5112 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
5113 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
5115 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5118 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5121 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
5123 return "ldm%?ia\t%0, %M0";
5127 otherops[1] = adj_offsettable_operand (operands[1], 4);
5128 /* Take care of overlapping base/data reg. */
5129 if (reg_mentioned_p (operands[0], operands[1]))
5131 output_asm_insn ("ldr%?\t%0, %1", otherops);
5132 output_asm_insn ("ldr%?\t%0, %1", operands);
5136 output_asm_insn ("ldr%?\t%0, %1", operands);
5137 output_asm_insn ("ldr%?\t%0, %1", otherops);
5143 abort (); /* Constraints should prevent this */
5145 else if (code0 == MEM && code1 == REG)
5147 if (REGNO (operands[1]) == IP_REGNUM)
5150 switch (GET_CODE (XEXP (operands[0], 0)))
5153 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
5157 abort (); /* Should never happen now */
5161 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
5165 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
5169 abort (); /* Should never happen now */
5173 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
5175 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
5178 output_asm_insn ("stm%?db\t%m0, %M1", operands);
5182 output_asm_insn ("stm%?da\t%m0, %M1", operands);
5186 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
5193 otherops[0] = adj_offsettable_operand (operands[0], 4);
5194 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
5195 output_asm_insn ("str%?\t%1, %0", operands);
5196 output_asm_insn ("str%?\t%1, %0", otherops);
5200 abort (); /* Constraints should prevent this */
5206 /* Output an arbitrary MOV reg, #n.
5207 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
5210 output_mov_immediate (operands)
5213 HOST_WIDE_INT n = INTVAL (operands[1]);
5217 /* Try to use one MOV */
5218 if (const_ok_for_arm (n))
5220 output_asm_insn ("mov%?\t%0, %1", operands);
5224 /* Try to use one MVN */
5225 if (const_ok_for_arm (~n))
5227 operands[1] = GEN_INT (~n);
5228 output_asm_insn ("mvn%?\t%0, %1", operands);
5232 /* If all else fails, make it out of ORRs or BICs as appropriate. */
5234 for (i=0; i < 32; i++)
5238 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
5239 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5242 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5249 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5250 adding zero to one register, output nothing. */
5253 output_add_immediate (operands)
5256 HOST_WIDE_INT n = INTVAL (operands[2]);
5258 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
5261 output_multi_immediate (operands,
5262 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5265 output_multi_immediate (operands,
5266 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5273 /* Output a multiple immediate operation.
5274 OPERANDS is the vector of operands referred to in the output patterns.
5275 INSTR1 is the output pattern to use for the first constant.
5276 INSTR2 is the output pattern to use for subsequent constants.
5277 IMMED_OP is the index of the constant slot in OPERANDS.
5278 N is the constant value. */
5281 output_multi_immediate (operands, instr1, instr2, immed_op, n)
5283 char * instr1, * instr2;
5287 #if HOST_BITS_PER_WIDE_INT > 32
5293 operands[immed_op] = const0_rtx;
5294 output_asm_insn (instr1, operands); /* Quick and easy output */
5299 char *instr = instr1;
5301 /* Note that n is never zero here (which would give no output) */
5302 for (i = 0; i < 32; i += 2)
5306 operands[immed_op] = GEN_INT (n & (255 << i));
5307 output_asm_insn (instr, operands);
5317 /* Return the appropriate ARM instruction for the operation code.
5318 The returned result should not be overwritten. OP is the rtx of the
5319 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5323 arithmetic_instr (op, shift_first_arg)
5325 int shift_first_arg;
5327 switch (GET_CODE (op))
5333 return shift_first_arg ? "rsb" : "sub";
5350 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5351 for the operation code. The returned result should not be overwritten.
5352 OP is the rtx code of the shift.
5353 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5357 shift_op (op, amountp)
5359 HOST_WIDE_INT *amountp;
5362 enum rtx_code code = GET_CODE (op);
5364 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5366 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5367 *amountp = INTVAL (XEXP (op, 1));
5390 /* We never have to worry about the amount being other than a
5391 power of 2, since this case can never be reloaded from a reg. */
5393 *amountp = int_log2 (*amountp);
5404 /* This is not 100% correct, but follows from the desire to merge
5405 multiplication by a power of 2 with the recognizer for a
5406 shift. >=32 is not a valid shift for "asl", so we must try and
5407 output a shift that produces the correct arithmetical result.
5408 Using lsr #32 is identical except for the fact that the carry bit
5409 is not set correctly if we set the flags; but we never use the
5410 carry bit from such an operation, so we can ignore that. */
5411 if (code == ROTATERT)
5412 *amountp &= 31; /* Rotate is just modulo 32 */
5413 else if (*amountp != (*amountp & 31))
5420 /* Shifts of 0 are no-ops. */
5429 /* Obtain the shift from the POWER of two. */
5431 static HOST_WIDE_INT
5433 HOST_WIDE_INT power;
5435 HOST_WIDE_INT shift = 0;
5437 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5447 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5448 /bin/as is horribly restrictive. */
5449 #define MAX_ASCII_LEN 51
5452 output_ascii_pseudo_op (stream, p, len)
5460 fputs ("\t.ascii\t\"", stream);
5462 for (i = 0; i < len; i++)
5464 register int c = p[i];
5466 if (len_so_far >= MAX_ASCII_LEN)
5468 fputs ("\"\n\t.ascii\t\"", stream);
5475 fputs ("\\t", stream);
5480 fputs ("\\f", stream);
5485 fputs ("\\b", stream);
5490 fputs ("\\r", stream);
5494 case TARGET_NEWLINE:
5495 fputs ("\\n", stream);
5497 if ((c >= ' ' && c <= '~')
5499 /* This is a good place for a line break. */
5500 len_so_far = MAX_ASCII_LEN;
5507 putc ('\\', stream);
5512 if (c >= ' ' && c <= '~')
5519 fprintf (stream, "\\%03o", c);
5526 fputs ("\"\n", stream);
5530 /* Try to determine whether a pattern really clobbers the link register.
5531 This information is useful when peepholing, so that lr need not be pushed
5532 if we combine a call followed by a return.
5533 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5534 such a check should not be needed because these only update an existing
5535 value within a register; the register must still be set elsewhere within
5539 pattern_really_clobbers_lr (x)
5544 switch (GET_CODE (x))
5547 switch (GET_CODE (SET_DEST (x)))
5550 return REGNO (SET_DEST (x)) == LR_REGNUM;
5553 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5554 return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
5556 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5565 for (i = 0; i < XVECLEN (x, 0); i++)
5566 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5571 switch (GET_CODE (XEXP (x, 0)))
5574 return REGNO (XEXP (x, 0)) == LR_REGNUM;
5577 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5578 return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
5594 function_really_clobbers_lr (first)
5599 for (insn = first; insn; insn = next_nonnote_insn (insn))
5601 switch (GET_CODE (insn))
5606 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5610 if (pattern_really_clobbers_lr (PATTERN (insn)))
5615 /* Don't yet know how to handle those calls that are not to a
5617 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5620 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5623 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5629 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5635 default: /* Don't recognize it, be safe */
5639 /* A call can be made (by peepholing) not to clobber lr iff it is
5640 followed by a return. There may, however, be a use insn iff
5641 we are returning the result of the call.
5642 If we run off the end of the insn chain, then that means the
5643 call was at the end of the function. Unfortunately we don't
5644 have a return insn for the peephole to recognize, so we
5645 must reject this. (Can this be fixed by adding our own insn?) */
5646 if ((next = next_nonnote_insn (insn)) == NULL)
5649 /* No need to worry about lr if the call never returns */
5650 if (GET_CODE (next) == BARRIER)
5653 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5654 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5655 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5656 == REGNO (XEXP (PATTERN (next), 0))))
5657 if ((next = next_nonnote_insn (next)) == NULL)
5660 if (GET_CODE (next) == JUMP_INSN
5661 && GET_CODE (PATTERN (next)) == RETURN)
5670 /* We have reached the end of the chain so lr was _not_ clobbered */
5675 output_return_instruction (operand, really_return, reverse)
5681 int reg, live_regs = 0;
5682 int volatile_func = (optimize > 0
5683 && TREE_THIS_VOLATILE (current_function_decl));
5685 return_used_this_function = 1;
5687 if (TARGET_ABORT_NORETURN && volatile_func)
5689 /* If this function was declared non-returning, and we have found a tail
5690 call, then we have to trust that the called function won't return. */
5695 /* Otherwise, trap an attempted return by aborting. */
5697 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
5699 assemble_external_libcall (ops[1]);
5700 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5706 if (current_function_calls_alloca && ! really_return)
5709 for (reg = 0; reg <= 10; reg++)
5710 if (regs_ever_live[reg] && ! call_used_regs[reg])
5713 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5714 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5717 if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
5720 if (frame_pointer_needed)
5723 /* On some ARM architectures it is faster to use LDR rather than LDM to
5724 load a single register. On other architectures, the cost is the same. */
5726 && regs_ever_live[LR_REGNUM]
5727 && ! lr_save_eliminated
5728 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
5729 really_return is true, and only the PC needs restoring. */
5732 output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
5733 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
5737 if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
5740 if (frame_pointer_needed)
5742 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5745 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5747 for (reg = 0; reg <= 10; reg++)
5748 if (regs_ever_live[reg]
5749 && (! call_used_regs[reg]
5750 || (flag_pic && ! TARGET_SINGLE_PIC_BASE
5751 && reg == PIC_OFFSET_TABLE_REGNUM)))
5753 strcat (instr, "%|");
5754 strcat (instr, reg_names[reg]);
5756 strcat (instr, ", ");
5759 if (frame_pointer_needed)
5761 strcat (instr, "%|");
5762 strcat (instr, reg_names[11]);
5763 strcat (instr, ", ");
5764 strcat (instr, "%|");
5765 strcat (instr, reg_names[13]);
5766 strcat (instr, ", ");
5767 strcat (instr, "%|");
5768 strcat (instr, TARGET_INTERWORK || (! really_return)
5769 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
5773 strcat (instr, "%|");
5774 if (TARGET_INTERWORK && really_return)
5775 strcat (instr, reg_names[IP_REGNUM]);
5777 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
5779 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5780 output_asm_insn (instr, &operand);
5782 if (TARGET_INTERWORK && really_return)
5784 strcpy (instr, "bx%?");
5785 strcat (instr, reverse ? "%D0" : "%d0");
5786 strcat (instr, "\t%|");
5787 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5789 output_asm_insn (instr, & operand);
5792 else if (really_return)
5794 if (TARGET_INTERWORK)
5795 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5797 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5798 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5800 output_asm_insn (instr, & operand);
5806 /* Return nonzero if optimizing and the current function is volatile.
5807 Such functions never return, and many memory cycles can be saved
5808 by not storing register values that will never be needed again.
5809 This optimization was added to speed up context switching in a
5810 kernel application. */
5813 arm_volatile_func ()
5815 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5818 /* Write the function name into the code section, directly preceding
5819 the function prologue.
5821 Code will be output similar to this:
5823 .ascii "arm_poke_function_name", 0
5826 .word 0xff000000 + (t1 - t0)
5827 arm_poke_function_name
5829 stmfd sp!, {fp, ip, lr, pc}
5832 When performing a stack backtrace, code can inspect the value
5833 of 'pc' stored at 'fp' + 0. If the trace function then looks
5834 at location pc - 12 and the top 8 bits are set, then we know
5835 that there is a function name embedded immediately preceding this
5836 location and has length ((pc[-3]) & 0xff000000).
5838 We assume that pc is declared as a pointer to an unsigned long.
5840 It is of no benefit to output the function name if we are assembling
5841 a leaf function. These function types will not contain a stack
5842 backtrace structure, therefore it is not possible to determine the
5846 arm_poke_function_name (stream, name)
5850 unsigned long alignlength;
5851 unsigned long length;
5854 length = strlen (name) + 1;
5855 alignlength = (length + 3) & ~3;
5857 ASM_OUTPUT_ASCII (stream, name, length);
5858 ASM_OUTPUT_ALIGN (stream, 2);
5859 x = GEN_INT (0xff000000UL + alignlength);
5860 ASM_OUTPUT_INT (stream, x);
5863 /* The amount of stack adjustment that happens here, in output_return and in
5864 output_epilogue must be exactly the same as was calculated during reload,
5865 or things will point to the wrong place. The only time we can safely
5866 ignore this constraint is when a function has no arguments on the stack,
5867 no stack frame requirement and no live registers execpt for `lr'. If we
5868 can guarantee that by making all function calls into tail calls and that
5869 lr is not clobbered in any other way, then there is no need to push lr
5873 output_func_prologue (f, frame_size)
5877 int reg, live_regs_mask = 0;
5878 int volatile_func = (optimize > 0
5879 && TREE_THIS_VOLATILE (current_function_decl));
5881 /* Nonzero if we must stuff some register arguments onto the stack as if
5882 they were passed there. */
5883 int store_arg_regs = 0;
5885 if (arm_ccfsm_state || arm_target_insn)
5886 abort (); /* Sanity check */
5888 if (arm_naked_function_p (current_function_decl))
5891 return_used_this_function = 0;
5892 lr_save_eliminated = 0;
5894 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
5895 current_function_args_size,
5896 current_function_pretend_args_size, frame_size);
5897 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
5898 frame_pointer_needed,
5899 current_function_anonymous_args);
5902 asm_fprintf (f, "\t%@ Volatile function.\n");
5904 if (current_function_anonymous_args && current_function_pretend_args_size)
5907 for (reg = 0; reg <= 10; reg++)
5908 if (regs_ever_live[reg] && ! call_used_regs[reg])
5909 live_regs_mask |= (1 << reg);
5911 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5912 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5913 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5915 if (frame_pointer_needed)
5916 live_regs_mask |= 0xD800;
5917 else if (regs_ever_live[LR_REGNUM])
5919 if (! current_function_args_size
5920 && ! function_really_clobbers_lr (get_insns ()))
5921 lr_save_eliminated = 1;
5923 live_regs_mask |= 1 << LR_REGNUM;
5928 /* if a di mode load/store multiple is used, and the base register
5929 is r3, then r4 can become an ever live register without lr
5930 doing so, in this case we need to push lr as well, or we
5931 will fail to get a proper return. */
5933 live_regs_mask |= 1 << LR_REGNUM;
5934 lr_save_eliminated = 0;
5938 if (lr_save_eliminated)
5939 asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
5941 #ifdef AOF_ASSEMBLER
5943 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
5948 arm_output_epilogue ()
5951 int live_regs_mask = 0;
5952 /* If we need this, then it will always be at least this much */
5953 int floats_offset = 12;
5955 int frame_size = get_frame_size ();
5956 FILE *f = asm_out_file;
5957 int volatile_func = (optimize > 0
5958 && TREE_THIS_VOLATILE (current_function_decl));
5960 if (use_return_insn (FALSE) && return_used_this_function)
5963 /* Naked functions don't have epilogues. */
5964 if (arm_naked_function_p (current_function_decl))
5967 /* A volatile function should never return. Call abort. */
5968 if (TARGET_ABORT_NORETURN && volatile_func)
5971 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
5972 assemble_external_libcall (op);
5973 output_asm_insn ("bl\t%a0", &op);
5977 for (reg = 0; reg <= 10; reg++)
5978 if (regs_ever_live[reg] && ! call_used_regs[reg])
5980 live_regs_mask |= (1 << reg);
5984 /* If we aren't loading the PIC register, don't stack it even though it may
5986 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5987 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5989 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5993 if (frame_pointer_needed)
5995 if (arm_fpu_arch == FP_SOFT2)
5997 for (reg = 23; reg > 15; reg--)
5998 if (regs_ever_live[reg] && ! call_used_regs[reg])
6000 floats_offset += 12;
6001 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
6002 reg, FP_REGNUM, floats_offset);
6009 for (reg = 23; reg > 15; reg--)
6011 if (regs_ever_live[reg] && ! call_used_regs[reg])
6013 floats_offset += 12;
6015 /* We can't unstack more than four registers at once */
6016 if (start_reg - reg == 3)
6018 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
6019 reg, FP_REGNUM, floats_offset);
6020 start_reg = reg - 1;
6025 if (reg != start_reg)
6026 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6027 reg + 1, start_reg - reg,
6028 FP_REGNUM, floats_offset);
6029 start_reg = reg - 1;
6033 /* Just in case the last register checked also needs unstacking. */
6034 if (reg != start_reg)
6035 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6036 reg + 1, start_reg - reg,
6037 FP_REGNUM, floats_offset);
6040 if (TARGET_INTERWORK)
6042 live_regs_mask |= 0x6800;
6043 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
6044 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6048 live_regs_mask |= 0xA800;
6049 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
6050 TARGET_APCS_32 ? FALSE : TRUE);
6055 /* Restore stack pointer if necessary. */
6056 if (frame_size + current_function_outgoing_args_size != 0)
6058 operands[0] = operands[1] = stack_pointer_rtx;
6059 operands[2] = GEN_INT (frame_size
6060 + current_function_outgoing_args_size);
6061 output_add_immediate (operands);
6064 if (arm_fpu_arch == FP_SOFT2)
6066 for (reg = 16; reg < 24; reg++)
6067 if (regs_ever_live[reg] && ! call_used_regs[reg])
6068 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
6075 for (reg = 16; reg < 24; reg++)
6077 if (regs_ever_live[reg] && ! call_used_regs[reg])
6079 if (reg - start_reg == 3)
6081 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
6082 start_reg, SP_REGNUM);
6083 start_reg = reg + 1;
6088 if (reg != start_reg)
6089 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6090 start_reg, reg - start_reg,
6093 start_reg = reg + 1;
6097 /* Just in case the last register checked also needs unstacking. */
6098 if (reg != start_reg)
6099 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6100 start_reg, reg - start_reg, SP_REGNUM);
6103 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
6105 if (TARGET_INTERWORK)
6107 if (! lr_save_eliminated)
6108 live_regs_mask |= 1 << LR_REGNUM;
6110 if (live_regs_mask != 0)
6111 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6113 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6115 else if (lr_save_eliminated)
6116 asm_fprintf (f, "\tmov%c\t%r, %r\n",
6117 TARGET_APCS_32 ? ' ' : 's',
6118 PC_REGNUM, LR_REGNUM);
6120 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
6121 TARGET_APCS_32 ? FALSE : TRUE);
6125 if (live_regs_mask || regs_ever_live[LR_REGNUM])
6127 /* Restore the integer regs, and the return address into lr */
6128 if (! lr_save_eliminated)
6129 live_regs_mask |= 1 << LR_REGNUM;
6131 if (live_regs_mask != 0)
6132 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6135 if (current_function_pretend_args_size)
6137 /* Unwind the pre-pushed regs */
6138 operands[0] = operands[1] = stack_pointer_rtx;
6139 operands[2] = GEN_INT (current_function_pretend_args_size);
6140 output_add_immediate (operands);
6142 /* And finally, go home */
6143 if (TARGET_INTERWORK)
6144 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6145 else if (TARGET_APCS_32)
6146 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6148 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6156 output_func_epilogue (frame_size)
6159 if (use_return_insn (FALSE) && return_used_this_function
6160 && (frame_size + current_function_outgoing_args_size) != 0
6161 && ! (frame_pointer_needed && TARGET_APCS))
6164 /* Reset the ARM-specific per-function variables. */
6165 current_function_anonymous_args = 0;
6166 after_arm_reorg = 0;
6170 emit_multi_reg_push (mask)
6177 for (i = 0; i < 16; i++)
6178 if (mask & (1 << i))
6181 if (num_regs == 0 || num_regs > 16)
6184 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
6186 for (i = 0; i < 16; i++)
6188 if (mask & (1 << i))
6191 = gen_rtx_SET (VOIDmode,
6192 gen_rtx_MEM (BLKmode,
6193 gen_rtx_PRE_DEC (BLKmode,
6194 stack_pointer_rtx)),
6195 gen_rtx_UNSPEC (BLKmode,
6197 gen_rtx_REG (SImode, i)),
6203 for (j = 1, i++; j < num_regs; i++)
6205 if (mask & (1 << i))
6208 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
6217 emit_sfm (base_reg, count)
6224 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6227 = gen_rtx_SET (VOIDmode,
6228 gen_rtx_MEM (BLKmode,
6229 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
6230 gen_rtx_UNSPEC (BLKmode,
6231 gen_rtvec (1, gen_rtx_REG (XFmode,
6234 for (i = 1; i < count; i++)
6235 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
6236 gen_rtx_REG (XFmode, base_reg++));
6242 arm_expand_prologue ()
6245 rtx amount = GEN_INT (-(get_frame_size ()
6246 + current_function_outgoing_args_size));
6247 int live_regs_mask = 0;
6248 int store_arg_regs = 0;
6249 /* If this function doesn't return, then there is no need to push
6250 the call-saved regs. */
6251 int volatile_func = (optimize > 0
6252 && TREE_THIS_VOLATILE (current_function_decl));
6254 /* Naked functions don't have prologues. */
6255 if (arm_naked_function_p (current_function_decl))
6258 if (current_function_anonymous_args && current_function_pretend_args_size)
6261 if (! volatile_func)
6263 for (reg = 0; reg <= 10; reg++)
6264 if (regs_ever_live[reg] && ! call_used_regs[reg])
6265 live_regs_mask |= 1 << reg;
6267 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6268 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6270 if (regs_ever_live[LR_REGNUM])
6271 live_regs_mask |= 1 << LR_REGNUM;
6274 if (frame_pointer_needed)
6276 live_regs_mask |= 0xD800;
6277 emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
6278 stack_pointer_rtx));
6281 if (current_function_pretend_args_size)
6284 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
6287 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6288 GEN_INT (-current_function_pretend_args_size)));
6293 /* If we have to push any regs, then we must push lr as well, or
6294 we won't get a proper return. */
6295 live_regs_mask |= 1 << LR_REGNUM;
6296 emit_multi_reg_push (live_regs_mask);
6299 /* For now the integer regs are still pushed in output_func_epilogue (). */
6301 if (! volatile_func)
6303 if (arm_fpu_arch == FP_SOFT2)
6305 for (reg = 23; reg > 15; reg--)
6306 if (regs_ever_live[reg] && ! call_used_regs[reg])
6307 emit_insn (gen_rtx_SET
6309 gen_rtx_MEM (XFmode,
6310 gen_rtx_PRE_DEC (XFmode,
6311 stack_pointer_rtx)),
6312 gen_rtx_REG (XFmode, reg)));
6318 for (reg = 23; reg > 15; reg--)
6320 if (regs_ever_live[reg] && ! call_used_regs[reg])
6322 if (start_reg - reg == 3)
6325 start_reg = reg - 1;
6330 if (start_reg != reg)
6331 emit_sfm (reg + 1, start_reg - reg);
6332 start_reg = reg - 1;
6336 if (start_reg != reg)
6337 emit_sfm (reg + 1, start_reg - reg);
6341 if (frame_pointer_needed)
6342 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, IP_REGNUM),
6344 (-(4 + current_function_pretend_args_size)))));
6346 if (amount != const0_rtx)
6348 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
6349 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6350 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
6353 /* If we are profiling, make sure no instructions are scheduled before
6354 the call to mcount. Similarly if the user has requested no
6355 scheduling in the prolog. */
6356 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
6357 emit_insn (gen_blockage ());
6361 /* If CODE is 'd', then the X is a condition operand and the instruction
6362 should only be executed if the condition is true.
6363 if CODE is 'D', then the X is a condition operand and the instruction
6364 should only be executed if the condition is false: however, if the mode
6365 of the comparison is CCFPEmode, then always execute the instruction -- we
6366 do this because in these circumstances !GE does not necessarily imply LT;
6367 in these cases the instruction pattern will take care to make sure that
6368 an instruction containing %d will follow, thereby undoing the effects of
6369 doing this instruction unconditionally.
6370 If CODE is 'N' then X is a floating point operand that must be negated
6372 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6373 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6376 arm_print_operand (stream, x, code)
6384 fputs (ASM_COMMENT_START, stream);
6388 fputs (REGISTER_PREFIX, stream);
6392 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
6393 fputs (arm_condition_codes[arm_current_cc], stream);
6399 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6400 r = REAL_VALUE_NEGATE (r);
6401 fprintf (stream, "%s", fp_const_from_val (&r));
6406 if (GET_CODE (x) == CONST_INT)
6409 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6410 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6415 output_addr_const (stream, x);
6420 fprintf (stream, "%s", arithmetic_instr (x, 1));
6424 fprintf (stream, "%s", arithmetic_instr (x, 0));
6430 char * shift = shift_op (x, & val);
6434 fprintf (stream, ", %s ", shift_op (x, & val));
6436 arm_print_operand (stream, XEXP (x, 1), 0);
6439 fputc ('#', stream);
6440 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6449 fputs (REGISTER_PREFIX, stream);
6450 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6456 fputs (REGISTER_PREFIX, stream);
6457 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6461 fputs (REGISTER_PREFIX, stream);
6462 if (GET_CODE (XEXP (x, 0)) == REG)
6463 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6465 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6469 asm_fprintf (stream, "{%r-%r}",
6470 REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
6475 fputs (arm_condition_codes[get_arm_condition_code (x)],
6481 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6482 (get_arm_condition_code (x))],
6490 if (GET_CODE (x) == REG)
6492 fputs (REGISTER_PREFIX, stream);
6493 fputs (reg_names[REGNO (x)], stream);
6495 else if (GET_CODE (x) == MEM)
6497 output_memory_reference_mode = GET_MODE (x);
6498 output_address (XEXP (x, 0));
6500 else if (GET_CODE (x) == CONST_DOUBLE)
6501 fprintf (stream, "#%s", fp_immediate_constant (x));
6502 else if (GET_CODE (x) == NEG)
6503 abort (); /* This should never happen now. */
6506 fputc ('#', stream);
6507 output_addr_const (stream, x);
6512 /* A finite state machine takes care of noticing whether or not instructions
6513 can be conditionally executed, and thus decrease execution time and code
6514 size by deleting branch instructions. The fsm is controlled by
6515 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6517 /* The state of the fsm controlling condition codes are:
6518 0: normal, do nothing special
6519 1: make ASM_OUTPUT_OPCODE not output this instruction
6520 2: make ASM_OUTPUT_OPCODE not output this instruction
6521 3: make instructions conditional
6522 4: make instructions conditional
6524 State transitions (state->state by whom under condition):
6525 0 -> 1 final_prescan_insn if the `target' is a label
6526 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6527 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6528 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6529 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6530 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6531 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6532 (the target insn is arm_target_insn).
6534 If the jump clobbers the conditions then we use states 2 and 4.
6536 A similar thing can be done with conditional return insns.
6538 XXX In case the `target' is an unconditional branch, this conditionalising
6539 of the instructions always reduces code size, but not always execution
6540 time. But then, I want to reduce the code size to somewhere near what
6541 /bin/cc produces. */
6543 /* Returns the index of the ARM condition code string in
6544 `arm_condition_codes'. COMPARISON should be an rtx like
6545 `(eq (...) (...))'. */
6547 static enum arm_cond_code
6548 get_arm_condition_code (comparison)
6551 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6553 register enum rtx_code comp_code = GET_CODE (comparison);
6555 if (GET_MODE_CLASS (mode) != MODE_CC)
6556 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6557 XEXP (comparison, 1));
6561 case CC_DNEmode: code = ARM_NE; goto dominance;
6562 case CC_DEQmode: code = ARM_EQ; goto dominance;
6563 case CC_DGEmode: code = ARM_GE; goto dominance;
6564 case CC_DGTmode: code = ARM_GT; goto dominance;
6565 case CC_DLEmode: code = ARM_LE; goto dominance;
6566 case CC_DLTmode: code = ARM_LT; goto dominance;
6567 case CC_DGEUmode: code = ARM_CS; goto dominance;
6568 case CC_DGTUmode: code = ARM_HI; goto dominance;
6569 case CC_DLEUmode: code = ARM_LS; goto dominance;
6570 case CC_DLTUmode: code = ARM_CC;
6573 if (comp_code != EQ && comp_code != NE)
6576 if (comp_code == EQ)
6577 return ARM_INVERSE_CONDITION_CODE (code);
6583 case NE: return ARM_NE;
6584 case EQ: return ARM_EQ;
6585 case GE: return ARM_PL;
6586 case LT: return ARM_MI;
6594 case NE: return ARM_NE;
6595 case EQ: return ARM_EQ;
6602 case GE: return ARM_GE;
6603 case GT: return ARM_GT;
6604 case LE: return ARM_LS;
6605 case LT: return ARM_MI;
6612 case NE: return ARM_NE;
6613 case EQ: return ARM_EQ;
6614 case GE: return ARM_LE;
6615 case GT: return ARM_LT;
6616 case LE: return ARM_GE;
6617 case LT: return ARM_GT;
6618 case GEU: return ARM_LS;
6619 case GTU: return ARM_CC;
6620 case LEU: return ARM_CS;
6621 case LTU: return ARM_HI;
6628 case LTU: return ARM_CS;
6629 case GEU: return ARM_CC;
6636 case NE: return ARM_NE;
6637 case EQ: return ARM_EQ;
6638 case GE: return ARM_GE;
6639 case GT: return ARM_GT;
6640 case LE: return ARM_LE;
6641 case LT: return ARM_LT;
6642 case GEU: return ARM_CS;
6643 case GTU: return ARM_HI;
6644 case LEU: return ARM_LS;
6645 case LTU: return ARM_CC;
6657 arm_final_prescan_insn (insn)
6660 /* BODY will hold the body of INSN. */
6661 register rtx body = PATTERN (insn);
6663 /* This will be 1 if trying to repeat the trick, and things need to be
6664 reversed if it appears to fail. */
6667 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6668 taken are clobbered, even if the rtl suggests otherwise. It also
6669 means that we have to grub around within the jump expression to find
6670 out what the conditions are when the jump isn't taken. */
6671 int jump_clobbers = 0;
6673 /* If we start with a return insn, we only succeed if we find another one. */
6674 int seeking_return = 0;
6676 /* START_INSN will hold the insn from where we start looking. This is the
6677 first insn after the following code_label if REVERSE is true. */
6678 rtx start_insn = insn;
6680 /* If in state 4, check if the target branch is reached, in order to
6681 change back to state 0. */
6682 if (arm_ccfsm_state == 4)
6684 if (insn == arm_target_insn)
6686 arm_target_insn = NULL;
6687 arm_ccfsm_state = 0;
6692 /* If in state 3, it is possible to repeat the trick, if this insn is an
6693 unconditional branch to a label, and immediately following this branch
6694 is the previous target label which is only used once, and the label this
6695 branch jumps to is not too far off. */
6696 if (arm_ccfsm_state == 3)
6698 if (simplejump_p (insn))
6700 start_insn = next_nonnote_insn (start_insn);
6701 if (GET_CODE (start_insn) == BARRIER)
6703 /* XXX Isn't this always a barrier? */
6704 start_insn = next_nonnote_insn (start_insn);
6706 if (GET_CODE (start_insn) == CODE_LABEL
6707 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6708 && LABEL_NUSES (start_insn) == 1)
6713 else if (GET_CODE (body) == RETURN)
6715 start_insn = next_nonnote_insn (start_insn);
6716 if (GET_CODE (start_insn) == BARRIER)
6717 start_insn = next_nonnote_insn (start_insn);
6718 if (GET_CODE (start_insn) == CODE_LABEL
6719 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6720 && LABEL_NUSES (start_insn) == 1)
6732 if (arm_ccfsm_state != 0 && !reverse)
6734 if (GET_CODE (insn) != JUMP_INSN)
6737 /* This jump might be paralleled with a clobber of the condition codes
6738 the jump should always come first */
6739 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6740 body = XVECEXP (body, 0, 0);
6743 /* If this is a conditional return then we don't want to know */
6744 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6745 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6746 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6747 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6752 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6753 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6756 int fail = FALSE, succeed = FALSE;
6757 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6758 int then_not_else = TRUE;
6759 rtx this_insn = start_insn, label = 0;
6761 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6763 /* The code below is wrong for these, and I haven't time to
6764 fix it now. So we just do the safe thing and return. This
6765 whole function needs re-writing anyway. */
6770 /* Register the insn jumped to. */
6773 if (!seeking_return)
6774 label = XEXP (SET_SRC (body), 0);
6776 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6777 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6778 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6780 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6781 then_not_else = FALSE;
6783 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6785 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6788 then_not_else = FALSE;
6793 /* See how many insns this branch skips, and what kind of insns. If all
6794 insns are okay, and the label or unconditional branch to the same
6795 label is not too far away, succeed. */
6796 for (insns_skipped = 0;
6797 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6801 this_insn = next_nonnote_insn (this_insn);
6805 switch (GET_CODE (this_insn))
6808 /* Succeed if it is the target label, otherwise fail since
6809 control falls in from somewhere else. */
6810 if (this_insn == label)
6814 arm_ccfsm_state = 2;
6815 this_insn = next_nonnote_insn (this_insn);
6818 arm_ccfsm_state = 1;
6826 /* Succeed if the following insn is the target label.
6828 If return insns are used then the last insn in a function
6829 will be a barrier. */
6830 this_insn = next_nonnote_insn (this_insn);
6831 if (this_insn && this_insn == label)
6835 arm_ccfsm_state = 2;
6836 this_insn = next_nonnote_insn (this_insn);
6839 arm_ccfsm_state = 1;
6847 /* If using 32-bit addresses the cc is not preserved over
6851 /* Succeed if the following insn is the target label,
6852 or if the following two insns are a barrier and
6853 the target label. */
6854 this_insn = next_nonnote_insn (this_insn);
6855 if (this_insn && GET_CODE (this_insn) == BARRIER)
6856 this_insn = next_nonnote_insn (this_insn);
6858 if (this_insn && this_insn == label
6859 && insns_skipped < max_insns_skipped)
6863 arm_ccfsm_state = 2;
6864 this_insn = next_nonnote_insn (this_insn);
6867 arm_ccfsm_state = 1;
6876 /* If this is an unconditional branch to the same label, succeed.
6877 If it is to another label, do nothing. If it is conditional,
6879 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6881 scanbody = PATTERN (this_insn);
6882 if (GET_CODE (scanbody) == SET
6883 && GET_CODE (SET_DEST (scanbody)) == PC)
6885 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
6886 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
6888 arm_ccfsm_state = 2;
6891 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
6894 /* Fail if a conditional return is undesirable (eg on a
6895 StrongARM), but still allow this if optimizing for size. */
6896 else if (GET_CODE (scanbody) == RETURN
6897 && ! use_return_insn (TRUE)
6900 else if (GET_CODE (scanbody) == RETURN
6903 arm_ccfsm_state = 2;
6906 else if (GET_CODE (scanbody) == PARALLEL)
6908 switch (get_attr_conds (this_insn))
6920 /* Instructions using or affecting the condition codes make it
6922 scanbody = PATTERN (this_insn);
6923 if (! (GET_CODE (scanbody) == SET
6924 || GET_CODE (scanbody) == PARALLEL)
6925 || get_attr_conds (this_insn) != CONDS_NOCOND)
6935 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
6936 arm_target_label = CODE_LABEL_NUMBER (label);
6937 else if (seeking_return || arm_ccfsm_state == 2)
6939 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
6941 this_insn = next_nonnote_insn (this_insn);
6942 if (this_insn && (GET_CODE (this_insn) == BARRIER
6943 || GET_CODE (this_insn) == CODE_LABEL))
6948 /* Oh, dear! we ran off the end.. give up */
6949 recog (PATTERN (insn), insn, NULL_PTR);
6950 arm_ccfsm_state = 0;
6951 arm_target_insn = NULL;
6954 arm_target_insn = this_insn;
6963 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
6965 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
6966 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6967 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
6968 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6972 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6975 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
6979 if (reverse || then_not_else)
6980 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6983 /* Restore recog_data (getting the attributes of other insns can
6984 destroy this array, but final.c assumes that it remains intact
6985 across this call; since the insn has been recognized already we
6986 call recog direct). */
6987 recog (PATTERN (insn), insn, NULL_PTR);
6991 #ifdef AOF_ASSEMBLER
6992 /* Special functions only needed when producing AOF syntax assembler. */
6994 rtx aof_pic_label = NULL_RTX;
6997 struct pic_chain * next;
7001 static struct pic_chain * aof_pic_chain = NULL;
7007 struct pic_chain ** chainp;
7010 if (aof_pic_label == NULL_RTX)
7012 /* We mark this here and not in arm_add_gc_roots() to avoid
7013 polluting even more code with ifdefs, and because it never
7014 contains anything useful until we assign to it here. */
7015 ggc_add_rtx_root (&aof_pic_label, 1);
7016 /* This needs to persist throughout the compilation. */
7017 end_temporary_allocation ();
7018 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
7019 resume_temporary_allocation ();
7022 for (offset = 0, chainp = &aof_pic_chain; *chainp;
7023 offset += 4, chainp = &(*chainp)->next)
7024 if ((*chainp)->symname == XSTR (x, 0))
7025 return plus_constant (aof_pic_label, offset);
7027 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
7028 (*chainp)->next = NULL;
7029 (*chainp)->symname = XSTR (x, 0);
7030 return plus_constant (aof_pic_label, offset);
7034 aof_dump_pic_table (f)
7037 struct pic_chain * chain;
7039 if (aof_pic_chain == NULL)
7042 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
7043 PIC_OFFSET_TABLE_REGNUM,
7044 PIC_OFFSET_TABLE_REGNUM);
7045 fputs ("|x$adcons|\n", f);
7047 for (chain = aof_pic_chain; chain; chain = chain->next)
7049 fputs ("\tDCD\t", f);
7050 assemble_name (f, chain->symname);
7055 int arm_text_section_count = 1;
7060 static char buf[100];
7061 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
7062 arm_text_section_count++);
7064 strcat (buf, ", PIC, REENTRANT");
7068 static int arm_data_section_count = 1;
7073 static char buf[100];
7074 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
7078 /* The AOF assembler is religiously strict about declarations of
7079 imported and exported symbols, so that it is impossible to declare
7080 a function as imported near the beginning of the file, and then to
7081 export it later on. It is, however, possible to delay the decision
7082 until all the functions in the file have been compiled. To get
7083 around this, we maintain a list of the imports and exports, and
7084 delete from it any that are subsequently defined. At the end of
7085 compilation we spit the remainder of the list out before the END
7090 struct import * next;
7094 static struct import * imports_list = NULL;
7097 aof_add_import (name)
7100 struct import * new;
7102 for (new = imports_list; new; new = new->next)
7103 if (new->name == name)
7106 new = (struct import *) xmalloc (sizeof (struct import));
7107 new->next = imports_list;
7113 aof_delete_import (name)
7116 struct import ** old;
7118 for (old = &imports_list; *old; old = & (*old)->next)
7120 if ((*old)->name == name)
7122 *old = (*old)->next;
7128 int arm_main_function = 0;
7131 aof_dump_imports (f)
7134 /* The AOF assembler needs this to cause the startup code to be extracted
7135 from the library. Brining in __main causes the whole thing to work
7137 if (arm_main_function)
7140 fputs ("\tIMPORT __main\n", f);
7141 fputs ("\tDCD __main\n", f);
7144 /* Now dump the remaining imports. */
7145 while (imports_list)
7147 fprintf (f, "\tIMPORT\t");
7148 assemble_name (f, imports_list->name);
7150 imports_list = imports_list->next;
7153 #endif /* AOF_ASSEMBLER */