1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
46 #define Mmode enum machine_mode
49 /* Some function declarations. */
50 static HOST_WIDE_INT int_log2 PARAMS ((HOST_WIDE_INT));
51 static char * output_multi_immediate PARAMS ((rtx *, char *, char *, int, HOST_WIDE_INT));
52 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, HOST_WIDE_INT, rtx, rtx, int, int));
53 static int arm_naked_function_p PARAMS ((tree));
54 static void init_fpa_table PARAMS ((void));
55 static enum machine_mode select_dominance_cc_mode PARAMS ((rtx, rtx, HOST_WIDE_INT));
56 static HOST_WIDE_INT add_minipool_constant PARAMS ((rtx, Mmode));
57 static void dump_minipool PARAMS ((rtx));
58 static rtx find_barrier PARAMS ((rtx, int));
59 static void push_minipool_fix PARAMS ((rtx, int, rtx *, Mmode, rtx));
60 static void push_minipool_barrier PARAMS ((rtx, int));
61 static void note_invalid_constants PARAMS ((rtx, int));
62 static char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
63 static int eliminate_lr2ip PARAMS ((rtx *));
64 static char * shift_op PARAMS ((rtx, HOST_WIDE_INT *));
65 static int pattern_really_clobbers_lr PARAMS ((rtx));
66 static int function_really_clobbers_lr PARAMS ((rtx));
67 static void emit_multi_reg_push PARAMS ((int));
68 static void emit_sfm PARAMS ((int, int));
69 static enum arm_cond_code get_arm_condition_code PARAMS ((rtx));
70 static int const_ok_for_op PARAMS ((HOST_WIDE_INT, enum rtx_code));
71 static void arm_add_gc_roots PARAMS ((void));
73 /* The maximum number of insns skipped which will be conditionalised if
75 static int max_insns_skipped = 5;
77 extern FILE * asm_out_file;
79 /* True if we are currently building a constant table. */
80 int making_const_table;
82 /* Define the information needed to generate branch insns. This is
83 stored from the compare operation. */
84 rtx arm_compare_op0, arm_compare_op1;
86 /* What type of floating point are we tuning for? */
87 enum floating_point_type arm_fpu;
89 /* What type of floating point instructions are available? */
90 enum floating_point_type arm_fpu_arch;
92 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
93 enum prog_mode_type arm_prgmode;
95 /* Set by the -mfp=... option */
96 const char * target_fp_name = NULL;
98 /* Used to parse -mstructure_size_boundary command line option. */
99 const char * structure_size_string = NULL;
100 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
102 /* Bit values used to identify processor capabilities. */
103 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
104 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
105 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
106 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
107 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
108 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
109 #define FL_THUMB (1 << 6) /* Thumb aware */
110 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
111 #define FL_STRONG (1 << 8) /* StrongARM */
113 /* The bits in this mask specify which instructions we are allowed to
115 static int insn_flags = 0;
116 /* The bits in this mask specify which instruction scheduling options should
117 be used. Note - there is an overlap with the FL_FAST_MULT. For some
118 hardware we want to be able to generate the multiply instructions, but to
119 tune as if they were not present in the architecture. */
120 static int tune_flags = 0;
122 /* The following are used in the arm.md file as equivalents to bits
123 in the above two flag variables. */
125 /* Nonzero if this is an "M" variant of the processor. */
126 int arm_fast_multiply = 0;
128 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
131 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
134 /* Nonzero if this chip can benefit from load scheduling. */
135 int arm_ld_sched = 0;
137 /* Nonzero if this chip is a StrongARM. */
138 int arm_is_strong = 0;
140 /* Nonzero if this chip is a an ARM6 or an ARM7. */
141 int arm_is_6_or_7 = 0;
143 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
144 must report the mode of the memory reference from PRINT_OPERAND to
145 PRINT_OPERAND_ADDRESS. */
146 enum machine_mode output_memory_reference_mode;
148 /* Nonzero if the prologue must setup `fp'. */
149 int current_function_anonymous_args;
151 /* The register number to be used for the PIC offset register. */
152 const char * arm_pic_register_string = NULL;
153 int arm_pic_register = 9;
155 /* Set to one if we think that lr is only saved because of subroutine calls,
156 but all of these can be `put after' return insns */
157 int lr_save_eliminated;
159 /* Set to 1 when a return insn is output, this means that the epilogue
161 static int return_used_this_function;
163 /* Set to 1 after arm_reorg has started. Reset to start at the start of
164 the next function. */
165 static int after_arm_reorg = 0;
167 /* The maximum number of insns to be used when loading a constant. */
168 static int arm_constant_limit = 3;
170 /* For an explanation of these variables, see final_prescan_insn below. */
172 enum arm_cond_code arm_current_cc;
174 int arm_target_label;
176 /* The condition codes of the ARM, and the inverse function. */
177 char * arm_condition_codes[] =
179 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
180 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
183 static enum arm_cond_code get_arm_condition_code ();
185 #define streq(string1, string2) (strcmp (string1, string2) == 0)
187 /* Initialization code */
195 /* Not all of these give usefully different compilation alternatives,
196 but there is no simple way of generalizing them. */
197 static struct processors all_cores[] =
201 {"arm2", FL_CO_PROC | FL_MODE26 },
202 {"arm250", FL_CO_PROC | FL_MODE26 },
203 {"arm3", FL_CO_PROC | FL_MODE26 },
204 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
205 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
206 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm610", FL_MODE26 | FL_MODE32 },
208 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
210 /* arm7m doesn't exist on its own, but only with D, (and I), but
211 those don't alter the code, so arm7m is sometimes used. */
212 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
213 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
214 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
215 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
216 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
217 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
218 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
219 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
220 {"arm710", FL_MODE26 | FL_MODE32 },
221 {"arm720", FL_MODE26 | FL_MODE32 },
222 {"arm710c", FL_MODE26 | FL_MODE32 },
223 {"arm7100", FL_MODE26 | FL_MODE32 },
224 {"arm7500", FL_MODE26 | FL_MODE32 },
225 /* Doesn't have an external co-proc, but does have embedded fpu. */
226 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
227 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
228 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
229 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
230 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
231 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
232 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
233 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
234 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
235 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
236 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
241 static struct processors all_architectures[] =
243 /* ARM Architectures */
245 { "armv2", FL_CO_PROC | FL_MODE26 },
246 { "armv2a", FL_CO_PROC | FL_MODE26 },
247 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
248 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
249 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
250 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
251 implementations that support it, so we will leave it out for now. */
252 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
253 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
257 /* This is a magic stucture. The 'string' field is magically filled in
258 with a pointer to the value specified by the user on the command line
259 assuming that the user has specified such a value. */
261 struct arm_cpu_select arm_select[] =
263 /* string name processors */
264 { NULL, "-mcpu=", all_cores },
265 { NULL, "-march=", all_architectures },
266 { NULL, "-mtune=", all_cores }
269 /* Return the number of bits set in value' */
274 unsigned int count = 0;
278 value &= ~(value & - value);
285 /* Fix up any incompatible options that the user has specified.
286 This has now turned into a maze. */
288 arm_override_options ()
292 /* Set up the flags based on the cpu/architecture selected by the user. */
293 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
295 struct arm_cpu_select * ptr = arm_select + i;
297 if (ptr->string != NULL && ptr->string[0] != '\0')
299 const struct processors * sel;
301 for (sel = ptr->processors; sel->name != NULL; sel ++)
302 if (streq (ptr->string, sel->name))
305 tune_flags = sel->flags;
308 /* If we have been given an architecture and a processor
309 make sure that they are compatible. We only generate
310 a warning though, and we prefer the CPU over the
312 if (insn_flags != 0 && (insn_flags ^ sel->flags))
313 warning ("switch -mcpu=%s conflicts with -march= switch",
316 insn_flags = sel->flags;
322 if (sel->name == NULL)
323 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
327 /* If the user did not specify a processor, choose one for them. */
330 struct processors * sel;
332 static struct cpu_default
339 { TARGET_CPU_arm2, "arm2" },
340 { TARGET_CPU_arm6, "arm6" },
341 { TARGET_CPU_arm610, "arm610" },
342 { TARGET_CPU_arm710, "arm710" },
343 { TARGET_CPU_arm7m, "arm7m" },
344 { TARGET_CPU_arm7500fe, "arm7500fe" },
345 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
346 { TARGET_CPU_arm8, "arm8" },
347 { TARGET_CPU_arm810, "arm810" },
348 { TARGET_CPU_arm9, "arm9" },
349 { TARGET_CPU_strongarm, "strongarm" },
350 { TARGET_CPU_generic, "arm" },
353 struct cpu_default * def;
355 /* Find the default. */
356 for (def = cpu_defaults; def->name; def ++)
357 if (def->cpu == TARGET_CPU_DEFAULT)
360 /* Make sure we found the default CPU. */
361 if (def->name == NULL)
364 /* Find the default CPU's flags. */
365 for (sel = all_cores; sel->name != NULL; sel ++)
366 if (streq (def->name, sel->name))
369 if (sel->name == NULL)
372 insn_flags = sel->flags;
374 /* Now check to see if the user has specified some command line
375 switch that require certain abilities from the cpu. */
378 if (TARGET_INTERWORK)
380 sought |= (FL_THUMB | FL_MODE32);
382 /* Force apcs-32 to be used for interworking. */
383 target_flags |= ARM_FLAG_APCS_32;
385 /* There are no ARM processor that supports both APCS-26 and
386 interworking. Therefore we force FL_MODE26 to be removed
387 from insn_flags here (if it was set), so that the search
388 below will always be able to find a compatible processor. */
389 insn_flags &= ~ FL_MODE26;
392 if (! TARGET_APCS_32)
395 if (sought != 0 && ((sought & insn_flags) != sought))
397 /* Try to locate a CPU type that supports all of the abilities
398 of the default CPU, plus the extra abilities requested by
400 for (sel = all_cores; sel->name != NULL; sel ++)
401 if ((sel->flags & sought) == (sought | insn_flags))
404 if (sel->name == NULL)
406 unsigned int current_bit_count = 0;
407 struct processors * best_fit = NULL;
409 /* Ideally we would like to issue an error message here
410 saying that it was not possible to find a CPU compatible
411 with the default CPU, but which also supports the command
412 line options specified by the programmer, and so they
413 ought to use the -mcpu=<name> command line option to
414 override the default CPU type.
416 Unfortunately this does not work with multilibing. We
417 need to be able to support multilibs for -mapcs-26 and for
418 -mthumb-interwork and there is no CPU that can support both
419 options. Instead if we cannot find a cpu that has both the
420 characteristics of the default cpu and the given command line
421 options we scan the array again looking for a best match. */
422 for (sel = all_cores; sel->name != NULL; sel ++)
423 if ((sel->flags & sought) == sought)
427 count = bit_count (sel->flags & insn_flags);
429 if (count >= current_bit_count)
432 current_bit_count = count;
436 if (best_fit == NULL)
442 insn_flags = sel->flags;
446 /* If tuning has not been specified, tune for whichever processor or
447 architecture has been selected. */
449 tune_flags = insn_flags;
451 /* Make sure that the processor choice does not conflict with any of the
452 other command line choices. */
453 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
455 /* If APCS-32 was not the default then it must have been set by the
456 user, so issue a warning message. If the user has specified
457 "-mapcs-32 -mcpu=arm2" then we loose here. */
458 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
459 warning ("target CPU does not support APCS-32" );
460 target_flags &= ~ ARM_FLAG_APCS_32;
462 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
464 warning ("target CPU does not support APCS-26" );
465 target_flags |= ARM_FLAG_APCS_32;
468 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
470 warning ("target CPU does not support interworking" );
471 target_flags &= ~ARM_FLAG_INTERWORK;
474 /* If interworking is enabled then APCS-32 must be selected as well. */
475 if (TARGET_INTERWORK)
477 if (! TARGET_APCS_32)
478 warning ("interworking forces APCS-32 to be used" );
479 target_flags |= ARM_FLAG_APCS_32;
482 if (TARGET_APCS_STACK && ! TARGET_APCS)
484 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
485 target_flags |= ARM_FLAG_APCS_FRAME;
488 if (TARGET_POKE_FUNCTION_NAME)
489 target_flags |= ARM_FLAG_APCS_FRAME;
491 if (TARGET_APCS_REENT && flag_pic)
492 fatal ("-fpic and -mapcs-reent are incompatible");
494 if (TARGET_APCS_REENT)
495 warning ("APCS reentrant code not supported. Ignored");
497 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
498 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
500 /* If stack checking is disabled, we can use r10 as the PIC register,
501 which keeps r9 available. */
502 if (flag_pic && ! TARGET_APCS_STACK)
503 arm_pic_register = 10;
505 if (TARGET_APCS_FLOAT)
506 warning ("Passing floating point arguments in fp regs not yet supported");
508 /* Initialise boolean versions of the flags, for use in the arm.md file. */
509 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
510 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
511 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
513 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
514 arm_is_strong = (tune_flags & FL_STRONG) != 0;
515 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
516 && !(tune_flags & FL_ARCH4)) != 0;
518 /* Default value for floating point code... if no co-processor
519 bus, then schedule for emulated floating point. Otherwise,
520 assume the user has an FPA.
521 Note: this does not prevent use of floating point instructions,
522 -msoft-float does that. */
523 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
527 if (streq (target_fp_name, "2"))
528 arm_fpu_arch = FP_SOFT2;
529 else if (streq (target_fp_name, "3"))
530 arm_fpu_arch = FP_SOFT3;
532 fatal ("Invalid floating point emulation option: -mfpe-%s",
536 arm_fpu_arch = FP_DEFAULT;
538 if (TARGET_FPE && arm_fpu != FP_HARD)
541 /* For arm2/3 there is no need to do any scheduling if there is only
542 a floating point emulator, or we are doing software floating-point. */
543 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
544 && (tune_flags & FL_MODE32) == 0)
545 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
547 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
549 if (structure_size_string != NULL)
551 int size = strtol (structure_size_string, NULL, 0);
553 if (size == 8 || size == 32)
554 arm_structure_size_boundary = size;
556 warning ("Structure size boundary can only be set to 8 or 32");
559 if (arm_pic_register_string != NULL)
564 warning ("-mpic-register= is useless without -fpic");
566 pic_register = decode_reg_name (arm_pic_register_string);
568 /* Prevent the user from choosing an obviously stupid PIC register. */
569 if (pic_register < 0 || call_used_regs[pic_register]
570 || pic_register == HARD_FRAME_POINTER_REGNUM
571 || pic_register == STACK_POINTER_REGNUM
572 || pic_register >= PC_REGNUM)
573 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
575 arm_pic_register = pic_register;
578 /* If optimizing for space, don't synthesize constants.
579 For processors with load scheduling, it never costs more than 2 cycles
580 to load a constant, and the load scheduler may well reduce that to 1. */
581 if (optimize_size || (tune_flags & FL_LDSCHED))
582 arm_constant_limit = 1;
584 /* If optimizing for size, bump the number of instructions that we
585 are prepared to conditionally execute (even on a StrongARM).
586 Otherwise for the StrongARM, which has early execution of branches,
587 a sequence that is worth skipping is shorter. */
589 max_insns_skipped = 6;
590 else if (arm_is_strong)
591 max_insns_skipped = 3;
593 /* Register global variables with the garbage collector. */
600 ggc_add_rtx_root (&arm_compare_op0, 1);
601 ggc_add_rtx_root (&arm_compare_op1, 1);
602 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
603 /* XXX: What about the minipool tables? */
607 /* Return 1 if it is possible to return using a single instruction */
610 use_return_insn (iscond)
615 if (!reload_completed
616 || current_function_pretend_args_size
617 || current_function_anonymous_args
618 || ((get_frame_size () + current_function_outgoing_args_size != 0)
619 && !(TARGET_APCS && frame_pointer_needed)))
622 /* Can't be done if interworking with Thumb, and any registers have been
623 stacked. Similarly, on StrongARM, conditional returns are expensive
624 if they aren't taken and registers have been stacked. */
625 if (iscond && arm_is_strong && frame_pointer_needed)
627 if ((iscond && arm_is_strong)
630 for (regno = 0; regno < 16; regno++)
631 if (regs_ever_live[regno] && ! call_used_regs[regno])
634 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
638 /* Can't be done if any of the FPU regs are pushed, since this also
640 for (regno = 16; regno < 24; regno++)
641 if (regs_ever_live[regno] && ! call_used_regs[regno])
644 /* If a function is naked, don't use the "return" insn. */
645 if (arm_naked_function_p (current_function_decl))
651 /* Return TRUE if int I is a valid immediate ARM constant. */
657 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
659 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
660 be all zero, or all one. */
661 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
662 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
663 != ((~(unsigned HOST_WIDE_INT) 0)
664 & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
667 /* Fast return for 0 and powers of 2 */
668 if ((i & (i - 1)) == 0)
673 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
676 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
677 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
678 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
683 /* Return true if I is a valid constant for the operation CODE. */
685 const_ok_for_op (i, code)
689 if (const_ok_for_arm (i))
695 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
697 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
703 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
710 /* Emit a sequence of insns to handle a large constant.
711 CODE is the code of the operation required, it can be any of SET, PLUS,
712 IOR, AND, XOR, MINUS;
713 MODE is the mode in which the operation is being performed;
714 VAL is the integer to operate on;
715 SOURCE is the other operand (a register, or a null-pointer for SET);
716 SUBTARGETS means it is safe to create scratch registers if that will
717 either produce a simpler sequence, or we will want to cse the values.
718 Return value is the number of insns emitted. */
721 arm_split_constant (code, mode, val, target, source, subtargets)
723 enum machine_mode mode;
729 if (subtargets || code == SET
730 || (GET_CODE (target) == REG && GET_CODE (source) == REG
731 && REGNO (target) != REGNO (source)))
733 /* After arm_reorg has been called, we can't fix up expensive
734 constants by pushing them into memory so we must synthesise
735 them in-line, regardless of the cost. This is only likely to
736 be more costly on chips that have load delay slots and we are
737 compiling without running the scheduler (so no splitting
738 occurred before the final instruction emission).
740 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
742 if (! after_arm_reorg
743 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
744 > arm_constant_limit + (code != SET)))
748 /* Currently SET is the only monadic value for CODE, all
749 the rest are diadic. */
750 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
755 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
757 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
758 /* For MINUS, the value is subtracted from, since we never
759 have subtraction of a constant. */
761 emit_insn (gen_rtx_SET (VOIDmode, target,
762 gen_rtx (code, mode, temp, source)));
764 emit_insn (gen_rtx_SET (VOIDmode, target,
765 gen_rtx (code, mode, source, temp)));
771 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
774 /* As above, but extra parameter GENERATE which, if clear, suppresses
777 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
779 enum machine_mode mode;
788 int can_negate_initial = 0;
791 int num_bits_set = 0;
792 int set_sign_bit_copies = 0;
793 int clear_sign_bit_copies = 0;
794 int clear_zero_bit_copies = 0;
795 int set_zero_bit_copies = 0;
797 unsigned HOST_WIDE_INT temp1, temp2;
798 unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
800 /* find out which operations are safe for a given CODE. Also do a quick
801 check for degenerate cases; these can occur when DImode operations
813 can_negate_initial = 1;
817 if (remainder == 0xffffffffUL)
820 emit_insn (gen_rtx_SET (VOIDmode, target,
821 GEN_INT (ARM_SIGN_EXTEND (val))));
826 if (reload_completed && rtx_equal_p (target, source))
829 emit_insn (gen_rtx_SET (VOIDmode, target, source));
838 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
841 if (remainder == 0xffffffffUL)
843 if (reload_completed && rtx_equal_p (target, source))
846 emit_insn (gen_rtx_SET (VOIDmode, target, source));
855 if (reload_completed && rtx_equal_p (target, source))
858 emit_insn (gen_rtx_SET (VOIDmode, target, source));
861 if (remainder == 0xffffffffUL)
864 emit_insn (gen_rtx_SET (VOIDmode, target,
865 gen_rtx_NOT (mode, source)));
869 /* We don't know how to handle this yet below. */
873 /* We treat MINUS as (val - source), since (source - val) is always
874 passed as (source + (-val)). */
878 emit_insn (gen_rtx_SET (VOIDmode, target,
879 gen_rtx_NEG (mode, source)));
882 if (const_ok_for_arm (val))
885 emit_insn (gen_rtx_SET (VOIDmode, target,
886 gen_rtx_MINUS (mode, GEN_INT (val),
898 /* If we can do it in one insn get out quickly */
899 if (const_ok_for_arm (val)
900 || (can_negate_initial && const_ok_for_arm (-val))
901 || (can_invert && const_ok_for_arm (~val)))
904 emit_insn (gen_rtx_SET (VOIDmode, target,
905 (source ? gen_rtx (code, mode, source,
912 /* Calculate a few attributes that may be useful for specific
915 for (i = 31; i >= 0; i--)
917 if ((remainder & (1 << i)) == 0)
918 clear_sign_bit_copies++;
923 for (i = 31; i >= 0; i--)
925 if ((remainder & (1 << i)) != 0)
926 set_sign_bit_copies++;
931 for (i = 0; i <= 31; i++)
933 if ((remainder & (1 << i)) == 0)
934 clear_zero_bit_copies++;
939 for (i = 0; i <= 31; i++)
941 if ((remainder & (1 << i)) != 0)
942 set_zero_bit_copies++;
950 /* See if we can do this by sign_extending a constant that is known
951 to be negative. This is a good, way of doing it, since the shift
952 may well merge into a subsequent insn. */
953 if (set_sign_bit_copies > 1)
956 (temp1 = ARM_SIGN_EXTEND (remainder
957 << (set_sign_bit_copies - 1))))
961 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
962 emit_insn (gen_rtx_SET (VOIDmode, new_src,
964 emit_insn (gen_ashrsi3 (target, new_src,
965 GEN_INT (set_sign_bit_copies - 1)));
969 /* For an inverted constant, we will need to set the low bits,
970 these will be shifted out of harm's way. */
971 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
972 if (const_ok_for_arm (~temp1))
976 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
977 emit_insn (gen_rtx_SET (VOIDmode, new_src,
979 emit_insn (gen_ashrsi3 (target, new_src,
980 GEN_INT (set_sign_bit_copies - 1)));
986 /* See if we can generate this by setting the bottom (or the top)
987 16 bits, and then shifting these into the other half of the
988 word. We only look for the simplest cases, to do more would cost
989 too much. Be careful, however, not to generate this when the
990 alternative would take fewer insns. */
991 if (val & 0xffff0000UL)
993 temp1 = remainder & 0xffff0000UL;
994 temp2 = remainder & 0x0000ffff;
996 /* Overlaps outside this range are best done using other methods. */
997 for (i = 9; i < 24; i++)
999 if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
1000 && ! const_ok_for_arm (temp2))
1002 rtx new_src = (subtargets
1003 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1005 insns = arm_gen_constant (code, mode, temp2, new_src,
1006 source, subtargets, generate);
1009 emit_insn (gen_rtx_SET
1012 gen_rtx_ASHIFT (mode, source,
1019 /* Don't duplicate cases already considered. */
1020 for (i = 17; i < 24; i++)
1022 if (((temp1 | (temp1 >> i)) == remainder)
1023 && ! const_ok_for_arm (temp1))
1025 rtx new_src = (subtargets
1026 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1028 insns = arm_gen_constant (code, mode, temp1, new_src,
1029 source, subtargets, generate);
1033 (gen_rtx_SET (VOIDmode, target,
1036 gen_rtx_LSHIFTRT (mode, source,
1047 /* If we have IOR or XOR, and the constant can be loaded in a
1048 single instruction, and we can find a temporary to put it in,
1049 then this can be done in two instructions instead of 3-4. */
1051 /* TARGET can't be NULL if SUBTARGETS is 0 */
1052 || (reload_completed && ! reg_mentioned_p (target, source)))
1054 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1058 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1060 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1061 emit_insn (gen_rtx_SET (VOIDmode, target,
1062 gen_rtx (code, mode, source, sub)));
1071 if (set_sign_bit_copies > 8
1072 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1076 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1077 rtx shift = GEN_INT (set_sign_bit_copies);
1079 emit_insn (gen_rtx_SET (VOIDmode, sub,
1081 gen_rtx_ASHIFT (mode,
1084 emit_insn (gen_rtx_SET (VOIDmode, target,
1086 gen_rtx_LSHIFTRT (mode, sub,
1092 if (set_zero_bit_copies > 8
1093 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1097 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1098 rtx shift = GEN_INT (set_zero_bit_copies);
1100 emit_insn (gen_rtx_SET (VOIDmode, sub,
1102 gen_rtx_LSHIFTRT (mode,
1105 emit_insn (gen_rtx_SET (VOIDmode, target,
1107 gen_rtx_ASHIFT (mode, sub,
1113 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1117 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1118 emit_insn (gen_rtx_SET (VOIDmode, sub,
1119 gen_rtx_NOT (mode, source)));
1122 sub = gen_reg_rtx (mode);
1123 emit_insn (gen_rtx_SET (VOIDmode, sub,
1124 gen_rtx_AND (mode, source,
1126 emit_insn (gen_rtx_SET (VOIDmode, target,
1127 gen_rtx_NOT (mode, sub)));
1134 /* See if two shifts will do 2 or more insn's worth of work. */
1135 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1137 HOST_WIDE_INT shift_mask = ((0xffffffffUL
1138 << (32 - clear_sign_bit_copies))
1141 if ((remainder | shift_mask) != 0xffffffffUL)
1145 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1146 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1147 new_src, source, subtargets, 1);
1152 rtx targ = subtargets ? NULL_RTX : target;
1153 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1154 targ, source, subtargets, 0);
1160 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1161 rtx shift = GEN_INT (clear_sign_bit_copies);
1163 emit_insn (gen_ashlsi3 (new_src, source, shift));
1164 emit_insn (gen_lshrsi3 (target, new_src, shift));
1170 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1172 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1174 if ((remainder | shift_mask) != 0xffffffffUL)
1178 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1180 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1181 new_src, source, subtargets, 1);
1186 rtx targ = subtargets ? NULL_RTX : target;
1188 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1189 targ, source, subtargets, 0);
1195 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1196 rtx shift = GEN_INT (clear_zero_bit_copies);
1198 emit_insn (gen_lshrsi3 (new_src, source, shift));
1199 emit_insn (gen_ashlsi3 (target, new_src, shift));
1211 for (i = 0; i < 32; i++)
1212 if (remainder & (1 << i))
1215 if (code == AND || (can_invert && num_bits_set > 16))
1216 remainder = (~remainder) & 0xffffffffUL;
1217 else if (code == PLUS && num_bits_set > 16)
1218 remainder = (-remainder) & 0xffffffffUL;
1225 /* Now try and find a way of doing the job in either two or three
1227 We start by looking for the largest block of zeros that are aligned on
1228 a 2-bit boundary, we then fill up the temps, wrapping around to the
1229 top of the word when we drop off the bottom.
1230 In the worst case this code should produce no more than four insns. */
1233 int best_consecutive_zeros = 0;
1235 for (i = 0; i < 32; i += 2)
1237 int consecutive_zeros = 0;
1239 if (! (remainder & (3 << i)))
1241 while ((i < 32) && ! (remainder & (3 << i)))
1243 consecutive_zeros += 2;
1246 if (consecutive_zeros > best_consecutive_zeros)
1248 best_consecutive_zeros = consecutive_zeros;
1249 best_start = i - consecutive_zeros;
1255 /* Now start emitting the insns, starting with the one with the highest
1256 bit set: we do this so that the smallest number will be emitted last;
1257 this is more likely to be combinable with addressing insns. */
1265 if (remainder & (3 << (i - 2)))
1270 temp1 = remainder & ((0x0ff << end)
1271 | ((i < end) ? (0xff >> (32 - end)) : 0));
1272 remainder &= ~temp1;
1279 emit_insn (gen_rtx_SET (VOIDmode,
1280 new_src = (subtargets
1281 ? gen_reg_rtx (mode)
1284 ? ~temp1 : temp1)));
1285 else if (code == MINUS)
1286 emit_insn (gen_rtx_SET (VOIDmode,
1287 new_src = (subtargets
1288 ? gen_reg_rtx (mode)
1290 gen_rtx (code, mode, GEN_INT (temp1),
1293 emit_insn (gen_rtx_SET (VOIDmode,
1294 new_src = (remainder
1296 ? gen_reg_rtx (mode)
1299 gen_rtx (code, mode, source,
1300 GEN_INT (can_invert ? ~temp1
1312 else if (code == MINUS)
1319 } while (remainder);
1324 /* Canonicalize a comparison so that we are more likely to recognize it.
1325 This can be done for a few constant compares, where we can make the
1326 immediate value easier to load. */
1328 arm_canonicalize_comparison (code, op1)
1332 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1342 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1344 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1346 *op1 = GEN_INT (i+1);
1347 return code == GT ? GE : LT;
1353 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1354 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1356 *op1 = GEN_INT (i-1);
1357 return code == GE ? GT : LE;
1363 if (i != ~((unsigned HOST_WIDE_INT) 0)
1364 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1366 *op1 = GEN_INT (i + 1);
1367 return code == GTU ? GEU : LTU;
1374 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1376 *op1 = GEN_INT (i - 1);
1377 return code == GEU ? GTU : LEU;
1388 /* Decide whether a type should be returned in memory (true)
1389 or in a register (false). This is called by the macro
1390 RETURN_IN_MEMORY. */
1392 arm_return_in_memory (type)
1395 if (! AGGREGATE_TYPE_P (type))
1396 /* All simple types are returned in registers. */
1399 if (int_size_in_bytes (type) > 4)
1400 /* All structures/unions bigger than one word are returned in memory. */
1403 if (TREE_CODE (type) == RECORD_TYPE)
1407 /* For a struct the APCS says that we only return in a register
1408 if the type is 'integer like' and every addressable element
1409 has an offset of zero. For practical purposes this means
1410 that the structure can have at most one non bit-field element
1411 and that this element must be the first one in the structure. */
1413 /* Find the first field, ignoring non FIELD_DECL things which will
1414 have been created by C++. */
1415 for (field = TYPE_FIELDS (type);
1416 field && TREE_CODE (field) != FIELD_DECL;
1417 field = TREE_CHAIN (field))
1421 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1423 /* Check that the first field is valid for returning in a register... */
1424 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1427 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1430 /* Now check the remaining fields, if any. Only bitfields are allowed,
1431 since they are not addressable. */
1432 for (field = TREE_CHAIN (field);
1434 field = TREE_CHAIN (field))
1436 if (TREE_CODE (field) != FIELD_DECL)
1439 if (! DECL_BIT_FIELD_TYPE (field))
1446 if (TREE_CODE (type) == UNION_TYPE)
1450 /* Unions can be returned in registers if every element is
1451 integral, or can be returned in an integer register. */
1452 for (field = TYPE_FIELDS (type);
1454 field = TREE_CHAIN (field))
1456 if (TREE_CODE (field) != FIELD_DECL)
1459 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1462 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1469 /* XXX Not sure what should be done for
1470 other aggregates so put them in memory. */
1474 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1475 for a call to a function whose data type is FNTYPE.
1476 For a library call, FNTYPE is NULL. */
1478 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1479 CUMULATIVE_ARGS * pcum;
1481 rtx libname ATTRIBUTE_UNUSED;
1482 int indirect ATTRIBUTE_UNUSED;
1484 /* On the ARM, the offset starts at 0. */
1485 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1487 pcum->call_cookie = CALL_NORMAL;
1489 if (TARGET_LONG_CALLS)
1490 pcum->call_cookie = CALL_LONG;
1492 /* Check for long call/short call attributes. The attributes
1493 override any command line option. */
1496 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1497 pcum->call_cookie = CALL_SHORT;
1498 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1499 pcum->call_cookie = CALL_LONG;
1503 /* Determine where to put an argument to a function.
1504 Value is zero to push the argument on the stack,
1505 or a hard register in which to store the argument.
1507 MODE is the argument's machine mode.
1508 TYPE is the data type of the argument (as a tree).
1509 This is null for libcalls where that information may
1511 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1512 the preceding args and about the function being called.
1513 NAMED is nonzero if this argument is a named parameter
1514 (otherwise it is an extra parameter matching an ellipsis). */
1516 arm_function_arg (pcum, mode, type, named)
1517 CUMULATIVE_ARGS * pcum;
1518 enum machine_mode mode;
1519 tree type ATTRIBUTE_UNUSED;
1522 if (mode == VOIDmode)
1523 /* Compute operand 2 of the call insn. */
1524 return GEN_INT (pcum->call_cookie);
1526 if (! named || pcum->nregs >= NUM_ARG_REGS)
1529 return gen_rtx_REG (mode, pcum->nregs);
1532 /* Encode the current state of the #pragma [no_]long_calls. */
1535 OFF, /* No #pramgma [no_]long_calls is in effect. */
1536 LONG, /* #pragma long_calls is in effect. */
1537 SHORT /* #pragma no_long_calls is in effect. */
1540 static arm_pragma_enum arm_pragma_long_calls = OFF;
1542 /* Handle pragmas for compatibility with Intel's compilers.
1543 FIXME: This is incomplete, since it does not handle all
1544 the pragmas that the Intel compilers understand. */
1546 arm_process_pragma (p_getc, p_ungetc, pname)
1547 int (* p_getc) PARAMS ((void)) ATTRIBUTE_UNUSED;
1548 void (* p_ungetc) PARAMS ((int)) ATTRIBUTE_UNUSED;
1551 /* Should be pragma 'far' or equivalent for callx/balx here. */
1552 if (strcmp (pname, "long_calls") == 0)
1553 arm_pragma_long_calls = LONG;
1554 else if (strcmp (pname, "no_long_calls") == 0)
1555 arm_pragma_long_calls = SHORT;
1556 else if (strcmp (pname, "long_calls_off") == 0)
1557 arm_pragma_long_calls = OFF;
1564 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1565 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1566 assigned to TYPE. */
1568 arm_valid_type_attribute_p (type, attributes, identifier, args)
1570 tree attributes ATTRIBUTE_UNUSED;
1574 if ( TREE_CODE (type) != FUNCTION_TYPE
1575 && TREE_CODE (type) != METHOD_TYPE
1576 && TREE_CODE (type) != FIELD_DECL
1577 && TREE_CODE (type) != TYPE_DECL)
1580 /* Function calls made to this symbol must be done indirectly, because
1581 it may lie outside of the 26 bit addressing range of a normal function
1583 if (is_attribute_p ("long_call", identifier))
1584 return (args == NULL_TREE);
1586 /* Whereas these functions are always known to reside within the 26 bit
1587 addressing range. */
1588 if (is_attribute_p ("short_call", identifier))
1589 return (args == NULL_TREE);
1594 /* Return 0 if the attributes for two types are incompatible, 1 if they
1595 are compatible, and 2 if they are nearly compatible (which causes a
1596 warning to be generated). */
1598 arm_comp_type_attributes (type1, type2)
1604 /* Check for mismatch of non-default calling convention. */
1605 if (TREE_CODE (type1) != FUNCTION_TYPE)
1608 /* Check for mismatched call attributes. */
1609 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1610 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1611 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1612 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1614 /* Only bother to check if an attribute is defined. */
1615 if (l1 | l2 | s1 | s2)
1617 /* If one type has an attribute, the other must have the same attribute. */
1618 if ((l1 != l2) || (s1 != s2))
1621 /* Disallow mixed attributes. */
1622 if ((l1 & s2) || (l2 & s1))
1629 /* Check the ARM specific attributes on the given function decl.
1630 If any of them would prevent the function from being inlined,
1631 return a tesxtual description of why not. Otherwise return NULL. */
1633 arm_function_attribute_inlineable_p (fndecl)
1636 if (lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (fndecl)))
1637 return "naked functions cannot be inlined";
1639 /* Allow functions with short_call and long_call attributes to be inlined. */
1643 /* Encode long_call or short_call attribute by prefixing
1644 symbol name in DECL with a special character FLAG. */
1646 arm_encode_call_attribute (decl, flag)
1650 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1651 int len = strlen (str);
1654 if (TREE_CODE (decl) != FUNCTION_DECL)
1657 /* Do not allow weak functions to be treated as short call. */
1658 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1662 newstr = ggc_alloc_string (NULL, len + 2);
1664 newstr = permalloc (len + 2);
1666 sprintf (newstr, "%c%s", flag, str);
1668 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1671 /* Assigns default attributes to newly defined type. This is used to
1672 set short_call/long_call attributes for function types of
1673 functions defined inside corresponding #pragma scopes. */
1675 arm_set_default_type_attributes (type)
1678 /* Add __attribute__ ((long_call)) to all functions, when
1679 inside #pragma long_calls or __attribute__ ((short_call)),
1680 when inside #pragma no_long_calls. */
1681 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
1683 tree type_attr_list, attr_name;
1684 type_attr_list = TYPE_ATTRIBUTES (type);
1686 if (arm_pragma_long_calls == LONG)
1687 attr_name = get_identifier ("long_call");
1688 else if (arm_pragma_long_calls == SHORT)
1689 attr_name = get_identifier ("short_call");
1693 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
1694 TYPE_ATTRIBUTES (type) = type_attr_list;
1698 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1699 defined within the current compilation unit. If this caanot be
1700 determined, then 0 is returned. */
1702 current_file_function_operand (sym_ref)
1705 /* This is a bit of a fib. A function will have a short call flag
1706 applied to its name if it has the short call attribute, or it has
1707 already been defined within the current compilation unit. */
1708 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
1711 /* The current funciton is always defined within the current compilation
1712 unit. if it s a weak defintion however, then this may not be the real
1713 defintion of the function, and so we have to say no. */
1714 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
1715 && ! DECL_WEAK (current_function_decl))
1718 /* We cannot make the determination - default to returning 0. */
1722 /* Return non-zero if a 32 bit "long_call" should be generated for
1723 this call. We generate a long_call if the function:
1725 a. has an __attribute__((long call))
1726 or b. is within the scope of a #pragma long_calls
1727 or c. the -mlong-calls command line switch has been specified
1729 However we do not generate a long call if the function:
1731 d. has an __attribute__ ((short_call))
1732 or e. is inside the scope of a #pragma no_long_calls
1733 or f. has an __attribute__ ((section))
1734 or g. is defined within the current compilation unit.
1736 This function will be called by C fragments contained in the machine
1737 description file. CALL_REF and CALL_COOKIE correspond to the matched
1738 rtl operands. CALL_SYMBOL is used to distinguish between
1739 two different callers of the function. It is set to 1 in the
1740 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1741 and "call_value" patterns. This is because of the difference in the
1742 SYM_REFs passed by these patterns. */
1744 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
1751 if (GET_CODE (sym_ref) != MEM)
1754 sym_ref = XEXP (sym_ref, 0);
1757 if (GET_CODE (sym_ref) != SYMBOL_REF)
1760 if (call_cookie & CALL_SHORT)
1763 if (TARGET_LONG_CALLS && flag_function_sections)
1766 if (current_file_function_operand (sym_ref, VOIDmode))
1769 return (call_cookie & CALL_LONG)
1770 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
1771 || TARGET_LONG_CALLS;
1775 legitimate_pic_operand_p (x)
1778 if (CONSTANT_P (x) && flag_pic
1779 && (GET_CODE (x) == SYMBOL_REF
1780 || (GET_CODE (x) == CONST
1781 && GET_CODE (XEXP (x, 0)) == PLUS
1782 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1789 legitimize_pic_address (orig, mode, reg)
1791 enum machine_mode mode;
1794 if (GET_CODE (orig) == SYMBOL_REF)
1796 rtx pic_ref, address;
1802 if (reload_in_progress || reload_completed)
1805 reg = gen_reg_rtx (Pmode);
1810 #ifdef AOF_ASSEMBLER
1811 /* The AOF assembler can generate relocations for these directly, and
1812 understands that the PIC register has to be added into the offset.
1814 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1817 address = gen_reg_rtx (Pmode);
1821 emit_insn (gen_pic_load_addr (address, orig));
1823 pic_ref = gen_rtx_MEM (Pmode,
1824 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1826 RTX_UNCHANGING_P (pic_ref) = 1;
1827 insn = emit_move_insn (reg, pic_ref);
1829 current_function_uses_pic_offset_table = 1;
1830 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1832 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1836 else if (GET_CODE (orig) == CONST)
1840 if (GET_CODE (XEXP (orig, 0)) == PLUS
1841 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1846 if (reload_in_progress || reload_completed)
1849 reg = gen_reg_rtx (Pmode);
1852 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1854 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1855 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1856 base == reg ? 0 : reg);
1861 if (GET_CODE (offset) == CONST_INT)
1863 /* The base register doesn't really matter, we only want to
1864 test the index for the appropriate mode. */
1865 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1867 if (! reload_in_progress && ! reload_completed)
1868 offset = force_reg (Pmode, offset);
1873 if (GET_CODE (offset) == CONST_INT)
1874 return plus_constant_for_output (base, INTVAL (offset));
1877 if (GET_MODE_SIZE (mode) > 4
1878 && (GET_MODE_CLASS (mode) == MODE_INT
1879 || TARGET_SOFT_FLOAT))
1881 emit_insn (gen_addsi3 (reg, base, offset));
1885 return gen_rtx_PLUS (Pmode, base, offset);
1887 else if (GET_CODE (orig) == LABEL_REF)
1889 current_function_uses_pic_offset_table = 1;
1893 rtx pic_ref, address = gen_reg_rtx (Pmode);
1895 emit_insn (gen_pic_load_addr (address, orig));
1896 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
1898 emit_move_insn (address, pic_ref);
1920 #ifndef AOF_ASSEMBLER
1921 rtx l1, pic_tmp, pic_tmp2, seq;
1922 rtx global_offset_table;
1924 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
1931 l1 = gen_label_rtx ();
1933 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1934 /* On the ARM the PC register contains 'dot + 8' at the time of the
1936 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1938 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1939 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1941 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1943 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1945 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1946 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1948 seq = gen_sequence ();
1950 emit_insn_after (seq, get_insns ());
1952 /* Need to emit this whether or not we obey regdecls,
1953 since setjmp/longjmp can cause life info to screw up. */
1954 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1955 #endif /* AOF_ASSEMBLER */
1958 #define REG_OR_SUBREG_REG(X) \
1959 (GET_CODE (X) == REG \
1960 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1962 #define REG_OR_SUBREG_RTX(X) \
1963 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1965 #define ARM_FRAME_RTX(X) \
1966 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1967 || (X) == arg_pointer_rtx)
1970 arm_rtx_costs (x, code)
1974 enum machine_mode mode = GET_MODE (x);
1975 enum rtx_code subcode;
1981 /* Memory costs quite a lot for the first word, but subsequent words
1982 load at the equivalent of a single insn each. */
1983 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1984 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1991 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1998 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2000 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2001 + ((GET_CODE (XEXP (x, 0)) == REG
2002 || (GET_CODE (XEXP (x, 0)) == SUBREG
2003 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2005 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2006 || (GET_CODE (XEXP (x, 0)) == SUBREG
2007 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2009 + ((GET_CODE (XEXP (x, 1)) == REG
2010 || (GET_CODE (XEXP (x, 1)) == SUBREG
2011 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2012 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2017 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2018 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2019 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2020 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2023 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2024 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2025 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2026 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2028 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2029 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2030 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2033 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2034 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2035 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2036 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2037 || subcode == ASHIFTRT || subcode == LSHIFTRT
2038 || subcode == ROTATE || subcode == ROTATERT
2040 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2041 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2042 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2043 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2044 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2045 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2046 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2051 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2052 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2053 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2054 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2055 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2059 case AND: case XOR: case IOR:
2062 /* Normally the frame registers will be spilt into reg+const during
2063 reload, so it is a bad idea to combine them with other instructions,
2064 since then they might not be moved outside of loops. As a compromise
2065 we allow integration with ops that have a constant as their second
2067 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2068 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2069 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2070 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2071 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2075 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2076 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2077 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2078 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2081 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2082 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2083 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2084 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2085 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2088 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2089 return (1 + extra_cost
2090 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2091 || subcode == LSHIFTRT || subcode == ASHIFTRT
2092 || subcode == ROTATE || subcode == ROTATERT
2094 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2095 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2096 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2097 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2098 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2099 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2105 /* There is no point basing this on the tuning, since it is always the
2106 fast variant if it exists at all */
2107 if (arm_fast_multiply && mode == DImode
2108 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2109 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2110 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2113 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2117 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2119 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2120 & (unsigned HOST_WIDE_INT) 0xffffffffUL);
2121 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2123 /* Tune as appropriate */
2124 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2126 for (j = 0; i && j < 32; j += booth_unit_size)
2128 i >>= booth_unit_size;
2135 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2136 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2137 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2140 if (arm_fast_multiply && mode == SImode
2141 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2142 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2143 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2144 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2145 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2146 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2151 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2152 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2156 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2158 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2161 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2169 return 4 + (mode == DImode ? 4 : 0);
2172 if (GET_MODE (XEXP (x, 0)) == QImode)
2173 return (4 + (mode == DImode ? 4 : 0)
2174 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2177 switch (GET_MODE (XEXP (x, 0)))
2180 return (1 + (mode == DImode ? 4 : 0)
2181 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2184 return (4 + (mode == DImode ? 4 : 0)
2185 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2188 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2201 arm_adjust_cost (insn, link, dep, cost)
2209 /* XXX This is not strictly true for the FPA. */
2210 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
2211 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
2214 if ((i_pat = single_set (insn)) != NULL
2215 && GET_CODE (SET_SRC (i_pat)) == MEM
2216 && (d_pat = single_set (dep)) != NULL
2217 && GET_CODE (SET_DEST (d_pat)) == MEM)
2219 /* This is a load after a store, there is no conflict if the load reads
2220 from a cached area. Assume that loads from the stack, and from the
2221 constant pool are cached, and that others will miss. This is a
2224 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2225 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2226 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2227 || reg_mentioned_p (hard_frame_pointer_rtx,
2228 XEXP (SET_SRC (i_pat), 0)))
2235 /* This code has been fixed for cross compilation. */
2237 static int fpa_consts_inited = 0;
2239 char * strings_fpa[8] =
2242 "4", "5", "0.5", "10"
2245 static REAL_VALUE_TYPE values_fpa[8];
2253 for (i = 0; i < 8; i++)
2255 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2259 fpa_consts_inited = 1;
2262 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2265 const_double_rtx_ok_for_fpu (x)
2271 if (!fpa_consts_inited)
2274 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2275 if (REAL_VALUE_MINUS_ZERO (r))
2278 for (i = 0; i < 8; i++)
2279 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2285 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2288 neg_const_double_rtx_ok_for_fpu (x)
2294 if (!fpa_consts_inited)
2297 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2298 r = REAL_VALUE_NEGATE (r);
2299 if (REAL_VALUE_MINUS_ZERO (r))
2302 for (i = 0; i < 8; i++)
2303 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2309 /* Predicates for `match_operand' and `match_operator'. */
2311 /* s_register_operand is the same as register_operand, but it doesn't accept
2314 This function exists because at the time it was put in it led to better
2315 code. SUBREG(MEM) always needs a reload in the places where
2316 s_register_operand is used, and this seemed to lead to excessive
2320 s_register_operand (op, mode)
2322 enum machine_mode mode;
2324 if (GET_MODE (op) != mode && mode != VOIDmode)
2327 if (GET_CODE (op) == SUBREG)
2328 op = SUBREG_REG (op);
2330 /* We don't consider registers whose class is NO_REGS
2331 to be a register operand. */
2332 return (GET_CODE (op) == REG
2333 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2334 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2337 /* Only accept reg, subreg(reg), const_int. */
2340 reg_or_int_operand (op, mode)
2342 enum machine_mode mode;
2344 if (GET_CODE (op) == CONST_INT)
2347 if (GET_MODE (op) != mode && mode != VOIDmode)
2350 if (GET_CODE (op) == SUBREG)
2351 op = SUBREG_REG (op);
2353 /* We don't consider registers whose class is NO_REGS
2354 to be a register operand. */
2355 return (GET_CODE (op) == REG
2356 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2357 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2360 /* Return 1 if OP is an item in memory, given that we are in reload. */
2363 reload_memory_operand (op, mode)
2365 enum machine_mode mode ATTRIBUTE_UNUSED;
2367 int regno = true_regnum (op);
2369 return (! CONSTANT_P (op)
2371 || (GET_CODE (op) == REG
2372 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2375 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2376 memory access (architecture V4) */
2378 bad_signed_byte_operand (op, mode)
2380 enum machine_mode mode;
2382 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2387 /* A sum of anything more complex than reg + reg or reg + const is bad */
2388 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2389 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2390 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2391 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2394 /* Big constants are also bad */
2395 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2396 && (INTVAL (XEXP (op, 1)) > 0xff
2397 || -INTVAL (XEXP (op, 1)) > 0xff))
2400 /* Everything else is good, or can will automatically be made so. */
2404 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2407 arm_rhs_operand (op, mode)
2409 enum machine_mode mode;
2411 return (s_register_operand (op, mode)
2412 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2415 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2419 arm_rhsm_operand (op, mode)
2421 enum machine_mode mode;
2423 return (s_register_operand (op, mode)
2424 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2425 || memory_operand (op, mode));
2428 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2429 constant that is valid when negated. */
2432 arm_add_operand (op, mode)
2434 enum machine_mode mode;
2436 return (s_register_operand (op, mode)
2437 || (GET_CODE (op) == CONST_INT
2438 && (const_ok_for_arm (INTVAL (op))
2439 || const_ok_for_arm (-INTVAL (op)))));
2443 arm_not_operand (op, mode)
2445 enum machine_mode mode;
2447 return (s_register_operand (op, mode)
2448 || (GET_CODE (op) == CONST_INT
2449 && (const_ok_for_arm (INTVAL (op))
2450 || const_ok_for_arm (~INTVAL (op)))));
2453 /* Return TRUE if the operand is a memory reference which contains an
2454 offsettable address. */
2456 offsettable_memory_operand (op, mode)
2458 enum machine_mode mode;
2460 if (mode == VOIDmode)
2461 mode = GET_MODE (op);
2463 return (mode == GET_MODE (op)
2464 && GET_CODE (op) == MEM
2465 && offsettable_address_p (reload_completed | reload_in_progress,
2466 mode, XEXP (op, 0)));
2469 /* Return TRUE if the operand is a memory reference which is, or can be
2470 made word aligned by adjusting the offset. */
2472 alignable_memory_operand (op, mode)
2474 enum machine_mode mode;
2478 if (mode == VOIDmode)
2479 mode = GET_MODE (op);
2481 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2486 return ((GET_CODE (reg = op) == REG
2487 || (GET_CODE (op) == SUBREG
2488 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2489 || (GET_CODE (op) == PLUS
2490 && GET_CODE (XEXP (op, 1)) == CONST_INT
2491 && (GET_CODE (reg = XEXP (op, 0)) == REG
2492 || (GET_CODE (XEXP (op, 0)) == SUBREG
2493 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2494 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2497 /* Similar to s_register_operand, but does not allow hard integer
2500 f_register_operand (op, mode)
2502 enum machine_mode mode;
2504 if (GET_MODE (op) != mode && mode != VOIDmode)
2507 if (GET_CODE (op) == SUBREG)
2508 op = SUBREG_REG (op);
2510 /* We don't consider registers whose class is NO_REGS
2511 to be a register operand. */
2512 return (GET_CODE (op) == REG
2513 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2514 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2517 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2520 fpu_rhs_operand (op, mode)
2522 enum machine_mode mode;
2524 if (s_register_operand (op, mode))
2527 if (GET_MODE (op) != mode && mode != VOIDmode)
2530 if (GET_CODE (op) == CONST_DOUBLE)
2531 return const_double_rtx_ok_for_fpu (op);
2537 fpu_add_operand (op, mode)
2539 enum machine_mode mode;
2541 if (s_register_operand (op, mode))
2544 if (GET_MODE (op) != mode && mode != VOIDmode)
2547 if (GET_CODE (op) == CONST_DOUBLE)
2548 return (const_double_rtx_ok_for_fpu (op)
2549 || neg_const_double_rtx_ok_for_fpu (op));
2554 /* Return nonzero if OP is a constant power of two. */
2557 power_of_two_operand (op, mode)
2559 enum machine_mode mode ATTRIBUTE_UNUSED;
2561 if (GET_CODE (op) == CONST_INT)
2563 HOST_WIDE_INT value = INTVAL(op);
2564 return value != 0 && (value & (value - 1)) == 0;
2569 /* Return TRUE for a valid operand of a DImode operation.
2570 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2571 Note that this disallows MEM(REG+REG), but allows
2572 MEM(PRE/POST_INC/DEC(REG)). */
2575 di_operand (op, mode)
2577 enum machine_mode mode;
2579 if (s_register_operand (op, mode))
2582 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2585 if (GET_CODE (op) == SUBREG)
2586 op = SUBREG_REG (op);
2588 switch (GET_CODE (op))
2595 return memory_address_p (DImode, XEXP (op, 0));
2602 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2603 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2604 Note that this disallows MEM(REG+REG), but allows
2605 MEM(PRE/POST_INC/DEC(REG)). */
2608 soft_df_operand (op, mode)
2610 enum machine_mode mode;
2612 if (s_register_operand (op, mode))
2615 if (mode != VOIDmode && GET_MODE (op) != mode)
2618 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
2621 if (GET_CODE (op) == SUBREG)
2622 op = SUBREG_REG (op);
2624 switch (GET_CODE (op))
2630 return memory_address_p (DFmode, XEXP (op, 0));
2637 /* Return TRUE for valid index operands. */
2640 index_operand (op, mode)
2642 enum machine_mode mode;
2644 return (s_register_operand(op, mode)
2645 || (immediate_operand (op, mode)
2646 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2649 /* Return TRUE for valid shifts by a constant. This also accepts any
2650 power of two on the (somewhat overly relaxed) assumption that the
2651 shift operator in this case was a mult. */
2654 const_shift_operand (op, mode)
2656 enum machine_mode mode;
2658 return (power_of_two_operand (op, mode)
2659 || (immediate_operand (op, mode)
2660 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2663 /* Return TRUE for arithmetic operators which can be combined with a multiply
2667 shiftable_operator (x, mode)
2669 enum machine_mode mode;
2671 if (GET_MODE (x) != mode)
2675 enum rtx_code code = GET_CODE (x);
2677 return (code == PLUS || code == MINUS
2678 || code == IOR || code == XOR || code == AND);
2682 /* Return TRUE for binary logical operators. */
2685 logical_binary_operator (x, mode)
2687 enum machine_mode mode;
2689 if (GET_MODE (x) != mode)
2693 enum rtx_code code = GET_CODE (x);
2695 return (code == IOR || code == XOR || code == AND);
2699 /* Return TRUE for shift operators. */
2702 shift_operator (x, mode)
2704 enum machine_mode mode;
2706 if (GET_MODE (x) != mode)
2710 enum rtx_code code = GET_CODE (x);
2713 return power_of_two_operand (XEXP (x, 1), mode);
2715 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2716 || code == ROTATERT);
2720 int equality_operator (x, mode)
2722 enum machine_mode mode ATTRIBUTE_UNUSED;
2724 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2727 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2730 minmax_operator (x, mode)
2732 enum machine_mode mode;
2734 enum rtx_code code = GET_CODE (x);
2736 if (GET_MODE (x) != mode)
2739 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2742 /* return TRUE if x is EQ or NE */
2744 /* Return TRUE if this is the condition code register, if we aren't given
2745 a mode, accept any class CCmode register */
2748 cc_register (x, mode)
2750 enum machine_mode mode;
2752 if (mode == VOIDmode)
2754 mode = GET_MODE (x);
2755 if (GET_MODE_CLASS (mode) != MODE_CC)
2759 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2765 /* Return TRUE if this is the condition code register, if we aren't given
2766 a mode, accept any class CCmode register which indicates a dominance
2770 dominant_cc_register (x, mode)
2772 enum machine_mode mode;
2774 if (mode == VOIDmode)
2776 mode = GET_MODE (x);
2777 if (GET_MODE_CLASS (mode) != MODE_CC)
2781 if (mode != CC_DNEmode && mode != CC_DEQmode
2782 && mode != CC_DLEmode && mode != CC_DLTmode
2783 && mode != CC_DGEmode && mode != CC_DGTmode
2784 && mode != CC_DLEUmode && mode != CC_DLTUmode
2785 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2788 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2794 /* Return TRUE if X references a SYMBOL_REF. */
2796 symbol_mentioned_p (x)
2799 register const char * fmt;
2802 if (GET_CODE (x) == SYMBOL_REF)
2805 fmt = GET_RTX_FORMAT (GET_CODE (x));
2806 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2812 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2813 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2816 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2823 /* Return TRUE if X references a LABEL_REF. */
2825 label_mentioned_p (x)
2828 register const char * fmt;
2831 if (GET_CODE (x) == LABEL_REF)
2834 fmt = GET_RTX_FORMAT (GET_CODE (x));
2835 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2841 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2842 if (label_mentioned_p (XVECEXP (x, i, j)))
2845 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2856 enum rtx_code code = GET_CODE (x);
2860 else if (code == SMIN)
2862 else if (code == UMIN)
2864 else if (code == UMAX)
2870 /* Return 1 if memory locations are adjacent */
2873 adjacent_mem_locations (a, b)
2876 int val0 = 0, val1 = 0;
2879 if ((GET_CODE (XEXP (a, 0)) == REG
2880 || (GET_CODE (XEXP (a, 0)) == PLUS
2881 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2882 && (GET_CODE (XEXP (b, 0)) == REG
2883 || (GET_CODE (XEXP (b, 0)) == PLUS
2884 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2886 if (GET_CODE (XEXP (a, 0)) == PLUS)
2888 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2889 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2892 reg0 = REGNO (XEXP (a, 0));
2893 if (GET_CODE (XEXP (b, 0)) == PLUS)
2895 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2896 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2899 reg1 = REGNO (XEXP (b, 0));
2900 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2905 /* Return 1 if OP is a load multiple operation. It is known to be
2906 parallel and the first section will be tested. */
2909 load_multiple_operation (op, mode)
2911 enum machine_mode mode ATTRIBUTE_UNUSED;
2913 HOST_WIDE_INT count = XVECLEN (op, 0);
2916 HOST_WIDE_INT i = 1, base = 0;
2920 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2923 /* Check to see if this might be a write-back */
2924 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2929 /* Now check it more carefully */
2930 if (GET_CODE (SET_DEST (elt)) != REG
2931 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2932 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2933 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2934 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2935 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2936 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2937 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2938 != REGNO (SET_DEST (elt)))
2944 /* Perform a quick check so we don't blow up below. */
2946 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2947 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2948 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2951 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2952 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2954 for (; i < count; i++)
2956 elt = XVECEXP (op, 0, i);
2958 if (GET_CODE (elt) != SET
2959 || GET_CODE (SET_DEST (elt)) != REG
2960 || GET_MODE (SET_DEST (elt)) != SImode
2961 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2962 || GET_CODE (SET_SRC (elt)) != MEM
2963 || GET_MODE (SET_SRC (elt)) != SImode
2964 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2965 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2966 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2967 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2974 /* Return 1 if OP is a store multiple operation. It is known to be
2975 parallel and the first section will be tested. */
2978 store_multiple_operation (op, mode)
2980 enum machine_mode mode ATTRIBUTE_UNUSED;
2982 HOST_WIDE_INT count = XVECLEN (op, 0);
2985 HOST_WIDE_INT i = 1, base = 0;
2989 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2992 /* Check to see if this might be a write-back */
2993 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2998 /* Now check it more carefully */
2999 if (GET_CODE (SET_DEST (elt)) != REG
3000 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3001 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3002 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3003 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
3004 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
3005 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
3006 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
3007 != REGNO (SET_DEST (elt)))
3013 /* Perform a quick check so we don't blow up below. */
3015 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3016 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3017 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3020 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3021 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3023 for (; i < count; i++)
3025 elt = XVECEXP (op, 0, i);
3027 if (GET_CODE (elt) != SET
3028 || GET_CODE (SET_SRC (elt)) != REG
3029 || GET_MODE (SET_SRC (elt)) != SImode
3030 || REGNO (SET_SRC (elt)) != src_regno + i - base
3031 || GET_CODE (SET_DEST (elt)) != MEM
3032 || GET_MODE (SET_DEST (elt)) != SImode
3033 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3034 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3035 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3036 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3044 load_multiple_sequence (operands, nops, regs, base, load_offset)
3049 HOST_WIDE_INT * load_offset;
3051 int unsorted_regs[4];
3052 HOST_WIDE_INT unsorted_offsets[4];
3057 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3058 extended if required. */
3059 if (nops < 2 || nops > 4)
3062 /* Loop over the operands and check that the memory references are
3063 suitable (ie immediate offsets from the same base register). At
3064 the same time, extract the target register, and the memory
3066 for (i = 0; i < nops; i++)
3071 /* Convert a subreg of a mem into the mem itself. */
3072 if (GET_CODE (operands[nops + i]) == SUBREG)
3073 operands[nops + i] = alter_subreg(operands[nops + i]);
3075 if (GET_CODE (operands[nops + i]) != MEM)
3078 /* Don't reorder volatile memory references; it doesn't seem worth
3079 looking for the case where the order is ok anyway. */
3080 if (MEM_VOLATILE_P (operands[nops + i]))
3083 offset = const0_rtx;
3085 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3086 || (GET_CODE (reg) == SUBREG
3087 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3088 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3089 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3091 || (GET_CODE (reg) == SUBREG
3092 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3093 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3098 base_reg = REGNO(reg);
3099 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3100 ? REGNO (operands[i])
3101 : REGNO (SUBREG_REG (operands[i])));
3106 if (base_reg != REGNO (reg))
3107 /* Not addressed from the same base register. */
3110 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3111 ? REGNO (operands[i])
3112 : REGNO (SUBREG_REG (operands[i])));
3113 if (unsorted_regs[i] < unsorted_regs[order[0]])
3117 /* If it isn't an integer register, or if it overwrites the
3118 base register but isn't the last insn in the list, then
3119 we can't do this. */
3120 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3121 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3124 unsorted_offsets[i] = INTVAL (offset);
3127 /* Not a suitable memory address. */
3131 /* All the useful information has now been extracted from the
3132 operands into unsorted_regs and unsorted_offsets; additionally,
3133 order[0] has been set to the lowest numbered register in the
3134 list. Sort the registers into order, and check that the memory
3135 offsets are ascending and adjacent. */
3137 for (i = 1; i < nops; i++)
3141 order[i] = order[i - 1];
3142 for (j = 0; j < nops; j++)
3143 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3144 && (order[i] == order[i - 1]
3145 || unsorted_regs[j] < unsorted_regs[order[i]]))
3148 /* Have we found a suitable register? if not, one must be used more
3150 if (order[i] == order[i - 1])
3153 /* Is the memory address adjacent and ascending? */
3154 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3162 for (i = 0; i < nops; i++)
3163 regs[i] = unsorted_regs[order[i]];
3165 *load_offset = unsorted_offsets[order[0]];
3168 if (unsorted_offsets[order[0]] == 0)
3169 return 1; /* ldmia */
3171 if (unsorted_offsets[order[0]] == 4)
3172 return 2; /* ldmib */
3174 if (unsorted_offsets[order[nops - 1]] == 0)
3175 return 3; /* ldmda */
3177 if (unsorted_offsets[order[nops - 1]] == -4)
3178 return 4; /* ldmdb */
3180 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3181 if the offset isn't small enough. The reason 2 ldrs are faster
3182 is because these ARMs are able to do more than one cache access
3183 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3184 whilst the ARM8 has a double bandwidth cache. This means that
3185 these cores can do both an instruction fetch and a data fetch in
3186 a single cycle, so the trick of calculating the address into a
3187 scratch register (one of the result regs) and then doing a load
3188 multiple actually becomes slower (and no smaller in code size).
3189 That is the transformation
3191 ldr rd1, [rbase + offset]
3192 ldr rd2, [rbase + offset + 4]
3196 add rd1, rbase, offset
3197 ldmia rd1, {rd1, rd2}
3199 produces worse code -- '3 cycles + any stalls on rd2' instead of
3200 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3201 access per cycle, the first sequence could never complete in less
3202 than 6 cycles, whereas the ldm sequence would only take 5 and
3203 would make better use of sequential accesses if not hitting the
3206 We cheat here and test 'arm_ld_sched' which we currently know to
3207 only be true for the ARM8, ARM9 and StrongARM. If this ever
3208 changes, then the test below needs to be reworked. */
3209 if (nops == 2 && arm_ld_sched)
3212 /* Can't do it without setting up the offset, only do this if it takes
3213 no more than one insn. */
3214 return (const_ok_for_arm (unsorted_offsets[order[0]])
3215 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3219 emit_ldm_seq (operands, nops)
3225 HOST_WIDE_INT offset;
3229 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3232 strcpy (buf, "ldm%?ia\t");
3236 strcpy (buf, "ldm%?ib\t");
3240 strcpy (buf, "ldm%?da\t");
3244 strcpy (buf, "ldm%?db\t");
3249 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3250 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3253 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3254 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3256 output_asm_insn (buf, operands);
3258 strcpy (buf, "ldm%?ia\t");
3265 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3266 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3268 for (i = 1; i < nops; i++)
3269 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3270 reg_names[regs[i]]);
3272 strcat (buf, "}\t%@ phole ldm");
3274 output_asm_insn (buf, operands);
3279 store_multiple_sequence (operands, nops, regs, base, load_offset)
3284 HOST_WIDE_INT * load_offset;
3286 int unsorted_regs[4];
3287 HOST_WIDE_INT unsorted_offsets[4];
3292 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3293 extended if required. */
3294 if (nops < 2 || nops > 4)
3297 /* Loop over the operands and check that the memory references are
3298 suitable (ie immediate offsets from the same base register). At
3299 the same time, extract the target register, and the memory
3301 for (i = 0; i < nops; i++)
3306 /* Convert a subreg of a mem into the mem itself. */
3307 if (GET_CODE (operands[nops + i]) == SUBREG)
3308 operands[nops + i] = alter_subreg(operands[nops + i]);
3310 if (GET_CODE (operands[nops + i]) != MEM)
3313 /* Don't reorder volatile memory references; it doesn't seem worth
3314 looking for the case where the order is ok anyway. */
3315 if (MEM_VOLATILE_P (operands[nops + i]))
3318 offset = const0_rtx;
3320 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3321 || (GET_CODE (reg) == SUBREG
3322 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3323 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3324 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3326 || (GET_CODE (reg) == SUBREG
3327 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3328 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3333 base_reg = REGNO (reg);
3334 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3335 ? REGNO (operands[i])
3336 : REGNO (SUBREG_REG (operands[i])));
3341 if (base_reg != REGNO (reg))
3342 /* Not addressed from the same base register. */
3345 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3346 ? REGNO (operands[i])
3347 : REGNO (SUBREG_REG (operands[i])));
3348 if (unsorted_regs[i] < unsorted_regs[order[0]])
3352 /* If it isn't an integer register, then we can't do this. */
3353 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3356 unsorted_offsets[i] = INTVAL (offset);
3359 /* Not a suitable memory address. */
3363 /* All the useful information has now been extracted from the
3364 operands into unsorted_regs and unsorted_offsets; additionally,
3365 order[0] has been set to the lowest numbered register in the
3366 list. Sort the registers into order, and check that the memory
3367 offsets are ascending and adjacent. */
3369 for (i = 1; i < nops; i++)
3373 order[i] = order[i - 1];
3374 for (j = 0; j < nops; j++)
3375 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3376 && (order[i] == order[i - 1]
3377 || unsorted_regs[j] < unsorted_regs[order[i]]))
3380 /* Have we found a suitable register? if not, one must be used more
3382 if (order[i] == order[i - 1])
3385 /* Is the memory address adjacent and ascending? */
3386 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3394 for (i = 0; i < nops; i++)
3395 regs[i] = unsorted_regs[order[i]];
3397 *load_offset = unsorted_offsets[order[0]];
3400 if (unsorted_offsets[order[0]] == 0)
3401 return 1; /* stmia */
3403 if (unsorted_offsets[order[0]] == 4)
3404 return 2; /* stmib */
3406 if (unsorted_offsets[order[nops - 1]] == 0)
3407 return 3; /* stmda */
3409 if (unsorted_offsets[order[nops - 1]] == -4)
3410 return 4; /* stmdb */
3416 emit_stm_seq (operands, nops)
3422 HOST_WIDE_INT offset;
3426 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3429 strcpy (buf, "stm%?ia\t");
3433 strcpy (buf, "stm%?ib\t");
3437 strcpy (buf, "stm%?da\t");
3441 strcpy (buf, "stm%?db\t");
3448 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3449 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3451 for (i = 1; i < nops; i++)
3452 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3453 reg_names[regs[i]]);
3455 strcat (buf, "}\t%@ phole stm");
3457 output_asm_insn (buf, operands);
3462 multi_register_push (op, mode)
3464 enum machine_mode mode ATTRIBUTE_UNUSED;
3466 if (GET_CODE (op) != PARALLEL
3467 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3468 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3469 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3476 /* Routines for use with attributes. */
3478 /* Return nonzero if ATTR is a valid attribute for DECL.
3479 ATTRIBUTES are any existing attributes and ARGS are
3480 the arguments supplied with ATTR.
3482 Supported attributes:
3484 naked: don't output any prologue or epilogue code,
3485 the user is assumed to do the right thing.
3488 arm_valid_machine_decl_attribute (decl, attr, args)
3493 if (args != NULL_TREE)
3496 if (is_attribute_p ("naked", attr))
3497 return TREE_CODE (decl) == FUNCTION_DECL;
3501 /* Return non-zero if FUNC is a naked function. */
3504 arm_naked_function_p (func)
3509 if (TREE_CODE (func) != FUNCTION_DECL)
3512 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3513 return a != NULL_TREE;
3516 /* Routines for use in generating RTL */
3519 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3520 in_struct_p, scalar_p)
3532 int sign = up ? 1 : -1;
3535 result = gen_rtx_PARALLEL (VOIDmode,
3536 rtvec_alloc (count + (write_back ? 2 : 0)));
3539 XVECEXP (result, 0, 0)
3540 = gen_rtx_SET (GET_MODE (from), from,
3541 plus_constant (from, count * 4 * sign));
3546 for (j = 0; i < count; i++, j++)
3548 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3549 RTX_UNCHANGING_P (mem) = unchanging_p;
3550 MEM_IN_STRUCT_P (mem) = in_struct_p;
3551 MEM_SCALAR_P (mem) = scalar_p;
3552 XVECEXP (result, 0, i)
3553 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3557 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3563 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3564 in_struct_p, scalar_p)
3576 int sign = up ? 1 : -1;
3579 result = gen_rtx_PARALLEL (VOIDmode,
3580 rtvec_alloc (count + (write_back ? 2 : 0)));
3583 XVECEXP (result, 0, 0)
3584 = gen_rtx_SET (GET_MODE (to), to,
3585 plus_constant (to, count * 4 * sign));
3590 for (j = 0; i < count; i++, j++)
3592 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3593 RTX_UNCHANGING_P (mem) = unchanging_p;
3594 MEM_IN_STRUCT_P (mem) = in_struct_p;
3595 MEM_SCALAR_P (mem) = scalar_p;
3597 XVECEXP (result, 0, i)
3598 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3602 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3608 arm_gen_movstrqi (operands)
3611 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3614 rtx st_src, st_dst, fin_src, fin_dst;
3615 rtx part_bytes_reg = NULL;
3617 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3618 int dst_scalar_p, src_scalar_p;
3620 if (GET_CODE (operands[2]) != CONST_INT
3621 || GET_CODE (operands[3]) != CONST_INT
3622 || INTVAL (operands[2]) > 64
3623 || INTVAL (operands[3]) & 3)
3626 st_dst = XEXP (operands[0], 0);
3627 st_src = XEXP (operands[1], 0);
3629 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3630 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3631 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3632 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3633 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3634 src_scalar_p = MEM_SCALAR_P (operands[1]);
3636 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3637 fin_src = src = copy_to_mode_reg (SImode, st_src);
3639 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3640 out_words_to_go = INTVAL (operands[2]) / 4;
3641 last_bytes = INTVAL (operands[2]) & 3;
3643 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3644 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3646 for (i = 0; in_words_to_go >= 2; i+=4)
3648 if (in_words_to_go > 4)
3649 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3654 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3655 FALSE, src_unchanging_p,
3656 src_in_struct_p, src_scalar_p));
3658 if (out_words_to_go)
3660 if (out_words_to_go > 4)
3661 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3665 else if (out_words_to_go != 1)
3666 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3675 mem = gen_rtx_MEM (SImode, dst);
3676 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3677 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3678 MEM_SCALAR_P (mem) = dst_scalar_p;
3679 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3680 if (last_bytes != 0)
3681 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3685 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3686 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3689 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3690 if (out_words_to_go)
3694 mem = gen_rtx_MEM (SImode, src);
3695 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3696 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3697 MEM_SCALAR_P (mem) = src_scalar_p;
3698 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3699 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3701 mem = gen_rtx_MEM (SImode, dst);
3702 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3703 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3704 MEM_SCALAR_P (mem) = dst_scalar_p;
3705 emit_move_insn (mem, sreg);
3706 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3709 if (in_words_to_go) /* Sanity check */
3715 if (in_words_to_go < 0)
3718 mem = gen_rtx_MEM (SImode, src);
3719 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3720 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3721 MEM_SCALAR_P (mem) = src_scalar_p;
3722 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3725 if (BYTES_BIG_ENDIAN && last_bytes)
3727 rtx tmp = gen_reg_rtx (SImode);
3729 if (part_bytes_reg == NULL)
3732 /* The bytes we want are in the top end of the word */
3733 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3734 GEN_INT (8 * (4 - last_bytes))));
3735 part_bytes_reg = tmp;
3739 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3740 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3741 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3742 MEM_SCALAR_P (mem) = dst_scalar_p;
3743 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3747 tmp = gen_reg_rtx (SImode);
3748 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3749 part_bytes_reg = tmp;
3758 if (part_bytes_reg == NULL)
3761 mem = gen_rtx_MEM (QImode, dst);
3762 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3763 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3764 MEM_SCALAR_P (mem) = dst_scalar_p;
3765 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3769 rtx tmp = gen_reg_rtx (SImode);
3771 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3772 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3773 part_bytes_reg = tmp;
3781 /* Generate a memory reference for a half word, such that it will be loaded
3782 into the top 16 bits of the word. We can assume that the address is
3783 known to be alignable and of the form reg, or plus (reg, const). */
3785 gen_rotated_half_load (memref)
3788 HOST_WIDE_INT offset = 0;
3789 rtx base = XEXP (memref, 0);
3791 if (GET_CODE (base) == PLUS)
3793 offset = INTVAL (XEXP (base, 1));
3794 base = XEXP (base, 0);
3797 /* If we aren't allowed to generate unaligned addresses, then fail. */
3798 if (TARGET_MMU_TRAPS
3799 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3802 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3804 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3807 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3810 static enum machine_mode
3811 select_dominance_cc_mode (x, y, cond_or)
3814 HOST_WIDE_INT cond_or;
3816 enum rtx_code cond1, cond2;
3819 /* Currently we will probably get the wrong result if the individual
3820 comparisons are not simple. This also ensures that it is safe to
3821 reverse a comparison if necessary. */
3822 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3824 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3829 cond1 = reverse_condition (cond1);
3831 /* If the comparisons are not equal, and one doesn't dominate the other,
3832 then we can't do this. */
3834 && ! comparison_dominates_p (cond1, cond2)
3835 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3840 enum rtx_code temp = cond1;
3848 if (cond2 == EQ || ! cond_or)
3853 case LE: return CC_DLEmode;
3854 case LEU: return CC_DLEUmode;
3855 case GE: return CC_DGEmode;
3856 case GEU: return CC_DGEUmode;
3863 if (cond2 == LT || ! cond_or)
3872 if (cond2 == GT || ! cond_or)
3881 if (cond2 == LTU || ! cond_or)
3890 if (cond2 == GTU || ! cond_or)
3898 /* The remaining cases only occur when both comparisons are the
3923 arm_select_cc_mode (op, x, y)
3928 /* All floating point compares return CCFP if it is an equality
3929 comparison, and CCFPE otherwise. */
3930 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3931 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3933 /* A compare with a shifted operand. Because of canonicalization, the
3934 comparison will have to be swapped when we emit the assembler. */
3935 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3936 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3937 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3938 || GET_CODE (x) == ROTATERT))
3941 /* This is a special case that is used by combine to allow a
3942 comparison of a shifted byte load to be split into a zero-extend
3943 followed by a comparison of the shifted integer (only valid for
3944 equalities and unsigned inequalities). */
3945 if (GET_MODE (x) == SImode
3946 && GET_CODE (x) == ASHIFT
3947 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3948 && GET_CODE (XEXP (x, 0)) == SUBREG
3949 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3950 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3951 && (op == EQ || op == NE
3952 || op == GEU || op == GTU || op == LTU || op == LEU)
3953 && GET_CODE (y) == CONST_INT)
3956 /* An operation that sets the condition codes as a side-effect, the
3957 V flag is not set correctly, so we can only use comparisons where
3958 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3960 if (GET_MODE (x) == SImode
3962 && (op == EQ || op == NE || op == LT || op == GE)
3963 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3964 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3965 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3966 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3967 || GET_CODE (x) == LSHIFTRT
3968 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3969 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3972 /* A construct for a conditional compare, if the false arm contains
3973 0, then both conditions must be true, otherwise either condition
3974 must be true. Not all conditions are possible, so CCmode is
3975 returned if it can't be done. */
3976 if (GET_CODE (x) == IF_THEN_ELSE
3977 && (XEXP (x, 2) == const0_rtx
3978 || XEXP (x, 2) == const1_rtx)
3979 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3980 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3981 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3982 INTVAL (XEXP (x, 2)));
3984 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3987 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3988 && GET_CODE (x) == PLUS
3989 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3995 /* X and Y are two things to compare using CODE. Emit the compare insn and
3996 return the rtx for register 0 in the proper mode. FP means this is a
3997 floating point compare: I don't think that it is needed on the arm. */
4000 gen_compare_reg (code, x, y)
4004 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4005 rtx cc_reg = gen_rtx_REG (mode, 24);
4007 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4008 gen_rtx_COMPARE (mode, x, y)));
4014 arm_reload_in_hi (operands)
4017 rtx ref = operands[1];
4019 HOST_WIDE_INT offset = 0;
4021 if (GET_CODE (ref) == SUBREG)
4023 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4024 if (BYTES_BIG_ENDIAN)
4025 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4026 - MIN (UNITS_PER_WORD,
4027 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4028 ref = SUBREG_REG (ref);
4031 if (GET_CODE (ref) == REG)
4033 /* We have a pseudo which has been spilt onto the stack; there
4034 are two cases here: the first where there is a simple
4035 stack-slot replacement and a second where the stack-slot is
4036 out of range, or is used as a subreg. */
4037 if (reg_equiv_mem[REGNO (ref)])
4039 ref = reg_equiv_mem[REGNO (ref)];
4040 base = find_replacement (&XEXP (ref, 0));
4043 /* The slot is out of range, or was dressed up in a SUBREG */
4044 base = reg_equiv_address[REGNO (ref)];
4047 base = find_replacement (&XEXP (ref, 0));
4049 /* Handle the case where the address is too complex to be offset by 1. */
4050 if (GET_CODE (base) == MINUS
4051 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4053 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4055 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4058 else if (GET_CODE (base) == PLUS)
4060 /* The addend must be CONST_INT, or we would have dealt with it above */
4061 HOST_WIDE_INT hi, lo;
4063 offset += INTVAL (XEXP (base, 1));
4064 base = XEXP (base, 0);
4066 /* Rework the address into a legal sequence of insns */
4067 /* Valid range for lo is -4095 -> 4095 */
4070 : -((-offset) & 0xfff));
4072 /* Corner case, if lo is the max offset then we would be out of range
4073 once we have added the additional 1 below, so bump the msb into the
4074 pre-loading insn(s). */
4078 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4079 ^ (HOST_WIDE_INT) 0x80000000UL)
4080 - (HOST_WIDE_INT) 0x80000000UL);
4082 if (hi + lo != offset)
4087 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4089 /* Get the base address; addsi3 knows how to handle constants
4090 that require more than one insn */
4091 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4097 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4098 emit_insn (gen_zero_extendqisi2 (scratch,
4099 gen_rtx_MEM (QImode,
4100 plus_constant (base,
4102 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4103 gen_rtx_MEM (QImode,
4104 plus_constant (base,
4106 if (! BYTES_BIG_ENDIAN)
4107 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4108 gen_rtx_IOR (SImode,
4111 gen_rtx_SUBREG (SImode, operands[0], 0),
4115 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4116 gen_rtx_IOR (SImode,
4117 gen_rtx_ASHIFT (SImode, scratch,
4119 gen_rtx_SUBREG (SImode, operands[0],
4123 /* Handle storing a half-word to memory during reload by synthesising as two
4124 byte stores. Take care not to clobber the input values until after we
4125 have moved them somewhere safe. This code assumes that if the DImode
4126 scratch in operands[2] overlaps either the input value or output address
4127 in some way, then that value must die in this insn (we absolutely need
4128 two scratch registers for some corner cases). */
4130 arm_reload_out_hi (operands)
4133 rtx ref = operands[0];
4134 rtx outval = operands[1];
4136 HOST_WIDE_INT offset = 0;
4138 if (GET_CODE (ref) == SUBREG)
4140 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4141 if (BYTES_BIG_ENDIAN)
4142 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4143 - MIN (UNITS_PER_WORD,
4144 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4145 ref = SUBREG_REG (ref);
4149 if (GET_CODE (ref) == REG)
4151 /* We have a pseudo which has been spilt onto the stack; there
4152 are two cases here: the first where there is a simple
4153 stack-slot replacement and a second where the stack-slot is
4154 out of range, or is used as a subreg. */
4155 if (reg_equiv_mem[REGNO (ref)])
4157 ref = reg_equiv_mem[REGNO (ref)];
4158 base = find_replacement (&XEXP (ref, 0));
4161 /* The slot is out of range, or was dressed up in a SUBREG */
4162 base = reg_equiv_address[REGNO (ref)];
4165 base = find_replacement (&XEXP (ref, 0));
4167 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4169 /* Handle the case where the address is too complex to be offset by 1. */
4170 if (GET_CODE (base) == MINUS
4171 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4173 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4175 /* Be careful not to destroy OUTVAL. */
4176 if (reg_overlap_mentioned_p (base_plus, outval))
4178 /* Updating base_plus might destroy outval, see if we can
4179 swap the scratch and base_plus. */
4180 if (! reg_overlap_mentioned_p (scratch, outval))
4183 scratch = base_plus;
4188 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4190 /* Be conservative and copy OUTVAL into the scratch now,
4191 this should only be necessary if outval is a subreg
4192 of something larger than a word. */
4193 /* XXX Might this clobber base? I can't see how it can,
4194 since scratch is known to overlap with OUTVAL, and
4195 must be wider than a word. */
4196 emit_insn (gen_movhi (scratch_hi, outval));
4197 outval = scratch_hi;
4201 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4204 else if (GET_CODE (base) == PLUS)
4206 /* The addend must be CONST_INT, or we would have dealt with it above */
4207 HOST_WIDE_INT hi, lo;
4209 offset += INTVAL (XEXP (base, 1));
4210 base = XEXP (base, 0);
4212 /* Rework the address into a legal sequence of insns */
4213 /* Valid range for lo is -4095 -> 4095 */
4216 : -((-offset) & 0xfff));
4218 /* Corner case, if lo is the max offset then we would be out of range
4219 once we have added the additional 1 below, so bump the msb into the
4220 pre-loading insn(s). */
4224 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4225 ^ (HOST_WIDE_INT) 0x80000000UL)
4226 - (HOST_WIDE_INT) 0x80000000UL);
4228 if (hi + lo != offset)
4233 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4235 /* Be careful not to destroy OUTVAL. */
4236 if (reg_overlap_mentioned_p (base_plus, outval))
4238 /* Updating base_plus might destroy outval, see if we
4239 can swap the scratch and base_plus. */
4240 if (! reg_overlap_mentioned_p (scratch, outval))
4243 scratch = base_plus;
4248 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4250 /* Be conservative and copy outval into scratch now,
4251 this should only be necessary if outval is a
4252 subreg of something larger than a word. */
4253 /* XXX Might this clobber base? I can't see how it
4254 can, since scratch is known to overlap with
4256 emit_insn (gen_movhi (scratch_hi, outval));
4257 outval = scratch_hi;
4261 /* Get the base address; addsi3 knows how to handle constants
4262 that require more than one insn */
4263 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4269 if (BYTES_BIG_ENDIAN)
4271 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4272 plus_constant (base, offset + 1)),
4273 gen_rtx_SUBREG (QImode, outval, 0)));
4274 emit_insn (gen_lshrsi3 (scratch,
4275 gen_rtx_SUBREG (SImode, outval, 0),
4277 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4278 gen_rtx_SUBREG (QImode, scratch, 0)));
4282 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4283 gen_rtx_SUBREG (QImode, outval, 0)));
4284 emit_insn (gen_lshrsi3 (scratch,
4285 gen_rtx_SUBREG (SImode, outval, 0),
4287 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4288 plus_constant (base, offset + 1)),
4289 gen_rtx_SUBREG (QImode, scratch, 0)));
4293 /* Routines for manipulation of the constant pool. */
4295 /* Arm instructions cannot load a large constant directly into a
4296 register; they have to come from a pc relative load. The constant
4297 must therefore be placed in the addressable range of the pc
4298 relative load. Depending on the precise pc relative load
4299 instruction the range is somewhere between 256 bytes and 4k. This
4300 means that we often have to dump a constant inside a function, and
4301 generate code to branch around it.
4303 It is important to minimize this, since the branches will slow
4304 things down and make the code larger.
4306 Normally we can hide the table after an existing unconditional
4307 branch so that there is no interruption of the flow, but in the
4308 worst case the code looks like this:
4326 We fix this by performing a scan after scheduling, which notices
4327 which instructions need to have their operands fetched from the
4328 constant table and builds the table.
4330 The algorithm starts by building a table of all the constants that
4331 need fixing up and all the natural barriers in the function (places
4332 where a constant table can be dropped without breaking the flow).
4333 For each fixup we note how far the pc-relative replacement will be
4334 able to reach and the offset of the instruction into the function.
4336 Having built the table we then group the fixes together to form
4337 tables that are as large as possible (subject to addressing
4338 constraints) and emit each table of constants after the last
4339 barrier that is within range of all the instructions in the group.
4340 If a group does not contain a barrier, then we forcibly create one
4341 by inserting a jump instruction into the flow. Once the table has
4342 been inserted, the insns are then modified to reference the
4343 relevant entry in the pool.
4345 Possible enhancements to the alogorithm (not implemented) are:
4347 1) ARM instructions (but not thumb) can use negative offsets, so we
4348 could reference back to a previous pool rather than forwards to a
4349 new one. For large functions this may reduce the number of pools
4352 2) For some processors and object formats, there may be benefit in
4353 aligning the pools to the start of cache lines; this alignment
4354 would need to be taken into account when calculating addressability
4361 rtx value; /* Value in table */
4362 HOST_WIDE_INT next_offset;
4363 enum machine_mode mode; /* Mode of value */
4366 /* The maximum number of constants that can fit into one pool, since
4367 the pc relative range is 0...4092 bytes and constants are at least 4
4370 #define MAX_MINIPOOL_SIZE (4092/4)
4371 static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
4372 static int minipool_size;
4373 static rtx minipool_vector_label;
4375 /* Add a constant to the pool and return its offset within the current
4378 X is the rtx we want to replace. MODE is its mode. On return,
4379 ADDRESS_ONLY will be non-zero if we really want the address of such
4380 a constant, not the constant itself. */
4381 static HOST_WIDE_INT
4382 add_minipool_constant (x, mode)
4384 enum machine_mode mode;
4387 HOST_WIDE_INT offset;
4389 /* First, see if we've already got it. */
4390 for (i = 0; i < minipool_size; i++)
4392 if (GET_CODE (x) == minipool_vector[i].value->code
4393 && mode == minipool_vector[i].mode)
4395 if (GET_CODE (x) == CODE_LABEL)
4397 if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
4400 if (rtx_equal_p (x, minipool_vector[i].value))
4401 return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
4405 /* Need a new one */
4406 minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
4408 if (minipool_size == 0)
4409 minipool_vector_label = gen_label_rtx ();
4411 minipool_vector[minipool_size].next_offset
4412 += (offset = minipool_vector[minipool_size - 1].next_offset);
4414 minipool_vector[minipool_size].value = x;
4415 minipool_vector[minipool_size].mode = mode;
4420 /* Output the literal table */
4422 dump_minipool (scan)
4427 scan = emit_label_after (gen_label_rtx (), scan);
4428 scan = emit_insn_after (gen_align_4 (), scan);
4429 scan = emit_label_after (minipool_vector_label, scan);
4431 for (i = 0; i < minipool_size; i++)
4433 minipool_node *p = minipool_vector + i;
4435 switch (GET_MODE_SIZE (p->mode))
4438 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4442 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4451 scan = emit_insn_after (gen_consttable_end (), scan);
4452 scan = emit_barrier_after (scan);
4456 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4459 find_barrier (from, max_count)
4464 rtx found_barrier = 0;
4467 while (from && count < max_count)
4471 if (GET_CODE (from) == BARRIER)
4472 found_barrier = from;
4474 /* Count the length of this insn */
4475 if (GET_CODE (from) == JUMP_INSN
4476 && JUMP_LABEL (from) != 0
4477 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4478 == next_real_insn (from))
4480 && GET_CODE (tmp) == JUMP_INSN
4481 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4482 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4484 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4485 count += (get_attr_length (from)
4486 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4487 /* Continue after the dispatch table. */
4489 from = NEXT_INSN (tmp);
4493 count += get_attr_length (from);
4496 from = NEXT_INSN (from);
4499 if (! found_barrier)
4501 /* We didn't find a barrier in time to
4502 dump our stuff, so we'll make one. */
4503 rtx label = gen_label_rtx ();
4506 from = PREV_INSN (last);
4508 from = get_last_insn ();
4510 /* Walk back to be just before any jump. */
4511 while (GET_CODE (from) == JUMP_INSN
4512 || GET_CODE (from) == NOTE
4513 || GET_CODE (from) == CODE_LABEL)
4514 from = PREV_INSN (from);
4516 from = emit_jump_insn_after (gen_jump (label), from);
4517 JUMP_LABEL (from) = label;
4518 found_barrier = emit_barrier_after (from);
4519 emit_label_after (label, found_barrier);
4522 return found_barrier;
4525 struct minipool_fixup
4527 struct minipool_fixup *next;
4531 enum machine_mode mode;
4536 struct minipool_fixup *minipool_fix_head;
4537 struct minipool_fixup *minipool_fix_tail;
4540 push_minipool_barrier (insn, address)
4544 struct minipool_fixup *fix
4545 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4548 fix->address = address;
4551 if (minipool_fix_head != NULL)
4552 minipool_fix_tail->next = fix;
4554 minipool_fix_head = fix;
4556 minipool_fix_tail = fix;
4560 push_minipool_fix (insn, address, loc, mode, value)
4564 enum machine_mode mode;
4567 struct minipool_fixup *fix
4568 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4570 #ifdef AOF_ASSEMBLER
4571 /* PIC symbol refereneces need to be converted into offsets into the
4573 if (flag_pic && GET_MODE == SYMBOL_REF)
4574 value = aof_pic_entry (value);
4575 #endif /* AOF_ASSEMBLER */
4578 fix->address = address;
4582 fix->range = get_attr_pool_range (insn);
4584 /* If an insn doesn't have a range defined for it, then it isn't
4585 expecting to be reworked by this code. Better to abort now than
4586 to generate duff assembly code. */
4587 if (fix->range == 0)
4590 /* Add it to the chain of fixes */
4592 if (minipool_fix_head != NULL)
4593 minipool_fix_tail->next = fix;
4595 minipool_fix_head = fix;
4597 minipool_fix_tail = fix;
4601 note_invalid_constants (insn, address)
4607 /* Extract the operands of the insn */
4610 /* Find the alternative selected */
4611 if (! constrain_operands (1))
4612 fatal_insn_not_found (insn);
4614 /* Preprocess the constraints, to extract some useful information. */
4615 preprocess_constraints ();
4617 for (opno = 0; opno < recog_data.n_operands; opno++)
4619 /* Things we need to fix can only occur in inputs */
4620 if (recog_data.operand_type[opno] != OP_IN)
4623 /* If this alternative is a memory reference, then any mention
4624 of constants in this alternative is really to fool reload
4625 into allowing us to accept one there. We need to fix them up
4626 now so that we output the right code. */
4627 if (recog_op_alt[opno][which_alternative].memory_ok)
4629 rtx op = recog_data.operand[opno];
4631 if (CONSTANT_P (op))
4632 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4633 recog_data.operand_mode[opno], op);
4634 #ifndef AOF_ASSEMBLER
4635 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
4636 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4637 recog_data.operand_mode[opno],
4638 XVECEXP (op, 0, 0));
4640 else if (recog_data.operand_mode[opno] == SImode
4641 && GET_CODE (op) == MEM
4642 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
4643 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4644 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4645 recog_data.operand_mode[opno],
4646 get_pool_constant (XEXP (op, 0)));
4657 struct minipool_fixup *fix;
4659 minipool_fix_head = minipool_fix_tail = NULL;
4661 /* The first insn must always be a note, or the code below won't
4662 scan it properly. */
4663 if (GET_CODE (first) != NOTE)
4666 /* Scan all the insns and record the operands that will need fixing. */
4667 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
4670 if (GET_CODE (insn) == BARRIER)
4671 push_minipool_barrier(insn, address);
4672 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
4673 || GET_CODE (insn) == JUMP_INSN)
4677 note_invalid_constants (insn, address);
4678 address += get_attr_length (insn);
4679 /* If the insn is a vector jump, add the size of the table
4680 and skip the table. */
4681 if (GET_CODE (insn) == JUMP_INSN
4682 && JUMP_LABEL (insn) != NULL
4683 && ((table = next_real_insn (JUMP_LABEL (insn)))
4684 == next_real_insn (insn))
4686 && GET_CODE (table) == JUMP_INSN
4687 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4688 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4690 int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
4692 address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
4699 /* Now scan the fixups and perform the required changes. */
4700 for (fix = minipool_fix_head; fix; fix = fix->next)
4702 struct minipool_fixup *ftmp;
4703 struct minipool_fixup *last_barrier = NULL;
4706 struct minipool_fixup *this_fix;
4707 int new_minipool_size = 0;
4709 /* Skip any further barriers before the next fix. */
4710 while (fix && GET_CODE (fix->insn) == BARRIER)
4717 max_range = fix->address + fix->range;
4719 /* Find all the other fixes that can live in the same pool. */
4720 while (ftmp->next && ftmp->next->address < max_range
4721 && (GET_CODE (ftmp->next->insn) == BARRIER
4722 /* Ensure we can reach the constant inside the pool. */
4723 || ftmp->next->range > new_minipool_size))
4726 if (GET_CODE (ftmp->insn) == BARRIER)
4727 last_barrier = ftmp;
4730 /* Does this fix constrain the range we can search? */
4731 if (ftmp->address + ftmp->range - new_minipool_size < max_range)
4732 max_range = ftmp->address + ftmp->range - new_minipool_size;
4734 new_minipool_size += GET_MODE_SIZE (ftmp->mode);
4738 /* If we found a barrier, drop back to that; any fixes that we could
4739 have reached but come after the barrier will now go in the next
4741 if (last_barrier != NULL)
4743 barrier = last_barrier->insn;
4744 ftmp = last_barrier;
4746 /* ftmp is last fix that we can fit into this pool and we
4747 failed to find a barrier that we could use. Insert a new
4748 barrier in the code and arrange to jump around it. */
4751 /* Check that there isn't another fix that is in range that
4752 we couldn't fit into this pool because the pool was
4753 already too large: we need to put the pool before such an
4755 if (ftmp->next && ftmp->next->address < max_range)
4756 max_range = ftmp->address;
4758 barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
4761 /* Scan over the fixes we have identified for this pool, fixing them
4762 up and adding the constants to the pool itself. */
4763 for (this_fix = fix; this_fix && ftmp->next != this_fix;
4764 this_fix = this_fix->next)
4765 if (GET_CODE (this_fix->insn) != BARRIER)
4767 int offset = add_minipool_constant (this_fix->value,
4770 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4771 minipool_vector_label),
4773 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
4776 dump_minipool (barrier);
4780 /* From now on we must synthesize any constants that we can't handle
4781 directly. This can happen if the RTL gets split during final
4782 instruction generation. */
4783 after_arm_reorg = 1;
4787 /* Routines to output assembly language. */
4789 /* If the rtx is the correct value then return the string of the number.
4790 In this way we can ensure that valid double constants are generated even
4791 when cross compiling. */
4793 fp_immediate_constant (x)
4799 if (!fpa_consts_inited)
4802 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4803 for (i = 0; i < 8; i++)
4804 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4805 return strings_fpa[i];
4810 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4812 fp_const_from_val (r)
4813 REAL_VALUE_TYPE * r;
4817 if (! fpa_consts_inited)
4820 for (i = 0; i < 8; i++)
4821 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4822 return strings_fpa[i];
4827 /* Output the operands of a LDM/STM instruction to STREAM.
4828 MASK is the ARM register set mask of which only bits 0-15 are important.
4829 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4830 must follow the register list. */
4833 print_multi_reg (stream, instr, reg, mask, hat)
4841 int not_first = FALSE;
4843 fputc ('\t', stream);
4844 asm_fprintf (stream, instr, reg);
4845 fputs (", {", stream);
4847 for (i = 0; i < 16; i++)
4848 if (mask & (1 << i))
4851 fprintf (stream, ", ");
4853 asm_fprintf (stream, "%r", i);
4857 fprintf (stream, "}%s\n", hat ? "^" : "");
4860 /* Output a 'call' insn. */
4863 output_call (operands)
4866 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4868 if (REGNO (operands[0]) == LR_REGNUM)
4870 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
4871 output_asm_insn ("mov%?\t%0, %|lr", operands);
4874 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4876 if (TARGET_INTERWORK)
4877 output_asm_insn ("bx%?\t%0", operands);
4879 output_asm_insn ("mov%?\t%|pc, %0", operands);
4888 int something_changed = 0;
4890 int code = GET_CODE (x0);
4892 register const char * fmt;
4897 if (REGNO (x0) == LR_REGNUM)
4899 *x = gen_rtx_REG (SImode, IP_REGNUM);
4904 /* Scan through the sub-elements and change any references there */
4905 fmt = GET_RTX_FORMAT (code);
4907 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4909 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4910 else if (fmt[i] == 'E')
4911 for (j = 0; j < XVECLEN (x0, i); j++)
4912 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4914 return something_changed;
4918 /* Output a 'call' insn that is a reference in memory. */
4921 output_call_mem (operands)
4924 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4925 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4927 if (eliminate_lr2ip (&operands[0]))
4928 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4930 if (TARGET_INTERWORK)
4932 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4933 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4934 output_asm_insn ("bx%?\t%|ip", operands);
4938 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4939 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4946 /* Output a move from arm registers to an fpu registers.
4947 OPERANDS[0] is an fpu register.
4948 OPERANDS[1] is the first registers of an arm register pair. */
4951 output_mov_long_double_fpu_from_arm (operands)
4954 int arm_reg0 = REGNO (operands[1]);
4957 if (arm_reg0 == IP_REGNUM)
4960 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4961 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4962 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4964 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4965 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4970 /* Output a move from an fpu register to arm registers.
4971 OPERANDS[0] is the first registers of an arm register pair.
4972 OPERANDS[1] is an fpu register. */
4975 output_mov_long_double_arm_from_fpu (operands)
4978 int arm_reg0 = REGNO (operands[0]);
4981 if (arm_reg0 == IP_REGNUM)
4984 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4985 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4986 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4988 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4989 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4993 /* Output a move from arm registers to arm registers of a long double
4994 OPERANDS[0] is the destination.
4995 OPERANDS[1] is the source. */
4997 output_mov_long_double_arm_from_arm (operands)
5000 /* We have to be careful here because the two might overlap */
5001 int dest_start = REGNO (operands[0]);
5002 int src_start = REGNO (operands[1]);
5006 if (dest_start < src_start)
5008 for (i = 0; i < 3; i++)
5010 ops[0] = gen_rtx_REG (SImode, dest_start + i);
5011 ops[1] = gen_rtx_REG (SImode, src_start + i);
5012 output_asm_insn ("mov%?\t%0, %1", ops);
5017 for (i = 2; i >= 0; i--)
5019 ops[0] = gen_rtx_REG (SImode, dest_start + i);
5020 ops[1] = gen_rtx_REG (SImode, src_start + i);
5021 output_asm_insn ("mov%?\t%0, %1", ops);
5029 /* Output a move from arm registers to an fpu registers.
5030 OPERANDS[0] is an fpu register.
5031 OPERANDS[1] is the first registers of an arm register pair. */
5034 output_mov_double_fpu_from_arm (operands)
5037 int arm_reg0 = REGNO (operands[1]);
5040 if (arm_reg0 == IP_REGNUM)
5043 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5044 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5045 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
5046 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
5050 /* Output a move from an fpu register to arm registers.
5051 OPERANDS[0] is the first registers of an arm register pair.
5052 OPERANDS[1] is an fpu register. */
5055 output_mov_double_arm_from_fpu (operands)
5058 int arm_reg0 = REGNO (operands[0]);
5061 if (arm_reg0 == IP_REGNUM)
5064 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5065 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5066 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
5067 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
5071 /* Output a move between double words.
5072 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
5073 or MEM<-REG and all MEMs must be offsettable addresses. */
5076 output_move_double (operands)
5079 enum rtx_code code0 = GET_CODE (operands[0]);
5080 enum rtx_code code1 = GET_CODE (operands[1]);
5085 int reg0 = REGNO (operands[0]);
5087 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
5091 int reg1 = REGNO (operands[1]);
5092 if (reg1 == IP_REGNUM)
5095 /* Ensure the second source is not overwritten */
5096 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
5097 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
5099 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
5101 else if (code1 == CONST_DOUBLE)
5103 if (GET_MODE (operands[1]) == DFmode)
5106 union real_extract u;
5108 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
5110 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
5111 otherops[1] = GEN_INT(l[1]);
5112 operands[1] = GEN_INT(l[0]);
5114 else if (GET_MODE (operands[1]) != VOIDmode)
5116 else if (WORDS_BIG_ENDIAN)
5119 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5120 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5125 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5126 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5129 output_mov_immediate (operands);
5130 output_mov_immediate (otherops);
5132 else if (code1 == CONST_INT)
5134 #if HOST_BITS_PER_WIDE_INT > 32
5135 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5136 what the upper word is. */
5137 if (WORDS_BIG_ENDIAN)
5139 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5140 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5144 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5145 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5148 /* Sign extend the intval into the high-order word */
5149 if (WORDS_BIG_ENDIAN)
5151 otherops[1] = operands[1];
5152 operands[1] = (INTVAL (operands[1]) < 0
5153 ? constm1_rtx : const0_rtx);
5156 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
5158 output_mov_immediate (otherops);
5159 output_mov_immediate (operands);
5161 else if (code1 == MEM)
5163 switch (GET_CODE (XEXP (operands[1], 0)))
5166 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
5170 abort (); /* Should never happen now */
5174 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
5178 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
5182 abort (); /* Should never happen now */
5187 output_asm_insn ("adr%?\t%0, %1", operands);
5188 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
5192 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
5193 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
5195 otherops[0] = operands[0];
5196 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
5197 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
5198 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
5200 if (GET_CODE (otherops[2]) == CONST_INT)
5202 switch (INTVAL (otherops[2]))
5205 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
5208 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
5211 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
5214 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
5215 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
5217 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5220 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5223 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
5225 return "ldm%?ia\t%0, %M0";
5229 otherops[1] = adj_offsettable_operand (operands[1], 4);
5230 /* Take care of overlapping base/data reg. */
5231 if (reg_mentioned_p (operands[0], operands[1]))
5233 output_asm_insn ("ldr%?\t%0, %1", otherops);
5234 output_asm_insn ("ldr%?\t%0, %1", operands);
5238 output_asm_insn ("ldr%?\t%0, %1", operands);
5239 output_asm_insn ("ldr%?\t%0, %1", otherops);
5245 abort (); /* Constraints should prevent this */
5247 else if (code0 == MEM && code1 == REG)
5249 if (REGNO (operands[1]) == IP_REGNUM)
5252 switch (GET_CODE (XEXP (operands[0], 0)))
5255 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
5259 abort (); /* Should never happen now */
5263 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
5267 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
5271 abort (); /* Should never happen now */
5275 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
5277 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
5280 output_asm_insn ("stm%?db\t%m0, %M1", operands);
5284 output_asm_insn ("stm%?da\t%m0, %M1", operands);
5288 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
5295 otherops[0] = adj_offsettable_operand (operands[0], 4);
5296 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
5297 output_asm_insn ("str%?\t%1, %0", operands);
5298 output_asm_insn ("str%?\t%1, %0", otherops);
5302 abort (); /* Constraints should prevent this */
5308 /* Output an arbitrary MOV reg, #n.
5309 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
5312 output_mov_immediate (operands)
5315 HOST_WIDE_INT n = INTVAL (operands[1]);
5319 /* Try to use one MOV */
5320 if (const_ok_for_arm (n))
5322 output_asm_insn ("mov%?\t%0, %1", operands);
5326 /* Try to use one MVN */
5327 if (const_ok_for_arm (~n))
5329 operands[1] = GEN_INT (~n);
5330 output_asm_insn ("mvn%?\t%0, %1", operands);
5334 /* If all else fails, make it out of ORRs or BICs as appropriate. */
5336 for (i=0; i < 32; i++)
5340 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
5341 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5344 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5351 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5352 adding zero to one register, output nothing. */
5355 output_add_immediate (operands)
5358 HOST_WIDE_INT n = INTVAL (operands[2]);
5360 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
5363 output_multi_immediate (operands,
5364 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5367 output_multi_immediate (operands,
5368 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5375 /* Output a multiple immediate operation.
5376 OPERANDS is the vector of operands referred to in the output patterns.
5377 INSTR1 is the output pattern to use for the first constant.
5378 INSTR2 is the output pattern to use for subsequent constants.
5379 IMMED_OP is the index of the constant slot in OPERANDS.
5380 N is the constant value. */
5383 output_multi_immediate (operands, instr1, instr2, immed_op, n)
5385 char * instr1, * instr2;
5389 #if HOST_BITS_PER_WIDE_INT > 32
5395 operands[immed_op] = const0_rtx;
5396 output_asm_insn (instr1, operands); /* Quick and easy output */
5401 char *instr = instr1;
5403 /* Note that n is never zero here (which would give no output) */
5404 for (i = 0; i < 32; i += 2)
5408 operands[immed_op] = GEN_INT (n & (255 << i));
5409 output_asm_insn (instr, operands);
5419 /* Return the appropriate ARM instruction for the operation code.
5420 The returned result should not be overwritten. OP is the rtx of the
5421 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5425 arithmetic_instr (op, shift_first_arg)
5427 int shift_first_arg;
5429 switch (GET_CODE (op))
5435 return shift_first_arg ? "rsb" : "sub";
5452 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5453 for the operation code. The returned result should not be overwritten.
5454 OP is the rtx code of the shift.
5455 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5459 shift_op (op, amountp)
5461 HOST_WIDE_INT *amountp;
5464 enum rtx_code code = GET_CODE (op);
5466 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5468 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5469 *amountp = INTVAL (XEXP (op, 1));
5492 /* We never have to worry about the amount being other than a
5493 power of 2, since this case can never be reloaded from a reg. */
5495 *amountp = int_log2 (*amountp);
5506 /* This is not 100% correct, but follows from the desire to merge
5507 multiplication by a power of 2 with the recognizer for a
5508 shift. >=32 is not a valid shift for "asl", so we must try and
5509 output a shift that produces the correct arithmetical result.
5510 Using lsr #32 is identical except for the fact that the carry bit
5511 is not set correctly if we set the flags; but we never use the
5512 carry bit from such an operation, so we can ignore that. */
5513 if (code == ROTATERT)
5514 *amountp &= 31; /* Rotate is just modulo 32 */
5515 else if (*amountp != (*amountp & 31))
5522 /* Shifts of 0 are no-ops. */
5531 /* Obtain the shift from the POWER of two. */
5533 static HOST_WIDE_INT
5535 HOST_WIDE_INT power;
5537 HOST_WIDE_INT shift = 0;
5539 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5549 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5550 /bin/as is horribly restrictive. */
5551 #define MAX_ASCII_LEN 51
5554 output_ascii_pseudo_op (stream, p, len)
5556 const unsigned char * p;
5562 fputs ("\t.ascii\t\"", stream);
5564 for (i = 0; i < len; i++)
5566 register int c = p[i];
5568 if (len_so_far >= MAX_ASCII_LEN)
5570 fputs ("\"\n\t.ascii\t\"", stream);
5577 fputs ("\\t", stream);
5582 fputs ("\\f", stream);
5587 fputs ("\\b", stream);
5592 fputs ("\\r", stream);
5596 case TARGET_NEWLINE:
5597 fputs ("\\n", stream);
5599 if ((c >= ' ' && c <= '~')
5601 /* This is a good place for a line break. */
5602 len_so_far = MAX_ASCII_LEN;
5609 putc ('\\', stream);
5614 if (c >= ' ' && c <= '~')
5621 fprintf (stream, "\\%03o", c);
5628 fputs ("\"\n", stream);
5632 /* Try to determine whether a pattern really clobbers the link register.
5633 This information is useful when peepholing, so that lr need not be pushed
5634 if we combine a call followed by a return.
5635 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5636 such a check should not be needed because these only update an existing
5637 value within a register; the register must still be set elsewhere within
5641 pattern_really_clobbers_lr (x)
5646 switch (GET_CODE (x))
5649 switch (GET_CODE (SET_DEST (x)))
5652 return REGNO (SET_DEST (x)) == LR_REGNUM;
5655 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5656 return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
5658 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5667 for (i = 0; i < XVECLEN (x, 0); i++)
5668 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5673 switch (GET_CODE (XEXP (x, 0)))
5676 return REGNO (XEXP (x, 0)) == LR_REGNUM;
5679 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5680 return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
5696 function_really_clobbers_lr (first)
5701 for (insn = first; insn; insn = next_nonnote_insn (insn))
5703 switch (GET_CODE (insn))
5708 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5712 if (pattern_really_clobbers_lr (PATTERN (insn)))
5717 /* Don't yet know how to handle those calls that are not to a
5719 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5722 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5725 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5731 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5737 default: /* Don't recognize it, be safe */
5741 /* A call can be made (by peepholing) not to clobber lr iff it is
5742 followed by a return. There may, however, be a use insn iff
5743 we are returning the result of the call.
5744 If we run off the end of the insn chain, then that means the
5745 call was at the end of the function. Unfortunately we don't
5746 have a return insn for the peephole to recognize, so we
5747 must reject this. (Can this be fixed by adding our own insn?) */
5748 if ((next = next_nonnote_insn (insn)) == NULL)
5751 /* No need to worry about lr if the call never returns */
5752 if (GET_CODE (next) == BARRIER)
5755 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5756 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5757 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5758 == REGNO (XEXP (PATTERN (next), 0))))
5759 if ((next = next_nonnote_insn (next)) == NULL)
5762 if (GET_CODE (next) == JUMP_INSN
5763 && GET_CODE (PATTERN (next)) == RETURN)
5772 /* We have reached the end of the chain so lr was _not_ clobbered */
5777 output_return_instruction (operand, really_return, reverse)
5783 int reg, live_regs = 0;
5784 int volatile_func = (optimize > 0
5785 && TREE_THIS_VOLATILE (current_function_decl));
5787 return_used_this_function = 1;
5789 if (TARGET_ABORT_NORETURN && volatile_func)
5791 /* If this function was declared non-returning, and we have found a tail
5792 call, then we have to trust that the called function won't return. */
5797 /* Otherwise, trap an attempted return by aborting. */
5799 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
5801 assemble_external_libcall (ops[1]);
5802 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5808 if (current_function_calls_alloca && ! really_return)
5811 for (reg = 0; reg <= 10; reg++)
5812 if (regs_ever_live[reg] && ! call_used_regs[reg])
5815 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5816 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5819 if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
5822 if (frame_pointer_needed)
5825 /* On some ARM architectures it is faster to use LDR rather than LDM to
5826 load a single register. On other architectures, the cost is the same. */
5828 && regs_ever_live[LR_REGNUM]
5829 && ! lr_save_eliminated
5830 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
5831 really_return is true, and only the PC needs restoring. */
5834 output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
5835 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
5839 if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
5842 if (frame_pointer_needed)
5844 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5847 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5849 for (reg = 0; reg <= 10; reg++)
5850 if (regs_ever_live[reg]
5851 && (! call_used_regs[reg]
5852 || (flag_pic && ! TARGET_SINGLE_PIC_BASE
5853 && reg == PIC_OFFSET_TABLE_REGNUM)))
5855 strcat (instr, "%|");
5856 strcat (instr, reg_names[reg]);
5858 strcat (instr, ", ");
5861 if (frame_pointer_needed)
5863 strcat (instr, "%|");
5864 strcat (instr, reg_names[11]);
5865 strcat (instr, ", ");
5866 strcat (instr, "%|");
5867 strcat (instr, reg_names[13]);
5868 strcat (instr, ", ");
5869 strcat (instr, "%|");
5870 strcat (instr, TARGET_INTERWORK || (! really_return)
5871 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
5875 strcat (instr, "%|");
5876 if (TARGET_INTERWORK && really_return)
5877 strcat (instr, reg_names[IP_REGNUM]);
5879 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
5881 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5882 output_asm_insn (instr, &operand);
5884 if (TARGET_INTERWORK && really_return)
5886 strcpy (instr, "bx%?");
5887 strcat (instr, reverse ? "%D0" : "%d0");
5888 strcat (instr, "\t%|");
5889 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5891 output_asm_insn (instr, & operand);
5894 else if (really_return)
5896 if (TARGET_INTERWORK)
5897 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5899 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5900 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5902 output_asm_insn (instr, & operand);
5908 /* Return nonzero if optimizing and the current function is volatile.
5909 Such functions never return, and many memory cycles can be saved
5910 by not storing register values that will never be needed again.
5911 This optimization was added to speed up context switching in a
5912 kernel application. */
5915 arm_volatile_func ()
5917 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5920 /* Write the function name into the code section, directly preceding
5921 the function prologue.
5923 Code will be output similar to this:
5925 .ascii "arm_poke_function_name", 0
5928 .word 0xff000000 + (t1 - t0)
5929 arm_poke_function_name
5931 stmfd sp!, {fp, ip, lr, pc}
5934 When performing a stack backtrace, code can inspect the value
5935 of 'pc' stored at 'fp' + 0. If the trace function then looks
5936 at location pc - 12 and the top 8 bits are set, then we know
5937 that there is a function name embedded immediately preceding this
5938 location and has length ((pc[-3]) & 0xff000000).
5940 We assume that pc is declared as a pointer to an unsigned long.
5942 It is of no benefit to output the function name if we are assembling
5943 a leaf function. These function types will not contain a stack
5944 backtrace structure, therefore it is not possible to determine the
5948 arm_poke_function_name (stream, name)
5952 unsigned long alignlength;
5953 unsigned long length;
5956 length = strlen (name) + 1;
5957 alignlength = (length + 3) & ~3;
5959 ASM_OUTPUT_ASCII (stream, name, length);
5960 ASM_OUTPUT_ALIGN (stream, 2);
5961 x = GEN_INT (0xff000000UL + alignlength);
5962 ASM_OUTPUT_INT (stream, x);
5965 /* The amount of stack adjustment that happens here, in output_return and in
5966 output_epilogue must be exactly the same as was calculated during reload,
5967 or things will point to the wrong place. The only time we can safely
5968 ignore this constraint is when a function has no arguments on the stack,
5969 no stack frame requirement and no live registers execpt for `lr'. If we
5970 can guarantee that by making all function calls into tail calls and that
5971 lr is not clobbered in any other way, then there is no need to push lr
5975 output_func_prologue (f, frame_size)
5979 int reg, live_regs_mask = 0;
5980 int volatile_func = (optimize > 0
5981 && TREE_THIS_VOLATILE (current_function_decl));
5983 /* Nonzero if we must stuff some register arguments onto the stack as if
5984 they were passed there. */
5985 int store_arg_regs = 0;
5987 if (arm_ccfsm_state || arm_target_insn)
5988 abort (); /* Sanity check */
5990 if (arm_naked_function_p (current_function_decl))
5993 return_used_this_function = 0;
5994 lr_save_eliminated = 0;
5996 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
5997 current_function_args_size,
5998 current_function_pretend_args_size, frame_size);
5999 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
6000 frame_pointer_needed,
6001 current_function_anonymous_args);
6004 asm_fprintf (f, "\t%@ Volatile function.\n");
6006 if (current_function_anonymous_args && current_function_pretend_args_size)
6009 for (reg = 0; reg <= 10; reg++)
6010 if (regs_ever_live[reg] && ! call_used_regs[reg])
6011 live_regs_mask |= (1 << reg);
6013 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
6014 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6015 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6017 if (frame_pointer_needed)
6018 live_regs_mask |= 0xD800;
6019 else if (regs_ever_live[LR_REGNUM])
6021 if (! current_function_args_size
6022 && ! function_really_clobbers_lr (get_insns ()))
6023 lr_save_eliminated = 1;
6025 live_regs_mask |= 1 << LR_REGNUM;
6030 /* if a di mode load/store multiple is used, and the base register
6031 is r3, then r4 can become an ever live register without lr
6032 doing so, in this case we need to push lr as well, or we
6033 will fail to get a proper return. */
6035 live_regs_mask |= 1 << LR_REGNUM;
6036 lr_save_eliminated = 0;
6040 if (lr_save_eliminated)
6041 asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
6043 #ifdef AOF_ASSEMBLER
6045 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
6050 arm_output_epilogue ()
6053 int live_regs_mask = 0;
6054 /* If we need this, then it will always be at least this much */
6055 int floats_offset = 12;
6057 int frame_size = get_frame_size ();
6058 FILE *f = asm_out_file;
6059 int volatile_func = (optimize > 0
6060 && TREE_THIS_VOLATILE (current_function_decl));
6062 if (use_return_insn (FALSE) && return_used_this_function)
6065 /* Naked functions don't have epilogues. */
6066 if (arm_naked_function_p (current_function_decl))
6069 /* A volatile function should never return. Call abort. */
6070 if (TARGET_ABORT_NORETURN && volatile_func)
6073 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
6074 assemble_external_libcall (op);
6075 output_asm_insn ("bl\t%a0", &op);
6079 for (reg = 0; reg <= 10; reg++)
6080 if (regs_ever_live[reg] && ! call_used_regs[reg])
6082 live_regs_mask |= (1 << reg);
6086 /* If we aren't loading the PIC register, don't stack it even though it may
6088 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
6089 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6091 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6095 if (frame_pointer_needed)
6097 if (arm_fpu_arch == FP_SOFT2)
6099 for (reg = 23; reg > 15; reg--)
6100 if (regs_ever_live[reg] && ! call_used_regs[reg])
6102 floats_offset += 12;
6103 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
6104 reg, FP_REGNUM, floats_offset);
6111 for (reg = 23; reg > 15; reg--)
6113 if (regs_ever_live[reg] && ! call_used_regs[reg])
6115 floats_offset += 12;
6117 /* We can't unstack more than four registers at once */
6118 if (start_reg - reg == 3)
6120 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
6121 reg, FP_REGNUM, floats_offset);
6122 start_reg = reg - 1;
6127 if (reg != start_reg)
6128 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6129 reg + 1, start_reg - reg,
6130 FP_REGNUM, floats_offset);
6131 start_reg = reg - 1;
6135 /* Just in case the last register checked also needs unstacking. */
6136 if (reg != start_reg)
6137 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6138 reg + 1, start_reg - reg,
6139 FP_REGNUM, floats_offset);
6142 if (TARGET_INTERWORK)
6144 live_regs_mask |= 0x6800;
6145 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
6146 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6150 live_regs_mask |= 0xA800;
6151 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
6152 TARGET_APCS_32 ? FALSE : TRUE);
6157 /* Restore stack pointer if necessary. */
6158 if (frame_size + current_function_outgoing_args_size != 0)
6160 operands[0] = operands[1] = stack_pointer_rtx;
6161 operands[2] = GEN_INT (frame_size
6162 + current_function_outgoing_args_size);
6163 output_add_immediate (operands);
6166 if (arm_fpu_arch == FP_SOFT2)
6168 for (reg = 16; reg < 24; reg++)
6169 if (regs_ever_live[reg] && ! call_used_regs[reg])
6170 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
6177 for (reg = 16; reg < 24; reg++)
6179 if (regs_ever_live[reg] && ! call_used_regs[reg])
6181 if (reg - start_reg == 3)
6183 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
6184 start_reg, SP_REGNUM);
6185 start_reg = reg + 1;
6190 if (reg != start_reg)
6191 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6192 start_reg, reg - start_reg,
6195 start_reg = reg + 1;
6199 /* Just in case the last register checked also needs unstacking. */
6200 if (reg != start_reg)
6201 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6202 start_reg, reg - start_reg, SP_REGNUM);
6205 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
6207 if (TARGET_INTERWORK)
6209 if (! lr_save_eliminated)
6210 live_regs_mask |= 1 << LR_REGNUM;
6212 if (live_regs_mask != 0)
6213 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6215 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6217 else if (lr_save_eliminated)
6219 TARGET_APCS_32 ? "\tmov\t%r, %r\n" : "\tmovs\t%r, %r\n",
6220 PC_REGNUM, LR_REGNUM);
6222 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
6223 TARGET_APCS_32 ? FALSE : TRUE);
6227 if (live_regs_mask || regs_ever_live[LR_REGNUM])
6229 /* Restore the integer regs, and the return address into lr */
6230 if (! lr_save_eliminated)
6231 live_regs_mask |= 1 << LR_REGNUM;
6233 if (live_regs_mask != 0)
6234 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6237 if (current_function_pretend_args_size)
6239 /* Unwind the pre-pushed regs */
6240 operands[0] = operands[1] = stack_pointer_rtx;
6241 operands[2] = GEN_INT (current_function_pretend_args_size);
6242 output_add_immediate (operands);
6244 /* And finally, go home */
6245 if (TARGET_INTERWORK)
6246 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6247 else if (TARGET_APCS_32)
6248 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6250 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6258 output_func_epilogue (frame_size)
6261 if (use_return_insn (FALSE) && return_used_this_function
6262 && (frame_size + current_function_outgoing_args_size) != 0
6263 && ! (frame_pointer_needed && TARGET_APCS))
6266 /* Reset the ARM-specific per-function variables. */
6267 current_function_anonymous_args = 0;
6268 after_arm_reorg = 0;
6272 emit_multi_reg_push (mask)
6279 for (i = 0; i < 16; i++)
6280 if (mask & (1 << i))
6283 if (num_regs == 0 || num_regs > 16)
6286 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
6288 for (i = 0; i < 16; i++)
6290 if (mask & (1 << i))
6293 = gen_rtx_SET (VOIDmode,
6294 gen_rtx_MEM (BLKmode,
6295 gen_rtx_PRE_DEC (BLKmode,
6296 stack_pointer_rtx)),
6297 gen_rtx_UNSPEC (BLKmode,
6299 gen_rtx_REG (SImode, i)),
6305 for (j = 1, i++; j < num_regs; i++)
6307 if (mask & (1 << i))
6310 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
6319 emit_sfm (base_reg, count)
6326 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6329 = gen_rtx_SET (VOIDmode,
6330 gen_rtx_MEM (BLKmode,
6331 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
6332 gen_rtx_UNSPEC (BLKmode,
6333 gen_rtvec (1, gen_rtx_REG (XFmode,
6336 for (i = 1; i < count; i++)
6337 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
6338 gen_rtx_REG (XFmode, base_reg++));
6344 arm_expand_prologue ()
6347 rtx amount = GEN_INT (-(get_frame_size ()
6348 + current_function_outgoing_args_size));
6349 int live_regs_mask = 0;
6350 int store_arg_regs = 0;
6351 /* If this function doesn't return, then there is no need to push
6352 the call-saved regs. */
6353 int volatile_func = (optimize > 0
6354 && TREE_THIS_VOLATILE (current_function_decl));
6356 /* Naked functions don't have prologues. */
6357 if (arm_naked_function_p (current_function_decl))
6360 if (current_function_anonymous_args && current_function_pretend_args_size)
6363 if (! volatile_func)
6365 for (reg = 0; reg <= 10; reg++)
6366 if (regs_ever_live[reg] && ! call_used_regs[reg])
6367 live_regs_mask |= 1 << reg;
6369 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6370 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6372 if (regs_ever_live[LR_REGNUM])
6373 live_regs_mask |= 1 << LR_REGNUM;
6376 if (frame_pointer_needed)
6378 live_regs_mask |= 0xD800;
6379 emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
6380 stack_pointer_rtx));
6383 if (current_function_pretend_args_size)
6386 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
6389 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6390 GEN_INT (-current_function_pretend_args_size)));
6395 /* If we have to push any regs, then we must push lr as well, or
6396 we won't get a proper return. */
6397 live_regs_mask |= 1 << LR_REGNUM;
6398 emit_multi_reg_push (live_regs_mask);
6401 /* For now the integer regs are still pushed in output_func_epilogue (). */
6403 if (! volatile_func)
6405 if (arm_fpu_arch == FP_SOFT2)
6407 for (reg = 23; reg > 15; reg--)
6408 if (regs_ever_live[reg] && ! call_used_regs[reg])
6409 emit_insn (gen_rtx_SET
6411 gen_rtx_MEM (XFmode,
6412 gen_rtx_PRE_DEC (XFmode,
6413 stack_pointer_rtx)),
6414 gen_rtx_REG (XFmode, reg)));
6420 for (reg = 23; reg > 15; reg--)
6422 if (regs_ever_live[reg] && ! call_used_regs[reg])
6424 if (start_reg - reg == 3)
6427 start_reg = reg - 1;
6432 if (start_reg != reg)
6433 emit_sfm (reg + 1, start_reg - reg);
6434 start_reg = reg - 1;
6438 if (start_reg != reg)
6439 emit_sfm (reg + 1, start_reg - reg);
6443 if (frame_pointer_needed)
6444 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, IP_REGNUM),
6446 (-(4 + current_function_pretend_args_size)))));
6448 if (amount != const0_rtx)
6450 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
6451 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6452 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
6455 /* If we are profiling, make sure no instructions are scheduled before
6456 the call to mcount. Similarly if the user has requested no
6457 scheduling in the prolog. */
6458 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
6459 emit_insn (gen_blockage ());
6463 /* If CODE is 'd', then the X is a condition operand and the instruction
6464 should only be executed if the condition is true.
6465 if CODE is 'D', then the X is a condition operand and the instruction
6466 should only be executed if the condition is false: however, if the mode
6467 of the comparison is CCFPEmode, then always execute the instruction -- we
6468 do this because in these circumstances !GE does not necessarily imply LT;
6469 in these cases the instruction pattern will take care to make sure that
6470 an instruction containing %d will follow, thereby undoing the effects of
6471 doing this instruction unconditionally.
6472 If CODE is 'N' then X is a floating point operand that must be negated
6474 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6475 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6478 arm_print_operand (stream, x, code)
6486 fputs (ASM_COMMENT_START, stream);
6490 fputs (REGISTER_PREFIX, stream);
6494 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
6495 fputs (arm_condition_codes[arm_current_cc], stream);
6501 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6502 r = REAL_VALUE_NEGATE (r);
6503 fprintf (stream, "%s", fp_const_from_val (&r));
6508 if (GET_CODE (x) == CONST_INT)
6511 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6512 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6517 output_addr_const (stream, x);
6522 fprintf (stream, "%s", arithmetic_instr (x, 1));
6526 fprintf (stream, "%s", arithmetic_instr (x, 0));
6532 char * shift = shift_op (x, & val);
6536 fprintf (stream, ", %s ", shift_op (x, & val));
6538 arm_print_operand (stream, XEXP (x, 1), 0);
6541 fputc ('#', stream);
6542 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6551 fputs (REGISTER_PREFIX, stream);
6552 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6558 fputs (REGISTER_PREFIX, stream);
6559 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6563 fputs (REGISTER_PREFIX, stream);
6564 if (GET_CODE (XEXP (x, 0)) == REG)
6565 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6567 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6571 asm_fprintf (stream, "{%r-%r}",
6572 REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
6577 fputs (arm_condition_codes[get_arm_condition_code (x)],
6583 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6584 (get_arm_condition_code (x))],
6592 if (GET_CODE (x) == REG)
6594 fputs (REGISTER_PREFIX, stream);
6595 fputs (reg_names[REGNO (x)], stream);
6597 else if (GET_CODE (x) == MEM)
6599 output_memory_reference_mode = GET_MODE (x);
6600 output_address (XEXP (x, 0));
6602 else if (GET_CODE (x) == CONST_DOUBLE)
6603 fprintf (stream, "#%s", fp_immediate_constant (x));
6604 else if (GET_CODE (x) == NEG)
6605 abort (); /* This should never happen now. */
6608 fputc ('#', stream);
6609 output_addr_const (stream, x);
6614 /* A finite state machine takes care of noticing whether or not instructions
6615 can be conditionally executed, and thus decrease execution time and code
6616 size by deleting branch instructions. The fsm is controlled by
6617 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6619 /* The state of the fsm controlling condition codes are:
6620 0: normal, do nothing special
6621 1: make ASM_OUTPUT_OPCODE not output this instruction
6622 2: make ASM_OUTPUT_OPCODE not output this instruction
6623 3: make instructions conditional
6624 4: make instructions conditional
6626 State transitions (state->state by whom under condition):
6627 0 -> 1 final_prescan_insn if the `target' is a label
6628 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6629 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6630 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6631 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6632 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6633 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6634 (the target insn is arm_target_insn).
6636 If the jump clobbers the conditions then we use states 2 and 4.
6638 A similar thing can be done with conditional return insns.
6640 XXX In case the `target' is an unconditional branch, this conditionalising
6641 of the instructions always reduces code size, but not always execution
6642 time. But then, I want to reduce the code size to somewhere near what
6643 /bin/cc produces. */
6645 /* Returns the index of the ARM condition code string in
6646 `arm_condition_codes'. COMPARISON should be an rtx like
6647 `(eq (...) (...))'. */
6649 static enum arm_cond_code
6650 get_arm_condition_code (comparison)
6653 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6655 register enum rtx_code comp_code = GET_CODE (comparison);
6657 if (GET_MODE_CLASS (mode) != MODE_CC)
6658 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6659 XEXP (comparison, 1));
6663 case CC_DNEmode: code = ARM_NE; goto dominance;
6664 case CC_DEQmode: code = ARM_EQ; goto dominance;
6665 case CC_DGEmode: code = ARM_GE; goto dominance;
6666 case CC_DGTmode: code = ARM_GT; goto dominance;
6667 case CC_DLEmode: code = ARM_LE; goto dominance;
6668 case CC_DLTmode: code = ARM_LT; goto dominance;
6669 case CC_DGEUmode: code = ARM_CS; goto dominance;
6670 case CC_DGTUmode: code = ARM_HI; goto dominance;
6671 case CC_DLEUmode: code = ARM_LS; goto dominance;
6672 case CC_DLTUmode: code = ARM_CC;
6675 if (comp_code != EQ && comp_code != NE)
6678 if (comp_code == EQ)
6679 return ARM_INVERSE_CONDITION_CODE (code);
6685 case NE: return ARM_NE;
6686 case EQ: return ARM_EQ;
6687 case GE: return ARM_PL;
6688 case LT: return ARM_MI;
6696 case NE: return ARM_NE;
6697 case EQ: return ARM_EQ;
6704 case GE: return ARM_GE;
6705 case GT: return ARM_GT;
6706 case LE: return ARM_LS;
6707 case LT: return ARM_MI;
6714 case NE: return ARM_NE;
6715 case EQ: return ARM_EQ;
6716 case GE: return ARM_LE;
6717 case GT: return ARM_LT;
6718 case LE: return ARM_GE;
6719 case LT: return ARM_GT;
6720 case GEU: return ARM_LS;
6721 case GTU: return ARM_CC;
6722 case LEU: return ARM_CS;
6723 case LTU: return ARM_HI;
6730 case LTU: return ARM_CS;
6731 case GEU: return ARM_CC;
6738 case NE: return ARM_NE;
6739 case EQ: return ARM_EQ;
6740 case GE: return ARM_GE;
6741 case GT: return ARM_GT;
6742 case LE: return ARM_LE;
6743 case LT: return ARM_LT;
6744 case GEU: return ARM_CS;
6745 case GTU: return ARM_HI;
6746 case LEU: return ARM_LS;
6747 case LTU: return ARM_CC;
6759 arm_final_prescan_insn (insn)
6762 /* BODY will hold the body of INSN. */
6763 register rtx body = PATTERN (insn);
6765 /* This will be 1 if trying to repeat the trick, and things need to be
6766 reversed if it appears to fail. */
6769 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6770 taken are clobbered, even if the rtl suggests otherwise. It also
6771 means that we have to grub around within the jump expression to find
6772 out what the conditions are when the jump isn't taken. */
6773 int jump_clobbers = 0;
6775 /* If we start with a return insn, we only succeed if we find another one. */
6776 int seeking_return = 0;
6778 /* START_INSN will hold the insn from where we start looking. This is the
6779 first insn after the following code_label if REVERSE is true. */
6780 rtx start_insn = insn;
6782 /* If in state 4, check if the target branch is reached, in order to
6783 change back to state 0. */
6784 if (arm_ccfsm_state == 4)
6786 if (insn == arm_target_insn)
6788 arm_target_insn = NULL;
6789 arm_ccfsm_state = 0;
6794 /* If in state 3, it is possible to repeat the trick, if this insn is an
6795 unconditional branch to a label, and immediately following this branch
6796 is the previous target label which is only used once, and the label this
6797 branch jumps to is not too far off. */
6798 if (arm_ccfsm_state == 3)
6800 if (simplejump_p (insn))
6802 start_insn = next_nonnote_insn (start_insn);
6803 if (GET_CODE (start_insn) == BARRIER)
6805 /* XXX Isn't this always a barrier? */
6806 start_insn = next_nonnote_insn (start_insn);
6808 if (GET_CODE (start_insn) == CODE_LABEL
6809 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6810 && LABEL_NUSES (start_insn) == 1)
6815 else if (GET_CODE (body) == RETURN)
6817 start_insn = next_nonnote_insn (start_insn);
6818 if (GET_CODE (start_insn) == BARRIER)
6819 start_insn = next_nonnote_insn (start_insn);
6820 if (GET_CODE (start_insn) == CODE_LABEL
6821 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6822 && LABEL_NUSES (start_insn) == 1)
6834 if (arm_ccfsm_state != 0 && !reverse)
6836 if (GET_CODE (insn) != JUMP_INSN)
6839 /* This jump might be paralleled with a clobber of the condition codes
6840 the jump should always come first */
6841 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6842 body = XVECEXP (body, 0, 0);
6845 /* If this is a conditional return then we don't want to know */
6846 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6847 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6848 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6849 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6854 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6855 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6858 int fail = FALSE, succeed = FALSE;
6859 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6860 int then_not_else = TRUE;
6861 rtx this_insn = start_insn, label = 0;
6863 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6865 /* The code below is wrong for these, and I haven't time to
6866 fix it now. So we just do the safe thing and return. This
6867 whole function needs re-writing anyway. */
6872 /* Register the insn jumped to. */
6875 if (!seeking_return)
6876 label = XEXP (SET_SRC (body), 0);
6878 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6879 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6880 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6882 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6883 then_not_else = FALSE;
6885 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6887 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6890 then_not_else = FALSE;
6895 /* See how many insns this branch skips, and what kind of insns. If all
6896 insns are okay, and the label or unconditional branch to the same
6897 label is not too far away, succeed. */
6898 for (insns_skipped = 0;
6899 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6903 this_insn = next_nonnote_insn (this_insn);
6907 switch (GET_CODE (this_insn))
6910 /* Succeed if it is the target label, otherwise fail since
6911 control falls in from somewhere else. */
6912 if (this_insn == label)
6916 arm_ccfsm_state = 2;
6917 this_insn = next_nonnote_insn (this_insn);
6920 arm_ccfsm_state = 1;
6928 /* Succeed if the following insn is the target label.
6930 If return insns are used then the last insn in a function
6931 will be a barrier. */
6932 this_insn = next_nonnote_insn (this_insn);
6933 if (this_insn && this_insn == label)
6937 arm_ccfsm_state = 2;
6938 this_insn = next_nonnote_insn (this_insn);
6941 arm_ccfsm_state = 1;
6949 /* If using 32-bit addresses the cc is not preserved over
6953 /* Succeed if the following insn is the target label,
6954 or if the following two insns are a barrier and
6955 the target label. */
6956 this_insn = next_nonnote_insn (this_insn);
6957 if (this_insn && GET_CODE (this_insn) == BARRIER)
6958 this_insn = next_nonnote_insn (this_insn);
6960 if (this_insn && this_insn == label
6961 && insns_skipped < max_insns_skipped)
6965 arm_ccfsm_state = 2;
6966 this_insn = next_nonnote_insn (this_insn);
6969 arm_ccfsm_state = 1;
6978 /* If this is an unconditional branch to the same label, succeed.
6979 If it is to another label, do nothing. If it is conditional,
6981 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6983 scanbody = PATTERN (this_insn);
6984 if (GET_CODE (scanbody) == SET
6985 && GET_CODE (SET_DEST (scanbody)) == PC)
6987 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
6988 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
6990 arm_ccfsm_state = 2;
6993 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
6996 /* Fail if a conditional return is undesirable (eg on a
6997 StrongARM), but still allow this if optimizing for size. */
6998 else if (GET_CODE (scanbody) == RETURN
6999 && ! use_return_insn (TRUE)
7002 else if (GET_CODE (scanbody) == RETURN
7005 arm_ccfsm_state = 2;
7008 else if (GET_CODE (scanbody) == PARALLEL)
7010 switch (get_attr_conds (this_insn))
7022 /* Instructions using or affecting the condition codes make it
7024 scanbody = PATTERN (this_insn);
7025 if (! (GET_CODE (scanbody) == SET
7026 || GET_CODE (scanbody) == PARALLEL)
7027 || get_attr_conds (this_insn) != CONDS_NOCOND)
7037 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
7038 arm_target_label = CODE_LABEL_NUMBER (label);
7039 else if (seeking_return || arm_ccfsm_state == 2)
7041 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
7043 this_insn = next_nonnote_insn (this_insn);
7044 if (this_insn && (GET_CODE (this_insn) == BARRIER
7045 || GET_CODE (this_insn) == CODE_LABEL))
7050 /* Oh, dear! we ran off the end.. give up */
7051 recog (PATTERN (insn), insn, NULL_PTR);
7052 arm_ccfsm_state = 0;
7053 arm_target_insn = NULL;
7056 arm_target_insn = this_insn;
7065 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
7067 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
7068 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7069 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
7070 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7074 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
7077 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
7081 if (reverse || then_not_else)
7082 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7085 /* Restore recog_data (getting the attributes of other insns can
7086 destroy this array, but final.c assumes that it remains intact
7087 across this call; since the insn has been recognized already we
7088 call recog direct). */
7089 recog (PATTERN (insn), insn, NULL_PTR);
7093 /* Return the length of a function name prefix
7094 that starts with the character 'c'. */
7096 arm_get_strip_length (char c)
7100 ARM_NAME_ENCODING_LENGTHS
7105 /* Return a pointer to a function's name with any
7106 and all prefix encodings stripped from it. */
7108 arm_strip_name_encoding (const char * name)
7112 while ((skip = arm_get_strip_length (* name)))
7118 #ifdef AOF_ASSEMBLER
7119 /* Special functions only needed when producing AOF syntax assembler. */
7121 rtx aof_pic_label = NULL_RTX;
7124 struct pic_chain * next;
7128 static struct pic_chain * aof_pic_chain = NULL;
7134 struct pic_chain ** chainp;
7137 if (aof_pic_label == NULL_RTX)
7139 /* We mark this here and not in arm_add_gc_roots() to avoid
7140 polluting even more code with ifdefs, and because it never
7141 contains anything useful until we assign to it here. */
7142 ggc_add_rtx_root (&aof_pic_label, 1);
7143 /* This needs to persist throughout the compilation. */
7144 end_temporary_allocation ();
7145 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
7146 resume_temporary_allocation ();
7149 for (offset = 0, chainp = &aof_pic_chain; *chainp;
7150 offset += 4, chainp = &(*chainp)->next)
7151 if ((*chainp)->symname == XSTR (x, 0))
7152 return plus_constant (aof_pic_label, offset);
7154 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
7155 (*chainp)->next = NULL;
7156 (*chainp)->symname = XSTR (x, 0);
7157 return plus_constant (aof_pic_label, offset);
7161 aof_dump_pic_table (f)
7164 struct pic_chain * chain;
7166 if (aof_pic_chain == NULL)
7169 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
7170 PIC_OFFSET_TABLE_REGNUM,
7171 PIC_OFFSET_TABLE_REGNUM);
7172 fputs ("|x$adcons|\n", f);
7174 for (chain = aof_pic_chain; chain; chain = chain->next)
7176 fputs ("\tDCD\t", f);
7177 assemble_name (f, chain->symname);
7182 int arm_text_section_count = 1;
7187 static char buf[100];
7188 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
7189 arm_text_section_count++);
7191 strcat (buf, ", PIC, REENTRANT");
7195 static int arm_data_section_count = 1;
7200 static char buf[100];
7201 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
7205 /* The AOF assembler is religiously strict about declarations of
7206 imported and exported symbols, so that it is impossible to declare
7207 a function as imported near the beginning of the file, and then to
7208 export it later on. It is, however, possible to delay the decision
7209 until all the functions in the file have been compiled. To get
7210 around this, we maintain a list of the imports and exports, and
7211 delete from it any that are subsequently defined. At the end of
7212 compilation we spit the remainder of the list out before the END
7217 struct import * next;
7221 static struct import * imports_list = NULL;
7224 aof_add_import (name)
7227 struct import * new;
7229 for (new = imports_list; new; new = new->next)
7230 if (new->name == name)
7233 new = (struct import *) xmalloc (sizeof (struct import));
7234 new->next = imports_list;
7240 aof_delete_import (name)
7243 struct import ** old;
7245 for (old = &imports_list; *old; old = & (*old)->next)
7247 if ((*old)->name == name)
7249 *old = (*old)->next;
7255 int arm_main_function = 0;
7258 aof_dump_imports (f)
7261 /* The AOF assembler needs this to cause the startup code to be extracted
7262 from the library. Brining in __main causes the whole thing to work
7264 if (arm_main_function)
7267 fputs ("\tIMPORT __main\n", f);
7268 fputs ("\tDCD __main\n", f);
7271 /* Now dump the remaining imports. */
7272 while (imports_list)
7274 fprintf (f, "\tIMPORT\t");
7275 assemble_name (f, imports_list->name);
7277 imports_list = imports_list->next;
7280 #endif /* AOF_ASSEMBLER */