1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
57 /* Forward definitions of types. */
58 typedef struct minipool_node Mnode;
59 typedef struct minipool_fixup Mfix;
61 const struct attribute_spec arm_attribute_table[];
63 /* Forward function declarations. */
64 static arm_stack_offsets *arm_get_frame_offsets (void);
65 static void arm_add_gc_roots (void);
66 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
67 HOST_WIDE_INT, rtx, rtx, int, int);
68 static unsigned bit_count (unsigned long);
69 static int arm_address_register_rtx_p (rtx, int);
70 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
71 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
72 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
73 inline static int thumb1_index_register_rtx_p (rtx, int);
74 static int thumb_far_jump_used_p (void);
75 static bool thumb_force_lr_save (void);
76 static unsigned long thumb1_compute_save_reg_mask (void);
77 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
78 static rtx emit_sfm (int, int);
79 static int arm_size_return_regs (void);
81 static bool arm_assemble_integer (rtx, unsigned int, int);
83 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
84 static arm_cc get_arm_condition_code (rtx);
85 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
86 static rtx is_jump_table (rtx);
87 static const char *output_multi_immediate (rtx *, const char *, const char *,
89 static const char *shift_op (rtx, HOST_WIDE_INT *);
90 static struct machine_function *arm_init_machine_status (void);
91 static void thumb_exit (FILE *, int);
92 static rtx is_jump_table (rtx);
93 static HOST_WIDE_INT get_jump_table_size (rtx);
94 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
95 static Mnode *add_minipool_forward_ref (Mfix *);
96 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_backward_ref (Mfix *);
98 static void assign_minipool_offsets (Mfix *);
99 static void arm_print_value (FILE *, rtx);
100 static void dump_minipool (rtx);
101 static int arm_barrier_cost (rtx);
102 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
103 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
104 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
106 static void arm_reorg (void);
107 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
147 static rtx emit_set_insn (rtx, rtx);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
153 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
156 static void arm_encode_section_info (tree, rtx, int);
159 static void arm_file_end (void);
160 static void arm_file_start (void);
163 static void aof_globalize_label (FILE *, const char *);
164 static void aof_dump_imports (FILE *);
165 static void aof_dump_pic_table (FILE *);
166 static void aof_file_start (void);
167 static void aof_file_end (void);
168 static void aof_asm_init_sections (void);
170 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
172 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
173 enum machine_mode, tree, bool);
174 static bool arm_promote_prototypes (tree);
175 static bool arm_default_short_enums (void);
176 static bool arm_align_anon_bitfield (void);
177 static bool arm_return_in_msb (tree);
178 static bool arm_must_pass_in_stack (enum machine_mode, tree);
179 #ifdef TARGET_UNWIND_INFO
180 static void arm_unwind_emit (FILE *, rtx);
181 static bool arm_output_ttype (rtx);
183 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
185 static tree arm_cxx_guard_type (void);
186 static bool arm_cxx_guard_mask_bit (void);
187 static tree arm_get_cookie_size (tree);
188 static bool arm_cookie_has_size (void);
189 static bool arm_cxx_cdtor_returns_this (void);
190 static bool arm_cxx_key_method_may_be_inline (void);
191 static void arm_cxx_determine_class_data_visibility (tree);
192 static bool arm_cxx_class_data_always_comdat (void);
193 static bool arm_cxx_use_aeabi_atexit (void);
194 static void arm_init_libfuncs (void);
195 static bool arm_handle_option (size_t, const char *, int);
196 static void arm_target_help (void);
197 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
198 static bool arm_cannot_copy_insn_p (rtx);
199 static bool arm_tls_symbol_p (rtx x);
200 static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
203 /* Initialize the GCC target structure. */
204 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
205 #undef TARGET_MERGE_DECL_ATTRIBUTES
206 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
209 #undef TARGET_ATTRIBUTE_TABLE
210 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
212 #undef TARGET_ASM_FILE_START
213 #define TARGET_ASM_FILE_START arm_file_start
214 #undef TARGET_ASM_FILE_END
215 #define TARGET_ASM_FILE_END arm_file_end
218 #undef TARGET_ASM_BYTE_OP
219 #define TARGET_ASM_BYTE_OP "\tDCB\t"
220 #undef TARGET_ASM_ALIGNED_HI_OP
221 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
224 #undef TARGET_ASM_GLOBALIZE_LABEL
225 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
226 #undef TARGET_ASM_FILE_START
227 #define TARGET_ASM_FILE_START aof_file_start
228 #undef TARGET_ASM_FILE_END
229 #define TARGET_ASM_FILE_END aof_file_end
231 #undef TARGET_ASM_ALIGNED_SI_OP
232 #define TARGET_ASM_ALIGNED_SI_OP NULL
233 #undef TARGET_ASM_INTEGER
234 #define TARGET_ASM_INTEGER arm_assemble_integer
237 #undef TARGET_ASM_FUNCTION_PROLOGUE
238 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
240 #undef TARGET_ASM_FUNCTION_EPILOGUE
241 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
243 #undef TARGET_DEFAULT_TARGET_FLAGS
244 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
245 #undef TARGET_HANDLE_OPTION
246 #define TARGET_HANDLE_OPTION arm_handle_option
248 #define TARGET_HELP arm_target_help
250 #undef TARGET_COMP_TYPE_ATTRIBUTES
251 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
253 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
254 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
256 #undef TARGET_SCHED_ADJUST_COST
257 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
259 #undef TARGET_ENCODE_SECTION_INFO
261 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
263 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
266 #undef TARGET_STRIP_NAME_ENCODING
267 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
269 #undef TARGET_ASM_INTERNAL_LABEL
270 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
272 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
273 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
275 #undef TARGET_ASM_OUTPUT_MI_THUNK
276 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
277 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
278 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
280 /* This will be overridden in arm_override_options. */
281 #undef TARGET_RTX_COSTS
282 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
283 #undef TARGET_ADDRESS_COST
284 #define TARGET_ADDRESS_COST arm_address_cost
286 #undef TARGET_SHIFT_TRUNCATION_MASK
287 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
288 #undef TARGET_VECTOR_MODE_SUPPORTED_P
289 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
291 #undef TARGET_MACHINE_DEPENDENT_REORG
292 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
294 #undef TARGET_INIT_BUILTINS
295 #define TARGET_INIT_BUILTINS arm_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
299 #undef TARGET_INIT_LIBFUNCS
300 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
302 #undef TARGET_PROMOTE_FUNCTION_ARGS
303 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
304 #undef TARGET_PROMOTE_FUNCTION_RETURN
305 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
306 #undef TARGET_PROMOTE_PROTOTYPES
307 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
308 #undef TARGET_PASS_BY_REFERENCE
309 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
310 #undef TARGET_ARG_PARTIAL_BYTES
311 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
313 #undef TARGET_SETUP_INCOMING_VARARGS
314 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
316 #undef TARGET_DEFAULT_SHORT_ENUMS
317 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
319 #undef TARGET_ALIGN_ANON_BITFIELD
320 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
322 #undef TARGET_NARROW_VOLATILE_BITFIELD
323 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
325 #undef TARGET_CXX_GUARD_TYPE
326 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
328 #undef TARGET_CXX_GUARD_MASK_BIT
329 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
331 #undef TARGET_CXX_GET_COOKIE_SIZE
332 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
334 #undef TARGET_CXX_COOKIE_HAS_SIZE
335 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
337 #undef TARGET_CXX_CDTOR_RETURNS_THIS
338 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
340 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
341 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
343 #undef TARGET_CXX_USE_AEABI_ATEXIT
344 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
346 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
347 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
348 arm_cxx_determine_class_data_visibility
350 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
351 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
353 #undef TARGET_RETURN_IN_MSB
354 #define TARGET_RETURN_IN_MSB arm_return_in_msb
356 #undef TARGET_MUST_PASS_IN_STACK
357 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
359 #ifdef TARGET_UNWIND_INFO
360 #undef TARGET_UNWIND_EMIT
361 #define TARGET_UNWIND_EMIT arm_unwind_emit
363 /* EABI unwinding tables use a different format for the typeinfo tables. */
364 #undef TARGET_ASM_TTYPE
365 #define TARGET_ASM_TTYPE arm_output_ttype
367 #undef TARGET_ARM_EABI_UNWINDER
368 #define TARGET_ARM_EABI_UNWINDER true
369 #endif /* TARGET_UNWIND_INFO */
371 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
372 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
374 #undef TARGET_CANNOT_COPY_INSN_P
375 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
378 #undef TARGET_HAVE_TLS
379 #define TARGET_HAVE_TLS true
382 #undef TARGET_CANNOT_FORCE_CONST_MEM
383 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
386 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
387 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
390 struct gcc_target targetm = TARGET_INITIALIZER;
392 /* Obstack for minipool constant handling. */
393 static struct obstack minipool_obstack;
394 static char * minipool_startobj;
396 /* The maximum number of insns skipped which
397 will be conditionalised if possible. */
398 static int max_insns_skipped = 5;
400 extern FILE * asm_out_file;
402 /* True if we are currently building a constant table. */
403 int making_const_table;
405 /* Define the information needed to generate branch insns. This is
406 stored from the compare operation. */
407 rtx arm_compare_op0, arm_compare_op1;
409 /* The processor for which instructions should be scheduled. */
410 enum processor_type arm_tune = arm_none;
412 /* The default processor used if not overridden by commandline. */
413 static enum processor_type arm_default_cpu = arm_none;
415 /* Which floating point model to use. */
416 enum arm_fp_model arm_fp_model;
418 /* Which floating point hardware is available. */
419 enum fputype arm_fpu_arch;
421 /* Which floating point hardware to schedule for. */
422 enum fputype arm_fpu_tune;
424 /* Whether to use floating point hardware. */
425 enum float_abi_type arm_float_abi;
427 /* Which ABI to use. */
428 enum arm_abi_type arm_abi;
430 /* Which thread pointer model to use. */
431 enum arm_tp_type target_thread_pointer = TP_AUTO;
433 /* Used to parse -mstructure_size_boundary command line option. */
434 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
436 /* Used for Thumb call_via trampolines. */
437 rtx thumb_call_via_label[14];
438 static int thumb_call_reg_needed;
440 /* Bit values used to identify processor capabilities. */
441 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
442 #define FL_ARCH3M (1 << 1) /* Extended multiply */
443 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
444 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
445 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
446 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
447 #define FL_THUMB (1 << 6) /* Thumb aware */
448 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
449 #define FL_STRONG (1 << 8) /* StrongARM */
450 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
451 #define FL_XSCALE (1 << 10) /* XScale */
452 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
453 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
454 media instructions. */
455 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
456 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
457 Note: ARM6 & 7 derivatives only. */
458 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
459 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
460 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
462 #define FL_DIV (1 << 18) /* Hardware divide. */
463 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
465 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
467 #define FL_FOR_ARCH2 FL_NOTM
468 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
469 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
470 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
471 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
472 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
473 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
474 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
475 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
476 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
477 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
478 #define FL_FOR_ARCH6J FL_FOR_ARCH6
479 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
480 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
481 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
482 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
483 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
484 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
485 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
486 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
488 /* The bits in this mask specify which
489 instructions we are allowed to generate. */
490 static unsigned long insn_flags = 0;
492 /* The bits in this mask specify which instruction scheduling options should
494 static unsigned long tune_flags = 0;
496 /* The following are used in the arm.md file as equivalents to bits
497 in the above two flag variables. */
499 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
502 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
505 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
508 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
511 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
514 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
517 /* Nonzero if this chip supports the ARM 6K extensions. */
520 /* Nonzero if instructions not present in the 'M' profile can be used. */
521 int arm_arch_notm = 0;
523 /* Nonzero if this chip can benefit from load scheduling. */
524 int arm_ld_sched = 0;
526 /* Nonzero if this chip is a StrongARM. */
527 int arm_tune_strongarm = 0;
529 /* Nonzero if this chip is a Cirrus variant. */
530 int arm_arch_cirrus = 0;
532 /* Nonzero if this chip supports Intel Wireless MMX technology. */
533 int arm_arch_iwmmxt = 0;
535 /* Nonzero if this chip is an XScale. */
536 int arm_arch_xscale = 0;
538 /* Nonzero if tuning for XScale */
539 int arm_tune_xscale = 0;
541 /* Nonzero if we want to tune for stores that access the write-buffer.
542 This typically means an ARM6 or ARM7 with MMU or MPU. */
543 int arm_tune_wbuf = 0;
545 /* Nonzero if generating Thumb instructions. */
548 /* Nonzero if we should define __THUMB_INTERWORK__ in the
550 XXX This is a bit of a hack, it's intended to help work around
551 problems in GLD which doesn't understand that armv5t code is
552 interworking clean. */
553 int arm_cpp_interwork = 0;
555 /* Nonzero if chip supports Thumb 2. */
558 /* Nonzero if chip supports integer division instruction. */
561 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
562 must report the mode of the memory reference from PRINT_OPERAND to
563 PRINT_OPERAND_ADDRESS. */
564 enum machine_mode output_memory_reference_mode;
566 /* The register number to be used for the PIC offset register. */
567 unsigned arm_pic_register = INVALID_REGNUM;
569 /* Set to 1 when a return insn is output, this means that the epilogue
571 int return_used_this_function;
573 /* Set to 1 after arm_reorg has started. Reset to start at the start of
574 the next function. */
575 static int after_arm_reorg = 0;
577 /* The maximum number of insns to be used when loading a constant. */
578 static int arm_constant_limit = 3;
580 /* For an explanation of these variables, see final_prescan_insn below. */
582 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
583 enum arm_cond_code arm_current_cc;
585 int arm_target_label;
586 /* The number of conditionally executed insns, including the current insn. */
587 int arm_condexec_count = 0;
588 /* A bitmask specifying the patterns for the IT block.
589 Zero means do not output an IT block before this insn. */
590 int arm_condexec_mask = 0;
591 /* The number of bits used in arm_condexec_mask. */
592 int arm_condexec_masklen = 0;
594 /* The condition codes of the ARM, and the inverse function. */
595 static const char * const arm_condition_codes[] =
597 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
598 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
601 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
602 #define streq(string1, string2) (strcmp (string1, string2) == 0)
604 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
605 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
606 | (1 << PIC_OFFSET_TABLE_REGNUM)))
608 /* Initialization code. */
612 const char *const name;
613 enum processor_type core;
615 const unsigned long flags;
616 bool (* rtx_costs) (rtx, int, int, int *);
619 /* Not all of these give usefully different compilation alternatives,
620 but there is no simple way of generalizing them. */
621 static const struct processors all_cores[] =
624 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
625 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
626 #include "arm-cores.def"
628 {NULL, arm_none, NULL, 0, NULL}
631 static const struct processors all_architectures[] =
633 /* ARM Architectures */
634 /* We don't specify rtx_costs here as it will be figured out
637 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
638 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
639 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
640 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
641 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
642 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
643 implementations that support it, so we will leave it out for now. */
644 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
645 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
646 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
647 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
648 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
649 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
650 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
651 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
652 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
653 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
654 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
655 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
656 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
657 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
658 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
659 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
660 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
661 {NULL, arm_none, NULL, 0 , NULL}
664 struct arm_cpu_select
668 const struct processors * processors;
671 /* This is a magic structure. The 'string' field is magically filled in
672 with a pointer to the value specified by the user on the command line
673 assuming that the user has specified such a value. */
675 static struct arm_cpu_select arm_select[] =
677 /* string name processors */
678 { NULL, "-mcpu=", all_cores },
679 { NULL, "-march=", all_architectures },
680 { NULL, "-mtune=", all_cores }
683 /* Defines representing the indexes into the above table. */
684 #define ARM_OPT_SET_CPU 0
685 #define ARM_OPT_SET_ARCH 1
686 #define ARM_OPT_SET_TUNE 2
688 /* The name of the preprocessor macro to define for this architecture. */
690 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
699 /* Available values for -mfpu=. */
701 static const struct fpu_desc all_fpus[] =
703 {"fpa", FPUTYPE_FPA},
704 {"fpe2", FPUTYPE_FPA_EMU2},
705 {"fpe3", FPUTYPE_FPA_EMU2},
706 {"maverick", FPUTYPE_MAVERICK},
707 {"vfp", FPUTYPE_VFP},
708 {"vfp3", FPUTYPE_VFP3},
712 /* Floating point models used by the different hardware.
713 See fputype in arm.h. */
715 static const enum fputype fp_model_for_fpu[] =
717 /* No FP hardware. */
718 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
719 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
720 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
721 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
722 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
723 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */
724 ARM_FP_MODEL_VFP /* FPUTYPE_VFP3 */
731 enum float_abi_type abi_type;
735 /* Available values for -mfloat-abi=. */
737 static const struct float_abi all_float_abis[] =
739 {"soft", ARM_FLOAT_ABI_SOFT},
740 {"softfp", ARM_FLOAT_ABI_SOFTFP},
741 {"hard", ARM_FLOAT_ABI_HARD}
748 enum arm_abi_type abi_type;
752 /* Available values for -mabi=. */
754 static const struct abi_name arm_all_abis[] =
756 {"apcs-gnu", ARM_ABI_APCS},
757 {"atpcs", ARM_ABI_ATPCS},
758 {"aapcs", ARM_ABI_AAPCS},
759 {"iwmmxt", ARM_ABI_IWMMXT},
760 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
763 /* Supported TLS relocations. */
773 /* Emit an insn that's a simple single-set. Both the operands must be known
776 emit_set_insn (rtx x, rtx y)
778 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
781 /* Return the number of bits set in VALUE. */
783 bit_count (unsigned long value)
785 unsigned long count = 0;
790 value &= value - 1; /* Clear the least-significant set bit. */
796 /* Set up library functions unique to ARM. */
799 arm_init_libfuncs (void)
801 /* There are no special library functions unless we are using the
806 /* The functions below are described in Section 4 of the "Run-Time
807 ABI for the ARM architecture", Version 1.0. */
809 /* Double-precision floating-point arithmetic. Table 2. */
810 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
811 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
812 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
813 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
814 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
816 /* Double-precision comparisons. Table 3. */
817 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
818 set_optab_libfunc (ne_optab, DFmode, NULL);
819 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
820 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
821 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
822 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
823 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
825 /* Single-precision floating-point arithmetic. Table 4. */
826 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
827 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
828 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
829 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
830 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
832 /* Single-precision comparisons. Table 5. */
833 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
834 set_optab_libfunc (ne_optab, SFmode, NULL);
835 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
836 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
837 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
838 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
839 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
841 /* Floating-point to integer conversions. Table 6. */
842 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
843 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
844 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
845 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
846 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
847 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
848 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
849 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
851 /* Conversions between floating types. Table 7. */
852 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
853 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
855 /* Integer to floating-point conversions. Table 8. */
856 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
857 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
858 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
859 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
860 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
861 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
862 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
863 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
865 /* Long long. Table 9. */
866 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
867 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
868 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
869 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
870 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
871 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
872 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
873 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
875 /* Integer (32/32->32) division. \S 4.3.1. */
876 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
877 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
879 /* The divmod functions are designed so that they can be used for
880 plain division, even though they return both the quotient and the
881 remainder. The quotient is returned in the usual location (i.e.,
882 r0 for SImode, {r0, r1} for DImode), just as would be expected
883 for an ordinary division routine. Because the AAPCS calling
884 conventions specify that all of { r0, r1, r2, r3 } are
885 callee-saved registers, there is no need to tell the compiler
886 explicitly that those registers are clobbered by these
888 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
889 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
891 /* For SImode division the ABI provides div-without-mod routines,
893 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
894 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
896 /* We don't have mod libcalls. Fortunately gcc knows how to use the
897 divmod libcalls instead. */
898 set_optab_libfunc (smod_optab, DImode, NULL);
899 set_optab_libfunc (umod_optab, DImode, NULL);
900 set_optab_libfunc (smod_optab, SImode, NULL);
901 set_optab_libfunc (umod_optab, SImode, NULL);
904 /* Implement TARGET_HANDLE_OPTION. */
907 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
912 arm_select[1].string = arg;
916 arm_select[0].string = arg;
919 case OPT_mhard_float:
920 target_float_abi_name = "hard";
923 case OPT_msoft_float:
924 target_float_abi_name = "soft";
928 arm_select[2].string = arg;
937 arm_target_help (void)
940 static int columns = 0;
943 /* If we have not done so already, obtain the desired maximum width of
944 the output. Note - this is a duplication of the code at the start of
945 gcc/opts.c:print_specific_help() - the two copies should probably be
946 replaced by a single function. */
951 GET_ENVIRONMENT (p, "COLUMNS");
954 int value = atoi (p);
961 /* Use a reasonable default. */
965 printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n");
967 /* The - 2 is because we know that the last entry in the array is NULL. */
968 i = ARRAY_SIZE (all_cores) - 2;
970 printf (" %s", all_cores[i].name);
971 remaining = columns - (strlen (all_cores[i].name) + 4);
972 gcc_assert (remaining >= 0);
976 int len = strlen (all_cores[i].name);
978 if (remaining > len + 2)
980 printf (", %s", all_cores[i].name);
981 remaining -= len + 2;
987 printf ("\n %s", all_cores[i].name);
988 remaining = columns - (len + 4);
992 printf ("\n\n Known ARM architectures (for use with the -march= option):\n");
994 i = ARRAY_SIZE (all_architectures) - 2;
997 printf (" %s", all_architectures[i].name);
998 remaining = columns - (strlen (all_architectures[i].name) + 4);
999 gcc_assert (remaining >= 0);
1003 int len = strlen (all_architectures[i].name);
1005 if (remaining > len + 2)
1007 printf (", %s", all_architectures[i].name);
1008 remaining -= len + 2;
1014 printf ("\n %s", all_architectures[i].name);
1015 remaining = columns - (len + 4);
1022 /* Fix up any incompatible options that the user has specified.
1023 This has now turned into a maze. */
1025 arm_override_options (void)
1028 enum processor_type target_arch_cpu = arm_none;
1030 /* Set up the flags based on the cpu/architecture selected by the user. */
1031 for (i = ARRAY_SIZE (arm_select); i--;)
1033 struct arm_cpu_select * ptr = arm_select + i;
1035 if (ptr->string != NULL && ptr->string[0] != '\0')
1037 const struct processors * sel;
1039 for (sel = ptr->processors; sel->name != NULL; sel++)
1040 if (streq (ptr->string, sel->name))
1042 /* Set the architecture define. */
1043 if (i != ARM_OPT_SET_TUNE)
1044 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1046 /* Determine the processor core for which we should
1047 tune code-generation. */
1048 if (/* -mcpu= is a sensible default. */
1049 i == ARM_OPT_SET_CPU
1050 /* -mtune= overrides -mcpu= and -march=. */
1051 || i == ARM_OPT_SET_TUNE)
1052 arm_tune = (enum processor_type) (sel - ptr->processors);
1054 /* Remember the CPU associated with this architecture.
1055 If no other option is used to set the CPU type,
1056 we'll use this to guess the most suitable tuning
1058 if (i == ARM_OPT_SET_ARCH)
1059 target_arch_cpu = sel->core;
1061 if (i != ARM_OPT_SET_TUNE)
1063 /* If we have been given an architecture and a processor
1064 make sure that they are compatible. We only generate
1065 a warning though, and we prefer the CPU over the
1067 if (insn_flags != 0 && (insn_flags ^ sel->flags))
1068 warning (0, "switch -mcpu=%s conflicts with -march= switch",
1071 insn_flags = sel->flags;
1077 if (sel->name == NULL)
1078 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1082 /* Guess the tuning options from the architecture if necessary. */
1083 if (arm_tune == arm_none)
1084 arm_tune = target_arch_cpu;
1086 /* If the user did not specify a processor, choose one for them. */
1087 if (insn_flags == 0)
1089 const struct processors * sel;
1090 unsigned int sought;
1091 enum processor_type cpu;
1093 cpu = TARGET_CPU_DEFAULT;
1094 if (cpu == arm_none)
1096 #ifdef SUBTARGET_CPU_DEFAULT
1097 /* Use the subtarget default CPU if none was specified by
1099 cpu = SUBTARGET_CPU_DEFAULT;
1101 /* Default to ARM6. */
1102 if (cpu == arm_none)
1105 sel = &all_cores[cpu];
1107 insn_flags = sel->flags;
1109 /* Now check to see if the user has specified some command line
1110 switch that require certain abilities from the cpu. */
1113 if (TARGET_INTERWORK || TARGET_THUMB)
1115 sought |= (FL_THUMB | FL_MODE32);
1117 /* There are no ARM processors that support both APCS-26 and
1118 interworking. Therefore we force FL_MODE26 to be removed
1119 from insn_flags here (if it was set), so that the search
1120 below will always be able to find a compatible processor. */
1121 insn_flags &= ~FL_MODE26;
1124 if (sought != 0 && ((sought & insn_flags) != sought))
1126 /* Try to locate a CPU type that supports all of the abilities
1127 of the default CPU, plus the extra abilities requested by
1129 for (sel = all_cores; sel->name != NULL; sel++)
1130 if ((sel->flags & sought) == (sought | insn_flags))
1133 if (sel->name == NULL)
1135 unsigned current_bit_count = 0;
1136 const struct processors * best_fit = NULL;
1138 /* Ideally we would like to issue an error message here
1139 saying that it was not possible to find a CPU compatible
1140 with the default CPU, but which also supports the command
1141 line options specified by the programmer, and so they
1142 ought to use the -mcpu=<name> command line option to
1143 override the default CPU type.
1145 If we cannot find a cpu that has both the
1146 characteristics of the default cpu and the given
1147 command line options we scan the array again looking
1148 for a best match. */
1149 for (sel = all_cores; sel->name != NULL; sel++)
1150 if ((sel->flags & sought) == sought)
1154 count = bit_count (sel->flags & insn_flags);
1156 if (count >= current_bit_count)
1159 current_bit_count = count;
1163 gcc_assert (best_fit);
1167 insn_flags = sel->flags;
1169 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1170 arm_default_cpu = (enum processor_type) (sel - all_cores);
1171 if (arm_tune == arm_none)
1172 arm_tune = arm_default_cpu;
1175 /* The processor for which we should tune should now have been
1177 gcc_assert (arm_tune != arm_none);
1179 tune_flags = all_cores[(int)arm_tune].flags;
1181 targetm.rtx_costs = arm_size_rtx_costs;
1183 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1185 /* Make sure that the processor choice does not conflict with any of the
1186 other command line choices. */
1187 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1188 error ("target CPU does not support ARM mode");
1190 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1192 warning (0, "target CPU does not support interworking" );
1193 target_flags &= ~MASK_INTERWORK;
1196 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1198 warning (0, "target CPU does not support THUMB instructions");
1199 target_flags &= ~MASK_THUMB;
1202 if (TARGET_APCS_FRAME && TARGET_THUMB)
1204 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1205 target_flags &= ~MASK_APCS_FRAME;
1208 /* Callee super interworking implies thumb interworking. Adding
1209 this to the flags here simplifies the logic elsewhere. */
1210 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1211 target_flags |= MASK_INTERWORK;
1213 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1214 from here where no function is being compiled currently. */
1215 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1216 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1218 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1219 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1221 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1222 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1224 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1226 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1227 target_flags |= MASK_APCS_FRAME;
1230 if (TARGET_POKE_FUNCTION_NAME)
1231 target_flags |= MASK_APCS_FRAME;
1233 if (TARGET_APCS_REENT && flag_pic)
1234 error ("-fpic and -mapcs-reent are incompatible");
1236 if (TARGET_APCS_REENT)
1237 warning (0, "APCS reentrant code not supported. Ignored");
1239 /* If this target is normally configured to use APCS frames, warn if they
1240 are turned off and debugging is turned on. */
1242 && write_symbols != NO_DEBUG
1243 && !TARGET_APCS_FRAME
1244 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1245 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1247 if (TARGET_APCS_FLOAT)
1248 warning (0, "passing floating point arguments in fp regs not yet supported");
1250 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1251 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1252 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1253 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1254 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1255 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1256 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1257 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1258 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1259 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1260 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1261 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1263 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1264 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1265 thumb_code = (TARGET_ARM == 0);
1266 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1267 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1268 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1269 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1271 /* V5 code we generate is completely interworking capable, so we turn off
1272 TARGET_INTERWORK here to avoid many tests later on. */
1274 /* XXX However, we must pass the right pre-processor defines to CPP
1275 or GLD can get confused. This is a hack. */
1276 if (TARGET_INTERWORK)
1277 arm_cpp_interwork = 1;
1280 target_flags &= ~MASK_INTERWORK;
1282 if (target_abi_name)
1284 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1286 if (streq (arm_all_abis[i].name, target_abi_name))
1288 arm_abi = arm_all_abis[i].abi_type;
1292 if (i == ARRAY_SIZE (arm_all_abis))
1293 error ("invalid ABI option: -mabi=%s", target_abi_name);
1296 arm_abi = ARM_DEFAULT_ABI;
1298 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1299 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1301 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1302 error ("iwmmxt abi requires an iwmmxt capable cpu");
1304 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1305 if (target_fpu_name == NULL && target_fpe_name != NULL)
1307 if (streq (target_fpe_name, "2"))
1308 target_fpu_name = "fpe2";
1309 else if (streq (target_fpe_name, "3"))
1310 target_fpu_name = "fpe3";
1312 error ("invalid floating point emulation option: -mfpe=%s",
1315 if (target_fpu_name != NULL)
1317 /* The user specified a FPU. */
1318 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1320 if (streq (all_fpus[i].name, target_fpu_name))
1322 arm_fpu_arch = all_fpus[i].fpu;
1323 arm_fpu_tune = arm_fpu_arch;
1324 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1328 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1329 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1333 #ifdef FPUTYPE_DEFAULT
1334 /* Use the default if it is specified for this platform. */
1335 arm_fpu_arch = FPUTYPE_DEFAULT;
1336 arm_fpu_tune = FPUTYPE_DEFAULT;
1338 /* Pick one based on CPU type. */
1339 /* ??? Some targets assume FPA is the default.
1340 if ((insn_flags & FL_VFP) != 0)
1341 arm_fpu_arch = FPUTYPE_VFP;
1344 if (arm_arch_cirrus)
1345 arm_fpu_arch = FPUTYPE_MAVERICK;
1347 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1349 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1350 arm_fpu_tune = FPUTYPE_FPA;
1352 arm_fpu_tune = arm_fpu_arch;
1353 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1354 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1357 if (target_float_abi_name != NULL)
1359 /* The user specified a FP ABI. */
1360 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1362 if (streq (all_float_abis[i].name, target_float_abi_name))
1364 arm_float_abi = all_float_abis[i].abi_type;
1368 if (i == ARRAY_SIZE (all_float_abis))
1369 error ("invalid floating point abi: -mfloat-abi=%s",
1370 target_float_abi_name);
1373 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1375 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1376 sorry ("-mfloat-abi=hard and VFP");
1378 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1379 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1380 will ever exist. GCC makes no attempt to support this combination. */
1381 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1382 sorry ("iWMMXt and hardware floating point");
1384 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1385 if (TARGET_THUMB2 && TARGET_IWMMXT)
1386 sorry ("Thumb-2 iWMMXt");
1388 /* If soft-float is specified then don't use FPU. */
1389 if (TARGET_SOFT_FLOAT)
1390 arm_fpu_arch = FPUTYPE_NONE;
1392 /* For arm2/3 there is no need to do any scheduling if there is only
1393 a floating point emulator, or we are doing software floating-point. */
1394 if ((TARGET_SOFT_FLOAT
1395 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1396 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1397 && (tune_flags & FL_MODE32) == 0)
1398 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1400 if (target_thread_switch)
1402 if (strcmp (target_thread_switch, "soft") == 0)
1403 target_thread_pointer = TP_SOFT;
1404 else if (strcmp (target_thread_switch, "auto") == 0)
1405 target_thread_pointer = TP_AUTO;
1406 else if (strcmp (target_thread_switch, "cp15") == 0)
1407 target_thread_pointer = TP_CP15;
1409 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1412 /* Use the cp15 method if it is available. */
1413 if (target_thread_pointer == TP_AUTO)
1415 if (arm_arch6k && !TARGET_THUMB)
1416 target_thread_pointer = TP_CP15;
1418 target_thread_pointer = TP_SOFT;
1421 if (TARGET_HARD_TP && TARGET_THUMB1)
1422 error ("can not use -mtp=cp15 with 16-bit Thumb");
1424 /* Override the default structure alignment for AAPCS ABI. */
1425 if (TARGET_AAPCS_BASED)
1426 arm_structure_size_boundary = 8;
1428 if (structure_size_string != NULL)
1430 int size = strtol (structure_size_string, NULL, 0);
1432 if (size == 8 || size == 32
1433 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1434 arm_structure_size_boundary = size;
1436 warning (0, "structure size boundary can only be set to %s",
1437 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1440 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1442 error ("RTP PIC is incompatible with Thumb");
1446 /* If stack checking is disabled, we can use r10 as the PIC register,
1447 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1448 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1450 if (TARGET_VXWORKS_RTP)
1451 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1452 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1455 if (flag_pic && TARGET_VXWORKS_RTP)
1456 arm_pic_register = 9;
1458 if (arm_pic_register_string != NULL)
1460 int pic_register = decode_reg_name (arm_pic_register_string);
1463 warning (0, "-mpic-register= is useless without -fpic");
1465 /* Prevent the user from choosing an obviously stupid PIC register. */
1466 else if (pic_register < 0 || call_used_regs[pic_register]
1467 || pic_register == HARD_FRAME_POINTER_REGNUM
1468 || pic_register == STACK_POINTER_REGNUM
1469 || pic_register >= PC_REGNUM
1470 || (TARGET_VXWORKS_RTP
1471 && (unsigned int) pic_register != arm_pic_register))
1472 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1474 arm_pic_register = pic_register;
1477 /* ??? We might want scheduling for thumb2. */
1478 if (TARGET_THUMB && flag_schedule_insns)
1480 /* Don't warn since it's on by default in -O2. */
1481 flag_schedule_insns = 0;
1486 arm_constant_limit = 1;
1488 /* If optimizing for size, bump the number of instructions that we
1489 are prepared to conditionally execute (even on a StrongARM). */
1490 max_insns_skipped = 6;
1494 /* For processors with load scheduling, it never costs more than
1495 2 cycles to load a constant, and the load scheduler may well
1496 reduce that to 1. */
1498 arm_constant_limit = 1;
1500 /* On XScale the longer latency of a load makes it more difficult
1501 to achieve a good schedule, so it's faster to synthesize
1502 constants that can be done in two insns. */
1503 if (arm_tune_xscale)
1504 arm_constant_limit = 2;
1506 /* StrongARM has early execution of branches, so a sequence
1507 that is worth skipping is shorter. */
1508 if (arm_tune_strongarm)
1509 max_insns_skipped = 3;
1512 /* Register global variables with the garbage collector. */
1513 arm_add_gc_roots ();
1517 arm_add_gc_roots (void)
1519 gcc_obstack_init(&minipool_obstack);
1520 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1523 /* A table of known ARM exception types.
1524 For use with the interrupt function attribute. */
1528 const char *const arg;
1529 const unsigned long return_value;
1533 static const isr_attribute_arg isr_attribute_args [] =
1535 { "IRQ", ARM_FT_ISR },
1536 { "irq", ARM_FT_ISR },
1537 { "FIQ", ARM_FT_FIQ },
1538 { "fiq", ARM_FT_FIQ },
1539 { "ABORT", ARM_FT_ISR },
1540 { "abort", ARM_FT_ISR },
1541 { "ABORT", ARM_FT_ISR },
1542 { "abort", ARM_FT_ISR },
1543 { "UNDEF", ARM_FT_EXCEPTION },
1544 { "undef", ARM_FT_EXCEPTION },
1545 { "SWI", ARM_FT_EXCEPTION },
1546 { "swi", ARM_FT_EXCEPTION },
1547 { NULL, ARM_FT_NORMAL }
1550 /* Returns the (interrupt) function type of the current
1551 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1553 static unsigned long
1554 arm_isr_value (tree argument)
1556 const isr_attribute_arg * ptr;
1560 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1562 /* No argument - default to IRQ. */
1563 if (argument == NULL_TREE)
1566 /* Get the value of the argument. */
1567 if (TREE_VALUE (argument) == NULL_TREE
1568 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1569 return ARM_FT_UNKNOWN;
1571 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1573 /* Check it against the list of known arguments. */
1574 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1575 if (streq (arg, ptr->arg))
1576 return ptr->return_value;
1578 /* An unrecognized interrupt type. */
1579 return ARM_FT_UNKNOWN;
1582 /* Computes the type of the current function. */
1584 static unsigned long
1585 arm_compute_func_type (void)
1587 unsigned long type = ARM_FT_UNKNOWN;
1591 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1593 /* Decide if the current function is volatile. Such functions
1594 never return, and many memory cycles can be saved by not storing
1595 register values that will never be needed again. This optimization
1596 was added to speed up context switching in a kernel application. */
1598 && (TREE_NOTHROW (current_function_decl)
1599 || !(flag_unwind_tables
1600 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1601 && TREE_THIS_VOLATILE (current_function_decl))
1602 type |= ARM_FT_VOLATILE;
1604 if (cfun->static_chain_decl != NULL)
1605 type |= ARM_FT_NESTED;
1607 attr = DECL_ATTRIBUTES (current_function_decl);
1609 a = lookup_attribute ("naked", attr);
1611 type |= ARM_FT_NAKED;
1613 a = lookup_attribute ("isr", attr);
1615 a = lookup_attribute ("interrupt", attr);
1618 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1620 type |= arm_isr_value (TREE_VALUE (a));
1625 /* Returns the type of the current function. */
1628 arm_current_func_type (void)
1630 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1631 cfun->machine->func_type = arm_compute_func_type ();
1633 return cfun->machine->func_type;
1636 /* Return 1 if it is possible to return using a single instruction.
1637 If SIBLING is non-null, this is a test for a return before a sibling
1638 call. SIBLING is the call insn, so we can examine its register usage. */
1641 use_return_insn (int iscond, rtx sibling)
1644 unsigned int func_type;
1645 unsigned long saved_int_regs;
1646 unsigned HOST_WIDE_INT stack_adjust;
1647 arm_stack_offsets *offsets;
1649 /* Never use a return instruction before reload has run. */
1650 if (!reload_completed)
1653 func_type = arm_current_func_type ();
1655 /* Naked, volatile and stack alignment functions need special
1657 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1660 /* So do interrupt functions that use the frame pointer and Thumb
1661 interrupt functions. */
1662 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1665 offsets = arm_get_frame_offsets ();
1666 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1668 /* As do variadic functions. */
1669 if (current_function_pretend_args_size
1670 || cfun->machine->uses_anonymous_args
1671 /* Or if the function calls __builtin_eh_return () */
1672 || current_function_calls_eh_return
1673 /* Or if the function calls alloca */
1674 || current_function_calls_alloca
1675 /* Or if there is a stack adjustment. However, if the stack pointer
1676 is saved on the stack, we can use a pre-incrementing stack load. */
1677 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1680 saved_int_regs = arm_compute_save_reg_mask ();
1682 /* Unfortunately, the insn
1684 ldmib sp, {..., sp, ...}
1686 triggers a bug on most SA-110 based devices, such that the stack
1687 pointer won't be correctly restored if the instruction takes a
1688 page fault. We work around this problem by popping r3 along with
1689 the other registers, since that is never slower than executing
1690 another instruction.
1692 We test for !arm_arch5 here, because code for any architecture
1693 less than this could potentially be run on one of the buggy
1695 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1697 /* Validate that r3 is a call-clobbered register (always true in
1698 the default abi) ... */
1699 if (!call_used_regs[3])
1702 /* ... that it isn't being used for a return value ... */
1703 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1706 /* ... or for a tail-call argument ... */
1709 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1711 if (find_regno_fusage (sibling, USE, 3))
1715 /* ... and that there are no call-saved registers in r0-r2
1716 (always true in the default ABI). */
1717 if (saved_int_regs & 0x7)
1721 /* Can't be done if interworking with Thumb, and any registers have been
1723 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1726 /* On StrongARM, conditional returns are expensive if they aren't
1727 taken and multiple registers have been stacked. */
1728 if (iscond && arm_tune_strongarm)
1730 /* Conditional return when just the LR is stored is a simple
1731 conditional-load instruction, that's not expensive. */
1732 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1736 && arm_pic_register != INVALID_REGNUM
1737 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
1741 /* If there are saved registers but the LR isn't saved, then we need
1742 two instructions for the return. */
1743 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1746 /* Can't be done if any of the FPA regs are pushed,
1747 since this also requires an insn. */
1748 if (TARGET_HARD_FLOAT && TARGET_FPA)
1749 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1750 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
1753 /* Likewise VFP regs. */
1754 if (TARGET_HARD_FLOAT && TARGET_VFP)
1755 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1756 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
1759 if (TARGET_REALLY_IWMMXT)
1760 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1761 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1767 /* Return TRUE if int I is a valid immediate ARM constant. */
1770 const_ok_for_arm (HOST_WIDE_INT i)
1774 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1775 be all zero, or all one. */
1776 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1777 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1778 != ((~(unsigned HOST_WIDE_INT) 0)
1779 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1782 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1784 /* Fast return for 0 and small values. We must do this for zero, since
1785 the code below can't handle that one case. */
1786 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1789 /* Get the number of trailing zeros. */
1790 lowbit = ffs((int) i) - 1;
1792 /* Only even shifts are allowed in ARM mode so round down to the
1793 nearest even number. */
1797 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1802 /* Allow rotated constants in ARM mode. */
1804 && ((i & ~0xc000003f) == 0
1805 || (i & ~0xf000000f) == 0
1806 || (i & ~0xfc000003) == 0))
1813 /* Allow repeated pattern. */
1816 if (i == v || i == (v | (v << 8)))
1823 /* Return true if I is a valid constant for the operation CODE. */
1825 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1827 if (const_ok_for_arm (i))
1833 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1835 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1841 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1848 /* Emit a sequence of insns to handle a large constant.
1849 CODE is the code of the operation required, it can be any of SET, PLUS,
1850 IOR, AND, XOR, MINUS;
1851 MODE is the mode in which the operation is being performed;
1852 VAL is the integer to operate on;
1853 SOURCE is the other operand (a register, or a null-pointer for SET);
1854 SUBTARGETS means it is safe to create scratch registers if that will
1855 either produce a simpler sequence, or we will want to cse the values.
1856 Return value is the number of insns emitted. */
1858 /* ??? Tweak this for thumb2. */
1860 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1861 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1865 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1866 cond = COND_EXEC_TEST (PATTERN (insn));
1870 if (subtargets || code == SET
1871 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1872 && REGNO (target) != REGNO (source)))
1874 /* After arm_reorg has been called, we can't fix up expensive
1875 constants by pushing them into memory so we must synthesize
1876 them in-line, regardless of the cost. This is only likely to
1877 be more costly on chips that have load delay slots and we are
1878 compiling without running the scheduler (so no splitting
1879 occurred before the final instruction emission).
1881 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1883 if (!after_arm_reorg
1885 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1887 > arm_constant_limit + (code != SET)))
1891 /* Currently SET is the only monadic value for CODE, all
1892 the rest are diadic. */
1893 emit_set_insn (target, GEN_INT (val));
1898 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1900 emit_set_insn (temp, GEN_INT (val));
1901 /* For MINUS, the value is subtracted from, since we never
1902 have subtraction of a constant. */
1904 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1906 emit_set_insn (target,
1907 gen_rtx_fmt_ee (code, mode, source, temp));
1913 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1917 /* Return the number of ARM instructions required to synthesize the given
1920 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1922 HOST_WIDE_INT temp1;
1930 if (remainder & (3 << (i - 2)))
1935 temp1 = remainder & ((0x0ff << end)
1936 | ((i < end) ? (0xff >> (32 - end)) : 0));
1937 remainder &= ~temp1;
1942 } while (remainder);
1946 /* Emit an instruction with the indicated PATTERN. If COND is
1947 non-NULL, conditionalize the execution of the instruction on COND
1951 emit_constant_insn (rtx cond, rtx pattern)
1954 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1955 emit_insn (pattern);
1958 /* As above, but extra parameter GENERATE which, if clear, suppresses
1960 /* ??? This needs more work for thumb2. */
1963 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1964 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1969 int can_negate_initial = 0;
1972 int num_bits_set = 0;
1973 int set_sign_bit_copies = 0;
1974 int clear_sign_bit_copies = 0;
1975 int clear_zero_bit_copies = 0;
1976 int set_zero_bit_copies = 0;
1978 unsigned HOST_WIDE_INT temp1, temp2;
1979 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1981 /* Find out which operations are safe for a given CODE. Also do a quick
1982 check for degenerate cases; these can occur when DImode operations
1994 can_negate_initial = 1;
1998 if (remainder == 0xffffffff)
2001 emit_constant_insn (cond,
2002 gen_rtx_SET (VOIDmode, target,
2003 GEN_INT (ARM_SIGN_EXTEND (val))));
2008 if (reload_completed && rtx_equal_p (target, source))
2011 emit_constant_insn (cond,
2012 gen_rtx_SET (VOIDmode, target, source));
2021 emit_constant_insn (cond,
2022 gen_rtx_SET (VOIDmode, target, const0_rtx));
2025 if (remainder == 0xffffffff)
2027 if (reload_completed && rtx_equal_p (target, source))
2030 emit_constant_insn (cond,
2031 gen_rtx_SET (VOIDmode, target, source));
2040 if (reload_completed && rtx_equal_p (target, source))
2043 emit_constant_insn (cond,
2044 gen_rtx_SET (VOIDmode, target, source));
2048 /* We don't know how to handle other cases yet. */
2049 gcc_assert (remainder == 0xffffffff);
2052 emit_constant_insn (cond,
2053 gen_rtx_SET (VOIDmode, target,
2054 gen_rtx_NOT (mode, source)));
2058 /* We treat MINUS as (val - source), since (source - val) is always
2059 passed as (source + (-val)). */
2063 emit_constant_insn (cond,
2064 gen_rtx_SET (VOIDmode, target,
2065 gen_rtx_NEG (mode, source)));
2068 if (const_ok_for_arm (val))
2071 emit_constant_insn (cond,
2072 gen_rtx_SET (VOIDmode, target,
2073 gen_rtx_MINUS (mode, GEN_INT (val),
2085 /* If we can do it in one insn get out quickly. */
2086 if (const_ok_for_arm (val)
2087 || (can_negate_initial && const_ok_for_arm (-val))
2088 || (can_invert && const_ok_for_arm (~val)))
2091 emit_constant_insn (cond,
2092 gen_rtx_SET (VOIDmode, target,
2094 ? gen_rtx_fmt_ee (code, mode, source,
2100 /* Calculate a few attributes that may be useful for specific
2102 for (i = 31; i >= 0; i--)
2104 if ((remainder & (1 << i)) == 0)
2105 clear_sign_bit_copies++;
2110 for (i = 31; i >= 0; i--)
2112 if ((remainder & (1 << i)) != 0)
2113 set_sign_bit_copies++;
2118 for (i = 0; i <= 31; i++)
2120 if ((remainder & (1 << i)) == 0)
2121 clear_zero_bit_copies++;
2126 for (i = 0; i <= 31; i++)
2128 if ((remainder & (1 << i)) != 0)
2129 set_zero_bit_copies++;
2137 /* See if we can use movw. */
2138 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2141 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2146 /* See if we can do this by sign_extending a constant that is known
2147 to be negative. This is a good, way of doing it, since the shift
2148 may well merge into a subsequent insn. */
2149 if (set_sign_bit_copies > 1)
2151 if (const_ok_for_arm
2152 (temp1 = ARM_SIGN_EXTEND (remainder
2153 << (set_sign_bit_copies - 1))))
2157 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2158 emit_constant_insn (cond,
2159 gen_rtx_SET (VOIDmode, new_src,
2161 emit_constant_insn (cond,
2162 gen_ashrsi3 (target, new_src,
2163 GEN_INT (set_sign_bit_copies - 1)));
2167 /* For an inverted constant, we will need to set the low bits,
2168 these will be shifted out of harm's way. */
2169 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2170 if (const_ok_for_arm (~temp1))
2174 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2175 emit_constant_insn (cond,
2176 gen_rtx_SET (VOIDmode, new_src,
2178 emit_constant_insn (cond,
2179 gen_ashrsi3 (target, new_src,
2180 GEN_INT (set_sign_bit_copies - 1)));
2186 /* See if we can calculate the value as the difference between two
2187 valid immediates. */
2188 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2190 int topshift = clear_sign_bit_copies & ~1;
2192 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2193 & (0xff000000 >> topshift));
2195 /* If temp1 is zero, then that means the 9 most significant
2196 bits of remainder were 1 and we've caused it to overflow.
2197 When topshift is 0 we don't need to do anything since we
2198 can borrow from 'bit 32'. */
2199 if (temp1 == 0 && topshift != 0)
2200 temp1 = 0x80000000 >> (topshift - 1);
2202 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2204 if (const_ok_for_arm (temp2))
2208 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2209 emit_constant_insn (cond,
2210 gen_rtx_SET (VOIDmode, new_src,
2212 emit_constant_insn (cond,
2213 gen_addsi3 (target, new_src,
2221 /* See if we can generate this by setting the bottom (or the top)
2222 16 bits, and then shifting these into the other half of the
2223 word. We only look for the simplest cases, to do more would cost
2224 too much. Be careful, however, not to generate this when the
2225 alternative would take fewer insns. */
2226 if (val & 0xffff0000)
2228 temp1 = remainder & 0xffff0000;
2229 temp2 = remainder & 0x0000ffff;
2231 /* Overlaps outside this range are best done using other methods. */
2232 for (i = 9; i < 24; i++)
2234 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2235 && !const_ok_for_arm (temp2))
2237 rtx new_src = (subtargets
2238 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2240 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2241 source, subtargets, generate);
2249 gen_rtx_ASHIFT (mode, source,
2256 /* Don't duplicate cases already considered. */
2257 for (i = 17; i < 24; i++)
2259 if (((temp1 | (temp1 >> i)) == remainder)
2260 && !const_ok_for_arm (temp1))
2262 rtx new_src = (subtargets
2263 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2265 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2266 source, subtargets, generate);
2271 gen_rtx_SET (VOIDmode, target,
2274 gen_rtx_LSHIFTRT (mode, source,
2285 /* If we have IOR or XOR, and the constant can be loaded in a
2286 single instruction, and we can find a temporary to put it in,
2287 then this can be done in two instructions instead of 3-4. */
2289 /* TARGET can't be NULL if SUBTARGETS is 0 */
2290 || (reload_completed && !reg_mentioned_p (target, source)))
2292 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2296 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2298 emit_constant_insn (cond,
2299 gen_rtx_SET (VOIDmode, sub,
2301 emit_constant_insn (cond,
2302 gen_rtx_SET (VOIDmode, target,
2303 gen_rtx_fmt_ee (code, mode,
2313 if (set_sign_bit_copies > 8
2314 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2318 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2319 rtx shift = GEN_INT (set_sign_bit_copies);
2323 gen_rtx_SET (VOIDmode, sub,
2325 gen_rtx_ASHIFT (mode,
2330 gen_rtx_SET (VOIDmode, target,
2332 gen_rtx_LSHIFTRT (mode, sub,
2338 if (set_zero_bit_copies > 8
2339 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2343 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2344 rtx shift = GEN_INT (set_zero_bit_copies);
2348 gen_rtx_SET (VOIDmode, sub,
2350 gen_rtx_LSHIFTRT (mode,
2355 gen_rtx_SET (VOIDmode, target,
2357 gen_rtx_ASHIFT (mode, sub,
2363 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2367 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2368 emit_constant_insn (cond,
2369 gen_rtx_SET (VOIDmode, sub,
2370 gen_rtx_NOT (mode, source)));
2373 sub = gen_reg_rtx (mode);
2374 emit_constant_insn (cond,
2375 gen_rtx_SET (VOIDmode, sub,
2376 gen_rtx_AND (mode, source,
2378 emit_constant_insn (cond,
2379 gen_rtx_SET (VOIDmode, target,
2380 gen_rtx_NOT (mode, sub)));
2387 /* See if two shifts will do 2 or more insn's worth of work. */
2388 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2390 HOST_WIDE_INT shift_mask = ((0xffffffff
2391 << (32 - clear_sign_bit_copies))
2394 if ((remainder | shift_mask) != 0xffffffff)
2398 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2399 insns = arm_gen_constant (AND, mode, cond,
2400 remainder | shift_mask,
2401 new_src, source, subtargets, 1);
2406 rtx targ = subtargets ? NULL_RTX : target;
2407 insns = arm_gen_constant (AND, mode, cond,
2408 remainder | shift_mask,
2409 targ, source, subtargets, 0);
2415 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2416 rtx shift = GEN_INT (clear_sign_bit_copies);
2418 emit_insn (gen_ashlsi3 (new_src, source, shift));
2419 emit_insn (gen_lshrsi3 (target, new_src, shift));
2425 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2427 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2429 if ((remainder | shift_mask) != 0xffffffff)
2433 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2435 insns = arm_gen_constant (AND, mode, cond,
2436 remainder | shift_mask,
2437 new_src, source, subtargets, 1);
2442 rtx targ = subtargets ? NULL_RTX : target;
2444 insns = arm_gen_constant (AND, mode, cond,
2445 remainder | shift_mask,
2446 targ, source, subtargets, 0);
2452 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2453 rtx shift = GEN_INT (clear_zero_bit_copies);
2455 emit_insn (gen_lshrsi3 (new_src, source, shift));
2456 emit_insn (gen_ashlsi3 (target, new_src, shift));
2468 for (i = 0; i < 32; i++)
2469 if (remainder & (1 << i))
2472 if (code == AND || (can_invert && num_bits_set > 16))
2473 remainder = (~remainder) & 0xffffffff;
2474 else if (code == PLUS && num_bits_set > 16)
2475 remainder = (-remainder) & 0xffffffff;
2482 /* Now try and find a way of doing the job in either two or three
2484 We start by looking for the largest block of zeros that are aligned on
2485 a 2-bit boundary, we then fill up the temps, wrapping around to the
2486 top of the word when we drop off the bottom.
2487 In the worst case this code should produce no more than four insns.
2488 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2489 best place to start. */
2491 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2497 int best_consecutive_zeros = 0;
2499 for (i = 0; i < 32; i += 2)
2501 int consecutive_zeros = 0;
2503 if (!(remainder & (3 << i)))
2505 while ((i < 32) && !(remainder & (3 << i)))
2507 consecutive_zeros += 2;
2510 if (consecutive_zeros > best_consecutive_zeros)
2512 best_consecutive_zeros = consecutive_zeros;
2513 best_start = i - consecutive_zeros;
2519 /* So long as it won't require any more insns to do so, it's
2520 desirable to emit a small constant (in bits 0...9) in the last
2521 insn. This way there is more chance that it can be combined with
2522 a later addressing insn to form a pre-indexed load or store
2523 operation. Consider:
2525 *((volatile int *)0xe0000100) = 1;
2526 *((volatile int *)0xe0000110) = 2;
2528 We want this to wind up as:
2532 str rB, [rA, #0x100]
2534 str rB, [rA, #0x110]
2536 rather than having to synthesize both large constants from scratch.
2538 Therefore, we calculate how many insns would be required to emit
2539 the constant starting from `best_start', and also starting from
2540 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2541 yield a shorter sequence, we may as well use zero. */
2543 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2544 && (count_insns_for_constant (remainder, 0) <=
2545 count_insns_for_constant (remainder, best_start)))
2549 /* Now start emitting the insns. */
2557 if (remainder & (3 << (i - 2)))
2562 temp1 = remainder & ((0x0ff << end)
2563 | ((i < end) ? (0xff >> (32 - end)) : 0));
2564 remainder &= ~temp1;
2568 rtx new_src, temp1_rtx;
2570 if (code == SET || code == MINUS)
2572 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2573 if (can_invert && code != MINUS)
2578 if (remainder && subtargets)
2579 new_src = gen_reg_rtx (mode);
2584 else if (can_negate)
2588 temp1 = trunc_int_for_mode (temp1, mode);
2589 temp1_rtx = GEN_INT (temp1);
2593 else if (code == MINUS)
2594 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2596 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2598 emit_constant_insn (cond,
2599 gen_rtx_SET (VOIDmode, new_src,
2609 else if (code == MINUS)
2618 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2631 /* Canonicalize a comparison so that we are more likely to recognize it.
2632 This can be done for a few constant compares, where we can make the
2633 immediate value easier to load. */
2636 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2639 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2640 unsigned HOST_WIDE_INT maxval;
2641 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2652 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2654 *op1 = GEN_INT (i + 1);
2655 return code == GT ? GE : LT;
2662 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2664 *op1 = GEN_INT (i - 1);
2665 return code == GE ? GT : LE;
2671 if (i != ~((unsigned HOST_WIDE_INT) 0)
2672 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2674 *op1 = GEN_INT (i + 1);
2675 return code == GTU ? GEU : LTU;
2682 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2684 *op1 = GEN_INT (i - 1);
2685 return code == GEU ? GTU : LEU;
2697 /* Define how to find the value returned by a function. */
2700 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2702 enum machine_mode mode;
2703 int unsignedp ATTRIBUTE_UNUSED;
2704 rtx r ATTRIBUTE_UNUSED;
2706 mode = TYPE_MODE (type);
2707 /* Promote integer types. */
2708 if (INTEGRAL_TYPE_P (type))
2709 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2711 /* Promotes small structs returned in a register to full-word size
2712 for big-endian AAPCS. */
2713 if (arm_return_in_msb (type))
2715 HOST_WIDE_INT size = int_size_in_bytes (type);
2716 if (size % UNITS_PER_WORD != 0)
2718 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2719 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2723 return LIBCALL_VALUE(mode);
2726 /* Determine the amount of memory needed to store the possible return
2727 registers of an untyped call. */
2729 arm_apply_result_size (void)
2735 if (TARGET_HARD_FLOAT_ABI)
2739 if (TARGET_MAVERICK)
2742 if (TARGET_IWMMXT_ABI)
2749 /* Decide whether a type should be returned in memory (true)
2750 or in a register (false). This is called by the macro
2751 RETURN_IN_MEMORY. */
2753 arm_return_in_memory (tree type)
2757 if (!AGGREGATE_TYPE_P (type) &&
2758 (TREE_CODE (type) != VECTOR_TYPE) &&
2759 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2760 /* All simple types are returned in registers.
2761 For AAPCS, complex types are treated the same as aggregates. */
2764 size = int_size_in_bytes (type);
2766 if (arm_abi != ARM_ABI_APCS)
2768 /* ATPCS and later return aggregate types in memory only if they are
2769 larger than a word (or are variable size). */
2770 return (size < 0 || size > UNITS_PER_WORD);
2773 /* To maximize backwards compatibility with previous versions of gcc,
2774 return vectors up to 4 words in registers. */
2775 if (TREE_CODE (type) == VECTOR_TYPE)
2776 return (size < 0 || size > (4 * UNITS_PER_WORD));
2778 /* For the arm-wince targets we choose to be compatible with Microsoft's
2779 ARM and Thumb compilers, which always return aggregates in memory. */
2781 /* All structures/unions bigger than one word are returned in memory.
2782 Also catch the case where int_size_in_bytes returns -1. In this case
2783 the aggregate is either huge or of variable size, and in either case
2784 we will want to return it via memory and not in a register. */
2785 if (size < 0 || size > UNITS_PER_WORD)
2788 if (TREE_CODE (type) == RECORD_TYPE)
2792 /* For a struct the APCS says that we only return in a register
2793 if the type is 'integer like' and every addressable element
2794 has an offset of zero. For practical purposes this means
2795 that the structure can have at most one non bit-field element
2796 and that this element must be the first one in the structure. */
2798 /* Find the first field, ignoring non FIELD_DECL things which will
2799 have been created by C++. */
2800 for (field = TYPE_FIELDS (type);
2801 field && TREE_CODE (field) != FIELD_DECL;
2802 field = TREE_CHAIN (field))
2806 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2808 /* Check that the first field is valid for returning in a register. */
2810 /* ... Floats are not allowed */
2811 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2814 /* ... Aggregates that are not themselves valid for returning in
2815 a register are not allowed. */
2816 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2819 /* Now check the remaining fields, if any. Only bitfields are allowed,
2820 since they are not addressable. */
2821 for (field = TREE_CHAIN (field);
2823 field = TREE_CHAIN (field))
2825 if (TREE_CODE (field) != FIELD_DECL)
2828 if (!DECL_BIT_FIELD_TYPE (field))
2835 if (TREE_CODE (type) == UNION_TYPE)
2839 /* Unions can be returned in registers if every element is
2840 integral, or can be returned in an integer register. */
2841 for (field = TYPE_FIELDS (type);
2843 field = TREE_CHAIN (field))
2845 if (TREE_CODE (field) != FIELD_DECL)
2848 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2851 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2857 #endif /* not ARM_WINCE */
2859 /* Return all other types in memory. */
2863 /* Indicate whether or not words of a double are in big-endian order. */
2866 arm_float_words_big_endian (void)
2868 if (TARGET_MAVERICK)
2871 /* For FPA, float words are always big-endian. For VFP, floats words
2872 follow the memory system mode. */
2880 return (TARGET_BIG_END ? 1 : 0);
2885 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2886 for a call to a function whose data type is FNTYPE.
2887 For a library call, FNTYPE is NULL. */
2889 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2890 rtx libname ATTRIBUTE_UNUSED,
2891 tree fndecl ATTRIBUTE_UNUSED)
2893 /* On the ARM, the offset starts at 0. */
2895 pcum->iwmmxt_nregs = 0;
2896 pcum->can_split = true;
2898 /* Varargs vectors are treated the same as long long.
2899 named_count avoids having to change the way arm handles 'named' */
2900 pcum->named_count = 0;
2903 if (TARGET_REALLY_IWMMXT && fntype)
2907 for (fn_arg = TYPE_ARG_TYPES (fntype);
2909 fn_arg = TREE_CHAIN (fn_arg))
2910 pcum->named_count += 1;
2912 if (! pcum->named_count)
2913 pcum->named_count = INT_MAX;
2918 /* Return true if mode/type need doubleword alignment. */
2920 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2922 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2923 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2927 /* Determine where to put an argument to a function.
2928 Value is zero to push the argument on the stack,
2929 or a hard register in which to store the argument.
2931 MODE is the argument's machine mode.
2932 TYPE is the data type of the argument (as a tree).
2933 This is null for libcalls where that information may
2935 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2936 the preceding args and about the function being called.
2937 NAMED is nonzero if this argument is a named parameter
2938 (otherwise it is an extra parameter matching an ellipsis). */
2941 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2942 tree type, int named)
2946 /* Varargs vectors are treated the same as long long.
2947 named_count avoids having to change the way arm handles 'named' */
2948 if (TARGET_IWMMXT_ABI
2949 && arm_vector_mode_supported_p (mode)
2950 && pcum->named_count > pcum->nargs + 1)
2952 if (pcum->iwmmxt_nregs <= 9)
2953 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2956 pcum->can_split = false;
2961 /* Put doubleword aligned quantities in even register pairs. */
2963 && ARM_DOUBLEWORD_ALIGN
2964 && arm_needs_doubleword_align (mode, type))
2967 if (mode == VOIDmode)
2968 /* Pick an arbitrary value for operand 2 of the call insn. */
2971 /* Only allow splitting an arg between regs and memory if all preceding
2972 args were allocated to regs. For args passed by reference we only count
2973 the reference pointer. */
2974 if (pcum->can_split)
2977 nregs = ARM_NUM_REGS2 (mode, type);
2979 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2982 return gen_rtx_REG (mode, pcum->nregs);
2986 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2987 tree type, bool named ATTRIBUTE_UNUSED)
2989 int nregs = pcum->nregs;
2991 if (arm_vector_mode_supported_p (mode))
2994 if (NUM_ARG_REGS > nregs
2995 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2997 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
3002 /* Variable sized types are passed by reference. This is a GCC
3003 extension to the ARM ABI. */
3006 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3007 enum machine_mode mode ATTRIBUTE_UNUSED,
3008 tree type, bool named ATTRIBUTE_UNUSED)
3010 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3013 /* Encode the current state of the #pragma [no_]long_calls. */
3016 OFF, /* No #pragma [no_]long_calls is in effect. */
3017 LONG, /* #pragma long_calls is in effect. */
3018 SHORT /* #pragma no_long_calls is in effect. */
3021 static arm_pragma_enum arm_pragma_long_calls = OFF;
3024 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3026 arm_pragma_long_calls = LONG;
3030 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3032 arm_pragma_long_calls = SHORT;
3036 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3038 arm_pragma_long_calls = OFF;
3041 /* Table of machine attributes. */
3042 const struct attribute_spec arm_attribute_table[] =
3044 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3045 /* Function calls made to this symbol must be done indirectly, because
3046 it may lie outside of the 26 bit addressing range of a normal function
3048 { "long_call", 0, 0, false, true, true, NULL },
3049 /* Whereas these functions are always known to reside within the 26 bit
3050 addressing range. */
3051 { "short_call", 0, 0, false, true, true, NULL },
3052 /* Interrupt Service Routines have special prologue and epilogue requirements. */
3053 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
3054 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
3055 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3057 /* ARM/PE has three new attributes:
3059 dllexport - for exporting a function/variable that will live in a dll
3060 dllimport - for importing a function/variable from a dll
3062 Microsoft allows multiple declspecs in one __declspec, separating
3063 them with spaces. We do NOT support this. Instead, use __declspec
3066 { "dllimport", 0, 0, true, false, false, NULL },
3067 { "dllexport", 0, 0, true, false, false, NULL },
3068 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3069 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
3070 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
3071 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
3072 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
3074 { NULL, 0, 0, false, false, false, NULL }
3077 /* Handle an attribute requiring a FUNCTION_DECL;
3078 arguments as in struct attribute_spec.handler. */
3080 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
3081 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
3083 if (TREE_CODE (*node) != FUNCTION_DECL)
3085 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3086 IDENTIFIER_POINTER (name));
3087 *no_add_attrs = true;
3093 /* Handle an "interrupt" or "isr" attribute;
3094 arguments as in struct attribute_spec.handler. */
3096 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3101 if (TREE_CODE (*node) != FUNCTION_DECL)
3103 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3104 IDENTIFIER_POINTER (name));
3105 *no_add_attrs = true;
3107 /* FIXME: the argument if any is checked for type attributes;
3108 should it be checked for decl ones? */
3112 if (TREE_CODE (*node) == FUNCTION_TYPE
3113 || TREE_CODE (*node) == METHOD_TYPE)
3115 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3117 warning (OPT_Wattributes, "%qs attribute ignored",
3118 IDENTIFIER_POINTER (name));
3119 *no_add_attrs = true;
3122 else if (TREE_CODE (*node) == POINTER_TYPE
3123 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3124 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3125 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3127 *node = build_variant_type_copy (*node);
3128 TREE_TYPE (*node) = build_type_attribute_variant
3130 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3131 *no_add_attrs = true;
3135 /* Possibly pass this attribute on from the type to a decl. */
3136 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3137 | (int) ATTR_FLAG_FUNCTION_NEXT
3138 | (int) ATTR_FLAG_ARRAY_NEXT))
3140 *no_add_attrs = true;
3141 return tree_cons (name, args, NULL_TREE);
3145 warning (OPT_Wattributes, "%qs attribute ignored",
3146 IDENTIFIER_POINTER (name));
3154 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3155 /* Handle the "notshared" attribute. This attribute is another way of
3156 requesting hidden visibility. ARM's compiler supports
3157 "__declspec(notshared)"; we support the same thing via an
3161 arm_handle_notshared_attribute (tree *node,
3162 tree name ATTRIBUTE_UNUSED,
3163 tree args ATTRIBUTE_UNUSED,
3164 int flags ATTRIBUTE_UNUSED,
3167 tree decl = TYPE_NAME (*node);
3171 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3172 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3173 *no_add_attrs = false;
3179 /* Return 0 if the attributes for two types are incompatible, 1 if they
3180 are compatible, and 2 if they are nearly compatible (which causes a
3181 warning to be generated). */
3183 arm_comp_type_attributes (tree type1, tree type2)
3187 /* Check for mismatch of non-default calling convention. */
3188 if (TREE_CODE (type1) != FUNCTION_TYPE)
3191 /* Check for mismatched call attributes. */
3192 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3193 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3194 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3195 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3197 /* Only bother to check if an attribute is defined. */
3198 if (l1 | l2 | s1 | s2)
3200 /* If one type has an attribute, the other must have the same attribute. */
3201 if ((l1 != l2) || (s1 != s2))
3204 /* Disallow mixed attributes. */
3205 if ((l1 & s2) || (l2 & s1))
3209 /* Check for mismatched ISR attribute. */
3210 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3212 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3213 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3215 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3222 /* Assigns default attributes to newly defined type. This is used to
3223 set short_call/long_call attributes for function types of
3224 functions defined inside corresponding #pragma scopes. */
3226 arm_set_default_type_attributes (tree type)
3228 /* Add __attribute__ ((long_call)) to all functions, when
3229 inside #pragma long_calls or __attribute__ ((short_call)),
3230 when inside #pragma no_long_calls. */
3231 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3233 tree type_attr_list, attr_name;
3234 type_attr_list = TYPE_ATTRIBUTES (type);
3236 if (arm_pragma_long_calls == LONG)
3237 attr_name = get_identifier ("long_call");
3238 else if (arm_pragma_long_calls == SHORT)
3239 attr_name = get_identifier ("short_call");
3243 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3244 TYPE_ATTRIBUTES (type) = type_attr_list;
3248 /* Return true if DECL is known to be linked into section SECTION. */
3251 arm_function_in_section_p (tree decl, section *section)
3253 /* We can only be certain about functions defined in the same
3254 compilation unit. */
3255 if (!TREE_STATIC (decl))
3258 /* Make sure that SYMBOL always binds to the definition in this
3259 compilation unit. */
3260 if (!targetm.binds_local_p (decl))
3263 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3264 if (!DECL_SECTION_NAME (decl))
3266 /* Only cater for unit-at-a-time mode, where we know that the user
3267 cannot later specify a section for DECL. */
3268 if (!flag_unit_at_a_time)
3271 /* Make sure that we will not create a unique section for DECL. */
3272 if (flag_function_sections || DECL_ONE_ONLY (decl))
3276 return function_section (decl) == section;
3279 /* Return nonzero if a 32-bit "long_call" should be generated for
3280 a call from the current function to DECL. We generate a long_call
3283 a. has an __attribute__((long call))
3284 or b. is within the scope of a #pragma long_calls
3285 or c. the -mlong-calls command line switch has been specified
3287 However we do not generate a long call if the function:
3289 d. has an __attribute__ ((short_call))
3290 or e. is inside the scope of a #pragma no_long_calls
3291 or f. is defined in the same section as the current function. */
3294 arm_is_long_call_p (tree decl)
3299 return TARGET_LONG_CALLS;
3301 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3302 if (lookup_attribute ("short_call", attrs))
3305 /* For "f", be conservative, and only cater for cases in which the
3306 whole of the current function is placed in the same section. */
3307 if (!flag_reorder_blocks_and_partition
3308 && arm_function_in_section_p (decl, current_function_section ()))
3311 if (lookup_attribute ("long_call", attrs))
3314 return TARGET_LONG_CALLS;
3317 /* Return nonzero if it is ok to make a tail-call to DECL. */
3319 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3321 unsigned long func_type;
3323 if (cfun->machine->sibcall_blocked)
3326 /* Never tailcall something for which we have no decl, or if we
3327 are in Thumb mode. */
3328 if (decl == NULL || TARGET_THUMB)
3331 /* The PIC register is live on entry to VxWorks PLT entries, so we
3332 must make the call before restoring the PIC register. */
3333 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
3336 /* Cannot tail-call to long calls, since these are out of range of
3337 a branch instruction. */
3338 if (arm_is_long_call_p (decl))
3341 /* If we are interworking and the function is not declared static
3342 then we can't tail-call it unless we know that it exists in this
3343 compilation unit (since it might be a Thumb routine). */
3344 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3347 func_type = arm_current_func_type ();
3348 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3349 if (IS_INTERRUPT (func_type))
3352 /* Never tailcall if function may be called with a misaligned SP. */
3353 if (IS_STACKALIGN (func_type))
3356 /* Everything else is ok. */
3361 /* Addressing mode support functions. */
3363 /* Return nonzero if X is a legitimate immediate operand when compiling
3364 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3366 legitimate_pic_operand_p (rtx x)
3368 if (GET_CODE (x) == SYMBOL_REF
3369 || (GET_CODE (x) == CONST
3370 && GET_CODE (XEXP (x, 0)) == PLUS
3371 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3377 /* Record that the current function needs a PIC register. Initialize
3378 cfun->machine->pic_reg if we have not already done so. */
3381 require_pic_register (void)
3383 /* A lot of the logic here is made obscure by the fact that this
3384 routine gets called as part of the rtx cost estimation process.
3385 We don't want those calls to affect any assumptions about the real
3386 function; and further, we can't call entry_of_function() until we
3387 start the real expansion process. */
3388 if (!current_function_uses_pic_offset_table)
3390 gcc_assert (can_create_pseudo_p ());
3391 if (arm_pic_register != INVALID_REGNUM)
3393 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3395 /* Play games to avoid marking the function as needing pic
3396 if we are being called as part of the cost-estimation
3398 if (current_ir_type () != IR_GIMPLE)
3399 current_function_uses_pic_offset_table = 1;
3405 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3407 /* Play games to avoid marking the function as needing pic
3408 if we are being called as part of the cost-estimation
3410 if (current_ir_type () != IR_GIMPLE)
3412 current_function_uses_pic_offset_table = 1;
3415 arm_load_pic_register (0UL);
3419 emit_insn_after (seq, entry_of_function ());
3426 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3428 if (GET_CODE (orig) == SYMBOL_REF
3429 || GET_CODE (orig) == LABEL_REF)
3431 #ifndef AOF_ASSEMBLER
3432 rtx pic_ref, address;
3437 /* If this function doesn't have a pic register, create one now. */
3438 require_pic_register ();
3442 gcc_assert (can_create_pseudo_p ());
3443 reg = gen_reg_rtx (Pmode);
3448 #ifdef AOF_ASSEMBLER
3449 /* The AOF assembler can generate relocations for these directly, and
3450 understands that the PIC register has to be added into the offset. */
3451 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3454 address = gen_reg_rtx (Pmode);
3459 emit_insn (gen_pic_load_addr_arm (address, orig));
3460 else if (TARGET_THUMB2)
3461 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3462 else /* TARGET_THUMB1 */
3463 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3465 /* VxWorks does not impose a fixed gap between segments; the run-time
3466 gap can be different from the object-file gap. We therefore can't
3467 use GOTOFF unless we are absolutely sure that the symbol is in the
3468 same segment as the GOT. Unfortunately, the flexibility of linker
3469 scripts means that we can't be sure of that in general, so assume
3470 that GOTOFF is never valid on VxWorks. */
3471 if ((GET_CODE (orig) == LABEL_REF
3472 || (GET_CODE (orig) == SYMBOL_REF &&
3473 SYMBOL_REF_LOCAL_P (orig)))
3475 && !TARGET_VXWORKS_RTP)
3476 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3479 pic_ref = gen_const_mem (Pmode,
3480 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3484 insn = emit_move_insn (reg, pic_ref);
3486 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3488 set_unique_reg_note (insn, REG_EQUAL, orig);
3492 else if (GET_CODE (orig) == CONST)
3496 if (GET_CODE (XEXP (orig, 0)) == PLUS
3497 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3500 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3501 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3506 gcc_assert (can_create_pseudo_p ());
3507 reg = gen_reg_rtx (Pmode);
3510 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3512 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3513 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3514 base == reg ? 0 : reg);
3516 if (GET_CODE (offset) == CONST_INT)
3518 /* The base register doesn't really matter, we only want to
3519 test the index for the appropriate mode. */
3520 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3522 gcc_assert (can_create_pseudo_p ());
3523 offset = force_reg (Pmode, offset);
3526 if (GET_CODE (offset) == CONST_INT)
3527 return plus_constant (base, INTVAL (offset));
3530 if (GET_MODE_SIZE (mode) > 4
3531 && (GET_MODE_CLASS (mode) == MODE_INT
3532 || TARGET_SOFT_FLOAT))
3534 emit_insn (gen_addsi3 (reg, base, offset));
3538 return gen_rtx_PLUS (Pmode, base, offset);
3545 /* Find a spare register to use during the prolog of a function. */
3548 thumb_find_work_register (unsigned long pushed_regs_mask)
3552 /* Check the argument registers first as these are call-used. The
3553 register allocation order means that sometimes r3 might be used
3554 but earlier argument registers might not, so check them all. */
3555 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3556 if (!df_regs_ever_live_p (reg))
3559 /* Before going on to check the call-saved registers we can try a couple
3560 more ways of deducing that r3 is available. The first is when we are
3561 pushing anonymous arguments onto the stack and we have less than 4
3562 registers worth of fixed arguments(*). In this case r3 will be part of
3563 the variable argument list and so we can be sure that it will be
3564 pushed right at the start of the function. Hence it will be available
3565 for the rest of the prologue.
3566 (*): ie current_function_pretend_args_size is greater than 0. */
3567 if (cfun->machine->uses_anonymous_args
3568 && current_function_pretend_args_size > 0)
3569 return LAST_ARG_REGNUM;
3571 /* The other case is when we have fixed arguments but less than 4 registers
3572 worth. In this case r3 might be used in the body of the function, but
3573 it is not being used to convey an argument into the function. In theory
3574 we could just check current_function_args_size to see how many bytes are
3575 being passed in argument registers, but it seems that it is unreliable.
3576 Sometimes it will have the value 0 when in fact arguments are being
3577 passed. (See testcase execute/20021111-1.c for an example). So we also
3578 check the args_info.nregs field as well. The problem with this field is
3579 that it makes no allowances for arguments that are passed to the
3580 function but which are not used. Hence we could miss an opportunity
3581 when a function has an unused argument in r3. But it is better to be
3582 safe than to be sorry. */
3583 if (! cfun->machine->uses_anonymous_args
3584 && current_function_args_size >= 0
3585 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3586 && cfun->args_info.nregs < 4)
3587 return LAST_ARG_REGNUM;
3589 /* Otherwise look for a call-saved register that is going to be pushed. */
3590 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3591 if (pushed_regs_mask & (1 << reg))
3596 /* Thumb-2 can use high regs. */
3597 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3598 if (pushed_regs_mask & (1 << reg))
3601 /* Something went wrong - thumb_compute_save_reg_mask()
3602 should have arranged for a suitable register to be pushed. */
3606 static GTY(()) int pic_labelno;
3608 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3612 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3614 #ifndef AOF_ASSEMBLER
3615 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
3616 rtx global_offset_table;
3618 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3621 gcc_assert (flag_pic);
3623 pic_reg = cfun->machine->pic_reg;
3624 if (TARGET_VXWORKS_RTP)
3626 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
3627 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3628 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3630 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
3632 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
3633 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
3637 /* We use an UNSPEC rather than a LABEL_REF because this label
3638 never appears in the code stream. */
3640 labelno = GEN_INT (pic_labelno++);
3641 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3642 l1 = gen_rtx_CONST (VOIDmode, l1);
3645 = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3646 /* On the ARM the PC register contains 'dot + 8' at the time of the
3647 addition, on the Thumb it is 'dot + 4'. */
3648 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3651 pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
3652 pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
3655 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3657 pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
3658 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3662 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3663 emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno));
3665 else if (TARGET_THUMB2)
3667 /* Thumb-2 only allows very limited access to the PC. Calculate the
3668 address in a temporary register. */
3669 if (arm_pic_register != INVALID_REGNUM)
3671 pic_tmp = gen_rtx_REG (SImode,
3672 thumb_find_work_register (saved_regs));
3676 gcc_assert (can_create_pseudo_p ());
3677 pic_tmp = gen_reg_rtx (Pmode);
3680 emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx));
3681 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3682 emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp));
3684 else /* TARGET_THUMB1 */
3686 if (arm_pic_register != INVALID_REGNUM
3687 && REGNO (pic_reg) > LAST_LO_REGNUM)
3689 /* We will have pushed the pic register, so we should always be
3690 able to find a work register. */
3691 pic_tmp = gen_rtx_REG (SImode,
3692 thumb_find_work_register (saved_regs));
3693 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3694 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3697 emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx));
3698 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
3702 /* Need to emit this whether or not we obey regdecls,
3703 since setjmp/longjmp can cause life info to screw up. */
3704 emit_insn (gen_rtx_USE (VOIDmode, pic_reg));
3705 #endif /* AOF_ASSEMBLER */
3709 /* Return nonzero if X is valid as an ARM state addressing register. */
3711 arm_address_register_rtx_p (rtx x, int strict_p)
3715 if (GET_CODE (x) != REG)
3721 return ARM_REGNO_OK_FOR_BASE_P (regno);
3723 return (regno <= LAST_ARM_REGNUM
3724 || regno >= FIRST_PSEUDO_REGISTER
3725 || regno == FRAME_POINTER_REGNUM
3726 || regno == ARG_POINTER_REGNUM);
3729 /* Return TRUE if this rtx is the difference of a symbol and a label,
3730 and will reduce to a PC-relative relocation in the object file.
3731 Expressions like this can be left alone when generating PIC, rather
3732 than forced through the GOT. */
3734 pcrel_constant_p (rtx x)
3736 if (GET_CODE (x) == MINUS)
3737 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3742 /* Return nonzero if X is a valid ARM state address operand. */
3744 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3748 enum rtx_code code = GET_CODE (x);
3750 if (arm_address_register_rtx_p (x, strict_p))
3753 use_ldrd = (TARGET_LDRD
3755 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3757 if (code == POST_INC || code == PRE_DEC
3758 || ((code == PRE_INC || code == POST_DEC)
3759 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3760 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3762 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3763 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3764 && GET_CODE (XEXP (x, 1)) == PLUS
3765 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3767 rtx addend = XEXP (XEXP (x, 1), 1);
3769 /* Don't allow ldrd post increment by register because it's hard
3770 to fixup invalid register choices. */
3772 && GET_CODE (x) == POST_MODIFY
3773 && GET_CODE (addend) == REG)
3776 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3777 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3780 /* After reload constants split into minipools will have addresses
3781 from a LABEL_REF. */
3782 else if (reload_completed
3783 && (code == LABEL_REF
3785 && GET_CODE (XEXP (x, 0)) == PLUS
3786 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3787 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3790 else if (mode == TImode)
3793 else if (code == PLUS)
3795 rtx xop0 = XEXP (x, 0);
3796 rtx xop1 = XEXP (x, 1);
3798 return ((arm_address_register_rtx_p (xop0, strict_p)
3799 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3800 || (arm_address_register_rtx_p (xop1, strict_p)
3801 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3805 /* Reload currently can't handle MINUS, so disable this for now */
3806 else if (GET_CODE (x) == MINUS)
3808 rtx xop0 = XEXP (x, 0);
3809 rtx xop1 = XEXP (x, 1);
3811 return (arm_address_register_rtx_p (xop0, strict_p)
3812 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3816 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3817 && code == SYMBOL_REF
3818 && CONSTANT_POOL_ADDRESS_P (x)
3820 && symbol_mentioned_p (get_pool_constant (x))
3821 && ! pcrel_constant_p (get_pool_constant (x))))
3827 /* Return nonzero if X is a valid Thumb-2 address operand. */
3829 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3832 enum rtx_code code = GET_CODE (x);
3834 if (arm_address_register_rtx_p (x, strict_p))
3837 use_ldrd = (TARGET_LDRD
3839 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3841 if (code == POST_INC || code == PRE_DEC
3842 || ((code == PRE_INC || code == POST_DEC)
3843 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3844 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3846 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3847 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3848 && GET_CODE (XEXP (x, 1)) == PLUS
3849 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3851 /* Thumb-2 only has autoincrement by constant. */
3852 rtx addend = XEXP (XEXP (x, 1), 1);
3853 HOST_WIDE_INT offset;
3855 if (GET_CODE (addend) != CONST_INT)
3858 offset = INTVAL(addend);
3859 if (GET_MODE_SIZE (mode) <= 4)
3860 return (offset > -256 && offset < 256);
3862 return (use_ldrd && offset > -1024 && offset < 1024
3863 && (offset & 3) == 0);
3866 /* After reload constants split into minipools will have addresses
3867 from a LABEL_REF. */
3868 else if (reload_completed
3869 && (code == LABEL_REF
3871 && GET_CODE (XEXP (x, 0)) == PLUS
3872 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3873 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3876 else if (mode == TImode)
3879 else if (code == PLUS)
3881 rtx xop0 = XEXP (x, 0);
3882 rtx xop1 = XEXP (x, 1);
3884 return ((arm_address_register_rtx_p (xop0, strict_p)
3885 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3886 || (arm_address_register_rtx_p (xop1, strict_p)
3887 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3890 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3891 && code == SYMBOL_REF
3892 && CONSTANT_POOL_ADDRESS_P (x)
3894 && symbol_mentioned_p (get_pool_constant (x))
3895 && ! pcrel_constant_p (get_pool_constant (x))))
3901 /* Return nonzero if INDEX is valid for an address index operand in
3904 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3907 HOST_WIDE_INT range;
3908 enum rtx_code code = GET_CODE (index);
3910 /* Standard coprocessor addressing modes. */
3911 if (TARGET_HARD_FLOAT
3912 && (TARGET_FPA || TARGET_MAVERICK)
3913 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3914 || (TARGET_MAVERICK && mode == DImode)))
3915 return (code == CONST_INT && INTVAL (index) < 1024
3916 && INTVAL (index) > -1024
3917 && (INTVAL (index) & 3) == 0);
3919 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3920 return (code == CONST_INT
3921 && INTVAL (index) < 1024
3922 && INTVAL (index) > -1024
3923 && (INTVAL (index) & 3) == 0);
3925 if (arm_address_register_rtx_p (index, strict_p)
3926 && (GET_MODE_SIZE (mode) <= 4))
3929 if (mode == DImode || mode == DFmode)
3931 if (code == CONST_INT)
3933 HOST_WIDE_INT val = INTVAL (index);
3936 return val > -256 && val < 256;
3938 return val > -4096 && val < 4092;
3941 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3944 if (GET_MODE_SIZE (mode) <= 4
3947 || (mode == QImode && outer == SIGN_EXTEND))))
3951 rtx xiop0 = XEXP (index, 0);
3952 rtx xiop1 = XEXP (index, 1);
3954 return ((arm_address_register_rtx_p (xiop0, strict_p)
3955 && power_of_two_operand (xiop1, SImode))
3956 || (arm_address_register_rtx_p (xiop1, strict_p)
3957 && power_of_two_operand (xiop0, SImode)));
3959 else if (code == LSHIFTRT || code == ASHIFTRT
3960 || code == ASHIFT || code == ROTATERT)
3962 rtx op = XEXP (index, 1);
3964 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3965 && GET_CODE (op) == CONST_INT
3967 && INTVAL (op) <= 31);
3971 /* For ARM v4 we may be doing a sign-extend operation during the
3975 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3981 range = (mode == HImode) ? 4095 : 4096;
3983 return (code == CONST_INT
3984 && INTVAL (index) < range
3985 && INTVAL (index) > -range);
3988 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3989 index operand. i.e. 1, 2, 4 or 8. */
3991 thumb2_index_mul_operand (rtx op)
3995 if (GET_CODE(op) != CONST_INT)
3999 return (val == 1 || val == 2 || val == 4 || val == 8);
4002 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
4004 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
4006 enum rtx_code code = GET_CODE (index);
4008 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
4009 /* Standard coprocessor addressing modes. */
4010 if (TARGET_HARD_FLOAT
4011 && (TARGET_FPA || TARGET_MAVERICK)
4012 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4013 || (TARGET_MAVERICK && mode == DImode)))
4014 return (code == CONST_INT && INTVAL (index) < 1024
4015 && INTVAL (index) > -1024
4016 && (INTVAL (index) & 3) == 0);
4018 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
4020 /* For DImode assume values will usually live in core regs
4021 and only allow LDRD addressing modes. */
4022 if (!TARGET_LDRD || mode != DImode)
4023 return (code == CONST_INT
4024 && INTVAL (index) < 1024
4025 && INTVAL (index) > -1024
4026 && (INTVAL (index) & 3) == 0);
4029 if (arm_address_register_rtx_p (index, strict_p)
4030 && (GET_MODE_SIZE (mode) <= 4))
4033 if (mode == DImode || mode == DFmode)
4035 HOST_WIDE_INT val = INTVAL (index);
4036 /* ??? Can we assume ldrd for thumb2? */
4037 /* Thumb-2 ldrd only has reg+const addressing modes. */
4038 if (code != CONST_INT)
4041 /* ldrd supports offsets of +-1020.
4042 However the ldr fallback does not. */
4043 return val > -256 && val < 256 && (val & 3) == 0;
4048 rtx xiop0 = XEXP (index, 0);
4049 rtx xiop1 = XEXP (index, 1);
4051 return ((arm_address_register_rtx_p (xiop0, strict_p)
4052 && thumb2_index_mul_operand (xiop1))
4053 || (arm_address_register_rtx_p (xiop1, strict_p)
4054 && thumb2_index_mul_operand (xiop0)));
4056 else if (code == ASHIFT)
4058 rtx op = XEXP (index, 1);
4060 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
4061 && GET_CODE (op) == CONST_INT
4063 && INTVAL (op) <= 3);
4066 return (code == CONST_INT
4067 && INTVAL (index) < 4096
4068 && INTVAL (index) > -256);
4071 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
4073 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
4077 if (GET_CODE (x) != REG)
4083 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
4085 return (regno <= LAST_LO_REGNUM
4086 || regno > LAST_VIRTUAL_REGISTER
4087 || regno == FRAME_POINTER_REGNUM
4088 || (GET_MODE_SIZE (mode) >= 4
4089 && (regno == STACK_POINTER_REGNUM
4090 || regno >= FIRST_PSEUDO_REGISTER
4091 || x == hard_frame_pointer_rtx
4092 || x == arg_pointer_rtx)));
4095 /* Return nonzero if x is a legitimate index register. This is the case
4096 for any base register that can access a QImode object. */
4098 thumb1_index_register_rtx_p (rtx x, int strict_p)
4100 return thumb1_base_register_rtx_p (x, QImode, strict_p);
4103 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4105 The AP may be eliminated to either the SP or the FP, so we use the
4106 least common denominator, e.g. SImode, and offsets from 0 to 64.
4108 ??? Verify whether the above is the right approach.
4110 ??? Also, the FP may be eliminated to the SP, so perhaps that
4111 needs special handling also.
4113 ??? Look at how the mips16 port solves this problem. It probably uses
4114 better ways to solve some of these problems.
4116 Although it is not incorrect, we don't accept QImode and HImode
4117 addresses based on the frame pointer or arg pointer until the
4118 reload pass starts. This is so that eliminating such addresses
4119 into stack based ones won't produce impossible code. */
4121 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
4123 /* ??? Not clear if this is right. Experiment. */
4124 if (GET_MODE_SIZE (mode) < 4
4125 && !(reload_in_progress || reload_completed)
4126 && (reg_mentioned_p (frame_pointer_rtx, x)
4127 || reg_mentioned_p (arg_pointer_rtx, x)
4128 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4129 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4130 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4131 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4134 /* Accept any base register. SP only in SImode or larger. */
4135 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
4138 /* This is PC relative data before arm_reorg runs. */
4139 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4140 && GET_CODE (x) == SYMBOL_REF
4141 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
4144 /* This is PC relative data after arm_reorg runs. */
4145 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4146 && (GET_CODE (x) == LABEL_REF
4147 || (GET_CODE (x) == CONST
4148 && GET_CODE (XEXP (x, 0)) == PLUS
4149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4153 /* Post-inc indexing only supported for SImode and larger. */
4154 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4155 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4158 else if (GET_CODE (x) == PLUS)
4160 /* REG+REG address can be any two index registers. */
4161 /* We disallow FRAME+REG addressing since we know that FRAME
4162 will be replaced with STACK, and SP relative addressing only
4163 permits SP+OFFSET. */
4164 if (GET_MODE_SIZE (mode) <= 4
4165 && XEXP (x, 0) != frame_pointer_rtx
4166 && XEXP (x, 1) != frame_pointer_rtx
4167 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4168 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4171 /* REG+const has 5-7 bit offset for non-SP registers. */
4172 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4173 || XEXP (x, 0) == arg_pointer_rtx)
4174 && GET_CODE (XEXP (x, 1)) == CONST_INT
4175 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4178 /* REG+const has 10-bit offset for SP, but only SImode and
4179 larger is supported. */
4180 /* ??? Should probably check for DI/DFmode overflow here
4181 just like GO_IF_LEGITIMATE_OFFSET does. */
4182 else if (GET_CODE (XEXP (x, 0)) == REG
4183 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4184 && GET_MODE_SIZE (mode) >= 4
4185 && GET_CODE (XEXP (x, 1)) == CONST_INT
4186 && INTVAL (XEXP (x, 1)) >= 0
4187 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4188 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4191 else if (GET_CODE (XEXP (x, 0)) == REG
4192 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4193 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4194 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4195 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4196 && GET_MODE_SIZE (mode) >= 4
4197 && GET_CODE (XEXP (x, 1)) == CONST_INT
4198 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4202 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4203 && GET_MODE_SIZE (mode) == 4
4204 && GET_CODE (x) == SYMBOL_REF
4205 && CONSTANT_POOL_ADDRESS_P (x)
4207 && symbol_mentioned_p (get_pool_constant (x))
4208 && ! pcrel_constant_p (get_pool_constant (x))))
4214 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4215 instruction of mode MODE. */
4217 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4219 switch (GET_MODE_SIZE (mode))
4222 return val >= 0 && val < 32;
4225 return val >= 0 && val < 64 && (val & 1) == 0;
4229 && (val + GET_MODE_SIZE (mode)) <= 128
4234 /* Build the SYMBOL_REF for __tls_get_addr. */
4236 static GTY(()) rtx tls_get_addr_libfunc;
4239 get_tls_get_addr (void)
4241 if (!tls_get_addr_libfunc)
4242 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4243 return tls_get_addr_libfunc;
4247 arm_load_tp (rtx target)
4250 target = gen_reg_rtx (SImode);
4254 /* Can return in any reg. */
4255 emit_insn (gen_load_tp_hard (target));
4259 /* Always returned in r0. Immediately copy the result into a pseudo,
4260 otherwise other uses of r0 (e.g. setting up function arguments) may
4261 clobber the value. */
4265 emit_insn (gen_load_tp_soft ());
4267 tmp = gen_rtx_REG (SImode, 0);
4268 emit_move_insn (target, tmp);
4274 load_tls_operand (rtx x, rtx reg)
4278 if (reg == NULL_RTX)
4279 reg = gen_reg_rtx (SImode);
4281 tmp = gen_rtx_CONST (SImode, x);
4283 emit_move_insn (reg, tmp);
4289 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4291 rtx insns, label, labelno, sum;
4295 labelno = GEN_INT (pic_labelno++);
4296 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4297 label = gen_rtx_CONST (VOIDmode, label);
4299 sum = gen_rtx_UNSPEC (Pmode,
4300 gen_rtvec (4, x, GEN_INT (reloc), label,
4301 GEN_INT (TARGET_ARM ? 8 : 4)),
4303 reg = load_tls_operand (sum, reg);
4306 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4307 else if (TARGET_THUMB2)
4310 /* Thumb-2 only allows very limited access to the PC. Calculate
4311 the address in a temporary register. */
4312 tmp = gen_reg_rtx (SImode);
4313 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4314 emit_insn (gen_addsi3(reg, reg, tmp));
4316 else /* TARGET_THUMB1 */
4317 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4319 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4320 Pmode, 1, reg, Pmode);
4322 insns = get_insns ();
4329 legitimize_tls_address (rtx x, rtx reg)
4331 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4332 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4336 case TLS_MODEL_GLOBAL_DYNAMIC:
4337 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4338 dest = gen_reg_rtx (Pmode);
4339 emit_libcall_block (insns, dest, ret, x);
4342 case TLS_MODEL_LOCAL_DYNAMIC:
4343 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4345 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4346 share the LDM result with other LD model accesses. */
4347 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4349 dest = gen_reg_rtx (Pmode);
4350 emit_libcall_block (insns, dest, ret, eqv);
4352 /* Load the addend. */
4353 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4355 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4356 return gen_rtx_PLUS (Pmode, dest, addend);
4358 case TLS_MODEL_INITIAL_EXEC:
4359 labelno = GEN_INT (pic_labelno++);
4360 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4361 label = gen_rtx_CONST (VOIDmode, label);
4362 sum = gen_rtx_UNSPEC (Pmode,
4363 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4364 GEN_INT (TARGET_ARM ? 8 : 4)),
4366 reg = load_tls_operand (sum, reg);
4369 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4370 else if (TARGET_THUMB2)
4373 /* Thumb-2 only allows very limited access to the PC. Calculate
4374 the address in a temporary register. */
4375 tmp = gen_reg_rtx (SImode);
4376 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4377 emit_insn (gen_addsi3(reg, reg, tmp));
4378 emit_move_insn (reg, gen_const_mem (SImode, reg));
4382 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4383 emit_move_insn (reg, gen_const_mem (SImode, reg));
4386 tp = arm_load_tp (NULL_RTX);
4388 return gen_rtx_PLUS (Pmode, tp, reg);
4390 case TLS_MODEL_LOCAL_EXEC:
4391 tp = arm_load_tp (NULL_RTX);
4393 reg = gen_rtx_UNSPEC (Pmode,
4394 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4396 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4398 return gen_rtx_PLUS (Pmode, tp, reg);
4405 /* Try machine-dependent ways of modifying an illegitimate address
4406 to be legitimate. If we find one, return the new, valid address. */
4408 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4410 if (arm_tls_symbol_p (x))
4411 return legitimize_tls_address (x, NULL_RTX);
4413 if (GET_CODE (x) == PLUS)
4415 rtx xop0 = XEXP (x, 0);
4416 rtx xop1 = XEXP (x, 1);
4418 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4419 xop0 = force_reg (SImode, xop0);
4421 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4422 xop1 = force_reg (SImode, xop1);
4424 if (ARM_BASE_REGISTER_RTX_P (xop0)
4425 && GET_CODE (xop1) == CONST_INT)
4427 HOST_WIDE_INT n, low_n;
4431 /* VFP addressing modes actually allow greater offsets, but for
4432 now we just stick with the lowest common denominator. */
4434 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4446 low_n = ((mode) == TImode ? 0
4447 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4451 base_reg = gen_reg_rtx (SImode);
4452 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4453 emit_move_insn (base_reg, val);
4454 x = plus_constant (base_reg, low_n);
4456 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4457 x = gen_rtx_PLUS (SImode, xop0, xop1);
4460 /* XXX We don't allow MINUS any more -- see comment in
4461 arm_legitimate_address_p (). */
4462 else if (GET_CODE (x) == MINUS)
4464 rtx xop0 = XEXP (x, 0);
4465 rtx xop1 = XEXP (x, 1);
4467 if (CONSTANT_P (xop0))
4468 xop0 = force_reg (SImode, xop0);
4470 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4471 xop1 = force_reg (SImode, xop1);
4473 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4474 x = gen_rtx_MINUS (SImode, xop0, xop1);
4477 /* Make sure to take full advantage of the pre-indexed addressing mode
4478 with absolute addresses which often allows for the base register to
4479 be factorized for multiple adjacent memory references, and it might
4480 even allows for the mini pool to be avoided entirely. */
4481 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4484 HOST_WIDE_INT mask, base, index;
4487 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4488 use a 8-bit index. So let's use a 12-bit index for SImode only and
4489 hope that arm_gen_constant will enable ldrb to use more bits. */
4490 bits = (mode == SImode) ? 12 : 8;
4491 mask = (1 << bits) - 1;
4492 base = INTVAL (x) & ~mask;
4493 index = INTVAL (x) & mask;
4494 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4496 /* It'll most probably be more efficient to generate the base
4497 with more bits set and use a negative index instead. */
4501 base_reg = force_reg (SImode, GEN_INT (base));
4502 x = plus_constant (base_reg, index);
4507 /* We need to find and carefully transform any SYMBOL and LABEL
4508 references; so go back to the original address expression. */
4509 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4511 if (new_x != orig_x)
4519 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4520 to be legitimate. If we find one, return the new, valid address. */
4522 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4524 if (arm_tls_symbol_p (x))
4525 return legitimize_tls_address (x, NULL_RTX);
4527 if (GET_CODE (x) == PLUS
4528 && GET_CODE (XEXP (x, 1)) == CONST_INT
4529 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4530 || INTVAL (XEXP (x, 1)) < 0))
4532 rtx xop0 = XEXP (x, 0);
4533 rtx xop1 = XEXP (x, 1);
4534 HOST_WIDE_INT offset = INTVAL (xop1);
4536 /* Try and fold the offset into a biasing of the base register and
4537 then offsetting that. Don't do this when optimizing for space
4538 since it can cause too many CSEs. */
4539 if (optimize_size && offset >= 0
4540 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4542 HOST_WIDE_INT delta;
4545 delta = offset - (256 - GET_MODE_SIZE (mode));
4546 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4547 delta = 31 * GET_MODE_SIZE (mode);
4549 delta = offset & (~31 * GET_MODE_SIZE (mode));
4551 xop0 = force_operand (plus_constant (xop0, offset - delta),
4553 x = plus_constant (xop0, delta);
4555 else if (offset < 0 && offset > -256)
4556 /* Small negative offsets are best done with a subtract before the
4557 dereference, forcing these into a register normally takes two
4559 x = force_operand (x, NULL_RTX);
4562 /* For the remaining cases, force the constant into a register. */
4563 xop1 = force_reg (SImode, xop1);
4564 x = gen_rtx_PLUS (SImode, xop0, xop1);
4567 else if (GET_CODE (x) == PLUS
4568 && s_register_operand (XEXP (x, 1), SImode)
4569 && !s_register_operand (XEXP (x, 0), SImode))
4571 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4573 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4578 /* We need to find and carefully transform any SYMBOL and LABEL
4579 references; so go back to the original address expression. */
4580 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4582 if (new_x != orig_x)
4590 thumb_legitimize_reload_address (rtx *x_p,
4591 enum machine_mode mode,
4592 int opnum, int type,
4593 int ind_levels ATTRIBUTE_UNUSED)
4597 if (GET_CODE (x) == PLUS
4598 && GET_MODE_SIZE (mode) < 4
4599 && REG_P (XEXP (x, 0))
4600 && XEXP (x, 0) == stack_pointer_rtx
4601 && GET_CODE (XEXP (x, 1)) == CONST_INT
4602 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4607 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4608 Pmode, VOIDmode, 0, 0, opnum, type);
4612 /* If both registers are hi-regs, then it's better to reload the
4613 entire expression rather than each register individually. That
4614 only requires one reload register rather than two. */
4615 if (GET_CODE (x) == PLUS
4616 && REG_P (XEXP (x, 0))
4617 && REG_P (XEXP (x, 1))
4618 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4619 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4624 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4625 Pmode, VOIDmode, 0, 0, opnum, type);
4632 /* Test for various thread-local symbols. */
4634 /* Return TRUE if X is a thread-local symbol. */
4637 arm_tls_symbol_p (rtx x)
4639 if (! TARGET_HAVE_TLS)
4642 if (GET_CODE (x) != SYMBOL_REF)
4645 return SYMBOL_REF_TLS_MODEL (x) != 0;
4648 /* Helper for arm_tls_referenced_p. */
4651 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4653 if (GET_CODE (*x) == SYMBOL_REF)
4654 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4656 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4657 TLS offsets, not real symbol references. */
4658 if (GET_CODE (*x) == UNSPEC
4659 && XINT (*x, 1) == UNSPEC_TLS)
4665 /* Return TRUE if X contains any TLS symbol references. */
4668 arm_tls_referenced_p (rtx x)
4670 if (! TARGET_HAVE_TLS)
4673 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4676 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
4679 arm_cannot_force_const_mem (rtx x)
4683 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
4685 split_const (x, &base, &offset);
4686 if (GET_CODE (base) == SYMBOL_REF
4687 && !offset_within_block_p (base, INTVAL (offset)))
4690 return arm_tls_referenced_p (x);
4693 #define REG_OR_SUBREG_REG(X) \
4694 (GET_CODE (X) == REG \
4695 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4697 #define REG_OR_SUBREG_RTX(X) \
4698 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4700 #ifndef COSTS_N_INSNS
4701 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4704 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4706 enum machine_mode mode = GET_MODE (x);
4719 return COSTS_N_INSNS (1);
4722 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4725 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4732 return COSTS_N_INSNS (2) + cycles;
4734 return COSTS_N_INSNS (1) + 16;
4737 return (COSTS_N_INSNS (1)
4738 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4739 + GET_CODE (SET_DEST (x)) == MEM));
4744 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4746 if (thumb_shiftable_const (INTVAL (x)))
4747 return COSTS_N_INSNS (2);
4748 return COSTS_N_INSNS (3);
4750 else if ((outer == PLUS || outer == COMPARE)
4751 && INTVAL (x) < 256 && INTVAL (x) > -256)
4753 else if (outer == AND
4754 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4755 return COSTS_N_INSNS (1);
4756 else if (outer == ASHIFT || outer == ASHIFTRT
4757 || outer == LSHIFTRT)
4759 return COSTS_N_INSNS (2);
4765 return COSTS_N_INSNS (3);
4783 /* XXX another guess. */
4784 /* Memory costs quite a lot for the first word, but subsequent words
4785 load at the equivalent of a single insn each. */
4786 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4787 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4792 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4797 /* XXX still guessing. */
4798 switch (GET_MODE (XEXP (x, 0)))
4801 return (1 + (mode == DImode ? 4 : 0)
4802 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4805 return (4 + (mode == DImode ? 4 : 0)
4806 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4809 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4821 /* Worker routine for arm_rtx_costs. */
4822 /* ??? This needs updating for thumb2. */
4824 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4826 enum machine_mode mode = GET_MODE (x);
4827 enum rtx_code subcode;
4833 /* Memory costs quite a lot for the first word, but subsequent words
4834 load at the equivalent of a single insn each. */
4835 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4836 + (GET_CODE (x) == SYMBOL_REF
4837 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4843 return optimize_size ? COSTS_N_INSNS (2) : 100;
4846 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4853 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4855 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4856 + ((GET_CODE (XEXP (x, 0)) == REG
4857 || (GET_CODE (XEXP (x, 0)) == SUBREG
4858 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4860 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4861 || (GET_CODE (XEXP (x, 0)) == SUBREG
4862 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4864 + ((GET_CODE (XEXP (x, 1)) == REG
4865 || (GET_CODE (XEXP (x, 1)) == SUBREG
4866 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4867 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4871 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4873 extra_cost = rtx_cost (XEXP (x, 1), code);
4874 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4875 extra_cost += 4 * ARM_NUM_REGS (mode);
4880 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4881 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4882 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4883 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4886 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4887 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4888 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4889 && arm_const_double_rtx (XEXP (x, 1))))
4891 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4892 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4893 && arm_const_double_rtx (XEXP (x, 0))))
4896 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4897 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4898 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4899 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4900 || subcode == ASHIFTRT || subcode == LSHIFTRT
4901 || subcode == ROTATE || subcode == ROTATERT
4903 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4904 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4905 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4906 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4907 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4908 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4909 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4914 if (GET_CODE (XEXP (x, 0)) == MULT)
4916 extra_cost = rtx_cost (XEXP (x, 0), code);
4917 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4918 extra_cost += 4 * ARM_NUM_REGS (mode);
4922 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4923 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4924 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4925 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4926 && arm_const_double_rtx (XEXP (x, 1))))
4930 case AND: case XOR: case IOR:
4933 /* Normally the frame registers will be spilt into reg+const during
4934 reload, so it is a bad idea to combine them with other instructions,
4935 since then they might not be moved outside of loops. As a compromise
4936 we allow integration with ops that have a constant as their second
4938 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4939 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4940 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4941 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4942 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4946 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4947 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4948 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4949 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4952 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4953 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4954 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4955 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4956 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4959 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4960 return (1 + extra_cost
4961 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4962 || subcode == LSHIFTRT || subcode == ASHIFTRT
4963 || subcode == ROTATE || subcode == ROTATERT
4965 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4966 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4967 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4968 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4969 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4970 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4976 /* This should have been handled by the CPU specific routines. */
4980 if (arm_arch3m && mode == SImode
4981 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4982 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4983 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4984 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4985 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4986 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4991 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4992 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4996 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4998 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
5001 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
5009 return 4 + (mode == DImode ? 4 : 0);
5012 /* ??? value extensions are cheaper on armv6. */
5013 if (GET_MODE (XEXP (x, 0)) == QImode)
5014 return (4 + (mode == DImode ? 4 : 0)
5015 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5018 switch (GET_MODE (XEXP (x, 0)))
5021 return (1 + (mode == DImode ? 4 : 0)
5022 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5025 return (4 + (mode == DImode ? 4 : 0)
5026 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5029 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5044 if (const_ok_for_arm (INTVAL (x)))
5045 return outer == SET ? 2 : -1;
5046 else if (outer == AND
5047 && const_ok_for_arm (~INTVAL (x)))
5049 else if ((outer == COMPARE
5050 || outer == PLUS || outer == MINUS)
5051 && const_ok_for_arm (-INTVAL (x)))
5062 if (arm_const_double_rtx (x) || vfp3_const_double_rtx (x))
5063 return outer == SET ? 2 : -1;
5064 else if ((outer == COMPARE || outer == PLUS)
5065 && neg_const_double_rtx_ok_for_fpa (x))
5074 /* RTX costs when optimizing for size. */
5076 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
5078 enum machine_mode mode = GET_MODE (x);
5082 /* XXX TBD. For now, use the standard costs. */
5083 *total = thumb1_rtx_costs (x, code, outer_code);
5090 /* A memory access costs 1 insn if the mode is small, or the address is
5091 a single register, otherwise it costs one insn per word. */
5092 if (REG_P (XEXP (x, 0)))
5093 *total = COSTS_N_INSNS (1);
5095 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5102 /* Needs a libcall, so it costs about this. */
5103 *total = COSTS_N_INSNS (2);
5107 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
5109 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
5117 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
5119 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
5122 else if (mode == SImode)
5124 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5125 /* Slightly disparage register shifts, but not by much. */
5126 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5127 *total += 1 + rtx_cost (XEXP (x, 1), code);
5131 /* Needs a libcall. */
5132 *total = COSTS_N_INSNS (2);
5136 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5138 *total = COSTS_N_INSNS (1);
5144 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5145 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5147 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5148 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5149 || subcode1 == ROTATE || subcode1 == ROTATERT
5150 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5151 || subcode1 == ASHIFTRT)
5153 /* It's just the cost of the two operands. */
5158 *total = COSTS_N_INSNS (1);
5162 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5166 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5168 *total = COSTS_N_INSNS (1);
5173 case AND: case XOR: case IOR:
5176 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5178 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5179 || subcode == LSHIFTRT || subcode == ASHIFTRT
5180 || (code == AND && subcode == NOT))
5182 /* It's just the cost of the two operands. */
5188 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5192 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5196 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5197 *total = COSTS_N_INSNS (1);
5200 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5209 if (cc_register (XEXP (x, 0), VOIDmode))
5212 *total = COSTS_N_INSNS (1);
5216 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5217 *total = COSTS_N_INSNS (1);
5219 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5224 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5226 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5227 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5230 *total += COSTS_N_INSNS (1);
5235 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5237 switch (GET_MODE (XEXP (x, 0)))
5240 *total += COSTS_N_INSNS (1);
5244 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5250 *total += COSTS_N_INSNS (2);
5255 *total += COSTS_N_INSNS (1);
5260 if (const_ok_for_arm (INTVAL (x)))
5261 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5262 else if (const_ok_for_arm (~INTVAL (x)))
5263 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5264 else if (const_ok_for_arm (-INTVAL (x)))
5266 if (outer_code == COMPARE || outer_code == PLUS
5267 || outer_code == MINUS)
5270 *total = COSTS_N_INSNS (1);
5273 *total = COSTS_N_INSNS (2);
5279 *total = COSTS_N_INSNS (2);
5283 *total = COSTS_N_INSNS (4);
5287 if (mode != VOIDmode)
5288 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5290 *total = COSTS_N_INSNS (4); /* How knows? */
5295 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5296 supported on any "slowmul" cores, so it can be ignored. */
5299 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5301 enum machine_mode mode = GET_MODE (x);
5305 *total = thumb1_rtx_costs (x, code, outer_code);
5312 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5319 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5321 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5322 & (unsigned HOST_WIDE_INT) 0xffffffff);
5323 int cost, const_ok = const_ok_for_arm (i);
5324 int j, booth_unit_size;
5326 /* Tune as appropriate. */
5327 cost = const_ok ? 4 : 8;
5328 booth_unit_size = 2;
5329 for (j = 0; i && j < 32; j += booth_unit_size)
5331 i >>= booth_unit_size;
5339 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5340 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5344 *total = arm_rtx_costs_1 (x, code, outer_code);
5350 /* RTX cost for cores with a fast multiply unit (M variants). */
5353 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5355 enum machine_mode mode = GET_MODE (x);
5359 *total = thumb1_rtx_costs (x, code, outer_code);
5363 /* ??? should thumb2 use different costs? */
5367 /* There is no point basing this on the tuning, since it is always the
5368 fast variant if it exists at all. */
5370 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5371 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5372 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5379 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5386 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5388 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5389 & (unsigned HOST_WIDE_INT) 0xffffffff);
5390 int cost, const_ok = const_ok_for_arm (i);
5391 int j, booth_unit_size;
5393 /* Tune as appropriate. */
5394 cost = const_ok ? 4 : 8;
5395 booth_unit_size = 8;
5396 for (j = 0; i && j < 32; j += booth_unit_size)
5398 i >>= booth_unit_size;
5406 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5407 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5411 *total = arm_rtx_costs_1 (x, code, outer_code);
5417 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5418 so it can be ignored. */
5421 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5423 enum machine_mode mode = GET_MODE (x);
5427 *total = thumb1_rtx_costs (x, code, outer_code);
5434 /* There is no point basing this on the tuning, since it is always the
5435 fast variant if it exists at all. */
5437 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5438 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5439 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5446 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5453 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5455 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5456 & (unsigned HOST_WIDE_INT) 0xffffffff);
5457 int cost, const_ok = const_ok_for_arm (i);
5458 unsigned HOST_WIDE_INT masked_const;
5460 /* The cost will be related to two insns.
5461 First a load of the constant (MOV or LDR), then a multiply. */
5464 cost += 1; /* LDR is probably more expensive because
5465 of longer result latency. */
5466 masked_const = i & 0xffff8000;
5467 if (masked_const != 0 && masked_const != 0xffff8000)
5469 masked_const = i & 0xf8000000;
5470 if (masked_const == 0 || masked_const == 0xf8000000)
5479 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5480 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5484 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5485 will stall until the multiplication is complete. */
5486 if (GET_CODE (XEXP (x, 0)) == MULT)
5487 *total = 4 + rtx_cost (XEXP (x, 0), code);
5489 *total = arm_rtx_costs_1 (x, code, outer_code);
5493 *total = arm_rtx_costs_1 (x, code, outer_code);
5499 /* RTX costs for 9e (and later) cores. */
5502 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5504 enum machine_mode mode = GET_MODE (x);
5513 *total = COSTS_N_INSNS (3);
5517 *total = thumb1_rtx_costs (x, code, outer_code);
5525 /* There is no point basing this on the tuning, since it is always the
5526 fast variant if it exists at all. */
5528 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5529 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5530 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5537 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5554 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5555 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5559 *total = arm_rtx_costs_1 (x, code, outer_code);
5563 /* All address computations that can be done are free, but rtx cost returns
5564 the same for practically all of them. So we weight the different types
5565 of address here in the order (most pref first):
5566 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5568 arm_arm_address_cost (rtx x)
5570 enum rtx_code c = GET_CODE (x);
5572 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5574 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5577 if (c == PLUS || c == MINUS)
5579 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5582 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5592 arm_thumb_address_cost (rtx x)
5594 enum rtx_code c = GET_CODE (x);
5599 && GET_CODE (XEXP (x, 0)) == REG
5600 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5607 arm_address_cost (rtx x)
5609 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5613 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5617 /* Some true dependencies can have a higher cost depending
5618 on precisely how certain input operands are used. */
5620 && REG_NOTE_KIND (link) == 0
5621 && recog_memoized (insn) >= 0
5622 && recog_memoized (dep) >= 0)
5624 int shift_opnum = get_attr_shift (insn);
5625 enum attr_type attr_type = get_attr_type (dep);
5627 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5628 operand for INSN. If we have a shifted input operand and the
5629 instruction we depend on is another ALU instruction, then we may
5630 have to account for an additional stall. */
5631 if (shift_opnum != 0
5632 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5634 rtx shifted_operand;
5637 /* Get the shifted operand. */
5638 extract_insn (insn);
5639 shifted_operand = recog_data.operand[shift_opnum];
5641 /* Iterate over all the operands in DEP. If we write an operand
5642 that overlaps with SHIFTED_OPERAND, then we have increase the
5643 cost of this dependency. */
5645 preprocess_constraints ();
5646 for (opno = 0; opno < recog_data.n_operands; opno++)
5648 /* We can ignore strict inputs. */
5649 if (recog_data.operand_type[opno] == OP_IN)
5652 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5659 /* XXX This is not strictly true for the FPA. */
5660 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5661 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5664 /* Call insns don't incur a stall, even if they follow a load. */
5665 if (REG_NOTE_KIND (link) == 0
5666 && GET_CODE (insn) == CALL_INSN)
5669 if ((i_pat = single_set (insn)) != NULL
5670 && GET_CODE (SET_SRC (i_pat)) == MEM
5671 && (d_pat = single_set (dep)) != NULL
5672 && GET_CODE (SET_DEST (d_pat)) == MEM)
5674 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5675 /* This is a load after a store, there is no conflict if the load reads
5676 from a cached area. Assume that loads from the stack, and from the
5677 constant pool are cached, and that others will miss. This is a
5680 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5681 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5682 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5683 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5690 static int fp_consts_inited = 0;
5692 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5693 static const char * const strings_fp[8] =
5696 "4", "5", "0.5", "10"
5699 static REAL_VALUE_TYPE values_fp[8];
5702 init_fp_table (void)
5708 fp_consts_inited = 1;
5710 fp_consts_inited = 8;
5712 for (i = 0; i < fp_consts_inited; i++)
5714 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5719 /* Return TRUE if rtx X is a valid immediate FP constant. */
5721 arm_const_double_rtx (rtx x)
5726 if (!fp_consts_inited)
5729 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5730 if (REAL_VALUE_MINUS_ZERO (r))
5733 for (i = 0; i < fp_consts_inited; i++)
5734 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5740 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5742 neg_const_double_rtx_ok_for_fpa (rtx x)
5747 if (!fp_consts_inited)
5750 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5751 r = REAL_VALUE_NEGATE (r);
5752 if (REAL_VALUE_MINUS_ZERO (r))
5755 for (i = 0; i < 8; i++)
5756 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5763 /* VFPv3 has a fairly wide range of representable immediates, formed from
5764 "quarter-precision" floating-point values. These can be evaluated using this
5765 formula (with ^ for exponentiation):
5769 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
5770 16 <= n <= 31 and 0 <= r <= 7.
5772 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
5774 - A (most-significant) is the sign bit.
5775 - BCD are the exponent (encoded as r XOR 3).
5776 - EFGH are the mantissa (encoded as n - 16).
5779 /* Return an integer index for a VFPv3 immediate operand X suitable for the
5780 fconst[sd] instruction, or -1 if X isn't suitable. */
5782 vfp3_const_double_index (rtx x)
5784 REAL_VALUE_TYPE r, m;
5786 unsigned HOST_WIDE_INT mantissa, mant_hi;
5787 unsigned HOST_WIDE_INT mask;
5788 HOST_WIDE_INT m1, m2;
5789 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
5791 if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
5794 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5796 /* We can't represent these things, so detect them first. */
5797 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
5800 /* Extract sign, exponent and mantissa. */
5801 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
5802 r = REAL_VALUE_ABS (r);
5803 exponent = REAL_EXP (&r);
5804 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
5805 highest (sign) bit, with a fixed binary point at bit point_pos.
5806 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
5807 bits for the mantissa, this may fail (low bits would be lost). */
5808 real_ldexp (&m, &r, point_pos - exponent);
5809 REAL_VALUE_TO_INT (&m1, &m2, m);
5813 /* If there are bits set in the low part of the mantissa, we can't
5814 represent this value. */
5818 /* Now make it so that mantissa contains the most-significant bits, and move
5819 the point_pos to indicate that the least-significant bits have been
5821 point_pos -= HOST_BITS_PER_WIDE_INT;
5824 /* We can permit four significant bits of mantissa only, plus a high bit
5825 which is always 1. */
5826 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
5827 if ((mantissa & mask) != 0)
5830 /* Now we know the mantissa is in range, chop off the unneeded bits. */
5831 mantissa >>= point_pos - 5;
5833 /* The mantissa may be zero. Disallow that case. (It's possible to load the
5834 floating-point immediate zero with Neon using an integer-zero load, but
5835 that case is handled elsewhere.) */
5839 gcc_assert (mantissa >= 16 && mantissa <= 31);
5841 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
5842 normalized significands are in the range [1, 2). (Our mantissa is shifted
5843 left 4 places at this point relative to normalized IEEE754 values). GCC
5844 internally uses [0.5, 1) (see real.c), so the exponent returned from
5845 REAL_EXP must be altered. */
5846 exponent = 5 - exponent;
5848 if (exponent < 0 || exponent > 7)
5851 /* Sign, mantissa and exponent are now in the correct form to plug into the
5852 formulae described in the comment above. */
5853 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
5856 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
5858 vfp3_const_double_rtx (rtx x)
5863 return vfp3_const_double_index (x) != -1;
5867 /* Predicates for `match_operand' and `match_operator'. */
5869 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5871 cirrus_memory_offset (rtx op)
5873 /* Reject eliminable registers. */
5874 if (! (reload_in_progress || reload_completed)
5875 && ( reg_mentioned_p (frame_pointer_rtx, op)
5876 || reg_mentioned_p (arg_pointer_rtx, op)
5877 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5878 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5879 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5880 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5883 if (GET_CODE (op) == MEM)
5889 /* Match: (mem (reg)). */
5890 if (GET_CODE (ind) == REG)
5896 if (GET_CODE (ind) == PLUS
5897 && GET_CODE (XEXP (ind, 0)) == REG
5898 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5899 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5906 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5907 WB is true if full writeback address modes are allowed and is false
5908 if limited writeback address modes (POST_INC and PRE_DEC) are
5912 arm_coproc_mem_operand (rtx op, bool wb)
5916 /* Reject eliminable registers. */
5917 if (! (reload_in_progress || reload_completed)
5918 && ( reg_mentioned_p (frame_pointer_rtx, op)
5919 || reg_mentioned_p (arg_pointer_rtx, op)
5920 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5921 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5922 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5923 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5926 /* Constants are converted into offsets from labels. */
5927 if (GET_CODE (op) != MEM)
5932 if (reload_completed
5933 && (GET_CODE (ind) == LABEL_REF
5934 || (GET_CODE (ind) == CONST
5935 && GET_CODE (XEXP (ind, 0)) == PLUS
5936 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5937 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5940 /* Match: (mem (reg)). */
5941 if (GET_CODE (ind) == REG)
5942 return arm_address_register_rtx_p (ind, 0);
5944 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5945 acceptable in any case (subject to verification by
5946 arm_address_register_rtx_p). We need WB to be true to accept
5947 PRE_INC and POST_DEC. */
5948 if (GET_CODE (ind) == POST_INC
5949 || GET_CODE (ind) == PRE_DEC
5951 && (GET_CODE (ind) == PRE_INC
5952 || GET_CODE (ind) == POST_DEC)))
5953 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5956 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5957 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5958 && GET_CODE (XEXP (ind, 1)) == PLUS
5959 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5960 ind = XEXP (ind, 1);
5965 if (GET_CODE (ind) == PLUS
5966 && GET_CODE (XEXP (ind, 0)) == REG
5967 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5968 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5969 && INTVAL (XEXP (ind, 1)) > -1024
5970 && INTVAL (XEXP (ind, 1)) < 1024
5971 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5977 /* Return true if X is a register that will be eliminated later on. */
5979 arm_eliminable_register (rtx x)
5981 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5982 || REGNO (x) == ARG_POINTER_REGNUM
5983 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5984 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5987 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5988 coprocessor registers. Otherwise return NO_REGS. */
5991 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5993 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5996 return GENERAL_REGS;
5999 /* Values which must be returned in the most-significant end of the return
6003 arm_return_in_msb (tree valtype)
6005 return (TARGET_AAPCS_BASED
6007 && (AGGREGATE_TYPE_P (valtype)
6008 || TREE_CODE (valtype) == COMPLEX_TYPE));
6011 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
6012 Use by the Cirrus Maverick code which has to workaround
6013 a hardware bug triggered by such instructions. */
6015 arm_memory_load_p (rtx insn)
6017 rtx body, lhs, rhs;;
6019 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
6022 body = PATTERN (insn);
6024 if (GET_CODE (body) != SET)
6027 lhs = XEXP (body, 0);
6028 rhs = XEXP (body, 1);
6030 lhs = REG_OR_SUBREG_RTX (lhs);
6032 /* If the destination is not a general purpose
6033 register we do not have to worry. */
6034 if (GET_CODE (lhs) != REG
6035 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
6038 /* As well as loads from memory we also have to react
6039 to loads of invalid constants which will be turned
6040 into loads from the minipool. */
6041 return (GET_CODE (rhs) == MEM
6042 || GET_CODE (rhs) == SYMBOL_REF
6043 || note_invalid_constants (insn, -1, false));
6046 /* Return TRUE if INSN is a Cirrus instruction. */
6048 arm_cirrus_insn_p (rtx insn)
6050 enum attr_cirrus attr;
6052 /* get_attr cannot accept USE or CLOBBER. */
6054 || GET_CODE (insn) != INSN
6055 || GET_CODE (PATTERN (insn)) == USE
6056 || GET_CODE (PATTERN (insn)) == CLOBBER)
6059 attr = get_attr_cirrus (insn);
6061 return attr != CIRRUS_NOT;
6064 /* Cirrus reorg for invalid instruction combinations. */
6066 cirrus_reorg (rtx first)
6068 enum attr_cirrus attr;
6069 rtx body = PATTERN (first);
6073 /* Any branch must be followed by 2 non Cirrus instructions. */
6074 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
6077 t = next_nonnote_insn (first);
6079 if (arm_cirrus_insn_p (t))
6082 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
6086 emit_insn_after (gen_nop (), first);
6091 /* (float (blah)) is in parallel with a clobber. */
6092 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6093 body = XVECEXP (body, 0, 0);
6095 if (GET_CODE (body) == SET)
6097 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
6099 /* cfldrd, cfldr64, cfstrd, cfstr64 must
6100 be followed by a non Cirrus insn. */
6101 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
6103 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
6104 emit_insn_after (gen_nop (), first);
6108 else if (arm_memory_load_p (first))
6110 unsigned int arm_regno;
6112 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
6113 ldr/cfmv64hr combination where the Rd field is the same
6114 in both instructions must be split with a non Cirrus
6121 /* Get Arm register number for ldr insn. */
6122 if (GET_CODE (lhs) == REG)
6123 arm_regno = REGNO (lhs);
6126 gcc_assert (GET_CODE (rhs) == REG);
6127 arm_regno = REGNO (rhs);
6131 first = next_nonnote_insn (first);
6133 if (! arm_cirrus_insn_p (first))
6136 body = PATTERN (first);
6138 /* (float (blah)) is in parallel with a clobber. */
6139 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
6140 body = XVECEXP (body, 0, 0);
6142 if (GET_CODE (body) == FLOAT)
6143 body = XEXP (body, 0);
6145 if (get_attr_cirrus (first) == CIRRUS_MOVE
6146 && GET_CODE (XEXP (body, 1)) == REG
6147 && arm_regno == REGNO (XEXP (body, 1)))
6148 emit_insn_after (gen_nop (), first);
6154 /* get_attr cannot accept USE or CLOBBER. */
6156 || GET_CODE (first) != INSN
6157 || GET_CODE (PATTERN (first)) == USE
6158 || GET_CODE (PATTERN (first)) == CLOBBER)
6161 attr = get_attr_cirrus (first);
6163 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
6164 must be followed by a non-coprocessor instruction. */
6165 if (attr == CIRRUS_COMPARE)
6169 t = next_nonnote_insn (first);
6171 if (arm_cirrus_insn_p (t))
6174 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
6178 emit_insn_after (gen_nop (), first);
6184 /* Return TRUE if X references a SYMBOL_REF. */
6186 symbol_mentioned_p (rtx x)
6191 if (GET_CODE (x) == SYMBOL_REF)
6194 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
6195 are constant offsets, not symbols. */
6196 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6199 fmt = GET_RTX_FORMAT (GET_CODE (x));
6201 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6207 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6208 if (symbol_mentioned_p (XVECEXP (x, i, j)))
6211 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
6218 /* Return TRUE if X references a LABEL_REF. */
6220 label_mentioned_p (rtx x)
6225 if (GET_CODE (x) == LABEL_REF)
6228 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6229 instruction, but they are constant offsets, not symbols. */
6230 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6233 fmt = GET_RTX_FORMAT (GET_CODE (x));
6234 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6240 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6241 if (label_mentioned_p (XVECEXP (x, i, j)))
6244 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6252 tls_mentioned_p (rtx x)
6254 switch (GET_CODE (x))
6257 return tls_mentioned_p (XEXP (x, 0));
6260 if (XINT (x, 1) == UNSPEC_TLS)
6268 /* Must not copy a SET whose source operand is PC-relative. */
6271 arm_cannot_copy_insn_p (rtx insn)
6273 rtx pat = PATTERN (insn);
6275 if (GET_CODE (pat) == SET)
6277 rtx rhs = SET_SRC (pat);
6279 if (GET_CODE (rhs) == UNSPEC
6280 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6283 if (GET_CODE (rhs) == MEM
6284 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6285 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6295 enum rtx_code code = GET_CODE (x);
6312 /* Return 1 if memory locations are adjacent. */
6314 adjacent_mem_locations (rtx a, rtx b)
6316 /* We don't guarantee to preserve the order of these memory refs. */
6317 if (volatile_refs_p (a) || volatile_refs_p (b))
6320 if ((GET_CODE (XEXP (a, 0)) == REG
6321 || (GET_CODE (XEXP (a, 0)) == PLUS
6322 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6323 && (GET_CODE (XEXP (b, 0)) == REG
6324 || (GET_CODE (XEXP (b, 0)) == PLUS
6325 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6327 HOST_WIDE_INT val0 = 0, val1 = 0;
6331 if (GET_CODE (XEXP (a, 0)) == PLUS)
6333 reg0 = XEXP (XEXP (a, 0), 0);
6334 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6339 if (GET_CODE (XEXP (b, 0)) == PLUS)
6341 reg1 = XEXP (XEXP (b, 0), 0);
6342 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6347 /* Don't accept any offset that will require multiple
6348 instructions to handle, since this would cause the
6349 arith_adjacentmem pattern to output an overlong sequence. */
6350 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6353 /* Don't allow an eliminable register: register elimination can make
6354 the offset too large. */
6355 if (arm_eliminable_register (reg0))
6358 val_diff = val1 - val0;
6362 /* If the target has load delay slots, then there's no benefit
6363 to using an ldm instruction unless the offset is zero and
6364 we are optimizing for size. */
6365 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6366 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6367 && (val_diff == 4 || val_diff == -4));
6370 return ((REGNO (reg0) == REGNO (reg1))
6371 && (val_diff == 4 || val_diff == -4));
6378 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6379 HOST_WIDE_INT *load_offset)
6381 int unsorted_regs[4];
6382 HOST_WIDE_INT unsorted_offsets[4];
6387 /* Can only handle 2, 3, or 4 insns at present,
6388 though could be easily extended if required. */
6389 gcc_assert (nops >= 2 && nops <= 4);
6391 /* Loop over the operands and check that the memory references are
6392 suitable (i.e. immediate offsets from the same base register). At
6393 the same time, extract the target register, and the memory
6395 for (i = 0; i < nops; i++)
6400 /* Convert a subreg of a mem into the mem itself. */
6401 if (GET_CODE (operands[nops + i]) == SUBREG)
6402 operands[nops + i] = alter_subreg (operands + (nops + i));
6404 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6406 /* Don't reorder volatile memory references; it doesn't seem worth
6407 looking for the case where the order is ok anyway. */
6408 if (MEM_VOLATILE_P (operands[nops + i]))
6411 offset = const0_rtx;
6413 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6414 || (GET_CODE (reg) == SUBREG
6415 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6416 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6417 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6419 || (GET_CODE (reg) == SUBREG
6420 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6421 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6426 base_reg = REGNO (reg);
6427 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6428 ? REGNO (operands[i])
6429 : REGNO (SUBREG_REG (operands[i])));
6434 if (base_reg != (int) REGNO (reg))
6435 /* Not addressed from the same base register. */
6438 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6439 ? REGNO (operands[i])
6440 : REGNO (SUBREG_REG (operands[i])));
6441 if (unsorted_regs[i] < unsorted_regs[order[0]])
6445 /* If it isn't an integer register, or if it overwrites the
6446 base register but isn't the last insn in the list, then
6447 we can't do this. */
6448 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6449 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6452 unsorted_offsets[i] = INTVAL (offset);
6455 /* Not a suitable memory address. */
6459 /* All the useful information has now been extracted from the
6460 operands into unsorted_regs and unsorted_offsets; additionally,
6461 order[0] has been set to the lowest numbered register in the
6462 list. Sort the registers into order, and check that the memory
6463 offsets are ascending and adjacent. */
6465 for (i = 1; i < nops; i++)
6469 order[i] = order[i - 1];
6470 for (j = 0; j < nops; j++)
6471 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6472 && (order[i] == order[i - 1]
6473 || unsorted_regs[j] < unsorted_regs[order[i]]))
6476 /* Have we found a suitable register? if not, one must be used more
6478 if (order[i] == order[i - 1])
6481 /* Is the memory address adjacent and ascending? */
6482 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6490 for (i = 0; i < nops; i++)
6491 regs[i] = unsorted_regs[order[i]];
6493 *load_offset = unsorted_offsets[order[0]];
6496 if (unsorted_offsets[order[0]] == 0)
6497 return 1; /* ldmia */
6499 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
6500 return 2; /* ldmib */
6502 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
6503 return 3; /* ldmda */
6505 if (unsorted_offsets[order[nops - 1]] == -4)
6506 return 4; /* ldmdb */
6508 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6509 if the offset isn't small enough. The reason 2 ldrs are faster
6510 is because these ARMs are able to do more than one cache access
6511 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6512 whilst the ARM8 has a double bandwidth cache. This means that
6513 these cores can do both an instruction fetch and a data fetch in
6514 a single cycle, so the trick of calculating the address into a
6515 scratch register (one of the result regs) and then doing a load
6516 multiple actually becomes slower (and no smaller in code size).
6517 That is the transformation
6519 ldr rd1, [rbase + offset]
6520 ldr rd2, [rbase + offset + 4]
6524 add rd1, rbase, offset
6525 ldmia rd1, {rd1, rd2}
6527 produces worse code -- '3 cycles + any stalls on rd2' instead of
6528 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6529 access per cycle, the first sequence could never complete in less
6530 than 6 cycles, whereas the ldm sequence would only take 5 and
6531 would make better use of sequential accesses if not hitting the
6534 We cheat here and test 'arm_ld_sched' which we currently know to
6535 only be true for the ARM8, ARM9 and StrongARM. If this ever
6536 changes, then the test below needs to be reworked. */
6537 if (nops == 2 && arm_ld_sched)
6540 /* Can't do it without setting up the offset, only do this if it takes
6541 no more than one insn. */
6542 return (const_ok_for_arm (unsorted_offsets[order[0]])
6543 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
6547 emit_ldm_seq (rtx *operands, int nops)
6551 HOST_WIDE_INT offset;
6555 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6558 strcpy (buf, "ldm%(ia%)\t");
6562 strcpy (buf, "ldm%(ib%)\t");
6566 strcpy (buf, "ldm%(da%)\t");
6570 strcpy (buf, "ldm%(db%)\t");
6575 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6576 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6579 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6580 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6582 output_asm_insn (buf, operands);
6584 strcpy (buf, "ldm%(ia%)\t");
6591 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6592 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6594 for (i = 1; i < nops; i++)
6595 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6596 reg_names[regs[i]]);
6598 strcat (buf, "}\t%@ phole ldm");
6600 output_asm_insn (buf, operands);
6605 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6606 HOST_WIDE_INT * load_offset)
6608 int unsorted_regs[4];
6609 HOST_WIDE_INT unsorted_offsets[4];
6614 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6615 extended if required. */
6616 gcc_assert (nops >= 2 && nops <= 4);
6618 /* Loop over the operands and check that the memory references are
6619 suitable (i.e. immediate offsets from the same base register). At
6620 the same time, extract the target register, and the memory
6622 for (i = 0; i < nops; i++)
6627 /* Convert a subreg of a mem into the mem itself. */
6628 if (GET_CODE (operands[nops + i]) == SUBREG)
6629 operands[nops + i] = alter_subreg (operands + (nops + i));
6631 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6633 /* Don't reorder volatile memory references; it doesn't seem worth
6634 looking for the case where the order is ok anyway. */
6635 if (MEM_VOLATILE_P (operands[nops + i]))
6638 offset = const0_rtx;
6640 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6641 || (GET_CODE (reg) == SUBREG
6642 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6643 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6644 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6646 || (GET_CODE (reg) == SUBREG
6647 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6648 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6653 base_reg = REGNO (reg);
6654 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6655 ? REGNO (operands[i])
6656 : REGNO (SUBREG_REG (operands[i])));
6661 if (base_reg != (int) REGNO (reg))
6662 /* Not addressed from the same base register. */
6665 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6666 ? REGNO (operands[i])
6667 : REGNO (SUBREG_REG (operands[i])));
6668 if (unsorted_regs[i] < unsorted_regs[order[0]])
6672 /* If it isn't an integer register, then we can't do this. */
6673 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6676 unsorted_offsets[i] = INTVAL (offset);
6679 /* Not a suitable memory address. */
6683 /* All the useful information has now been extracted from the
6684 operands into unsorted_regs and unsorted_offsets; additionally,
6685 order[0] has been set to the lowest numbered register in the
6686 list. Sort the registers into order, and check that the memory
6687 offsets are ascending and adjacent. */
6689 for (i = 1; i < nops; i++)
6693 order[i] = order[i - 1];
6694 for (j = 0; j < nops; j++)
6695 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6696 && (order[i] == order[i - 1]
6697 || unsorted_regs[j] < unsorted_regs[order[i]]))
6700 /* Have we found a suitable register? if not, one must be used more
6702 if (order[i] == order[i - 1])
6705 /* Is the memory address adjacent and ascending? */
6706 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6714 for (i = 0; i < nops; i++)
6715 regs[i] = unsorted_regs[order[i]];
6717 *load_offset = unsorted_offsets[order[0]];
6720 if (unsorted_offsets[order[0]] == 0)
6721 return 1; /* stmia */
6723 if (unsorted_offsets[order[0]] == 4)
6724 return 2; /* stmib */
6726 if (unsorted_offsets[order[nops - 1]] == 0)
6727 return 3; /* stmda */
6729 if (unsorted_offsets[order[nops - 1]] == -4)
6730 return 4; /* stmdb */
6736 emit_stm_seq (rtx *operands, int nops)
6740 HOST_WIDE_INT offset;
6744 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6747 strcpy (buf, "stm%(ia%)\t");
6751 strcpy (buf, "stm%(ib%)\t");
6755 strcpy (buf, "stm%(da%)\t");
6759 strcpy (buf, "stm%(db%)\t");
6766 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6767 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6769 for (i = 1; i < nops; i++)
6770 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6771 reg_names[regs[i]]);
6773 strcat (buf, "}\t%@ phole stm");
6775 output_asm_insn (buf, operands);
6779 /* Routines for use in generating RTL. */
6782 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6783 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6785 HOST_WIDE_INT offset = *offsetp;
6788 int sign = up ? 1 : -1;
6791 /* XScale has load-store double instructions, but they have stricter
6792 alignment requirements than load-store multiple, so we cannot
6795 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6796 the pipeline until completion.
6804 An ldr instruction takes 1-3 cycles, but does not block the
6813 Best case ldr will always win. However, the more ldr instructions
6814 we issue, the less likely we are to be able to schedule them well.
6815 Using ldr instructions also increases code size.
6817 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6818 for counts of 3 or 4 regs. */
6819 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6825 for (i = 0; i < count; i++)
6827 addr = plus_constant (from, i * 4 * sign);
6828 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6829 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6835 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6845 result = gen_rtx_PARALLEL (VOIDmode,
6846 rtvec_alloc (count + (write_back ? 1 : 0)));
6849 XVECEXP (result, 0, 0)
6850 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6855 for (j = 0; i < count; i++, j++)
6857 addr = plus_constant (from, j * 4 * sign);
6858 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6859 XVECEXP (result, 0, i)
6860 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6871 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6872 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6874 HOST_WIDE_INT offset = *offsetp;
6877 int sign = up ? 1 : -1;
6880 /* See arm_gen_load_multiple for discussion of
6881 the pros/cons of ldm/stm usage for XScale. */
6882 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6888 for (i = 0; i < count; i++)
6890 addr = plus_constant (to, i * 4 * sign);
6891 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6892 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6898 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6908 result = gen_rtx_PARALLEL (VOIDmode,
6909 rtvec_alloc (count + (write_back ? 1 : 0)));
6912 XVECEXP (result, 0, 0)
6913 = gen_rtx_SET (VOIDmode, to,
6914 plus_constant (to, count * 4 * sign));
6919 for (j = 0; i < count; i++, j++)
6921 addr = plus_constant (to, j * 4 * sign);
6922 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6923 XVECEXP (result, 0, i)
6924 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6935 arm_gen_movmemqi (rtx *operands)
6937 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6938 HOST_WIDE_INT srcoffset, dstoffset;
6940 rtx src, dst, srcbase, dstbase;
6941 rtx part_bytes_reg = NULL;
6944 if (GET_CODE (operands[2]) != CONST_INT
6945 || GET_CODE (operands[3]) != CONST_INT
6946 || INTVAL (operands[2]) > 64
6947 || INTVAL (operands[3]) & 3)
6950 dstbase = operands[0];
6951 srcbase = operands[1];
6953 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6954 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6956 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6957 out_words_to_go = INTVAL (operands[2]) / 4;
6958 last_bytes = INTVAL (operands[2]) & 3;
6959 dstoffset = srcoffset = 0;
6961 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6962 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6964 for (i = 0; in_words_to_go >= 2; i+=4)
6966 if (in_words_to_go > 4)
6967 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6968 srcbase, &srcoffset));
6970 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6971 FALSE, srcbase, &srcoffset));
6973 if (out_words_to_go)
6975 if (out_words_to_go > 4)
6976 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6977 dstbase, &dstoffset));
6978 else if (out_words_to_go != 1)
6979 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6983 dstbase, &dstoffset));
6986 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6987 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6988 if (last_bytes != 0)
6990 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6996 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6997 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
7000 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
7001 if (out_words_to_go)
7005 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
7006 sreg = copy_to_reg (mem);
7008 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
7009 emit_move_insn (mem, sreg);
7012 gcc_assert (!in_words_to_go); /* Sanity check */
7017 gcc_assert (in_words_to_go > 0);
7019 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
7020 part_bytes_reg = copy_to_mode_reg (SImode, mem);
7023 gcc_assert (!last_bytes || part_bytes_reg);
7025 if (BYTES_BIG_ENDIAN && last_bytes)
7027 rtx tmp = gen_reg_rtx (SImode);
7029 /* The bytes we want are in the top end of the word. */
7030 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
7031 GEN_INT (8 * (4 - last_bytes))));
7032 part_bytes_reg = tmp;
7036 mem = adjust_automodify_address (dstbase, QImode,
7037 plus_constant (dst, last_bytes - 1),
7038 dstoffset + last_bytes - 1);
7039 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7043 tmp = gen_reg_rtx (SImode);
7044 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
7045 part_bytes_reg = tmp;
7054 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
7055 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
7059 rtx tmp = gen_reg_rtx (SImode);
7060 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
7061 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
7062 part_bytes_reg = tmp;
7069 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
7070 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7077 /* Select a dominance comparison mode if possible for a test of the general
7078 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
7079 COND_OR == DOM_CC_X_AND_Y => (X && Y)
7080 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
7081 COND_OR == DOM_CC_X_OR_Y => (X || Y)
7082 In all cases OP will be either EQ or NE, but we don't need to know which
7083 here. If we are unable to support a dominance comparison we return
7084 CC mode. This will then fail to match for the RTL expressions that
7085 generate this call. */
7087 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
7089 enum rtx_code cond1, cond2;
7092 /* Currently we will probably get the wrong result if the individual
7093 comparisons are not simple. This also ensures that it is safe to
7094 reverse a comparison if necessary. */
7095 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
7097 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
7101 /* The if_then_else variant of this tests the second condition if the
7102 first passes, but is true if the first fails. Reverse the first
7103 condition to get a true "inclusive-or" expression. */
7104 if (cond_or == DOM_CC_NX_OR_Y)
7105 cond1 = reverse_condition (cond1);
7107 /* If the comparisons are not equal, and one doesn't dominate the other,
7108 then we can't do this. */
7110 && !comparison_dominates_p (cond1, cond2)
7111 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
7116 enum rtx_code temp = cond1;
7124 if (cond_or == DOM_CC_X_AND_Y)
7129 case EQ: return CC_DEQmode;
7130 case LE: return CC_DLEmode;
7131 case LEU: return CC_DLEUmode;
7132 case GE: return CC_DGEmode;
7133 case GEU: return CC_DGEUmode;
7134 default: gcc_unreachable ();
7138 if (cond_or == DOM_CC_X_AND_Y)
7154 if (cond_or == DOM_CC_X_AND_Y)
7170 if (cond_or == DOM_CC_X_AND_Y)
7186 if (cond_or == DOM_CC_X_AND_Y)
7201 /* The remaining cases only occur when both comparisons are the
7204 gcc_assert (cond1 == cond2);
7208 gcc_assert (cond1 == cond2);
7212 gcc_assert (cond1 == cond2);
7216 gcc_assert (cond1 == cond2);
7220 gcc_assert (cond1 == cond2);
7229 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
7231 /* All floating point compares return CCFP if it is an equality
7232 comparison, and CCFPE otherwise. */
7233 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
7253 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
7262 /* A compare with a shifted operand. Because of canonicalization, the
7263 comparison will have to be swapped when we emit the assembler. */
7264 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7265 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7266 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7267 || GET_CODE (x) == ROTATERT))
7270 /* This operation is performed swapped, but since we only rely on the Z
7271 flag we don't need an additional mode. */
7272 if (GET_MODE (y) == SImode && REG_P (y)
7273 && GET_CODE (x) == NEG
7274 && (op == EQ || op == NE))
7277 /* This is a special case that is used by combine to allow a
7278 comparison of a shifted byte load to be split into a zero-extend
7279 followed by a comparison of the shifted integer (only valid for
7280 equalities and unsigned inequalities). */
7281 if (GET_MODE (x) == SImode
7282 && GET_CODE (x) == ASHIFT
7283 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7284 && GET_CODE (XEXP (x, 0)) == SUBREG
7285 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7286 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7287 && (op == EQ || op == NE
7288 || op == GEU || op == GTU || op == LTU || op == LEU)
7289 && GET_CODE (y) == CONST_INT)
7292 /* A construct for a conditional compare, if the false arm contains
7293 0, then both conditions must be true, otherwise either condition
7294 must be true. Not all conditions are possible, so CCmode is
7295 returned if it can't be done. */
7296 if (GET_CODE (x) == IF_THEN_ELSE
7297 && (XEXP (x, 2) == const0_rtx
7298 || XEXP (x, 2) == const1_rtx)
7299 && COMPARISON_P (XEXP (x, 0))
7300 && COMPARISON_P (XEXP (x, 1)))
7301 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7302 INTVAL (XEXP (x, 2)));
7304 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7305 if (GET_CODE (x) == AND
7306 && COMPARISON_P (XEXP (x, 0))
7307 && COMPARISON_P (XEXP (x, 1)))
7308 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7311 if (GET_CODE (x) == IOR
7312 && COMPARISON_P (XEXP (x, 0))
7313 && COMPARISON_P (XEXP (x, 1)))
7314 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7317 /* An operation (on Thumb) where we want to test for a single bit.
7318 This is done by shifting that bit up into the top bit of a
7319 scratch register; we can then branch on the sign bit. */
7321 && GET_MODE (x) == SImode
7322 && (op == EQ || op == NE)
7323 && GET_CODE (x) == ZERO_EXTRACT
7324 && XEXP (x, 1) == const1_rtx)
7327 /* An operation that sets the condition codes as a side-effect, the
7328 V flag is not set correctly, so we can only use comparisons where
7329 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7331 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7332 if (GET_MODE (x) == SImode
7334 && (op == EQ || op == NE || op == LT || op == GE)
7335 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7336 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7337 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7338 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7339 || GET_CODE (x) == LSHIFTRT
7340 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7341 || GET_CODE (x) == ROTATERT
7342 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
7345 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7348 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7349 && GET_CODE (x) == PLUS
7350 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7356 /* X and Y are two things to compare using CODE. Emit the compare insn and
7357 return the rtx for register 0 in the proper mode. FP means this is a
7358 floating point compare: I don't think that it is needed on the arm. */
7360 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
7362 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
7363 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
7365 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
7370 /* Generate a sequence of insns that will generate the correct return
7371 address mask depending on the physical architecture that the program
7374 arm_gen_return_addr_mask (void)
7376 rtx reg = gen_reg_rtx (Pmode);
7378 emit_insn (gen_return_addr_mask (reg));
7383 arm_reload_in_hi (rtx *operands)
7385 rtx ref = operands[1];
7387 HOST_WIDE_INT offset = 0;
7389 if (GET_CODE (ref) == SUBREG)
7391 offset = SUBREG_BYTE (ref);
7392 ref = SUBREG_REG (ref);
7395 if (GET_CODE (ref) == REG)
7397 /* We have a pseudo which has been spilt onto the stack; there
7398 are two cases here: the first where there is a simple
7399 stack-slot replacement and a second where the stack-slot is
7400 out of range, or is used as a subreg. */
7401 if (reg_equiv_mem[REGNO (ref)])
7403 ref = reg_equiv_mem[REGNO (ref)];
7404 base = find_replacement (&XEXP (ref, 0));
7407 /* The slot is out of range, or was dressed up in a SUBREG. */
7408 base = reg_equiv_address[REGNO (ref)];
7411 base = find_replacement (&XEXP (ref, 0));
7413 /* Handle the case where the address is too complex to be offset by 1. */
7414 if (GET_CODE (base) == MINUS
7415 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7417 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7419 emit_set_insn (base_plus, base);
7422 else if (GET_CODE (base) == PLUS)
7424 /* The addend must be CONST_INT, or we would have dealt with it above. */
7425 HOST_WIDE_INT hi, lo;
7427 offset += INTVAL (XEXP (base, 1));
7428 base = XEXP (base, 0);
7430 /* Rework the address into a legal sequence of insns. */
7431 /* Valid range for lo is -4095 -> 4095 */
7434 : -((-offset) & 0xfff));
7436 /* Corner case, if lo is the max offset then we would be out of range
7437 once we have added the additional 1 below, so bump the msb into the
7438 pre-loading insn(s). */
7442 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7443 ^ (HOST_WIDE_INT) 0x80000000)
7444 - (HOST_WIDE_INT) 0x80000000);
7446 gcc_assert (hi + lo == offset);
7450 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7452 /* Get the base address; addsi3 knows how to handle constants
7453 that require more than one insn. */
7454 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7460 /* Operands[2] may overlap operands[0] (though it won't overlap
7461 operands[1]), that's why we asked for a DImode reg -- so we can
7462 use the bit that does not overlap. */
7463 if (REGNO (operands[2]) == REGNO (operands[0]))
7464 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7466 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7468 emit_insn (gen_zero_extendqisi2 (scratch,
7469 gen_rtx_MEM (QImode,
7470 plus_constant (base,
7472 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
7473 gen_rtx_MEM (QImode,
7474 plus_constant (base,
7476 if (!BYTES_BIG_ENDIAN)
7477 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7478 gen_rtx_IOR (SImode,
7481 gen_rtx_SUBREG (SImode, operands[0], 0),
7485 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7486 gen_rtx_IOR (SImode,
7487 gen_rtx_ASHIFT (SImode, scratch,
7489 gen_rtx_SUBREG (SImode, operands[0], 0)));
7492 /* Handle storing a half-word to memory during reload by synthesizing as two
7493 byte stores. Take care not to clobber the input values until after we
7494 have moved them somewhere safe. This code assumes that if the DImode
7495 scratch in operands[2] overlaps either the input value or output address
7496 in some way, then that value must die in this insn (we absolutely need
7497 two scratch registers for some corner cases). */
7499 arm_reload_out_hi (rtx *operands)
7501 rtx ref = operands[0];
7502 rtx outval = operands[1];
7504 HOST_WIDE_INT offset = 0;
7506 if (GET_CODE (ref) == SUBREG)
7508 offset = SUBREG_BYTE (ref);
7509 ref = SUBREG_REG (ref);
7512 if (GET_CODE (ref) == REG)
7514 /* We have a pseudo which has been spilt onto the stack; there
7515 are two cases here: the first where there is a simple
7516 stack-slot replacement and a second where the stack-slot is
7517 out of range, or is used as a subreg. */
7518 if (reg_equiv_mem[REGNO (ref)])
7520 ref = reg_equiv_mem[REGNO (ref)];
7521 base = find_replacement (&XEXP (ref, 0));
7524 /* The slot is out of range, or was dressed up in a SUBREG. */
7525 base = reg_equiv_address[REGNO (ref)];
7528 base = find_replacement (&XEXP (ref, 0));
7530 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7532 /* Handle the case where the address is too complex to be offset by 1. */
7533 if (GET_CODE (base) == MINUS
7534 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7536 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7538 /* Be careful not to destroy OUTVAL. */
7539 if (reg_overlap_mentioned_p (base_plus, outval))
7541 /* Updating base_plus might destroy outval, see if we can
7542 swap the scratch and base_plus. */
7543 if (!reg_overlap_mentioned_p (scratch, outval))
7546 scratch = base_plus;
7551 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7553 /* Be conservative and copy OUTVAL into the scratch now,
7554 this should only be necessary if outval is a subreg
7555 of something larger than a word. */
7556 /* XXX Might this clobber base? I can't see how it can,
7557 since scratch is known to overlap with OUTVAL, and
7558 must be wider than a word. */
7559 emit_insn (gen_movhi (scratch_hi, outval));
7560 outval = scratch_hi;
7564 emit_set_insn (base_plus, base);
7567 else if (GET_CODE (base) == PLUS)
7569 /* The addend must be CONST_INT, or we would have dealt with it above. */
7570 HOST_WIDE_INT hi, lo;
7572 offset += INTVAL (XEXP (base, 1));
7573 base = XEXP (base, 0);
7575 /* Rework the address into a legal sequence of insns. */
7576 /* Valid range for lo is -4095 -> 4095 */
7579 : -((-offset) & 0xfff));
7581 /* Corner case, if lo is the max offset then we would be out of range
7582 once we have added the additional 1 below, so bump the msb into the
7583 pre-loading insn(s). */
7587 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7588 ^ (HOST_WIDE_INT) 0x80000000)
7589 - (HOST_WIDE_INT) 0x80000000);
7591 gcc_assert (hi + lo == offset);
7595 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7597 /* Be careful not to destroy OUTVAL. */
7598 if (reg_overlap_mentioned_p (base_plus, outval))
7600 /* Updating base_plus might destroy outval, see if we
7601 can swap the scratch and base_plus. */
7602 if (!reg_overlap_mentioned_p (scratch, outval))
7605 scratch = base_plus;
7610 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7612 /* Be conservative and copy outval into scratch now,
7613 this should only be necessary if outval is a
7614 subreg of something larger than a word. */
7615 /* XXX Might this clobber base? I can't see how it
7616 can, since scratch is known to overlap with
7618 emit_insn (gen_movhi (scratch_hi, outval));
7619 outval = scratch_hi;
7623 /* Get the base address; addsi3 knows how to handle constants
7624 that require more than one insn. */
7625 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7631 if (BYTES_BIG_ENDIAN)
7633 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7634 plus_constant (base, offset + 1)),
7635 gen_lowpart (QImode, outval)));
7636 emit_insn (gen_lshrsi3 (scratch,
7637 gen_rtx_SUBREG (SImode, outval, 0),
7639 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7640 gen_lowpart (QImode, scratch)));
7644 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7645 gen_lowpart (QImode, outval)));
7646 emit_insn (gen_lshrsi3 (scratch,
7647 gen_rtx_SUBREG (SImode, outval, 0),
7649 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7650 plus_constant (base, offset + 1)),
7651 gen_lowpart (QImode, scratch)));
7655 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7656 (padded to the size of a word) should be passed in a register. */
7659 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7661 if (TARGET_AAPCS_BASED)
7662 return must_pass_in_stack_var_size (mode, type);
7664 return must_pass_in_stack_var_size_or_pad (mode, type);
7668 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7669 Return true if an argument passed on the stack should be padded upwards,
7670 i.e. if the least-significant byte has useful data.
7671 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7672 aggregate types are placed in the lowest memory address. */
7675 arm_pad_arg_upward (enum machine_mode mode, tree type)
7677 if (!TARGET_AAPCS_BASED)
7678 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7680 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7687 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7688 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7689 byte of the register has useful data, and return the opposite if the
7690 most significant byte does.
7691 For AAPCS, small aggregates and small complex types are always padded
7695 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7696 tree type, int first ATTRIBUTE_UNUSED)
7698 if (TARGET_AAPCS_BASED
7700 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7701 && int_size_in_bytes (type) <= 4)
7704 /* Otherwise, use default padding. */
7705 return !BYTES_BIG_ENDIAN;
7709 /* Print a symbolic form of X to the debug file, F. */
7711 arm_print_value (FILE *f, rtx x)
7713 switch (GET_CODE (x))
7716 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7720 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7728 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7730 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7731 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7739 fprintf (f, "\"%s\"", XSTR (x, 0));
7743 fprintf (f, "`%s'", XSTR (x, 0));
7747 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7751 arm_print_value (f, XEXP (x, 0));
7755 arm_print_value (f, XEXP (x, 0));
7757 arm_print_value (f, XEXP (x, 1));
7765 fprintf (f, "????");
7770 /* Routines for manipulation of the constant pool. */
7772 /* Arm instructions cannot load a large constant directly into a
7773 register; they have to come from a pc relative load. The constant
7774 must therefore be placed in the addressable range of the pc
7775 relative load. Depending on the precise pc relative load
7776 instruction the range is somewhere between 256 bytes and 4k. This
7777 means that we often have to dump a constant inside a function, and
7778 generate code to branch around it.
7780 It is important to minimize this, since the branches will slow
7781 things down and make the code larger.
7783 Normally we can hide the table after an existing unconditional
7784 branch so that there is no interruption of the flow, but in the
7785 worst case the code looks like this:
7803 We fix this by performing a scan after scheduling, which notices
7804 which instructions need to have their operands fetched from the
7805 constant table and builds the table.
7807 The algorithm starts by building a table of all the constants that
7808 need fixing up and all the natural barriers in the function (places
7809 where a constant table can be dropped without breaking the flow).
7810 For each fixup we note how far the pc-relative replacement will be
7811 able to reach and the offset of the instruction into the function.
7813 Having built the table we then group the fixes together to form
7814 tables that are as large as possible (subject to addressing
7815 constraints) and emit each table of constants after the last
7816 barrier that is within range of all the instructions in the group.
7817 If a group does not contain a barrier, then we forcibly create one
7818 by inserting a jump instruction into the flow. Once the table has
7819 been inserted, the insns are then modified to reference the
7820 relevant entry in the pool.
7822 Possible enhancements to the algorithm (not implemented) are:
7824 1) For some processors and object formats, there may be benefit in
7825 aligning the pools to the start of cache lines; this alignment
7826 would need to be taken into account when calculating addressability
7829 /* These typedefs are located at the start of this file, so that
7830 they can be used in the prototypes there. This comment is to
7831 remind readers of that fact so that the following structures
7832 can be understood more easily.
7834 typedef struct minipool_node Mnode;
7835 typedef struct minipool_fixup Mfix; */
7837 struct minipool_node
7839 /* Doubly linked chain of entries. */
7842 /* The maximum offset into the code that this entry can be placed. While
7843 pushing fixes for forward references, all entries are sorted in order
7844 of increasing max_address. */
7845 HOST_WIDE_INT max_address;
7846 /* Similarly for an entry inserted for a backwards ref. */
7847 HOST_WIDE_INT min_address;
7848 /* The number of fixes referencing this entry. This can become zero
7849 if we "unpush" an entry. In this case we ignore the entry when we
7850 come to emit the code. */
7852 /* The offset from the start of the minipool. */
7853 HOST_WIDE_INT offset;
7854 /* The value in table. */
7856 /* The mode of value. */
7857 enum machine_mode mode;
7858 /* The size of the value. With iWMMXt enabled
7859 sizes > 4 also imply an alignment of 8-bytes. */
7863 struct minipool_fixup
7867 HOST_WIDE_INT address;
7869 enum machine_mode mode;
7873 HOST_WIDE_INT forwards;
7874 HOST_WIDE_INT backwards;
7877 /* Fixes less than a word need padding out to a word boundary. */
7878 #define MINIPOOL_FIX_SIZE(mode) \
7879 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7881 static Mnode * minipool_vector_head;
7882 static Mnode * minipool_vector_tail;
7883 static rtx minipool_vector_label;
7884 static int minipool_pad;
7886 /* The linked list of all minipool fixes required for this function. */
7887 Mfix * minipool_fix_head;
7888 Mfix * minipool_fix_tail;
7889 /* The fix entry for the current minipool, once it has been placed. */
7890 Mfix * minipool_barrier;
7892 /* Determines if INSN is the start of a jump table. Returns the end
7893 of the TABLE or NULL_RTX. */
7895 is_jump_table (rtx insn)
7899 if (GET_CODE (insn) == JUMP_INSN
7900 && JUMP_LABEL (insn) != NULL
7901 && ((table = next_real_insn (JUMP_LABEL (insn)))
7902 == next_real_insn (insn))
7904 && GET_CODE (table) == JUMP_INSN
7905 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7906 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7912 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7913 #define JUMP_TABLES_IN_TEXT_SECTION 0
7916 static HOST_WIDE_INT
7917 get_jump_table_size (rtx insn)
7919 /* ADDR_VECs only take room if read-only data does into the text
7921 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7923 rtx body = PATTERN (insn);
7924 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7926 HOST_WIDE_INT modesize;
7928 modesize = GET_MODE_SIZE (GET_MODE (body));
7929 size = modesize * XVECLEN (body, elt);
7933 /* Round up size of TBB table to a halfword boundary. */
7934 size = (size + 1) & ~(HOST_WIDE_INT)1;
7937 /* No padding necessary for TBH. */
7940 /* Add two bytes for alignment on Thumb. */
7953 /* Move a minipool fix MP from its current location to before MAX_MP.
7954 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7955 constraints may need updating. */
7957 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7958 HOST_WIDE_INT max_address)
7960 /* The code below assumes these are different. */
7961 gcc_assert (mp != max_mp);
7965 if (max_address < mp->max_address)
7966 mp->max_address = max_address;
7970 if (max_address > max_mp->max_address - mp->fix_size)
7971 mp->max_address = max_mp->max_address - mp->fix_size;
7973 mp->max_address = max_address;
7975 /* Unlink MP from its current position. Since max_mp is non-null,
7976 mp->prev must be non-null. */
7977 mp->prev->next = mp->next;
7978 if (mp->next != NULL)
7979 mp->next->prev = mp->prev;
7981 minipool_vector_tail = mp->prev;
7983 /* Re-insert it before MAX_MP. */
7985 mp->prev = max_mp->prev;
7988 if (mp->prev != NULL)
7989 mp->prev->next = mp;
7991 minipool_vector_head = mp;
7994 /* Save the new entry. */
7997 /* Scan over the preceding entries and adjust their addresses as
7999 while (mp->prev != NULL
8000 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8002 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8009 /* Add a constant to the minipool for a forward reference. Returns the
8010 node added or NULL if the constant will not fit in this pool. */
8012 add_minipool_forward_ref (Mfix *fix)
8014 /* If set, max_mp is the first pool_entry that has a lower
8015 constraint than the one we are trying to add. */
8016 Mnode * max_mp = NULL;
8017 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
8020 /* If the minipool starts before the end of FIX->INSN then this FIX
8021 can not be placed into the current pool. Furthermore, adding the
8022 new constant pool entry may cause the pool to start FIX_SIZE bytes
8024 if (minipool_vector_head &&
8025 (fix->address + get_attr_length (fix->insn)
8026 >= minipool_vector_head->max_address - fix->fix_size))
8029 /* Scan the pool to see if a constant with the same value has
8030 already been added. While we are doing this, also note the
8031 location where we must insert the constant if it doesn't already
8033 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8035 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8036 && fix->mode == mp->mode
8037 && (GET_CODE (fix->value) != CODE_LABEL
8038 || (CODE_LABEL_NUMBER (fix->value)
8039 == CODE_LABEL_NUMBER (mp->value)))
8040 && rtx_equal_p (fix->value, mp->value))
8042 /* More than one fix references this entry. */
8044 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
8047 /* Note the insertion point if necessary. */
8049 && mp->max_address > max_address)
8052 /* If we are inserting an 8-bytes aligned quantity and
8053 we have not already found an insertion point, then
8054 make sure that all such 8-byte aligned quantities are
8055 placed at the start of the pool. */
8056 if (ARM_DOUBLEWORD_ALIGN
8058 && fix->fix_size == 8
8059 && mp->fix_size != 8)
8062 max_address = mp->max_address;
8066 /* The value is not currently in the minipool, so we need to create
8067 a new entry for it. If MAX_MP is NULL, the entry will be put on
8068 the end of the list since the placement is less constrained than
8069 any existing entry. Otherwise, we insert the new fix before
8070 MAX_MP and, if necessary, adjust the constraints on the other
8073 mp->fix_size = fix->fix_size;
8074 mp->mode = fix->mode;
8075 mp->value = fix->value;
8077 /* Not yet required for a backwards ref. */
8078 mp->min_address = -65536;
8082 mp->max_address = max_address;
8084 mp->prev = minipool_vector_tail;
8086 if (mp->prev == NULL)
8088 minipool_vector_head = mp;
8089 minipool_vector_label = gen_label_rtx ();
8092 mp->prev->next = mp;
8094 minipool_vector_tail = mp;
8098 if (max_address > max_mp->max_address - mp->fix_size)
8099 mp->max_address = max_mp->max_address - mp->fix_size;
8101 mp->max_address = max_address;
8104 mp->prev = max_mp->prev;
8106 if (mp->prev != NULL)
8107 mp->prev->next = mp;
8109 minipool_vector_head = mp;
8112 /* Save the new entry. */
8115 /* Scan over the preceding entries and adjust their addresses as
8117 while (mp->prev != NULL
8118 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8120 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8128 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
8129 HOST_WIDE_INT min_address)
8131 HOST_WIDE_INT offset;
8133 /* The code below assumes these are different. */
8134 gcc_assert (mp != min_mp);
8138 if (min_address > mp->min_address)
8139 mp->min_address = min_address;
8143 /* We will adjust this below if it is too loose. */
8144 mp->min_address = min_address;
8146 /* Unlink MP from its current position. Since min_mp is non-null,
8147 mp->next must be non-null. */
8148 mp->next->prev = mp->prev;
8149 if (mp->prev != NULL)
8150 mp->prev->next = mp->next;
8152 minipool_vector_head = mp->next;
8154 /* Reinsert it after MIN_MP. */
8156 mp->next = min_mp->next;
8158 if (mp->next != NULL)
8159 mp->next->prev = mp;
8161 minipool_vector_tail = mp;
8167 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8169 mp->offset = offset;
8170 if (mp->refcount > 0)
8171 offset += mp->fix_size;
8173 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
8174 mp->next->min_address = mp->min_address + mp->fix_size;
8180 /* Add a constant to the minipool for a backward reference. Returns the
8181 node added or NULL if the constant will not fit in this pool.
8183 Note that the code for insertion for a backwards reference can be
8184 somewhat confusing because the calculated offsets for each fix do
8185 not take into account the size of the pool (which is still under
8188 add_minipool_backward_ref (Mfix *fix)
8190 /* If set, min_mp is the last pool_entry that has a lower constraint
8191 than the one we are trying to add. */
8192 Mnode *min_mp = NULL;
8193 /* This can be negative, since it is only a constraint. */
8194 HOST_WIDE_INT min_address = fix->address - fix->backwards;
8197 /* If we can't reach the current pool from this insn, or if we can't
8198 insert this entry at the end of the pool without pushing other
8199 fixes out of range, then we don't try. This ensures that we
8200 can't fail later on. */
8201 if (min_address >= minipool_barrier->address
8202 || (minipool_vector_tail->min_address + fix->fix_size
8203 >= minipool_barrier->address))
8206 /* Scan the pool to see if a constant with the same value has
8207 already been added. While we are doing this, also note the
8208 location where we must insert the constant if it doesn't already
8210 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
8212 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8213 && fix->mode == mp->mode
8214 && (GET_CODE (fix->value) != CODE_LABEL
8215 || (CODE_LABEL_NUMBER (fix->value)
8216 == CODE_LABEL_NUMBER (mp->value)))
8217 && rtx_equal_p (fix->value, mp->value)
8218 /* Check that there is enough slack to move this entry to the
8219 end of the table (this is conservative). */
8221 > (minipool_barrier->address
8222 + minipool_vector_tail->offset
8223 + minipool_vector_tail->fix_size)))
8226 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8230 mp->min_address += fix->fix_size;
8233 /* Note the insertion point if necessary. */
8234 if (mp->min_address < min_address)
8236 /* For now, we do not allow the insertion of 8-byte alignment
8237 requiring nodes anywhere but at the start of the pool. */
8238 if (ARM_DOUBLEWORD_ALIGN
8239 && fix->fix_size == 8 && mp->fix_size != 8)
8244 else if (mp->max_address
8245 < minipool_barrier->address + mp->offset + fix->fix_size)
8247 /* Inserting before this entry would push the fix beyond
8248 its maximum address (which can happen if we have
8249 re-located a forwards fix); force the new fix to come
8252 min_address = mp->min_address + fix->fix_size;
8254 /* If we are inserting an 8-bytes aligned quantity and
8255 we have not already found an insertion point, then
8256 make sure that all such 8-byte aligned quantities are
8257 placed at the start of the pool. */
8258 else if (ARM_DOUBLEWORD_ALIGN
8260 && fix->fix_size == 8
8261 && mp->fix_size < 8)
8264 min_address = mp->min_address + fix->fix_size;
8269 /* We need to create a new entry. */
8271 mp->fix_size = fix->fix_size;
8272 mp->mode = fix->mode;
8273 mp->value = fix->value;
8275 mp->max_address = minipool_barrier->address + 65536;
8277 mp->min_address = min_address;
8282 mp->next = minipool_vector_head;
8284 if (mp->next == NULL)
8286 minipool_vector_tail = mp;
8287 minipool_vector_label = gen_label_rtx ();
8290 mp->next->prev = mp;
8292 minipool_vector_head = mp;
8296 mp->next = min_mp->next;
8300 if (mp->next != NULL)
8301 mp->next->prev = mp;
8303 minipool_vector_tail = mp;
8306 /* Save the new entry. */
8314 /* Scan over the following entries and adjust their offsets. */
8315 while (mp->next != NULL)
8317 if (mp->next->min_address < mp->min_address + mp->fix_size)
8318 mp->next->min_address = mp->min_address + mp->fix_size;
8321 mp->next->offset = mp->offset + mp->fix_size;
8323 mp->next->offset = mp->offset;
8332 assign_minipool_offsets (Mfix *barrier)
8334 HOST_WIDE_INT offset = 0;
8337 minipool_barrier = barrier;
8339 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8341 mp->offset = offset;
8343 if (mp->refcount > 0)
8344 offset += mp->fix_size;
8348 /* Output the literal table */
8350 dump_minipool (rtx scan)
8356 if (ARM_DOUBLEWORD_ALIGN)
8357 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8358 if (mp->refcount > 0 && mp->fix_size == 8)
8366 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8367 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
8369 scan = emit_label_after (gen_label_rtx (), scan);
8370 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
8371 scan = emit_label_after (minipool_vector_label, scan);
8373 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8375 if (mp->refcount > 0)
8380 ";; Offset %u, min %ld, max %ld ",
8381 (unsigned) mp->offset, (unsigned long) mp->min_address,
8382 (unsigned long) mp->max_address);
8383 arm_print_value (dump_file, mp->value);
8384 fputc ('\n', dump_file);
8387 switch (mp->fix_size)
8389 #ifdef HAVE_consttable_1
8391 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8395 #ifdef HAVE_consttable_2
8397 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8401 #ifdef HAVE_consttable_4
8403 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8407 #ifdef HAVE_consttable_8
8409 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8422 minipool_vector_head = minipool_vector_tail = NULL;
8423 scan = emit_insn_after (gen_consttable_end (), scan);
8424 scan = emit_barrier_after (scan);
8427 /* Return the cost of forcibly inserting a barrier after INSN. */
8429 arm_barrier_cost (rtx insn)
8431 /* Basing the location of the pool on the loop depth is preferable,
8432 but at the moment, the basic block information seems to be
8433 corrupt by this stage of the compilation. */
8435 rtx next = next_nonnote_insn (insn);
8437 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8440 switch (GET_CODE (insn))
8443 /* It will always be better to place the table before the label, rather
8452 return base_cost - 10;
8455 return base_cost + 10;
8459 /* Find the best place in the insn stream in the range
8460 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8461 Create the barrier by inserting a jump and add a new fix entry for
8464 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
8466 HOST_WIDE_INT count = 0;
8468 rtx from = fix->insn;
8469 /* The instruction after which we will insert the jump. */
8470 rtx selected = NULL;
8472 /* The address at which the jump instruction will be placed. */
8473 HOST_WIDE_INT selected_address;
8475 HOST_WIDE_INT max_count = max_address - fix->address;
8476 rtx label = gen_label_rtx ();
8478 selected_cost = arm_barrier_cost (from);
8479 selected_address = fix->address;
8481 while (from && count < max_count)
8486 /* This code shouldn't have been called if there was a natural barrier
8488 gcc_assert (GET_CODE (from) != BARRIER);
8490 /* Count the length of this insn. */
8491 count += get_attr_length (from);
8493 /* If there is a jump table, add its length. */
8494 tmp = is_jump_table (from);
8497 count += get_jump_table_size (tmp);
8499 /* Jump tables aren't in a basic block, so base the cost on
8500 the dispatch insn. If we select this location, we will
8501 still put the pool after the table. */
8502 new_cost = arm_barrier_cost (from);
8504 if (count < max_count
8505 && (!selected || new_cost <= selected_cost))
8508 selected_cost = new_cost;
8509 selected_address = fix->address + count;
8512 /* Continue after the dispatch table. */
8513 from = NEXT_INSN (tmp);
8517 new_cost = arm_barrier_cost (from);
8519 if (count < max_count
8520 && (!selected || new_cost <= selected_cost))
8523 selected_cost = new_cost;
8524 selected_address = fix->address + count;
8527 from = NEXT_INSN (from);
8530 /* Make sure that we found a place to insert the jump. */
8531 gcc_assert (selected);
8533 /* Create a new JUMP_INSN that branches around a barrier. */
8534 from = emit_jump_insn_after (gen_jump (label), selected);
8535 JUMP_LABEL (from) = label;
8536 barrier = emit_barrier_after (from);
8537 emit_label_after (label, barrier);
8539 /* Create a minipool barrier entry for the new barrier. */
8540 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
8541 new_fix->insn = barrier;
8542 new_fix->address = selected_address;
8543 new_fix->next = fix->next;
8544 fix->next = new_fix;
8549 /* Record that there is a natural barrier in the insn stream at
8552 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
8554 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8557 fix->address = address;
8560 if (minipool_fix_head != NULL)
8561 minipool_fix_tail->next = fix;
8563 minipool_fix_head = fix;
8565 minipool_fix_tail = fix;
8568 /* Record INSN, which will need fixing up to load a value from the
8569 minipool. ADDRESS is the offset of the insn since the start of the
8570 function; LOC is a pointer to the part of the insn which requires
8571 fixing; VALUE is the constant that must be loaded, which is of type
8574 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8575 enum machine_mode mode, rtx value)
8577 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8579 #ifdef AOF_ASSEMBLER
8580 /* PIC symbol references need to be converted into offsets into the
8582 /* XXX This shouldn't be done here. */
8583 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8584 value = aof_pic_entry (value);
8585 #endif /* AOF_ASSEMBLER */
8588 fix->address = address;
8591 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8593 fix->forwards = get_attr_pool_range (insn);
8594 fix->backwards = get_attr_neg_pool_range (insn);
8595 fix->minipool = NULL;
8597 /* If an insn doesn't have a range defined for it, then it isn't
8598 expecting to be reworked by this code. Better to stop now than
8599 to generate duff assembly code. */
8600 gcc_assert (fix->forwards || fix->backwards);
8602 /* If an entry requires 8-byte alignment then assume all constant pools
8603 require 4 bytes of padding. Trying to do this later on a per-pool
8604 basis is awkward because existing pool entries have to be modified. */
8605 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8611 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8612 GET_MODE_NAME (mode),
8613 INSN_UID (insn), (unsigned long) address,
8614 -1 * (long)fix->backwards, (long)fix->forwards);
8615 arm_print_value (dump_file, fix->value);
8616 fprintf (dump_file, "\n");
8619 /* Add it to the chain of fixes. */
8622 if (minipool_fix_head != NULL)
8623 minipool_fix_tail->next = fix;
8625 minipool_fix_head = fix;
8627 minipool_fix_tail = fix;
8630 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8631 Returns the number of insns needed, or 99 if we don't know how to
8634 arm_const_double_inline_cost (rtx val)
8636 rtx lowpart, highpart;
8637 enum machine_mode mode;
8639 mode = GET_MODE (val);
8641 if (mode == VOIDmode)
8644 gcc_assert (GET_MODE_SIZE (mode) == 8);
8646 lowpart = gen_lowpart (SImode, val);
8647 highpart = gen_highpart_mode (SImode, mode, val);
8649 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8650 gcc_assert (GET_CODE (highpart) == CONST_INT);
8652 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8653 NULL_RTX, NULL_RTX, 0, 0)
8654 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8655 NULL_RTX, NULL_RTX, 0, 0));
8658 /* Return true if it is worthwhile to split a 64-bit constant into two
8659 32-bit operations. This is the case if optimizing for size, or
8660 if we have load delay slots, or if one 32-bit part can be done with
8661 a single data operation. */
8663 arm_const_double_by_parts (rtx val)
8665 enum machine_mode mode = GET_MODE (val);
8668 if (optimize_size || arm_ld_sched)
8671 if (mode == VOIDmode)
8674 part = gen_highpart_mode (SImode, mode, val);
8676 gcc_assert (GET_CODE (part) == CONST_INT);
8678 if (const_ok_for_arm (INTVAL (part))
8679 || const_ok_for_arm (~INTVAL (part)))
8682 part = gen_lowpart (SImode, val);
8684 gcc_assert (GET_CODE (part) == CONST_INT);
8686 if (const_ok_for_arm (INTVAL (part))
8687 || const_ok_for_arm (~INTVAL (part)))
8693 /* Scan INSN and note any of its operands that need fixing.
8694 If DO_PUSHES is false we do not actually push any of the fixups
8695 needed. The function returns TRUE if any fixups were needed/pushed.
8696 This is used by arm_memory_load_p() which needs to know about loads
8697 of constants that will be converted into minipool loads. */
8699 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8701 bool result = false;
8704 extract_insn (insn);
8706 if (!constrain_operands (1))
8707 fatal_insn_not_found (insn);
8709 if (recog_data.n_alternatives == 0)
8712 /* Fill in recog_op_alt with information about the constraints of
8714 preprocess_constraints ();
8716 for (opno = 0; opno < recog_data.n_operands; opno++)
8718 /* Things we need to fix can only occur in inputs. */
8719 if (recog_data.operand_type[opno] != OP_IN)
8722 /* If this alternative is a memory reference, then any mention
8723 of constants in this alternative is really to fool reload
8724 into allowing us to accept one there. We need to fix them up
8725 now so that we output the right code. */
8726 if (recog_op_alt[opno][which_alternative].memory_ok)
8728 rtx op = recog_data.operand[opno];
8730 if (CONSTANT_P (op))
8733 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8734 recog_data.operand_mode[opno], op);
8737 else if (GET_CODE (op) == MEM
8738 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8739 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8743 rtx cop = avoid_constant_pool_reference (op);
8745 /* Casting the address of something to a mode narrower
8746 than a word can cause avoid_constant_pool_reference()
8747 to return the pool reference itself. That's no good to
8748 us here. Lets just hope that we can use the
8749 constant pool value directly. */
8751 cop = get_pool_constant (XEXP (op, 0));
8753 push_minipool_fix (insn, address,
8754 recog_data.operand_loc[opno],
8755 recog_data.operand_mode[opno], cop);
8766 /* Gcc puts the pool in the wrong place for ARM, since we can only
8767 load addresses a limited distance around the pc. We do some
8768 special munging to move the constant pool values to the correct
8769 point in the code. */
8774 HOST_WIDE_INT address = 0;
8777 minipool_fix_head = minipool_fix_tail = NULL;
8779 /* The first insn must always be a note, or the code below won't
8780 scan it properly. */
8781 insn = get_insns ();
8782 gcc_assert (GET_CODE (insn) == NOTE);
8785 /* Scan all the insns and record the operands that will need fixing. */
8786 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8788 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8789 && (arm_cirrus_insn_p (insn)
8790 || GET_CODE (insn) == JUMP_INSN
8791 || arm_memory_load_p (insn)))
8792 cirrus_reorg (insn);
8794 if (GET_CODE (insn) == BARRIER)
8795 push_minipool_barrier (insn, address);
8796 else if (INSN_P (insn))
8800 note_invalid_constants (insn, address, true);
8801 address += get_attr_length (insn);
8803 /* If the insn is a vector jump, add the size of the table
8804 and skip the table. */
8805 if ((table = is_jump_table (insn)) != NULL)
8807 address += get_jump_table_size (table);
8813 fix = minipool_fix_head;
8815 /* Now scan the fixups and perform the required changes. */
8820 Mfix * last_added_fix;
8821 Mfix * last_barrier = NULL;
8824 /* Skip any further barriers before the next fix. */
8825 while (fix && GET_CODE (fix->insn) == BARRIER)
8828 /* No more fixes. */
8832 last_added_fix = NULL;
8834 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8836 if (GET_CODE (ftmp->insn) == BARRIER)
8838 if (ftmp->address >= minipool_vector_head->max_address)
8841 last_barrier = ftmp;
8843 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8846 last_added_fix = ftmp; /* Keep track of the last fix added. */
8849 /* If we found a barrier, drop back to that; any fixes that we
8850 could have reached but come after the barrier will now go in
8851 the next mini-pool. */
8852 if (last_barrier != NULL)
8854 /* Reduce the refcount for those fixes that won't go into this
8856 for (fdel = last_barrier->next;
8857 fdel && fdel != ftmp;
8860 fdel->minipool->refcount--;
8861 fdel->minipool = NULL;
8864 ftmp = last_barrier;
8868 /* ftmp is first fix that we can't fit into this pool and
8869 there no natural barriers that we could use. Insert a
8870 new barrier in the code somewhere between the previous
8871 fix and this one, and arrange to jump around it. */
8872 HOST_WIDE_INT max_address;
8874 /* The last item on the list of fixes must be a barrier, so
8875 we can never run off the end of the list of fixes without
8876 last_barrier being set. */
8879 max_address = minipool_vector_head->max_address;
8880 /* Check that there isn't another fix that is in range that
8881 we couldn't fit into this pool because the pool was
8882 already too large: we need to put the pool before such an
8883 instruction. The pool itself may come just after the
8884 fix because create_fix_barrier also allows space for a
8885 jump instruction. */
8886 if (ftmp->address < max_address)
8887 max_address = ftmp->address + 1;
8889 last_barrier = create_fix_barrier (last_added_fix, max_address);
8892 assign_minipool_offsets (last_barrier);
8896 if (GET_CODE (ftmp->insn) != BARRIER
8897 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8904 /* Scan over the fixes we have identified for this pool, fixing them
8905 up and adding the constants to the pool itself. */
8906 for (this_fix = fix; this_fix && ftmp != this_fix;
8907 this_fix = this_fix->next)
8908 if (GET_CODE (this_fix->insn) != BARRIER)
8911 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8912 minipool_vector_label),
8913 this_fix->minipool->offset);
8914 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8917 dump_minipool (last_barrier->insn);
8921 /* From now on we must synthesize any constants that we can't handle
8922 directly. This can happen if the RTL gets split during final
8923 instruction generation. */
8924 after_arm_reorg = 1;
8926 /* Free the minipool memory. */
8927 obstack_free (&minipool_obstack, minipool_startobj);
8930 /* Routines to output assembly language. */
8932 /* If the rtx is the correct value then return the string of the number.
8933 In this way we can ensure that valid double constants are generated even
8934 when cross compiling. */
8936 fp_immediate_constant (rtx x)
8941 if (!fp_consts_inited)
8944 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8945 for (i = 0; i < 8; i++)
8946 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8947 return strings_fp[i];
8952 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8954 fp_const_from_val (REAL_VALUE_TYPE *r)
8958 if (!fp_consts_inited)
8961 for (i = 0; i < 8; i++)
8962 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8963 return strings_fp[i];
8968 /* Output the operands of a LDM/STM instruction to STREAM.
8969 MASK is the ARM register set mask of which only bits 0-15 are important.
8970 REG is the base register, either the frame pointer or the stack pointer,
8971 INSTR is the possibly suffixed load or store instruction.
8972 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8975 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8976 unsigned long mask, int rfe)
8979 bool not_first = FALSE;
8981 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
8982 fputc ('\t', stream);
8983 asm_fprintf (stream, instr, reg);
8984 fputc ('{', stream);
8986 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8987 if (mask & (1 << i))
8990 fprintf (stream, ", ");
8992 asm_fprintf (stream, "%r", i);
8997 fprintf (stream, "}^\n");
8999 fprintf (stream, "}\n");
9003 /* Output a FLDMD instruction to STREAM.
9004 BASE if the register containing the address.
9005 REG and COUNT specify the register range.
9006 Extra registers may be added to avoid hardware bugs.
9008 We output FLDMD even for ARMv5 VFP implementations. Although
9009 FLDMD is technically not supported until ARMv6, it is believed
9010 that all VFP implementations support its use in this context. */
9013 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
9017 /* Workaround ARM10 VFPr1 bug. */
9018 if (count == 2 && !arm_arch6)
9025 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
9026 load into multiple parts if we have to handle more than 16 registers. */
9029 vfp_output_fldmd (stream, base, reg, 16);
9030 vfp_output_fldmd (stream, base, reg + 16, count - 16);
9034 fputc ('\t', stream);
9035 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
9037 for (i = reg; i < reg + count; i++)
9040 fputs (", ", stream);
9041 asm_fprintf (stream, "d%d", i);
9043 fputs ("}\n", stream);
9048 /* Output the assembly for a store multiple. */
9051 vfp_output_fstmd (rtx * operands)
9058 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
9059 p = strlen (pattern);
9061 gcc_assert (GET_CODE (operands[1]) == REG);
9063 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
9064 for (i = 1; i < XVECLEN (operands[2], 0); i++)
9066 p += sprintf (&pattern[p], ", d%d", base + i);
9068 strcpy (&pattern[p], "}");
9070 output_asm_insn (pattern, operands);
9075 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
9076 number of bytes pushed. */
9079 vfp_emit_fstmd (int base_reg, int count)
9086 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
9087 register pairs are stored by a store multiple insn. We avoid this
9088 by pushing an extra pair. */
9089 if (count == 2 && !arm_arch6)
9091 if (base_reg == LAST_VFP_REGNUM - 3)
9096 /* FSTMD may not store more than 16 doubleword registers at once. Split
9097 larger stores into multiple parts (up to a maximum of two, in
9102 /* NOTE: base_reg is an internal register number, so each D register
9104 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
9105 saved += vfp_emit_fstmd (base_reg, 16);
9109 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9110 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9112 reg = gen_rtx_REG (DFmode, base_reg);
9116 = gen_rtx_SET (VOIDmode,
9117 gen_frame_mem (BLKmode,
9118 gen_rtx_PRE_DEC (BLKmode,
9119 stack_pointer_rtx)),
9120 gen_rtx_UNSPEC (BLKmode,
9124 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9125 plus_constant (stack_pointer_rtx, -(count * 8)));
9126 RTX_FRAME_RELATED_P (tmp) = 1;
9127 XVECEXP (dwarf, 0, 0) = tmp;
9129 tmp = gen_rtx_SET (VOIDmode,
9130 gen_frame_mem (DFmode, stack_pointer_rtx),
9132 RTX_FRAME_RELATED_P (tmp) = 1;
9133 XVECEXP (dwarf, 0, 1) = tmp;
9135 for (i = 1; i < count; i++)
9137 reg = gen_rtx_REG (DFmode, base_reg);
9139 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9141 tmp = gen_rtx_SET (VOIDmode,
9142 gen_frame_mem (DFmode,
9143 plus_constant (stack_pointer_rtx,
9146 RTX_FRAME_RELATED_P (tmp) = 1;
9147 XVECEXP (dwarf, 0, i + 1) = tmp;
9150 par = emit_insn (par);
9151 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9153 RTX_FRAME_RELATED_P (par) = 1;
9158 /* Emit a call instruction with pattern PAT. ADDR is the address of
9162 arm_emit_call_insn (rtx pat, rtx addr)
9166 insn = emit_call_insn (pat);
9168 /* The PIC register is live on entry to VxWorks PIC PLT entries.
9169 If the call might use such an entry, add a use of the PIC register
9170 to the instruction's CALL_INSN_FUNCTION_USAGE. */
9171 if (TARGET_VXWORKS_RTP
9173 && GET_CODE (addr) == SYMBOL_REF
9174 && (SYMBOL_REF_DECL (addr)
9175 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
9176 : !SYMBOL_REF_LOCAL_P (addr)))
9178 require_pic_register ();
9179 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
9183 /* Output a 'call' insn. */
9185 output_call (rtx *operands)
9187 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
9189 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
9190 if (REGNO (operands[0]) == LR_REGNUM)
9192 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
9193 output_asm_insn ("mov%?\t%0, %|lr", operands);
9196 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9198 if (TARGET_INTERWORK || arm_arch4t)
9199 output_asm_insn ("bx%?\t%0", operands);
9201 output_asm_insn ("mov%?\t%|pc, %0", operands);
9206 /* Output a 'call' insn that is a reference in memory. */
9208 output_call_mem (rtx *operands)
9210 if (TARGET_INTERWORK && !arm_arch5)
9212 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9213 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9214 output_asm_insn ("bx%?\t%|ip", operands);
9216 else if (regno_use_in (LR_REGNUM, operands[0]))
9218 /* LR is used in the memory address. We load the address in the
9219 first instruction. It's safe to use IP as the target of the
9220 load since the call will kill it anyway. */
9221 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9223 output_asm_insn ("blx%?\t%|ip", operands);
9226 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9228 output_asm_insn ("bx%?\t%|ip", operands);
9230 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
9235 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9236 output_asm_insn ("ldr%?\t%|pc, %0", operands);
9243 /* Output a move from arm registers to an fpa registers.
9244 OPERANDS[0] is an fpa register.
9245 OPERANDS[1] is the first registers of an arm register pair. */
9247 output_mov_long_double_fpa_from_arm (rtx *operands)
9249 int arm_reg0 = REGNO (operands[1]);
9252 gcc_assert (arm_reg0 != IP_REGNUM);
9254 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9255 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9256 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9258 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9259 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
9264 /* Output a move from an fpa register to arm registers.
9265 OPERANDS[0] is the first registers of an arm register pair.
9266 OPERANDS[1] is an fpa register. */
9268 output_mov_long_double_arm_from_fpa (rtx *operands)
9270 int arm_reg0 = REGNO (operands[0]);
9273 gcc_assert (arm_reg0 != IP_REGNUM);
9275 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9276 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9277 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9279 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
9280 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9284 /* Output a move from arm registers to arm registers of a long double
9285 OPERANDS[0] is the destination.
9286 OPERANDS[1] is the source. */
9288 output_mov_long_double_arm_from_arm (rtx *operands)
9290 /* We have to be careful here because the two might overlap. */
9291 int dest_start = REGNO (operands[0]);
9292 int src_start = REGNO (operands[1]);
9296 if (dest_start < src_start)
9298 for (i = 0; i < 3; i++)
9300 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9301 ops[1] = gen_rtx_REG (SImode, src_start + i);
9302 output_asm_insn ("mov%?\t%0, %1", ops);
9307 for (i = 2; i >= 0; i--)
9309 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9310 ops[1] = gen_rtx_REG (SImode, src_start + i);
9311 output_asm_insn ("mov%?\t%0, %1", ops);
9319 /* Output a move from arm registers to an fpa registers.
9320 OPERANDS[0] is an fpa register.
9321 OPERANDS[1] is the first registers of an arm register pair. */
9323 output_mov_double_fpa_from_arm (rtx *operands)
9325 int arm_reg0 = REGNO (operands[1]);
9328 gcc_assert (arm_reg0 != IP_REGNUM);
9330 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9331 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9332 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
9333 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
9337 /* Output a move from an fpa register to arm registers.
9338 OPERANDS[0] is the first registers of an arm register pair.
9339 OPERANDS[1] is an fpa register. */
9341 output_mov_double_arm_from_fpa (rtx *operands)
9343 int arm_reg0 = REGNO (operands[0]);
9346 gcc_assert (arm_reg0 != IP_REGNUM);
9348 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9349 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9350 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
9351 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
9355 /* Output a move between double words.
9356 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9357 or MEM<-REG and all MEMs must be offsettable addresses. */
9359 output_move_double (rtx *operands)
9361 enum rtx_code code0 = GET_CODE (operands[0]);
9362 enum rtx_code code1 = GET_CODE (operands[1]);
9367 int reg0 = REGNO (operands[0]);
9369 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9371 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9373 switch (GET_CODE (XEXP (operands[1], 0)))
9376 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
9380 gcc_assert (TARGET_LDRD);
9381 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
9386 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9388 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
9392 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
9396 gcc_assert (TARGET_LDRD);
9397 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
9402 otherops[0] = operands[0];
9403 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9404 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
9406 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
9408 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9410 /* Registers overlap so split out the increment. */
9411 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9412 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
9416 /* IWMMXT allows offsets larger than ldrd can handle,
9417 fix these up with a pair of ldr. */
9418 if (GET_CODE (otherops[2]) == CONST_INT
9419 && (INTVAL(otherops[2]) <= -256
9420 || INTVAL(otherops[2]) >= 256))
9422 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9423 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9424 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9427 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9432 /* IWMMXT allows offsets larger than ldrd can handle,
9433 fix these up with a pair of ldr. */
9434 if (GET_CODE (otherops[2]) == CONST_INT
9435 && (INTVAL(otherops[2]) <= -256
9436 || INTVAL(otherops[2]) >= 256))
9438 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9439 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9440 otherops[0] = operands[0];
9441 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9444 /* We only allow constant increments, so this is safe. */
9445 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
9451 output_asm_insn ("adr%?\t%0, %1", operands);
9452 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
9455 /* ??? This needs checking for thumb2. */
9457 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9458 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9460 otherops[0] = operands[0];
9461 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9462 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
9464 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
9466 if (GET_CODE (otherops[2]) == CONST_INT)
9468 switch ((int) INTVAL (otherops[2]))
9471 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
9476 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
9481 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
9486 && (GET_CODE (otherops[2]) == REG
9487 || (GET_CODE (otherops[2]) == CONST_INT
9488 && INTVAL (otherops[2]) > -256
9489 && INTVAL (otherops[2]) < 256)))
9491 if (reg_overlap_mentioned_p (otherops[0],
9494 /* Swap base and index registers over to
9495 avoid a conflict. */
9496 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9497 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
9499 /* If both registers conflict, it will usually
9500 have been fixed by a splitter. */
9501 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9503 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9504 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9508 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
9512 if (GET_CODE (otherops[2]) == CONST_INT)
9514 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
9515 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
9517 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9520 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9523 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
9525 return "ldm%(ia%)\t%0, %M0";
9529 otherops[1] = adjust_address (operands[1], SImode, 4);
9530 /* Take care of overlapping base/data reg. */
9531 if (reg_mentioned_p (operands[0], operands[1]))
9533 output_asm_insn ("ldr%?\t%0, %1", otherops);
9534 output_asm_insn ("ldr%?\t%0, %1", operands);
9538 output_asm_insn ("ldr%?\t%0, %1", operands);
9539 output_asm_insn ("ldr%?\t%0, %1", otherops);
9546 /* Constraints should ensure this. */
9547 gcc_assert (code0 == MEM && code1 == REG);
9548 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
9550 switch (GET_CODE (XEXP (operands[0], 0)))
9553 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9557 gcc_assert (TARGET_LDRD);
9558 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9563 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
9565 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9569 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9573 gcc_assert (TARGET_LDRD);
9574 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
9579 otherops[0] = operands[1];
9580 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
9581 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
9583 /* IWMMXT allows offsets larger than ldrd can handle,
9584 fix these up with a pair of ldr. */
9585 if (GET_CODE (otherops[2]) == CONST_INT
9586 && (INTVAL(otherops[2]) <= -256
9587 || INTVAL(otherops[2]) >= 256))
9590 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9591 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9593 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9595 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9600 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9601 otherops[0] = operands[1];
9602 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9605 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9606 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
9608 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9612 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
9613 if (GET_CODE (otherops[2]) == CONST_INT)
9615 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
9618 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
9624 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
9630 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
9635 && (GET_CODE (otherops[2]) == REG
9636 || (GET_CODE (otherops[2]) == CONST_INT
9637 && INTVAL (otherops[2]) > -256
9638 && INTVAL (otherops[2]) < 256)))
9640 otherops[0] = operands[1];
9641 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9642 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
9648 otherops[0] = adjust_address (operands[0], SImode, 4);
9649 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9650 output_asm_insn ("str%?\t%1, %0", operands);
9651 output_asm_insn ("str%?\t%1, %0", otherops);
9658 /* Output a VFP load or store instruction. */
9661 output_move_vfp (rtx *operands)
9663 rtx reg, mem, addr, ops[2];
9664 int load = REG_P (operands[0]);
9665 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
9666 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
9667 const char *template;
9670 reg = operands[!load];
9671 mem = operands[load];
9673 gcc_assert (REG_P (reg));
9674 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
9675 gcc_assert (GET_MODE (reg) == SFmode
9676 || GET_MODE (reg) == DFmode
9677 || GET_MODE (reg) == SImode
9678 || GET_MODE (reg) == DImode);
9679 gcc_assert (MEM_P (mem));
9681 addr = XEXP (mem, 0);
9683 switch (GET_CODE (addr))
9686 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9687 ops[0] = XEXP (addr, 0);
9692 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9693 ops[0] = XEXP (addr, 0);
9698 template = "f%s%c%%?\t%%%s0, %%1%s";
9704 sprintf (buff, template,
9708 integer_p ? "\t%@ int" : "");
9709 output_asm_insn (buff, ops);
9714 /* Output an ADD r, s, #n where n may be too big for one instruction.
9715 If adding zero to one register, output nothing. */
9717 output_add_immediate (rtx *operands)
9719 HOST_WIDE_INT n = INTVAL (operands[2]);
9721 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9724 output_multi_immediate (operands,
9725 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9728 output_multi_immediate (operands,
9729 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9736 /* Output a multiple immediate operation.
9737 OPERANDS is the vector of operands referred to in the output patterns.
9738 INSTR1 is the output pattern to use for the first constant.
9739 INSTR2 is the output pattern to use for subsequent constants.
9740 IMMED_OP is the index of the constant slot in OPERANDS.
9741 N is the constant value. */
9743 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9744 int immed_op, HOST_WIDE_INT n)
9746 #if HOST_BITS_PER_WIDE_INT > 32
9752 /* Quick and easy output. */
9753 operands[immed_op] = const0_rtx;
9754 output_asm_insn (instr1, operands);
9759 const char * instr = instr1;
9761 /* Note that n is never zero here (which would give no output). */
9762 for (i = 0; i < 32; i += 2)
9766 operands[immed_op] = GEN_INT (n & (255 << i));
9767 output_asm_insn (instr, operands);
9777 /* Return the name of a shifter operation. */
9779 arm_shift_nmem(enum rtx_code code)
9784 return ARM_LSL_NAME;
9800 /* Return the appropriate ARM instruction for the operation code.
9801 The returned result should not be overwritten. OP is the rtx of the
9802 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9805 arithmetic_instr (rtx op, int shift_first_arg)
9807 switch (GET_CODE (op))
9813 return shift_first_arg ? "rsb" : "sub";
9828 return arm_shift_nmem(GET_CODE(op));
9835 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9836 for the operation code. The returned result should not be overwritten.
9837 OP is the rtx code of the shift.
9838 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9841 shift_op (rtx op, HOST_WIDE_INT *amountp)
9844 enum rtx_code code = GET_CODE (op);
9846 switch (GET_CODE (XEXP (op, 1)))
9854 *amountp = INTVAL (XEXP (op, 1));
9864 gcc_assert (*amountp != -1);
9865 *amountp = 32 - *amountp;
9874 mnem = arm_shift_nmem(code);
9878 /* We never have to worry about the amount being other than a
9879 power of 2, since this case can never be reloaded from a reg. */
9880 gcc_assert (*amountp != -1);
9881 *amountp = int_log2 (*amountp);
9882 return ARM_LSL_NAME;
9890 /* This is not 100% correct, but follows from the desire to merge
9891 multiplication by a power of 2 with the recognizer for a
9892 shift. >=32 is not a valid shift for "lsl", so we must try and
9893 output a shift that produces the correct arithmetical result.
9894 Using lsr #32 is identical except for the fact that the carry bit
9895 is not set correctly if we set the flags; but we never use the
9896 carry bit from such an operation, so we can ignore that. */
9897 if (code == ROTATERT)
9898 /* Rotate is just modulo 32. */
9900 else if (*amountp != (*amountp & 31))
9907 /* Shifts of 0 are no-ops. */
9915 /* Obtain the shift from the POWER of two. */
9917 static HOST_WIDE_INT
9918 int_log2 (HOST_WIDE_INT power)
9920 HOST_WIDE_INT shift = 0;
9922 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9924 gcc_assert (shift <= 31);
9931 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9932 because /bin/as is horribly restrictive. The judgement about
9933 whether or not each character is 'printable' (and can be output as
9934 is) or not (and must be printed with an octal escape) must be made
9935 with reference to the *host* character set -- the situation is
9936 similar to that discussed in the comments above pp_c_char in
9937 c-pretty-print.c. */
9939 #define MAX_ASCII_LEN 51
9942 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9947 fputs ("\t.ascii\t\"", stream);
9949 for (i = 0; i < len; i++)
9953 if (len_so_far >= MAX_ASCII_LEN)
9955 fputs ("\"\n\t.ascii\t\"", stream);
9961 if (c == '\\' || c == '\"')
9963 putc ('\\', stream);
9971 fprintf (stream, "\\%03o", c);
9976 fputs ("\"\n", stream);
9979 /* Compute the register save mask for registers 0 through 12
9980 inclusive. This code is used by arm_compute_save_reg_mask. */
9982 static unsigned long
9983 arm_compute_save_reg0_reg12_mask (void)
9985 unsigned long func_type = arm_current_func_type ();
9986 unsigned long save_reg_mask = 0;
9989 if (IS_INTERRUPT (func_type))
9991 unsigned int max_reg;
9992 /* Interrupt functions must not corrupt any registers,
9993 even call clobbered ones. If this is a leaf function
9994 we can just examine the registers used by the RTL, but
9995 otherwise we have to assume that whatever function is
9996 called might clobber anything, and so we have to save
9997 all the call-clobbered registers as well. */
9998 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9999 /* FIQ handlers have registers r8 - r12 banked, so
10000 we only need to check r0 - r7, Normal ISRs only
10001 bank r14 and r15, so we must check up to r12.
10002 r13 is the stack pointer which is always preserved,
10003 so we do not need to consider it here. */
10008 for (reg = 0; reg <= max_reg; reg++)
10009 if (df_regs_ever_live_p (reg)
10010 || (! current_function_is_leaf && call_used_regs[reg]))
10011 save_reg_mask |= (1 << reg);
10013 /* Also save the pic base register if necessary. */
10015 && !TARGET_SINGLE_PIC_BASE
10016 && arm_pic_register != INVALID_REGNUM
10017 && current_function_uses_pic_offset_table)
10018 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10022 /* In arm mode we handle r11 (FP) as a special case. */
10023 unsigned last_reg = TARGET_ARM ? 10 : 11;
10025 /* In the normal case we only need to save those registers
10026 which are call saved and which are used by this function. */
10027 for (reg = 0; reg <= last_reg; reg++)
10028 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
10029 save_reg_mask |= (1 << reg);
10031 /* Handle the frame pointer as a special case. */
10032 if (! TARGET_APCS_FRAME
10033 && ! frame_pointer_needed
10034 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
10035 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
10036 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10037 else if (! TARGET_APCS_FRAME
10038 && ! frame_pointer_needed
10039 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
10040 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
10041 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10043 /* If we aren't loading the PIC register,
10044 don't stack it even though it may be live. */
10046 && !TARGET_SINGLE_PIC_BASE
10047 && arm_pic_register != INVALID_REGNUM
10048 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
10049 || current_function_uses_pic_offset_table))
10050 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10052 /* The prologue will copy SP into R0, so save it. */
10053 if (IS_STACKALIGN (func_type))
10054 save_reg_mask |= 1;
10057 /* Save registers so the exception handler can modify them. */
10058 if (current_function_calls_eh_return)
10064 reg = EH_RETURN_DATA_REGNO (i);
10065 if (reg == INVALID_REGNUM)
10067 save_reg_mask |= 1 << reg;
10071 return save_reg_mask;
10075 /* Compute a bit mask of which registers need to be
10076 saved on the stack for the current function. */
10078 static unsigned long
10079 arm_compute_save_reg_mask (void)
10081 unsigned int save_reg_mask = 0;
10082 unsigned long func_type = arm_current_func_type ();
10085 if (IS_NAKED (func_type))
10086 /* This should never really happen. */
10089 /* If we are creating a stack frame, then we must save the frame pointer,
10090 IP (which will hold the old stack pointer), LR and the PC. */
10091 if (frame_pointer_needed && TARGET_ARM)
10093 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
10096 | (1 << PC_REGNUM);
10098 /* Volatile functions do not return, so there
10099 is no need to save any other registers. */
10100 if (IS_VOLATILE (func_type))
10101 return save_reg_mask;
10103 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
10105 /* Decide if we need to save the link register.
10106 Interrupt routines have their own banked link register,
10107 so they never need to save it.
10108 Otherwise if we do not use the link register we do not need to save
10109 it. If we are pushing other registers onto the stack however, we
10110 can save an instruction in the epilogue by pushing the link register
10111 now and then popping it back into the PC. This incurs extra memory
10112 accesses though, so we only do it when optimizing for size, and only
10113 if we know that we will not need a fancy return sequence. */
10114 if (df_regs_ever_live_p (LR_REGNUM)
10117 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10118 && !current_function_calls_eh_return))
10119 save_reg_mask |= 1 << LR_REGNUM;
10121 if (cfun->machine->lr_save_eliminated)
10122 save_reg_mask &= ~ (1 << LR_REGNUM);
10124 if (TARGET_REALLY_IWMMXT
10125 && ((bit_count (save_reg_mask)
10126 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
10128 /* The total number of registers that are going to be pushed
10129 onto the stack is odd. We need to ensure that the stack
10130 is 64-bit aligned before we start to save iWMMXt registers,
10131 and also before we start to create locals. (A local variable
10132 might be a double or long long which we will load/store using
10133 an iWMMXt instruction). Therefore we need to push another
10134 ARM register, so that the stack will be 64-bit aligned. We
10135 try to avoid using the arg registers (r0 -r3) as they might be
10136 used to pass values in a tail call. */
10137 for (reg = 4; reg <= 12; reg++)
10138 if ((save_reg_mask & (1 << reg)) == 0)
10142 save_reg_mask |= (1 << reg);
10145 cfun->machine->sibcall_blocked = 1;
10146 save_reg_mask |= (1 << 3);
10150 /* We may need to push an additional register for use initializing the
10151 PIC base register. */
10152 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
10153 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
10155 reg = thumb_find_work_register (1 << 4);
10156 if (!call_used_regs[reg])
10157 save_reg_mask |= (1 << reg);
10160 return save_reg_mask;
10164 /* Compute a bit mask of which registers need to be
10165 saved on the stack for the current function. */
10166 static unsigned long
10167 thumb1_compute_save_reg_mask (void)
10169 unsigned long mask;
10173 for (reg = 0; reg < 12; reg ++)
10174 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10178 && !TARGET_SINGLE_PIC_BASE
10179 && arm_pic_register != INVALID_REGNUM
10180 && current_function_uses_pic_offset_table)
10181 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10183 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
10184 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
10185 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
10187 /* LR will also be pushed if any lo regs are pushed. */
10188 if (mask & 0xff || thumb_force_lr_save ())
10189 mask |= (1 << LR_REGNUM);
10191 /* Make sure we have a low work register if we need one.
10192 We will need one if we are going to push a high register,
10193 but we are not currently intending to push a low register. */
10194 if ((mask & 0xff) == 0
10195 && ((mask & 0x0f00) || TARGET_BACKTRACE))
10197 /* Use thumb_find_work_register to choose which register
10198 we will use. If the register is live then we will
10199 have to push it. Use LAST_LO_REGNUM as our fallback
10200 choice for the register to select. */
10201 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
10202 /* Make sure the register returned by thumb_find_work_register is
10203 not part of the return value. */
10204 if (reg * UNITS_PER_WORD <= arm_size_return_regs ())
10205 reg = LAST_LO_REGNUM;
10207 if (! call_used_regs[reg])
10215 /* Return the number of bytes required to save VFP registers. */
10217 arm_get_vfp_saved_size (void)
10219 unsigned int regno;
10224 /* Space for saved VFP registers. */
10225 if (TARGET_HARD_FLOAT && TARGET_VFP)
10228 for (regno = FIRST_VFP_REGNUM;
10229 regno < LAST_VFP_REGNUM;
10232 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
10233 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
10237 /* Workaround ARM10 VFPr1 bug. */
10238 if (count == 2 && !arm_arch6)
10240 saved += count * 8;
10249 if (count == 2 && !arm_arch6)
10251 saved += count * 8;
10258 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
10259 everything bar the final return instruction. */
10261 output_return_instruction (rtx operand, int really_return, int reverse)
10263 char conditional[10];
10266 unsigned long live_regs_mask;
10267 unsigned long func_type;
10268 arm_stack_offsets *offsets;
10270 func_type = arm_current_func_type ();
10272 if (IS_NAKED (func_type))
10275 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10277 /* If this function was declared non-returning, and we have
10278 found a tail call, then we have to trust that the called
10279 function won't return. */
10284 /* Otherwise, trap an attempted return by aborting. */
10286 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
10288 assemble_external_libcall (ops[1]);
10289 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
10295 gcc_assert (!current_function_calls_alloca || really_return);
10297 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
10299 return_used_this_function = 1;
10301 live_regs_mask = arm_compute_save_reg_mask ();
10303 if (live_regs_mask)
10305 const char * return_reg;
10307 /* If we do not have any special requirements for function exit
10308 (e.g. interworking) then we can load the return address
10309 directly into the PC. Otherwise we must load it into LR. */
10311 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
10312 return_reg = reg_names[PC_REGNUM];
10314 return_reg = reg_names[LR_REGNUM];
10316 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
10318 /* There are three possible reasons for the IP register
10319 being saved. 1) a stack frame was created, in which case
10320 IP contains the old stack pointer, or 2) an ISR routine
10321 corrupted it, or 3) it was saved to align the stack on
10322 iWMMXt. In case 1, restore IP into SP, otherwise just
10324 if (frame_pointer_needed)
10326 live_regs_mask &= ~ (1 << IP_REGNUM);
10327 live_regs_mask |= (1 << SP_REGNUM);
10330 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
10333 /* On some ARM architectures it is faster to use LDR rather than
10334 LDM to load a single register. On other architectures, the
10335 cost is the same. In 26 bit mode, or for exception handlers,
10336 we have to use LDM to load the PC so that the CPSR is also
10338 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10339 if (live_regs_mask == (1U << reg))
10342 if (reg <= LAST_ARM_REGNUM
10343 && (reg != LR_REGNUM
10345 || ! IS_INTERRUPT (func_type)))
10347 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
10348 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
10355 /* Generate the load multiple instruction to restore the
10356 registers. Note we can get here, even if
10357 frame_pointer_needed is true, but only if sp already
10358 points to the base of the saved core registers. */
10359 if (live_regs_mask & (1 << SP_REGNUM))
10361 unsigned HOST_WIDE_INT stack_adjust;
10363 offsets = arm_get_frame_offsets ();
10364 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
10365 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
10367 if (stack_adjust && arm_arch5 && TARGET_ARM)
10368 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
10371 /* If we can't use ldmib (SA110 bug),
10372 then try to pop r3 instead. */
10374 live_regs_mask |= 1 << 3;
10375 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
10379 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
10381 p = instr + strlen (instr);
10383 for (reg = 0; reg <= SP_REGNUM; reg++)
10384 if (live_regs_mask & (1 << reg))
10386 int l = strlen (reg_names[reg]);
10392 memcpy (p, ", ", 2);
10396 memcpy (p, "%|", 2);
10397 memcpy (p + 2, reg_names[reg], l);
10401 if (live_regs_mask & (1 << LR_REGNUM))
10403 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
10404 /* If returning from an interrupt, restore the CPSR. */
10405 if (IS_INTERRUPT (func_type))
10412 output_asm_insn (instr, & operand);
10414 /* See if we need to generate an extra instruction to
10415 perform the actual function return. */
10417 && func_type != ARM_FT_INTERWORKED
10418 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
10420 /* The return has already been handled
10421 by loading the LR into the PC. */
10428 switch ((int) ARM_FUNC_TYPE (func_type))
10432 /* ??? This is wrong for unified assembly syntax. */
10433 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
10436 case ARM_FT_INTERWORKED:
10437 sprintf (instr, "bx%s\t%%|lr", conditional);
10440 case ARM_FT_EXCEPTION:
10441 /* ??? This is wrong for unified assembly syntax. */
10442 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
10446 /* Use bx if it's available. */
10447 if (arm_arch5 || arm_arch4t)
10448 sprintf (instr, "bx%s\t%%|lr", conditional);
10450 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
10454 output_asm_insn (instr, & operand);
10460 /* Write the function name into the code section, directly preceding
10461 the function prologue.
10463 Code will be output similar to this:
10465 .ascii "arm_poke_function_name", 0
10468 .word 0xff000000 + (t1 - t0)
10469 arm_poke_function_name
10471 stmfd sp!, {fp, ip, lr, pc}
10474 When performing a stack backtrace, code can inspect the value
10475 of 'pc' stored at 'fp' + 0. If the trace function then looks
10476 at location pc - 12 and the top 8 bits are set, then we know
10477 that there is a function name embedded immediately preceding this
10478 location and has length ((pc[-3]) & 0xff000000).
10480 We assume that pc is declared as a pointer to an unsigned long.
10482 It is of no benefit to output the function name if we are assembling
10483 a leaf function. These function types will not contain a stack
10484 backtrace structure, therefore it is not possible to determine the
10487 arm_poke_function_name (FILE *stream, const char *name)
10489 unsigned long alignlength;
10490 unsigned long length;
10493 length = strlen (name) + 1;
10494 alignlength = ROUND_UP_WORD (length);
10496 ASM_OUTPUT_ASCII (stream, name, length);
10497 ASM_OUTPUT_ALIGN (stream, 2);
10498 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
10499 assemble_aligned_integer (UNITS_PER_WORD, x);
10502 /* Place some comments into the assembler stream
10503 describing the current function. */
10505 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
10507 unsigned long func_type;
10511 thumb1_output_function_prologue (f, frame_size);
10515 /* Sanity check. */
10516 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
10518 func_type = arm_current_func_type ();
10520 switch ((int) ARM_FUNC_TYPE (func_type))
10523 case ARM_FT_NORMAL:
10525 case ARM_FT_INTERWORKED:
10526 asm_fprintf (f, "\t%@ Function supports interworking.\n");
10529 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
10532 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
10534 case ARM_FT_EXCEPTION:
10535 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
10539 if (IS_NAKED (func_type))
10540 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10542 if (IS_VOLATILE (func_type))
10543 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
10545 if (IS_NESTED (func_type))
10546 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
10547 if (IS_STACKALIGN (func_type))
10548 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10550 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10551 current_function_args_size,
10552 current_function_pretend_args_size, frame_size);
10554 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10555 frame_pointer_needed,
10556 cfun->machine->uses_anonymous_args);
10558 if (cfun->machine->lr_save_eliminated)
10559 asm_fprintf (f, "\t%@ link register save eliminated.\n");
10561 if (current_function_calls_eh_return)
10562 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
10564 #ifdef AOF_ASSEMBLER
10566 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
10569 return_used_this_function = 0;
10573 arm_output_epilogue (rtx sibling)
10576 unsigned long saved_regs_mask;
10577 unsigned long func_type;
10578 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10579 frame that is $fp + 4 for a non-variadic function. */
10580 int floats_offset = 0;
10582 FILE * f = asm_out_file;
10583 unsigned int lrm_count = 0;
10584 int really_return = (sibling == NULL);
10586 arm_stack_offsets *offsets;
10588 /* If we have already generated the return instruction
10589 then it is futile to generate anything else. */
10590 if (use_return_insn (FALSE, sibling) && return_used_this_function)
10593 func_type = arm_current_func_type ();
10595 if (IS_NAKED (func_type))
10596 /* Naked functions don't have epilogues. */
10599 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10603 /* A volatile function should never return. Call abort. */
10604 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
10605 assemble_external_libcall (op);
10606 output_asm_insn ("bl\t%a0", &op);
10611 /* If we are throwing an exception, then we really must be doing a
10612 return, so we can't tail-call. */
10613 gcc_assert (!current_function_calls_eh_return || really_return);
10615 offsets = arm_get_frame_offsets ();
10616 saved_regs_mask = arm_compute_save_reg_mask ();
10619 lrm_count = bit_count (saved_regs_mask);
10621 floats_offset = offsets->saved_args;
10622 /* Compute how far away the floats will be. */
10623 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10624 if (saved_regs_mask & (1 << reg))
10625 floats_offset += 4;
10627 if (frame_pointer_needed && TARGET_ARM)
10629 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10630 int vfp_offset = offsets->frame;
10632 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10634 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10635 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10637 floats_offset += 12;
10638 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
10639 reg, FP_REGNUM, floats_offset - vfp_offset);
10644 start_reg = LAST_FPA_REGNUM;
10646 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10648 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10650 floats_offset += 12;
10652 /* We can't unstack more than four registers at once. */
10653 if (start_reg - reg == 3)
10655 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
10656 reg, FP_REGNUM, floats_offset - vfp_offset);
10657 start_reg = reg - 1;
10662 if (reg != start_reg)
10663 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10664 reg + 1, start_reg - reg,
10665 FP_REGNUM, floats_offset - vfp_offset);
10666 start_reg = reg - 1;
10670 /* Just in case the last register checked also needs unstacking. */
10671 if (reg != start_reg)
10672 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10673 reg + 1, start_reg - reg,
10674 FP_REGNUM, floats_offset - vfp_offset);
10677 if (TARGET_HARD_FLOAT && TARGET_VFP)
10681 /* The fldmd insns do not have base+offset addressing
10682 modes, so we use IP to hold the address. */
10683 saved_size = arm_get_vfp_saved_size ();
10685 if (saved_size > 0)
10687 floats_offset += saved_size;
10688 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
10689 FP_REGNUM, floats_offset - vfp_offset);
10691 start_reg = FIRST_VFP_REGNUM;
10692 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10694 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
10695 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
10697 if (start_reg != reg)
10698 vfp_output_fldmd (f, IP_REGNUM,
10699 (start_reg - FIRST_VFP_REGNUM) / 2,
10700 (reg - start_reg) / 2);
10701 start_reg = reg + 2;
10704 if (start_reg != reg)
10705 vfp_output_fldmd (f, IP_REGNUM,
10706 (start_reg - FIRST_VFP_REGNUM) / 2,
10707 (reg - start_reg) / 2);
10712 /* The frame pointer is guaranteed to be non-double-word aligned.
10713 This is because it is set to (old_stack_pointer - 4) and the
10714 old_stack_pointer was double word aligned. Thus the offset to
10715 the iWMMXt registers to be loaded must also be non-double-word
10716 sized, so that the resultant address *is* double-word aligned.
10717 We can ignore floats_offset since that was already included in
10718 the live_regs_mask. */
10719 lrm_count += (lrm_count % 2 ? 2 : 1);
10721 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10722 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10724 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
10725 reg, FP_REGNUM, lrm_count * 4);
10730 /* saved_regs_mask should contain the IP, which at the time of stack
10731 frame generation actually contains the old stack pointer. So a
10732 quick way to unwind the stack is just pop the IP register directly
10733 into the stack pointer. */
10734 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
10735 saved_regs_mask &= ~ (1 << IP_REGNUM);
10736 saved_regs_mask |= (1 << SP_REGNUM);
10738 /* There are two registers left in saved_regs_mask - LR and PC. We
10739 only need to restore the LR register (the return address), but to
10740 save time we can load it directly into the PC, unless we need a
10741 special function exit sequence, or we are not really returning. */
10743 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10744 && !current_function_calls_eh_return)
10745 /* Delete the LR from the register mask, so that the LR on
10746 the stack is loaded into the PC in the register mask. */
10747 saved_regs_mask &= ~ (1 << LR_REGNUM);
10749 saved_regs_mask &= ~ (1 << PC_REGNUM);
10751 /* We must use SP as the base register, because SP is one of the
10752 registers being restored. If an interrupt or page fault
10753 happens in the ldm instruction, the SP might or might not
10754 have been restored. That would be bad, as then SP will no
10755 longer indicate the safe area of stack, and we can get stack
10756 corruption. Using SP as the base register means that it will
10757 be reset correctly to the original value, should an interrupt
10758 occur. If the stack pointer already points at the right
10759 place, then omit the subtraction. */
10760 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10761 || current_function_calls_alloca)
10762 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10763 4 * bit_count (saved_regs_mask));
10764 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
10766 if (IS_INTERRUPT (func_type))
10767 /* Interrupt handlers will have pushed the
10768 IP onto the stack, so restore it now. */
10769 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
10773 HOST_WIDE_INT amount;
10775 /* Restore stack pointer if necessary. */
10776 if (frame_pointer_needed)
10778 /* For Thumb-2 restore sp from the frame pointer.
10779 Operand restrictions mean we have to increment FP, then copy
10781 amount = offsets->locals_base - offsets->saved_regs;
10782 operands[0] = hard_frame_pointer_rtx;
10786 operands[0] = stack_pointer_rtx;
10787 amount = offsets->outgoing_args - offsets->saved_regs;
10792 operands[1] = operands[0];
10793 operands[2] = GEN_INT (amount);
10794 output_add_immediate (operands);
10796 if (frame_pointer_needed)
10797 asm_fprintf (f, "\tmov\t%r, %r\n",
10798 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
10800 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10802 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10803 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10804 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10809 start_reg = FIRST_FPA_REGNUM;
10811 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10813 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10815 if (reg - start_reg == 3)
10817 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10818 start_reg, SP_REGNUM);
10819 start_reg = reg + 1;
10824 if (reg != start_reg)
10825 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10826 start_reg, reg - start_reg,
10829 start_reg = reg + 1;
10833 /* Just in case the last register checked also needs unstacking. */
10834 if (reg != start_reg)
10835 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10836 start_reg, reg - start_reg, SP_REGNUM);
10839 if (TARGET_HARD_FLOAT && TARGET_VFP)
10841 start_reg = FIRST_VFP_REGNUM;
10842 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10844 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
10845 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
10847 if (start_reg != reg)
10848 vfp_output_fldmd (f, SP_REGNUM,
10849 (start_reg - FIRST_VFP_REGNUM) / 2,
10850 (reg - start_reg) / 2);
10851 start_reg = reg + 2;
10854 if (start_reg != reg)
10855 vfp_output_fldmd (f, SP_REGNUM,
10856 (start_reg - FIRST_VFP_REGNUM) / 2,
10857 (reg - start_reg) / 2);
10860 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10861 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10862 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10864 /* If we can, restore the LR into the PC. */
10865 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
10866 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
10867 && !IS_STACKALIGN (func_type)
10869 && current_function_pretend_args_size == 0
10870 && saved_regs_mask & (1 << LR_REGNUM)
10871 && !current_function_calls_eh_return)
10873 saved_regs_mask &= ~ (1 << LR_REGNUM);
10874 saved_regs_mask |= (1 << PC_REGNUM);
10875 rfe = IS_INTERRUPT (func_type);
10880 /* Load the registers off the stack. If we only have one register
10881 to load use the LDR instruction - it is faster. For Thumb-2
10882 always use pop and the assembler will pick the best instruction.*/
10883 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
10884 && !IS_INTERRUPT(func_type))
10886 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10888 else if (saved_regs_mask)
10890 if (saved_regs_mask & (1 << SP_REGNUM))
10891 /* Note - write back to the stack register is not enabled
10892 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10893 in the list of registers and if we add writeback the
10894 instruction becomes UNPREDICTABLE. */
10895 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
10897 else if (TARGET_ARM)
10898 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
10901 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
10904 if (current_function_pretend_args_size)
10906 /* Unwind the pre-pushed regs. */
10907 operands[0] = operands[1] = stack_pointer_rtx;
10908 operands[2] = GEN_INT (current_function_pretend_args_size);
10909 output_add_immediate (operands);
10913 /* We may have already restored PC directly from the stack. */
10914 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10917 /* Stack adjustment for exception handler. */
10918 if (current_function_calls_eh_return)
10919 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10920 ARM_EH_STACKADJ_REGNUM);
10922 /* Generate the return instruction. */
10923 switch ((int) ARM_FUNC_TYPE (func_type))
10927 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10930 case ARM_FT_EXCEPTION:
10931 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10934 case ARM_FT_INTERWORKED:
10935 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10939 if (IS_STACKALIGN (func_type))
10941 /* See comment in arm_expand_prologue. */
10942 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
10944 if (arm_arch5 || arm_arch4t)
10945 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10947 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10955 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10956 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10958 arm_stack_offsets *offsets;
10964 /* Emit any call-via-reg trampolines that are needed for v4t support
10965 of call_reg and call_value_reg type insns. */
10966 for (regno = 0; regno < LR_REGNUM; regno++)
10968 rtx label = cfun->machine->call_via[regno];
10972 switch_to_section (function_section (current_function_decl));
10973 targetm.asm_out.internal_label (asm_out_file, "L",
10974 CODE_LABEL_NUMBER (label));
10975 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10979 /* ??? Probably not safe to set this here, since it assumes that a
10980 function will be emitted as assembly immediately after we generate
10981 RTL for it. This does not happen for inline functions. */
10982 return_used_this_function = 0;
10984 else /* TARGET_32BIT */
10986 /* We need to take into account any stack-frame rounding. */
10987 offsets = arm_get_frame_offsets ();
10989 gcc_assert (!use_return_insn (FALSE, NULL)
10990 || !return_used_this_function
10991 || offsets->saved_regs == offsets->outgoing_args
10992 || frame_pointer_needed);
10994 /* Reset the ARM-specific per-function variables. */
10995 after_arm_reorg = 0;
10999 /* Generate and emit an insn that we will recognize as a push_multi.
11000 Unfortunately, since this insn does not reflect very well the actual
11001 semantics of the operation, we need to annotate the insn for the benefit
11002 of DWARF2 frame unwind information. */
11004 emit_multi_reg_push (unsigned long mask)
11007 int num_dwarf_regs;
11011 int dwarf_par_index;
11014 for (i = 0; i <= LAST_ARM_REGNUM; i++)
11015 if (mask & (1 << i))
11018 gcc_assert (num_regs && num_regs <= 16);
11020 /* We don't record the PC in the dwarf frame information. */
11021 num_dwarf_regs = num_regs;
11022 if (mask & (1 << PC_REGNUM))
11025 /* For the body of the insn we are going to generate an UNSPEC in
11026 parallel with several USEs. This allows the insn to be recognized
11027 by the push_multi pattern in the arm.md file. The insn looks
11028 something like this:
11031 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
11032 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
11033 (use (reg:SI 11 fp))
11034 (use (reg:SI 12 ip))
11035 (use (reg:SI 14 lr))
11036 (use (reg:SI 15 pc))
11039 For the frame note however, we try to be more explicit and actually
11040 show each register being stored into the stack frame, plus a (single)
11041 decrement of the stack pointer. We do it this way in order to be
11042 friendly to the stack unwinding code, which only wants to see a single
11043 stack decrement per instruction. The RTL we generate for the note looks
11044 something like this:
11047 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
11048 (set (mem:SI (reg:SI sp)) (reg:SI r4))
11049 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
11050 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
11051 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
11054 This sequence is used both by the code to support stack unwinding for
11055 exceptions handlers and the code to generate dwarf2 frame debugging. */
11057 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
11058 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
11059 dwarf_par_index = 1;
11061 for (i = 0; i <= LAST_ARM_REGNUM; i++)
11063 if (mask & (1 << i))
11065 reg = gen_rtx_REG (SImode, i);
11067 XVECEXP (par, 0, 0)
11068 = gen_rtx_SET (VOIDmode,
11069 gen_frame_mem (BLKmode,
11070 gen_rtx_PRE_DEC (BLKmode,
11071 stack_pointer_rtx)),
11072 gen_rtx_UNSPEC (BLKmode,
11073 gen_rtvec (1, reg),
11074 UNSPEC_PUSH_MULT));
11076 if (i != PC_REGNUM)
11078 tmp = gen_rtx_SET (VOIDmode,
11079 gen_frame_mem (SImode, stack_pointer_rtx),
11081 RTX_FRAME_RELATED_P (tmp) = 1;
11082 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
11090 for (j = 1, i++; j < num_regs; i++)
11092 if (mask & (1 << i))
11094 reg = gen_rtx_REG (SImode, i);
11096 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
11098 if (i != PC_REGNUM)
11101 = gen_rtx_SET (VOIDmode,
11102 gen_frame_mem (SImode,
11103 plus_constant (stack_pointer_rtx,
11106 RTX_FRAME_RELATED_P (tmp) = 1;
11107 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
11114 par = emit_insn (par);
11116 tmp = gen_rtx_SET (VOIDmode,
11118 plus_constant (stack_pointer_rtx, -4 * num_regs));
11119 RTX_FRAME_RELATED_P (tmp) = 1;
11120 XVECEXP (dwarf, 0, 0) = tmp;
11122 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11127 /* Calculate the size of the return value that is passed in registers. */
11129 arm_size_return_regs (void)
11131 enum machine_mode mode;
11133 if (current_function_return_rtx != 0)
11134 mode = GET_MODE (current_function_return_rtx);
11136 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11138 return GET_MODE_SIZE (mode);
11142 emit_sfm (int base_reg, int count)
11149 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
11150 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
11152 reg = gen_rtx_REG (XFmode, base_reg++);
11154 XVECEXP (par, 0, 0)
11155 = gen_rtx_SET (VOIDmode,
11156 gen_frame_mem (BLKmode,
11157 gen_rtx_PRE_DEC (BLKmode,
11158 stack_pointer_rtx)),
11159 gen_rtx_UNSPEC (BLKmode,
11160 gen_rtvec (1, reg),
11161 UNSPEC_PUSH_MULT));
11162 tmp = gen_rtx_SET (VOIDmode,
11163 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
11164 RTX_FRAME_RELATED_P (tmp) = 1;
11165 XVECEXP (dwarf, 0, 1) = tmp;
11167 for (i = 1; i < count; i++)
11169 reg = gen_rtx_REG (XFmode, base_reg++);
11170 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
11172 tmp = gen_rtx_SET (VOIDmode,
11173 gen_frame_mem (XFmode,
11174 plus_constant (stack_pointer_rtx,
11177 RTX_FRAME_RELATED_P (tmp) = 1;
11178 XVECEXP (dwarf, 0, i + 1) = tmp;
11181 tmp = gen_rtx_SET (VOIDmode,
11183 plus_constant (stack_pointer_rtx, -12 * count));
11185 RTX_FRAME_RELATED_P (tmp) = 1;
11186 XVECEXP (dwarf, 0, 0) = tmp;
11188 par = emit_insn (par);
11189 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11195 /* Return true if the current function needs to save/restore LR. */
11198 thumb_force_lr_save (void)
11200 return !cfun->machine->lr_save_eliminated
11201 && (!leaf_function_p ()
11202 || thumb_far_jump_used_p ()
11203 || df_regs_ever_live_p (LR_REGNUM));
11207 /* Compute the distance from register FROM to register TO.
11208 These can be the arg pointer (26), the soft frame pointer (25),
11209 the stack pointer (13) or the hard frame pointer (11).
11210 In thumb mode r7 is used as the soft frame pointer, if needed.
11211 Typical stack layout looks like this:
11213 old stack pointer -> | |
11216 | | saved arguments for
11217 | | vararg functions
11220 hard FP & arg pointer -> | | \
11228 soft frame pointer -> | | /
11233 locals base pointer -> | | /
11238 current stack pointer -> | | /
11241 For a given function some or all of these stack components
11242 may not be needed, giving rise to the possibility of
11243 eliminating some of the registers.
11245 The values returned by this function must reflect the behavior
11246 of arm_expand_prologue() and arm_compute_save_reg_mask().
11248 The sign of the number returned reflects the direction of stack
11249 growth, so the values are positive for all eliminations except
11250 from the soft frame pointer to the hard frame pointer.
11252 SFP may point just inside the local variables block to ensure correct
11256 /* Calculate stack offsets. These are used to calculate register elimination
11257 offsets and in prologue/epilogue code. */
11259 static arm_stack_offsets *
11260 arm_get_frame_offsets (void)
11262 struct arm_stack_offsets *offsets;
11263 unsigned long func_type;
11266 HOST_WIDE_INT frame_size;
11268 offsets = &cfun->machine->stack_offsets;
11270 /* We need to know if we are a leaf function. Unfortunately, it
11271 is possible to be called after start_sequence has been called,
11272 which causes get_insns to return the insns for the sequence,
11273 not the function, which will cause leaf_function_p to return
11274 the incorrect result.
11276 to know about leaf functions once reload has completed, and the
11277 frame size cannot be changed after that time, so we can safely
11278 use the cached value. */
11280 if (reload_completed)
11283 /* Initially this is the size of the local variables. It will translated
11284 into an offset once we have determined the size of preceding data. */
11285 frame_size = ROUND_UP_WORD (get_frame_size ());
11287 leaf = leaf_function_p ();
11289 /* Space for variadic functions. */
11290 offsets->saved_args = current_function_pretend_args_size;
11292 /* In Thumb mode this is incorrect, but never used. */
11293 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
11297 unsigned int regno;
11299 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
11301 /* We know that SP will be doubleword aligned on entry, and we must
11302 preserve that condition at any subroutine call. We also require the
11303 soft frame pointer to be doubleword aligned. */
11305 if (TARGET_REALLY_IWMMXT)
11307 /* Check for the call-saved iWMMXt registers. */
11308 for (regno = FIRST_IWMMXT_REGNUM;
11309 regno <= LAST_IWMMXT_REGNUM;
11311 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
11315 func_type = arm_current_func_type ();
11316 if (! IS_VOLATILE (func_type))
11318 /* Space for saved FPA registers. */
11319 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
11320 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
11323 /* Space for saved VFP registers. */
11324 if (TARGET_HARD_FLOAT && TARGET_VFP)
11325 saved += arm_get_vfp_saved_size ();
11328 else /* TARGET_THUMB1 */
11330 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
11331 if (TARGET_BACKTRACE)
11335 /* Saved registers include the stack frame. */
11336 offsets->saved_regs = offsets->saved_args + saved;
11337 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
11338 /* A leaf function does not need any stack alignment if it has nothing
11340 if (leaf && frame_size == 0)
11342 offsets->outgoing_args = offsets->soft_frame;
11343 offsets->locals_base = offsets->soft_frame;
11347 /* Ensure SFP has the correct alignment. */
11348 if (ARM_DOUBLEWORD_ALIGN
11349 && (offsets->soft_frame & 7))
11350 offsets->soft_frame += 4;
11352 offsets->locals_base = offsets->soft_frame + frame_size;
11353 offsets->outgoing_args = (offsets->locals_base
11354 + current_function_outgoing_args_size);
11356 if (ARM_DOUBLEWORD_ALIGN)
11358 /* Ensure SP remains doubleword aligned. */
11359 if (offsets->outgoing_args & 7)
11360 offsets->outgoing_args += 4;
11361 gcc_assert (!(offsets->outgoing_args & 7));
11368 /* Calculate the relative offsets for the different stack pointers. Positive
11369 offsets are in the direction of stack growth. */
11372 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
11374 arm_stack_offsets *offsets;
11376 offsets = arm_get_frame_offsets ();
11378 /* OK, now we have enough information to compute the distances.
11379 There must be an entry in these switch tables for each pair
11380 of registers in ELIMINABLE_REGS, even if some of the entries
11381 seem to be redundant or useless. */
11384 case ARG_POINTER_REGNUM:
11387 case THUMB_HARD_FRAME_POINTER_REGNUM:
11390 case FRAME_POINTER_REGNUM:
11391 /* This is the reverse of the soft frame pointer
11392 to hard frame pointer elimination below. */
11393 return offsets->soft_frame - offsets->saved_args;
11395 case ARM_HARD_FRAME_POINTER_REGNUM:
11396 /* If there is no stack frame then the hard
11397 frame pointer and the arg pointer coincide. */
11398 if (offsets->frame == offsets->saved_regs)
11400 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11401 return (frame_pointer_needed
11402 && cfun->static_chain_decl != NULL
11403 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
11405 case STACK_POINTER_REGNUM:
11406 /* If nothing has been pushed on the stack at all
11407 then this will return -4. This *is* correct! */
11408 return offsets->outgoing_args - (offsets->saved_args + 4);
11411 gcc_unreachable ();
11413 gcc_unreachable ();
11415 case FRAME_POINTER_REGNUM:
11418 case THUMB_HARD_FRAME_POINTER_REGNUM:
11421 case ARM_HARD_FRAME_POINTER_REGNUM:
11422 /* The hard frame pointer points to the top entry in the
11423 stack frame. The soft frame pointer to the bottom entry
11424 in the stack frame. If there is no stack frame at all,
11425 then they are identical. */
11427 return offsets->frame - offsets->soft_frame;
11429 case STACK_POINTER_REGNUM:
11430 return offsets->outgoing_args - offsets->soft_frame;
11433 gcc_unreachable ();
11435 gcc_unreachable ();
11438 /* You cannot eliminate from the stack pointer.
11439 In theory you could eliminate from the hard frame
11440 pointer to the stack pointer, but this will never
11441 happen, since if a stack frame is not needed the
11442 hard frame pointer will never be used. */
11443 gcc_unreachable ();
11448 /* Emit RTL to save coprocessor registers on function entry. Returns the
11449 number of bytes pushed. */
11452 arm_save_coproc_regs(void)
11454 int saved_size = 0;
11456 unsigned start_reg;
11459 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
11460 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
11462 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
11463 insn = gen_rtx_MEM (V2SImode, insn);
11464 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
11465 RTX_FRAME_RELATED_P (insn) = 1;
11469 /* Save any floating point call-saved registers used by this
11471 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
11473 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11474 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
11476 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
11477 insn = gen_rtx_MEM (XFmode, insn);
11478 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
11479 RTX_FRAME_RELATED_P (insn) = 1;
11485 start_reg = LAST_FPA_REGNUM;
11487 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11489 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
11491 if (start_reg - reg == 3)
11493 insn = emit_sfm (reg, 4);
11494 RTX_FRAME_RELATED_P (insn) = 1;
11496 start_reg = reg - 1;
11501 if (start_reg != reg)
11503 insn = emit_sfm (reg + 1, start_reg - reg);
11504 RTX_FRAME_RELATED_P (insn) = 1;
11505 saved_size += (start_reg - reg) * 12;
11507 start_reg = reg - 1;
11511 if (start_reg != reg)
11513 insn = emit_sfm (reg + 1, start_reg - reg);
11514 saved_size += (start_reg - reg) * 12;
11515 RTX_FRAME_RELATED_P (insn) = 1;
11518 if (TARGET_HARD_FLOAT && TARGET_VFP)
11520 start_reg = FIRST_VFP_REGNUM;
11522 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11524 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11525 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
11527 if (start_reg != reg)
11528 saved_size += vfp_emit_fstmd (start_reg,
11529 (reg - start_reg) / 2);
11530 start_reg = reg + 2;
11533 if (start_reg != reg)
11534 saved_size += vfp_emit_fstmd (start_reg,
11535 (reg - start_reg) / 2);
11541 /* Set the Thumb frame pointer from the stack pointer. */
11544 thumb_set_frame_pointer (arm_stack_offsets *offsets)
11546 HOST_WIDE_INT amount;
11549 amount = offsets->outgoing_args - offsets->locals_base;
11551 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11552 stack_pointer_rtx, GEN_INT (amount)));
11555 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
11556 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11557 hard_frame_pointer_rtx,
11558 stack_pointer_rtx));
11559 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11560 plus_constant (stack_pointer_rtx, amount));
11561 RTX_FRAME_RELATED_P (dwarf) = 1;
11562 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11566 RTX_FRAME_RELATED_P (insn) = 1;
11569 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11572 arm_expand_prologue (void)
11577 unsigned long live_regs_mask;
11578 unsigned long func_type;
11580 int saved_pretend_args = 0;
11581 int saved_regs = 0;
11582 unsigned HOST_WIDE_INT args_to_push;
11583 arm_stack_offsets *offsets;
11585 func_type = arm_current_func_type ();
11587 /* Naked functions don't have prologues. */
11588 if (IS_NAKED (func_type))
11591 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11592 args_to_push = current_function_pretend_args_size;
11594 /* Compute which register we will have to save onto the stack. */
11595 live_regs_mask = arm_compute_save_reg_mask ();
11597 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
11599 if (IS_STACKALIGN (func_type))
11604 /* Handle a word-aligned stack pointer. We generate the following:
11609 <save and restore r0 in normal prologue/epilogue>
11613 The unwinder doesn't need to know about the stack realignment.
11614 Just tell it we saved SP in r0. */
11615 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
11617 r0 = gen_rtx_REG (SImode, 0);
11618 r1 = gen_rtx_REG (SImode, 1);
11619 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
11620 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
11621 insn = gen_movsi (r0, stack_pointer_rtx);
11622 RTX_FRAME_RELATED_P (insn) = 1;
11623 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11624 dwarf, REG_NOTES (insn));
11626 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
11627 emit_insn (gen_movsi (stack_pointer_rtx, r1));
11630 if (frame_pointer_needed && TARGET_ARM)
11632 if (IS_INTERRUPT (func_type))
11634 /* Interrupt functions must not corrupt any registers.
11635 Creating a frame pointer however, corrupts the IP
11636 register, so we must push it first. */
11637 insn = emit_multi_reg_push (1 << IP_REGNUM);
11639 /* Do not set RTX_FRAME_RELATED_P on this insn.
11640 The dwarf stack unwinding code only wants to see one
11641 stack decrement per function, and this is not it. If
11642 this instruction is labeled as being part of the frame
11643 creation sequence then dwarf2out_frame_debug_expr will
11644 die when it encounters the assignment of IP to FP
11645 later on, since the use of SP here establishes SP as
11646 the CFA register and not IP.
11648 Anyway this instruction is not really part of the stack
11649 frame creation although it is part of the prologue. */
11651 else if (IS_NESTED (func_type))
11653 /* The Static chain register is the same as the IP register
11654 used as a scratch register during stack frame creation.
11655 To get around this need to find somewhere to store IP
11656 whilst the frame is being created. We try the following
11659 1. The last argument register.
11660 2. A slot on the stack above the frame. (This only
11661 works if the function is not a varargs function).
11662 3. Register r3, after pushing the argument registers
11665 Note - we only need to tell the dwarf2 backend about the SP
11666 adjustment in the second variant; the static chain register
11667 doesn't need to be unwound, as it doesn't contain a value
11668 inherited from the caller. */
11670 if (df_regs_ever_live_p (3) == false)
11671 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11672 else if (args_to_push == 0)
11676 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
11677 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
11680 /* Just tell the dwarf backend that we adjusted SP. */
11681 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11682 plus_constant (stack_pointer_rtx,
11684 RTX_FRAME_RELATED_P (insn) = 1;
11685 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11686 dwarf, REG_NOTES (insn));
11690 /* Store the args on the stack. */
11691 if (cfun->machine->uses_anonymous_args)
11692 insn = emit_multi_reg_push
11693 ((0xf0 >> (args_to_push / 4)) & 0xf);
11696 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11697 GEN_INT (- args_to_push)));
11699 RTX_FRAME_RELATED_P (insn) = 1;
11701 saved_pretend_args = 1;
11702 fp_offset = args_to_push;
11705 /* Now reuse r3 to preserve IP. */
11706 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11710 insn = emit_set_insn (ip_rtx,
11711 plus_constant (stack_pointer_rtx, fp_offset));
11712 RTX_FRAME_RELATED_P (insn) = 1;
11717 /* Push the argument registers, or reserve space for them. */
11718 if (cfun->machine->uses_anonymous_args)
11719 insn = emit_multi_reg_push
11720 ((0xf0 >> (args_to_push / 4)) & 0xf);
11723 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11724 GEN_INT (- args_to_push)));
11725 RTX_FRAME_RELATED_P (insn) = 1;
11728 /* If this is an interrupt service routine, and the link register
11729 is going to be pushed, and we are not creating a stack frame,
11730 (which would involve an extra push of IP and a pop in the epilogue)
11731 subtracting four from LR now will mean that the function return
11732 can be done with a single instruction. */
11733 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
11734 && (live_regs_mask & (1 << LR_REGNUM)) != 0
11735 && ! frame_pointer_needed
11738 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
11740 emit_set_insn (lr, plus_constant (lr, -4));
11743 if (live_regs_mask)
11745 insn = emit_multi_reg_push (live_regs_mask);
11746 saved_regs += bit_count (live_regs_mask) * 4;
11747 RTX_FRAME_RELATED_P (insn) = 1;
11750 if (! IS_VOLATILE (func_type))
11751 saved_regs += arm_save_coproc_regs ();
11753 if (frame_pointer_needed && TARGET_ARM)
11755 /* Create the new frame pointer. */
11757 insn = GEN_INT (-(4 + args_to_push + fp_offset));
11758 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
11759 RTX_FRAME_RELATED_P (insn) = 1;
11761 if (IS_NESTED (func_type))
11763 /* Recover the static chain register. */
11764 if (!df_regs_ever_live_p (3)
11765 || saved_pretend_args)
11766 insn = gen_rtx_REG (SImode, 3);
11767 else /* if (current_function_pretend_args_size == 0) */
11769 insn = plus_constant (hard_frame_pointer_rtx, 4);
11770 insn = gen_frame_mem (SImode, insn);
11772 emit_set_insn (ip_rtx, insn);
11773 /* Add a USE to stop propagate_one_insn() from barfing. */
11774 emit_insn (gen_prologue_use (ip_rtx));
11779 offsets = arm_get_frame_offsets ();
11780 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
11782 /* This add can produce multiple insns for a large constant, so we
11783 need to get tricky. */
11784 rtx last = get_last_insn ();
11786 amount = GEN_INT (offsets->saved_args + saved_regs
11787 - offsets->outgoing_args);
11789 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11793 last = last ? NEXT_INSN (last) : get_insns ();
11794 RTX_FRAME_RELATED_P (last) = 1;
11796 while (last != insn);
11798 /* If the frame pointer is needed, emit a special barrier that
11799 will prevent the scheduler from moving stores to the frame
11800 before the stack adjustment. */
11801 if (frame_pointer_needed)
11802 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
11803 hard_frame_pointer_rtx));
11807 if (frame_pointer_needed && TARGET_THUMB2)
11808 thumb_set_frame_pointer (offsets);
11810 if (flag_pic && arm_pic_register != INVALID_REGNUM)
11812 unsigned long mask;
11814 mask = live_regs_mask;
11815 mask &= THUMB2_WORK_REGS;
11816 if (!IS_NESTED (func_type))
11817 mask |= (1 << IP_REGNUM);
11818 arm_load_pic_register (mask);
11821 /* If we are profiling, make sure no instructions are scheduled before
11822 the call to mcount. Similarly if the user has requested no
11823 scheduling in the prolog. Similarly if we want non-call exceptions
11824 using the EABI unwinder, to prevent faulting instructions from being
11825 swapped with a stack adjustment. */
11826 if (current_function_profile || !TARGET_SCHED_PROLOG
11827 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
11828 emit_insn (gen_blockage ());
11830 /* If the link register is being kept alive, with the return address in it,
11831 then make sure that it does not get reused by the ce2 pass. */
11832 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
11833 cfun->machine->lr_save_eliminated = 1;
11836 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11838 arm_print_condition (FILE *stream)
11840 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11842 /* Branch conversion is not implemented for Thumb-2. */
11845 output_operand_lossage ("predicated Thumb instruction");
11848 if (current_insn_predicate != NULL)
11850 output_operand_lossage
11851 ("predicated instruction in conditional sequence");
11855 fputs (arm_condition_codes[arm_current_cc], stream);
11857 else if (current_insn_predicate)
11859 enum arm_cond_code code;
11863 output_operand_lossage ("predicated Thumb instruction");
11867 code = get_arm_condition_code (current_insn_predicate);
11868 fputs (arm_condition_codes[code], stream);
11873 /* If CODE is 'd', then the X is a condition operand and the instruction
11874 should only be executed if the condition is true.
11875 if CODE is 'D', then the X is a condition operand and the instruction
11876 should only be executed if the condition is false: however, if the mode
11877 of the comparison is CCFPEmode, then always execute the instruction -- we
11878 do this because in these circumstances !GE does not necessarily imply LT;
11879 in these cases the instruction pattern will take care to make sure that
11880 an instruction containing %d will follow, thereby undoing the effects of
11881 doing this instruction unconditionally.
11882 If CODE is 'N' then X is a floating point operand that must be negated
11884 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11885 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11887 arm_print_operand (FILE *stream, rtx x, int code)
11892 fputs (ASM_COMMENT_START, stream);
11896 fputs (user_label_prefix, stream);
11900 fputs (REGISTER_PREFIX, stream);
11904 arm_print_condition (stream);
11908 /* Nothing in unified syntax, otherwise the current condition code. */
11909 if (!TARGET_UNIFIED_ASM)
11910 arm_print_condition (stream);
11914 /* The current condition code in unified syntax, otherwise nothing. */
11915 if (TARGET_UNIFIED_ASM)
11916 arm_print_condition (stream);
11920 /* The current condition code for a condition code setting instruction.
11921 Preceded by 's' in unified syntax, otherwise followed by 's'. */
11922 if (TARGET_UNIFIED_ASM)
11924 fputc('s', stream);
11925 arm_print_condition (stream);
11929 arm_print_condition (stream);
11930 fputc('s', stream);
11935 /* If the instruction is conditionally executed then print
11936 the current condition code, otherwise print 's'. */
11937 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
11938 if (current_insn_predicate)
11939 arm_print_condition (stream);
11941 fputc('s', stream);
11947 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11948 r = REAL_VALUE_NEGATE (r);
11949 fprintf (stream, "%s", fp_const_from_val (&r));
11954 if (GET_CODE (x) == CONST_INT)
11957 val = ARM_SIGN_EXTEND (~INTVAL (x));
11958 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11962 putc ('~', stream);
11963 output_addr_const (stream, x);
11968 /* The low 16 bits of an immediate constant. */
11969 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
11973 fprintf (stream, "%s", arithmetic_instr (x, 1));
11976 /* Truncate Cirrus shift counts. */
11978 if (GET_CODE (x) == CONST_INT)
11980 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11983 arm_print_operand (stream, x, 0);
11987 fprintf (stream, "%s", arithmetic_instr (x, 0));
11995 if (!shift_operator (x, SImode))
11997 output_operand_lossage ("invalid shift operand");
12001 shift = shift_op (x, &val);
12005 fprintf (stream, ", %s ", shift);
12007 arm_print_operand (stream, XEXP (x, 1), 0);
12009 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
12014 /* An explanation of the 'Q', 'R' and 'H' register operands:
12016 In a pair of registers containing a DI or DF value the 'Q'
12017 operand returns the register number of the register containing
12018 the least significant part of the value. The 'R' operand returns
12019 the register number of the register containing the most
12020 significant part of the value.
12022 The 'H' operand returns the higher of the two register numbers.
12023 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
12024 same as the 'Q' operand, since the most significant part of the
12025 value is held in the lower number register. The reverse is true
12026 on systems where WORDS_BIG_ENDIAN is false.
12028 The purpose of these operands is to distinguish between cases
12029 where the endian-ness of the values is important (for example
12030 when they are added together), and cases where the endian-ness
12031 is irrelevant, but the order of register operations is important.
12032 For example when loading a value from memory into a register
12033 pair, the endian-ness does not matter. Provided that the value
12034 from the lower memory address is put into the lower numbered
12035 register, and the value from the higher address is put into the
12036 higher numbered register, the load will work regardless of whether
12037 the value being loaded is big-wordian or little-wordian. The
12038 order of the two register loads can matter however, if the address
12039 of the memory location is actually held in one of the registers
12040 being overwritten by the load. */
12042 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12044 output_operand_lossage ("invalid operand for code '%c'", code);
12048 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
12052 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12054 output_operand_lossage ("invalid operand for code '%c'", code);
12058 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
12062 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12064 output_operand_lossage ("invalid operand for code '%c'", code);
12068 asm_fprintf (stream, "%r", REGNO (x) + 1);
12072 asm_fprintf (stream, "%r",
12073 GET_CODE (XEXP (x, 0)) == REG
12074 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
12078 asm_fprintf (stream, "{%r-%r}",
12080 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
12084 /* CONST_TRUE_RTX means always -- that's the default. */
12085 if (x == const_true_rtx)
12088 if (!COMPARISON_P (x))
12090 output_operand_lossage ("invalid operand for code '%c'", code);
12094 fputs (arm_condition_codes[get_arm_condition_code (x)],
12099 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
12100 want to do that. */
12101 if (x == const_true_rtx)
12103 output_operand_lossage ("instruction never executed");
12106 if (!COMPARISON_P (x))
12108 output_operand_lossage ("invalid operand for code '%c'", code);
12112 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
12113 (get_arm_condition_code (x))],
12117 /* Cirrus registers can be accessed in a variety of ways:
12118 single floating point (f)
12119 double floating point (d)
12121 64bit integer (dx). */
12122 case 'W': /* Cirrus register in F mode. */
12123 case 'X': /* Cirrus register in D mode. */
12124 case 'Y': /* Cirrus register in FX mode. */
12125 case 'Z': /* Cirrus register in DX mode. */
12126 gcc_assert (GET_CODE (x) == REG
12127 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
12129 fprintf (stream, "mv%s%s",
12131 : code == 'X' ? "d"
12132 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
12136 /* Print cirrus register in the mode specified by the register's mode. */
12139 int mode = GET_MODE (x);
12141 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
12143 output_operand_lossage ("invalid operand for code '%c'", code);
12147 fprintf (stream, "mv%s%s",
12148 mode == DFmode ? "d"
12149 : mode == SImode ? "fx"
12150 : mode == DImode ? "dx"
12151 : "f", reg_names[REGNO (x)] + 2);
12157 if (GET_CODE (x) != REG
12158 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
12159 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
12160 /* Bad value for wCG register number. */
12162 output_operand_lossage ("invalid operand for code '%c'", code);
12167 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
12170 /* Print an iWMMXt control register name. */
12172 if (GET_CODE (x) != CONST_INT
12174 || INTVAL (x) >= 16)
12175 /* Bad value for wC register number. */
12177 output_operand_lossage ("invalid operand for code '%c'", code);
12183 static const char * wc_reg_names [16] =
12185 "wCID", "wCon", "wCSSF", "wCASF",
12186 "wC4", "wC5", "wC6", "wC7",
12187 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
12188 "wC12", "wC13", "wC14", "wC15"
12191 fprintf (stream, wc_reg_names [INTVAL (x)]);
12195 /* Print a VFP double precision register name. */
12198 int mode = GET_MODE (x);
12201 if (mode != DImode && mode != DFmode)
12203 output_operand_lossage ("invalid operand for code '%c'", code);
12207 if (GET_CODE (x) != REG
12208 || !IS_VFP_REGNUM (REGNO (x)))
12210 output_operand_lossage ("invalid operand for code '%c'", code);
12214 num = REGNO(x) - FIRST_VFP_REGNUM;
12217 output_operand_lossage ("invalid operand for code '%c'", code);
12221 fprintf (stream, "d%d", num >> 1);
12225 /* Print a VFPv3 floating-point constant, represented as an integer
12229 int index = vfp3_const_double_index (x);
12230 gcc_assert (index != -1);
12231 fprintf (stream, "%d", index);
12238 output_operand_lossage ("missing operand");
12242 switch (GET_CODE (x))
12245 asm_fprintf (stream, "%r", REGNO (x));
12249 output_memory_reference_mode = GET_MODE (x);
12250 output_address (XEXP (x, 0));
12254 fprintf (stream, "#%s", fp_immediate_constant (x));
12258 gcc_assert (GET_CODE (x) != NEG);
12259 fputc ('#', stream);
12260 output_addr_const (stream, x);
12266 #ifndef AOF_ASSEMBLER
12267 /* Target hook for assembling integer objects. The ARM version needs to
12268 handle word-sized values specially. */
12270 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
12272 if (size == UNITS_PER_WORD && aligned_p)
12274 fputs ("\t.word\t", asm_out_file);
12275 output_addr_const (asm_out_file, x);
12277 /* Mark symbols as position independent. We only do this in the
12278 .text segment, not in the .data segment. */
12279 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
12280 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
12282 /* See legitimize_pic_address for an explanation of the
12283 TARGET_VXWORKS_RTP check. */
12284 if (TARGET_VXWORKS_RTP
12285 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
12286 fputs ("(GOT)", asm_out_file);
12288 fputs ("(GOTOFF)", asm_out_file);
12290 fputc ('\n', asm_out_file);
12294 if (arm_vector_mode_supported_p (GET_MODE (x)))
12298 gcc_assert (GET_CODE (x) == CONST_VECTOR);
12300 units = CONST_VECTOR_NUNITS (x);
12302 switch (GET_MODE (x))
12304 case V2SImode: size = 4; break;
12305 case V4HImode: size = 2; break;
12306 case V8QImode: size = 1; break;
12308 gcc_unreachable ();
12311 for (i = 0; i < units; i++)
12315 elt = CONST_VECTOR_ELT (x, i);
12317 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
12323 return default_assemble_integer (x, size, aligned_p);
12327 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
12331 if (!TARGET_AAPCS_BASED)
12334 default_named_section_asm_out_constructor
12335 : default_named_section_asm_out_destructor) (symbol, priority);
12339 /* Put these in the .init_array section, using a special relocation. */
12340 if (priority != DEFAULT_INIT_PRIORITY)
12343 sprintf (buf, "%s.%.5u",
12344 is_ctor ? ".init_array" : ".fini_array",
12346 s = get_section (buf, SECTION_WRITE, NULL_TREE);
12353 switch_to_section (s);
12354 assemble_align (POINTER_SIZE);
12355 fputs ("\t.word\t", asm_out_file);
12356 output_addr_const (asm_out_file, symbol);
12357 fputs ("(target1)\n", asm_out_file);
12360 /* Add a function to the list of static constructors. */
12363 arm_elf_asm_constructor (rtx symbol, int priority)
12365 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
12368 /* Add a function to the list of static destructors. */
12371 arm_elf_asm_destructor (rtx symbol, int priority)
12373 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
12377 /* A finite state machine takes care of noticing whether or not instructions
12378 can be conditionally executed, and thus decrease execution time and code
12379 size by deleting branch instructions. The fsm is controlled by
12380 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12382 /* The state of the fsm controlling condition codes are:
12383 0: normal, do nothing special
12384 1: make ASM_OUTPUT_OPCODE not output this instruction
12385 2: make ASM_OUTPUT_OPCODE not output this instruction
12386 3: make instructions conditional
12387 4: make instructions conditional
12389 State transitions (state->state by whom under condition):
12390 0 -> 1 final_prescan_insn if the `target' is a label
12391 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12392 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12393 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12394 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12395 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12396 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12397 (the target insn is arm_target_insn).
12399 If the jump clobbers the conditions then we use states 2 and 4.
12401 A similar thing can be done with conditional return insns.
12403 XXX In case the `target' is an unconditional branch, this conditionalising
12404 of the instructions always reduces code size, but not always execution
12405 time. But then, I want to reduce the code size to somewhere near what
12406 /bin/cc produces. */
12408 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12409 instructions. When a COND_EXEC instruction is seen the subsequent
12410 instructions are scanned so that multiple conditional instructions can be
12411 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12412 specify the length and true/false mask for the IT block. These will be
12413 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12415 /* Returns the index of the ARM condition code string in
12416 `arm_condition_codes'. COMPARISON should be an rtx like
12417 `(eq (...) (...))'. */
12418 static enum arm_cond_code
12419 get_arm_condition_code (rtx comparison)
12421 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
12423 enum rtx_code comp_code = GET_CODE (comparison);
12425 if (GET_MODE_CLASS (mode) != MODE_CC)
12426 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
12427 XEXP (comparison, 1));
12431 case CC_DNEmode: code = ARM_NE; goto dominance;
12432 case CC_DEQmode: code = ARM_EQ; goto dominance;
12433 case CC_DGEmode: code = ARM_GE; goto dominance;
12434 case CC_DGTmode: code = ARM_GT; goto dominance;
12435 case CC_DLEmode: code = ARM_LE; goto dominance;
12436 case CC_DLTmode: code = ARM_LT; goto dominance;
12437 case CC_DGEUmode: code = ARM_CS; goto dominance;
12438 case CC_DGTUmode: code = ARM_HI; goto dominance;
12439 case CC_DLEUmode: code = ARM_LS; goto dominance;
12440 case CC_DLTUmode: code = ARM_CC;
12443 gcc_assert (comp_code == EQ || comp_code == NE);
12445 if (comp_code == EQ)
12446 return ARM_INVERSE_CONDITION_CODE (code);
12452 case NE: return ARM_NE;
12453 case EQ: return ARM_EQ;
12454 case GE: return ARM_PL;
12455 case LT: return ARM_MI;
12456 default: gcc_unreachable ();
12462 case NE: return ARM_NE;
12463 case EQ: return ARM_EQ;
12464 default: gcc_unreachable ();
12470 case NE: return ARM_MI;
12471 case EQ: return ARM_PL;
12472 default: gcc_unreachable ();
12477 /* These encodings assume that AC=1 in the FPA system control
12478 byte. This allows us to handle all cases except UNEQ and
12482 case GE: return ARM_GE;
12483 case GT: return ARM_GT;
12484 case LE: return ARM_LS;
12485 case LT: return ARM_MI;
12486 case NE: return ARM_NE;
12487 case EQ: return ARM_EQ;
12488 case ORDERED: return ARM_VC;
12489 case UNORDERED: return ARM_VS;
12490 case UNLT: return ARM_LT;
12491 case UNLE: return ARM_LE;
12492 case UNGT: return ARM_HI;
12493 case UNGE: return ARM_PL;
12494 /* UNEQ and LTGT do not have a representation. */
12495 case UNEQ: /* Fall through. */
12496 case LTGT: /* Fall through. */
12497 default: gcc_unreachable ();
12503 case NE: return ARM_NE;
12504 case EQ: return ARM_EQ;
12505 case GE: return ARM_LE;
12506 case GT: return ARM_LT;
12507 case LE: return ARM_GE;
12508 case LT: return ARM_GT;
12509 case GEU: return ARM_LS;
12510 case GTU: return ARM_CC;
12511 case LEU: return ARM_CS;
12512 case LTU: return ARM_HI;
12513 default: gcc_unreachable ();
12519 case LTU: return ARM_CS;
12520 case GEU: return ARM_CC;
12521 default: gcc_unreachable ();
12527 case NE: return ARM_NE;
12528 case EQ: return ARM_EQ;
12529 case GE: return ARM_GE;
12530 case GT: return ARM_GT;
12531 case LE: return ARM_LE;
12532 case LT: return ARM_LT;
12533 case GEU: return ARM_CS;
12534 case GTU: return ARM_HI;
12535 case LEU: return ARM_LS;
12536 case LTU: return ARM_CC;
12537 default: gcc_unreachable ();
12540 default: gcc_unreachable ();
12544 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
12547 thumb2_final_prescan_insn (rtx insn)
12549 rtx first_insn = insn;
12550 rtx body = PATTERN (insn);
12552 enum arm_cond_code code;
12556 /* Remove the previous insn from the count of insns to be output. */
12557 if (arm_condexec_count)
12558 arm_condexec_count--;
12560 /* Nothing to do if we are already inside a conditional block. */
12561 if (arm_condexec_count)
12564 if (GET_CODE (body) != COND_EXEC)
12567 /* Conditional jumps are implemented directly. */
12568 if (GET_CODE (insn) == JUMP_INSN)
12571 predicate = COND_EXEC_TEST (body);
12572 arm_current_cc = get_arm_condition_code (predicate);
12574 n = get_attr_ce_count (insn);
12575 arm_condexec_count = 1;
12576 arm_condexec_mask = (1 << n) - 1;
12577 arm_condexec_masklen = n;
12578 /* See if subsequent instructions can be combined into the same block. */
12581 insn = next_nonnote_insn (insn);
12583 /* Jumping into the middle of an IT block is illegal, so a label or
12584 barrier terminates the block. */
12585 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
12588 body = PATTERN (insn);
12589 /* USE and CLOBBER aren't really insns, so just skip them. */
12590 if (GET_CODE (body) == USE
12591 || GET_CODE (body) == CLOBBER)
12594 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
12595 if (GET_CODE (body) != COND_EXEC)
12597 /* Allow up to 4 conditionally executed instructions in a block. */
12598 n = get_attr_ce_count (insn);
12599 if (arm_condexec_masklen + n > 4)
12602 predicate = COND_EXEC_TEST (body);
12603 code = get_arm_condition_code (predicate);
12604 mask = (1 << n) - 1;
12605 if (arm_current_cc == code)
12606 arm_condexec_mask |= (mask << arm_condexec_masklen);
12607 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
12610 arm_condexec_count++;
12611 arm_condexec_masklen += n;
12613 /* A jump must be the last instruction in a conditional block. */
12614 if (GET_CODE(insn) == JUMP_INSN)
12617 /* Restore recog_data (getting the attributes of other insns can
12618 destroy this array, but final.c assumes that it remains intact
12619 across this call). */
12620 extract_constrain_insn_cached (first_insn);
12624 arm_final_prescan_insn (rtx insn)
12626 /* BODY will hold the body of INSN. */
12627 rtx body = PATTERN (insn);
12629 /* This will be 1 if trying to repeat the trick, and things need to be
12630 reversed if it appears to fail. */
12633 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12634 taken are clobbered, even if the rtl suggests otherwise. It also
12635 means that we have to grub around within the jump expression to find
12636 out what the conditions are when the jump isn't taken. */
12637 int jump_clobbers = 0;
12639 /* If we start with a return insn, we only succeed if we find another one. */
12640 int seeking_return = 0;
12642 /* START_INSN will hold the insn from where we start looking. This is the
12643 first insn after the following code_label if REVERSE is true. */
12644 rtx start_insn = insn;
12646 /* If in state 4, check if the target branch is reached, in order to
12647 change back to state 0. */
12648 if (arm_ccfsm_state == 4)
12650 if (insn == arm_target_insn)
12652 arm_target_insn = NULL;
12653 arm_ccfsm_state = 0;
12658 /* If in state 3, it is possible to repeat the trick, if this insn is an
12659 unconditional branch to a label, and immediately following this branch
12660 is the previous target label which is only used once, and the label this
12661 branch jumps to is not too far off. */
12662 if (arm_ccfsm_state == 3)
12664 if (simplejump_p (insn))
12666 start_insn = next_nonnote_insn (start_insn);
12667 if (GET_CODE (start_insn) == BARRIER)
12669 /* XXX Isn't this always a barrier? */
12670 start_insn = next_nonnote_insn (start_insn);
12672 if (GET_CODE (start_insn) == CODE_LABEL
12673 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12674 && LABEL_NUSES (start_insn) == 1)
12679 else if (GET_CODE (body) == RETURN)
12681 start_insn = next_nonnote_insn (start_insn);
12682 if (GET_CODE (start_insn) == BARRIER)
12683 start_insn = next_nonnote_insn (start_insn);
12684 if (GET_CODE (start_insn) == CODE_LABEL
12685 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12686 && LABEL_NUSES (start_insn) == 1)
12689 seeking_return = 1;
12698 gcc_assert (!arm_ccfsm_state || reverse);
12699 if (GET_CODE (insn) != JUMP_INSN)
12702 /* This jump might be paralleled with a clobber of the condition codes
12703 the jump should always come first */
12704 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
12705 body = XVECEXP (body, 0, 0);
12708 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
12709 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
12712 int fail = FALSE, succeed = FALSE;
12713 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12714 int then_not_else = TRUE;
12715 rtx this_insn = start_insn, label = 0;
12717 /* If the jump cannot be done with one instruction, we cannot
12718 conditionally execute the instruction in the inverse case. */
12719 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
12725 /* Register the insn jumped to. */
12728 if (!seeking_return)
12729 label = XEXP (SET_SRC (body), 0);
12731 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
12732 label = XEXP (XEXP (SET_SRC (body), 1), 0);
12733 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
12735 label = XEXP (XEXP (SET_SRC (body), 2), 0);
12736 then_not_else = FALSE;
12738 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
12739 seeking_return = 1;
12740 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
12742 seeking_return = 1;
12743 then_not_else = FALSE;
12746 gcc_unreachable ();
12748 /* See how many insns this branch skips, and what kind of insns. If all
12749 insns are okay, and the label or unconditional branch to the same
12750 label is not too far away, succeed. */
12751 for (insns_skipped = 0;
12752 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
12756 this_insn = next_nonnote_insn (this_insn);
12760 switch (GET_CODE (this_insn))
12763 /* Succeed if it is the target label, otherwise fail since
12764 control falls in from somewhere else. */
12765 if (this_insn == label)
12769 arm_ccfsm_state = 2;
12770 this_insn = next_nonnote_insn (this_insn);
12773 arm_ccfsm_state = 1;
12781 /* Succeed if the following insn is the target label.
12783 If return insns are used then the last insn in a function
12784 will be a barrier. */
12785 this_insn = next_nonnote_insn (this_insn);
12786 if (this_insn && this_insn == label)
12790 arm_ccfsm_state = 2;
12791 this_insn = next_nonnote_insn (this_insn);
12794 arm_ccfsm_state = 1;
12802 /* The AAPCS says that conditional calls should not be
12803 used since they make interworking inefficient (the
12804 linker can't transform BL<cond> into BLX). That's
12805 only a problem if the machine has BLX. */
12812 /* Succeed if the following insn is the target label, or
12813 if the following two insns are a barrier and the
12815 this_insn = next_nonnote_insn (this_insn);
12816 if (this_insn && GET_CODE (this_insn) == BARRIER)
12817 this_insn = next_nonnote_insn (this_insn);
12819 if (this_insn && this_insn == label
12820 && insns_skipped < max_insns_skipped)
12824 arm_ccfsm_state = 2;
12825 this_insn = next_nonnote_insn (this_insn);
12828 arm_ccfsm_state = 1;
12836 /* If this is an unconditional branch to the same label, succeed.
12837 If it is to another label, do nothing. If it is conditional,
12839 /* XXX Probably, the tests for SET and the PC are
12842 scanbody = PATTERN (this_insn);
12843 if (GET_CODE (scanbody) == SET
12844 && GET_CODE (SET_DEST (scanbody)) == PC)
12846 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
12847 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
12849 arm_ccfsm_state = 2;
12852 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
12855 /* Fail if a conditional return is undesirable (e.g. on a
12856 StrongARM), but still allow this if optimizing for size. */
12857 else if (GET_CODE (scanbody) == RETURN
12858 && !use_return_insn (TRUE, NULL)
12861 else if (GET_CODE (scanbody) == RETURN
12864 arm_ccfsm_state = 2;
12867 else if (GET_CODE (scanbody) == PARALLEL)
12869 switch (get_attr_conds (this_insn))
12879 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
12884 /* Instructions using or affecting the condition codes make it
12886 scanbody = PATTERN (this_insn);
12887 if (!(GET_CODE (scanbody) == SET
12888 || GET_CODE (scanbody) == PARALLEL)
12889 || get_attr_conds (this_insn) != CONDS_NOCOND)
12892 /* A conditional cirrus instruction must be followed by
12893 a non Cirrus instruction. However, since we
12894 conditionalize instructions in this function and by
12895 the time we get here we can't add instructions
12896 (nops), because shorten_branches() has already been
12897 called, we will disable conditionalizing Cirrus
12898 instructions to be safe. */
12899 if (GET_CODE (scanbody) != USE
12900 && GET_CODE (scanbody) != CLOBBER
12901 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
12911 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
12912 arm_target_label = CODE_LABEL_NUMBER (label);
12915 gcc_assert (seeking_return || arm_ccfsm_state == 2);
12917 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
12919 this_insn = next_nonnote_insn (this_insn);
12920 gcc_assert (!this_insn
12921 || (GET_CODE (this_insn) != BARRIER
12922 && GET_CODE (this_insn) != CODE_LABEL));
12926 /* Oh, dear! we ran off the end.. give up. */
12927 extract_constrain_insn_cached (insn);
12928 arm_ccfsm_state = 0;
12929 arm_target_insn = NULL;
12932 arm_target_insn = this_insn;
12936 gcc_assert (!reverse);
12938 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
12940 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
12941 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12942 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
12943 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12947 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12950 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
12954 if (reverse || then_not_else)
12955 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12958 /* Restore recog_data (getting the attributes of other insns can
12959 destroy this array, but final.c assumes that it remains intact
12960 across this call. */
12961 extract_constrain_insn_cached (insn);
12965 /* Output IT instructions. */
12967 thumb2_asm_output_opcode (FILE * stream)
12972 if (arm_condexec_mask)
12974 for (n = 0; n < arm_condexec_masklen; n++)
12975 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
12977 asm_fprintf(stream, "i%s\t%s\n\t", buff,
12978 arm_condition_codes[arm_current_cc]);
12979 arm_condexec_mask = 0;
12983 /* Returns true if REGNO is a valid register
12984 for holding a quantity of type MODE. */
12986 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
12988 if (GET_MODE_CLASS (mode) == MODE_CC)
12989 return (regno == CC_REGNUM
12990 || (TARGET_HARD_FLOAT && TARGET_VFP
12991 && regno == VFPCC_REGNUM));
12994 /* For the Thumb we only allow values bigger than SImode in
12995 registers 0 - 6, so that there is always a second low
12996 register available to hold the upper part of the value.
12997 We probably we ought to ensure that the register is the
12998 start of an even numbered register pair. */
12999 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
13001 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
13002 && IS_CIRRUS_REGNUM (regno))
13003 /* We have outlawed SI values in Cirrus registers because they
13004 reside in the lower 32 bits, but SF values reside in the
13005 upper 32 bits. This causes gcc all sorts of grief. We can't
13006 even split the registers into pairs because Cirrus SI values
13007 get sign extended to 64bits-- aldyh. */
13008 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
13010 if (TARGET_HARD_FLOAT && TARGET_VFP
13011 && IS_VFP_REGNUM (regno))
13013 if (mode == SFmode || mode == SImode)
13014 return VFP_REGNO_OK_FOR_SINGLE (regno);
13016 if (mode == DFmode)
13017 return VFP_REGNO_OK_FOR_DOUBLE (regno);
13021 if (TARGET_REALLY_IWMMXT)
13023 if (IS_IWMMXT_GR_REGNUM (regno))
13024 return mode == SImode;
13026 if (IS_IWMMXT_REGNUM (regno))
13027 return VALID_IWMMXT_REG_MODE (mode);
13030 /* We allow any value to be stored in the general registers.
13031 Restrict doubleword quantities to even register pairs so that we can
13033 if (regno <= LAST_ARM_REGNUM)
13034 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
13036 if (regno == FRAME_POINTER_REGNUM
13037 || regno == ARG_POINTER_REGNUM)
13038 /* We only allow integers in the fake hard registers. */
13039 return GET_MODE_CLASS (mode) == MODE_INT;
13041 /* The only registers left are the FPA registers
13042 which we only allow to hold FP values. */
13043 return (TARGET_HARD_FLOAT && TARGET_FPA
13044 && GET_MODE_CLASS (mode) == MODE_FLOAT
13045 && regno >= FIRST_FPA_REGNUM
13046 && regno <= LAST_FPA_REGNUM);
13049 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
13050 not used in arm mode. */
13052 arm_regno_class (int regno)
13056 if (regno == STACK_POINTER_REGNUM)
13058 if (regno == CC_REGNUM)
13065 if (TARGET_THUMB2 && regno < 8)
13068 if ( regno <= LAST_ARM_REGNUM
13069 || regno == FRAME_POINTER_REGNUM
13070 || regno == ARG_POINTER_REGNUM)
13071 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
13073 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
13074 return TARGET_THUMB2 ? CC_REG : NO_REGS;
13076 if (IS_CIRRUS_REGNUM (regno))
13077 return CIRRUS_REGS;
13079 if (IS_VFP_REGNUM (regno))
13081 if (regno <= D7_VFP_REGNUM)
13082 return VFP_D0_D7_REGS;
13083 else if (regno <= LAST_LO_VFP_REGNUM)
13084 return VFP_LO_REGS;
13086 return VFP_HI_REGS;
13089 if (IS_IWMMXT_REGNUM (regno))
13090 return IWMMXT_REGS;
13092 if (IS_IWMMXT_GR_REGNUM (regno))
13093 return IWMMXT_GR_REGS;
13098 /* Handle a special case when computing the offset
13099 of an argument from the frame pointer. */
13101 arm_debugger_arg_offset (int value, rtx addr)
13105 /* We are only interested if dbxout_parms() failed to compute the offset. */
13109 /* We can only cope with the case where the address is held in a register. */
13110 if (GET_CODE (addr) != REG)
13113 /* If we are using the frame pointer to point at the argument, then
13114 an offset of 0 is correct. */
13115 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
13118 /* If we are using the stack pointer to point at the
13119 argument, then an offset of 0 is correct. */
13120 /* ??? Check this is consistent with thumb2 frame layout. */
13121 if ((TARGET_THUMB || !frame_pointer_needed)
13122 && REGNO (addr) == SP_REGNUM)
13125 /* Oh dear. The argument is pointed to by a register rather
13126 than being held in a register, or being stored at a known
13127 offset from the frame pointer. Since GDB only understands
13128 those two kinds of argument we must translate the address
13129 held in the register into an offset from the frame pointer.
13130 We do this by searching through the insns for the function
13131 looking to see where this register gets its value. If the
13132 register is initialized from the frame pointer plus an offset
13133 then we are in luck and we can continue, otherwise we give up.
13135 This code is exercised by producing debugging information
13136 for a function with arguments like this:
13138 double func (double a, double b, int c, double d) {return d;}
13140 Without this code the stab for parameter 'd' will be set to
13141 an offset of 0 from the frame pointer, rather than 8. */
13143 /* The if() statement says:
13145 If the insn is a normal instruction
13146 and if the insn is setting the value in a register
13147 and if the register being set is the register holding the address of the argument
13148 and if the address is computing by an addition
13149 that involves adding to a register
13150 which is the frame pointer
13155 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13157 if ( GET_CODE (insn) == INSN
13158 && GET_CODE (PATTERN (insn)) == SET
13159 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
13160 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
13161 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
13162 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
13163 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
13166 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
13175 warning (0, "unable to compute real location of stacked parameter");
13176 value = 8; /* XXX magic hack */
13182 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
13185 if ((MASK) & insn_flags) \
13186 add_builtin_function ((NAME), (TYPE), (CODE), \
13187 BUILT_IN_MD, NULL, NULL_TREE); \
13191 struct builtin_description
13193 const unsigned int mask;
13194 const enum insn_code icode;
13195 const char * const name;
13196 const enum arm_builtins code;
13197 const enum rtx_code comparison;
13198 const unsigned int flag;
13201 static const struct builtin_description bdesc_2arg[] =
13203 #define IWMMXT_BUILTIN(code, string, builtin) \
13204 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
13205 ARM_BUILTIN_##builtin, 0, 0 },
13207 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
13208 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
13209 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
13210 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
13211 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
13212 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
13213 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
13214 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
13215 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
13216 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
13217 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
13218 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
13219 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
13220 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
13221 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
13222 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
13223 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
13224 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
13225 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
13226 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
13227 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
13228 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
13229 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
13230 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
13231 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
13232 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
13233 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
13234 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
13235 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
13236 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
13237 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
13238 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
13239 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
13240 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
13241 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
13242 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
13243 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
13244 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
13245 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
13246 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
13247 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
13248 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
13249 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
13250 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
13251 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
13252 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
13253 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
13254 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
13255 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
13256 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
13257 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
13258 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
13259 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
13260 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
13261 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
13262 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
13263 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
13264 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
13266 #define IWMMXT_BUILTIN2(code, builtin) \
13267 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
13269 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
13270 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
13271 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
13272 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
13273 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
13274 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
13275 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
13276 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
13277 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
13278 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
13279 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
13280 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
13281 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
13282 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
13283 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
13284 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
13285 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
13286 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
13287 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
13288 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
13289 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
13290 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
13291 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
13292 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
13293 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
13294 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
13295 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
13296 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
13297 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
13298 IWMMXT_BUILTIN2 (rordi3, WRORDI)
13299 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
13300 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
13303 static const struct builtin_description bdesc_1arg[] =
13305 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
13306 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
13307 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
13308 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
13309 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
13310 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
13311 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
13312 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
13313 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
13314 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
13315 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
13316 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
13317 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
13318 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
13319 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
13320 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
13321 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
13322 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
13325 /* Set up all the iWMMXt builtins. This is
13326 not called if TARGET_IWMMXT is zero. */
13329 arm_init_iwmmxt_builtins (void)
13331 const struct builtin_description * d;
13333 tree endlink = void_list_node;
13335 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
13336 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
13337 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
13340 = build_function_type (integer_type_node,
13341 tree_cons (NULL_TREE, integer_type_node, endlink));
13342 tree v8qi_ftype_v8qi_v8qi_int
13343 = build_function_type (V8QI_type_node,
13344 tree_cons (NULL_TREE, V8QI_type_node,
13345 tree_cons (NULL_TREE, V8QI_type_node,
13346 tree_cons (NULL_TREE,
13349 tree v4hi_ftype_v4hi_int
13350 = build_function_type (V4HI_type_node,
13351 tree_cons (NULL_TREE, V4HI_type_node,
13352 tree_cons (NULL_TREE, integer_type_node,
13354 tree v2si_ftype_v2si_int
13355 = build_function_type (V2SI_type_node,
13356 tree_cons (NULL_TREE, V2SI_type_node,
13357 tree_cons (NULL_TREE, integer_type_node,
13359 tree v2si_ftype_di_di
13360 = build_function_type (V2SI_type_node,
13361 tree_cons (NULL_TREE, long_long_integer_type_node,
13362 tree_cons (NULL_TREE, long_long_integer_type_node,
13364 tree di_ftype_di_int
13365 = build_function_type (long_long_integer_type_node,
13366 tree_cons (NULL_TREE, long_long_integer_type_node,
13367 tree_cons (NULL_TREE, integer_type_node,
13369 tree di_ftype_di_int_int
13370 = build_function_type (long_long_integer_type_node,
13371 tree_cons (NULL_TREE, long_long_integer_type_node,
13372 tree_cons (NULL_TREE, integer_type_node,
13373 tree_cons (NULL_TREE,
13376 tree int_ftype_v8qi
13377 = build_function_type (integer_type_node,
13378 tree_cons (NULL_TREE, V8QI_type_node,
13380 tree int_ftype_v4hi
13381 = build_function_type (integer_type_node,
13382 tree_cons (NULL_TREE, V4HI_type_node,
13384 tree int_ftype_v2si
13385 = build_function_type (integer_type_node,
13386 tree_cons (NULL_TREE, V2SI_type_node,
13388 tree int_ftype_v8qi_int
13389 = build_function_type (integer_type_node,
13390 tree_cons (NULL_TREE, V8QI_type_node,
13391 tree_cons (NULL_TREE, integer_type_node,
13393 tree int_ftype_v4hi_int
13394 = build_function_type (integer_type_node,
13395 tree_cons (NULL_TREE, V4HI_type_node,
13396 tree_cons (NULL_TREE, integer_type_node,
13398 tree int_ftype_v2si_int
13399 = build_function_type (integer_type_node,
13400 tree_cons (NULL_TREE, V2SI_type_node,
13401 tree_cons (NULL_TREE, integer_type_node,
13403 tree v8qi_ftype_v8qi_int_int
13404 = build_function_type (V8QI_type_node,
13405 tree_cons (NULL_TREE, V8QI_type_node,
13406 tree_cons (NULL_TREE, integer_type_node,
13407 tree_cons (NULL_TREE,
13410 tree v4hi_ftype_v4hi_int_int
13411 = build_function_type (V4HI_type_node,
13412 tree_cons (NULL_TREE, V4HI_type_node,
13413 tree_cons (NULL_TREE, integer_type_node,
13414 tree_cons (NULL_TREE,
13417 tree v2si_ftype_v2si_int_int
13418 = build_function_type (V2SI_type_node,
13419 tree_cons (NULL_TREE, V2SI_type_node,
13420 tree_cons (NULL_TREE, integer_type_node,
13421 tree_cons (NULL_TREE,
13424 /* Miscellaneous. */
13425 tree v8qi_ftype_v4hi_v4hi
13426 = build_function_type (V8QI_type_node,
13427 tree_cons (NULL_TREE, V4HI_type_node,
13428 tree_cons (NULL_TREE, V4HI_type_node,
13430 tree v4hi_ftype_v2si_v2si
13431 = build_function_type (V4HI_type_node,
13432 tree_cons (NULL_TREE, V2SI_type_node,
13433 tree_cons (NULL_TREE, V2SI_type_node,
13435 tree v2si_ftype_v4hi_v4hi
13436 = build_function_type (V2SI_type_node,
13437 tree_cons (NULL_TREE, V4HI_type_node,
13438 tree_cons (NULL_TREE, V4HI_type_node,
13440 tree v2si_ftype_v8qi_v8qi
13441 = build_function_type (V2SI_type_node,
13442 tree_cons (NULL_TREE, V8QI_type_node,
13443 tree_cons (NULL_TREE, V8QI_type_node,
13445 tree v4hi_ftype_v4hi_di
13446 = build_function_type (V4HI_type_node,
13447 tree_cons (NULL_TREE, V4HI_type_node,
13448 tree_cons (NULL_TREE,
13449 long_long_integer_type_node,
13451 tree v2si_ftype_v2si_di
13452 = build_function_type (V2SI_type_node,
13453 tree_cons (NULL_TREE, V2SI_type_node,
13454 tree_cons (NULL_TREE,
13455 long_long_integer_type_node,
13457 tree void_ftype_int_int
13458 = build_function_type (void_type_node,
13459 tree_cons (NULL_TREE, integer_type_node,
13460 tree_cons (NULL_TREE, integer_type_node,
13463 = build_function_type (long_long_unsigned_type_node, endlink);
13465 = build_function_type (long_long_integer_type_node,
13466 tree_cons (NULL_TREE, V8QI_type_node,
13469 = build_function_type (long_long_integer_type_node,
13470 tree_cons (NULL_TREE, V4HI_type_node,
13473 = build_function_type (long_long_integer_type_node,
13474 tree_cons (NULL_TREE, V2SI_type_node,
13476 tree v2si_ftype_v4hi
13477 = build_function_type (V2SI_type_node,
13478 tree_cons (NULL_TREE, V4HI_type_node,
13480 tree v4hi_ftype_v8qi
13481 = build_function_type (V4HI_type_node,
13482 tree_cons (NULL_TREE, V8QI_type_node,
13485 tree di_ftype_di_v4hi_v4hi
13486 = build_function_type (long_long_unsigned_type_node,
13487 tree_cons (NULL_TREE,
13488 long_long_unsigned_type_node,
13489 tree_cons (NULL_TREE, V4HI_type_node,
13490 tree_cons (NULL_TREE,
13494 tree di_ftype_v4hi_v4hi
13495 = build_function_type (long_long_unsigned_type_node,
13496 tree_cons (NULL_TREE, V4HI_type_node,
13497 tree_cons (NULL_TREE, V4HI_type_node,
13500 /* Normal vector binops. */
13501 tree v8qi_ftype_v8qi_v8qi
13502 = build_function_type (V8QI_type_node,
13503 tree_cons (NULL_TREE, V8QI_type_node,
13504 tree_cons (NULL_TREE, V8QI_type_node,
13506 tree v4hi_ftype_v4hi_v4hi
13507 = build_function_type (V4HI_type_node,
13508 tree_cons (NULL_TREE, V4HI_type_node,
13509 tree_cons (NULL_TREE, V4HI_type_node,
13511 tree v2si_ftype_v2si_v2si
13512 = build_function_type (V2SI_type_node,
13513 tree_cons (NULL_TREE, V2SI_type_node,
13514 tree_cons (NULL_TREE, V2SI_type_node,
13516 tree di_ftype_di_di
13517 = build_function_type (long_long_unsigned_type_node,
13518 tree_cons (NULL_TREE, long_long_unsigned_type_node,
13519 tree_cons (NULL_TREE,
13520 long_long_unsigned_type_node,
13523 /* Add all builtins that are more or less simple operations on two
13525 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13527 /* Use one of the operands; the target can have a different mode for
13528 mask-generating compares. */
13529 enum machine_mode mode;
13535 mode = insn_data[d->icode].operand[1].mode;
13540 type = v8qi_ftype_v8qi_v8qi;
13543 type = v4hi_ftype_v4hi_v4hi;
13546 type = v2si_ftype_v2si_v2si;
13549 type = di_ftype_di_di;
13553 gcc_unreachable ();
13556 def_mbuiltin (d->mask, d->name, type, d->code);
13559 /* Add the remaining MMX insns with somewhat more complicated types. */
13560 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
13561 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
13562 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
13564 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
13565 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
13566 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
13567 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
13568 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
13569 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
13571 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
13572 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
13573 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
13574 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
13575 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
13576 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
13578 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
13579 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
13580 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
13581 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
13582 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
13583 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
13585 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
13586 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
13587 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
13588 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
13589 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
13590 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
13592 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
13594 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
13595 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
13596 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
13597 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
13599 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
13600 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
13601 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
13602 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
13603 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
13604 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
13605 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
13606 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
13607 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
13609 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
13610 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
13611 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
13613 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
13614 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
13615 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
13617 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
13618 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
13619 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
13620 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
13621 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
13622 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
13624 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
13625 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
13626 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
13627 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
13628 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
13629 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
13630 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
13631 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
13632 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
13633 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
13634 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
13635 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
13637 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
13638 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
13639 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
13640 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
13642 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
13643 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
13644 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
13645 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
13646 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
13647 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
13648 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
13652 arm_init_tls_builtins (void)
13655 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
13656 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
13658 ftype = build_function_type (ptr_type_node, void_list_node);
13659 add_builtin_function ("__builtin_thread_pointer", ftype,
13660 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
13661 NULL, const_nothrow);
13665 arm_init_builtins (void)
13667 arm_init_tls_builtins ();
13669 if (TARGET_REALLY_IWMMXT)
13670 arm_init_iwmmxt_builtins ();
13673 /* Errors in the source file can cause expand_expr to return const0_rtx
13674 where we expect a vector. To avoid crashing, use one of the vector
13675 clear instructions. */
13678 safe_vector_operand (rtx x, enum machine_mode mode)
13680 if (x != const0_rtx)
13682 x = gen_reg_rtx (mode);
13684 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
13685 : gen_rtx_SUBREG (DImode, x, 0)));
13689 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13692 arm_expand_binop_builtin (enum insn_code icode,
13693 tree exp, rtx target)
13696 tree arg0 = CALL_EXPR_ARG (exp, 0);
13697 tree arg1 = CALL_EXPR_ARG (exp, 1);
13698 rtx op0 = expand_normal (arg0);
13699 rtx op1 = expand_normal (arg1);
13700 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13701 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13702 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
13704 if (VECTOR_MODE_P (mode0))
13705 op0 = safe_vector_operand (op0, mode0);
13706 if (VECTOR_MODE_P (mode1))
13707 op1 = safe_vector_operand (op1, mode1);
13710 || GET_MODE (target) != tmode
13711 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13712 target = gen_reg_rtx (tmode);
13714 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
13716 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13717 op0 = copy_to_mode_reg (mode0, op0);
13718 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13719 op1 = copy_to_mode_reg (mode1, op1);
13721 pat = GEN_FCN (icode) (target, op0, op1);
13728 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13731 arm_expand_unop_builtin (enum insn_code icode,
13732 tree exp, rtx target, int do_load)
13735 tree arg0 = CALL_EXPR_ARG (exp, 0);
13736 rtx op0 = expand_normal (arg0);
13737 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13738 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13741 || GET_MODE (target) != tmode
13742 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13743 target = gen_reg_rtx (tmode);
13745 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
13748 if (VECTOR_MODE_P (mode0))
13749 op0 = safe_vector_operand (op0, mode0);
13751 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13752 op0 = copy_to_mode_reg (mode0, op0);
13755 pat = GEN_FCN (icode) (target, op0);
13762 /* Expand an expression EXP that calls a built-in function,
13763 with result going to TARGET if that's convenient
13764 (and in mode MODE if that's convenient).
13765 SUBTARGET may be used as the target for computing one of EXP's operands.
13766 IGNORE is nonzero if the value is to be ignored. */
13769 arm_expand_builtin (tree exp,
13771 rtx subtarget ATTRIBUTE_UNUSED,
13772 enum machine_mode mode ATTRIBUTE_UNUSED,
13773 int ignore ATTRIBUTE_UNUSED)
13775 const struct builtin_description * d;
13776 enum insn_code icode;
13777 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13785 int fcode = DECL_FUNCTION_CODE (fndecl);
13787 enum machine_mode tmode;
13788 enum machine_mode mode0;
13789 enum machine_mode mode1;
13790 enum machine_mode mode2;
13794 case ARM_BUILTIN_TEXTRMSB:
13795 case ARM_BUILTIN_TEXTRMUB:
13796 case ARM_BUILTIN_TEXTRMSH:
13797 case ARM_BUILTIN_TEXTRMUH:
13798 case ARM_BUILTIN_TEXTRMSW:
13799 case ARM_BUILTIN_TEXTRMUW:
13800 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
13801 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
13802 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
13803 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
13804 : CODE_FOR_iwmmxt_textrmw);
13806 arg0 = CALL_EXPR_ARG (exp, 0);
13807 arg1 = CALL_EXPR_ARG (exp, 1);
13808 op0 = expand_normal (arg0);
13809 op1 = expand_normal (arg1);
13810 tmode = insn_data[icode].operand[0].mode;
13811 mode0 = insn_data[icode].operand[1].mode;
13812 mode1 = insn_data[icode].operand[2].mode;
13814 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13815 op0 = copy_to_mode_reg (mode0, op0);
13816 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13818 /* @@@ better error message */
13819 error ("selector must be an immediate");
13820 return gen_reg_rtx (tmode);
13823 || GET_MODE (target) != tmode
13824 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13825 target = gen_reg_rtx (tmode);
13826 pat = GEN_FCN (icode) (target, op0, op1);
13832 case ARM_BUILTIN_TINSRB:
13833 case ARM_BUILTIN_TINSRH:
13834 case ARM_BUILTIN_TINSRW:
13835 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
13836 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
13837 : CODE_FOR_iwmmxt_tinsrw);
13838 arg0 = CALL_EXPR_ARG (exp, 0);
13839 arg1 = CALL_EXPR_ARG (exp, 1);
13840 arg2 = CALL_EXPR_ARG (exp, 2);
13841 op0 = expand_normal (arg0);
13842 op1 = expand_normal (arg1);
13843 op2 = expand_normal (arg2);
13844 tmode = insn_data[icode].operand[0].mode;
13845 mode0 = insn_data[icode].operand[1].mode;
13846 mode1 = insn_data[icode].operand[2].mode;
13847 mode2 = insn_data[icode].operand[3].mode;
13849 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13850 op0 = copy_to_mode_reg (mode0, op0);
13851 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13852 op1 = copy_to_mode_reg (mode1, op1);
13853 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13855 /* @@@ better error message */
13856 error ("selector must be an immediate");
13860 || GET_MODE (target) != tmode
13861 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13862 target = gen_reg_rtx (tmode);
13863 pat = GEN_FCN (icode) (target, op0, op1, op2);
13869 case ARM_BUILTIN_SETWCX:
13870 arg0 = CALL_EXPR_ARG (exp, 0);
13871 arg1 = CALL_EXPR_ARG (exp, 1);
13872 op0 = force_reg (SImode, expand_normal (arg0));
13873 op1 = expand_normal (arg1);
13874 emit_insn (gen_iwmmxt_tmcr (op1, op0));
13877 case ARM_BUILTIN_GETWCX:
13878 arg0 = CALL_EXPR_ARG (exp, 0);
13879 op0 = expand_normal (arg0);
13880 target = gen_reg_rtx (SImode);
13881 emit_insn (gen_iwmmxt_tmrc (target, op0));
13884 case ARM_BUILTIN_WSHUFH:
13885 icode = CODE_FOR_iwmmxt_wshufh;
13886 arg0 = CALL_EXPR_ARG (exp, 0);
13887 arg1 = CALL_EXPR_ARG (exp, 1);
13888 op0 = expand_normal (arg0);
13889 op1 = expand_normal (arg1);
13890 tmode = insn_data[icode].operand[0].mode;
13891 mode1 = insn_data[icode].operand[1].mode;
13892 mode2 = insn_data[icode].operand[2].mode;
13894 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
13895 op0 = copy_to_mode_reg (mode1, op0);
13896 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
13898 /* @@@ better error message */
13899 error ("mask must be an immediate");
13903 || GET_MODE (target) != tmode
13904 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13905 target = gen_reg_rtx (tmode);
13906 pat = GEN_FCN (icode) (target, op0, op1);
13912 case ARM_BUILTIN_WSADB:
13913 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
13914 case ARM_BUILTIN_WSADH:
13915 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
13916 case ARM_BUILTIN_WSADBZ:
13917 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
13918 case ARM_BUILTIN_WSADHZ:
13919 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
13921 /* Several three-argument builtins. */
13922 case ARM_BUILTIN_WMACS:
13923 case ARM_BUILTIN_WMACU:
13924 case ARM_BUILTIN_WALIGN:
13925 case ARM_BUILTIN_TMIA:
13926 case ARM_BUILTIN_TMIAPH:
13927 case ARM_BUILTIN_TMIATT:
13928 case ARM_BUILTIN_TMIATB:
13929 case ARM_BUILTIN_TMIABT:
13930 case ARM_BUILTIN_TMIABB:
13931 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
13932 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
13933 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
13934 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
13935 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
13936 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
13937 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
13938 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
13939 : CODE_FOR_iwmmxt_walign);
13940 arg0 = CALL_EXPR_ARG (exp, 0);
13941 arg1 = CALL_EXPR_ARG (exp, 1);
13942 arg2 = CALL_EXPR_ARG (exp, 2);
13943 op0 = expand_normal (arg0);
13944 op1 = expand_normal (arg1);
13945 op2 = expand_normal (arg2);
13946 tmode = insn_data[icode].operand[0].mode;
13947 mode0 = insn_data[icode].operand[1].mode;
13948 mode1 = insn_data[icode].operand[2].mode;
13949 mode2 = insn_data[icode].operand[3].mode;
13951 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13952 op0 = copy_to_mode_reg (mode0, op0);
13953 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13954 op1 = copy_to_mode_reg (mode1, op1);
13955 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13956 op2 = copy_to_mode_reg (mode2, op2);
13958 || GET_MODE (target) != tmode
13959 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13960 target = gen_reg_rtx (tmode);
13961 pat = GEN_FCN (icode) (target, op0, op1, op2);
13967 case ARM_BUILTIN_WZERO:
13968 target = gen_reg_rtx (DImode);
13969 emit_insn (gen_iwmmxt_clrdi (target));
13972 case ARM_BUILTIN_THREAD_POINTER:
13973 return arm_load_tp (target);
13979 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13980 if (d->code == (const enum arm_builtins) fcode)
13981 return arm_expand_binop_builtin (d->icode, exp, target);
13983 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13984 if (d->code == (const enum arm_builtins) fcode)
13985 return arm_expand_unop_builtin (d->icode, exp, target, 0);
13987 /* @@@ Should really do something sensible here. */
13991 /* Return the number (counting from 0) of
13992 the least significant set bit in MASK. */
13995 number_of_first_bit_set (unsigned mask)
14000 (mask & (1 << bit)) == 0;
14007 /* Emit code to push or pop registers to or from the stack. F is the
14008 assembly file. MASK is the registers to push or pop. PUSH is
14009 nonzero if we should push, and zero if we should pop. For debugging
14010 output, if pushing, adjust CFA_OFFSET by the amount of space added
14011 to the stack. REAL_REGS should have the same number of bits set as
14012 MASK, and will be used instead (in the same order) to describe which
14013 registers were saved - this is used to mark the save slots when we
14014 push high registers after moving them to low registers. */
14016 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
14017 unsigned long real_regs)
14020 int lo_mask = mask & 0xFF;
14021 int pushed_words = 0;
14025 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
14027 /* Special case. Do not generate a POP PC statement here, do it in
14029 thumb_exit (f, -1);
14033 if (ARM_EABI_UNWIND_TABLES && push)
14035 fprintf (f, "\t.save\t{");
14036 for (regno = 0; regno < 15; regno++)
14038 if (real_regs & (1 << regno))
14040 if (real_regs & ((1 << regno) -1))
14042 asm_fprintf (f, "%r", regno);
14045 fprintf (f, "}\n");
14048 fprintf (f, "\t%s\t{", push ? "push" : "pop");
14050 /* Look at the low registers first. */
14051 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
14055 asm_fprintf (f, "%r", regno);
14057 if ((lo_mask & ~1) != 0)
14064 if (push && (mask & (1 << LR_REGNUM)))
14066 /* Catch pushing the LR. */
14070 asm_fprintf (f, "%r", LR_REGNUM);
14074 else if (!push && (mask & (1 << PC_REGNUM)))
14076 /* Catch popping the PC. */
14077 if (TARGET_INTERWORK || TARGET_BACKTRACE
14078 || current_function_calls_eh_return)
14080 /* The PC is never poped directly, instead
14081 it is popped into r3 and then BX is used. */
14082 fprintf (f, "}\n");
14084 thumb_exit (f, -1);
14093 asm_fprintf (f, "%r", PC_REGNUM);
14097 fprintf (f, "}\n");
14099 if (push && pushed_words && dwarf2out_do_frame ())
14101 char *l = dwarf2out_cfi_label ();
14102 int pushed_mask = real_regs;
14104 *cfa_offset += pushed_words * 4;
14105 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
14108 pushed_mask = real_regs;
14109 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
14111 if (pushed_mask & 1)
14112 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
14117 /* Generate code to return from a thumb function.
14118 If 'reg_containing_return_addr' is -1, then the return address is
14119 actually on the stack, at the stack pointer. */
14121 thumb_exit (FILE *f, int reg_containing_return_addr)
14123 unsigned regs_available_for_popping;
14124 unsigned regs_to_pop;
14126 unsigned available;
14130 int restore_a4 = FALSE;
14132 /* Compute the registers we need to pop. */
14136 if (reg_containing_return_addr == -1)
14138 regs_to_pop |= 1 << LR_REGNUM;
14142 if (TARGET_BACKTRACE)
14144 /* Restore the (ARM) frame pointer and stack pointer. */
14145 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
14149 /* If there is nothing to pop then just emit the BX instruction and
14151 if (pops_needed == 0)
14153 if (current_function_calls_eh_return)
14154 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14156 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14159 /* Otherwise if we are not supporting interworking and we have not created
14160 a backtrace structure and the function was not entered in ARM mode then
14161 just pop the return address straight into the PC. */
14162 else if (!TARGET_INTERWORK
14163 && !TARGET_BACKTRACE
14164 && !is_called_in_ARM_mode (current_function_decl)
14165 && !current_function_calls_eh_return)
14167 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
14171 /* Find out how many of the (return) argument registers we can corrupt. */
14172 regs_available_for_popping = 0;
14174 /* If returning via __builtin_eh_return, the bottom three registers
14175 all contain information needed for the return. */
14176 if (current_function_calls_eh_return)
14180 /* If we can deduce the registers used from the function's
14181 return value. This is more reliable that examining
14182 df_regs_ever_live_p () because that will be set if the register is
14183 ever used in the function, not just if the register is used
14184 to hold a return value. */
14186 if (current_function_return_rtx != 0)
14187 mode = GET_MODE (current_function_return_rtx);
14189 mode = DECL_MODE (DECL_RESULT (current_function_decl));
14191 size = GET_MODE_SIZE (mode);
14195 /* In a void function we can use any argument register.
14196 In a function that returns a structure on the stack
14197 we can use the second and third argument registers. */
14198 if (mode == VOIDmode)
14199 regs_available_for_popping =
14200 (1 << ARG_REGISTER (1))
14201 | (1 << ARG_REGISTER (2))
14202 | (1 << ARG_REGISTER (3));
14204 regs_available_for_popping =
14205 (1 << ARG_REGISTER (2))
14206 | (1 << ARG_REGISTER (3));
14208 else if (size <= 4)
14209 regs_available_for_popping =
14210 (1 << ARG_REGISTER (2))
14211 | (1 << ARG_REGISTER (3));
14212 else if (size <= 8)
14213 regs_available_for_popping =
14214 (1 << ARG_REGISTER (3));
14217 /* Match registers to be popped with registers into which we pop them. */
14218 for (available = regs_available_for_popping,
14219 required = regs_to_pop;
14220 required != 0 && available != 0;
14221 available &= ~(available & - available),
14222 required &= ~(required & - required))
14225 /* If we have any popping registers left over, remove them. */
14227 regs_available_for_popping &= ~available;
14229 /* Otherwise if we need another popping register we can use
14230 the fourth argument register. */
14231 else if (pops_needed)
14233 /* If we have not found any free argument registers and
14234 reg a4 contains the return address, we must move it. */
14235 if (regs_available_for_popping == 0
14236 && reg_containing_return_addr == LAST_ARG_REGNUM)
14238 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14239 reg_containing_return_addr = LR_REGNUM;
14241 else if (size > 12)
14243 /* Register a4 is being used to hold part of the return value,
14244 but we have dire need of a free, low register. */
14247 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
14250 if (reg_containing_return_addr != LAST_ARG_REGNUM)
14252 /* The fourth argument register is available. */
14253 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
14259 /* Pop as many registers as we can. */
14260 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14261 regs_available_for_popping);
14263 /* Process the registers we popped. */
14264 if (reg_containing_return_addr == -1)
14266 /* The return address was popped into the lowest numbered register. */
14267 regs_to_pop &= ~(1 << LR_REGNUM);
14269 reg_containing_return_addr =
14270 number_of_first_bit_set (regs_available_for_popping);
14272 /* Remove this register for the mask of available registers, so that
14273 the return address will not be corrupted by further pops. */
14274 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
14277 /* If we popped other registers then handle them here. */
14278 if (regs_available_for_popping)
14282 /* Work out which register currently contains the frame pointer. */
14283 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
14285 /* Move it into the correct place. */
14286 asm_fprintf (f, "\tmov\t%r, %r\n",
14287 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
14289 /* (Temporarily) remove it from the mask of popped registers. */
14290 regs_available_for_popping &= ~(1 << frame_pointer);
14291 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
14293 if (regs_available_for_popping)
14297 /* We popped the stack pointer as well,
14298 find the register that contains it. */
14299 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
14301 /* Move it into the stack register. */
14302 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
14304 /* At this point we have popped all necessary registers, so
14305 do not worry about restoring regs_available_for_popping
14306 to its correct value:
14308 assert (pops_needed == 0)
14309 assert (regs_available_for_popping == (1 << frame_pointer))
14310 assert (regs_to_pop == (1 << STACK_POINTER)) */
14314 /* Since we have just move the popped value into the frame
14315 pointer, the popping register is available for reuse, and
14316 we know that we still have the stack pointer left to pop. */
14317 regs_available_for_popping |= (1 << frame_pointer);
14321 /* If we still have registers left on the stack, but we no longer have
14322 any registers into which we can pop them, then we must move the return
14323 address into the link register and make available the register that
14325 if (regs_available_for_popping == 0 && pops_needed > 0)
14327 regs_available_for_popping |= 1 << reg_containing_return_addr;
14329 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
14330 reg_containing_return_addr);
14332 reg_containing_return_addr = LR_REGNUM;
14335 /* If we have registers left on the stack then pop some more.
14336 We know that at most we will want to pop FP and SP. */
14337 if (pops_needed > 0)
14342 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14343 regs_available_for_popping);
14345 /* We have popped either FP or SP.
14346 Move whichever one it is into the correct register. */
14347 popped_into = number_of_first_bit_set (regs_available_for_popping);
14348 move_to = number_of_first_bit_set (regs_to_pop);
14350 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
14352 regs_to_pop &= ~(1 << move_to);
14357 /* If we still have not popped everything then we must have only
14358 had one register available to us and we are now popping the SP. */
14359 if (pops_needed > 0)
14363 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14364 regs_available_for_popping);
14366 popped_into = number_of_first_bit_set (regs_available_for_popping);
14368 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
14370 assert (regs_to_pop == (1 << STACK_POINTER))
14371 assert (pops_needed == 1)
14375 /* If necessary restore the a4 register. */
14378 if (reg_containing_return_addr != LR_REGNUM)
14380 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14381 reg_containing_return_addr = LR_REGNUM;
14384 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
14387 if (current_function_calls_eh_return)
14388 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14390 /* Return to caller. */
14391 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14396 thumb1_final_prescan_insn (rtx insn)
14398 if (flag_print_asm_name)
14399 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
14400 INSN_ADDRESSES (INSN_UID (insn)));
14404 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
14406 unsigned HOST_WIDE_INT mask = 0xff;
14409 if (val == 0) /* XXX */
14412 for (i = 0; i < 25; i++)
14413 if ((val & (mask << i)) == val)
14419 /* Returns nonzero if the current function contains,
14420 or might contain a far jump. */
14422 thumb_far_jump_used_p (void)
14426 /* This test is only important for leaf functions. */
14427 /* assert (!leaf_function_p ()); */
14429 /* If we have already decided that far jumps may be used,
14430 do not bother checking again, and always return true even if
14431 it turns out that they are not being used. Once we have made
14432 the decision that far jumps are present (and that hence the link
14433 register will be pushed onto the stack) we cannot go back on it. */
14434 if (cfun->machine->far_jump_used)
14437 /* If this function is not being called from the prologue/epilogue
14438 generation code then it must be being called from the
14439 INITIAL_ELIMINATION_OFFSET macro. */
14440 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
14442 /* In this case we know that we are being asked about the elimination
14443 of the arg pointer register. If that register is not being used,
14444 then there are no arguments on the stack, and we do not have to
14445 worry that a far jump might force the prologue to push the link
14446 register, changing the stack offsets. In this case we can just
14447 return false, since the presence of far jumps in the function will
14448 not affect stack offsets.
14450 If the arg pointer is live (or if it was live, but has now been
14451 eliminated and so set to dead) then we do have to test to see if
14452 the function might contain a far jump. This test can lead to some
14453 false negatives, since before reload is completed, then length of
14454 branch instructions is not known, so gcc defaults to returning their
14455 longest length, which in turn sets the far jump attribute to true.
14457 A false negative will not result in bad code being generated, but it
14458 will result in a needless push and pop of the link register. We
14459 hope that this does not occur too often.
14461 If we need doubleword stack alignment this could affect the other
14462 elimination offsets so we can't risk getting it wrong. */
14463 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
14464 cfun->machine->arg_pointer_live = 1;
14465 else if (!cfun->machine->arg_pointer_live)
14469 /* Check to see if the function contains a branch
14470 insn with the far jump attribute set. */
14471 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14473 if (GET_CODE (insn) == JUMP_INSN
14474 /* Ignore tablejump patterns. */
14475 && GET_CODE (PATTERN (insn)) != ADDR_VEC
14476 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
14477 && get_attr_far_jump (insn) == FAR_JUMP_YES
14480 /* Record the fact that we have decided that
14481 the function does use far jumps. */
14482 cfun->machine->far_jump_used = 1;
14490 /* Return nonzero if FUNC must be entered in ARM mode. */
14492 is_called_in_ARM_mode (tree func)
14494 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
14496 /* Ignore the problem about functions whose address is taken. */
14497 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
14501 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
14507 /* The bits which aren't usefully expanded as rtl. */
14509 thumb_unexpanded_epilogue (void)
14512 unsigned long live_regs_mask = 0;
14513 int high_regs_pushed = 0;
14514 int had_to_push_lr;
14517 if (return_used_this_function)
14520 if (IS_NAKED (arm_current_func_type ()))
14523 live_regs_mask = thumb1_compute_save_reg_mask ();
14524 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14526 /* If we can deduce the registers used from the function's return value.
14527 This is more reliable that examining df_regs_ever_live_p () because that
14528 will be set if the register is ever used in the function, not just if
14529 the register is used to hold a return value. */
14530 size = arm_size_return_regs ();
14532 /* The prolog may have pushed some high registers to use as
14533 work registers. e.g. the testsuite file:
14534 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14535 compiles to produce:
14536 push {r4, r5, r6, r7, lr}
14540 as part of the prolog. We have to undo that pushing here. */
14542 if (high_regs_pushed)
14544 unsigned long mask = live_regs_mask & 0xff;
14547 /* The available low registers depend on the size of the value we are
14555 /* Oh dear! We have no low registers into which we can pop
14558 ("no low registers available for popping high registers");
14560 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
14561 if (live_regs_mask & (1 << next_hi_reg))
14564 while (high_regs_pushed)
14566 /* Find lo register(s) into which the high register(s) can
14568 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14570 if (mask & (1 << regno))
14571 high_regs_pushed--;
14572 if (high_regs_pushed == 0)
14576 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
14578 /* Pop the values into the low register(s). */
14579 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
14581 /* Move the value(s) into the high registers. */
14582 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14584 if (mask & (1 << regno))
14586 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
14589 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
14590 if (live_regs_mask & (1 << next_hi_reg))
14595 live_regs_mask &= ~0x0f00;
14598 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
14599 live_regs_mask &= 0xff;
14601 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
14603 /* Pop the return address into the PC. */
14604 if (had_to_push_lr)
14605 live_regs_mask |= 1 << PC_REGNUM;
14607 /* Either no argument registers were pushed or a backtrace
14608 structure was created which includes an adjusted stack
14609 pointer, so just pop everything. */
14610 if (live_regs_mask)
14611 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14614 /* We have either just popped the return address into the
14615 PC or it is was kept in LR for the entire function. */
14616 if (!had_to_push_lr)
14617 thumb_exit (asm_out_file, LR_REGNUM);
14621 /* Pop everything but the return address. */
14622 if (live_regs_mask)
14623 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14626 if (had_to_push_lr)
14630 /* We have no free low regs, so save one. */
14631 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
14635 /* Get the return address into a temporary register. */
14636 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
14637 1 << LAST_ARG_REGNUM);
14641 /* Move the return address to lr. */
14642 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
14644 /* Restore the low register. */
14645 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
14650 regno = LAST_ARG_REGNUM;
14655 /* Remove the argument registers that were pushed onto the stack. */
14656 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
14657 SP_REGNUM, SP_REGNUM,
14658 current_function_pretend_args_size);
14660 thumb_exit (asm_out_file, regno);
14666 /* Functions to save and restore machine-specific function data. */
14667 static struct machine_function *
14668 arm_init_machine_status (void)
14670 struct machine_function *machine;
14671 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
14673 #if ARM_FT_UNKNOWN != 0
14674 machine->func_type = ARM_FT_UNKNOWN;
14679 /* Return an RTX indicating where the return address to the
14680 calling function can be found. */
14682 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
14687 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
14690 /* Do anything needed before RTL is emitted for each function. */
14692 arm_init_expanders (void)
14694 /* Arrange to initialize and mark the machine per-function status. */
14695 init_machine_status = arm_init_machine_status;
14697 /* This is to stop the combine pass optimizing away the alignment
14698 adjustment of va_arg. */
14699 /* ??? It is claimed that this should not be necessary. */
14701 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
14705 /* Like arm_compute_initial_elimination offset. Simpler because there
14706 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14707 to point at the base of the local variables after static stack
14708 space for a function has been allocated. */
14711 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
14713 arm_stack_offsets *offsets;
14715 offsets = arm_get_frame_offsets ();
14719 case ARG_POINTER_REGNUM:
14722 case STACK_POINTER_REGNUM:
14723 return offsets->outgoing_args - offsets->saved_args;
14725 case FRAME_POINTER_REGNUM:
14726 return offsets->soft_frame - offsets->saved_args;
14728 case ARM_HARD_FRAME_POINTER_REGNUM:
14729 return offsets->saved_regs - offsets->saved_args;
14731 case THUMB_HARD_FRAME_POINTER_REGNUM:
14732 return offsets->locals_base - offsets->saved_args;
14735 gcc_unreachable ();
14739 case FRAME_POINTER_REGNUM:
14742 case STACK_POINTER_REGNUM:
14743 return offsets->outgoing_args - offsets->soft_frame;
14745 case ARM_HARD_FRAME_POINTER_REGNUM:
14746 return offsets->saved_regs - offsets->soft_frame;
14748 case THUMB_HARD_FRAME_POINTER_REGNUM:
14749 return offsets->locals_base - offsets->soft_frame;
14752 gcc_unreachable ();
14757 gcc_unreachable ();
14761 /* Generate the rest of a function's prologue. */
14763 thumb1_expand_prologue (void)
14767 HOST_WIDE_INT amount;
14768 arm_stack_offsets *offsets;
14769 unsigned long func_type;
14771 unsigned long live_regs_mask;
14773 func_type = arm_current_func_type ();
14775 /* Naked functions don't have prologues. */
14776 if (IS_NAKED (func_type))
14779 if (IS_INTERRUPT (func_type))
14781 error ("interrupt Service Routines cannot be coded in Thumb mode");
14785 live_regs_mask = thumb1_compute_save_reg_mask ();
14786 /* Load the pic register before setting the frame pointer,
14787 so we can use r7 as a temporary work register. */
14788 if (flag_pic && arm_pic_register != INVALID_REGNUM)
14789 arm_load_pic_register (live_regs_mask);
14791 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
14792 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
14793 stack_pointer_rtx);
14795 offsets = arm_get_frame_offsets ();
14796 amount = offsets->outgoing_args - offsets->saved_regs;
14801 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14802 GEN_INT (- amount)));
14803 RTX_FRAME_RELATED_P (insn) = 1;
14809 /* The stack decrement is too big for an immediate value in a single
14810 insn. In theory we could issue multiple subtracts, but after
14811 three of them it becomes more space efficient to place the full
14812 value in the constant pool and load into a register. (Also the
14813 ARM debugger really likes to see only one stack decrement per
14814 function). So instead we look for a scratch register into which
14815 we can load the decrement, and then we subtract this from the
14816 stack pointer. Unfortunately on the thumb the only available
14817 scratch registers are the argument registers, and we cannot use
14818 these as they may hold arguments to the function. Instead we
14819 attempt to locate a call preserved register which is used by this
14820 function. If we can find one, then we know that it will have
14821 been pushed at the start of the prologue and so we can corrupt
14823 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
14824 if (live_regs_mask & (1 << regno)
14825 && !(frame_pointer_needed
14826 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
14829 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
14831 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
14833 /* Choose an arbitrary, non-argument low register. */
14834 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
14836 /* Save it by copying it into a high, scratch register. */
14837 emit_insn (gen_movsi (spare, reg));
14838 /* Add a USE to stop propagate_one_insn() from barfing. */
14839 emit_insn (gen_prologue_use (spare));
14841 /* Decrement the stack. */
14842 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14843 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14844 stack_pointer_rtx, reg));
14845 RTX_FRAME_RELATED_P (insn) = 1;
14846 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14847 plus_constant (stack_pointer_rtx,
14849 RTX_FRAME_RELATED_P (dwarf) = 1;
14851 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14854 /* Restore the low register's original value. */
14855 emit_insn (gen_movsi (reg, spare));
14857 /* Emit a USE of the restored scratch register, so that flow
14858 analysis will not consider the restore redundant. The
14859 register won't be used again in this function and isn't
14860 restored by the epilogue. */
14861 emit_insn (gen_prologue_use (reg));
14865 reg = gen_rtx_REG (SImode, regno);
14867 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14869 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14870 stack_pointer_rtx, reg));
14871 RTX_FRAME_RELATED_P (insn) = 1;
14872 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14873 plus_constant (stack_pointer_rtx,
14875 RTX_FRAME_RELATED_P (dwarf) = 1;
14877 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14883 if (frame_pointer_needed)
14884 thumb_set_frame_pointer (offsets);
14886 /* If we are profiling, make sure no instructions are scheduled before
14887 the call to mcount. Similarly if the user has requested no
14888 scheduling in the prolog. Similarly if we want non-call exceptions
14889 using the EABI unwinder, to prevent faulting instructions from being
14890 swapped with a stack adjustment. */
14891 if (current_function_profile || !TARGET_SCHED_PROLOG
14892 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
14893 emit_insn (gen_blockage ());
14895 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
14896 if (live_regs_mask & 0xff)
14897 cfun->machine->lr_save_eliminated = 0;
14902 thumb1_expand_epilogue (void)
14904 HOST_WIDE_INT amount;
14905 arm_stack_offsets *offsets;
14908 /* Naked functions don't have prologues. */
14909 if (IS_NAKED (arm_current_func_type ()))
14912 offsets = arm_get_frame_offsets ();
14913 amount = offsets->outgoing_args - offsets->saved_regs;
14915 if (frame_pointer_needed)
14917 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
14918 amount = offsets->locals_base - offsets->saved_regs;
14921 gcc_assert (amount >= 0);
14925 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14926 GEN_INT (amount)));
14929 /* r3 is always free in the epilogue. */
14930 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
14932 emit_insn (gen_movsi (reg, GEN_INT (amount)));
14933 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
14937 /* Emit a USE (stack_pointer_rtx), so that
14938 the stack adjustment will not be deleted. */
14939 emit_insn (gen_prologue_use (stack_pointer_rtx));
14941 if (current_function_profile || !TARGET_SCHED_PROLOG)
14942 emit_insn (gen_blockage ());
14944 /* Emit a clobber for each insn that will be restored in the epilogue,
14945 so that flow2 will get register lifetimes correct. */
14946 for (regno = 0; regno < 13; regno++)
14947 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
14948 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
14950 if (! df_regs_ever_live_p (LR_REGNUM))
14951 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
14955 thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14957 unsigned long live_regs_mask = 0;
14958 unsigned long l_mask;
14959 unsigned high_regs_pushed = 0;
14960 int cfa_offset = 0;
14963 if (IS_NAKED (arm_current_func_type ()))
14966 if (is_called_in_ARM_mode (current_function_decl))
14970 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
14971 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
14973 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14975 /* Generate code sequence to switch us into Thumb mode. */
14976 /* The .code 32 directive has already been emitted by
14977 ASM_DECLARE_FUNCTION_NAME. */
14978 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
14979 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
14981 /* Generate a label, so that the debugger will notice the
14982 change in instruction sets. This label is also used by
14983 the assembler to bypass the ARM code when this function
14984 is called from a Thumb encoded function elsewhere in the
14985 same file. Hence the definition of STUB_NAME here must
14986 agree with the definition in gas/config/tc-arm.c. */
14988 #define STUB_NAME ".real_start_of"
14990 fprintf (f, "\t.code\t16\n");
14992 if (arm_dllexport_name_p (name))
14993 name = arm_strip_name_encoding (name);
14995 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
14996 fprintf (f, "\t.thumb_func\n");
14997 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
15000 if (current_function_pretend_args_size)
15002 /* Output unwind directive for the stack adjustment. */
15003 if (ARM_EABI_UNWIND_TABLES)
15004 fprintf (f, "\t.pad #%d\n",
15005 current_function_pretend_args_size);
15007 if (cfun->machine->uses_anonymous_args)
15011 fprintf (f, "\tpush\t{");
15013 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
15015 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
15016 regno <= LAST_ARG_REGNUM;
15018 asm_fprintf (f, "%r%s", regno,
15019 regno == LAST_ARG_REGNUM ? "" : ", ");
15021 fprintf (f, "}\n");
15024 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
15025 SP_REGNUM, SP_REGNUM,
15026 current_function_pretend_args_size);
15028 /* We don't need to record the stores for unwinding (would it
15029 help the debugger any if we did?), but record the change in
15030 the stack pointer. */
15031 if (dwarf2out_do_frame ())
15033 char *l = dwarf2out_cfi_label ();
15035 cfa_offset = cfa_offset + current_function_pretend_args_size;
15036 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
15040 /* Get the registers we are going to push. */
15041 live_regs_mask = thumb1_compute_save_reg_mask ();
15042 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
15043 l_mask = live_regs_mask & 0x40ff;
15044 /* Then count how many other high registers will need to be pushed. */
15045 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
15047 if (TARGET_BACKTRACE)
15050 unsigned work_register;
15052 /* We have been asked to create a stack backtrace structure.
15053 The code looks like this:
15057 0 sub SP, #16 Reserve space for 4 registers.
15058 2 push {R7} Push low registers.
15059 4 add R7, SP, #20 Get the stack pointer before the push.
15060 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
15061 8 mov R7, PC Get hold of the start of this code plus 12.
15062 10 str R7, [SP, #16] Store it.
15063 12 mov R7, FP Get hold of the current frame pointer.
15064 14 str R7, [SP, #4] Store it.
15065 16 mov R7, LR Get hold of the current return address.
15066 18 str R7, [SP, #12] Store it.
15067 20 add R7, SP, #16 Point at the start of the backtrace structure.
15068 22 mov FP, R7 Put this value into the frame pointer. */
15070 work_register = thumb_find_work_register (live_regs_mask);
15072 if (ARM_EABI_UNWIND_TABLES)
15073 asm_fprintf (f, "\t.pad #16\n");
15076 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
15077 SP_REGNUM, SP_REGNUM);
15079 if (dwarf2out_do_frame ())
15081 char *l = dwarf2out_cfi_label ();
15083 cfa_offset = cfa_offset + 16;
15084 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
15089 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
15090 offset = bit_count (l_mask) * UNITS_PER_WORD;
15095 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
15096 offset + 16 + current_function_pretend_args_size);
15098 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15101 /* Make sure that the instruction fetching the PC is in the right place
15102 to calculate "start of backtrace creation code + 12". */
15105 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
15106 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15108 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
15109 ARM_HARD_FRAME_POINTER_REGNUM);
15110 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15115 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
15116 ARM_HARD_FRAME_POINTER_REGNUM);
15117 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15119 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
15120 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15124 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
15125 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15127 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
15129 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
15130 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
15132 /* Optimization: If we are not pushing any low registers but we are going
15133 to push some high registers then delay our first push. This will just
15134 be a push of LR and we can combine it with the push of the first high
15136 else if ((l_mask & 0xff) != 0
15137 || (high_regs_pushed == 0 && l_mask))
15138 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
15140 if (high_regs_pushed)
15142 unsigned pushable_regs;
15143 unsigned next_hi_reg;
15145 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
15146 if (live_regs_mask & (1 << next_hi_reg))
15149 pushable_regs = l_mask & 0xff;
15151 if (pushable_regs == 0)
15152 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
15154 while (high_regs_pushed > 0)
15156 unsigned long real_regs_mask = 0;
15158 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
15160 if (pushable_regs & (1 << regno))
15162 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
15164 high_regs_pushed --;
15165 real_regs_mask |= (1 << next_hi_reg);
15167 if (high_regs_pushed)
15169 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
15171 if (live_regs_mask & (1 << next_hi_reg))
15176 pushable_regs &= ~((1 << regno) - 1);
15182 /* If we had to find a work register and we have not yet
15183 saved the LR then add it to the list of regs to push. */
15184 if (l_mask == (1 << LR_REGNUM))
15186 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
15188 real_regs_mask | (1 << LR_REGNUM));
15192 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
15197 /* Handle the case of a double word load into a low register from
15198 a computed memory address. The computed address may involve a
15199 register which is overwritten by the load. */
15201 thumb_load_double_from_address (rtx *operands)
15209 gcc_assert (GET_CODE (operands[0]) == REG);
15210 gcc_assert (GET_CODE (operands[1]) == MEM);
15212 /* Get the memory address. */
15213 addr = XEXP (operands[1], 0);
15215 /* Work out how the memory address is computed. */
15216 switch (GET_CODE (addr))
15219 operands[2] = adjust_address (operands[1], SImode, 4);
15221 if (REGNO (operands[0]) == REGNO (addr))
15223 output_asm_insn ("ldr\t%H0, %2", operands);
15224 output_asm_insn ("ldr\t%0, %1", operands);
15228 output_asm_insn ("ldr\t%0, %1", operands);
15229 output_asm_insn ("ldr\t%H0, %2", operands);
15234 /* Compute <address> + 4 for the high order load. */
15235 operands[2] = adjust_address (operands[1], SImode, 4);
15237 output_asm_insn ("ldr\t%0, %1", operands);
15238 output_asm_insn ("ldr\t%H0, %2", operands);
15242 arg1 = XEXP (addr, 0);
15243 arg2 = XEXP (addr, 1);
15245 if (CONSTANT_P (arg1))
15246 base = arg2, offset = arg1;
15248 base = arg1, offset = arg2;
15250 gcc_assert (GET_CODE (base) == REG);
15252 /* Catch the case of <address> = <reg> + <reg> */
15253 if (GET_CODE (offset) == REG)
15255 int reg_offset = REGNO (offset);
15256 int reg_base = REGNO (base);
15257 int reg_dest = REGNO (operands[0]);
15259 /* Add the base and offset registers together into the
15260 higher destination register. */
15261 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
15262 reg_dest + 1, reg_base, reg_offset);
15264 /* Load the lower destination register from the address in
15265 the higher destination register. */
15266 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
15267 reg_dest, reg_dest + 1);
15269 /* Load the higher destination register from its own address
15271 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
15272 reg_dest + 1, reg_dest + 1);
15276 /* Compute <address> + 4 for the high order load. */
15277 operands[2] = adjust_address (operands[1], SImode, 4);
15279 /* If the computed address is held in the low order register
15280 then load the high order register first, otherwise always
15281 load the low order register first. */
15282 if (REGNO (operands[0]) == REGNO (base))
15284 output_asm_insn ("ldr\t%H0, %2", operands);
15285 output_asm_insn ("ldr\t%0, %1", operands);
15289 output_asm_insn ("ldr\t%0, %1", operands);
15290 output_asm_insn ("ldr\t%H0, %2", operands);
15296 /* With no registers to worry about we can just load the value
15298 operands[2] = adjust_address (operands[1], SImode, 4);
15300 output_asm_insn ("ldr\t%H0, %2", operands);
15301 output_asm_insn ("ldr\t%0, %1", operands);
15305 gcc_unreachable ();
15312 thumb_output_move_mem_multiple (int n, rtx *operands)
15319 if (REGNO (operands[4]) > REGNO (operands[5]))
15322 operands[4] = operands[5];
15325 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
15326 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
15330 if (REGNO (operands[4]) > REGNO (operands[5]))
15333 operands[4] = operands[5];
15336 if (REGNO (operands[5]) > REGNO (operands[6]))
15339 operands[5] = operands[6];
15342 if (REGNO (operands[4]) > REGNO (operands[5]))
15345 operands[4] = operands[5];
15349 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
15350 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
15354 gcc_unreachable ();
15360 /* Output a call-via instruction for thumb state. */
15362 thumb_call_via_reg (rtx reg)
15364 int regno = REGNO (reg);
15367 gcc_assert (regno < LR_REGNUM);
15369 /* If we are in the normal text section we can use a single instance
15370 per compilation unit. If we are doing function sections, then we need
15371 an entry per section, since we can't rely on reachability. */
15372 if (in_section == text_section)
15374 thumb_call_reg_needed = 1;
15376 if (thumb_call_via_label[regno] == NULL)
15377 thumb_call_via_label[regno] = gen_label_rtx ();
15378 labelp = thumb_call_via_label + regno;
15382 if (cfun->machine->call_via[regno] == NULL)
15383 cfun->machine->call_via[regno] = gen_label_rtx ();
15384 labelp = cfun->machine->call_via + regno;
15387 output_asm_insn ("bl\t%a0", labelp);
15391 /* Routines for generating rtl. */
15393 thumb_expand_movmemqi (rtx *operands)
15395 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
15396 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
15397 HOST_WIDE_INT len = INTVAL (operands[2]);
15398 HOST_WIDE_INT offset = 0;
15402 emit_insn (gen_movmem12b (out, in, out, in));
15408 emit_insn (gen_movmem8b (out, in, out, in));
15414 rtx reg = gen_reg_rtx (SImode);
15415 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
15416 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
15423 rtx reg = gen_reg_rtx (HImode);
15424 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
15425 plus_constant (in, offset))));
15426 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
15434 rtx reg = gen_reg_rtx (QImode);
15435 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
15436 plus_constant (in, offset))));
15437 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
15443 thumb_reload_out_hi (rtx *operands)
15445 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
15448 /* Handle reading a half-word from memory during reload. */
15450 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
15452 gcc_unreachable ();
15455 /* Return the length of a function name prefix
15456 that starts with the character 'c'. */
15458 arm_get_strip_length (int c)
15462 ARM_NAME_ENCODING_LENGTHS
15467 /* Return a pointer to a function's name with any
15468 and all prefix encodings stripped from it. */
15470 arm_strip_name_encoding (const char *name)
15474 while ((skip = arm_get_strip_length (* name)))
15480 /* If there is a '*' anywhere in the name's prefix, then
15481 emit the stripped name verbatim, otherwise prepend an
15482 underscore if leading underscores are being used. */
15484 arm_asm_output_labelref (FILE *stream, const char *name)
15489 while ((skip = arm_get_strip_length (* name)))
15491 verbatim |= (*name == '*');
15496 fputs (name, stream);
15498 asm_fprintf (stream, "%U%s", name);
15502 arm_file_start (void)
15506 if (TARGET_UNIFIED_ASM)
15507 asm_fprintf (asm_out_file, "\t.syntax unified\n");
15511 const char *fpu_name;
15512 if (arm_select[0].string)
15513 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
15514 else if (arm_select[1].string)
15515 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
15517 asm_fprintf (asm_out_file, "\t.cpu %s\n",
15518 all_cores[arm_default_cpu].name);
15520 if (TARGET_SOFT_FLOAT)
15523 fpu_name = "softvfp";
15525 fpu_name = "softfpa";
15529 int set_float_abi_attributes = 0;
15530 switch (arm_fpu_arch)
15535 case FPUTYPE_FPA_EMU2:
15538 case FPUTYPE_FPA_EMU3:
15541 case FPUTYPE_MAVERICK:
15542 fpu_name = "maverick";
15546 set_float_abi_attributes = 1;
15550 set_float_abi_attributes = 1;
15555 if (set_float_abi_attributes)
15557 if (TARGET_HARD_FLOAT)
15558 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
15559 if (TARGET_HARD_FLOAT_ABI)
15560 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
15563 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
15565 /* Some of these attributes only apply when the corresponding features
15566 are used. However we don't have any easy way of figuring this out.
15567 Conservatively record the setting that would have been used. */
15569 /* Tag_ABI_PCS_wchar_t. */
15570 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
15571 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
15573 /* Tag_ABI_FP_rounding. */
15574 if (flag_rounding_math)
15575 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
15576 if (!flag_unsafe_math_optimizations)
15578 /* Tag_ABI_FP_denomal. */
15579 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
15580 /* Tag_ABI_FP_exceptions. */
15581 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
15583 /* Tag_ABI_FP_user_exceptions. */
15584 if (flag_signaling_nans)
15585 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
15586 /* Tag_ABI_FP_number_model. */
15587 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
15588 flag_finite_math_only ? 1 : 3);
15590 /* Tag_ABI_align8_needed. */
15591 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
15592 /* Tag_ABI_align8_preserved. */
15593 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
15594 /* Tag_ABI_enum_size. */
15595 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
15596 flag_short_enums ? 1 : 2);
15598 /* Tag_ABI_optimization_goals. */
15601 else if (optimize >= 2)
15607 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
15609 default_file_start();
15613 arm_file_end (void)
15617 if (NEED_INDICATE_EXEC_STACK)
15618 /* Add .note.GNU-stack. */
15619 file_end_indicate_exec_stack ();
15621 if (! thumb_call_reg_needed)
15624 switch_to_section (text_section);
15625 asm_fprintf (asm_out_file, "\t.code 16\n");
15626 ASM_OUTPUT_ALIGN (asm_out_file, 1);
15628 for (regno = 0; regno < LR_REGNUM; regno++)
15630 rtx label = thumb_call_via_label[regno];
15634 targetm.asm_out.internal_label (asm_out_file, "L",
15635 CODE_LABEL_NUMBER (label));
15636 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
15643 #ifdef AOF_ASSEMBLER
15644 /* Special functions only needed when producing AOF syntax assembler. */
15648 struct pic_chain * next;
15649 const char * symname;
15652 static struct pic_chain * aof_pic_chain = NULL;
15655 aof_pic_entry (rtx x)
15657 struct pic_chain ** chainp;
15660 if (aof_pic_label == NULL_RTX)
15662 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
15665 for (offset = 0, chainp = &aof_pic_chain; *chainp;
15666 offset += 4, chainp = &(*chainp)->next)
15667 if ((*chainp)->symname == XSTR (x, 0))
15668 return plus_constant (aof_pic_label, offset);
15670 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
15671 (*chainp)->next = NULL;
15672 (*chainp)->symname = XSTR (x, 0);
15673 return plus_constant (aof_pic_label, offset);
15677 aof_dump_pic_table (FILE *f)
15679 struct pic_chain * chain;
15681 if (aof_pic_chain == NULL)
15684 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
15685 PIC_OFFSET_TABLE_REGNUM,
15686 PIC_OFFSET_TABLE_REGNUM);
15687 fputs ("|x$adcons|\n", f);
15689 for (chain = aof_pic_chain; chain; chain = chain->next)
15691 fputs ("\tDCD\t", f);
15692 assemble_name (f, chain->symname);
15697 int arm_text_section_count = 1;
15699 /* A get_unnamed_section callback for switching to the text section. */
15702 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15704 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
15705 arm_text_section_count++);
15707 fprintf (asm_out_file, ", PIC, REENTRANT");
15708 fprintf (asm_out_file, "\n");
15711 static int arm_data_section_count = 1;
15713 /* A get_unnamed_section callback for switching to the data section. */
15716 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15718 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
15719 arm_data_section_count++);
15722 /* Implement TARGET_ASM_INIT_SECTIONS.
15724 AOF Assembler syntax is a nightmare when it comes to areas, since once
15725 we change from one area to another, we can't go back again. Instead,
15726 we must create a new area with the same attributes and add the new output
15727 to that. Unfortunately, there is nothing we can do here to guarantee that
15728 two areas with the same attributes will be linked adjacently in the
15729 resulting executable, so we have to be careful not to do pc-relative
15730 addressing across such boundaries. */
15733 aof_asm_init_sections (void)
15735 text_section = get_unnamed_section (SECTION_CODE,
15736 aof_output_text_section_asm_op, NULL);
15737 data_section = get_unnamed_section (SECTION_WRITE,
15738 aof_output_data_section_asm_op, NULL);
15739 readonly_data_section = text_section;
15743 zero_init_section (void)
15745 static int zero_init_count = 1;
15747 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
15751 /* The AOF assembler is religiously strict about declarations of
15752 imported and exported symbols, so that it is impossible to declare
15753 a function as imported near the beginning of the file, and then to
15754 export it later on. It is, however, possible to delay the decision
15755 until all the functions in the file have been compiled. To get
15756 around this, we maintain a list of the imports and exports, and
15757 delete from it any that are subsequently defined. At the end of
15758 compilation we spit the remainder of the list out before the END
15763 struct import * next;
15767 static struct import * imports_list = NULL;
15770 aof_add_import (const char *name)
15772 struct import * new;
15774 for (new = imports_list; new; new = new->next)
15775 if (new->name == name)
15778 new = (struct import *) xmalloc (sizeof (struct import));
15779 new->next = imports_list;
15780 imports_list = new;
15785 aof_delete_import (const char *name)
15787 struct import ** old;
15789 for (old = &imports_list; *old; old = & (*old)->next)
15791 if ((*old)->name == name)
15793 *old = (*old)->next;
15799 int arm_main_function = 0;
15802 aof_dump_imports (FILE *f)
15804 /* The AOF assembler needs this to cause the startup code to be extracted
15805 from the library. Brining in __main causes the whole thing to work
15807 if (arm_main_function)
15809 switch_to_section (text_section);
15810 fputs ("\tIMPORT __main\n", f);
15811 fputs ("\tDCD __main\n", f);
15814 /* Now dump the remaining imports. */
15815 while (imports_list)
15817 fprintf (f, "\tIMPORT\t");
15818 assemble_name (f, imports_list->name);
15820 imports_list = imports_list->next;
15825 aof_globalize_label (FILE *stream, const char *name)
15827 default_globalize_label (stream, name);
15828 if (! strcmp (name, "main"))
15829 arm_main_function = 1;
15833 aof_file_start (void)
15835 fputs ("__r0\tRN\t0\n", asm_out_file);
15836 fputs ("__a1\tRN\t0\n", asm_out_file);
15837 fputs ("__a2\tRN\t1\n", asm_out_file);
15838 fputs ("__a3\tRN\t2\n", asm_out_file);
15839 fputs ("__a4\tRN\t3\n", asm_out_file);
15840 fputs ("__v1\tRN\t4\n", asm_out_file);
15841 fputs ("__v2\tRN\t5\n", asm_out_file);
15842 fputs ("__v3\tRN\t6\n", asm_out_file);
15843 fputs ("__v4\tRN\t7\n", asm_out_file);
15844 fputs ("__v5\tRN\t8\n", asm_out_file);
15845 fputs ("__v6\tRN\t9\n", asm_out_file);
15846 fputs ("__sl\tRN\t10\n", asm_out_file);
15847 fputs ("__fp\tRN\t11\n", asm_out_file);
15848 fputs ("__ip\tRN\t12\n", asm_out_file);
15849 fputs ("__sp\tRN\t13\n", asm_out_file);
15850 fputs ("__lr\tRN\t14\n", asm_out_file);
15851 fputs ("__pc\tRN\t15\n", asm_out_file);
15852 fputs ("__f0\tFN\t0\n", asm_out_file);
15853 fputs ("__f1\tFN\t1\n", asm_out_file);
15854 fputs ("__f2\tFN\t2\n", asm_out_file);
15855 fputs ("__f3\tFN\t3\n", asm_out_file);
15856 fputs ("__f4\tFN\t4\n", asm_out_file);
15857 fputs ("__f5\tFN\t5\n", asm_out_file);
15858 fputs ("__f6\tFN\t6\n", asm_out_file);
15859 fputs ("__f7\tFN\t7\n", asm_out_file);
15860 switch_to_section (text_section);
15864 aof_file_end (void)
15867 aof_dump_pic_table (asm_out_file);
15869 aof_dump_imports (asm_out_file);
15870 fputs ("\tEND\n", asm_out_file);
15872 #endif /* AOF_ASSEMBLER */
15875 /* Symbols in the text segment can be accessed without indirecting via the
15876 constant pool; it may take an extra binary operation, but this is still
15877 faster than indirecting via memory. Don't do this when not optimizing,
15878 since we won't be calculating al of the offsets necessary to do this
15882 arm_encode_section_info (tree decl, rtx rtl, int first)
15884 /* This doesn't work with AOF syntax, since the string table may be in
15885 a different AREA. */
15886 #ifndef AOF_ASSEMBLER
15887 if (optimize > 0 && TREE_CONSTANT (decl))
15888 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
15891 default_encode_section_info (decl, rtl, first);
15893 #endif /* !ARM_PE */
15896 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
15898 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
15899 && !strcmp (prefix, "L"))
15901 arm_ccfsm_state = 0;
15902 arm_target_insn = NULL;
15904 default_internal_label (stream, prefix, labelno);
15907 /* Output code to add DELTA to the first argument, and then jump
15908 to FUNCTION. Used for C++ multiple inheritance. */
15910 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
15911 HOST_WIDE_INT delta,
15912 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
15915 static int thunk_label = 0;
15918 int mi_delta = delta;
15919 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
15921 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
15924 mi_delta = - mi_delta;
15925 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15928 int labelno = thunk_label++;
15929 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
15930 fputs ("\tldr\tr12, ", file);
15931 assemble_name (file, label);
15932 fputc ('\n', file);
15935 /* If we are generating PIC, the ldr instruction below loads
15936 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15937 the address of the add + 8, so we have:
15939 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15942 Note that we have "+ 1" because some versions of GNU ld
15943 don't set the low bit of the result for R_ARM_REL32
15944 relocations against thumb function symbols. */
15945 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
15946 assemble_name (file, labelpc);
15947 fputs (":\n", file);
15948 fputs ("\tadd\tr12, pc, r12\n", file);
15951 /* TODO: Use movw/movt for large constants when available. */
15952 while (mi_delta != 0)
15954 if ((mi_delta & (3 << shift)) == 0)
15958 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
15959 mi_op, this_regno, this_regno,
15960 mi_delta & (0xff << shift));
15961 mi_delta &= ~(0xff << shift);
15967 fprintf (file, "\tbx\tr12\n");
15968 ASM_OUTPUT_ALIGN (file, 2);
15969 assemble_name (file, label);
15970 fputs (":\n", file);
15973 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15974 rtx tem = XEXP (DECL_RTL (function), 0);
15975 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
15976 tem = gen_rtx_MINUS (GET_MODE (tem),
15978 gen_rtx_SYMBOL_REF (Pmode,
15979 ggc_strdup (labelpc)));
15980 assemble_integer (tem, 4, BITS_PER_WORD, 1);
15983 /* Output ".word .LTHUNKn". */
15984 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
15988 fputs ("\tb\t", file);
15989 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
15990 if (NEED_PLT_RELOC)
15991 fputs ("(PLT)", file);
15992 fputc ('\n', file);
15997 arm_emit_vector_const (FILE *file, rtx x)
16000 const char * pattern;
16002 gcc_assert (GET_CODE (x) == CONST_VECTOR);
16004 switch (GET_MODE (x))
16006 case V2SImode: pattern = "%08x"; break;
16007 case V4HImode: pattern = "%04x"; break;
16008 case V8QImode: pattern = "%02x"; break;
16009 default: gcc_unreachable ();
16012 fprintf (file, "0x");
16013 for (i = CONST_VECTOR_NUNITS (x); i--;)
16017 element = CONST_VECTOR_ELT (x, i);
16018 fprintf (file, pattern, INTVAL (element));
16025 arm_output_load_gr (rtx *operands)
16032 if (GET_CODE (operands [1]) != MEM
16033 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
16034 || GET_CODE (reg = XEXP (sum, 0)) != REG
16035 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
16036 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
16037 return "wldrw%?\t%0, %1";
16039 /* Fix up an out-of-range load of a GR register. */
16040 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
16041 wcgr = operands[0];
16043 output_asm_insn ("ldr%?\t%0, %1", operands);
16045 operands[0] = wcgr;
16047 output_asm_insn ("tmcr%?\t%0, %1", operands);
16048 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
16053 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
16055 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
16056 named arg and all anonymous args onto the stack.
16057 XXX I know the prologue shouldn't be pushing registers, but it is faster
16061 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
16062 enum machine_mode mode ATTRIBUTE_UNUSED,
16063 tree type ATTRIBUTE_UNUSED,
16065 int second_time ATTRIBUTE_UNUSED)
16067 cfun->machine->uses_anonymous_args = 1;
16068 if (cum->nregs < NUM_ARG_REGS)
16069 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
16072 /* Return nonzero if the CONSUMER instruction (a store) does not need
16073 PRODUCER's value to calculate the address. */
16076 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
16078 rtx value = PATTERN (producer);
16079 rtx addr = PATTERN (consumer);
16081 if (GET_CODE (value) == COND_EXEC)
16082 value = COND_EXEC_CODE (value);
16083 if (GET_CODE (value) == PARALLEL)
16084 value = XVECEXP (value, 0, 0);
16085 value = XEXP (value, 0);
16086 if (GET_CODE (addr) == COND_EXEC)
16087 addr = COND_EXEC_CODE (addr);
16088 if (GET_CODE (addr) == PARALLEL)
16089 addr = XVECEXP (addr, 0, 0);
16090 addr = XEXP (addr, 0);
16092 return !reg_overlap_mentioned_p (value, addr);
16095 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
16096 have an early register shift value or amount dependency on the
16097 result of PRODUCER. */
16100 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
16102 rtx value = PATTERN (producer);
16103 rtx op = PATTERN (consumer);
16106 if (GET_CODE (value) == COND_EXEC)
16107 value = COND_EXEC_CODE (value);
16108 if (GET_CODE (value) == PARALLEL)
16109 value = XVECEXP (value, 0, 0);
16110 value = XEXP (value, 0);
16111 if (GET_CODE (op) == COND_EXEC)
16112 op = COND_EXEC_CODE (op);
16113 if (GET_CODE (op) == PARALLEL)
16114 op = XVECEXP (op, 0, 0);
16117 early_op = XEXP (op, 0);
16118 /* This is either an actual independent shift, or a shift applied to
16119 the first operand of another operation. We want the whole shift
16121 if (GET_CODE (early_op) == REG)
16124 return !reg_overlap_mentioned_p (value, early_op);
16127 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
16128 have an early register shift value dependency on the result of
16132 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
16134 rtx value = PATTERN (producer);
16135 rtx op = PATTERN (consumer);
16138 if (GET_CODE (value) == COND_EXEC)
16139 value = COND_EXEC_CODE (value);
16140 if (GET_CODE (value) == PARALLEL)
16141 value = XVECEXP (value, 0, 0);
16142 value = XEXP (value, 0);
16143 if (GET_CODE (op) == COND_EXEC)
16144 op = COND_EXEC_CODE (op);
16145 if (GET_CODE (op) == PARALLEL)
16146 op = XVECEXP (op, 0, 0);
16149 early_op = XEXP (op, 0);
16151 /* This is either an actual independent shift, or a shift applied to
16152 the first operand of another operation. We want the value being
16153 shifted, in either case. */
16154 if (GET_CODE (early_op) != REG)
16155 early_op = XEXP (early_op, 0);
16157 return !reg_overlap_mentioned_p (value, early_op);
16160 /* Return nonzero if the CONSUMER (a mul or mac op) does not
16161 have an early register mult dependency on the result of
16165 arm_no_early_mul_dep (rtx producer, rtx consumer)
16167 rtx value = PATTERN (producer);
16168 rtx op = PATTERN (consumer);
16170 if (GET_CODE (value) == COND_EXEC)
16171 value = COND_EXEC_CODE (value);
16172 if (GET_CODE (value) == PARALLEL)
16173 value = XVECEXP (value, 0, 0);
16174 value = XEXP (value, 0);
16175 if (GET_CODE (op) == COND_EXEC)
16176 op = COND_EXEC_CODE (op);
16177 if (GET_CODE (op) == PARALLEL)
16178 op = XVECEXP (op, 0, 0);
16181 return (GET_CODE (op) == PLUS
16182 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
16186 /* We can't rely on the caller doing the proper promotion when
16187 using APCS or ATPCS. */
16190 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
16192 return !TARGET_AAPCS_BASED;
16196 /* AAPCS based ABIs use short enums by default. */
16199 arm_default_short_enums (void)
16201 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
16205 /* AAPCS requires that anonymous bitfields affect structure alignment. */
16208 arm_align_anon_bitfield (void)
16210 return TARGET_AAPCS_BASED;
16214 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
16217 arm_cxx_guard_type (void)
16219 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
16223 /* The EABI says test the least significant bit of a guard variable. */
16226 arm_cxx_guard_mask_bit (void)
16228 return TARGET_AAPCS_BASED;
16232 /* The EABI specifies that all array cookies are 8 bytes long. */
16235 arm_get_cookie_size (tree type)
16239 if (!TARGET_AAPCS_BASED)
16240 return default_cxx_get_cookie_size (type);
16242 size = build_int_cst (sizetype, 8);
16247 /* The EABI says that array cookies should also contain the element size. */
16250 arm_cookie_has_size (void)
16252 return TARGET_AAPCS_BASED;
16256 /* The EABI says constructors and destructors should return a pointer to
16257 the object constructed/destroyed. */
16260 arm_cxx_cdtor_returns_this (void)
16262 return TARGET_AAPCS_BASED;
16265 /* The EABI says that an inline function may never be the key
16269 arm_cxx_key_method_may_be_inline (void)
16271 return !TARGET_AAPCS_BASED;
16275 arm_cxx_determine_class_data_visibility (tree decl)
16277 if (!TARGET_AAPCS_BASED)
16280 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
16281 is exported. However, on systems without dynamic vague linkage,
16282 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
16283 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
16284 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
16286 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
16287 DECL_VISIBILITY_SPECIFIED (decl) = 1;
16291 arm_cxx_class_data_always_comdat (void)
16293 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
16294 vague linkage if the class has no key function. */
16295 return !TARGET_AAPCS_BASED;
16299 /* The EABI says __aeabi_atexit should be used to register static
16303 arm_cxx_use_aeabi_atexit (void)
16305 return TARGET_AAPCS_BASED;
16310 arm_set_return_address (rtx source, rtx scratch)
16312 arm_stack_offsets *offsets;
16313 HOST_WIDE_INT delta;
16315 unsigned long saved_regs;
16317 saved_regs = arm_compute_save_reg_mask ();
16319 if ((saved_regs & (1 << LR_REGNUM)) == 0)
16320 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16323 if (frame_pointer_needed)
16324 addr = plus_constant(hard_frame_pointer_rtx, -4);
16327 /* LR will be the first saved register. */
16328 offsets = arm_get_frame_offsets ();
16329 delta = offsets->outgoing_args - (offsets->frame + 4);
16334 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
16335 GEN_INT (delta & ~4095)));
16340 addr = stack_pointer_rtx;
16342 addr = plus_constant (addr, delta);
16344 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16350 thumb_set_return_address (rtx source, rtx scratch)
16352 arm_stack_offsets *offsets;
16353 HOST_WIDE_INT delta;
16354 HOST_WIDE_INT limit;
16357 unsigned long mask;
16359 emit_insn (gen_rtx_USE (VOIDmode, source));
16361 mask = thumb1_compute_save_reg_mask ();
16362 if (mask & (1 << LR_REGNUM))
16364 offsets = arm_get_frame_offsets ();
16367 /* Find the saved regs. */
16368 if (frame_pointer_needed)
16370 delta = offsets->soft_frame - offsets->saved_args;
16371 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
16377 delta = offsets->outgoing_args - offsets->saved_args;
16380 /* Allow for the stack frame. */
16381 if (TARGET_THUMB1 && TARGET_BACKTRACE)
16383 /* The link register is always the first saved register. */
16386 /* Construct the address. */
16387 addr = gen_rtx_REG (SImode, reg);
16390 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
16391 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
16395 addr = plus_constant (addr, delta);
16397 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16400 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16403 /* Implements target hook vector_mode_supported_p. */
16405 arm_vector_mode_supported_p (enum machine_mode mode)
16407 if ((mode == V2SImode)
16408 || (mode == V4HImode)
16409 || (mode == V8QImode))
16415 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16416 ARM insns and therefore guarantee that the shift count is modulo 256.
16417 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16418 guarantee no particular behavior for out-of-range counts. */
16420 static unsigned HOST_WIDE_INT
16421 arm_shift_truncation_mask (enum machine_mode mode)
16423 return mode == SImode ? 255 : 0;
16427 /* Map internal gcc register numbers to DWARF2 register numbers. */
16430 arm_dbx_register_number (unsigned int regno)
16435 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16436 compatibility. The EABI defines them as registers 96-103. */
16437 if (IS_FPA_REGNUM (regno))
16438 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
16440 /* FIXME: VFPv3 register numbering. */
16441 if (IS_VFP_REGNUM (regno))
16442 return 64 + regno - FIRST_VFP_REGNUM;
16444 if (IS_IWMMXT_GR_REGNUM (regno))
16445 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
16447 if (IS_IWMMXT_REGNUM (regno))
16448 return 112 + regno - FIRST_IWMMXT_REGNUM;
16450 gcc_unreachable ();
16454 #ifdef TARGET_UNWIND_INFO
16455 /* Emit unwind directives for a store-multiple instruction or stack pointer
16456 push during alignment.
16457 These should only ever be generated by the function prologue code, so
16458 expect them to have a particular form. */
16461 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
16464 HOST_WIDE_INT offset;
16465 HOST_WIDE_INT nregs;
16471 e = XVECEXP (p, 0, 0);
16472 if (GET_CODE (e) != SET)
16475 /* First insn will adjust the stack pointer. */
16476 if (GET_CODE (e) != SET
16477 || GET_CODE (XEXP (e, 0)) != REG
16478 || REGNO (XEXP (e, 0)) != SP_REGNUM
16479 || GET_CODE (XEXP (e, 1)) != PLUS)
16482 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
16483 nregs = XVECLEN (p, 0) - 1;
16485 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
16488 /* The function prologue may also push pc, but not annotate it as it is
16489 never restored. We turn this into a stack pointer adjustment. */
16490 if (nregs * 4 == offset - 4)
16492 fprintf (asm_out_file, "\t.pad #4\n");
16496 fprintf (asm_out_file, "\t.save {");
16498 else if (IS_VFP_REGNUM (reg))
16501 fprintf (asm_out_file, "\t.vsave {");
16503 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
16505 /* FPA registers are done differently. */
16506 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
16510 /* Unknown register type. */
16513 /* If the stack increment doesn't match the size of the saved registers,
16514 something has gone horribly wrong. */
16515 if (offset != nregs * reg_size)
16520 /* The remaining insns will describe the stores. */
16521 for (i = 1; i <= nregs; i++)
16523 /* Expect (set (mem <addr>) (reg)).
16524 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16525 e = XVECEXP (p, 0, i);
16526 if (GET_CODE (e) != SET
16527 || GET_CODE (XEXP (e, 0)) != MEM
16528 || GET_CODE (XEXP (e, 1)) != REG)
16531 reg = REGNO (XEXP (e, 1));
16536 fprintf (asm_out_file, ", ");
16537 /* We can't use %r for vfp because we need to use the
16538 double precision register names. */
16539 if (IS_VFP_REGNUM (reg))
16540 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
16542 asm_fprintf (asm_out_file, "%r", reg);
16544 #ifdef ENABLE_CHECKING
16545 /* Check that the addresses are consecutive. */
16546 e = XEXP (XEXP (e, 0), 0);
16547 if (GET_CODE (e) == PLUS)
16549 offset += reg_size;
16550 if (GET_CODE (XEXP (e, 0)) != REG
16551 || REGNO (XEXP (e, 0)) != SP_REGNUM
16552 || GET_CODE (XEXP (e, 1)) != CONST_INT
16553 || offset != INTVAL (XEXP (e, 1)))
16557 || GET_CODE (e) != REG
16558 || REGNO (e) != SP_REGNUM)
16562 fprintf (asm_out_file, "}\n");
16565 /* Emit unwind directives for a SET. */
16568 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
16576 switch (GET_CODE (e0))
16579 /* Pushing a single register. */
16580 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
16581 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
16582 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
16585 asm_fprintf (asm_out_file, "\t.save ");
16586 if (IS_VFP_REGNUM (REGNO (e1)))
16587 asm_fprintf(asm_out_file, "{d%d}\n",
16588 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
16590 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
16594 if (REGNO (e0) == SP_REGNUM)
16596 /* A stack increment. */
16597 if (GET_CODE (e1) != PLUS
16598 || GET_CODE (XEXP (e1, 0)) != REG
16599 || REGNO (XEXP (e1, 0)) != SP_REGNUM
16600 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16603 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
16604 -INTVAL (XEXP (e1, 1)));
16606 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
16608 HOST_WIDE_INT offset;
16610 if (GET_CODE (e1) == PLUS)
16612 if (GET_CODE (XEXP (e1, 0)) != REG
16613 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16615 reg = REGNO (XEXP (e1, 0));
16616 offset = INTVAL (XEXP (e1, 1));
16617 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
16618 HARD_FRAME_POINTER_REGNUM, reg,
16619 INTVAL (XEXP (e1, 1)));
16621 else if (GET_CODE (e1) == REG)
16624 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
16625 HARD_FRAME_POINTER_REGNUM, reg);
16630 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
16632 /* Move from sp to reg. */
16633 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
16635 else if (GET_CODE (e1) == PLUS
16636 && GET_CODE (XEXP (e1, 0)) == REG
16637 && REGNO (XEXP (e1, 0)) == SP_REGNUM
16638 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
16640 /* Set reg to offset from sp. */
16641 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
16642 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
16644 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
16646 /* Stack pointer save before alignment. */
16648 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16661 /* Emit unwind directives for the given insn. */
16664 arm_unwind_emit (FILE * asm_out_file, rtx insn)
16668 if (!ARM_EABI_UNWIND_TABLES)
16671 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
16674 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
16676 pat = XEXP (pat, 0);
16678 pat = PATTERN (insn);
16680 switch (GET_CODE (pat))
16683 arm_unwind_emit_set (asm_out_file, pat);
16687 /* Store multiple. */
16688 arm_unwind_emit_sequence (asm_out_file, pat);
16697 /* Output a reference from a function exception table to the type_info
16698 object X. The EABI specifies that the symbol should be relocated by
16699 an R_ARM_TARGET2 relocation. */
16702 arm_output_ttype (rtx x)
16704 fputs ("\t.word\t", asm_out_file);
16705 output_addr_const (asm_out_file, x);
16706 /* Use special relocations for symbol references. */
16707 if (GET_CODE (x) != CONST_INT)
16708 fputs ("(TARGET2)", asm_out_file);
16709 fputc ('\n', asm_out_file);
16713 #endif /* TARGET_UNWIND_INFO */
16716 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16717 stack alignment. */
16720 arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
16722 rtx unspec = SET_SRC (pattern);
16723 gcc_assert (GET_CODE (unspec) == UNSPEC);
16727 case UNSPEC_STACK_ALIGN:
16728 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16729 put anything on the stack, so hopefully it won't matter.
16730 CFA = SP will be correct after alignment. */
16731 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
16732 SET_DEST (pattern));
16735 gcc_unreachable ();
16740 /* Output unwind directives for the start/end of a function. */
16743 arm_output_fn_unwind (FILE * f, bool prologue)
16745 if (!ARM_EABI_UNWIND_TABLES)
16749 fputs ("\t.fnstart\n", f);
16751 fputs ("\t.fnend\n", f);
16755 arm_emit_tls_decoration (FILE *fp, rtx x)
16757 enum tls_reloc reloc;
16760 val = XVECEXP (x, 0, 0);
16761 reloc = INTVAL (XVECEXP (x, 0, 1));
16763 output_addr_const (fp, val);
16768 fputs ("(tlsgd)", fp);
16771 fputs ("(tlsldm)", fp);
16774 fputs ("(tlsldo)", fp);
16777 fputs ("(gottpoff)", fp);
16780 fputs ("(tpoff)", fp);
16783 gcc_unreachable ();
16791 fputs (" + (. - ", fp);
16792 output_addr_const (fp, XVECEXP (x, 0, 2));
16794 output_addr_const (fp, XVECEXP (x, 0, 3));
16804 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
16807 arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
16809 gcc_assert (size == 4);
16810 fputs ("\t.word\t", file);
16811 output_addr_const (file, x);
16812 fputs ("(tlsldo)", file);
16816 arm_output_addr_const_extra (FILE *fp, rtx x)
16818 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
16819 return arm_emit_tls_decoration (fp, x);
16820 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
16823 int labelno = INTVAL (XVECEXP (x, 0, 0));
16825 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
16826 assemble_name_raw (fp, label);
16830 else if (GET_CODE (x) == CONST_VECTOR)
16831 return arm_emit_vector_const (fp, x);
16836 /* Output assembly for a shift instruction.
16837 SET_FLAGS determines how the instruction modifies the condition codes.
16838 0 - Do not set condition codes.
16839 1 - Set condition codes.
16840 2 - Use smallest instruction. */
16842 arm_output_shift(rtx * operands, int set_flags)
16845 static const char flag_chars[3] = {'?', '.', '!'};
16850 c = flag_chars[set_flags];
16851 if (TARGET_UNIFIED_ASM)
16853 shift = shift_op(operands[3], &val);
16857 operands[2] = GEN_INT(val);
16858 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
16861 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
16864 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
16865 output_asm_insn (pattern, operands);
16869 /* Output a Thumb-2 casesi instruction. */
16871 thumb2_output_casesi (rtx *operands)
16873 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
16875 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
16877 output_asm_insn ("cmp\t%0, %1", operands);
16878 output_asm_insn ("bhi\t%l3", operands);
16879 switch (GET_MODE(diff_vec))
16882 return "tbb\t[%|pc, %0]";
16884 return "tbh\t[%|pc, %0, lsl #1]";
16888 output_asm_insn ("adr\t%4, %l2", operands);
16889 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
16890 output_asm_insn ("add\t%4, %4, %5", operands);
16895 output_asm_insn ("adr\t%4, %l2", operands);
16896 return "ldr\t%|pc, [%4, %0, lsl #2]";
16899 gcc_unreachable ();
16903 #include "gt-arm.h"