1 /* Output routines for GCC for ARM/RISCiX.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
36 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 #define MAX_INSNS_SKIPPED 5
46 /* Some function declarations. */
47 extern FILE *asm_out_file;
48 extern char *output_multi_immediate ();
49 extern void arm_increase_location ();
51 HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
52 static int get_prologue_size PROTO ((void));
53 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
54 HOST_WIDE_INT, rtx, rtx, int, int));
56 /* Define the information needed to generate branch insns. This is
57 stored from the compare operation. */
59 rtx arm_compare_op0, arm_compare_op1;
62 /* What type of cpu are we compiling for? */
63 enum processor_type arm_cpu;
65 /* What type of floating point are we compiling for? */
66 enum floating_point_type arm_fpu;
68 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
69 enum prog_mode_type arm_prgmode;
71 char *target_cpu_name = ARM_CPU_NAME;
72 char *target_fpe_name = NULL;
74 /* Nonzero if this is an "M" variant of the processor. */
75 int arm_fast_multiply = 0;
77 /* Nonzero if this chip support the ARM Architecture 4 extensions */
80 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
81 must report the mode of the memory reference from PRINT_OPERAND to
82 PRINT_OPERAND_ADDRESS. */
83 enum machine_mode output_memory_reference_mode;
85 /* Nonzero if the prologue must setup `fp'. */
86 int current_function_anonymous_args;
88 /* Location counter of .text segment. */
89 int arm_text_location = 0;
91 /* Set to one if we think that lr is only saved because of subroutine calls,
92 but all of these can be `put after' return insns */
93 int lr_save_eliminated;
95 /* A hash table is used to store text segment labels and their associated
96 offset from the start of the text segment. */
101 struct label_offset *cdr;
104 #define LABEL_HASH_SIZE 257
106 static struct label_offset *offset_table[LABEL_HASH_SIZE];
108 /* Set to 1 when a return insn is output, this means that the epilogue
111 static int return_used_this_function;
113 static int arm_constant_limit = 3;
115 /* For an explanation of these variables, see final_prescan_insn below. */
117 enum arm_cond_code arm_current_cc;
119 int arm_target_label;
121 /* The condition codes of the ARM, and the inverse function. */
122 char *arm_condition_codes[] =
124 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
125 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
128 static enum arm_cond_code get_arm_condition_code ();
131 /* Initialization code */
133 struct arm_cpu_select arm_select[3] =
135 /* switch name, tune arch */
136 { (char *)0, "--with-cpu=", 1, 1 },
137 { (char *)0, "-mcpu=", 1, 1 },
138 { (char *)0, "-mtune=", 1, 0 },
141 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
142 #define FL_FAST_MULT 0x02 /* Fast multiply */
143 #define FL_MODE26 0x04 /* 26-bit mode support */
144 #define FL_MODE32 0x08 /* 32-bit mode support */
145 #define FL_ARCH4 0x10 /* Architecture rel 4 */
146 #define FL_THUMB 0x20 /* Thumb aware */
150 enum processor_type type;
154 /* Not all of these give usefully different compilation alternatives,
155 but there is no simple way of generalizing them. */
156 static struct processors all_procs[] =
158 {"arm2", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
159 {"arm250", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
160 {"arm3", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
161 {"arm6", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
162 {"arm60", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
163 {"arm600", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
164 {"arm610", PROCESSOR_ARM6, FL_MODE32 | FL_MODE26},
165 {"arm620", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
166 {"arm7", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
167 {"arm70", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
168 {"arm7d", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
169 {"arm7di", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
170 {"arm7dm", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
172 {"arm7dmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
174 {"arm700", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
175 {"arm700i", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
176 {"arm710", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
177 {"arm710c", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
178 {"arm7100", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
179 {"arm7500", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
180 {"arm7tdmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
181 | FL_ARCH4 | FL_THUMB)},
185 /* Fix up any incompatible options that the user has specified.
186 This has now turned into a maze. */
188 arm_override_options ()
190 int arm_thumb_aware = 0;
193 struct arm_cpu_select *ptr;
195 arm_cpu = PROCESSOR_DEFAULT;
196 arm_select[0].string = TARGET_CPU_DEFAULT;
198 for (i = 0; i < sizeof (arm_select) / sizeof (arm_select[0]); i++)
200 ptr = &arm_select[i];
201 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
203 struct processors *sel;
205 for (sel = all_procs; sel->name != NULL; sel++)
206 if (! strcmp (ptr->string, sel->name))
216 if (sel->name == NULL)
217 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
221 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
222 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
224 if (TARGET_POKE_FUNCTION_NAME)
225 target_flags |= ARM_FLAG_APCS_FRAME;
229 warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
230 target_flags |= ARM_FLAG_APCS_32;
231 arm_cpu = PROCESSOR_ARM6;
236 warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
237 target_flags &= ~ARM_FLAG_APCS_32;
238 arm_cpu = PROCESSOR_ARM2;
241 if (TARGET_APCS_REENT && flag_pic)
242 fatal ("-fpic and -mapcs-reent are incompatible");
244 if (TARGET_APCS_REENT)
245 warning ("APCS reentrant code not supported. Ignored");
248 warning ("Position independent code not supported. Ignored");
250 if (TARGET_APCS_FLOAT)
251 warning ("Passing floating point arguments in fp regs not yet supported");
253 if (TARGET_APCS_STACK && ! TARGET_APCS)
255 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
256 target_flags |= ARM_FLAG_APCS_FRAME;
261 /* Default value for floating point code... if no co-processor
262 bus, then schedule for emulated floating point. Otherwise,
263 assume the user has an FPA, unless overridden with -mfpe-... */
264 if (flags & FL_CO_PROC == 0)
268 arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
269 arm_arch4 = (flags & FL_ARCH4) != 0;
270 arm_thumb_aware = (flags & FL_THUMB) != 0;
274 if (strcmp (target_fpe_name, "2") == 0)
276 else if (strcmp (target_fpe_name, "3") == 0)
279 fatal ("Invalid floating point emulation option: -mfpe-%s",
283 if (TARGET_THUMB_INTERWORK && ! arm_thumb_aware)
285 warning ("This processor variant does not support Thumb interworking");
286 target_flags &= ~ARM_FLAG_THUMB;
289 if (TARGET_FPE && arm_fpu != FP_HARD)
292 /* For arm2/3 there is no need to do any scheduling if there is only
293 a floating point emulator, or we are doing software floating-point. */
294 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && arm_cpu == PROCESSOR_ARM2)
295 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
297 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
300 /* Return 1 if it is possible to return using a single instruction */
307 if (!reload_completed ||current_function_pretend_args_size
308 || current_function_anonymous_args
309 || (get_frame_size () && !(TARGET_APCS || frame_pointer_needed)))
312 /* Can't be done if any of the FPU regs are pushed, since this also
314 for (regno = 20; regno < 24; regno++)
315 if (regs_ever_live[regno])
318 /* If a function is naked, don't use the "return" insn. */
319 if (arm_naked_function_p (current_function_decl))
325 /* Return TRUE if int I is a valid immediate ARM constant. */
331 unsigned HOST_WIDE_INT mask = ~0xFF;
333 /* Fast return for 0 and powers of 2 */
334 if ((i & (i - 1)) == 0)
339 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
342 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
343 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
344 } while (mask != ~0xFF);
349 /* Return true if I is a valid constant for the operation CODE. */
351 const_ok_for_op (i, code, mode)
354 enum machine_mode mode;
356 if (const_ok_for_arm (i))
362 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
364 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
370 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
377 /* Emit a sequence of insns to handle a large constant.
378 CODE is the code of the operation required, it can be any of SET, PLUS,
379 IOR, AND, XOR, MINUS;
380 MODE is the mode in which the operation is being performed;
381 VAL is the integer to operate on;
382 SOURCE is the other operand (a register, or a null-pointer for SET);
383 SUBTARGETS means it is safe to create scratch registers if that will
384 either produce a simpler sequence, or we will want to cse the values.
385 Return value is the number of insns emitted. */
388 arm_split_constant (code, mode, val, target, source, subtargets)
390 enum machine_mode mode;
396 if (subtargets || code == SET
397 || (GET_CODE (target) == REG && GET_CODE (source) == REG
398 && REGNO (target) != REGNO (source)))
402 if (arm_gen_constant (code, mode, val, target, source, 1, 0)
403 > arm_constant_limit + (code != SET))
407 /* Currently SET is the only monadic value for CODE, all
408 the rest are diadic. */
409 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (val)));
414 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
416 emit_insn (gen_rtx (SET, VOIDmode, temp, GEN_INT (val)));
417 /* For MINUS, the value is subtracted from, since we never
418 have subtraction of a constant. */
420 emit_insn (gen_rtx (SET, VOIDmode, target,
421 gen_rtx (code, mode, temp, source)));
423 emit_insn (gen_rtx (SET, VOIDmode, target,
424 gen_rtx (code, mode, source, temp)));
430 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
433 /* As above, but extra parameter GENERATE which, if clear, suppresses
436 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
438 enum machine_mode mode;
448 int can_negate_initial = 0;
451 int num_bits_set = 0;
452 int set_sign_bit_copies = 0;
453 int clear_sign_bit_copies = 0;
454 int clear_zero_bit_copies = 0;
455 int set_zero_bit_copies = 0;
458 unsigned HOST_WIDE_INT temp1, temp2;
459 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
461 /* find out which operations are safe for a given CODE. Also do a quick
462 check for degenerate cases; these can occur when DImode operations
474 can_negate_initial = 1;
478 if (remainder == 0xffffffff)
481 emit_insn (gen_rtx (SET, VOIDmode, target,
482 GEN_INT (ARM_SIGN_EXTEND (val))));
487 if (reload_completed && rtx_equal_p (target, source))
490 emit_insn (gen_rtx (SET, VOIDmode, target, source));
499 emit_insn (gen_rtx (SET, VOIDmode, target, const0_rtx));
502 if (remainder == 0xffffffff)
504 if (reload_completed && rtx_equal_p (target, source))
507 emit_insn (gen_rtx (SET, VOIDmode, target, source));
516 if (reload_completed && rtx_equal_p (target, source))
519 emit_insn (gen_rtx (SET, VOIDmode, target, source));
522 if (remainder == 0xffffffff)
525 emit_insn (gen_rtx (SET, VOIDmode, target,
526 gen_rtx (NOT, mode, source)));
530 /* We don't know how to handle this yet below. */
534 /* We treat MINUS as (val - source), since (source - val) is always
535 passed as (source + (-val)). */
539 emit_insn (gen_rtx (SET, VOIDmode, target,
540 gen_rtx (NEG, mode, source)));
543 if (const_ok_for_arm (val))
546 emit_insn (gen_rtx (SET, VOIDmode, target,
547 gen_rtx (MINUS, mode, GEN_INT (val), source)));
558 /* If we can do it in one insn get out quickly */
559 if (const_ok_for_arm (val)
560 || (can_negate_initial && const_ok_for_arm (-val))
561 || (can_invert && const_ok_for_arm (~val)))
564 emit_insn (gen_rtx (SET, VOIDmode, target,
565 (source ? gen_rtx (code, mode, source,
572 /* Calculate a few attributes that may be useful for specific
575 for (i = 31; i >= 0; i--)
577 if ((remainder & (1 << i)) == 0)
578 clear_sign_bit_copies++;
583 for (i = 31; i >= 0; i--)
585 if ((remainder & (1 << i)) != 0)
586 set_sign_bit_copies++;
591 for (i = 0; i <= 31; i++)
593 if ((remainder & (1 << i)) == 0)
594 clear_zero_bit_copies++;
599 for (i = 0; i <= 31; i++)
601 if ((remainder & (1 << i)) != 0)
602 set_zero_bit_copies++;
610 /* See if we can do this by sign_extending a constant that is known
611 to be negative. This is a good, way of doing it, since the shift
612 may well merge into a subsequent insn. */
613 if (set_sign_bit_copies > 1)
616 (temp1 = ARM_SIGN_EXTEND (remainder
617 << (set_sign_bit_copies - 1))))
621 new_src = subtargets ? gen_reg_rtx (mode) : target;
622 emit_insn (gen_rtx (SET, VOIDmode, new_src,
624 emit_insn (gen_ashrsi3 (target, new_src,
625 GEN_INT (set_sign_bit_copies - 1)));
629 /* For an inverted constant, we will need to set the low bits,
630 these will be shifted out of harm's way. */
631 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
632 if (const_ok_for_arm (~temp1))
636 new_src = subtargets ? gen_reg_rtx (mode) : target;
637 emit_insn (gen_rtx (SET, VOIDmode, new_src,
639 emit_insn (gen_ashrsi3 (target, new_src,
640 GEN_INT (set_sign_bit_copies - 1)));
646 /* See if we can generate this by setting the bottom (or the top)
647 16 bits, and then shifting these into the other half of the
648 word. We only look for the simplest cases, to do more would cost
649 too much. Be careful, however, not to generate this when the
650 alternative would take fewer insns. */
651 if (val & 0xffff0000)
653 temp1 = remainder & 0xffff0000;
654 temp2 = remainder & 0x0000ffff;
656 /* Overlaps outside this range are best done using other methods. */
657 for (i = 9; i < 24; i++)
659 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
660 && ! const_ok_for_arm (temp2))
662 insns = arm_gen_constant (code, mode, temp2,
663 new_src = (subtargets
666 source, subtargets, generate);
669 emit_insn (gen_rtx (SET, VOIDmode, target,
671 gen_rtx (ASHIFT, mode, source,
678 /* Don't duplicate cases already considered. */
679 for (i = 17; i < 24; i++)
681 if (((temp1 | (temp1 >> i)) == remainder)
682 && ! const_ok_for_arm (temp1))
684 insns = arm_gen_constant (code, mode, temp1,
685 new_src = (subtargets
688 source, subtargets, generate);
691 emit_insn (gen_rtx (SET, VOIDmode, target,
693 gen_rtx (LSHIFTRT, mode,
694 source, GEN_INT (i)),
704 /* If we have IOR or XOR, and the inverse of the constant can be loaded
705 in a single instruction, and we can find a temporary to put it in,
706 then this can be done in two instructions instead of 3-4. */
708 || (reload_completed && ! reg_mentioned_p (target, source)))
710 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
714 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
716 emit_insn (gen_rtx (SET, VOIDmode, sub,
717 GEN_INT (ARM_SIGN_EXTEND (~ val))));
718 emit_insn (gen_rtx (SET, VOIDmode, target,
719 gen_rtx (code, mode, source, sub)));
728 if (set_sign_bit_copies > 8
729 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
733 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
734 rtx shift = GEN_INT (set_sign_bit_copies);
736 emit_insn (gen_rtx (SET, VOIDmode, sub,
738 gen_rtx (ASHIFT, mode, source,
740 emit_insn (gen_rtx (SET, VOIDmode, target,
742 gen_rtx (LSHIFTRT, mode, sub,
748 if (set_zero_bit_copies > 8
749 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
753 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
754 rtx shift = GEN_INT (set_zero_bit_copies);
756 emit_insn (gen_rtx (SET, VOIDmode, sub,
758 gen_rtx (LSHIFTRT, mode, source,
760 emit_insn (gen_rtx (SET, VOIDmode, target,
762 gen_rtx (ASHIFT, mode, sub,
768 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
772 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
773 emit_insn (gen_rtx (SET, VOIDmode, sub,
774 gen_rtx (NOT, mode, source)));
777 sub = gen_reg_rtx (mode);
778 emit_insn (gen_rtx (SET, VOIDmode, sub,
779 gen_rtx (AND, mode, source,
781 emit_insn (gen_rtx (SET, VOIDmode, target,
782 gen_rtx (NOT, mode, sub)));
789 /* See if two shifts will do 2 or more insn's worth of work. */
790 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
792 HOST_WIDE_INT shift_mask = ((0xffffffff
793 << (32 - clear_sign_bit_copies))
798 if ((remainder | shift_mask) != 0xffffffff)
802 new_source = subtargets ? gen_reg_rtx (mode) : target;
803 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
804 new_source, source, subtargets, 1);
808 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
809 new_source, source, subtargets, 0);
814 shift = GEN_INT (clear_sign_bit_copies);
815 new_source = subtargets ? gen_reg_rtx (mode) : target;
816 emit_insn (gen_ashlsi3 (new_source, source, shift));
817 emit_insn (gen_lshrsi3 (target, new_source, shift));
823 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
825 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
829 if ((remainder | shift_mask) != 0xffffffff)
833 new_source = subtargets ? gen_reg_rtx (mode) : target;
834 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
835 new_source, source, subtargets, 1);
839 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
840 new_source, source, subtargets, 0);
845 shift = GEN_INT (clear_zero_bit_copies);
846 new_source = subtargets ? gen_reg_rtx (mode) : target;
847 emit_insn (gen_lshrsi3 (new_source, source, shift));
848 emit_insn (gen_ashlsi3 (target, new_source, shift));
860 for (i = 0; i < 32; i++)
861 if (remainder & (1 << i))
864 if (code == AND || (can_invert && num_bits_set > 16))
865 remainder = (~remainder) & 0xffffffff;
866 else if (code == PLUS && num_bits_set > 16)
867 remainder = (-remainder) & 0xffffffff;
874 /* Now try and find a way of doing the job in either two or three
876 We start by looking for the largest block of zeros that are aligned on
877 a 2-bit boundary, we then fill up the temps, wrapping around to the
878 top of the word when we drop off the bottom.
879 In the worst case this code should produce no more than four insns. */
882 int best_consecutive_zeros = 0;
884 for (i = 0; i < 32; i += 2)
886 int consecutive_zeros = 0;
888 if (! (remainder & (3 << i)))
890 while ((i < 32) && ! (remainder & (3 << i)))
892 consecutive_zeros += 2;
895 if (consecutive_zeros > best_consecutive_zeros)
897 best_consecutive_zeros = consecutive_zeros;
898 best_start = i - consecutive_zeros;
904 /* Now start emitting the insns, starting with the one with the highest
905 bit set: we do this so that the smallest number will be emitted last;
906 this is more likely to be combinable with addressing insns. */
914 if (remainder & (3 << (i - 2)))
919 temp1 = remainder & ((0x0ff << end)
920 | ((i < end) ? (0xff >> (32 - end)) : 0));
926 emit_insn (gen_rtx (SET, VOIDmode,
927 new_src = (subtargets
930 GEN_INT (can_invert ? ~temp1 : temp1)));
934 else if (code == MINUS)
937 emit_insn (gen_rtx (SET, VOIDmode,
938 new_src = (subtargets
941 gen_rtx (code, mode, GEN_INT (temp1),
948 emit_insn (gen_rtx (SET, VOIDmode,
954 gen_rtx (code, mode, source,
955 GEN_INT (can_invert ? ~temp1
971 /* Canonicalize a comparison so that we are more likely to recognize it.
972 This can be done for a few constant compares, where we can make the
973 immediate value easier to load. */
975 arm_canonicalize_comparison (code, op1)
979 HOST_WIDE_INT i = INTVAL (*op1);
989 if (i != (1 << (HOST_BITS_PER_WIDE_INT - 1) - 1)
990 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
992 *op1 = GEN_INT (i+1);
993 return code == GT ? GE : LT;
999 if (i != (1 << (HOST_BITS_PER_WIDE_INT - 1))
1000 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1002 *op1 = GEN_INT (i-1);
1003 return code == GE ? GT : LE;
1010 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1012 *op1 = GEN_INT (i + 1);
1013 return code == GTU ? GEU : LTU;
1020 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1022 *op1 = GEN_INT (i - 1);
1023 return code == GEU ? GTU : LEU;
1035 /* Handle aggregates that are not laid out in a BLKmode element.
1036 This is a sub-element of RETURN_IN_MEMORY. */
1038 arm_return_in_memory (type)
1041 if (TREE_CODE (type) == RECORD_TYPE)
1045 /* For a struct, we can return in a register if every element was a
1047 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1048 if (TREE_CODE (field) != FIELD_DECL
1049 || ! DECL_BIT_FIELD_TYPE (field))
1054 else if (TREE_CODE (type) == UNION_TYPE)
1058 /* Unions can be returned in registers if every element is
1059 integral, or can be returned in an integer register. */
1060 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1062 if (TREE_CODE (field) != FIELD_DECL
1063 || (AGGREGATE_TYPE_P (TREE_TYPE (field))
1064 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1065 || FLOAT_TYPE_P (TREE_TYPE (field)))
1070 /* XXX Not sure what should be done for other aggregates, so put them in
1075 #define REG_OR_SUBREG_REG(X) \
1076 (GET_CODE (X) == REG \
1077 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1079 #define REG_OR_SUBREG_RTX(X) \
1080 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1082 #define ARM_FRAME_RTX(X) \
1083 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1084 || (X) == arg_pointer_rtx)
1087 arm_rtx_costs (x, code, outer_code)
1089 enum rtx_code code, outer_code;
1091 enum machine_mode mode = GET_MODE (x);
1092 enum rtx_code subcode;
1098 /* Memory costs quite a lot for the first word, but subsequent words
1099 load at the equivalent of a single insn each. */
1100 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1101 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1108 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1115 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1117 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1118 + ((GET_CODE (XEXP (x, 0)) == REG
1119 || (GET_CODE (XEXP (x, 0)) == SUBREG
1120 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1122 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1123 || (GET_CODE (XEXP (x, 0)) == SUBREG
1124 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1126 + ((GET_CODE (XEXP (x, 1)) == REG
1127 || (GET_CODE (XEXP (x, 1)) == SUBREG
1128 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1129 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1134 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1135 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1136 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1137 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1140 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1141 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1142 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1143 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1145 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1146 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1147 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1150 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1151 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1152 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1153 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1154 || subcode == ASHIFTRT || subcode == LSHIFTRT
1155 || subcode == ROTATE || subcode == ROTATERT
1157 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1158 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1159 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1160 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1161 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1162 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1163 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1168 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1169 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1170 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1171 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1172 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1176 case AND: case XOR: case IOR:
1179 /* Normally the frame registers will be spilt into reg+const during
1180 reload, so it is a bad idea to combine them with other instructions,
1181 since then they might not be moved outside of loops. As a compromise
1182 we allow integration with ops that have a constant as their second
1184 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1185 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1186 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1187 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1188 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1192 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1193 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1194 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1195 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1198 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1199 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1200 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1201 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1202 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1205 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1206 return (1 + extra_cost
1207 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1208 || subcode == LSHIFTRT || subcode == ASHIFTRT
1209 || subcode == ROTATE || subcode == ROTATERT
1211 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1212 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1213 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))
1214 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1215 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1216 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
1222 if (arm_fast_multiply && mode == DImode
1223 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1224 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1225 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1228 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1232 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1234 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1235 & (unsigned HOST_WIDE_INT) 0xffffffff);
1236 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1238 int booth_unit_size = (arm_fast_multiply ? 8 : 2);
1240 for (j = 0; i && j < 32; j += booth_unit_size)
1242 i >>= booth_unit_size;
1249 return ((arm_fast_multiply ? 8 : 30)
1250 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1251 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1254 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1255 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1259 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1261 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1264 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1272 return 4 + (mode == DImode ? 4 : 0);
1275 if (GET_MODE (XEXP (x, 0)) == QImode)
1276 return (4 + (mode == DImode ? 4 : 0)
1277 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1280 switch (GET_MODE (XEXP (x, 0)))
1283 return (1 + (mode == DImode ? 4 : 0)
1284 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1287 return (4 + (mode == DImode ? 4 : 0)
1288 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1291 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1300 /* This code has been fixed for cross compilation. */
1302 static int fpa_consts_inited = 0;
1304 char *strings_fpa[8] = {
1306 "4", "5", "0.5", "10"
1309 static REAL_VALUE_TYPE values_fpa[8];
1317 for (i = 0; i < 8; i++)
1319 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1323 fpa_consts_inited = 1;
1326 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1329 const_double_rtx_ok_for_fpu (x)
1335 if (!fpa_consts_inited)
1338 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1339 if (REAL_VALUE_MINUS_ZERO (r))
1342 for (i = 0; i < 8; i++)
1343 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1349 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1352 neg_const_double_rtx_ok_for_fpu (x)
1358 if (!fpa_consts_inited)
1361 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1362 r = REAL_VALUE_NEGATE (r);
1363 if (REAL_VALUE_MINUS_ZERO (r))
1366 for (i = 0; i < 8; i++)
1367 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1373 /* Predicates for `match_operand' and `match_operator'. */
1375 /* s_register_operand is the same as register_operand, but it doesn't accept
1378 This function exists because at the time it was put in it led to better
1379 code. SUBREG(MEM) always needs a reload in the places where
1380 s_register_operand is used, and this seemed to lead to excessive
1384 s_register_operand (op, mode)
1386 enum machine_mode mode;
1388 if (GET_MODE (op) != mode && mode != VOIDmode)
1391 if (GET_CODE (op) == SUBREG)
1392 op = SUBREG_REG (op);
1394 /* We don't consider registers whose class is NO_REGS
1395 to be a register operand. */
1396 return (GET_CODE (op) == REG
1397 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1398 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1401 /* Only accept reg, subreg(reg), const_int. */
1404 reg_or_int_operand (op, mode)
1406 enum machine_mode mode;
1408 if (GET_CODE (op) == CONST_INT)
1411 if (GET_MODE (op) != mode && mode != VOIDmode)
1414 if (GET_CODE (op) == SUBREG)
1415 op = SUBREG_REG (op);
1417 /* We don't consider registers whose class is NO_REGS
1418 to be a register operand. */
1419 return (GET_CODE (op) == REG
1420 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1421 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1424 /* Return 1 if OP is an item in memory, given that we are in reload. */
1427 reload_memory_operand (op, mode)
1429 enum machine_mode mode;
1431 int regno = true_regnum (op);
1433 return (! CONSTANT_P (op)
1435 || (GET_CODE (op) == REG
1436 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1439 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1442 arm_rhs_operand (op, mode)
1444 enum machine_mode mode;
1446 return (s_register_operand (op, mode)
1447 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
1450 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1454 arm_rhsm_operand (op, mode)
1456 enum machine_mode mode;
1458 return (s_register_operand (op, mode)
1459 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
1460 || memory_operand (op, mode));
1463 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1464 constant that is valid when negated. */
1467 arm_add_operand (op, mode)
1469 enum machine_mode mode;
1471 return (s_register_operand (op, mode)
1472 || (GET_CODE (op) == CONST_INT
1473 && (const_ok_for_arm (INTVAL (op))
1474 || const_ok_for_arm (-INTVAL (op)))));
1478 arm_not_operand (op, mode)
1480 enum machine_mode mode;
1482 return (s_register_operand (op, mode)
1483 || (GET_CODE (op) == CONST_INT
1484 && (const_ok_for_arm (INTVAL (op))
1485 || const_ok_for_arm (~INTVAL (op)))));
1488 /* Return TRUE if the operand is a memory reference which contains an
1489 offsettable address. */
1491 offsettable_memory_operand (op, mode)
1493 enum machine_mode mode;
1495 if (mode == VOIDmode)
1496 mode = GET_MODE (op);
1498 return (mode == GET_MODE (op)
1499 && GET_CODE (op) == MEM
1500 && offsettable_address_p (reload_completed | reload_in_progress,
1501 mode, XEXP (op, 0)));
1504 /* Return TRUE if the operand is a memory reference which is, or can be
1505 made word aligned by adjusting the offset. */
1507 alignable_memory_operand (op, mode)
1509 enum machine_mode mode;
1513 if (mode == VOIDmode)
1514 mode = GET_MODE (op);
1516 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
1521 return ((GET_CODE (reg = op) == REG
1522 || (GET_CODE (op) == SUBREG
1523 && GET_CODE (reg = SUBREG_REG (op)) == REG)
1524 || (GET_CODE (op) == PLUS
1525 && GET_CODE (XEXP (op, 1)) == CONST_INT
1526 && (GET_CODE (reg = XEXP (op, 0)) == REG
1527 || (GET_CODE (XEXP (op, 0)) == SUBREG
1528 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
1529 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
1532 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
1535 fpu_rhs_operand (op, mode)
1537 enum machine_mode mode;
1539 if (s_register_operand (op, mode))
1541 else if (GET_CODE (op) == CONST_DOUBLE)
1542 return (const_double_rtx_ok_for_fpu (op));
1548 fpu_add_operand (op, mode)
1550 enum machine_mode mode;
1552 if (s_register_operand (op, mode))
1554 else if (GET_CODE (op) == CONST_DOUBLE)
1555 return (const_double_rtx_ok_for_fpu (op)
1556 || neg_const_double_rtx_ok_for_fpu (op));
1561 /* Return nonzero if OP is a constant power of two. */
1564 power_of_two_operand (op, mode)
1566 enum machine_mode mode;
1568 if (GET_CODE (op) == CONST_INT)
1570 HOST_WIDE_INT value = INTVAL(op);
1571 return value != 0 && (value & (value - 1)) == 0;
1576 /* Return TRUE for a valid operand of a DImode operation.
1577 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1578 Note that this disallows MEM(REG+REG), but allows
1579 MEM(PRE/POST_INC/DEC(REG)). */
1582 di_operand (op, mode)
1584 enum machine_mode mode;
1586 if (s_register_operand (op, mode))
1589 switch (GET_CODE (op))
1596 return memory_address_p (DImode, XEXP (op, 0));
1603 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
1604 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1605 Note that this disallows MEM(REG+REG), but allows
1606 MEM(PRE/POST_INC/DEC(REG)). */
1609 soft_df_operand (op, mode)
1611 enum machine_mode mode;
1613 if (s_register_operand (op, mode))
1616 switch (GET_CODE (op))
1622 return memory_address_p (DFmode, XEXP (op, 0));
1629 /* Return TRUE for valid index operands. */
1632 index_operand (op, mode)
1634 enum machine_mode mode;
1636 return (s_register_operand(op, mode)
1637 || (immediate_operand (op, mode)
1638 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
1641 /* Return TRUE for valid shifts by a constant. This also accepts any
1642 power of two on the (somewhat overly relaxed) assumption that the
1643 shift operator in this case was a mult. */
1646 const_shift_operand (op, mode)
1648 enum machine_mode mode;
1650 return (power_of_two_operand (op, mode)
1651 || (immediate_operand (op, mode)
1652 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
1655 /* Return TRUE for arithmetic operators which can be combined with a multiply
1659 shiftable_operator (x, mode)
1661 enum machine_mode mode;
1663 if (GET_MODE (x) != mode)
1667 enum rtx_code code = GET_CODE (x);
1669 return (code == PLUS || code == MINUS
1670 || code == IOR || code == XOR || code == AND);
1674 /* Return TRUE for shift operators. */
1677 shift_operator (x, mode)
1679 enum machine_mode mode;
1681 if (GET_MODE (x) != mode)
1685 enum rtx_code code = GET_CODE (x);
1688 return power_of_two_operand (XEXP (x, 1));
1690 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
1691 || code == ROTATERT);
1695 int equality_operator (x, mode)
1697 enum machine_mode mode;
1699 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
1702 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
1705 minmax_operator (x, mode)
1707 enum machine_mode mode;
1709 enum rtx_code code = GET_CODE (x);
1711 if (GET_MODE (x) != mode)
1714 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
1717 /* return TRUE if x is EQ or NE */
1719 /* Return TRUE if this is the condition code register, if we aren't given
1720 a mode, accept any class CCmode register */
1723 cc_register (x, mode)
1725 enum machine_mode mode;
1727 if (mode == VOIDmode)
1729 mode = GET_MODE (x);
1730 if (GET_MODE_CLASS (mode) != MODE_CC)
1734 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
1740 /* Return TRUE if this is the condition code register, if we aren't given
1741 a mode, accept any class CCmode register which indicates a dominance
1745 dominant_cc_register (x, mode)
1747 enum machine_mode mode;
1749 if (mode == VOIDmode)
1751 mode = GET_MODE (x);
1752 if (GET_MODE_CLASS (mode) != MODE_CC)
1756 if (mode != CC_DNEmode && mode != CC_DEQmode
1757 && mode != CC_DLEmode && mode != CC_DLTmode
1758 && mode != CC_DGEmode && mode != CC_DGTmode
1759 && mode != CC_DLEUmode && mode != CC_DLTUmode
1760 && mode != CC_DGEUmode && mode != CC_DGTUmode)
1763 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
1769 /* Return TRUE if X references a SYMBOL_REF. */
1771 symbol_mentioned_p (x)
1777 if (GET_CODE (x) == SYMBOL_REF)
1780 fmt = GET_RTX_FORMAT (GET_CODE (x));
1781 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1787 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1788 if (symbol_mentioned_p (XVECEXP (x, i, j)))
1791 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
1798 /* Return TRUE if X references a LABEL_REF. */
1800 label_mentioned_p (x)
1806 if (GET_CODE (x) == LABEL_REF)
1809 fmt = GET_RTX_FORMAT (GET_CODE (x));
1810 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1817 if (label_mentioned_p (XVECEXP (x, i, j)))
1820 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
1831 enum rtx_code code = GET_CODE (x);
1835 else if (code == SMIN)
1837 else if (code == UMIN)
1839 else if (code == UMAX)
1845 /* Return 1 if memory locations are adjacent */
1848 adjacent_mem_locations (a, b)
1851 int val0 = 0, val1 = 0;
1854 if ((GET_CODE (XEXP (a, 0)) == REG
1855 || (GET_CODE (XEXP (a, 0)) == PLUS
1856 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
1857 && (GET_CODE (XEXP (b, 0)) == REG
1858 || (GET_CODE (XEXP (b, 0)) == PLUS
1859 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
1861 if (GET_CODE (XEXP (a, 0)) == PLUS)
1863 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
1864 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
1867 reg0 = REGNO (XEXP (a, 0));
1868 if (GET_CODE (XEXP (b, 0)) == PLUS)
1870 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
1871 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
1874 reg1 = REGNO (XEXP (b, 0));
1875 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
1880 /* Return 1 if OP is a load multiple operation. It is known to be
1881 parallel and the first section will be tested. */
1884 load_multiple_operation (op, mode)
1886 enum machine_mode mode;
1888 HOST_WIDE_INT count = XVECLEN (op, 0);
1891 HOST_WIDE_INT i = 1, base = 0;
1895 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
1898 /* Check to see if this might be a write-back */
1899 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
1904 /* Now check it more carefully */
1905 if (GET_CODE (SET_DEST (elt)) != REG
1906 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
1907 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
1908 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
1909 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
1910 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
1911 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
1912 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
1913 != REGNO (SET_DEST (elt)))
1919 /* Perform a quick check so we don't blow up below. */
1921 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
1922 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
1923 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
1926 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
1927 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
1929 for (; i < count; i++)
1931 rtx elt = XVECEXP (op, 0, i);
1933 if (GET_CODE (elt) != SET
1934 || GET_CODE (SET_DEST (elt)) != REG
1935 || GET_MODE (SET_DEST (elt)) != SImode
1936 || REGNO (SET_DEST (elt)) != dest_regno + i - base
1937 || GET_CODE (SET_SRC (elt)) != MEM
1938 || GET_MODE (SET_SRC (elt)) != SImode
1939 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1940 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1941 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1942 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
1949 /* Return 1 if OP is a store multiple operation. It is known to be
1950 parallel and the first section will be tested. */
1953 store_multiple_operation (op, mode)
1955 enum machine_mode mode;
1957 HOST_WIDE_INT count = XVECLEN (op, 0);
1960 HOST_WIDE_INT i = 1, base = 0;
1964 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
1967 /* Check to see if this might be a write-back */
1968 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
1973 /* Now check it more carefully */
1974 if (GET_CODE (SET_DEST (elt)) != REG
1975 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
1976 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
1977 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
1978 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
1979 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
1980 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
1981 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
1982 != REGNO (SET_DEST (elt)))
1988 /* Perform a quick check so we don't blow up below. */
1990 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
1991 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
1992 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
1995 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
1996 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
1998 for (; i < count; i++)
2000 elt = XVECEXP (op, 0, i);
2002 if (GET_CODE (elt) != SET
2003 || GET_CODE (SET_SRC (elt)) != REG
2004 || GET_MODE (SET_SRC (elt)) != SImode
2005 || REGNO (SET_SRC (elt)) != src_regno + i - base
2006 || GET_CODE (SET_DEST (elt)) != MEM
2007 || GET_MODE (SET_DEST (elt)) != SImode
2008 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2009 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2010 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2011 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2019 load_multiple_sequence (operands, nops, regs, base, load_offset)
2024 HOST_WIDE_INT *load_offset;
2026 int unsorted_regs[4];
2027 HOST_WIDE_INT unsorted_offsets[4];
2032 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2033 extended if required. */
2034 if (nops < 2 || nops > 4)
2037 /* Loop over the operands and check that the memory references are
2038 suitable (ie immediate offsets from the same base register). At
2039 the same time, extract the target register, and the memory
2041 for (i = 0; i < nops; i++)
2046 if (GET_CODE (operands[nops + i]) != MEM)
2049 /* Don't reorder volatile memory references; it doesn't seem worth
2050 looking for the case where the order is ok anyway. */
2051 if (MEM_VOLATILE_P (operands[nops + i]))
2054 offset = const0_rtx;
2056 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2057 || (GET_CODE (reg) == SUBREG
2058 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2059 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2060 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2062 || (GET_CODE (reg) == SUBREG
2063 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2064 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2069 base_reg = REGNO(reg);
2070 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2071 ? REGNO (operands[i])
2072 : REGNO (SUBREG_REG (operands[i])));
2077 if (base_reg != REGNO (reg))
2078 /* Not addressed from the same base register. */
2081 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2082 ? REGNO (operands[i])
2083 : REGNO (SUBREG_REG (operands[i])));
2084 if (unsorted_regs[i] < unsorted_regs[order[0]])
2088 /* If it isn't an integer register, or if it overwrites the
2089 base register but isn't the last insn in the list, then
2090 we can't do this. */
2091 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2092 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2095 unsorted_offsets[i] = INTVAL (offset);
2098 /* Not a suitable memory address. */
2102 /* All the useful information has now been extracted from the
2103 operands into unsorted_regs and unsorted_offsets; additionally,
2104 order[0] has been set to the lowest numbered register in the
2105 list. Sort the registers into order, and check that the memory
2106 offsets are ascending and adjacent. */
2108 for (i = 1; i < nops; i++)
2112 order[i] = order[i - 1];
2113 for (j = 0; j < nops; j++)
2114 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2115 && (order[i] == order[i - 1]
2116 || unsorted_regs[j] < unsorted_regs[order[i]]))
2119 /* Have we found a suitable register? if not, one must be used more
2121 if (order[i] == order[i - 1])
2124 /* Is the memory address adjacent and ascending? */
2125 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2133 for (i = 0; i < nops; i++)
2134 regs[i] = unsorted_regs[order[i]];
2136 *load_offset = unsorted_offsets[order[0]];
2139 if (unsorted_offsets[order[0]] == 0)
2140 return 1; /* ldmia */
2142 if (unsorted_offsets[order[0]] == 4)
2143 return 2; /* ldmib */
2145 if (unsorted_offsets[order[nops - 1]] == 0)
2146 return 3; /* ldmda */
2148 if (unsorted_offsets[order[nops - 1]] == -4)
2149 return 4; /* ldmdb */
2151 /* Can't do it without setting up the offset, only do this if it takes
2152 no more than one insn. */
2153 return (const_ok_for_arm (unsorted_offsets[order[0]])
2154 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2158 emit_ldm_seq (operands, nops)
2164 HOST_WIDE_INT offset;
2168 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2171 strcpy (buf, "ldm%?ia\t");
2175 strcpy (buf, "ldm%?ib\t");
2179 strcpy (buf, "ldm%?da\t");
2183 strcpy (buf, "ldm%?db\t");
2188 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2189 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2192 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2193 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2195 output_asm_insn (buf, operands);
2197 strcpy (buf, "ldm%?ia\t");
2204 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2205 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2207 for (i = 1; i < nops; i++)
2208 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2209 reg_names[regs[i]]);
2211 strcat (buf, "}\t%@ phole ldm");
2213 output_asm_insn (buf, operands);
2218 store_multiple_sequence (operands, nops, regs, base, load_offset)
2223 HOST_WIDE_INT *load_offset;
2225 int unsorted_regs[4];
2226 HOST_WIDE_INT unsorted_offsets[4];
2231 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2232 extended if required. */
2233 if (nops < 2 || nops > 4)
2236 /* Loop over the operands and check that the memory references are
2237 suitable (ie immediate offsets from the same base register). At
2238 the same time, extract the target register, and the memory
2240 for (i = 0; i < nops; i++)
2245 if (GET_CODE (operands[nops + i]) != MEM)
2248 /* Don't reorder volatile memory references; it doesn't seem worth
2249 looking for the case where the order is ok anyway. */
2250 if (MEM_VOLATILE_P (operands[nops + i]))
2253 offset = const0_rtx;
2255 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2256 || (GET_CODE (reg) == SUBREG
2257 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2258 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2259 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2261 || (GET_CODE (reg) == SUBREG
2262 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2263 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2268 base_reg = REGNO(reg);
2269 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2270 ? REGNO (operands[i])
2271 : REGNO (SUBREG_REG (operands[i])));
2276 if (base_reg != REGNO (reg))
2277 /* Not addressed from the same base register. */
2280 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2281 ? REGNO (operands[i])
2282 : REGNO (SUBREG_REG (operands[i])));
2283 if (unsorted_regs[i] < unsorted_regs[order[0]])
2287 /* If it isn't an integer register, then we can't do this. */
2288 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2291 unsorted_offsets[i] = INTVAL (offset);
2294 /* Not a suitable memory address. */
2298 /* All the useful information has now been extracted from the
2299 operands into unsorted_regs and unsorted_offsets; additionally,
2300 order[0] has been set to the lowest numbered register in the
2301 list. Sort the registers into order, and check that the memory
2302 offsets are ascending and adjacent. */
2304 for (i = 1; i < nops; i++)
2308 order[i] = order[i - 1];
2309 for (j = 0; j < nops; j++)
2310 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2311 && (order[i] == order[i - 1]
2312 || unsorted_regs[j] < unsorted_regs[order[i]]))
2315 /* Have we found a suitable register? if not, one must be used more
2317 if (order[i] == order[i - 1])
2320 /* Is the memory address adjacent and ascending? */
2321 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2329 for (i = 0; i < nops; i++)
2330 regs[i] = unsorted_regs[order[i]];
2332 *load_offset = unsorted_offsets[order[0]];
2335 if (unsorted_offsets[order[0]] == 0)
2336 return 1; /* stmia */
2338 if (unsorted_offsets[order[0]] == 4)
2339 return 2; /* stmib */
2341 if (unsorted_offsets[order[nops - 1]] == 0)
2342 return 3; /* stmda */
2344 if (unsorted_offsets[order[nops - 1]] == -4)
2345 return 4; /* stmdb */
2351 emit_stm_seq (operands, nops)
2357 HOST_WIDE_INT offset;
2361 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2364 strcpy (buf, "stm%?ia\t");
2368 strcpy (buf, "stm%?ib\t");
2372 strcpy (buf, "stm%?da\t");
2376 strcpy (buf, "stm%?db\t");
2383 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2384 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2386 for (i = 1; i < nops; i++)
2387 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2388 reg_names[regs[i]]);
2390 strcat (buf, "}\t%@ phole stm");
2392 output_asm_insn (buf, operands);
2397 multi_register_push (op, mode)
2399 enum machine_mode mode;
2401 if (GET_CODE (op) != PARALLEL
2402 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
2403 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
2404 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
2411 /* Routines for use with attributes */
2414 const_pool_offset (symbol)
2417 return get_pool_offset (symbol) - get_pool_size () - get_prologue_size ();
2420 /* Return nonzero if ATTR is a valid attribute for DECL.
2421 ATTRIBUTES are any existing attributes and ARGS are the arguments
2424 Supported attributes:
2426 naked: don't output any prologue or epilogue code, the user is assumed
2427 to do the right thing. */
2430 arm_valid_machine_decl_attribute (decl, attributes, attr, args)
2436 if (args != NULL_TREE)
2439 if (is_attribute_p ("naked", attr))
2440 return TREE_CODE (decl) == FUNCTION_DECL;
2444 /* Return non-zero if FUNC is a naked function. */
2447 arm_naked_function_p (func)
2452 if (TREE_CODE (func) != FUNCTION_DECL)
2455 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
2456 return a != NULL_TREE;
2459 /* Routines for use in generating RTL */
2462 arm_gen_load_multiple (base_regno, count, from, up, write_back)
2471 int sign = up ? 1 : -1;
2473 result = gen_rtx (PARALLEL, VOIDmode,
2474 rtvec_alloc (count + (write_back ? 2 : 0)));
2477 XVECEXP (result, 0, 0)
2478 = gen_rtx (SET, GET_MODE (from), from,
2479 plus_constant (from, count * 4 * sign));
2484 for (j = 0; i < count; i++, j++)
2486 XVECEXP (result, 0, i)
2487 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, base_regno + j),
2488 gen_rtx (MEM, SImode,
2489 plus_constant (from, j * 4 * sign)));
2493 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from);
2499 arm_gen_store_multiple (base_regno, count, to, up, write_back)
2508 int sign = up ? 1 : -1;
2510 result = gen_rtx (PARALLEL, VOIDmode,
2511 rtvec_alloc (count + (write_back ? 2 : 0)));
2514 XVECEXP (result, 0, 0)
2515 = gen_rtx (SET, GET_MODE (to), to,
2516 plus_constant (to, count * 4 * sign));
2521 for (j = 0; i < count; i++, j++)
2523 XVECEXP (result, 0, i)
2524 = gen_rtx (SET, VOIDmode,
2525 gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign)),
2526 gen_rtx (REG, SImode, base_regno + j));
2530 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to);
2536 arm_gen_movstrqi (operands)
2539 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
2542 rtx st_src, st_dst, end_src, end_dst, fin_src, fin_dst;
2543 rtx part_bytes_reg = NULL;
2544 extern int optimize;
2546 if (GET_CODE (operands[2]) != CONST_INT
2547 || GET_CODE (operands[3]) != CONST_INT
2548 || INTVAL (operands[2]) > 64
2549 || INTVAL (operands[3]) & 3)
2552 st_dst = XEXP (operands[0], 0);
2553 st_src = XEXP (operands[1], 0);
2554 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
2555 fin_src = src = copy_to_mode_reg (SImode, st_src);
2557 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
2558 out_words_to_go = INTVAL (operands[2]) / 4;
2559 last_bytes = INTVAL (operands[2]) & 3;
2561 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
2562 part_bytes_reg = gen_rtx (REG, SImode, (in_words_to_go - 1) & 3);
2564 for (i = 0; in_words_to_go >= 2; i+=4)
2566 if (in_words_to_go > 4)
2567 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE));
2569 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
2572 if (out_words_to_go)
2574 if (out_words_to_go > 4)
2575 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE));
2576 else if (out_words_to_go != 1)
2577 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
2583 emit_move_insn (gen_rtx (MEM, SImode, dst),
2584 gen_rtx (REG, SImode, 0));
2585 if (last_bytes != 0)
2586 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
2590 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
2591 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
2594 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
2595 if (out_words_to_go)
2599 emit_move_insn (sreg = gen_reg_rtx (SImode), gen_rtx (MEM, SImode, src));
2600 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
2601 emit_move_insn (gen_rtx (MEM, SImode, dst), sreg);
2602 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
2605 if (in_words_to_go) /* Sanity check */
2611 if (in_words_to_go < 0)
2614 part_bytes_reg = copy_to_mode_reg (SImode, gen_rtx (MEM, SImode, src));
2617 if (BYTES_BIG_ENDIAN && last_bytes)
2619 rtx tmp = gen_reg_rtx (SImode);
2621 if (part_bytes_reg == NULL)
2624 /* The bytes we want are in the top end of the word */
2625 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
2626 GEN_INT (8 * (4 - last_bytes))));
2627 part_bytes_reg = tmp;
2631 emit_move_insn (gen_rtx (MEM, QImode,
2632 plus_constant (dst, last_bytes - 1)),
2633 gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
2636 tmp = gen_reg_rtx (SImode);
2637 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
2638 part_bytes_reg = tmp;
2647 if (part_bytes_reg == NULL)
2650 emit_move_insn (gen_rtx (MEM, QImode, dst),
2651 gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
2654 rtx tmp = gen_reg_rtx (SImode);
2656 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
2657 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
2658 part_bytes_reg = tmp;
2666 /* Generate a memory reference for a half word, such that it will be loaded
2667 into the top 16 bits of the word. We can assume that the address is
2668 known to be alignable and of the form reg, or plus (reg, const). */
2670 gen_rotated_half_load (memref)
2673 HOST_WIDE_INT offset = 0;
2674 rtx base = XEXP (memref, 0);
2676 if (GET_CODE (base) == PLUS)
2678 offset = INTVAL (XEXP (base, 1));
2679 base = XEXP (base, 0);
2682 /* If we aren't allowed to generate unalligned addresses, then fail. */
2683 if (TARGET_SHORT_BY_BYTES
2684 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
2687 base = gen_rtx (MEM, SImode, plus_constant (base, offset & ~2));
2689 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
2692 return gen_rtx (ROTATE, SImode, base, GEN_INT (16));
2695 static enum machine_mode
2696 select_dominance_cc_mode (op, x, y, cond_or)
2700 HOST_WIDE_INT cond_or;
2702 enum rtx_code cond1, cond2;
2705 /* Currently we will probably get the wrong result if the individual
2706 comparisons are not simple. This also ensures that it is safe to
2707 reverse a comparions if necessary. */
2708 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
2710 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
2715 cond1 = reverse_condition (cond1);
2717 /* If the comparisons are not equal, and one doesn't dominate the other,
2718 then we can't do this. */
2720 && ! comparison_dominates_p (cond1, cond2)
2721 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
2726 enum rtx_code temp = cond1;
2734 if (cond2 == EQ || ! cond_or)
2739 case LE: return CC_DLEmode;
2740 case LEU: return CC_DLEUmode;
2741 case GE: return CC_DGEmode;
2742 case GEU: return CC_DGEUmode;
2748 if (cond2 == LT || ! cond_or)
2757 if (cond2 == GT || ! cond_or)
2766 if (cond2 == LTU || ! cond_or)
2775 if (cond2 == GTU || ! cond_or)
2783 /* The remaining cases only occur when both comparisons are the
2805 arm_select_cc_mode (op, x, y)
2810 /* All floating point compares return CCFP if it is an equality
2811 comparison, and CCFPE otherwise. */
2812 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2813 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
2815 /* A compare with a shifted operand. Because of canonicalization, the
2816 comparison will have to be swapped when we emit the assembler. */
2817 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
2818 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
2819 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
2820 || GET_CODE (x) == ROTATERT))
2823 /* This is a special case, that is used by combine to alow a
2824 comarison of a shifted byte load to be split into a zero-extend
2825 followed by a comparison of the shifted integer (only valid for
2826 equalities and unsigned inequalites. */
2827 if (GET_MODE (x) == SImode
2828 && GET_CODE (x) == ASHIFT
2829 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
2830 && GET_CODE (XEXP (x, 0)) == SUBREG
2831 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
2832 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
2833 && (op == EQ || op == NE
2834 || op == GEU || op == GTU || op == LTU || op == LEU)
2835 && GET_CODE (y) == CONST_INT)
2838 /* An operation that sets the condition codes as a side-effect, the
2839 V flag is not set correctly, so we can only use comparisons where
2840 this doesn't matter. (For LT and GE we can use "mi" and "pl"
2842 if (GET_MODE (x) == SImode
2844 && (op == EQ || op == NE || op == LT || op == GE)
2845 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2846 || GET_CODE (x) == AND || GET_CODE (x) == IOR
2847 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
2848 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
2849 || GET_CODE (x) == LSHIFTRT
2850 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
2851 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
2854 /* A construct for a conditional compare, if the false arm contains
2855 0, then both conditions must be true, otherwise either condition
2856 must be true. Not all conditions are possible, so CCmode is
2857 returned if it can't be done. */
2858 if (GET_CODE (x) == IF_THEN_ELSE
2859 && (XEXP (x, 2) == const0_rtx
2860 || XEXP (x, 2) == const1_rtx)
2861 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
2862 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
2863 return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
2864 INTVAL (XEXP (x, 2)));
2866 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
2869 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
2870 && GET_CODE (x) == PLUS
2871 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
2877 /* X and Y are two things to compare using CODE. Emit the compare insn and
2878 return the rtx for register 0 in the proper mode. FP means this is a
2879 floating point compare: I don't think that it is needed on the arm. */
2882 gen_compare_reg (code, x, y, fp)
2886 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2887 rtx cc_reg = gen_rtx (REG, mode, 24);
2889 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
2890 gen_rtx (COMPARE, mode, x, y)));
2896 arm_reload_in_hi (operands)
2899 rtx base = find_replacement (&XEXP (operands[1], 0));
2901 emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx (MEM, QImode, base)));
2902 emit_insn (gen_zero_extendqisi2 (gen_rtx (SUBREG, SImode, operands[0], 0),
2903 gen_rtx (MEM, QImode,
2904 plus_constant (base, 1))));
2905 if (BYTES_BIG_ENDIAN)
2906 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
2908 gen_rtx (IOR, SImode,
2909 gen_rtx (ASHIFT, SImode,
2910 gen_rtx (SUBREG, SImode,
2915 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
2917 gen_rtx (IOR, SImode,
2918 gen_rtx (ASHIFT, SImode,
2921 gen_rtx (SUBREG, SImode, operands[0], 0))));
2925 arm_reload_out_hi (operands)
2928 rtx base = find_replacement (&XEXP (operands[0], 0));
2930 if (BYTES_BIG_ENDIAN)
2932 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
2933 gen_rtx (SUBREG, QImode, operands[1], 0)));
2934 emit_insn (gen_lshrsi3 (operands[2],
2935 gen_rtx (SUBREG, SImode, operands[1], 0),
2937 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
2938 gen_rtx (SUBREG, QImode, operands[2], 0)));
2942 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
2943 gen_rtx (SUBREG, QImode, operands[1], 0)));
2944 emit_insn (gen_lshrsi3 (operands[2],
2945 gen_rtx (SUBREG, SImode, operands[1], 0),
2947 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
2948 gen_rtx (SUBREG, QImode, operands[2], 0)));
2952 /* Check to see if a branch is forwards or backwards. Return TRUE if it
2956 arm_backwards_branch (from, to)
2959 return insn_addresses[to] <= insn_addresses[from];
2962 /* Check to see if a branch is within the distance that can be done using
2963 an arithmetic expression. */
2965 short_branch (from, to)
2968 int delta = insn_addresses[from] + 8 - insn_addresses[to];
2970 return abs (delta) < 980; /* A small margin for safety */
2973 /* Check to see that the insn isn't the target of the conditionalizing
2976 arm_insn_not_targeted (insn)
2979 return insn != arm_target_insn;
2983 /* Routines for manipulation of the constant pool. */
2984 /* This is unashamedly hacked from the version in sh.c, since the problem is
2985 extremely similar. */
2987 /* Arm instructions cannot load a large constant into a register,
2988 constants have to come from a pc relative load. The reference of a pc
2989 relative load instruction must be less than 1k infront of the instruction.
2990 This means that we often have to dump a constant inside a function, and
2991 generate code to branch around it.
2993 It is important to minimize this, since the branches will slow things
2994 down and make things bigger.
2996 Worst case code looks like:
3012 We fix this by performing a scan before scheduling, which notices which
3013 instructions need to have their operands fetched from the constant table
3014 and builds the table.
3019 scan, find an instruction which needs a pcrel move. Look forward, find th
3020 last barrier which is within MAX_COUNT bytes of the requirement.
3021 If there isn't one, make one. Process all the instructions between
3022 the find and the barrier.
3024 In the above example, we can tell that L3 is within 1k of L1, so
3025 the first move can be shrunk from the 2 insn+constant sequence into
3026 just 1 insn, and the constant moved to L3 to make:
3037 Then the second move becomes the target for the shortening process.
3043 rtx value; /* Value in table */
3044 HOST_WIDE_INT next_offset;
3045 enum machine_mode mode; /* Mode of value */
3048 /* The maximum number of constants that can fit into one pool, since
3049 the pc relative range is 0...1020 bytes and constants are at least 4
3052 #define MAX_POOL_SIZE (1020/4)
3053 static pool_node pool_vector[MAX_POOL_SIZE];
3054 static int pool_size;
3055 static rtx pool_vector_label;
3057 /* Add a constant to the pool and return its label. */
3058 static HOST_WIDE_INT
3059 add_constant (x, mode)
3061 enum machine_mode mode;
3065 HOST_WIDE_INT offset;
3067 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3068 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3069 x = get_pool_constant (XEXP (x, 0));
3070 #ifndef AOF_ASSEMBLER
3071 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3072 x = XVECEXP (x, 0, 0);
3075 /* First see if we've already got it */
3076 for (i = 0; i < pool_size; i++)
3078 if (GET_CODE (x) == pool_vector[i].value->code
3079 && mode == pool_vector[i].mode)
3081 if (GET_CODE (x) == CODE_LABEL)
3083 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3086 if (rtx_equal_p (x, pool_vector[i].value))
3087 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
3091 /* Need a new one */
3092 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
3095 pool_vector_label = gen_label_rtx ();
3097 pool_vector[pool_size].next_offset
3098 += (offset = pool_vector[pool_size - 1].next_offset);
3100 pool_vector[pool_size].value = x;
3101 pool_vector[pool_size].mode = mode;
3106 /* Output the literal table */
3113 scan = emit_label_after (gen_label_rtx (), scan);
3114 scan = emit_insn_after (gen_align_4 (), scan);
3115 scan = emit_label_after (pool_vector_label, scan);
3117 for (i = 0; i < pool_size; i++)
3119 pool_node *p = pool_vector + i;
3121 switch (GET_MODE_SIZE (p->mode))
3124 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
3128 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
3137 scan = emit_insn_after (gen_consttable_end (), scan);
3138 scan = emit_barrier_after (scan);
3142 /* Non zero if the src operand needs to be fixed up */
3144 fixit (src, mode, destreg)
3146 enum machine_mode mode;
3149 if (CONSTANT_P (src))
3151 if (GET_CODE (src) == CONST_INT)
3152 return (! const_ok_for_arm (INTVAL (src))
3153 && ! const_ok_for_arm (~INTVAL (src)));
3154 if (GET_CODE (src) == CONST_DOUBLE)
3155 return (GET_MODE (src) == VOIDmode
3157 || (! const_double_rtx_ok_for_fpu (src)
3158 && ! neg_const_double_rtx_ok_for_fpu (src)));
3159 return symbol_mentioned_p (src);
3161 #ifndef AOF_ASSEMBLER
3162 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
3166 return (mode == SImode && GET_CODE (src) == MEM
3167 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
3168 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
3171 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3173 find_barrier (from, max_count)
3178 rtx found_barrier = 0;
3180 while (from && count < max_count)
3182 if (GET_CODE (from) == BARRIER)
3183 found_barrier = from;
3185 /* Count the length of this insn */
3186 if (GET_CODE (from) == INSN
3187 && GET_CODE (PATTERN (from)) == SET
3188 && CONSTANT_P (SET_SRC (PATTERN (from)))
3189 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
3191 rtx src = SET_SRC (PATTERN (from));
3195 count += get_attr_length (from);
3197 from = NEXT_INSN (from);
3202 /* We didn't find a barrier in time to
3203 dump our stuff, so we'll make one */
3204 rtx label = gen_label_rtx ();
3207 from = PREV_INSN (from);
3209 from = get_last_insn ();
3211 /* Walk back to be just before any jump */
3212 while (GET_CODE (from) == JUMP_INSN
3213 || GET_CODE (from) == NOTE
3214 || GET_CODE (from) == CODE_LABEL)
3215 from = PREV_INSN (from);
3217 from = emit_jump_insn_after (gen_jump (label), from);
3218 JUMP_LABEL (from) = label;
3219 found_barrier = emit_barrier_after (from);
3220 emit_label_after (label, found_barrier);
3221 return found_barrier;
3224 return found_barrier;
3227 /* Non zero if the insn is a move instruction which needs to be fixed. */
3232 if (!INSN_DELETED_P (insn)
3233 && GET_CODE (insn) == INSN
3234 && GET_CODE (PATTERN (insn)) == SET)
3236 rtx pat = PATTERN (insn);
3237 rtx src = SET_SRC (pat);
3238 rtx dst = SET_DEST (pat);
3240 enum machine_mode mode = GET_MODE (dst);
3244 if (GET_CODE (dst) == REG)
3245 destreg = REGNO (dst);
3246 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
3247 destreg = REGNO (SUBREG_REG (dst));
3249 return fixit (src, mode, destreg);
3263 /* The ldr instruction can work with up to a 4k offset, and most constants
3264 will be loaded with one of these instructions; however, the adr
3265 instruction and the ldf instructions only work with a 1k offset. This
3266 code needs to be rewritten to use the 4k offset when possible, and to
3267 adjust when a 1k offset is needed. For now we just use a 1k offset
3271 /* Floating point operands can't work further than 1024 bytes from the
3272 PC, so to make things simple we restrict all loads for such functions.
3274 if (TARGET_HARD_FLOAT)
3275 for (regno = 16; regno < 24; regno++)
3276 if (regs_ever_live[regno])
3285 for (insn = first; insn; insn = NEXT_INSN (insn))
3287 if (broken_move (insn))
3289 /* This is a broken move instruction, scan ahead looking for
3290 a barrier to stick the constant table behind */
3292 rtx barrier = find_barrier (insn, count_size);
3294 /* Now find all the moves between the points and modify them */
3295 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3297 if (broken_move (scan))
3299 /* This is a broken move instruction, add it to the pool */
3300 rtx pat = PATTERN (scan);
3301 rtx src = SET_SRC (pat);
3302 rtx dst = SET_DEST (pat);
3303 enum machine_mode mode = GET_MODE (dst);
3304 HOST_WIDE_INT offset;
3310 /* If this is an HImode constant load, convert it into
3311 an SImode constant load. Since the register is always
3312 32 bits this is safe. We have to do this, since the
3313 load pc-relative instruction only does a 32-bit load. */
3317 if (GET_CODE (dst) != REG)
3319 PUT_MODE (dst, SImode);
3322 offset = add_constant (src, mode);
3323 addr = plus_constant (gen_rtx (LABEL_REF, VOIDmode,
3327 /* For wide moves to integer regs we need to split the
3328 address calculation off into a separate insn, so that
3329 the load can then be done with a load-multiple. This is
3330 safe, since we have already noted the length of such
3331 insns to be 8, and we are immediately over-writing the
3332 scratch we have grabbed with the final result. */
3333 if (GET_MODE_SIZE (mode) > 4
3334 && (scratch = REGNO (dst)) < 16)
3336 rtx reg = gen_rtx (REG, SImode, scratch);
3337 newinsn = emit_insn_after (gen_movaddr (reg, addr),
3342 newsrc = gen_rtx (MEM, mode, addr);
3344 /* Build a jump insn wrapper around the move instead
3345 of an ordinary insn, because we want to have room for
3346 the target label rtx in fld[7], which an ordinary
3347 insn doesn't have. */
3348 newinsn = emit_jump_insn_after (gen_rtx (SET, VOIDmode,
3351 JUMP_LABEL (newinsn) = pool_vector_label;
3353 /* But it's still an ordinary insn */
3354 PUT_CODE (newinsn, INSN);
3361 dump_table (barrier);
3368 /* Routines to output assembly language. */
3370 /* If the rtx is the correct value then return the string of the number.
3371 In this way we can ensure that valid double constants are generated even
3372 when cross compiling. */
3374 fp_immediate_constant (x)
3380 if (!fpa_consts_inited)
3383 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3384 for (i = 0; i < 8; i++)
3385 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3386 return strings_fpa[i];
3391 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
3393 fp_const_from_val (r)
3398 if (! fpa_consts_inited)
3401 for (i = 0; i < 8; i++)
3402 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
3403 return strings_fpa[i];
3408 /* Output the operands of a LDM/STM instruction to STREAM.
3409 MASK is the ARM register set mask of which only bits 0-15 are important.
3410 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
3411 must follow the register list. */
3414 print_multi_reg (stream, instr, mask, hat)
3420 int not_first = FALSE;
3422 fputc ('\t', stream);
3423 fprintf (stream, instr, REGISTER_PREFIX);
3424 fputs (", {", stream);
3425 for (i = 0; i < 16; i++)
3426 if (mask & (1 << i))
3429 fprintf (stream, ", ");
3430 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
3434 fprintf (stream, "}%s\n", hat ? "^" : "");
3437 /* Output a 'call' insn. */
3440 output_call (operands)
3443 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
3445 if (REGNO (operands[0]) == 14)
3447 operands[0] = gen_rtx (REG, SImode, 12);
3448 output_asm_insn ("mov%?\t%0, %|lr", operands);
3450 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3451 output_asm_insn ("mov%?\t%|pc, %0", operands);
3459 int something_changed = 0;
3461 int code = GET_CODE (x0);
3468 if (REGNO (x0) == 14)
3470 *x = gen_rtx (REG, SImode, 12);
3475 /* Scan through the sub-elements and change any references there */
3476 fmt = GET_RTX_FORMAT (code);
3477 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3479 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
3480 else if (fmt[i] == 'E')
3481 for (j = 0; j < XVECLEN (x0, i); j++)
3482 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
3483 return something_changed;
3487 /* Output a 'call' insn that is a reference in memory. */
3490 output_call_mem (operands)
3493 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
3494 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
3496 if (eliminate_lr2ip (&operands[0]))
3497 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
3499 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3500 output_asm_insn ("ldr%?\t%|pc, %0", operands);
3505 /* Output a move from arm registers to an fpu registers.
3506 OPERANDS[0] is an fpu register.
3507 OPERANDS[1] is the first registers of an arm register pair. */
3510 output_mov_long_double_fpu_from_arm (operands)
3513 int arm_reg0 = REGNO (operands[1]);
3519 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3520 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3521 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
3523 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
3524 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
3528 /* Output a move from an fpu register to arm registers.
3529 OPERANDS[0] is the first registers of an arm register pair.
3530 OPERANDS[1] is an fpu register. */
3533 output_mov_long_double_arm_from_fpu (operands)
3536 int arm_reg0 = REGNO (operands[0]);
3542 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3543 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3544 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
3546 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
3547 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
3551 /* Output a move from arm registers to arm registers of a long double
3552 OPERANDS[0] is the destination.
3553 OPERANDS[1] is the source. */
3555 output_mov_long_double_arm_from_arm (operands)
3558 /* We have to be careful here because the two might overlap */
3559 int dest_start = REGNO (operands[0]);
3560 int src_start = REGNO (operands[1]);
3564 if (dest_start < src_start)
3566 for (i = 0; i < 3; i++)
3568 ops[0] = gen_rtx (REG, SImode, dest_start + i);
3569 ops[1] = gen_rtx (REG, SImode, src_start + i);
3570 output_asm_insn ("mov%?\t%0, %1", ops);
3575 for (i = 2; i >= 0; i--)
3577 ops[0] = gen_rtx (REG, SImode, dest_start + i);
3578 ops[1] = gen_rtx (REG, SImode, src_start + i);
3579 output_asm_insn ("mov%?\t%0, %1", ops);
3587 /* Output a move from arm registers to an fpu registers.
3588 OPERANDS[0] is an fpu register.
3589 OPERANDS[1] is the first registers of an arm register pair. */
3592 output_mov_double_fpu_from_arm (operands)
3595 int arm_reg0 = REGNO (operands[1]);
3600 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3601 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3602 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
3603 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
3607 /* Output a move from an fpu register to arm registers.
3608 OPERANDS[0] is the first registers of an arm register pair.
3609 OPERANDS[1] is an fpu register. */
3612 output_mov_double_arm_from_fpu (operands)
3615 int arm_reg0 = REGNO (operands[0]);
3621 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3622 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3623 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
3624 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
3628 /* Output a move between double words.
3629 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
3630 or MEM<-REG and all MEMs must be offsettable addresses. */
3633 output_move_double (operands)
3636 enum rtx_code code0 = GET_CODE (operands[0]);
3637 enum rtx_code code1 = GET_CODE (operands[1]);
3642 int reg0 = REGNO (operands[0]);
3644 otherops[0] = gen_rtx (REG, SImode, 1 + reg0);
3647 int reg1 = REGNO (operands[1]);
3651 /* Ensure the second source is not overwritten */
3652 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
3653 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
3655 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
3657 else if (code1 == CONST_DOUBLE)
3659 if (GET_MODE (operands[1]) == DFmode)
3662 union real_extract u;
3664 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
3666 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
3667 otherops[1] = GEN_INT(l[1]);
3668 operands[1] = GEN_INT(l[0]);
3670 else if (GET_MODE (operands[1]) != VOIDmode)
3672 else if (WORDS_BIG_ENDIAN)
3675 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
3676 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
3681 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
3682 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
3684 output_mov_immediate (operands);
3685 output_mov_immediate (otherops);
3687 else if (code1 == CONST_INT)
3689 /* sign extend the intval into the high-order word */
3690 if (WORDS_BIG_ENDIAN)
3692 otherops[1] = operands[1];
3693 operands[1] = (INTVAL (operands[1]) < 0
3694 ? constm1_rtx : const0_rtx);
3697 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
3698 output_mov_immediate (otherops);
3699 output_mov_immediate (operands);
3701 else if (code1 == MEM)
3703 switch (GET_CODE (XEXP (operands[1], 0)))
3706 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
3710 abort (); /* Should never happen now */
3714 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
3718 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
3722 abort (); /* Should never happen now */
3727 output_asm_insn ("adr%?\t%0, %1", operands);
3728 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
3732 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
3734 otherops[0] = operands[0];
3735 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
3736 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
3737 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
3739 if (GET_CODE (otherops[2]) == CONST_INT)
3741 switch (INTVAL (otherops[2]))
3744 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
3747 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
3750 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
3753 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
3754 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
3756 output_asm_insn ("add%?\t%0, %1, %2", otherops);
3759 output_asm_insn ("add%?\t%0, %1, %2", otherops);
3762 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
3763 return "ldm%?ia\t%0, %M0";
3767 otherops[1] = adj_offsettable_operand (operands[1], 4);
3768 /* Take care of overlapping base/data reg. */
3769 if (reg_mentioned_p (operands[0], operands[1]))
3771 output_asm_insn ("ldr%?\t%0, %1", otherops);
3772 output_asm_insn ("ldr%?\t%0, %1", operands);
3776 output_asm_insn ("ldr%?\t%0, %1", operands);
3777 output_asm_insn ("ldr%?\t%0, %1", otherops);
3783 abort(); /* Constraints should prevent this */
3785 else if (code0 == MEM && code1 == REG)
3787 if (REGNO (operands[1]) == 12)
3790 switch (GET_CODE (XEXP (operands[0], 0)))
3793 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
3797 abort (); /* Should never happen now */
3801 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
3805 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
3809 abort (); /* Should never happen now */
3813 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
3815 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
3818 output_asm_insn ("stm%?db\t%m0, %M1", operands);
3822 output_asm_insn ("stm%?da\t%m0, %M1", operands);
3826 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
3833 otherops[0] = adj_offsettable_operand (operands[0], 4);
3834 otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1]));
3835 output_asm_insn ("str%?\t%1, %0", operands);
3836 output_asm_insn ("str%?\t%1, %0", otherops);
3840 abort(); /* Constraints should prevent this */
3846 /* Output an arbitrary MOV reg, #n.
3847 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
3850 output_mov_immediate (operands)
3853 HOST_WIDE_INT n = INTVAL (operands[1]);
3857 /* Try to use one MOV */
3858 if (const_ok_for_arm (n))
3860 output_asm_insn ("mov%?\t%0, %1", operands);
3864 /* Try to use one MVN */
3865 if (const_ok_for_arm (~n))
3867 operands[1] = GEN_INT (~n);
3868 output_asm_insn ("mvn%?\t%0, %1", operands);
3872 /* If all else fails, make it out of ORRs or BICs as appropriate. */
3874 for (i=0; i < 32; i++)
3878 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
3879 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
3882 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
3889 /* Output an ADD r, s, #n where n may be too big for one instruction. If
3890 adding zero to one register, output nothing. */
3893 output_add_immediate (operands)
3896 HOST_WIDE_INT n = INTVAL (operands[2]);
3898 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
3901 output_multi_immediate (operands,
3902 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
3905 output_multi_immediate (operands,
3906 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
3913 /* Output a multiple immediate operation.
3914 OPERANDS is the vector of operands referred to in the output patterns.
3915 INSTR1 is the output pattern to use for the first constant.
3916 INSTR2 is the output pattern to use for subsequent constants.
3917 IMMED_OP is the index of the constant slot in OPERANDS.
3918 N is the constant value. */
3921 output_multi_immediate (operands, instr1, instr2, immed_op, n)
3923 char *instr1, *instr2;
3927 #if HOST_BITS_PER_WIDE_INT > 32
3933 operands[immed_op] = const0_rtx;
3934 output_asm_insn (instr1, operands); /* Quick and easy output */
3939 char *instr = instr1;
3941 /* Note that n is never zero here (which would give no output) */
3942 for (i = 0; i < 32; i += 2)
3946 operands[immed_op] = GEN_INT (n & (255 << i));
3947 output_asm_insn (instr, operands);
3957 /* Return the appropriate ARM instruction for the operation code.
3958 The returned result should not be overwritten. OP is the rtx of the
3959 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
3963 arithmetic_instr (op, shift_first_arg)
3965 int shift_first_arg;
3967 switch (GET_CODE (op))
3973 return shift_first_arg ? "rsb" : "sub";
3990 /* Ensure valid constant shifts and return the appropriate shift mnemonic
3991 for the operation code. The returned result should not be overwritten.
3992 OP is the rtx code of the shift.
3993 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
3997 shift_op (op, amountp)
3999 HOST_WIDE_INT *amountp;
4002 enum rtx_code code = GET_CODE (op);
4004 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
4006 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
4007 *amountp = INTVAL (XEXP (op, 1));
4030 /* We never have to worry about the amount being other than a
4031 power of 2, since this case can never be reloaded from a reg. */
4033 *amountp = int_log2 (*amountp);
4044 /* This is not 100% correct, but follows from the desire to merge
4045 multiplication by a power of 2 with the recognizer for a
4046 shift. >=32 is not a valid shift for "asl", so we must try and
4047 output a shift that produces the correct arithmetical result.
4048 Using lsr #32 is identical except for the fact that the carry bit
4049 is not set correctly if we set the flags; but we never use the
4050 carry bit from such an operation, so we can ignore that. */
4051 if (code == ROTATERT)
4052 *amountp &= 31; /* Rotate is just modulo 32 */
4053 else if (*amountp != (*amountp & 31))
4060 /* Shifts of 0 are no-ops. */
4069 /* Obtain the shift from the POWER of two. */
4073 HOST_WIDE_INT power;
4075 HOST_WIDE_INT shift = 0;
4077 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
4087 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4088 /bin/as is horribly restrictive. */
4091 output_ascii_pseudo_op (stream, p, len)
4097 int len_so_far = 1000;
4098 int chars_so_far = 0;
4100 for (i = 0; i < len; i++)
4102 register int c = p[i];
4104 if (len_so_far > 50)
4107 fputs ("\"\n", stream);
4108 fputs ("\t.ascii\t\"", stream);
4110 arm_increase_location (chars_so_far);
4114 if (c == '\"' || c == '\\')
4120 if (c >= ' ' && c < 0177)
4127 fprintf (stream, "\\%03o", c);
4134 fputs ("\"\n", stream);
4135 arm_increase_location (chars_so_far);
4139 /* Try to determine whether a pattern really clobbers the link register.
4140 This information is useful when peepholing, so that lr need not be pushed
4141 if we combine a call followed by a return.
4142 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4143 such a check should not be needed because these only update an existing
4144 value within a register; the register must still be set elsewhere within
4148 pattern_really_clobbers_lr (x)
4153 switch (GET_CODE (x))
4156 switch (GET_CODE (SET_DEST (x)))
4159 return REGNO (SET_DEST (x)) == 14;
4162 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
4163 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
4165 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
4174 for (i = 0; i < XVECLEN (x, 0); i++)
4175 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
4180 switch (GET_CODE (XEXP (x, 0)))
4183 return REGNO (XEXP (x, 0)) == 14;
4186 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
4187 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
4203 function_really_clobbers_lr (first)
4208 for (insn = first; insn; insn = next_nonnote_insn (insn))
4210 switch (GET_CODE (insn))
4215 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
4220 if (pattern_really_clobbers_lr (PATTERN (insn)))
4225 /* Don't yet know how to handle those calls that are not to a
4227 if (GET_CODE (PATTERN (insn)) != PARALLEL)
4230 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
4233 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
4239 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
4245 default: /* Don't recognize it, be safe */
4249 /* A call can be made (by peepholing) not to clobber lr iff it is
4250 followed by a return. There may, however, be a use insn iff
4251 we are returning the result of the call.
4252 If we run off the end of the insn chain, then that means the
4253 call was at the end of the function. Unfortunately we don't
4254 have a return insn for the peephole to recognize, so we
4255 must reject this. (Can this be fixed by adding our own insn?) */
4256 if ((next = next_nonnote_insn (insn)) == NULL)
4259 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
4260 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4261 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
4262 == REGNO (XEXP (PATTERN (next), 0))))
4263 if ((next = next_nonnote_insn (next)) == NULL)
4266 if (GET_CODE (next) == JUMP_INSN
4267 && GET_CODE (PATTERN (next)) == RETURN)
4276 /* We have reached the end of the chain so lr was _not_ clobbered */
4281 output_return_instruction (operand, really_return, reverse)
4287 int reg, live_regs = 0;
4288 int volatile_func = (optimize > 0
4289 && TREE_THIS_VOLATILE (current_function_decl));
4291 return_used_this_function = 1;
4296 /* If this function was declared non-returning, and we have found a tail
4297 call, then we have to trust that the called function won't return. */
4298 if (! really_return)
4301 /* Otherwise, trap an attempted return by aborting. */
4303 ops[1] = gen_rtx (SYMBOL_REF, Pmode, "abort");
4304 assemble_external_libcall (ops[1]);
4305 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
4309 if (current_function_calls_alloca && ! really_return)
4312 for (reg = 0; reg <= 10; reg++)
4313 if (regs_ever_live[reg] && ! call_used_regs[reg])
4316 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
4319 if (frame_pointer_needed)
4324 if (lr_save_eliminated || ! regs_ever_live[14])
4327 if (frame_pointer_needed)
4329 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
4332 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
4334 for (reg = 0; reg <= 10; reg++)
4335 if (regs_ever_live[reg] && ! call_used_regs[reg])
4337 strcat (instr, "%|");
4338 strcat (instr, reg_names[reg]);
4340 strcat (instr, ", ");
4343 if (frame_pointer_needed)
4345 strcat (instr, "%|");
4346 strcat (instr, reg_names[11]);
4347 strcat (instr, ", ");
4348 strcat (instr, "%|");
4349 strcat (instr, reg_names[13]);
4350 strcat (instr, ", ");
4351 strcat (instr, "%|");
4352 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4356 strcat (instr, "%|");
4357 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4359 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
4360 output_asm_insn (instr, &operand);
4362 else if (really_return)
4364 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
4365 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
4366 output_asm_insn (instr, &operand);
4372 /* Return nonzero if optimizing and the current function is volatile.
4373 Such functions never return, and many memory cycles can be saved
4374 by not storing register values that will never be needed again.
4375 This optimization was added to speed up context switching in a
4376 kernel application. */
4379 arm_volatile_func ()
4381 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
4384 /* Return the size of the prologue. It's not too bad if we slightly
4388 get_prologue_size ()
4390 return profile_flag ? 12 : 0;
4393 /* The amount of stack adjustment that happens here, in output_return and in
4394 output_epilogue must be exactly the same as was calculated during reload,
4395 or things will point to the wrong place. The only time we can safely
4396 ignore this constraint is when a function has no arguments on the stack,
4397 no stack frame requirement and no live registers execpt for `lr'. If we
4398 can guarantee that by making all function calls into tail calls and that
4399 lr is not clobbered in any other way, then there is no need to push lr
4403 output_func_prologue (f, frame_size)
4407 int reg, live_regs_mask = 0;
4409 int volatile_func = (optimize > 0
4410 && TREE_THIS_VOLATILE (current_function_decl));
4412 /* Nonzero if we must stuff some register arguments onto the stack as if
4413 they were passed there. */
4414 int store_arg_regs = 0;
4416 if (arm_ccfsm_state || arm_target_insn)
4417 abort (); /* Sanity check */
4419 if (arm_naked_function_p (current_function_decl))
4422 return_used_this_function = 0;
4423 lr_save_eliminated = 0;
4425 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
4426 ASM_COMMENT_START, current_function_args_size,
4427 current_function_pretend_args_size, frame_size);
4428 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
4429 ASM_COMMENT_START, frame_pointer_needed,
4430 current_function_anonymous_args);
4433 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
4435 if (current_function_anonymous_args && current_function_pretend_args_size)
4438 for (reg = 0; reg <= 10; reg++)
4439 if (regs_ever_live[reg] && ! call_used_regs[reg])
4440 live_regs_mask |= (1 << reg);
4442 if (frame_pointer_needed)
4443 live_regs_mask |= 0xD800;
4444 else if (regs_ever_live[14])
4446 if (! current_function_args_size
4447 && ! function_really_clobbers_lr (get_insns ()))
4448 lr_save_eliminated = 1;
4450 live_regs_mask |= 0x4000;
4455 /* if a di mode load/store multiple is used, and the base register
4456 is r3, then r4 can become an ever live register without lr
4457 doing so, in this case we need to push lr as well, or we
4458 will fail to get a proper return. */
4460 live_regs_mask |= 0x4000;
4461 lr_save_eliminated = 0;
4465 if (lr_save_eliminated)
4466 fprintf (f,"\t%s I don't think this function clobbers lr\n",
4472 output_func_epilogue (f, frame_size)
4476 int reg, live_regs_mask = 0, code_size = 0;
4477 /* If we need this then it will always be at lesat this much */
4478 int floats_offset = 24;
4480 int volatile_func = (optimize > 0
4481 && TREE_THIS_VOLATILE (current_function_decl));
4483 if (use_return_insn() && return_used_this_function)
4485 if (frame_size && !(frame_pointer_needed || TARGET_APCS))
4492 /* Naked functions don't have epilogues. */
4493 if (arm_naked_function_p (current_function_decl))
4496 /* A volatile function should never return. Call abort. */
4499 rtx op = gen_rtx (SYMBOL_REF, Pmode, "abort");
4500 assemble_external_libcall (op);
4501 output_asm_insn ("bl\t%a0", &op);
4506 for (reg = 0; reg <= 10; reg++)
4507 if (regs_ever_live[reg] && ! call_used_regs[reg])
4509 live_regs_mask |= (1 << reg);
4513 if (frame_pointer_needed)
4515 for (reg = 23; reg > 15; reg--)
4516 if (regs_ever_live[reg] && ! call_used_regs[reg])
4518 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
4519 reg_names[reg], REGISTER_PREFIX, floats_offset);
4520 floats_offset += 12;
4524 live_regs_mask |= 0xA800;
4525 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
4526 TARGET_APCS_32 ? FALSE : TRUE);
4531 /* Restore stack pointer if necessary. */
4534 operands[0] = operands[1] = stack_pointer_rtx;
4535 operands[2] = gen_rtx (CONST_INT, VOIDmode, frame_size);
4536 output_add_immediate (operands);
4539 for (reg = 16; reg < 24; reg++)
4540 if (regs_ever_live[reg] && ! call_used_regs[reg])
4542 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
4543 reg_names[reg], REGISTER_PREFIX);
4546 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
4548 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
4549 TARGET_APCS_32 ? FALSE : TRUE);
4554 if (live_regs_mask || regs_ever_live[14])
4556 live_regs_mask |= 0x4000;
4557 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
4560 if (current_function_pretend_args_size)
4562 operands[0] = operands[1] = stack_pointer_rtx;
4563 operands[2] = gen_rtx (CONST_INT, VOIDmode,
4564 current_function_pretend_args_size);
4565 output_add_immediate (operands);
4567 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
4568 : "\tmovs\t%spc, %slr\n"),
4569 REGISTER_PREFIX, REGISTER_PREFIX, f);
4576 /* insn_addresses isn't allocated when not optimizing */
4577 /* ??? The previous comment is incorrect. Clarify. */
4580 arm_increase_location (code_size
4581 + insn_addresses[INSN_UID (get_last_insn ())]
4582 + get_prologue_size ());
4584 current_function_anonymous_args = 0;
4588 emit_multi_reg_push (mask)
4595 for (i = 0; i < 16; i++)
4596 if (mask & (1 << i))
4599 if (num_regs == 0 || num_regs > 16)
4602 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num_regs));
4604 for (i = 0; i < 16; i++)
4606 if (mask & (1 << i))
4609 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, BLKmode,
4610 gen_rtx (PRE_DEC, BLKmode,
4611 stack_pointer_rtx)),
4612 gen_rtx (UNSPEC, BLKmode,
4613 gen_rtvec (1, gen_rtx (REG, SImode, i)),
4619 for (j = 1, i++; j < num_regs; i++)
4621 if (mask & (1 << i))
4624 = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, i));
4632 arm_expand_prologue ()
4635 rtx amount = GEN_INT (- get_frame_size ());
4638 int live_regs_mask = 0;
4639 int store_arg_regs = 0;
4640 int volatile_func = (optimize > 0
4641 && TREE_THIS_VOLATILE (current_function_decl));
4643 /* Naked functions don't have prologues. */
4644 if (arm_naked_function_p (current_function_decl))
4647 if (current_function_anonymous_args && current_function_pretend_args_size)
4650 if (! volatile_func)
4651 for (reg = 0; reg <= 10; reg++)
4652 if (regs_ever_live[reg] && ! call_used_regs[reg])
4653 live_regs_mask |= 1 << reg;
4655 if (! volatile_func && regs_ever_live[14])
4656 live_regs_mask |= 0x4000;
4658 if (frame_pointer_needed)
4660 live_regs_mask |= 0xD800;
4661 emit_insn (gen_movsi (gen_rtx (REG, SImode, 12),
4662 stack_pointer_rtx));
4665 if (current_function_pretend_args_size)
4668 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
4671 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
4672 GEN_INT (-current_function_pretend_args_size)));
4677 /* If we have to push any regs, then we must push lr as well, or
4678 we won't get a proper return. */
4679 live_regs_mask |= 0x4000;
4680 emit_multi_reg_push (live_regs_mask);
4683 /* For now the integer regs are still pushed in output_func_epilogue (). */
4685 if (! volatile_func)
4686 for (reg = 23; reg > 15; reg--)
4687 if (regs_ever_live[reg] && ! call_used_regs[reg])
4688 emit_insn (gen_rtx (SET, VOIDmode,
4689 gen_rtx (MEM, XFmode,
4690 gen_rtx (PRE_DEC, XFmode,
4691 stack_pointer_rtx)),
4692 gen_rtx (REG, XFmode, reg)));
4694 if (frame_pointer_needed)
4695 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx (REG, SImode, 12),
4697 (-(4 + current_function_pretend_args_size)))));
4699 if (amount != const0_rtx)
4701 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
4702 emit_insn (gen_rtx (CLOBBER, VOIDmode,
4703 gen_rtx (MEM, BLKmode, stack_pointer_rtx)));
4706 /* If we are profiling, make sure no instructions are scheduled before
4707 the call to mcount. */
4708 if (profile_flag || profile_block_flag)
4709 emit_insn (gen_blockage ());
4713 /* If CODE is 'd', then the X is a condition operand and the instruction
4714 should only be executed if the condition is true.
4715 if CODE is 'D', then the X is a condition operand and the instruction
4716 should only be executed if the condition is false: however, if the mode
4717 of the comparison is CCFPEmode, then always execute the instruction -- we
4718 do this because in these circumstances !GE does not necessarily imply LT;
4719 in these cases the instruction pattern will take care to make sure that
4720 an instruction containing %d will follow, thereby undoing the effects of
4721 doing this instruction unconditionally.
4722 If CODE is 'N' then X is a floating point operand that must be negated
4724 If CODE is 'B' then output a bitwise inverted value of X (a const int).
4725 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
4728 arm_print_operand (stream, x, code)
4736 fputs (ASM_COMMENT_START, stream);
4740 fputs (REGISTER_PREFIX, stream);
4744 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
4745 fputs (arm_condition_codes[arm_current_cc], stream);
4751 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4752 r = REAL_VALUE_NEGATE (r);
4753 fprintf (stream, "%s", fp_const_from_val (&r));
4758 if (GET_CODE (x) == CONST_INT)
4760 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
4765 ARM_SIGN_EXTEND (~ INTVAL (x)));
4769 output_addr_const (stream, x);
4774 fprintf (stream, "%s", arithmetic_instr (x, 1));
4778 fprintf (stream, "%s", arithmetic_instr (x, 0));
4784 char *shift = shift_op (x, &val);
4788 fprintf (stream, ", %s ", shift_op (x, &val));
4790 arm_print_operand (stream, XEXP (x, 1), 0);
4793 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
4806 fputs (REGISTER_PREFIX, stream);
4807 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
4813 fputs (REGISTER_PREFIX, stream);
4814 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
4818 fputs (REGISTER_PREFIX, stream);
4819 if (GET_CODE (XEXP (x, 0)) == REG)
4820 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
4822 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
4826 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
4827 REGISTER_PREFIX, reg_names[REGNO (x) - 1
4828 + ((GET_MODE_SIZE (GET_MODE (x))
4829 + GET_MODE_SIZE (SImode) - 1)
4830 / GET_MODE_SIZE (SImode))]);
4835 fputs (arm_condition_codes[get_arm_condition_code (x)],
4841 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
4842 (get_arm_condition_code (x))],
4850 if (GET_CODE (x) == REG)
4852 fputs (REGISTER_PREFIX, stream);
4853 fputs (reg_names[REGNO (x)], stream);
4855 else if (GET_CODE (x) == MEM)
4857 output_memory_reference_mode = GET_MODE (x);
4858 output_address (XEXP (x, 0));
4860 else if (GET_CODE (x) == CONST_DOUBLE)
4861 fprintf (stream, "#%s", fp_immediate_constant (x));
4862 else if (GET_CODE (x) == NEG)
4863 abort (); /* This should never happen now. */
4866 fputc ('#', stream);
4867 output_addr_const (stream, x);
4872 /* Increase the `arm_text_location' by AMOUNT if we're in the text
4876 arm_increase_location (amount)
4879 if (in_text_section ())
4880 arm_text_location += amount;
4884 /* Output a label definition. If this label is within the .text segment, it
4885 is stored in OFFSET_TABLE, to be used when building `llc' instructions.
4886 Maybe GCC remembers names not starting with a `*' for a long time, but this
4887 is a minority anyway, so we just make a copy. Do not store the leading `*'
4888 if the name starts with one. */
4891 arm_asm_output_label (stream, name)
4895 char *real_name, *s;
4896 struct label_offset *cur;
4899 ARM_OUTPUT_LABEL (stream, name);
4900 if (! in_text_section ())
4905 real_name = xmalloc (1 + strlen (&name[1]));
4906 strcpy (real_name, &name[1]);
4910 real_name = xmalloc (2 + strlen (name));
4911 strcpy (real_name, USER_LABEL_PREFIX);
4912 strcat (real_name, name);
4914 for (s = real_name; *s; s++)
4917 hash = hash % LABEL_HASH_SIZE;
4918 cur = (struct label_offset *) xmalloc (sizeof (struct label_offset));
4919 cur->name = real_name;
4920 cur->offset = arm_text_location;
4921 cur->cdr = offset_table[hash];
4922 offset_table[hash] = cur;
4925 /* Output code resembling an .lcomm directive. /bin/as doesn't have this
4926 directive hence this hack, which works by reserving some `.space' in the
4927 bss segment directly.
4929 XXX This is a severe hack, which is guaranteed NOT to work since it doesn't
4930 define STATIC COMMON space but merely STATIC BSS space. */
4933 output_lcomm_directive (stream, name, size, align)
4939 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
4940 ARM_OUTPUT_LABEL (stream, name);
4941 fprintf (stream, "\t.space\t%d\n", size);
4944 /* A finite state machine takes care of noticing whether or not instructions
4945 can be conditionally executed, and thus decrease execution time and code
4946 size by deleting branch instructions. The fsm is controlled by
4947 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
4949 /* The state of the fsm controlling condition codes are:
4950 0: normal, do nothing special
4951 1: make ASM_OUTPUT_OPCODE not output this instruction
4952 2: make ASM_OUTPUT_OPCODE not output this instruction
4953 3: make instructions conditional
4954 4: make instructions conditional
4956 State transitions (state->state by whom under condition):
4957 0 -> 1 final_prescan_insn if the `target' is a label
4958 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
4959 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
4960 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
4961 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
4962 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
4963 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
4964 (the target insn is arm_target_insn).
4966 If the jump clobbers the conditions then we use states 2 and 4.
4968 A similar thing can be done with conditional return insns.
4970 XXX In case the `target' is an unconditional branch, this conditionalising
4971 of the instructions always reduces code size, but not always execution
4972 time. But then, I want to reduce the code size to somewhere near what
4973 /bin/cc produces. */
4975 /* Returns the index of the ARM condition code string in
4976 `arm_condition_codes'. COMPARISON should be an rtx like
4977 `(eq (...) (...))'. */
4979 static enum arm_cond_code
4980 get_arm_condition_code (comparison)
4983 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
4985 register enum rtx_code comp_code = GET_CODE (comparison);
4987 if (GET_MODE_CLASS (mode) != MODE_CC)
4988 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
4989 XEXP (comparison, 1));
4993 case CC_DNEmode: code = ARM_NE; goto dominance;
4994 case CC_DEQmode: code = ARM_EQ; goto dominance;
4995 case CC_DGEmode: code = ARM_GE; goto dominance;
4996 case CC_DGTmode: code = ARM_GT; goto dominance;
4997 case CC_DLEmode: code = ARM_LE; goto dominance;
4998 case CC_DLTmode: code = ARM_LT; goto dominance;
4999 case CC_DGEUmode: code = ARM_CS; goto dominance;
5000 case CC_DGTUmode: code = ARM_HI; goto dominance;
5001 case CC_DLEUmode: code = ARM_LS; goto dominance;
5002 case CC_DLTUmode: code = ARM_CC;
5005 if (comp_code != EQ && comp_code != NE)
5008 if (comp_code == EQ)
5009 return ARM_INVERSE_CONDITION_CODE (code);
5015 case NE: return ARM_NE;
5016 case EQ: return ARM_EQ;
5017 case GE: return ARM_PL;
5018 case LT: return ARM_MI;
5026 case NE: return ARM_NE;
5027 case EQ: return ARM_EQ;
5034 case GE: return ARM_GE;
5035 case GT: return ARM_GT;
5036 case LE: return ARM_LS;
5037 case LT: return ARM_MI;
5044 case NE: return ARM_NE;
5045 case EQ: return ARM_EQ;
5046 case GE: return ARM_LE;
5047 case GT: return ARM_LT;
5048 case LE: return ARM_GE;
5049 case LT: return ARM_GT;
5050 case GEU: return ARM_LS;
5051 case GTU: return ARM_CC;
5052 case LEU: return ARM_CS;
5053 case LTU: return ARM_HI;
5060 case LTU: return ARM_CS;
5061 case GEU: return ARM_CC;
5068 case NE: return ARM_NE;
5069 case EQ: return ARM_EQ;
5070 case GE: return ARM_GE;
5071 case GT: return ARM_GT;
5072 case LE: return ARM_LE;
5073 case LT: return ARM_LT;
5074 case GEU: return ARM_CS;
5075 case GTU: return ARM_HI;
5076 case LEU: return ARM_LS;
5077 case LTU: return ARM_CC;
5089 final_prescan_insn (insn, opvec, noperands)
5094 /* BODY will hold the body of INSN. */
5095 register rtx body = PATTERN (insn);
5097 /* This will be 1 if trying to repeat the trick, and things need to be
5098 reversed if it appears to fail. */
5101 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5102 taken are clobbered, even if the rtl suggests otherwise. It also
5103 means that we have to grub around within the jump expression to find
5104 out what the conditions are when the jump isn't taken. */
5105 int jump_clobbers = 0;
5107 /* If we start with a return insn, we only succeed if we find another one. */
5108 int seeking_return = 0;
5110 /* START_INSN will hold the insn from where we start looking. This is the
5111 first insn after the following code_label if REVERSE is true. */
5112 rtx start_insn = insn;
5114 /* If in state 4, check if the target branch is reached, in order to
5115 change back to state 0. */
5116 if (arm_ccfsm_state == 4)
5118 if (insn == arm_target_insn)
5120 arm_target_insn = NULL;
5121 arm_ccfsm_state = 0;
5126 /* If in state 3, it is possible to repeat the trick, if this insn is an
5127 unconditional branch to a label, and immediately following this branch
5128 is the previous target label which is only used once, and the label this
5129 branch jumps to is not too far off. */
5130 if (arm_ccfsm_state == 3)
5132 if (simplejump_p (insn))
5134 start_insn = next_nonnote_insn (start_insn);
5135 if (GET_CODE (start_insn) == BARRIER)
5137 /* XXX Isn't this always a barrier? */
5138 start_insn = next_nonnote_insn (start_insn);
5140 if (GET_CODE (start_insn) == CODE_LABEL
5141 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5142 && LABEL_NUSES (start_insn) == 1)
5147 else if (GET_CODE (body) == RETURN)
5149 start_insn = next_nonnote_insn (start_insn);
5150 if (GET_CODE (start_insn) == BARRIER)
5151 start_insn = next_nonnote_insn (start_insn);
5152 if (GET_CODE (start_insn) == CODE_LABEL
5153 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5154 && LABEL_NUSES (start_insn) == 1)
5166 if (arm_ccfsm_state != 0 && !reverse)
5168 if (GET_CODE (insn) != JUMP_INSN)
5171 /* This jump might be paralleled with a clobber of the condition codes
5172 the jump should always come first */
5173 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5174 body = XVECEXP (body, 0, 0);
5177 /* If this is a conditional return then we don't want to know */
5178 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5179 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
5180 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
5181 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
5186 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5187 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
5190 int fail = FALSE, succeed = FALSE;
5191 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5192 int then_not_else = TRUE;
5193 rtx this_insn = start_insn, label = 0;
5195 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5197 /* The code below is wrong for these, and I haven't time to
5198 fix it now. So we just do the safe thing and return. This
5199 whole function needs re-writing anyway. */
5204 /* Register the insn jumped to. */
5207 if (!seeking_return)
5208 label = XEXP (SET_SRC (body), 0);
5210 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
5211 label = XEXP (XEXP (SET_SRC (body), 1), 0);
5212 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
5214 label = XEXP (XEXP (SET_SRC (body), 2), 0);
5215 then_not_else = FALSE;
5217 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
5219 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
5222 then_not_else = FALSE;
5227 /* See how many insns this branch skips, and what kind of insns. If all
5228 insns are okay, and the label or unconditional branch to the same
5229 label is not too far away, succeed. */
5230 for (insns_skipped = 0;
5231 !fail && !succeed && insns_skipped++ < MAX_INSNS_SKIPPED;)
5235 this_insn = next_nonnote_insn (this_insn);
5239 scanbody = PATTERN (this_insn);
5241 switch (GET_CODE (this_insn))
5244 /* Succeed if it is the target label, otherwise fail since
5245 control falls in from somewhere else. */
5246 if (this_insn == label)
5250 arm_ccfsm_state = 2;
5251 this_insn = next_nonnote_insn (this_insn);
5254 arm_ccfsm_state = 1;
5262 /* Succeed if the following insn is the target label.
5264 If return insns are used then the last insn in a function
5265 will be a barrier. */
5266 this_insn = next_nonnote_insn (this_insn);
5267 if (this_insn && this_insn == label)
5271 arm_ccfsm_state = 2;
5272 this_insn = next_nonnote_insn (this_insn);
5275 arm_ccfsm_state = 1;
5283 /* If using 32-bit addresses the cc is not preserved over
5287 /* Succeed if the following insn is the target label,
5288 or if the following two insns are a barrier and
5289 the target label. */
5290 this_insn = next_nonnote_insn (this_insn);
5291 if (this_insn && GET_CODE (this_insn) == BARRIER)
5292 this_insn = next_nonnote_insn (this_insn);
5294 if (this_insn && this_insn == label
5295 && insns_skipped < MAX_INSNS_SKIPPED)
5299 arm_ccfsm_state = 2;
5300 this_insn = next_nonnote_insn (this_insn);
5303 arm_ccfsm_state = 1;
5312 /* If this is an unconditional branch to the same label, succeed.
5313 If it is to another label, do nothing. If it is conditional,
5315 /* XXX Probably, the test for the SET and the PC are unnecessary. */
5317 if (GET_CODE (scanbody) == SET
5318 && GET_CODE (SET_DEST (scanbody)) == PC)
5320 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
5321 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
5323 arm_ccfsm_state = 2;
5326 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
5329 else if (GET_CODE (scanbody) == RETURN
5332 arm_ccfsm_state = 2;
5335 else if (GET_CODE (scanbody) == PARALLEL)
5337 switch (get_attr_conds (this_insn))
5349 /* Instructions using or affecting the condition codes make it
5351 if ((GET_CODE (scanbody) == SET
5352 || GET_CODE (scanbody) == PARALLEL)
5353 && get_attr_conds (this_insn) != CONDS_NOCOND)
5363 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
5364 arm_target_label = CODE_LABEL_NUMBER (label);
5365 else if (seeking_return || arm_ccfsm_state == 2)
5367 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
5369 this_insn = next_nonnote_insn (this_insn);
5370 if (this_insn && (GET_CODE (this_insn) == BARRIER
5371 || GET_CODE (this_insn) == CODE_LABEL))
5376 /* Oh, dear! we ran off the end.. give up */
5377 recog (PATTERN (insn), insn, NULL_PTR);
5378 arm_ccfsm_state = 0;
5379 arm_target_insn = NULL;
5382 arm_target_insn = this_insn;
5391 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
5393 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
5394 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5395 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
5396 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5400 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
5403 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
5407 if (reverse || then_not_else)
5408 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5410 /* restore recog_operand (getting the attributes of other insns can
5411 destroy this array, but final.c assumes that it remains intact
5412 across this call; since the insn has been recognized already we
5413 call recog direct). */
5414 recog (PATTERN (insn), insn, NULL_PTR);
5418 #ifdef AOF_ASSEMBLER
5419 /* Special functions only needed when producing AOF syntax assembler. */
5421 int arm_text_section_count = 1;
5426 static char buf[100];
5427 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
5428 arm_text_section_count++);
5430 strcat (buf, ", PIC, REENTRANT");
5434 static int arm_data_section_count = 1;
5439 static char buf[100];
5440 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
5444 /* The AOF assembler is religiously strict about declarations of
5445 imported and exported symbols, so that it is impossible to declare
5446 a function as imported near the begining of the file, and then to
5447 export it later on. It is, however, possible to delay the decision
5448 until all the functions in the file have been compiled. To get
5449 around this, we maintain a list of the imports and exports, and
5450 delete from it any that are subsequently defined. At the end of
5451 compilation we spit the remainder of the list out before the END
5456 struct import *next;
5460 static struct import *imports_list = NULL;
5463 aof_add_import (name)
5468 for (new = imports_list; new; new = new->next)
5469 if (new->name == name)
5472 new = (struct import *) xmalloc (sizeof (struct import));
5473 new->next = imports_list;
5479 aof_delete_import (name)
5482 struct import **old;
5484 for (old = &imports_list; *old; old = & (*old)->next)
5486 if ((*old)->name == name)
5488 *old = (*old)->next;
5494 int arm_main_function = 0;
5497 aof_dump_imports (f)
5500 /* The AOF assembler needs this to cause the startup code to be extracted
5501 from the library. Brining in __main causes the whole thing to work
5503 if (arm_main_function)
5506 fputs ("\tIMPORT __main\n", f);
5507 fputs ("\tDCD __main\n", f);
5510 /* Now dump the remaining imports. */
5511 while (imports_list)
5513 fprintf (f, "\tIMPORT\t");
5514 assemble_name (f, imports_list->name);
5516 imports_list = imports_list->next;
5519 #endif /* AOF_ASSEMBLER */