1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 static int max_insns_skipped = 5;
46 extern FILE * asm_out_file;
47 /* Some function declarations. */
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char * output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((rtx, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char * shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
71 static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));
73 /* True if we are currently building a constant table. */
74 int making_const_table;
76 /* Define the information needed to generate branch insns. This is
77 stored from the compare operation. */
78 rtx arm_compare_op0, arm_compare_op1;
80 /* What type of floating point are we tuning for? */
81 enum floating_point_type arm_fpu;
83 /* What type of floating point instructions are available? */
84 enum floating_point_type arm_fpu_arch;
86 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
87 enum prog_mode_type arm_prgmode;
89 /* Set by the -mfp=... option */
90 const char * target_fp_name = NULL;
92 /* Used to parse -mstructure_size_boundary command line option. */
93 const char * structure_size_string = NULL;
94 int arm_structure_size_boundary = 32; /* Used to be 8 */
96 /* Bit values used to identify processor capabilities. */
97 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
98 #define FL_FAST_MULT 0x02 /* Fast multiply */
99 #define FL_MODE26 0x04 /* 26-bit mode support */
100 #define FL_MODE32 0x08 /* 32-bit mode support */
101 #define FL_ARCH4 0x10 /* Architecture rel 4 */
102 #define FL_THUMB 0x20 /* Thumb aware */
103 #define FL_LDSCHED 0x40 /* Load scheduling necessary */
104 #define FL_STRONG 0x80 /* StrongARM */
106 /* The bits in this mask specify which instructions we are allowed to generate. */
107 static int insn_flags = 0;
108 /* The bits in this mask specify which instruction scheduling options should
109 be used. Note - there is an overlap with the FL_FAST_MULT. For some
110 hardware we want to be able to generate the multiply instructions, but to
111 tune as if they were not present in the architecture. */
112 static int tune_flags = 0;
114 /* The following are used in the arm.md file as equivalents to bits
115 in the above two flag variables. */
117 /* Nonzero if this is an "M" variant of the processor. */
118 int arm_fast_multiply = 0;
120 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
123 /* Nonzero if this chip can benefit from load scheduling. */
124 int arm_ld_sched = 0;
126 /* Nonzero if this chip is a StrongARM. */
127 int arm_is_strong = 0;
129 /* Nonzero if this chip is a an ARM6 or an ARM7. */
130 int arm_is_6_or_7 = 0;
132 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
133 must report the mode of the memory reference from PRINT_OPERAND to
134 PRINT_OPERAND_ADDRESS. */
135 enum machine_mode output_memory_reference_mode;
137 /* Nonzero if the prologue must setup `fp'. */
138 int current_function_anonymous_args;
140 /* The register number to be used for the PIC offset register. */
141 int arm_pic_register = 9;
143 /* Location counter of .text segment. */
144 int arm_text_location = 0;
146 /* Set to one if we think that lr is only saved because of subroutine calls,
147 but all of these can be `put after' return insns */
148 int lr_save_eliminated;
150 /* Set to 1 when a return insn is output, this means that the epilogue
152 static int return_used_this_function;
154 /* Set to 1 after arm_reorg has started. Reset to start at the start of
155 the next function. */
156 static int after_arm_reorg = 0;
158 /* The maximum number of insns to be used when loading a constant. */
159 static int arm_constant_limit = 3;
161 /* For an explanation of these variables, see final_prescan_insn below. */
163 enum arm_cond_code arm_current_cc;
165 int arm_target_label;
167 /* The condition codes of the ARM, and the inverse function. */
168 char * arm_condition_codes[] =
170 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
171 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
174 static enum arm_cond_code get_arm_condition_code ();
176 #define streq(string1, string2) (strcmp (string1, string2) == 0)
178 /* Initialization code */
186 /* Not all of these give usefully different compilation alternatives,
187 but there is no simple way of generalizing them. */
188 static struct processors all_cores[] =
192 {"arm2", FL_CO_PROC | FL_MODE26 },
193 {"arm250", FL_CO_PROC | FL_MODE26 },
194 {"arm3", FL_CO_PROC | FL_MODE26 },
195 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
196 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
197 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
198 {"arm610", FL_MODE26 | FL_MODE32 },
199 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
200 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
201 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */
202 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* but only with D, (and I), */
203 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */
204 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* so arm7m is sometimes used. */
205 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
206 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
208 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm710", FL_MODE26 | FL_MODE32 },
210 {"arm710c", FL_MODE26 | FL_MODE32 },
211 {"arm7100", FL_MODE26 | FL_MODE32 },
212 {"arm7500", FL_MODE26 | FL_MODE32 },
213 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu. */
214 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
215 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
216 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
217 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
218 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
219 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
220 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
221 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
226 static struct processors all_architectures[] =
228 /* ARM Architectures */
230 {"armv2", FL_CO_PROC | FL_MODE26 },
231 {"armv2a", FL_CO_PROC | FL_MODE26 },
232 {"armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
233 {"armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
234 {"armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
235 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
236 implementations that support it, so we will leave it out for now. */
237 {"armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
241 /* This is a magic stucture. The 'string' field is magically filled in
242 with a pointer to the value specified by the user on the command line
243 assuming that the user has specified such a value. */
245 struct arm_cpu_select arm_select[] =
247 /* string name processors */
248 { NULL, "-mcpu=", all_cores },
249 { NULL, "-march=", all_architectures },
250 { NULL, "-mtune=", all_cores }
253 /* Return the number of bits set in value' */
258 unsigned int count = 0;
262 value &= ~(value & - value);
269 /* Fix up any incompatible options that the user has specified.
270 This has now turned into a maze. */
272 arm_override_options ()
276 /* Set up the flags based on the cpu/architecture selected by the user. */
277 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
279 struct arm_cpu_select * ptr = arm_select + i;
281 if (ptr->string != NULL && ptr->string[0] != '\0')
283 const struct processors * sel;
285 for (sel = ptr->processors; sel->name != NULL; sel ++)
286 if (streq (ptr->string, sel->name))
289 tune_flags = sel->flags;
292 /* If we have been given an architecture and a processor
293 make sure that they are compatible. We only generate
294 a warning though, and we prefer the CPU over the
296 if (insn_flags != 0 && (insn_flags ^ sel->flags))
297 warning ("switch -mcpu=%s conflicts with -march= switch",
300 insn_flags = sel->flags;
306 if (sel->name == NULL)
307 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
311 /* If the user did not specify a processor, choose one for them. */
314 struct processors * sel;
316 static struct cpu_default
323 { TARGET_CPU_arm2, "arm2" },
324 { TARGET_CPU_arm6, "arm6" },
325 { TARGET_CPU_arm610, "arm610" },
326 { TARGET_CPU_arm710, "arm710" },
327 { TARGET_CPU_arm7m, "arm7m" },
328 { TARGET_CPU_arm7500fe, "arm7500fe" },
329 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
330 { TARGET_CPU_arm8, "arm8" },
331 { TARGET_CPU_arm810, "arm810" },
332 { TARGET_CPU_arm9, "arm9" },
333 { TARGET_CPU_strongarm, "strongarm" },
334 { TARGET_CPU_generic, "arm" },
337 struct cpu_default * def;
339 /* Find the default. */
340 for (def = cpu_defaults; def->name; def ++)
341 if (def->cpu == TARGET_CPU_DEFAULT)
344 /* Make sure we found the default CPU. */
345 if (def->name == NULL)
348 /* Find the default CPU's flags. */
349 for (sel = all_cores; sel->name != NULL; sel ++)
350 if (streq (def->name, sel->name))
353 if (sel->name == NULL)
356 insn_flags = sel->flags;
358 /* Now check to see if the user has specified some command line
359 switch that require certain abilities from the cpu. */
362 if (TARGET_THUMB_INTERWORK)
364 sought |= (FL_THUMB | FL_MODE32);
366 /* Force apcs-32 to be used for interworking. */
367 target_flags |= ARM_FLAG_APCS_32;
369 /* There are no ARM processor that supports both APCS-26 and
370 interworking. Therefore we force FL_MODE26 to be removed
371 from insn_flags here (if it was set), so that the search
372 below will always be able to find a compatible processor. */
373 insn_flags &= ~ FL_MODE26;
376 if (! TARGET_APCS_32)
379 if (sought != 0 && ((sought & insn_flags) != sought))
381 /* Try to locate a CPU type that supports all of the abilities
382 of the default CPU, plus the extra abilities requested by
384 for (sel = all_cores; sel->name != NULL; sel ++)
385 if ((sel->flags & sought) == (sought | insn_flags))
388 if (sel->name == NULL)
390 unsigned int current_bit_count = 0;
391 struct processors * best_fit = NULL;
393 /* Ideally we would like to issue an error message here
394 saying that it was not possible to find a CPU compatible
395 with the default CPU, but which also supports the command
396 line options specified by the programmer, and so they
397 ought to use the -mcpu=<name> command line option to
398 override the default CPU type.
400 Unfortunately this does not work with multilibing. We
401 need to be able to support multilibs for -mapcs-26 and for
402 -mthumb-interwork and there is no CPU that can support both
403 options. Instead if we cannot find a cpu that has both the
404 characteristics of the default cpu and the given command line
405 options we scan the array again looking for a best match. */
406 for (sel = all_cores; sel->name != NULL; sel ++)
407 if ((sel->flags & sought) == sought)
411 count = bit_count (sel->flags & insn_flags);
413 if (count >= current_bit_count)
416 current_bit_count = count;
420 if (best_fit == NULL)
426 insn_flags = sel->flags;
430 /* If tuning has not been specified, tune for whichever processor or
431 architecture has been selected. */
433 tune_flags = insn_flags;
435 /* Make sure that the processor choice does not conflict with any of the
436 other command line choices. */
437 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
439 /* If APCS-32 was not the default then it must have been set by the
440 user, so issue a warning message. If the user has specified
441 "-mapcs-32 -mcpu=arm2" then we loose here. */
442 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
443 warning ("target CPU does not support APCS-32" );
444 target_flags &= ~ ARM_FLAG_APCS_32;
446 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
448 warning ("target CPU does not support APCS-26" );
449 target_flags |= ARM_FLAG_APCS_32;
452 if (TARGET_THUMB_INTERWORK && !(insn_flags & FL_THUMB))
454 warning ("target CPU does not support interworking" );
455 target_flags &= ~ARM_FLAG_THUMB;
458 /* If interworking is enabled then APCS-32 must be selected as well. */
459 if (TARGET_THUMB_INTERWORK)
461 if (! TARGET_APCS_32)
462 warning ("interworking forces APCS-32 to be used" );
463 target_flags |= ARM_FLAG_APCS_32;
466 if (TARGET_APCS_STACK && ! TARGET_APCS)
468 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
469 target_flags |= ARM_FLAG_APCS_FRAME;
472 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
473 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
475 if (TARGET_POKE_FUNCTION_NAME)
476 target_flags |= ARM_FLAG_APCS_FRAME;
478 if (TARGET_APCS_REENT && flag_pic)
479 fatal ("-fpic and -mapcs-reent are incompatible");
481 if (TARGET_APCS_REENT)
482 warning ("APCS reentrant code not supported. Ignored");
484 /* If stack checking is disabled, we can use r10 as the PIC register,
485 which keeps r9 available. */
486 if (flag_pic && ! TARGET_APCS_STACK)
487 arm_pic_register = 10;
489 /* Well, I'm about to have a go, but pic is NOT going to be compatible
490 with APCS reentrancy, since that requires too much support in the
491 assembler and linker, and the ARMASM assembler seems to lack some
492 required directives. */
494 warning ("Position independent code not supported");
496 if (TARGET_APCS_FLOAT)
497 warning ("Passing floating point arguments in fp regs not yet supported");
499 /* Initialise boolean versions of the flags, for use in the arm.md file. */
500 arm_fast_multiply = insn_flags & FL_FAST_MULT;
501 arm_arch4 = insn_flags & FL_ARCH4;
503 arm_ld_sched = tune_flags & FL_LDSCHED;
504 arm_is_strong = tune_flags & FL_STRONG;
505 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
506 && !(tune_flags & FL_ARCH4));
508 /* Default value for floating point code... if no co-processor
509 bus, then schedule for emulated floating point. Otherwise,
510 assume the user has an FPA.
511 Note: this does not prevent use of floating point instructions,
512 -msoft-float does that. */
513 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
517 if (streq (target_fp_name, "2"))
518 arm_fpu_arch = FP_SOFT2;
519 else if (streq (target_fp_name, "3"))
520 arm_fpu_arch = FP_SOFT3;
522 fatal ("Invalid floating point emulation option: -mfpe-%s",
526 arm_fpu_arch = FP_DEFAULT;
528 if (TARGET_FPE && arm_fpu != FP_HARD)
531 /* For arm2/3 there is no need to do any scheduling if there is only
532 a floating point emulator, or we are doing software floating-point. */
533 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && (tune_flags & FL_MODE32) == 0)
534 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
536 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
538 if (structure_size_string != NULL)
540 int size = strtol (structure_size_string, NULL, 0);
542 if (size == 8 || size == 32)
543 arm_structure_size_boundary = size;
545 warning ("Structure size boundary can only be set to 8 or 32");
548 /* If optimizing for space, don't synthesize constants.
549 For processors with load scheduling, it never costs more than 2 cycles
550 to load a constant, and the load scheduler may well reduce that to 1. */
551 if (optimize_size || (tune_flags & FL_LDSCHED))
552 arm_constant_limit = 1;
554 /* If optimizing for size, bump the number of instructions that we
555 are prepared to conditionally execute (even on a StrongARM).
556 Otherwise for the StrongARM, which has early execution of branches,
557 a sequence that is worth skipping is shorter. */
559 max_insns_skipped = 6;
560 else if (arm_is_strong)
561 max_insns_skipped = 3;
564 /* Return 1 if it is possible to return using a single instruction */
567 use_return_insn (iscond)
572 if (!reload_completed
573 || current_function_pretend_args_size
574 || current_function_anonymous_args
575 || ((get_frame_size () + current_function_outgoing_args_size != 0)
576 && !(TARGET_APCS && frame_pointer_needed)))
579 /* Can't be done if interworking with Thumb, and any registers have been
580 stacked. Similarly, on StrongARM, conditional returns are expensive
581 if they aren't taken and registers have been stacked. */
582 if (iscond && arm_is_strong && frame_pointer_needed)
584 if ((iscond && arm_is_strong)
585 || TARGET_THUMB_INTERWORK)
586 for (regno = 0; regno < 16; regno++)
587 if (regs_ever_live[regno] && ! call_used_regs[regno])
590 /* Can't be done if any of the FPU regs are pushed, since this also
592 for (regno = 16; regno < 24; regno++)
593 if (regs_ever_live[regno] && ! call_used_regs[regno])
596 /* If a function is naked, don't use the "return" insn. */
597 if (arm_naked_function_p (current_function_decl))
603 /* Return TRUE if int I is a valid immediate ARM constant. */
609 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
611 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
612 be all zero, or all one. */
613 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
614 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
615 != ((~(unsigned HOST_WIDE_INT) 0)
616 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
619 /* Fast return for 0 and powers of 2 */
620 if ((i & (i - 1)) == 0)
625 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
628 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
629 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
630 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
635 /* Return true if I is a valid constant for the operation CODE. */
637 const_ok_for_op (i, code)
641 if (const_ok_for_arm (i))
647 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
649 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
655 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
662 /* Emit a sequence of insns to handle a large constant.
663 CODE is the code of the operation required, it can be any of SET, PLUS,
664 IOR, AND, XOR, MINUS;
665 MODE is the mode in which the operation is being performed;
666 VAL is the integer to operate on;
667 SOURCE is the other operand (a register, or a null-pointer for SET);
668 SUBTARGETS means it is safe to create scratch registers if that will
669 either produce a simpler sequence, or we will want to cse the values.
670 Return value is the number of insns emitted. */
673 arm_split_constant (code, mode, val, target, source, subtargets)
675 enum machine_mode mode;
681 if (subtargets || code == SET
682 || (GET_CODE (target) == REG && GET_CODE (source) == REG
683 && REGNO (target) != REGNO (source)))
685 /* After arm_reorg has been called, we can't fix up expensive
686 constants by pushing them into memory so we must synthesise
687 them in-line, regardless of the cost. This is only likely to
688 be more costly on chips that have load delay slots and we are
689 compiling without running the scheduler (so no splitting
690 occurred before the final instruction emission).
692 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
694 if (! after_arm_reorg
695 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
696 > arm_constant_limit + (code != SET)))
700 /* Currently SET is the only monadic value for CODE, all
701 the rest are diadic. */
702 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
707 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
709 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
710 /* For MINUS, the value is subtracted from, since we never
711 have subtraction of a constant. */
713 emit_insn (gen_rtx_SET (VOIDmode, target,
714 gen_rtx (code, mode, temp, source)));
716 emit_insn (gen_rtx_SET (VOIDmode, target,
717 gen_rtx (code, mode, source, temp)));
723 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
726 /* As above, but extra parameter GENERATE which, if clear, suppresses
729 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
731 enum machine_mode mode;
740 int can_negate_initial = 0;
743 int num_bits_set = 0;
744 int set_sign_bit_copies = 0;
745 int clear_sign_bit_copies = 0;
746 int clear_zero_bit_copies = 0;
747 int set_zero_bit_copies = 0;
749 unsigned HOST_WIDE_INT temp1, temp2;
750 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
752 /* find out which operations are safe for a given CODE. Also do a quick
753 check for degenerate cases; these can occur when DImode operations
765 can_negate_initial = 1;
769 if (remainder == 0xffffffff)
772 emit_insn (gen_rtx_SET (VOIDmode, target,
773 GEN_INT (ARM_SIGN_EXTEND (val))));
778 if (reload_completed && rtx_equal_p (target, source))
781 emit_insn (gen_rtx_SET (VOIDmode, target, source));
790 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
793 if (remainder == 0xffffffff)
795 if (reload_completed && rtx_equal_p (target, source))
798 emit_insn (gen_rtx_SET (VOIDmode, target, source));
807 if (reload_completed && rtx_equal_p (target, source))
810 emit_insn (gen_rtx_SET (VOIDmode, target, source));
813 if (remainder == 0xffffffff)
816 emit_insn (gen_rtx_SET (VOIDmode, target,
817 gen_rtx_NOT (mode, source)));
821 /* We don't know how to handle this yet below. */
825 /* We treat MINUS as (val - source), since (source - val) is always
826 passed as (source + (-val)). */
830 emit_insn (gen_rtx_SET (VOIDmode, target,
831 gen_rtx_NEG (mode, source)));
834 if (const_ok_for_arm (val))
837 emit_insn (gen_rtx_SET (VOIDmode, target,
838 gen_rtx_MINUS (mode, GEN_INT (val),
850 /* If we can do it in one insn get out quickly */
851 if (const_ok_for_arm (val)
852 || (can_negate_initial && const_ok_for_arm (-val))
853 || (can_invert && const_ok_for_arm (~val)))
856 emit_insn (gen_rtx_SET (VOIDmode, target,
857 (source ? gen_rtx (code, mode, source,
864 /* Calculate a few attributes that may be useful for specific
867 for (i = 31; i >= 0; i--)
869 if ((remainder & (1 << i)) == 0)
870 clear_sign_bit_copies++;
875 for (i = 31; i >= 0; i--)
877 if ((remainder & (1 << i)) != 0)
878 set_sign_bit_copies++;
883 for (i = 0; i <= 31; i++)
885 if ((remainder & (1 << i)) == 0)
886 clear_zero_bit_copies++;
891 for (i = 0; i <= 31; i++)
893 if ((remainder & (1 << i)) != 0)
894 set_zero_bit_copies++;
902 /* See if we can do this by sign_extending a constant that is known
903 to be negative. This is a good, way of doing it, since the shift
904 may well merge into a subsequent insn. */
905 if (set_sign_bit_copies > 1)
908 (temp1 = ARM_SIGN_EXTEND (remainder
909 << (set_sign_bit_copies - 1))))
913 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
914 emit_insn (gen_rtx_SET (VOIDmode, new_src,
916 emit_insn (gen_ashrsi3 (target, new_src,
917 GEN_INT (set_sign_bit_copies - 1)));
921 /* For an inverted constant, we will need to set the low bits,
922 these will be shifted out of harm's way. */
923 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
924 if (const_ok_for_arm (~temp1))
928 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
929 emit_insn (gen_rtx_SET (VOIDmode, new_src,
931 emit_insn (gen_ashrsi3 (target, new_src,
932 GEN_INT (set_sign_bit_copies - 1)));
938 /* See if we can generate this by setting the bottom (or the top)
939 16 bits, and then shifting these into the other half of the
940 word. We only look for the simplest cases, to do more would cost
941 too much. Be careful, however, not to generate this when the
942 alternative would take fewer insns. */
943 if (val & 0xffff0000)
945 temp1 = remainder & 0xffff0000;
946 temp2 = remainder & 0x0000ffff;
948 /* Overlaps outside this range are best done using other methods. */
949 for (i = 9; i < 24; i++)
951 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
952 && ! const_ok_for_arm (temp2))
954 rtx new_src = (subtargets
955 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
957 insns = arm_gen_constant (code, mode, temp2, new_src,
958 source, subtargets, generate);
961 emit_insn (gen_rtx_SET
964 gen_rtx_ASHIFT (mode, source,
971 /* Don't duplicate cases already considered. */
972 for (i = 17; i < 24; i++)
974 if (((temp1 | (temp1 >> i)) == remainder)
975 && ! const_ok_for_arm (temp1))
977 rtx new_src = (subtargets
978 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
980 insns = arm_gen_constant (code, mode, temp1, new_src,
981 source, subtargets, generate);
985 (gen_rtx_SET (VOIDmode, target,
988 gen_rtx_LSHIFTRT (mode, source,
999 /* If we have IOR or XOR, and the constant can be loaded in a
1000 single instruction, and we can find a temporary to put it in,
1001 then this can be done in two instructions instead of 3-4. */
1003 /* TARGET can't be NULL if SUBTARGETS is 0 */
1004 || (reload_completed && ! reg_mentioned_p (target, source)))
1006 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1010 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1012 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1013 emit_insn (gen_rtx_SET (VOIDmode, target,
1014 gen_rtx (code, mode, source, sub)));
1023 if (set_sign_bit_copies > 8
1024 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1028 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1029 rtx shift = GEN_INT (set_sign_bit_copies);
1031 emit_insn (gen_rtx_SET (VOIDmode, sub,
1033 gen_rtx_ASHIFT (mode,
1036 emit_insn (gen_rtx_SET (VOIDmode, target,
1038 gen_rtx_LSHIFTRT (mode, sub,
1044 if (set_zero_bit_copies > 8
1045 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1049 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1050 rtx shift = GEN_INT (set_zero_bit_copies);
1052 emit_insn (gen_rtx_SET (VOIDmode, sub,
1054 gen_rtx_LSHIFTRT (mode,
1057 emit_insn (gen_rtx_SET (VOIDmode, target,
1059 gen_rtx_ASHIFT (mode, sub,
1065 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1069 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1070 emit_insn (gen_rtx_SET (VOIDmode, sub,
1071 gen_rtx_NOT (mode, source)));
1074 sub = gen_reg_rtx (mode);
1075 emit_insn (gen_rtx_SET (VOIDmode, sub,
1076 gen_rtx_AND (mode, source,
1078 emit_insn (gen_rtx_SET (VOIDmode, target,
1079 gen_rtx_NOT (mode, sub)));
1086 /* See if two shifts will do 2 or more insn's worth of work. */
1087 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1089 HOST_WIDE_INT shift_mask = ((0xffffffff
1090 << (32 - clear_sign_bit_copies))
1093 if ((remainder | shift_mask) != 0xffffffff)
1097 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1098 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1099 new_src, source, subtargets, 1);
1104 rtx targ = subtargets ? NULL_RTX : target;
1105 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1106 targ, source, subtargets, 0);
1112 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1113 rtx shift = GEN_INT (clear_sign_bit_copies);
1115 emit_insn (gen_ashlsi3 (new_src, source, shift));
1116 emit_insn (gen_lshrsi3 (target, new_src, shift));
1122 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1124 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1126 if ((remainder | shift_mask) != 0xffffffff)
1130 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1132 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1133 new_src, source, subtargets, 1);
1138 rtx targ = subtargets ? NULL_RTX : target;
1140 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1141 targ, source, subtargets, 0);
1147 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1148 rtx shift = GEN_INT (clear_zero_bit_copies);
1150 emit_insn (gen_lshrsi3 (new_src, source, shift));
1151 emit_insn (gen_ashlsi3 (target, new_src, shift));
1163 for (i = 0; i < 32; i++)
1164 if (remainder & (1 << i))
1167 if (code == AND || (can_invert && num_bits_set > 16))
1168 remainder = (~remainder) & 0xffffffff;
1169 else if (code == PLUS && num_bits_set > 16)
1170 remainder = (-remainder) & 0xffffffff;
1177 /* Now try and find a way of doing the job in either two or three
1179 We start by looking for the largest block of zeros that are aligned on
1180 a 2-bit boundary, we then fill up the temps, wrapping around to the
1181 top of the word when we drop off the bottom.
1182 In the worst case this code should produce no more than four insns. */
1185 int best_consecutive_zeros = 0;
1187 for (i = 0; i < 32; i += 2)
1189 int consecutive_zeros = 0;
1191 if (! (remainder & (3 << i)))
1193 while ((i < 32) && ! (remainder & (3 << i)))
1195 consecutive_zeros += 2;
1198 if (consecutive_zeros > best_consecutive_zeros)
1200 best_consecutive_zeros = consecutive_zeros;
1201 best_start = i - consecutive_zeros;
1207 /* Now start emitting the insns, starting with the one with the highest
1208 bit set: we do this so that the smallest number will be emitted last;
1209 this is more likely to be combinable with addressing insns. */
1217 if (remainder & (3 << (i - 2)))
1222 temp1 = remainder & ((0x0ff << end)
1223 | ((i < end) ? (0xff >> (32 - end)) : 0));
1224 remainder &= ~temp1;
1231 emit_insn (gen_rtx_SET (VOIDmode,
1232 new_src = (subtargets
1233 ? gen_reg_rtx (mode)
1236 ? ~temp1 : temp1)));
1237 else if (code == MINUS)
1238 emit_insn (gen_rtx_SET (VOIDmode,
1239 new_src = (subtargets
1240 ? gen_reg_rtx (mode)
1242 gen_rtx (code, mode, GEN_INT (temp1),
1245 emit_insn (gen_rtx_SET (VOIDmode,
1246 new_src = (remainder
1248 ? gen_reg_rtx (mode)
1251 gen_rtx (code, mode, source,
1252 GEN_INT (can_invert ? ~temp1
1264 else if (code == MINUS)
1271 } while (remainder);
1276 /* Canonicalize a comparison so that we are more likely to recognize it.
1277 This can be done for a few constant compares, where we can make the
1278 immediate value easier to load. */
1280 arm_canonicalize_comparison (code, op1)
1284 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1294 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1296 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1298 *op1 = GEN_INT (i+1);
1299 return code == GT ? GE : LT;
1305 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1306 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1308 *op1 = GEN_INT (i-1);
1309 return code == GE ? GT : LE;
1315 if (i != ~((unsigned HOST_WIDE_INT) 0)
1316 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1318 *op1 = GEN_INT (i + 1);
1319 return code == GTU ? GEU : LTU;
1326 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1328 *op1 = GEN_INT (i - 1);
1329 return code == GEU ? GTU : LEU;
1340 /* Decide whether a type should be returned in memory (true)
1341 or in a register (false). This is called by the macro
1342 RETURN_IN_MEMORY. */
1344 arm_return_in_memory (type)
1347 if (! AGGREGATE_TYPE_P (type))
1349 /* All simple types are returned in registers. */
1352 else if (int_size_in_bytes (type) > 4)
1354 /* All structures/unions bigger than one word are returned in memory. */
1357 else if (TREE_CODE (type) == RECORD_TYPE)
1361 /* For a struct the APCS says that we must return in a register if
1362 every addressable element has an offset of zero. For practical
1363 purposes this means that the structure can have at most one non
1364 bit-field element and that this element must be the first one in
1367 /* Find the first field, ignoring non FIELD_DECL things which will
1368 have been created by C++. */
1369 for (field = TYPE_FIELDS (type);
1370 field && TREE_CODE (field) != FIELD_DECL;
1371 field = TREE_CHAIN (field))
1375 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1377 /* Now check the remaining fields, if any. */
1378 for (field = TREE_CHAIN (field);
1380 field = TREE_CHAIN (field))
1382 if (TREE_CODE (field) != FIELD_DECL)
1385 if (! DECL_BIT_FIELD_TYPE (field))
1391 else if (TREE_CODE (type) == UNION_TYPE)
1395 /* Unions can be returned in registers if every element is
1396 integral, or can be returned in an integer register. */
1397 for (field = TYPE_FIELDS (type);
1399 field = TREE_CHAIN (field))
1401 if (TREE_CODE (field) != FIELD_DECL)
1404 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1407 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1414 /* XXX Not sure what should be done for other aggregates, so put them in
1420 legitimate_pic_operand_p (x)
1423 if (CONSTANT_P (x) && flag_pic
1424 && (GET_CODE (x) == SYMBOL_REF
1425 || (GET_CODE (x) == CONST
1426 && GET_CODE (XEXP (x, 0)) == PLUS
1427 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1434 legitimize_pic_address (orig, mode, reg)
1436 enum machine_mode mode;
1439 if (GET_CODE (orig) == SYMBOL_REF)
1441 rtx pic_ref, address;
1447 if (reload_in_progress || reload_completed)
1450 reg = gen_reg_rtx (Pmode);
1455 #ifdef AOF_ASSEMBLER
1456 /* The AOF assembler can generate relocations for these directly, and
1457 understands that the PIC register has to be added into the offset.
1459 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1462 address = gen_reg_rtx (Pmode);
1466 emit_insn (gen_pic_load_addr (address, orig));
1468 pic_ref = gen_rtx_MEM (Pmode,
1469 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1471 RTX_UNCHANGING_P (pic_ref) = 1;
1472 insn = emit_move_insn (reg, pic_ref);
1474 current_function_uses_pic_offset_table = 1;
1475 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1477 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1481 else if (GET_CODE (orig) == CONST)
1485 if (GET_CODE (XEXP (orig, 0)) == PLUS
1486 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1491 if (reload_in_progress || reload_completed)
1494 reg = gen_reg_rtx (Pmode);
1497 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1499 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1500 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1501 base == reg ? 0 : reg);
1506 if (GET_CODE (offset) == CONST_INT)
1508 /* The base register doesn't really matter, we only want to
1509 test the index for the appropriate mode. */
1510 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1512 if (! reload_in_progress && ! reload_completed)
1513 offset = force_reg (Pmode, offset);
1518 if (GET_CODE (offset) == CONST_INT)
1519 return plus_constant_for_output (base, INTVAL (offset));
1522 if (GET_MODE_SIZE (mode) > 4
1523 && (GET_MODE_CLASS (mode) == MODE_INT
1524 || TARGET_SOFT_FLOAT))
1526 emit_insn (gen_addsi3 (reg, base, offset));
1530 return gen_rtx_PLUS (Pmode, base, offset);
1532 else if (GET_CODE (orig) == LABEL_REF)
1533 current_function_uses_pic_offset_table = 1;
1552 #ifndef AOF_ASSEMBLER
1553 rtx l1, pic_tmp, pic_tmp2, seq;
1554 rtx global_offset_table;
1556 if (current_function_uses_pic_offset_table == 0)
1563 l1 = gen_label_rtx ();
1565 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1566 /* On the ARM the PC register contains 'dot + 8' at the time of the
1568 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1569 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1570 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1572 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1574 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1575 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1577 seq = gen_sequence ();
1579 emit_insn_after (seq, get_insns ());
1581 /* Need to emit this whether or not we obey regdecls,
1582 since setjmp/longjmp can cause life info to screw up. */
1583 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1584 #endif /* AOF_ASSEMBLER */
1587 #define REG_OR_SUBREG_REG(X) \
1588 (GET_CODE (X) == REG \
1589 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1591 #define REG_OR_SUBREG_RTX(X) \
1592 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1594 #define ARM_FRAME_RTX(X) \
1595 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1596 || (X) == arg_pointer_rtx)
1599 arm_rtx_costs (x, code)
1603 enum machine_mode mode = GET_MODE (x);
1604 enum rtx_code subcode;
1610 /* Memory costs quite a lot for the first word, but subsequent words
1611 load at the equivalent of a single insn each. */
1612 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1613 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1620 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1627 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1629 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1630 + ((GET_CODE (XEXP (x, 0)) == REG
1631 || (GET_CODE (XEXP (x, 0)) == SUBREG
1632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1634 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1635 || (GET_CODE (XEXP (x, 0)) == SUBREG
1636 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1638 + ((GET_CODE (XEXP (x, 1)) == REG
1639 || (GET_CODE (XEXP (x, 1)) == SUBREG
1640 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1641 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1646 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1647 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1648 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1649 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1652 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1653 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1654 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1655 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1657 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1658 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1659 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1662 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1663 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1664 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1665 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1666 || subcode == ASHIFTRT || subcode == LSHIFTRT
1667 || subcode == ROTATE || subcode == ROTATERT
1669 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1670 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1671 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1672 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1673 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1674 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1675 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1680 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1681 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1682 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1683 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1684 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1688 case AND: case XOR: case IOR:
1691 /* Normally the frame registers will be spilt into reg+const during
1692 reload, so it is a bad idea to combine them with other instructions,
1693 since then they might not be moved outside of loops. As a compromise
1694 we allow integration with ops that have a constant as their second
1696 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1697 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1698 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1699 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1700 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1704 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1705 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1706 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1707 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1710 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1711 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1712 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1713 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1714 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1717 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1718 return (1 + extra_cost
1719 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1720 || subcode == LSHIFTRT || subcode == ASHIFTRT
1721 || subcode == ROTATE || subcode == ROTATERT
1723 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1724 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1725 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1726 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1727 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1728 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1734 /* There is no point basing this on the tuning, since it is always the
1735 fast variant if it exists at all */
1736 if (arm_fast_multiply && mode == DImode
1737 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1738 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1739 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1742 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1746 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1748 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1749 & (unsigned HOST_WIDE_INT) 0xffffffff);
1750 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1752 /* Tune as appropriate */
1753 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1755 for (j = 0; i && j < 32; j += booth_unit_size)
1757 i >>= booth_unit_size;
1764 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1765 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1766 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1769 if (arm_fast_multiply && mode == SImode
1770 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1771 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1772 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1773 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1774 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1775 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1780 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1781 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1785 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1787 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1790 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1798 return 4 + (mode == DImode ? 4 : 0);
1801 if (GET_MODE (XEXP (x, 0)) == QImode)
1802 return (4 + (mode == DImode ? 4 : 0)
1803 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1806 switch (GET_MODE (XEXP (x, 0)))
1809 return (1 + (mode == DImode ? 4 : 0)
1810 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1813 return (4 + (mode == DImode ? 4 : 0)
1814 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1817 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1830 arm_adjust_cost (insn, link, dep, cost)
1838 /* XXX This is not strictly true for the FPA. */
1839 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
1840 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
1843 if ((i_pat = single_set (insn)) != NULL
1844 && GET_CODE (SET_SRC (i_pat)) == MEM
1845 && (d_pat = single_set (dep)) != NULL
1846 && GET_CODE (SET_DEST (d_pat)) == MEM)
1848 /* This is a load after a store, there is no conflict if the load reads
1849 from a cached area. Assume that loads from the stack, and from the
1850 constant pool are cached, and that others will miss. This is a
1853 /* debug_rtx (insn);
1856 fprintf (stderr, "costs %d\n", cost); */
1858 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1859 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1860 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1861 || reg_mentioned_p (hard_frame_pointer_rtx,
1862 XEXP (SET_SRC (i_pat), 0)))
1864 /* fprintf (stderr, "***** Now 1\n"); */
1872 /* This code has been fixed for cross compilation. */
1874 static int fpa_consts_inited = 0;
1876 char *strings_fpa[8] = {
1878 "4", "5", "0.5", "10"
1881 static REAL_VALUE_TYPE values_fpa[8];
1889 for (i = 0; i < 8; i++)
1891 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1895 fpa_consts_inited = 1;
1898 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1901 const_double_rtx_ok_for_fpu (x)
1907 if (!fpa_consts_inited)
1910 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1911 if (REAL_VALUE_MINUS_ZERO (r))
1914 for (i = 0; i < 8; i++)
1915 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1921 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1924 neg_const_double_rtx_ok_for_fpu (x)
1930 if (!fpa_consts_inited)
1933 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1934 r = REAL_VALUE_NEGATE (r);
1935 if (REAL_VALUE_MINUS_ZERO (r))
1938 for (i = 0; i < 8; i++)
1939 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1945 /* Predicates for `match_operand' and `match_operator'. */
1947 /* s_register_operand is the same as register_operand, but it doesn't accept
1950 This function exists because at the time it was put in it led to better
1951 code. SUBREG(MEM) always needs a reload in the places where
1952 s_register_operand is used, and this seemed to lead to excessive
1956 s_register_operand (op, mode)
1958 enum machine_mode mode;
1960 if (GET_MODE (op) != mode && mode != VOIDmode)
1963 if (GET_CODE (op) == SUBREG)
1964 op = SUBREG_REG (op);
1966 /* We don't consider registers whose class is NO_REGS
1967 to be a register operand. */
1968 return (GET_CODE (op) == REG
1969 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1970 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1973 /* Only accept reg, subreg(reg), const_int. */
1976 reg_or_int_operand (op, mode)
1978 enum machine_mode mode;
1980 if (GET_CODE (op) == CONST_INT)
1983 if (GET_MODE (op) != mode && mode != VOIDmode)
1986 if (GET_CODE (op) == SUBREG)
1987 op = SUBREG_REG (op);
1989 /* We don't consider registers whose class is NO_REGS
1990 to be a register operand. */
1991 return (GET_CODE (op) == REG
1992 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1993 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1996 /* Return 1 if OP is an item in memory, given that we are in reload. */
1999 reload_memory_operand (op, mode)
2001 enum machine_mode mode ATTRIBUTE_UNUSED;
2003 int regno = true_regnum (op);
2005 return (! CONSTANT_P (op)
2007 || (GET_CODE (op) == REG
2008 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2011 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2012 memory access (architecture V4) */
2014 bad_signed_byte_operand (op, mode)
2016 enum machine_mode mode;
2018 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2023 /* A sum of anything more complex than reg + reg or reg + const is bad */
2024 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2025 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2026 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2027 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2030 /* Big constants are also bad */
2031 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2032 && (INTVAL (XEXP (op, 1)) > 0xff
2033 || -INTVAL (XEXP (op, 1)) > 0xff))
2036 /* Everything else is good, or can will automatically be made so. */
2040 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2043 arm_rhs_operand (op, mode)
2045 enum machine_mode mode;
2047 return (s_register_operand (op, mode)
2048 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2051 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2055 arm_rhsm_operand (op, mode)
2057 enum machine_mode mode;
2059 return (s_register_operand (op, mode)
2060 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2061 || memory_operand (op, mode));
2064 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2065 constant that is valid when negated. */
2068 arm_add_operand (op, mode)
2070 enum machine_mode mode;
2072 return (s_register_operand (op, mode)
2073 || (GET_CODE (op) == CONST_INT
2074 && (const_ok_for_arm (INTVAL (op))
2075 || const_ok_for_arm (-INTVAL (op)))));
2079 arm_not_operand (op, mode)
2081 enum machine_mode mode;
2083 return (s_register_operand (op, mode)
2084 || (GET_CODE (op) == CONST_INT
2085 && (const_ok_for_arm (INTVAL (op))
2086 || const_ok_for_arm (~INTVAL (op)))));
2089 /* Return TRUE if the operand is a memory reference which contains an
2090 offsettable address. */
2092 offsettable_memory_operand (op, mode)
2094 enum machine_mode mode;
2096 if (mode == VOIDmode)
2097 mode = GET_MODE (op);
2099 return (mode == GET_MODE (op)
2100 && GET_CODE (op) == MEM
2101 && offsettable_address_p (reload_completed | reload_in_progress,
2102 mode, XEXP (op, 0)));
2105 /* Return TRUE if the operand is a memory reference which is, or can be
2106 made word aligned by adjusting the offset. */
2108 alignable_memory_operand (op, mode)
2110 enum machine_mode mode;
2114 if (mode == VOIDmode)
2115 mode = GET_MODE (op);
2117 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2122 return ((GET_CODE (reg = op) == REG
2123 || (GET_CODE (op) == SUBREG
2124 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2125 || (GET_CODE (op) == PLUS
2126 && GET_CODE (XEXP (op, 1)) == CONST_INT
2127 && (GET_CODE (reg = XEXP (op, 0)) == REG
2128 || (GET_CODE (XEXP (op, 0)) == SUBREG
2129 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2130 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2133 /* Similar to s_register_operand, but does not allow hard integer
2136 f_register_operand (op, mode)
2138 enum machine_mode mode;
2140 if (GET_MODE (op) != mode && mode != VOIDmode)
2143 if (GET_CODE (op) == SUBREG)
2144 op = SUBREG_REG (op);
2146 /* We don't consider registers whose class is NO_REGS
2147 to be a register operand. */
2148 return (GET_CODE (op) == REG
2149 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2150 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2153 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2156 fpu_rhs_operand (op, mode)
2158 enum machine_mode mode;
2160 if (s_register_operand (op, mode))
2162 else if (GET_CODE (op) == CONST_DOUBLE)
2163 return (const_double_rtx_ok_for_fpu (op));
2169 fpu_add_operand (op, mode)
2171 enum machine_mode mode;
2173 if (s_register_operand (op, mode))
2175 else if (GET_CODE (op) == CONST_DOUBLE)
2176 return (const_double_rtx_ok_for_fpu (op)
2177 || neg_const_double_rtx_ok_for_fpu (op));
2182 /* Return nonzero if OP is a constant power of two. */
2185 power_of_two_operand (op, mode)
2187 enum machine_mode mode ATTRIBUTE_UNUSED;
2189 if (GET_CODE (op) == CONST_INT)
2191 HOST_WIDE_INT value = INTVAL(op);
2192 return value != 0 && (value & (value - 1)) == 0;
2197 /* Return TRUE for a valid operand of a DImode operation.
2198 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2199 Note that this disallows MEM(REG+REG), but allows
2200 MEM(PRE/POST_INC/DEC(REG)). */
2203 di_operand (op, mode)
2205 enum machine_mode mode;
2207 if (s_register_operand (op, mode))
2210 if (GET_CODE (op) == SUBREG)
2211 op = SUBREG_REG (op);
2213 switch (GET_CODE (op))
2220 return memory_address_p (DImode, XEXP (op, 0));
2227 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2228 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2229 Note that this disallows MEM(REG+REG), but allows
2230 MEM(PRE/POST_INC/DEC(REG)). */
2233 soft_df_operand (op, mode)
2235 enum machine_mode mode;
2237 if (s_register_operand (op, mode))
2240 if (GET_CODE (op) == SUBREG)
2241 op = SUBREG_REG (op);
2243 switch (GET_CODE (op))
2249 return memory_address_p (DFmode, XEXP (op, 0));
2256 /* Return TRUE for valid index operands. */
2259 index_operand (op, mode)
2261 enum machine_mode mode;
2263 return (s_register_operand(op, mode)
2264 || (immediate_operand (op, mode)
2265 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2268 /* Return TRUE for valid shifts by a constant. This also accepts any
2269 power of two on the (somewhat overly relaxed) assumption that the
2270 shift operator in this case was a mult. */
2273 const_shift_operand (op, mode)
2275 enum machine_mode mode;
2277 return (power_of_two_operand (op, mode)
2278 || (immediate_operand (op, mode)
2279 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2282 /* Return TRUE for arithmetic operators which can be combined with a multiply
2286 shiftable_operator (x, mode)
2288 enum machine_mode mode;
2290 if (GET_MODE (x) != mode)
2294 enum rtx_code code = GET_CODE (x);
2296 return (code == PLUS || code == MINUS
2297 || code == IOR || code == XOR || code == AND);
2301 /* Return TRUE for shift operators. */
2304 shift_operator (x, mode)
2306 enum machine_mode mode;
2308 if (GET_MODE (x) != mode)
2312 enum rtx_code code = GET_CODE (x);
2315 return power_of_two_operand (XEXP (x, 1), mode);
2317 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2318 || code == ROTATERT);
2322 int equality_operator (x, mode)
2324 enum machine_mode mode ATTRIBUTE_UNUSED;
2326 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2329 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2332 minmax_operator (x, mode)
2334 enum machine_mode mode;
2336 enum rtx_code code = GET_CODE (x);
2338 if (GET_MODE (x) != mode)
2341 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2344 /* return TRUE if x is EQ or NE */
2346 /* Return TRUE if this is the condition code register, if we aren't given
2347 a mode, accept any class CCmode register */
2350 cc_register (x, mode)
2352 enum machine_mode mode;
2354 if (mode == VOIDmode)
2356 mode = GET_MODE (x);
2357 if (GET_MODE_CLASS (mode) != MODE_CC)
2361 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2367 /* Return TRUE if this is the condition code register, if we aren't given
2368 a mode, accept any class CCmode register which indicates a dominance
2372 dominant_cc_register (x, mode)
2374 enum machine_mode mode;
2376 if (mode == VOIDmode)
2378 mode = GET_MODE (x);
2379 if (GET_MODE_CLASS (mode) != MODE_CC)
2383 if (mode != CC_DNEmode && mode != CC_DEQmode
2384 && mode != CC_DLEmode && mode != CC_DLTmode
2385 && mode != CC_DGEmode && mode != CC_DGTmode
2386 && mode != CC_DLEUmode && mode != CC_DLTUmode
2387 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2390 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2396 /* Return TRUE if X references a SYMBOL_REF. */
2398 symbol_mentioned_p (x)
2404 if (GET_CODE (x) == SYMBOL_REF)
2407 fmt = GET_RTX_FORMAT (GET_CODE (x));
2408 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2414 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2415 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2418 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2425 /* Return TRUE if X references a LABEL_REF. */
2427 label_mentioned_p (x)
2433 if (GET_CODE (x) == LABEL_REF)
2436 fmt = GET_RTX_FORMAT (GET_CODE (x));
2437 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2443 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2444 if (label_mentioned_p (XVECEXP (x, i, j)))
2447 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2458 enum rtx_code code = GET_CODE (x);
2462 else if (code == SMIN)
2464 else if (code == UMIN)
2466 else if (code == UMAX)
2472 /* Return 1 if memory locations are adjacent */
2475 adjacent_mem_locations (a, b)
2478 int val0 = 0, val1 = 0;
2481 if ((GET_CODE (XEXP (a, 0)) == REG
2482 || (GET_CODE (XEXP (a, 0)) == PLUS
2483 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2484 && (GET_CODE (XEXP (b, 0)) == REG
2485 || (GET_CODE (XEXP (b, 0)) == PLUS
2486 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2488 if (GET_CODE (XEXP (a, 0)) == PLUS)
2490 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2491 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2494 reg0 = REGNO (XEXP (a, 0));
2495 if (GET_CODE (XEXP (b, 0)) == PLUS)
2497 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2498 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2501 reg1 = REGNO (XEXP (b, 0));
2502 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2507 /* Return 1 if OP is a load multiple operation. It is known to be
2508 parallel and the first section will be tested. */
2511 load_multiple_operation (op, mode)
2513 enum machine_mode mode ATTRIBUTE_UNUSED;
2515 HOST_WIDE_INT count = XVECLEN (op, 0);
2518 HOST_WIDE_INT i = 1, base = 0;
2522 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2525 /* Check to see if this might be a write-back */
2526 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2531 /* Now check it more carefully */
2532 if (GET_CODE (SET_DEST (elt)) != REG
2533 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2534 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2535 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2536 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2537 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2538 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2539 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2540 != REGNO (SET_DEST (elt)))
2546 /* Perform a quick check so we don't blow up below. */
2548 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2549 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2550 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2553 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2554 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2556 for (; i < count; i++)
2558 elt = XVECEXP (op, 0, i);
2560 if (GET_CODE (elt) != SET
2561 || GET_CODE (SET_DEST (elt)) != REG
2562 || GET_MODE (SET_DEST (elt)) != SImode
2563 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2564 || GET_CODE (SET_SRC (elt)) != MEM
2565 || GET_MODE (SET_SRC (elt)) != SImode
2566 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2567 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2568 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2569 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2576 /* Return 1 if OP is a store multiple operation. It is known to be
2577 parallel and the first section will be tested. */
2580 store_multiple_operation (op, mode)
2582 enum machine_mode mode ATTRIBUTE_UNUSED;
2584 HOST_WIDE_INT count = XVECLEN (op, 0);
2587 HOST_WIDE_INT i = 1, base = 0;
2591 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2594 /* Check to see if this might be a write-back */
2595 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2600 /* Now check it more carefully */
2601 if (GET_CODE (SET_DEST (elt)) != REG
2602 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2603 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2604 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2605 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2606 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2607 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2608 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2609 != REGNO (SET_DEST (elt)))
2615 /* Perform a quick check so we don't blow up below. */
2617 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2618 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2619 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2622 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2623 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2625 for (; i < count; i++)
2627 elt = XVECEXP (op, 0, i);
2629 if (GET_CODE (elt) != SET
2630 || GET_CODE (SET_SRC (elt)) != REG
2631 || GET_MODE (SET_SRC (elt)) != SImode
2632 || REGNO (SET_SRC (elt)) != src_regno + i - base
2633 || GET_CODE (SET_DEST (elt)) != MEM
2634 || GET_MODE (SET_DEST (elt)) != SImode
2635 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2636 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2637 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2638 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2646 load_multiple_sequence (operands, nops, regs, base, load_offset)
2651 HOST_WIDE_INT *load_offset;
2653 int unsorted_regs[4];
2654 HOST_WIDE_INT unsorted_offsets[4];
2659 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2660 extended if required. */
2661 if (nops < 2 || nops > 4)
2664 /* Loop over the operands and check that the memory references are
2665 suitable (ie immediate offsets from the same base register). At
2666 the same time, extract the target register, and the memory
2668 for (i = 0; i < nops; i++)
2673 /* Convert a subreg of a mem into the mem itself. */
2674 if (GET_CODE (operands[nops + i]) == SUBREG)
2675 operands[nops + i] = alter_subreg(operands[nops + i]);
2677 if (GET_CODE (operands[nops + i]) != MEM)
2680 /* Don't reorder volatile memory references; it doesn't seem worth
2681 looking for the case where the order is ok anyway. */
2682 if (MEM_VOLATILE_P (operands[nops + i]))
2685 offset = const0_rtx;
2687 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2688 || (GET_CODE (reg) == SUBREG
2689 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2690 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2691 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2693 || (GET_CODE (reg) == SUBREG
2694 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2695 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2700 base_reg = REGNO(reg);
2701 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2702 ? REGNO (operands[i])
2703 : REGNO (SUBREG_REG (operands[i])));
2708 if (base_reg != REGNO (reg))
2709 /* Not addressed from the same base register. */
2712 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2713 ? REGNO (operands[i])
2714 : REGNO (SUBREG_REG (operands[i])));
2715 if (unsorted_regs[i] < unsorted_regs[order[0]])
2719 /* If it isn't an integer register, or if it overwrites the
2720 base register but isn't the last insn in the list, then
2721 we can't do this. */
2722 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2723 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2726 unsorted_offsets[i] = INTVAL (offset);
2729 /* Not a suitable memory address. */
2733 /* All the useful information has now been extracted from the
2734 operands into unsorted_regs and unsorted_offsets; additionally,
2735 order[0] has been set to the lowest numbered register in the
2736 list. Sort the registers into order, and check that the memory
2737 offsets are ascending and adjacent. */
2739 for (i = 1; i < nops; i++)
2743 order[i] = order[i - 1];
2744 for (j = 0; j < nops; j++)
2745 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2746 && (order[i] == order[i - 1]
2747 || unsorted_regs[j] < unsorted_regs[order[i]]))
2750 /* Have we found a suitable register? if not, one must be used more
2752 if (order[i] == order[i - 1])
2755 /* Is the memory address adjacent and ascending? */
2756 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2764 for (i = 0; i < nops; i++)
2765 regs[i] = unsorted_regs[order[i]];
2767 *load_offset = unsorted_offsets[order[0]];
2770 if (unsorted_offsets[order[0]] == 0)
2771 return 1; /* ldmia */
2773 if (unsorted_offsets[order[0]] == 4)
2774 return 2; /* ldmib */
2776 if (unsorted_offsets[order[nops - 1]] == 0)
2777 return 3; /* ldmda */
2779 if (unsorted_offsets[order[nops - 1]] == -4)
2780 return 4; /* ldmdb */
2782 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if
2783 the offset isn't small enough. The reason 2 ldrs are faster is because
2784 these ARMs are able to do more than one cache access in a single cycle.
2785 The ARM9 and StrongARM have Harvard caches, whilst the ARM8 has a double
2786 bandwidth cache. This means that these cores can do both an instruction
2787 fetch and a data fetch in a single cycle, so the trick of calculating the
2788 address into a scratch register (one of the result regs) and then doing a
2789 load multiple actually becomes slower (and no smaller in code size). That
2790 is the transformation
2792 ldr rd1, [rbase + offset]
2793 ldr rd2, [rbase + offset + 4]
2797 add rd1, rbase, offset
2798 ldmia rd1, {rd1, rd2}
2800 produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles
2801 + any stalls on rd2'. On ARMs with only one cache access per cycle, the
2802 first sequence could never complete in less than 6 cycles, whereas the ldm
2803 sequence would only take 5 and would make better use of sequential accesses
2804 if not hitting the cache.
2806 We cheat here and test 'arm_ld_sched' which we currently know to only be
2807 true for the ARM8, ARM9 and StrongARM. If this ever changes, then the test
2808 below needs to be reworked. */
2809 if (nops == 2 && arm_ld_sched)
2812 /* Can't do it without setting up the offset, only do this if it takes
2813 no more than one insn. */
2814 return (const_ok_for_arm (unsorted_offsets[order[0]])
2815 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2819 emit_ldm_seq (operands, nops)
2825 HOST_WIDE_INT offset;
2829 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2832 strcpy (buf, "ldm%?ia\t");
2836 strcpy (buf, "ldm%?ib\t");
2840 strcpy (buf, "ldm%?da\t");
2844 strcpy (buf, "ldm%?db\t");
2849 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2850 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2853 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2854 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2856 output_asm_insn (buf, operands);
2858 strcpy (buf, "ldm%?ia\t");
2865 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2866 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2868 for (i = 1; i < nops; i++)
2869 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2870 reg_names[regs[i]]);
2872 strcat (buf, "}\t%@ phole ldm");
2874 output_asm_insn (buf, operands);
2879 store_multiple_sequence (operands, nops, regs, base, load_offset)
2884 HOST_WIDE_INT *load_offset;
2886 int unsorted_regs[4];
2887 HOST_WIDE_INT unsorted_offsets[4];
2892 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2893 extended if required. */
2894 if (nops < 2 || nops > 4)
2897 /* Loop over the operands and check that the memory references are
2898 suitable (ie immediate offsets from the same base register). At
2899 the same time, extract the target register, and the memory
2901 for (i = 0; i < nops; i++)
2906 /* Convert a subreg of a mem into the mem itself. */
2907 if (GET_CODE (operands[nops + i]) == SUBREG)
2908 operands[nops + i] = alter_subreg(operands[nops + i]);
2910 if (GET_CODE (operands[nops + i]) != MEM)
2913 /* Don't reorder volatile memory references; it doesn't seem worth
2914 looking for the case where the order is ok anyway. */
2915 if (MEM_VOLATILE_P (operands[nops + i]))
2918 offset = const0_rtx;
2920 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2921 || (GET_CODE (reg) == SUBREG
2922 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2923 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2924 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2926 || (GET_CODE (reg) == SUBREG
2927 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2928 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2933 base_reg = REGNO(reg);
2934 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2935 ? REGNO (operands[i])
2936 : REGNO (SUBREG_REG (operands[i])));
2941 if (base_reg != REGNO (reg))
2942 /* Not addressed from the same base register. */
2945 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2946 ? REGNO (operands[i])
2947 : REGNO (SUBREG_REG (operands[i])));
2948 if (unsorted_regs[i] < unsorted_regs[order[0]])
2952 /* If it isn't an integer register, then we can't do this. */
2953 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2956 unsorted_offsets[i] = INTVAL (offset);
2959 /* Not a suitable memory address. */
2963 /* All the useful information has now been extracted from the
2964 operands into unsorted_regs and unsorted_offsets; additionally,
2965 order[0] has been set to the lowest numbered register in the
2966 list. Sort the registers into order, and check that the memory
2967 offsets are ascending and adjacent. */
2969 for (i = 1; i < nops; i++)
2973 order[i] = order[i - 1];
2974 for (j = 0; j < nops; j++)
2975 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2976 && (order[i] == order[i - 1]
2977 || unsorted_regs[j] < unsorted_regs[order[i]]))
2980 /* Have we found a suitable register? if not, one must be used more
2982 if (order[i] == order[i - 1])
2985 /* Is the memory address adjacent and ascending? */
2986 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2994 for (i = 0; i < nops; i++)
2995 regs[i] = unsorted_regs[order[i]];
2997 *load_offset = unsorted_offsets[order[0]];
3000 if (unsorted_offsets[order[0]] == 0)
3001 return 1; /* stmia */
3003 if (unsorted_offsets[order[0]] == 4)
3004 return 2; /* stmib */
3006 if (unsorted_offsets[order[nops - 1]] == 0)
3007 return 3; /* stmda */
3009 if (unsorted_offsets[order[nops - 1]] == -4)
3010 return 4; /* stmdb */
3016 emit_stm_seq (operands, nops)
3022 HOST_WIDE_INT offset;
3026 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3029 strcpy (buf, "stm%?ia\t");
3033 strcpy (buf, "stm%?ib\t");
3037 strcpy (buf, "stm%?da\t");
3041 strcpy (buf, "stm%?db\t");
3048 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3049 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3051 for (i = 1; i < nops; i++)
3052 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3053 reg_names[regs[i]]);
3055 strcat (buf, "}\t%@ phole stm");
3057 output_asm_insn (buf, operands);
3062 multi_register_push (op, mode)
3064 enum machine_mode mode ATTRIBUTE_UNUSED;
3066 if (GET_CODE (op) != PARALLEL
3067 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3068 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3069 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3076 /* Routines for use with attributes */
3078 /* Return nonzero if ATTR is a valid attribute for DECL.
3079 ATTRIBUTES are any existing attributes and ARGS are the arguments
3082 Supported attributes:
3084 naked: don't output any prologue or epilogue code, the user is assumed
3085 to do the right thing. */
3088 arm_valid_machine_decl_attribute (decl, attr, args)
3093 if (args != NULL_TREE)
3096 if (is_attribute_p ("naked", attr))
3097 return TREE_CODE (decl) == FUNCTION_DECL;
3101 /* Return non-zero if FUNC is a naked function. */
3104 arm_naked_function_p (func)
3109 if (TREE_CODE (func) != FUNCTION_DECL)
3112 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3113 return a != NULL_TREE;
3116 /* Routines for use in generating RTL */
3119 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3120 in_struct_p, scalar_p)
3132 int sign = up ? 1 : -1;
3135 result = gen_rtx_PARALLEL (VOIDmode,
3136 rtvec_alloc (count + (write_back ? 2 : 0)));
3139 XVECEXP (result, 0, 0)
3140 = gen_rtx_SET (GET_MODE (from), from,
3141 plus_constant (from, count * 4 * sign));
3146 for (j = 0; i < count; i++, j++)
3148 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3149 RTX_UNCHANGING_P (mem) = unchanging_p;
3150 MEM_IN_STRUCT_P (mem) = in_struct_p;
3151 MEM_SCALAR_P (mem) = scalar_p;
3152 XVECEXP (result, 0, i)
3153 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3157 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3163 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3164 in_struct_p, scalar_p)
3176 int sign = up ? 1 : -1;
3179 result = gen_rtx_PARALLEL (VOIDmode,
3180 rtvec_alloc (count + (write_back ? 2 : 0)));
3183 XVECEXP (result, 0, 0)
3184 = gen_rtx_SET (GET_MODE (to), to,
3185 plus_constant (to, count * 4 * sign));
3190 for (j = 0; i < count; i++, j++)
3192 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3193 RTX_UNCHANGING_P (mem) = unchanging_p;
3194 MEM_IN_STRUCT_P (mem) = in_struct_p;
3195 MEM_SCALAR_P (mem) = scalar_p;
3197 XVECEXP (result, 0, i)
3198 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3202 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3208 arm_gen_movstrqi (operands)
3211 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3214 rtx st_src, st_dst, fin_src, fin_dst;
3215 rtx part_bytes_reg = NULL;
3217 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3218 int dst_scalar_p, src_scalar_p;
3220 if (GET_CODE (operands[2]) != CONST_INT
3221 || GET_CODE (operands[3]) != CONST_INT
3222 || INTVAL (operands[2]) > 64
3223 || INTVAL (operands[3]) & 3)
3226 st_dst = XEXP (operands[0], 0);
3227 st_src = XEXP (operands[1], 0);
3229 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3230 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3231 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3232 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3233 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3234 src_scalar_p = MEM_SCALAR_P (operands[1]);
3236 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3237 fin_src = src = copy_to_mode_reg (SImode, st_src);
3239 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3240 out_words_to_go = INTVAL (operands[2]) / 4;
3241 last_bytes = INTVAL (operands[2]) & 3;
3243 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3244 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3246 for (i = 0; in_words_to_go >= 2; i+=4)
3248 if (in_words_to_go > 4)
3249 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3254 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3255 FALSE, src_unchanging_p,
3256 src_in_struct_p, src_scalar_p));
3258 if (out_words_to_go)
3260 if (out_words_to_go > 4)
3261 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3265 else if (out_words_to_go != 1)
3266 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3275 mem = gen_rtx_MEM (SImode, dst);
3276 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3277 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3278 MEM_SCALAR_P (mem) = dst_scalar_p;
3279 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3280 if (last_bytes != 0)
3281 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3285 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3286 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3289 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3290 if (out_words_to_go)
3294 mem = gen_rtx_MEM (SImode, src);
3295 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3296 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3297 MEM_SCALAR_P (mem) = src_scalar_p;
3298 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3299 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3301 mem = gen_rtx_MEM (SImode, dst);
3302 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3303 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3304 MEM_SCALAR_P (mem) = dst_scalar_p;
3305 emit_move_insn (mem, sreg);
3306 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3309 if (in_words_to_go) /* Sanity check */
3315 if (in_words_to_go < 0)
3318 mem = gen_rtx_MEM (SImode, src);
3319 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3320 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3321 MEM_SCALAR_P (mem) = src_scalar_p;
3322 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3325 if (BYTES_BIG_ENDIAN && last_bytes)
3327 rtx tmp = gen_reg_rtx (SImode);
3329 if (part_bytes_reg == NULL)
3332 /* The bytes we want are in the top end of the word */
3333 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3334 GEN_INT (8 * (4 - last_bytes))));
3335 part_bytes_reg = tmp;
3339 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3340 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3341 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3342 MEM_SCALAR_P (mem) = dst_scalar_p;
3343 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3346 tmp = gen_reg_rtx (SImode);
3347 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3348 part_bytes_reg = tmp;
3357 if (part_bytes_reg == NULL)
3360 mem = gen_rtx_MEM (QImode, dst);
3361 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3362 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3363 MEM_SCALAR_P (mem) = dst_scalar_p;
3364 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3367 rtx tmp = gen_reg_rtx (SImode);
3369 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3370 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3371 part_bytes_reg = tmp;
3379 /* Generate a memory reference for a half word, such that it will be loaded
3380 into the top 16 bits of the word. We can assume that the address is
3381 known to be alignable and of the form reg, or plus (reg, const). */
3383 gen_rotated_half_load (memref)
3386 HOST_WIDE_INT offset = 0;
3387 rtx base = XEXP (memref, 0);
3389 if (GET_CODE (base) == PLUS)
3391 offset = INTVAL (XEXP (base, 1));
3392 base = XEXP (base, 0);
3395 /* If we aren't allowed to generate unaligned addresses, then fail. */
3396 if (TARGET_SHORT_BY_BYTES
3397 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3400 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3402 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3405 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3408 static enum machine_mode
3409 select_dominance_cc_mode (x, y, cond_or)
3412 HOST_WIDE_INT cond_or;
3414 enum rtx_code cond1, cond2;
3417 /* Currently we will probably get the wrong result if the individual
3418 comparisons are not simple. This also ensures that it is safe to
3419 reverse a comparison if necessary. */
3420 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3422 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3427 cond1 = reverse_condition (cond1);
3429 /* If the comparisons are not equal, and one doesn't dominate the other,
3430 then we can't do this. */
3432 && ! comparison_dominates_p (cond1, cond2)
3433 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3438 enum rtx_code temp = cond1;
3446 if (cond2 == EQ || ! cond_or)
3451 case LE: return CC_DLEmode;
3452 case LEU: return CC_DLEUmode;
3453 case GE: return CC_DGEmode;
3454 case GEU: return CC_DGEUmode;
3461 if (cond2 == LT || ! cond_or)
3470 if (cond2 == GT || ! cond_or)
3479 if (cond2 == LTU || ! cond_or)
3488 if (cond2 == GTU || ! cond_or)
3496 /* The remaining cases only occur when both comparisons are the
3521 arm_select_cc_mode (op, x, y)
3526 /* All floating point compares return CCFP if it is an equality
3527 comparison, and CCFPE otherwise. */
3528 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3529 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3531 /* A compare with a shifted operand. Because of canonicalization, the
3532 comparison will have to be swapped when we emit the assembler. */
3533 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3534 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3535 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3536 || GET_CODE (x) == ROTATERT))
3539 /* This is a special case that is used by combine to allow a
3540 comparison of a shifted byte load to be split into a zero-extend
3541 followed by a comparison of the shifted integer (only valid for
3542 equalities and unsigned inequalities). */
3543 if (GET_MODE (x) == SImode
3544 && GET_CODE (x) == ASHIFT
3545 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3546 && GET_CODE (XEXP (x, 0)) == SUBREG
3547 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3548 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3549 && (op == EQ || op == NE
3550 || op == GEU || op == GTU || op == LTU || op == LEU)
3551 && GET_CODE (y) == CONST_INT)
3554 /* An operation that sets the condition codes as a side-effect, the
3555 V flag is not set correctly, so we can only use comparisons where
3556 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3558 if (GET_MODE (x) == SImode
3560 && (op == EQ || op == NE || op == LT || op == GE)
3561 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3562 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3563 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3564 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3565 || GET_CODE (x) == LSHIFTRT
3566 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3567 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3570 /* A construct for a conditional compare, if the false arm contains
3571 0, then both conditions must be true, otherwise either condition
3572 must be true. Not all conditions are possible, so CCmode is
3573 returned if it can't be done. */
3574 if (GET_CODE (x) == IF_THEN_ELSE
3575 && (XEXP (x, 2) == const0_rtx
3576 || XEXP (x, 2) == const1_rtx)
3577 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3578 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3579 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3580 INTVAL (XEXP (x, 2)));
3582 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3585 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3586 && GET_CODE (x) == PLUS
3587 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3593 /* X and Y are two things to compare using CODE. Emit the compare insn and
3594 return the rtx for register 0 in the proper mode. FP means this is a
3595 floating point compare: I don't think that it is needed on the arm. */
3598 gen_compare_reg (code, x, y)
3602 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3603 rtx cc_reg = gen_rtx_REG (mode, 24);
3605 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
3606 gen_rtx_COMPARE (mode, x, y)));
3612 arm_reload_in_hi (operands)
3615 rtx ref = operands[1];
3617 HOST_WIDE_INT offset = 0;
3619 if (GET_CODE (ref) == SUBREG)
3621 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3622 if (BYTES_BIG_ENDIAN)
3623 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3624 - MIN (UNITS_PER_WORD,
3625 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3626 ref = SUBREG_REG (ref);
3629 if (GET_CODE (ref) == REG)
3631 /* We have a pseudo which has been spilt onto the stack; there
3632 are two cases here: the first where there is a simple
3633 stack-slot replacement and a second where the stack-slot is
3634 out of range, or is used as a subreg. */
3635 if (reg_equiv_mem[REGNO (ref)])
3637 ref = reg_equiv_mem[REGNO (ref)];
3638 base = find_replacement (&XEXP (ref, 0));
3641 /* The slot is out of range, or was dressed up in a SUBREG */
3642 base = reg_equiv_address[REGNO (ref)];
3645 base = find_replacement (&XEXP (ref, 0));
3647 /* Handle the case where the address is too complex to be offset by 1. */
3648 if (GET_CODE (base) == MINUS
3649 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3651 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3653 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3656 else if (GET_CODE (base) == PLUS)
3658 /* The addend must be CONST_INT, or we would have dealt with it above */
3659 HOST_WIDE_INT hi, lo;
3661 offset += INTVAL (XEXP (base, 1));
3662 base = XEXP (base, 0);
3664 /* Rework the address into a legal sequence of insns */
3665 /* Valid range for lo is -4095 -> 4095 */
3668 : -((-offset) & 0xfff));
3670 /* Corner case, if lo is the max offset then we would be out of range
3671 once we have added the additional 1 below, so bump the msb into the
3672 pre-loading insn(s). */
3676 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3677 ^ (HOST_WIDE_INT) 0x80000000)
3678 - (HOST_WIDE_INT) 0x80000000);
3680 if (hi + lo != offset)
3685 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3687 /* Get the base address; addsi3 knows how to handle constants
3688 that require more than one insn */
3689 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3695 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3696 emit_insn (gen_zero_extendqisi2 (scratch,
3697 gen_rtx_MEM (QImode,
3698 plus_constant (base,
3700 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
3701 gen_rtx_MEM (QImode,
3702 plus_constant (base,
3704 if (BYTES_BIG_ENDIAN)
3705 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3706 gen_rtx_IOR (SImode,
3709 gen_rtx_SUBREG (SImode, operands[0], 0),
3713 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3714 gen_rtx_IOR (SImode,
3715 gen_rtx_ASHIFT (SImode, scratch,
3717 gen_rtx_SUBREG (SImode, operands[0],
3721 /* Handle storing a half-word to memory during reload by synthesising as two
3722 byte stores. Take care not to clobber the input values until after we
3723 have moved them somewhere safe. This code assumes that if the DImode
3724 scratch in operands[2] overlaps either the input value or output address
3725 in some way, then that value must die in this insn (we absolutely need
3726 two scratch registers for some corner cases). */
3728 arm_reload_out_hi (operands)
3731 rtx ref = operands[0];
3732 rtx outval = operands[1];
3734 HOST_WIDE_INT offset = 0;
3736 if (GET_CODE (ref) == SUBREG)
3738 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3739 if (BYTES_BIG_ENDIAN)
3740 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3741 - MIN (UNITS_PER_WORD,
3742 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3743 ref = SUBREG_REG (ref);
3747 if (GET_CODE (ref) == REG)
3749 /* We have a pseudo which has been spilt onto the stack; there
3750 are two cases here: the first where there is a simple
3751 stack-slot replacement and a second where the stack-slot is
3752 out of range, or is used as a subreg. */
3753 if (reg_equiv_mem[REGNO (ref)])
3755 ref = reg_equiv_mem[REGNO (ref)];
3756 base = find_replacement (&XEXP (ref, 0));
3759 /* The slot is out of range, or was dressed up in a SUBREG */
3760 base = reg_equiv_address[REGNO (ref)];
3763 base = find_replacement (&XEXP (ref, 0));
3765 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3767 /* Handle the case where the address is too complex to be offset by 1. */
3768 if (GET_CODE (base) == MINUS
3769 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3771 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3773 /* Be careful not to destroy OUTVAL. */
3774 if (reg_overlap_mentioned_p (base_plus, outval))
3776 /* Updating base_plus might destroy outval, see if we can
3777 swap the scratch and base_plus. */
3778 if (! reg_overlap_mentioned_p (scratch, outval))
3781 scratch = base_plus;
3786 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3788 /* Be conservative and copy OUTVAL into the scratch now,
3789 this should only be necessary if outval is a subreg
3790 of something larger than a word. */
3791 /* XXX Might this clobber base? I can't see how it can,
3792 since scratch is known to overlap with OUTVAL, and
3793 must be wider than a word. */
3794 emit_insn (gen_movhi (scratch_hi, outval));
3795 outval = scratch_hi;
3799 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3802 else if (GET_CODE (base) == PLUS)
3804 /* The addend must be CONST_INT, or we would have dealt with it above */
3805 HOST_WIDE_INT hi, lo;
3807 offset += INTVAL (XEXP (base, 1));
3808 base = XEXP (base, 0);
3810 /* Rework the address into a legal sequence of insns */
3811 /* Valid range for lo is -4095 -> 4095 */
3814 : -((-offset) & 0xfff));
3816 /* Corner case, if lo is the max offset then we would be out of range
3817 once we have added the additional 1 below, so bump the msb into the
3818 pre-loading insn(s). */
3822 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3823 ^ (HOST_WIDE_INT) 0x80000000)
3824 - (HOST_WIDE_INT) 0x80000000);
3826 if (hi + lo != offset)
3831 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3833 /* Be careful not to destroy OUTVAL. */
3834 if (reg_overlap_mentioned_p (base_plus, outval))
3836 /* Updating base_plus might destroy outval, see if we
3837 can swap the scratch and base_plus. */
3838 if (! reg_overlap_mentioned_p (scratch, outval))
3841 scratch = base_plus;
3846 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3848 /* Be conservative and copy outval into scratch now,
3849 this should only be necessary if outval is a
3850 subreg of something larger than a word. */
3851 /* XXX Might this clobber base? I can't see how it
3852 can, since scratch is known to overlap with
3854 emit_insn (gen_movhi (scratch_hi, outval));
3855 outval = scratch_hi;
3859 /* Get the base address; addsi3 knows how to handle constants
3860 that require more than one insn */
3861 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3867 if (BYTES_BIG_ENDIAN)
3869 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3870 plus_constant (base, offset + 1)),
3871 gen_rtx_SUBREG (QImode, outval, 0)));
3872 emit_insn (gen_lshrsi3 (scratch,
3873 gen_rtx_SUBREG (SImode, outval, 0),
3875 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3876 gen_rtx_SUBREG (QImode, scratch, 0)));
3880 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3881 gen_rtx_SUBREG (QImode, outval, 0)));
3882 emit_insn (gen_lshrsi3 (scratch,
3883 gen_rtx_SUBREG (SImode, outval, 0),
3885 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3886 plus_constant (base, offset + 1)),
3887 gen_rtx_SUBREG (QImode, scratch, 0)));
3891 /* Routines for manipulation of the constant pool. */
3892 /* This is unashamedly hacked from the version in sh.c, since the problem is
3893 extremely similar. */
3895 /* Arm instructions cannot load a large constant into a register,
3896 constants have to come from a pc relative load. The reference of a pc
3897 relative load instruction must be less than 1k infront of the instruction.
3898 This means that we often have to dump a constant inside a function, and
3899 generate code to branch around it.
3901 It is important to minimize this, since the branches will slow things
3902 down and make things bigger.
3904 Worst case code looks like:
3920 We fix this by performing a scan before scheduling, which notices which
3921 instructions need to have their operands fetched from the constant table
3922 and builds the table.
3927 scan, find an instruction which needs a pcrel move. Look forward, find th
3928 last barrier which is within MAX_COUNT bytes of the requirement.
3929 If there isn't one, make one. Process all the instructions between
3930 the find and the barrier.
3932 In the above example, we can tell that L3 is within 1k of L1, so
3933 the first move can be shrunk from the 2 insn+constant sequence into
3934 just 1 insn, and the constant moved to L3 to make:
3945 Then the second move becomes the target for the shortening process.
3951 rtx value; /* Value in table */
3952 HOST_WIDE_INT next_offset;
3953 enum machine_mode mode; /* Mode of value */
3956 /* The maximum number of constants that can fit into one pool, since
3957 the pc relative range is 0...1020 bytes and constants are at least 4
3960 #define MAX_POOL_SIZE (1020/4)
3961 static pool_node pool_vector[MAX_POOL_SIZE];
3962 static int pool_size;
3963 static rtx pool_vector_label;
3965 /* Add a constant to the pool and return its offset within the current
3968 X is the rtx we want to replace. MODE is its mode. On return,
3969 ADDRESS_ONLY will be non-zero if we really want the address of such
3970 a constant, not the constant itself. */
3971 static HOST_WIDE_INT
3972 add_constant (x, mode, address_only)
3974 enum machine_mode mode;
3978 HOST_WIDE_INT offset;
3982 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3983 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3984 x = get_pool_constant (XEXP (x, 0));
3985 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3988 mode = get_pool_mode (x);
3989 x = get_pool_constant (x);
3991 #ifndef AOF_ASSEMBLER
3992 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3993 x = XVECEXP (x, 0, 0);
3996 #ifdef AOF_ASSEMBLER
3997 /* PIC Symbol references need to be converted into offsets into the
3999 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
4000 x = aof_pic_entry (x);
4001 #endif /* AOF_ASSEMBLER */
4003 /* First see if we've already got it */
4004 for (i = 0; i < pool_size; i++)
4006 if (GET_CODE (x) == pool_vector[i].value->code
4007 && mode == pool_vector[i].mode)
4009 if (GET_CODE (x) == CODE_LABEL)
4011 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4014 if (rtx_equal_p (x, pool_vector[i].value))
4015 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
4019 /* Need a new one */
4020 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
4023 pool_vector_label = gen_label_rtx ();
4025 pool_vector[pool_size].next_offset
4026 += (offset = pool_vector[pool_size - 1].next_offset);
4028 pool_vector[pool_size].value = x;
4029 pool_vector[pool_size].mode = mode;
4034 /* Output the literal table */
4041 scan = emit_label_after (gen_label_rtx (), scan);
4042 scan = emit_insn_after (gen_align_4 (), scan);
4043 scan = emit_label_after (pool_vector_label, scan);
4045 for (i = 0; i < pool_size; i++)
4047 pool_node *p = pool_vector + i;
4049 switch (GET_MODE_SIZE (p->mode))
4052 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4056 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4065 scan = emit_insn_after (gen_consttable_end (), scan);
4066 scan = emit_barrier_after (scan);
4070 /* Non zero if the src operand needs to be fixed up */
4072 fixit (src, mode, destreg)
4074 enum machine_mode mode;
4077 if (CONSTANT_P (src))
4079 if (GET_CODE (src) == CONST_INT)
4080 return (! const_ok_for_arm (INTVAL (src))
4081 && ! const_ok_for_arm (~INTVAL (src)));
4082 if (GET_CODE (src) == CONST_DOUBLE)
4083 return (GET_MODE (src) == VOIDmode
4085 || (! const_double_rtx_ok_for_fpu (src)
4086 && ! neg_const_double_rtx_ok_for_fpu (src)));
4087 return symbol_mentioned_p (src);
4089 #ifndef AOF_ASSEMBLER
4090 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
4094 return (mode == SImode && GET_CODE (src) == MEM
4095 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
4096 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
4099 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
4101 find_barrier (from, max_count)
4106 rtx found_barrier = 0;
4109 while (from && count < max_count)
4113 if (GET_CODE (from) == BARRIER)
4114 found_barrier = from;
4116 /* Count the length of this insn */
4117 if (GET_CODE (from) == INSN
4118 && GET_CODE (PATTERN (from)) == SET
4119 && CONSTANT_P (SET_SRC (PATTERN (from)))
4120 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
4122 /* Handle table jumps as a single entity. */
4123 else if (GET_CODE (from) == JUMP_INSN
4124 && JUMP_LABEL (from) != 0
4125 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4126 == next_real_insn (from))
4128 && GET_CODE (tmp) == JUMP_INSN
4129 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4130 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4132 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4133 count += (get_attr_length (from)
4134 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4135 /* Continue after the dispatch table. */
4137 from = NEXT_INSN (tmp);
4141 count += get_attr_length (from);
4144 from = NEXT_INSN (from);
4147 if (! found_barrier)
4149 /* We didn't find a barrier in time to
4150 dump our stuff, so we'll make one. */
4151 rtx label = gen_label_rtx ();
4154 from = PREV_INSN (last);
4156 from = get_last_insn ();
4158 /* Walk back to be just before any jump. */
4159 while (GET_CODE (from) == JUMP_INSN
4160 || GET_CODE (from) == NOTE
4161 || GET_CODE (from) == CODE_LABEL)
4162 from = PREV_INSN (from);
4164 from = emit_jump_insn_after (gen_jump (label), from);
4165 JUMP_LABEL (from) = label;
4166 found_barrier = emit_barrier_after (from);
4167 emit_label_after (label, found_barrier);
4170 return found_barrier;
4173 /* Non zero if the insn is a move instruction which needs to be fixed. */
4178 if (!INSN_DELETED_P (insn)
4179 && GET_CODE (insn) == INSN
4180 && GET_CODE (PATTERN (insn)) == SET)
4182 rtx pat = PATTERN (insn);
4183 rtx src = SET_SRC (pat);
4184 rtx dst = SET_DEST (pat);
4186 enum machine_mode mode = GET_MODE (dst);
4191 if (GET_CODE (dst) == REG)
4192 destreg = REGNO (dst);
4193 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
4194 destreg = REGNO (SUBREG_REG (dst));
4198 return fixit (src, mode, destreg);
4211 /* The ldr instruction can work with up to a 4k offset, and most constants
4212 will be loaded with one of these instructions; however, the adr
4213 instruction and the ldf instructions only work with a 1k offset. This
4214 code needs to be rewritten to use the 4k offset when possible, and to
4215 adjust when a 1k offset is needed. For now we just use a 1k offset
4219 /* Floating point operands can't work further than 1024 bytes from the
4220 PC, so to make things simple we restrict all loads for such functions.
4222 if (TARGET_HARD_FLOAT)
4226 for (regno = 16; regno < 24; regno++)
4227 if (regs_ever_live[regno])
4237 for (insn = first; insn; insn = NEXT_INSN (insn))
4239 if (broken_move (insn))
4241 /* This is a broken move instruction, scan ahead looking for
4242 a barrier to stick the constant table behind */
4244 rtx barrier = find_barrier (insn, count_size);
4246 /* Now find all the moves between the points and modify them */
4247 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4249 if (broken_move (scan))
4251 /* This is a broken move instruction, add it to the pool */
4252 rtx pat = PATTERN (scan);
4253 rtx src = SET_SRC (pat);
4254 rtx dst = SET_DEST (pat);
4255 enum machine_mode mode = GET_MODE (dst);
4256 HOST_WIDE_INT offset;
4263 /* If this is an HImode constant load, convert it into
4264 an SImode constant load. Since the register is always
4265 32 bits this is safe. We have to do this, since the
4266 load pc-relative instruction only does a 32-bit load. */
4270 if (GET_CODE (dst) != REG)
4272 PUT_MODE (dst, SImode);
4275 offset = add_constant (src, mode, &address_only);
4276 addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4280 /* If we only want the address of the pool entry, or
4281 for wide moves to integer regs we need to split
4282 the address calculation off into a separate insn.
4283 If necessary, the load can then be done with a
4284 load-multiple. This is safe, since we have
4285 already noted the length of such insns to be 8,
4286 and we are immediately over-writing the scratch
4287 we have grabbed with the final result. */
4288 if ((address_only || GET_MODE_SIZE (mode) > 4)
4289 && (scratch = REGNO (dst)) < 16)
4296 reg = gen_rtx_REG (SImode, scratch);
4298 newinsn = emit_insn_after (gen_movaddr (reg, addr),
4305 newsrc = gen_rtx_MEM (mode, addr);
4307 /* XXX Fixme -- I think the following is bogus. */
4308 /* Build a jump insn wrapper around the move instead
4309 of an ordinary insn, because we want to have room for
4310 the target label rtx in fld[7], which an ordinary
4311 insn doesn't have. */
4313 = emit_jump_insn_after (gen_rtx_SET (VOIDmode, dst,
4316 JUMP_LABEL (newinsn) = pool_vector_label;
4318 /* But it's still an ordinary insn */
4319 PUT_CODE (newinsn, INSN);
4327 dump_table (barrier);
4332 after_arm_reorg = 1;
4336 /* Routines to output assembly language. */
4338 /* If the rtx is the correct value then return the string of the number.
4339 In this way we can ensure that valid double constants are generated even
4340 when cross compiling. */
4342 fp_immediate_constant (x)
4348 if (!fpa_consts_inited)
4351 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4352 for (i = 0; i < 8; i++)
4353 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4354 return strings_fpa[i];
4359 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4361 fp_const_from_val (r)
4366 if (! fpa_consts_inited)
4369 for (i = 0; i < 8; i++)
4370 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4371 return strings_fpa[i];
4376 /* Output the operands of a LDM/STM instruction to STREAM.
4377 MASK is the ARM register set mask of which only bits 0-15 are important.
4378 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4379 must follow the register list. */
4382 print_multi_reg (stream, instr, mask, hat)
4388 int not_first = FALSE;
4390 fputc ('\t', stream);
4391 fprintf (stream, instr, REGISTER_PREFIX);
4392 fputs (", {", stream);
4393 for (i = 0; i < 16; i++)
4394 if (mask & (1 << i))
4397 fprintf (stream, ", ");
4398 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
4402 fprintf (stream, "}%s\n", hat ? "^" : "");
4405 /* Output a 'call' insn. */
4408 output_call (operands)
4411 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4413 if (REGNO (operands[0]) == 14)
4415 operands[0] = gen_rtx_REG (SImode, 12);
4416 output_asm_insn ("mov%?\t%0, %|lr", operands);
4418 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4420 if (TARGET_THUMB_INTERWORK)
4421 output_asm_insn ("bx%?\t%0", operands);
4423 output_asm_insn ("mov%?\t%|pc, %0", operands);
4432 int something_changed = 0;
4434 int code = GET_CODE (x0);
4441 if (REGNO (x0) == 14)
4443 *x = gen_rtx_REG (SImode, 12);
4448 /* Scan through the sub-elements and change any references there */
4449 fmt = GET_RTX_FORMAT (code);
4450 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4452 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4453 else if (fmt[i] == 'E')
4454 for (j = 0; j < XVECLEN (x0, i); j++)
4455 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4456 return something_changed;
4460 /* Output a 'call' insn that is a reference in memory. */
4463 output_call_mem (operands)
4466 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4467 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4469 if (eliminate_lr2ip (&operands[0]))
4470 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4472 if (TARGET_THUMB_INTERWORK)
4474 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4475 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4476 output_asm_insn ("bx%?\t%|ip", operands);
4480 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4481 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4488 /* Output a move from arm registers to an fpu registers.
4489 OPERANDS[0] is an fpu register.
4490 OPERANDS[1] is the first registers of an arm register pair. */
4493 output_mov_long_double_fpu_from_arm (operands)
4496 int arm_reg0 = REGNO (operands[1]);
4502 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4503 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4504 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4506 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4507 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4511 /* Output a move from an fpu register to arm registers.
4512 OPERANDS[0] is the first registers of an arm register pair.
4513 OPERANDS[1] is an fpu register. */
4516 output_mov_long_double_arm_from_fpu (operands)
4519 int arm_reg0 = REGNO (operands[0]);
4525 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4526 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4527 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4529 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4530 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4534 /* Output a move from arm registers to arm registers of a long double
4535 OPERANDS[0] is the destination.
4536 OPERANDS[1] is the source. */
4538 output_mov_long_double_arm_from_arm (operands)
4541 /* We have to be careful here because the two might overlap */
4542 int dest_start = REGNO (operands[0]);
4543 int src_start = REGNO (operands[1]);
4547 if (dest_start < src_start)
4549 for (i = 0; i < 3; i++)
4551 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4552 ops[1] = gen_rtx_REG (SImode, src_start + i);
4553 output_asm_insn ("mov%?\t%0, %1", ops);
4558 for (i = 2; i >= 0; i--)
4560 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4561 ops[1] = gen_rtx_REG (SImode, src_start + i);
4562 output_asm_insn ("mov%?\t%0, %1", ops);
4570 /* Output a move from arm registers to an fpu registers.
4571 OPERANDS[0] is an fpu register.
4572 OPERANDS[1] is the first registers of an arm register pair. */
4575 output_mov_double_fpu_from_arm (operands)
4578 int arm_reg0 = REGNO (operands[1]);
4583 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4584 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4585 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4586 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4590 /* Output a move from an fpu register to arm registers.
4591 OPERANDS[0] is the first registers of an arm register pair.
4592 OPERANDS[1] is an fpu register. */
4595 output_mov_double_arm_from_fpu (operands)
4598 int arm_reg0 = REGNO (operands[0]);
4604 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4605 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4606 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4607 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4611 /* Output a move between double words.
4612 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4613 or MEM<-REG and all MEMs must be offsettable addresses. */
4616 output_move_double (operands)
4619 enum rtx_code code0 = GET_CODE (operands[0]);
4620 enum rtx_code code1 = GET_CODE (operands[1]);
4625 int reg0 = REGNO (operands[0]);
4627 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
4631 int reg1 = REGNO (operands[1]);
4635 /* Ensure the second source is not overwritten */
4636 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4637 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4639 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4641 else if (code1 == CONST_DOUBLE)
4643 if (GET_MODE (operands[1]) == DFmode)
4646 union real_extract u;
4648 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4650 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4651 otherops[1] = GEN_INT(l[1]);
4652 operands[1] = GEN_INT(l[0]);
4654 else if (GET_MODE (operands[1]) != VOIDmode)
4656 else if (WORDS_BIG_ENDIAN)
4659 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4660 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4665 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4666 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4668 output_mov_immediate (operands);
4669 output_mov_immediate (otherops);
4671 else if (code1 == CONST_INT)
4673 #if HOST_BITS_PER_WIDE_INT > 32
4674 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4675 what the upper word is. */
4676 if (WORDS_BIG_ENDIAN)
4678 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4679 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4683 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4684 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4687 /* Sign extend the intval into the high-order word */
4688 if (WORDS_BIG_ENDIAN)
4690 otherops[1] = operands[1];
4691 operands[1] = (INTVAL (operands[1]) < 0
4692 ? constm1_rtx : const0_rtx);
4695 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4697 output_mov_immediate (otherops);
4698 output_mov_immediate (operands);
4700 else if (code1 == MEM)
4702 switch (GET_CODE (XEXP (operands[1], 0)))
4705 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4709 abort (); /* Should never happen now */
4713 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4717 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4721 abort (); /* Should never happen now */
4726 output_asm_insn ("adr%?\t%0, %1", operands);
4727 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4731 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
4732 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
4734 otherops[0] = operands[0];
4735 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4736 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4737 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4739 if (GET_CODE (otherops[2]) == CONST_INT)
4741 switch (INTVAL (otherops[2]))
4744 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4747 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4750 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4753 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4754 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4756 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4759 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4762 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4763 return "ldm%?ia\t%0, %M0";
4767 otherops[1] = adj_offsettable_operand (operands[1], 4);
4768 /* Take care of overlapping base/data reg. */
4769 if (reg_mentioned_p (operands[0], operands[1]))
4771 output_asm_insn ("ldr%?\t%0, %1", otherops);
4772 output_asm_insn ("ldr%?\t%0, %1", operands);
4776 output_asm_insn ("ldr%?\t%0, %1", operands);
4777 output_asm_insn ("ldr%?\t%0, %1", otherops);
4783 abort(); /* Constraints should prevent this */
4785 else if (code0 == MEM && code1 == REG)
4787 if (REGNO (operands[1]) == 12)
4790 switch (GET_CODE (XEXP (operands[0], 0)))
4793 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4797 abort (); /* Should never happen now */
4801 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4805 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4809 abort (); /* Should never happen now */
4813 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4815 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4818 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4822 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4826 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4833 otherops[0] = adj_offsettable_operand (operands[0], 4);
4834 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
4835 output_asm_insn ("str%?\t%1, %0", operands);
4836 output_asm_insn ("str%?\t%1, %0", otherops);
4840 abort(); /* Constraints should prevent this */
4846 /* Output an arbitrary MOV reg, #n.
4847 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4850 output_mov_immediate (operands)
4853 HOST_WIDE_INT n = INTVAL (operands[1]);
4857 /* Try to use one MOV */
4858 if (const_ok_for_arm (n))
4860 output_asm_insn ("mov%?\t%0, %1", operands);
4864 /* Try to use one MVN */
4865 if (const_ok_for_arm (~n))
4867 operands[1] = GEN_INT (~n);
4868 output_asm_insn ("mvn%?\t%0, %1", operands);
4872 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4874 for (i=0; i < 32; i++)
4878 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4879 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4882 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4889 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4890 adding zero to one register, output nothing. */
4893 output_add_immediate (operands)
4896 HOST_WIDE_INT n = INTVAL (operands[2]);
4898 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4901 output_multi_immediate (operands,
4902 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4905 output_multi_immediate (operands,
4906 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4913 /* Output a multiple immediate operation.
4914 OPERANDS is the vector of operands referred to in the output patterns.
4915 INSTR1 is the output pattern to use for the first constant.
4916 INSTR2 is the output pattern to use for subsequent constants.
4917 IMMED_OP is the index of the constant slot in OPERANDS.
4918 N is the constant value. */
4921 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4923 char *instr1, *instr2;
4927 #if HOST_BITS_PER_WIDE_INT > 32
4933 operands[immed_op] = const0_rtx;
4934 output_asm_insn (instr1, operands); /* Quick and easy output */
4939 char *instr = instr1;
4941 /* Note that n is never zero here (which would give no output) */
4942 for (i = 0; i < 32; i += 2)
4946 operands[immed_op] = GEN_INT (n & (255 << i));
4947 output_asm_insn (instr, operands);
4957 /* Return the appropriate ARM instruction for the operation code.
4958 The returned result should not be overwritten. OP is the rtx of the
4959 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4963 arithmetic_instr (op, shift_first_arg)
4965 int shift_first_arg;
4967 switch (GET_CODE (op))
4973 return shift_first_arg ? "rsb" : "sub";
4990 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4991 for the operation code. The returned result should not be overwritten.
4992 OP is the rtx code of the shift.
4993 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4997 shift_op (op, amountp)
4999 HOST_WIDE_INT *amountp;
5002 enum rtx_code code = GET_CODE (op);
5004 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5006 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5007 *amountp = INTVAL (XEXP (op, 1));
5030 /* We never have to worry about the amount being other than a
5031 power of 2, since this case can never be reloaded from a reg. */
5033 *amountp = int_log2 (*amountp);
5044 /* This is not 100% correct, but follows from the desire to merge
5045 multiplication by a power of 2 with the recognizer for a
5046 shift. >=32 is not a valid shift for "asl", so we must try and
5047 output a shift that produces the correct arithmetical result.
5048 Using lsr #32 is identical except for the fact that the carry bit
5049 is not set correctly if we set the flags; but we never use the
5050 carry bit from such an operation, so we can ignore that. */
5051 if (code == ROTATERT)
5052 *amountp &= 31; /* Rotate is just modulo 32 */
5053 else if (*amountp != (*amountp & 31))
5060 /* Shifts of 0 are no-ops. */
5069 /* Obtain the shift from the POWER of two. */
5071 static HOST_WIDE_INT
5073 HOST_WIDE_INT power;
5075 HOST_WIDE_INT shift = 0;
5077 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5087 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5088 /bin/as is horribly restrictive. */
5091 output_ascii_pseudo_op (stream, p, len)
5097 int len_so_far = 1000;
5098 int chars_so_far = 0;
5100 for (i = 0; i < len; i++)
5102 register int c = p[i];
5104 if (len_so_far > 50)
5107 fputs ("\"\n", stream);
5108 fputs ("\t.ascii\t\"", stream);
5113 if (c == '\"' || c == '\\')
5119 if (c >= ' ' && c < 0177)
5126 fprintf (stream, "\\%03o", c);
5133 fputs ("\"\n", stream);
5137 /* Try to determine whether a pattern really clobbers the link register.
5138 This information is useful when peepholing, so that lr need not be pushed
5139 if we combine a call followed by a return.
5140 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5141 such a check should not be needed because these only update an existing
5142 value within a register; the register must still be set elsewhere within
5146 pattern_really_clobbers_lr (x)
5151 switch (GET_CODE (x))
5154 switch (GET_CODE (SET_DEST (x)))
5157 return REGNO (SET_DEST (x)) == 14;
5160 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5161 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
5163 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5172 for (i = 0; i < XVECLEN (x, 0); i++)
5173 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5178 switch (GET_CODE (XEXP (x, 0)))
5181 return REGNO (XEXP (x, 0)) == 14;
5184 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5185 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
5201 function_really_clobbers_lr (first)
5206 for (insn = first; insn; insn = next_nonnote_insn (insn))
5208 switch (GET_CODE (insn))
5213 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5218 if (pattern_really_clobbers_lr (PATTERN (insn)))
5223 /* Don't yet know how to handle those calls that are not to a
5225 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5228 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5231 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5237 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5243 default: /* Don't recognize it, be safe */
5247 /* A call can be made (by peepholing) not to clobber lr iff it is
5248 followed by a return. There may, however, be a use insn iff
5249 we are returning the result of the call.
5250 If we run off the end of the insn chain, then that means the
5251 call was at the end of the function. Unfortunately we don't
5252 have a return insn for the peephole to recognize, so we
5253 must reject this. (Can this be fixed by adding our own insn?) */
5254 if ((next = next_nonnote_insn (insn)) == NULL)
5257 /* No need to worry about lr if the call never returns */
5258 if (GET_CODE (next) == BARRIER)
5261 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5262 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5263 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5264 == REGNO (XEXP (PATTERN (next), 0))))
5265 if ((next = next_nonnote_insn (next)) == NULL)
5268 if (GET_CODE (next) == JUMP_INSN
5269 && GET_CODE (PATTERN (next)) == RETURN)
5278 /* We have reached the end of the chain so lr was _not_ clobbered */
5283 output_return_instruction (operand, really_return, reverse)
5289 int reg, live_regs = 0;
5290 int volatile_func = (optimize > 0
5291 && TREE_THIS_VOLATILE (current_function_decl));
5293 return_used_this_function = 1;
5298 /* If this function was declared non-returning, and we have found a tail
5299 call, then we have to trust that the called function won't return. */
5300 if (! really_return)
5303 /* Otherwise, trap an attempted return by aborting. */
5305 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)"
5307 assemble_external_libcall (ops[1]);
5308 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5312 if (current_function_calls_alloca && ! really_return)
5315 for (reg = 0; reg <= 10; reg++)
5316 if (regs_ever_live[reg] && ! call_used_regs[reg])
5319 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
5322 if (frame_pointer_needed)
5327 if (lr_save_eliminated || ! regs_ever_live[14])
5330 if (frame_pointer_needed)
5332 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5335 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5337 for (reg = 0; reg <= 10; reg++)
5338 if (regs_ever_live[reg] && ! call_used_regs[reg])
5340 strcat (instr, "%|");
5341 strcat (instr, reg_names[reg]);
5343 strcat (instr, ", ");
5346 if (frame_pointer_needed)
5348 strcat (instr, "%|");
5349 strcat (instr, reg_names[11]);
5350 strcat (instr, ", ");
5351 strcat (instr, "%|");
5352 strcat (instr, reg_names[13]);
5353 strcat (instr, ", ");
5354 strcat (instr, "%|");
5355 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
5356 ? reg_names[14] : reg_names[15] );
5360 strcat (instr, "%|");
5361 if (TARGET_THUMB_INTERWORK && really_return)
5362 strcat (instr, reg_names[12]);
5364 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
5366 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5367 output_asm_insn (instr, &operand);
5369 if (TARGET_THUMB_INTERWORK && really_return)
5371 strcpy (instr, "bx%?");
5372 strcat (instr, reverse ? "%D0" : "%d0");
5373 strcat (instr, "\t%|");
5374 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5376 output_asm_insn (instr, & operand);
5379 else if (really_return)
5381 if (TARGET_THUMB_INTERWORK)
5382 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5384 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5385 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5387 output_asm_insn (instr, & operand);
5393 /* Return nonzero if optimizing and the current function is volatile.
5394 Such functions never return, and many memory cycles can be saved
5395 by not storing register values that will never be needed again.
5396 This optimization was added to speed up context switching in a
5397 kernel application. */
5400 arm_volatile_func ()
5402 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5405 /* Write the function name into the code section, directly preceding
5406 the function prologue.
5408 Code will be output similar to this:
5410 .ascii "arm_poke_function_name", 0
5413 .word 0xff000000 + (t1 - t0)
5414 arm_poke_function_name
5416 stmfd sp!, {fp, ip, lr, pc}
5419 When performing a stack backtrace, code can inspect the value
5420 of 'pc' stored at 'fp' + 0. If the trace function then looks
5421 at location pc - 12 and the top 8 bits are set, then we know
5422 that there is a function name embedded immediately preceding this
5423 location and has length ((pc[-3]) & 0xff000000).
5425 We assume that pc is declared as a pointer to an unsigned long.
5427 It is of no benefit to output the function name if we are assembling
5428 a leaf function. These function types will not contain a stack
5429 backtrace structure, therefore it is not possible to determine the
5433 arm_poke_function_name (stream, name)
5437 unsigned long alignlength;
5438 unsigned long length;
5441 length = strlen (name);
5442 alignlength = (length + 1) + 3 & ~3;
5444 ASM_OUTPUT_ASCII (stream, name, length + 1);
5445 ASM_OUTPUT_ALIGN (stream, 2);
5446 x = GEN_INT (0xff000000UL + alignlength);
5447 ASM_OUTPUT_INT (stream, x);
5450 /* The amount of stack adjustment that happens here, in output_return and in
5451 output_epilogue must be exactly the same as was calculated during reload,
5452 or things will point to the wrong place. The only time we can safely
5453 ignore this constraint is when a function has no arguments on the stack,
5454 no stack frame requirement and no live registers execpt for `lr'. If we
5455 can guarantee that by making all function calls into tail calls and that
5456 lr is not clobbered in any other way, then there is no need to push lr
5460 output_func_prologue (f, frame_size)
5464 int reg, live_regs_mask = 0;
5465 int volatile_func = (optimize > 0
5466 && TREE_THIS_VOLATILE (current_function_decl));
5468 /* Nonzero if we must stuff some register arguments onto the stack as if
5469 they were passed there. */
5470 int store_arg_regs = 0;
5472 if (arm_ccfsm_state || arm_target_insn)
5473 abort (); /* Sanity check */
5475 if (arm_naked_function_p (current_function_decl))
5478 return_used_this_function = 0;
5479 lr_save_eliminated = 0;
5481 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
5482 ASM_COMMENT_START, current_function_args_size,
5483 current_function_pretend_args_size, frame_size);
5484 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
5485 ASM_COMMENT_START, frame_pointer_needed,
5486 current_function_anonymous_args);
5489 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
5491 if (current_function_anonymous_args && current_function_pretend_args_size)
5494 for (reg = 0; reg <= 10; reg++)
5495 if (regs_ever_live[reg] && ! call_used_regs[reg])
5496 live_regs_mask |= (1 << reg);
5498 if (frame_pointer_needed)
5499 live_regs_mask |= 0xD800;
5500 else if (regs_ever_live[14])
5502 if (! current_function_args_size
5503 && ! function_really_clobbers_lr (get_insns ()))
5504 lr_save_eliminated = 1;
5506 live_regs_mask |= 0x4000;
5511 /* if a di mode load/store multiple is used, and the base register
5512 is r3, then r4 can become an ever live register without lr
5513 doing so, in this case we need to push lr as well, or we
5514 will fail to get a proper return. */
5516 live_regs_mask |= 0x4000;
5517 lr_save_eliminated = 0;
5521 if (lr_save_eliminated)
5522 fprintf (f,"\t%s I don't think this function clobbers lr\n",
5525 #ifdef AOF_ASSEMBLER
5527 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
5528 reg_names[PIC_OFFSET_TABLE_REGNUM]);
5534 output_func_epilogue (f, frame_size)
5538 int reg, live_regs_mask = 0;
5539 /* If we need this then it will always be at least this much */
5540 int floats_offset = 12;
5542 int volatile_func = (optimize > 0
5543 && TREE_THIS_VOLATILE (current_function_decl));
5545 if (use_return_insn (FALSE) && return_used_this_function)
5547 if ((frame_size + current_function_outgoing_args_size) != 0
5548 && !(frame_pointer_needed && TARGET_APCS))
5553 /* Naked functions don't have epilogues. */
5554 if (arm_naked_function_p (current_function_decl))
5557 /* A volatile function should never return. Call abort. */
5558 if (TARGET_ABORT_NORETURN && volatile_func)
5561 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)" : "abort");
5562 assemble_external_libcall (op);
5563 output_asm_insn ("bl\t%a0", &op);
5567 for (reg = 0; reg <= 10; reg++)
5568 if (regs_ever_live[reg] && ! call_used_regs[reg])
5570 live_regs_mask |= (1 << reg);
5574 if (frame_pointer_needed)
5576 if (arm_fpu_arch == FP_SOFT2)
5578 for (reg = 23; reg > 15; reg--)
5579 if (regs_ever_live[reg] && ! call_used_regs[reg])
5581 floats_offset += 12;
5582 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
5583 reg_names[reg], REGISTER_PREFIX, floats_offset);
5590 for (reg = 23; reg > 15; reg--)
5592 if (regs_ever_live[reg] && ! call_used_regs[reg])
5594 floats_offset += 12;
5595 /* We can't unstack more than four registers at once */
5596 if (start_reg - reg == 3)
5598 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
5599 REGISTER_PREFIX, reg_names[reg],
5600 REGISTER_PREFIX, floats_offset);
5601 start_reg = reg - 1;
5606 if (reg != start_reg)
5607 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5608 REGISTER_PREFIX, reg_names[reg + 1],
5609 start_reg - reg, REGISTER_PREFIX, floats_offset);
5611 start_reg = reg - 1;
5615 /* Just in case the last register checked also needs unstacking. */
5616 if (reg != start_reg)
5617 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5618 REGISTER_PREFIX, reg_names[reg + 1],
5619 start_reg - reg, REGISTER_PREFIX, floats_offset);
5622 if (TARGET_THUMB_INTERWORK)
5624 live_regs_mask |= 0x6800;
5625 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5626 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5630 live_regs_mask |= 0xA800;
5631 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5632 TARGET_APCS_32 ? FALSE : TRUE);
5637 /* Restore stack pointer if necessary. */
5638 if (frame_size + current_function_outgoing_args_size != 0)
5640 operands[0] = operands[1] = stack_pointer_rtx;
5641 operands[2] = GEN_INT (frame_size
5642 + current_function_outgoing_args_size);
5643 output_add_immediate (operands);
5646 if (arm_fpu_arch == FP_SOFT2)
5648 for (reg = 16; reg < 24; reg++)
5649 if (regs_ever_live[reg] && ! call_used_regs[reg])
5650 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5651 reg_names[reg], REGISTER_PREFIX);
5657 for (reg = 16; reg < 24; reg++)
5659 if (regs_ever_live[reg] && ! call_used_regs[reg])
5661 if (reg - start_reg == 3)
5663 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5664 REGISTER_PREFIX, reg_names[start_reg],
5666 start_reg = reg + 1;
5671 if (reg != start_reg)
5672 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5673 REGISTER_PREFIX, reg_names[start_reg],
5674 reg - start_reg, REGISTER_PREFIX);
5676 start_reg = reg + 1;
5680 /* Just in case the last register checked also needs unstacking. */
5681 if (reg != start_reg)
5682 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5683 REGISTER_PREFIX, reg_names[start_reg],
5684 reg - start_reg, REGISTER_PREFIX);
5687 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5689 if (TARGET_THUMB_INTERWORK)
5691 if (! lr_save_eliminated)
5692 live_regs_mask |= 0x4000;
5694 if (live_regs_mask != 0)
5695 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5697 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5699 else if (lr_save_eliminated)
5700 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5701 : "\tmovs\t%spc, %slr\n"),
5702 REGISTER_PREFIX, REGISTER_PREFIX, f);
5704 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5705 TARGET_APCS_32 ? FALSE : TRUE);
5709 if (live_regs_mask || regs_ever_live[14])
5711 /* Restore the integer regs, and the return address into lr */
5712 if (! lr_save_eliminated)
5713 live_regs_mask |= 0x4000;
5715 if (live_regs_mask != 0)
5716 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5719 if (current_function_pretend_args_size)
5721 /* Unwind the pre-pushed regs */
5722 operands[0] = operands[1] = stack_pointer_rtx;
5723 operands[2] = GEN_INT (current_function_pretend_args_size);
5724 output_add_immediate (operands);
5726 /* And finally, go home */
5727 if (TARGET_THUMB_INTERWORK)
5728 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5729 else if (TARGET_APCS_32)
5730 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5732 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5738 /* Reset the ARM-specific per-function variables. */
5739 current_function_anonymous_args = 0;
5740 after_arm_reorg = 0;
5744 emit_multi_reg_push (mask)
5751 for (i = 0; i < 16; i++)
5752 if (mask & (1 << i))
5755 if (num_regs == 0 || num_regs > 16)
5758 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
5760 for (i = 0; i < 16; i++)
5762 if (mask & (1 << i))
5765 = gen_rtx_SET (VOIDmode,
5766 gen_rtx_MEM (BLKmode,
5767 gen_rtx_PRE_DEC (BLKmode,
5768 stack_pointer_rtx)),
5769 gen_rtx_UNSPEC (BLKmode,
5771 gen_rtx_REG (SImode, i)),
5777 for (j = 1, i++; j < num_regs; i++)
5779 if (mask & (1 << i))
5782 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
5791 emit_sfm (base_reg, count)
5798 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
5801 = gen_rtx_SET (VOIDmode,
5802 gen_rtx_MEM (BLKmode,
5803 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
5804 gen_rtx_UNSPEC (BLKmode,
5805 gen_rtvec (1, gen_rtx_REG (XFmode,
5808 for (i = 1; i < count; i++)
5809 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
5810 gen_rtx_REG (XFmode, base_reg++));
5816 arm_expand_prologue ()
5819 rtx amount = GEN_INT (-(get_frame_size ()
5820 + current_function_outgoing_args_size));
5821 int live_regs_mask = 0;
5822 int store_arg_regs = 0;
5823 int volatile_func = (optimize > 0
5824 && TREE_THIS_VOLATILE (current_function_decl));
5826 /* Naked functions don't have prologues. */
5827 if (arm_naked_function_p (current_function_decl))
5830 if (current_function_anonymous_args && current_function_pretend_args_size)
5833 if (! volatile_func)
5834 for (reg = 0; reg <= 10; reg++)
5835 if (regs_ever_live[reg] && ! call_used_regs[reg])
5836 live_regs_mask |= 1 << reg;
5838 if (! volatile_func && regs_ever_live[14])
5839 live_regs_mask |= 0x4000;
5841 if (frame_pointer_needed)
5843 live_regs_mask |= 0xD800;
5844 emit_insn (gen_movsi (gen_rtx_REG (SImode, 12),
5845 stack_pointer_rtx));
5848 if (current_function_pretend_args_size)
5851 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5854 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5855 GEN_INT (-current_function_pretend_args_size)));
5860 /* If we have to push any regs, then we must push lr as well, or
5861 we won't get a proper return. */
5862 live_regs_mask |= 0x4000;
5863 emit_multi_reg_push (live_regs_mask);
5866 /* For now the integer regs are still pushed in output_func_epilogue (). */
5868 if (! volatile_func)
5870 if (arm_fpu_arch == FP_SOFT2)
5872 for (reg = 23; reg > 15; reg--)
5873 if (regs_ever_live[reg] && ! call_used_regs[reg])
5874 emit_insn (gen_rtx_SET
5876 gen_rtx_MEM (XFmode,
5877 gen_rtx_PRE_DEC (XFmode,
5878 stack_pointer_rtx)),
5879 gen_rtx_REG (XFmode, reg)));
5885 for (reg = 23; reg > 15; reg--)
5887 if (regs_ever_live[reg] && ! call_used_regs[reg])
5889 if (start_reg - reg == 3)
5892 start_reg = reg - 1;
5897 if (start_reg != reg)
5898 emit_sfm (reg + 1, start_reg - reg);
5899 start_reg = reg - 1;
5903 if (start_reg != reg)
5904 emit_sfm (reg + 1, start_reg - reg);
5908 if (frame_pointer_needed)
5909 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, 12),
5911 (-(4 + current_function_pretend_args_size)))));
5913 if (amount != const0_rtx)
5915 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5916 emit_insn (gen_rtx_CLOBBER (VOIDmode,
5917 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
5920 /* If we are profiling, make sure no instructions are scheduled before
5921 the call to mcount. Similarly if the user has requested no
5922 scheduling in the prolog. */
5923 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
5924 emit_insn (gen_blockage ());
5928 /* If CODE is 'd', then the X is a condition operand and the instruction
5929 should only be executed if the condition is true.
5930 if CODE is 'D', then the X is a condition operand and the instruction
5931 should only be executed if the condition is false: however, if the mode
5932 of the comparison is CCFPEmode, then always execute the instruction -- we
5933 do this because in these circumstances !GE does not necessarily imply LT;
5934 in these cases the instruction pattern will take care to make sure that
5935 an instruction containing %d will follow, thereby undoing the effects of
5936 doing this instruction unconditionally.
5937 If CODE is 'N' then X is a floating point operand that must be negated
5939 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5940 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5943 arm_print_operand (stream, x, code)
5951 fputs (ASM_COMMENT_START, stream);
5955 fputs (REGISTER_PREFIX, stream);
5959 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5960 fputs (arm_condition_codes[arm_current_cc], stream);
5966 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5967 r = REAL_VALUE_NEGATE (r);
5968 fprintf (stream, "%s", fp_const_from_val (&r));
5973 if (GET_CODE (x) == CONST_INT)
5976 val = ARM_SIGN_EXTEND (~ INTVAL (x));
5977 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
5982 output_addr_const (stream, x);
5987 fprintf (stream, "%s", arithmetic_instr (x, 1));
5991 fprintf (stream, "%s", arithmetic_instr (x, 0));
5997 char * shift = shift_op (x, & val);
6001 fprintf (stream, ", %s ", shift_op (x, & val));
6003 arm_print_operand (stream, XEXP (x, 1), 0);
6006 fputc ('#', stream);
6007 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6016 fputs (REGISTER_PREFIX, stream);
6017 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6023 fputs (REGISTER_PREFIX, stream);
6024 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6028 fputs (REGISTER_PREFIX, stream);
6029 if (GET_CODE (XEXP (x, 0)) == REG)
6030 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6032 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6036 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
6037 REGISTER_PREFIX, reg_names[REGNO (x) - 1
6038 + ((GET_MODE_SIZE (GET_MODE (x))
6039 + GET_MODE_SIZE (SImode) - 1)
6040 / GET_MODE_SIZE (SImode))]);
6045 fputs (arm_condition_codes[get_arm_condition_code (x)],
6051 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6052 (get_arm_condition_code (x))],
6060 if (GET_CODE (x) == REG)
6062 fputs (REGISTER_PREFIX, stream);
6063 fputs (reg_names[REGNO (x)], stream);
6065 else if (GET_CODE (x) == MEM)
6067 output_memory_reference_mode = GET_MODE (x);
6068 output_address (XEXP (x, 0));
6070 else if (GET_CODE (x) == CONST_DOUBLE)
6071 fprintf (stream, "#%s", fp_immediate_constant (x));
6072 else if (GET_CODE (x) == NEG)
6073 abort (); /* This should never happen now. */
6076 fputc ('#', stream);
6077 output_addr_const (stream, x);
6083 /* A finite state machine takes care of noticing whether or not instructions
6084 can be conditionally executed, and thus decrease execution time and code
6085 size by deleting branch instructions. The fsm is controlled by
6086 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6088 /* The state of the fsm controlling condition codes are:
6089 0: normal, do nothing special
6090 1: make ASM_OUTPUT_OPCODE not output this instruction
6091 2: make ASM_OUTPUT_OPCODE not output this instruction
6092 3: make instructions conditional
6093 4: make instructions conditional
6095 State transitions (state->state by whom under condition):
6096 0 -> 1 final_prescan_insn if the `target' is a label
6097 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6098 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6099 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6100 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6101 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6102 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6103 (the target insn is arm_target_insn).
6105 If the jump clobbers the conditions then we use states 2 and 4.
6107 A similar thing can be done with conditional return insns.
6109 XXX In case the `target' is an unconditional branch, this conditionalising
6110 of the instructions always reduces code size, but not always execution
6111 time. But then, I want to reduce the code size to somewhere near what
6112 /bin/cc produces. */
6114 /* Returns the index of the ARM condition code string in
6115 `arm_condition_codes'. COMPARISON should be an rtx like
6116 `(eq (...) (...))'. */
6118 static enum arm_cond_code
6119 get_arm_condition_code (comparison)
6122 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6124 register enum rtx_code comp_code = GET_CODE (comparison);
6126 if (GET_MODE_CLASS (mode) != MODE_CC)
6127 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6128 XEXP (comparison, 1));
6132 case CC_DNEmode: code = ARM_NE; goto dominance;
6133 case CC_DEQmode: code = ARM_EQ; goto dominance;
6134 case CC_DGEmode: code = ARM_GE; goto dominance;
6135 case CC_DGTmode: code = ARM_GT; goto dominance;
6136 case CC_DLEmode: code = ARM_LE; goto dominance;
6137 case CC_DLTmode: code = ARM_LT; goto dominance;
6138 case CC_DGEUmode: code = ARM_CS; goto dominance;
6139 case CC_DGTUmode: code = ARM_HI; goto dominance;
6140 case CC_DLEUmode: code = ARM_LS; goto dominance;
6141 case CC_DLTUmode: code = ARM_CC;
6144 if (comp_code != EQ && comp_code != NE)
6147 if (comp_code == EQ)
6148 return ARM_INVERSE_CONDITION_CODE (code);
6154 case NE: return ARM_NE;
6155 case EQ: return ARM_EQ;
6156 case GE: return ARM_PL;
6157 case LT: return ARM_MI;
6165 case NE: return ARM_NE;
6166 case EQ: return ARM_EQ;
6173 case GE: return ARM_GE;
6174 case GT: return ARM_GT;
6175 case LE: return ARM_LS;
6176 case LT: return ARM_MI;
6183 case NE: return ARM_NE;
6184 case EQ: return ARM_EQ;
6185 case GE: return ARM_LE;
6186 case GT: return ARM_LT;
6187 case LE: return ARM_GE;
6188 case LT: return ARM_GT;
6189 case GEU: return ARM_LS;
6190 case GTU: return ARM_CC;
6191 case LEU: return ARM_CS;
6192 case LTU: return ARM_HI;
6199 case LTU: return ARM_CS;
6200 case GEU: return ARM_CC;
6207 case NE: return ARM_NE;
6208 case EQ: return ARM_EQ;
6209 case GE: return ARM_GE;
6210 case GT: return ARM_GT;
6211 case LE: return ARM_LE;
6212 case LT: return ARM_LT;
6213 case GEU: return ARM_CS;
6214 case GTU: return ARM_HI;
6215 case LEU: return ARM_LS;
6216 case LTU: return ARM_CC;
6228 arm_final_prescan_insn (insn)
6231 /* BODY will hold the body of INSN. */
6232 register rtx body = PATTERN (insn);
6234 /* This will be 1 if trying to repeat the trick, and things need to be
6235 reversed if it appears to fail. */
6238 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6239 taken are clobbered, even if the rtl suggests otherwise. It also
6240 means that we have to grub around within the jump expression to find
6241 out what the conditions are when the jump isn't taken. */
6242 int jump_clobbers = 0;
6244 /* If we start with a return insn, we only succeed if we find another one. */
6245 int seeking_return = 0;
6247 /* START_INSN will hold the insn from where we start looking. This is the
6248 first insn after the following code_label if REVERSE is true. */
6249 rtx start_insn = insn;
6251 /* If in state 4, check if the target branch is reached, in order to
6252 change back to state 0. */
6253 if (arm_ccfsm_state == 4)
6255 if (insn == arm_target_insn)
6257 arm_target_insn = NULL;
6258 arm_ccfsm_state = 0;
6263 /* If in state 3, it is possible to repeat the trick, if this insn is an
6264 unconditional branch to a label, and immediately following this branch
6265 is the previous target label which is only used once, and the label this
6266 branch jumps to is not too far off. */
6267 if (arm_ccfsm_state == 3)
6269 if (simplejump_p (insn))
6271 start_insn = next_nonnote_insn (start_insn);
6272 if (GET_CODE (start_insn) == BARRIER)
6274 /* XXX Isn't this always a barrier? */
6275 start_insn = next_nonnote_insn (start_insn);
6277 if (GET_CODE (start_insn) == CODE_LABEL
6278 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6279 && LABEL_NUSES (start_insn) == 1)
6284 else if (GET_CODE (body) == RETURN)
6286 start_insn = next_nonnote_insn (start_insn);
6287 if (GET_CODE (start_insn) == BARRIER)
6288 start_insn = next_nonnote_insn (start_insn);
6289 if (GET_CODE (start_insn) == CODE_LABEL
6290 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6291 && LABEL_NUSES (start_insn) == 1)
6303 if (arm_ccfsm_state != 0 && !reverse)
6305 if (GET_CODE (insn) != JUMP_INSN)
6308 /* This jump might be paralleled with a clobber of the condition codes
6309 the jump should always come first */
6310 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6311 body = XVECEXP (body, 0, 0);
6314 /* If this is a conditional return then we don't want to know */
6315 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6316 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6317 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6318 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6323 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6324 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6327 int fail = FALSE, succeed = FALSE;
6328 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6329 int then_not_else = TRUE;
6330 rtx this_insn = start_insn, label = 0;
6332 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6334 /* The code below is wrong for these, and I haven't time to
6335 fix it now. So we just do the safe thing and return. This
6336 whole function needs re-writing anyway. */
6341 /* Register the insn jumped to. */
6344 if (!seeking_return)
6345 label = XEXP (SET_SRC (body), 0);
6347 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6348 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6349 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6351 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6352 then_not_else = FALSE;
6354 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6356 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6359 then_not_else = FALSE;
6364 /* See how many insns this branch skips, and what kind of insns. If all
6365 insns are okay, and the label or unconditional branch to the same
6366 label is not too far away, succeed. */
6367 for (insns_skipped = 0;
6368 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6372 this_insn = next_nonnote_insn (this_insn);
6376 switch (GET_CODE (this_insn))
6379 /* Succeed if it is the target label, otherwise fail since
6380 control falls in from somewhere else. */
6381 if (this_insn == label)
6385 arm_ccfsm_state = 2;
6386 this_insn = next_nonnote_insn (this_insn);
6389 arm_ccfsm_state = 1;
6397 /* Succeed if the following insn is the target label.
6399 If return insns are used then the last insn in a function
6400 will be a barrier. */
6401 this_insn = next_nonnote_insn (this_insn);
6402 if (this_insn && this_insn == label)
6406 arm_ccfsm_state = 2;
6407 this_insn = next_nonnote_insn (this_insn);
6410 arm_ccfsm_state = 1;
6418 /* If using 32-bit addresses the cc is not preserved over
6422 /* Succeed if the following insn is the target label,
6423 or if the following two insns are a barrier and
6424 the target label. */
6425 this_insn = next_nonnote_insn (this_insn);
6426 if (this_insn && GET_CODE (this_insn) == BARRIER)
6427 this_insn = next_nonnote_insn (this_insn);
6429 if (this_insn && this_insn == label
6430 && insns_skipped < max_insns_skipped)
6434 arm_ccfsm_state = 2;
6435 this_insn = next_nonnote_insn (this_insn);
6438 arm_ccfsm_state = 1;
6447 /* If this is an unconditional branch to the same label, succeed.
6448 If it is to another label, do nothing. If it is conditional,
6450 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6452 scanbody = PATTERN (this_insn);
6453 if (GET_CODE (scanbody) == SET
6454 && GET_CODE (SET_DEST (scanbody)) == PC)
6456 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
6457 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
6459 arm_ccfsm_state = 2;
6462 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
6465 /* Fail if a conditional return is undesirable (eg on a
6466 StrongARM), but still allow this if optimizing for size. */
6467 else if (GET_CODE (scanbody) == RETURN
6468 && ! use_return_insn (TRUE)
6471 else if (GET_CODE (scanbody) == RETURN
6474 arm_ccfsm_state = 2;
6477 else if (GET_CODE (scanbody) == PARALLEL)
6479 switch (get_attr_conds (this_insn))
6491 /* Instructions using or affecting the condition codes make it
6493 scanbody = PATTERN (this_insn);
6494 if (! (GET_CODE (scanbody) == SET
6495 || GET_CODE (scanbody) == PARALLEL)
6496 || get_attr_conds (this_insn) != CONDS_NOCOND)
6506 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
6507 arm_target_label = CODE_LABEL_NUMBER (label);
6508 else if (seeking_return || arm_ccfsm_state == 2)
6510 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
6512 this_insn = next_nonnote_insn (this_insn);
6513 if (this_insn && (GET_CODE (this_insn) == BARRIER
6514 || GET_CODE (this_insn) == CODE_LABEL))
6519 /* Oh, dear! we ran off the end.. give up */
6520 recog (PATTERN (insn), insn, NULL_PTR);
6521 arm_ccfsm_state = 0;
6522 arm_target_insn = NULL;
6525 arm_target_insn = this_insn;
6534 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
6536 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
6537 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6538 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
6539 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6543 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6546 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
6550 if (reverse || then_not_else)
6551 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6553 /* restore recog_operand (getting the attributes of other insns can
6554 destroy this array, but final.c assumes that it remains intact
6555 across this call; since the insn has been recognized already we
6556 call recog direct). */
6557 recog (PATTERN (insn), insn, NULL_PTR);
6561 #ifdef AOF_ASSEMBLER
6562 /* Special functions only needed when producing AOF syntax assembler. */
6564 rtx aof_pic_label = NULL_RTX;
6567 struct pic_chain *next;
6571 static struct pic_chain *aof_pic_chain = NULL;
6577 struct pic_chain **chainp;
6580 if (aof_pic_label == NULL_RTX)
6582 /* This needs to persist throughout the compilation. */
6583 end_temporary_allocation ();
6584 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
6585 resume_temporary_allocation ();
6588 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6589 offset += 4, chainp = &(*chainp)->next)
6590 if ((*chainp)->symname == XSTR (x, 0))
6591 return plus_constant (aof_pic_label, offset);
6593 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6594 (*chainp)->next = NULL;
6595 (*chainp)->symname = XSTR (x, 0);
6596 return plus_constant (aof_pic_label, offset);
6600 aof_dump_pic_table (f)
6603 struct pic_chain *chain;
6605 if (aof_pic_chain == NULL)
6608 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
6609 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
6610 reg_names[PIC_OFFSET_TABLE_REGNUM]);
6611 fputs ("|x$adcons|\n", f);
6613 for (chain = aof_pic_chain; chain; chain = chain->next)
6615 fputs ("\tDCD\t", f);
6616 assemble_name (f, chain->symname);
6621 int arm_text_section_count = 1;
6626 static char buf[100];
6627 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6628 arm_text_section_count++);
6630 strcat (buf, ", PIC, REENTRANT");
6634 static int arm_data_section_count = 1;
6639 static char buf[100];
6640 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6644 /* The AOF assembler is religiously strict about declarations of
6645 imported and exported symbols, so that it is impossible to declare
6646 a function as imported near the beginning of the file, and then to
6647 export it later on. It is, however, possible to delay the decision
6648 until all the functions in the file have been compiled. To get
6649 around this, we maintain a list of the imports and exports, and
6650 delete from it any that are subsequently defined. At the end of
6651 compilation we spit the remainder of the list out before the END
6656 struct import *next;
6660 static struct import *imports_list = NULL;
6663 aof_add_import (name)
6668 for (new = imports_list; new; new = new->next)
6669 if (new->name == name)
6672 new = (struct import *) xmalloc (sizeof (struct import));
6673 new->next = imports_list;
6679 aof_delete_import (name)
6682 struct import **old;
6684 for (old = &imports_list; *old; old = & (*old)->next)
6686 if ((*old)->name == name)
6688 *old = (*old)->next;
6694 int arm_main_function = 0;
6697 aof_dump_imports (f)
6700 /* The AOF assembler needs this to cause the startup code to be extracted
6701 from the library. Brining in __main causes the whole thing to work
6703 if (arm_main_function)
6706 fputs ("\tIMPORT __main\n", f);
6707 fputs ("\tDCD __main\n", f);
6710 /* Now dump the remaining imports. */
6711 while (imports_list)
6713 fprintf (f, "\tIMPORT\t");
6714 assemble_name (f, imports_list->name);
6716 imports_list = imports_list->next;
6719 #endif /* AOF_ASSEMBLER */