1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx, int, int, int *);
132 static int arm_address_cost (rtx);
133 static bool arm_memory_load_p (rtx);
134 static bool arm_cirrus_insn_p (rtx);
135 static void cirrus_reorg (rtx);
136 static void arm_init_builtins (void);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx safe_vector_operand (rtx, enum machine_mode);
140 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
141 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
142 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
143 static void emit_constant_insn (rtx cond, rtx pattern);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree, rtx, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx arm_struct_value_rtx (tree, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
161 static bool arm_promote_prototypes (tree);
162 static bool arm_default_short_enums (void);
163 static bool arm_align_anon_bitfield (void);
165 static tree arm_cxx_guard_type (void);
166 static bool arm_cxx_guard_mask_bit (void);
169 /* Initialize the GCC target structure. */
170 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
171 #undef TARGET_MERGE_DECL_ATTRIBUTES
172 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
175 #undef TARGET_ATTRIBUTE_TABLE
176 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
179 #undef TARGET_ASM_BYTE_OP
180 #define TARGET_ASM_BYTE_OP "\tDCB\t"
181 #undef TARGET_ASM_ALIGNED_HI_OP
182 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
185 #undef TARGET_ASM_GLOBALIZE_LABEL
186 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
187 #undef TARGET_ASM_FILE_START
188 #define TARGET_ASM_FILE_START aof_file_start
189 #undef TARGET_ASM_FILE_END
190 #define TARGET_ASM_FILE_END aof_file_end
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP NULL
194 #undef TARGET_ASM_INTEGER
195 #define TARGET_ASM_INTEGER arm_assemble_integer
198 #undef TARGET_ASM_FUNCTION_PROLOGUE
199 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
201 #undef TARGET_ASM_FUNCTION_EPILOGUE
202 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
204 #undef TARGET_COMP_TYPE_ATTRIBUTES
205 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
207 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
208 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
210 #undef TARGET_SCHED_ADJUST_COST
211 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
213 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
214 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
216 #undef TARGET_ENCODE_SECTION_INFO
218 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
220 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
223 #undef TARGET_STRIP_NAME_ENCODING
224 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
226 #undef TARGET_ASM_INTERNAL_LABEL
227 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
229 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
230 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
232 #undef TARGET_ASM_OUTPUT_MI_THUNK
233 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
234 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
235 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
237 /* This will be overridden in arm_override_options. */
238 #undef TARGET_RTX_COSTS
239 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
240 #undef TARGET_ADDRESS_COST
241 #define TARGET_ADDRESS_COST arm_address_cost
243 #undef TARGET_MACHINE_DEPENDENT_REORG
244 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
246 #undef TARGET_INIT_BUILTINS
247 #define TARGET_INIT_BUILTINS arm_init_builtins
248 #undef TARGET_EXPAND_BUILTIN
249 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
251 #undef TARGET_PROMOTE_FUNCTION_ARGS
252 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
253 #undef TARGET_PROMOTE_FUNCTION_RETURN
254 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
255 #undef TARGET_PROMOTE_PROTOTYPES
256 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
258 #undef TARGET_STRUCT_VALUE_RTX
259 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
261 #undef TARGET_SETUP_INCOMING_VARARGS
262 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
264 #undef TARGET_DEFAULT_SHORT_ENUMS
265 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
267 #undef TARGET_ALIGN_ANON_BITFIELD
268 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
270 #undef TARGET_CXX_GUARD_TYPE
271 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
273 #undef TARGET_CXX_GUARD_MASK_BIT
274 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
276 struct gcc_target targetm = TARGET_INITIALIZER;
278 /* Obstack for minipool constant handling. */
279 static struct obstack minipool_obstack;
280 static char * minipool_startobj;
282 /* The maximum number of insns skipped which
283 will be conditionalised if possible. */
284 static int max_insns_skipped = 5;
286 extern FILE * asm_out_file;
288 /* True if we are currently building a constant table. */
289 int making_const_table;
291 /* Define the information needed to generate branch insns. This is
292 stored from the compare operation. */
293 rtx arm_compare_op0, arm_compare_op1;
295 /* The processor for which instructions should be scheduled. */
296 enum processor_type arm_tune = arm_none;
298 /* Which floating point model to use. */
299 enum arm_fp_model arm_fp_model;
301 /* Which floating point hardware is available. */
302 enum fputype arm_fpu_arch;
304 /* Which floating point hardware to schedule for. */
305 enum fputype arm_fpu_tune;
307 /* Whether to use floating point hardware. */
308 enum float_abi_type arm_float_abi;
310 /* Which ABI to use. */
311 enum arm_abi_type arm_abi;
313 /* Set by the -mfpu=... option. */
314 const char * target_fpu_name = NULL;
316 /* Set by the -mfpe=... option. */
317 const char * target_fpe_name = NULL;
319 /* Set by the -mfloat-abi=... option. */
320 const char * target_float_abi_name = NULL;
322 /* Set by the -mabi=... option. */
323 const char * target_abi_name = NULL;
325 /* Used to parse -mstructure_size_boundary command line option. */
326 const char * structure_size_string = NULL;
327 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
329 /* Bit values used to identify processor capabilities. */
330 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
331 #define FL_ARCH3M (1 << 1) /* Extended multiply */
332 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
333 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
334 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
335 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
336 #define FL_THUMB (1 << 6) /* Thumb aware */
337 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
338 #define FL_STRONG (1 << 8) /* StrongARM */
339 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
340 #define FL_XSCALE (1 << 10) /* XScale */
341 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
342 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
343 media instructions. */
344 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
346 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
348 #define FL_FOR_ARCH2 0
349 #define FL_FOR_ARCH3 FL_MODE32
350 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
351 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
352 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
353 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
354 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
355 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
356 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
357 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
358 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
359 #define FL_FOR_ARCH6J FL_FOR_ARCH6
361 /* The bits in this mask specify which
362 instructions we are allowed to generate. */
363 static unsigned long insn_flags = 0;
365 /* The bits in this mask specify which instruction scheduling options should
367 static unsigned long tune_flags = 0;
369 /* The following are used in the arm.md file as equivalents to bits
370 in the above two flag variables. */
372 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
375 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
378 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
381 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
384 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
387 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
390 /* Nonzero if this chip can benefit from load scheduling. */
391 int arm_ld_sched = 0;
393 /* Nonzero if this chip is a StrongARM. */
394 int arm_is_strong = 0;
396 /* Nonzero if this chip is a Cirrus variant. */
397 int arm_arch_cirrus = 0;
399 /* Nonzero if this chip supports Intel Wireless MMX technology. */
400 int arm_arch_iwmmxt = 0;
402 /* Nonzero if this chip is an XScale. */
403 int arm_arch_xscale = 0;
405 /* Nonzero if tuning for XScale */
406 int arm_tune_xscale = 0;
408 /* Nonzero if this chip is an ARM6 or an ARM7. */
409 int arm_is_6_or_7 = 0;
411 /* Nonzero if generating Thumb instructions. */
414 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
415 must report the mode of the memory reference from PRINT_OPERAND to
416 PRINT_OPERAND_ADDRESS. */
417 enum machine_mode output_memory_reference_mode;
419 /* The register number to be used for the PIC offset register. */
420 const char * arm_pic_register_string = NULL;
421 int arm_pic_register = INVALID_REGNUM;
423 /* Set to 1 when a return insn is output, this means that the epilogue
425 int return_used_this_function;
427 /* Set to 1 after arm_reorg has started. Reset to start at the start of
428 the next function. */
429 static int after_arm_reorg = 0;
431 /* The maximum number of insns to be used when loading a constant. */
432 static int arm_constant_limit = 3;
434 /* For an explanation of these variables, see final_prescan_insn below. */
436 enum arm_cond_code arm_current_cc;
438 int arm_target_label;
440 /* The condition codes of the ARM, and the inverse function. */
441 static const char * const arm_condition_codes[] =
443 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
444 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
447 #define streq(string1, string2) (strcmp (string1, string2) == 0)
449 /* Initialization code. */
453 const char *const name;
454 enum processor_type core;
456 const unsigned long flags;
457 bool (* rtx_costs) (rtx, int, int, int *);
460 /* Not all of these give usefully different compilation alternatives,
461 but there is no simple way of generalizing them. */
462 static const struct processors all_cores[] =
465 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
466 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
467 #include "arm-cores.def"
469 {NULL, arm_none, NULL, 0, NULL}
472 static const struct processors all_architectures[] =
474 /* ARM Architectures */
475 /* We don't specify rtx_costs here as it will be figured out
478 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
479 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
480 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
481 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
482 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
483 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
484 implementations that support it, so we will leave it out for now. */
485 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
486 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
487 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
488 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
489 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
490 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
491 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
492 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
493 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
494 {NULL, arm_none, NULL, 0 , NULL}
497 /* This is a magic structure. The 'string' field is magically filled in
498 with a pointer to the value specified by the user on the command line
499 assuming that the user has specified such a value. */
501 struct arm_cpu_select arm_select[] =
503 /* string name processors */
504 { NULL, "-mcpu=", all_cores },
505 { NULL, "-march=", all_architectures },
506 { NULL, "-mtune=", all_cores }
510 /* The name of the proprocessor macro to define for this architecture. */
512 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
521 /* Available values for for -mfpu=. */
523 static const struct fpu_desc all_fpus[] =
525 {"fpa", FPUTYPE_FPA},
526 {"fpe2", FPUTYPE_FPA_EMU2},
527 {"fpe3", FPUTYPE_FPA_EMU2},
528 {"maverick", FPUTYPE_MAVERICK},
533 /* Floating point models used by the different hardware.
534 See fputype in arm.h. */
536 static const enum fputype fp_model_for_fpu[] =
538 /* No FP hardware. */
539 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
540 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
541 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
542 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
543 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
544 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
551 enum float_abi_type abi_type;
555 /* Available values for -mfloat-abi=. */
557 static const struct float_abi all_float_abis[] =
559 {"soft", ARM_FLOAT_ABI_SOFT},
560 {"softfp", ARM_FLOAT_ABI_SOFTFP},
561 {"hard", ARM_FLOAT_ABI_HARD}
568 enum arm_abi_type abi_type;
572 /* Available values for -mabi=. */
574 static const struct abi_name arm_all_abis[] =
576 {"apcs-gnu", ARM_ABI_APCS},
577 {"atpcs", ARM_ABI_ATPCS},
578 {"aapcs", ARM_ABI_AAPCS},
579 {"iwmmxt", ARM_ABI_IWMMXT}
582 /* Return the number of bits set in VALUE. */
584 bit_count (unsigned long value)
586 unsigned long count = 0;
591 value &= value - 1; /* Clear the least-significant set bit. */
597 /* Fix up any incompatible options that the user has specified.
598 This has now turned into a maze. */
600 arm_override_options (void)
604 /* Set up the flags based on the cpu/architecture selected by the user. */
605 for (i = ARRAY_SIZE (arm_select); i--;)
607 struct arm_cpu_select * ptr = arm_select + i;
609 if (ptr->string != NULL && ptr->string[0] != '\0')
611 const struct processors * sel;
613 for (sel = ptr->processors; sel->name != NULL; sel++)
614 if (streq (ptr->string, sel->name))
616 /* Set the architecture define. */
618 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
620 /* Determine the processor core for which we should
621 tune code-generation. */
622 if (/* -mcpu= is a sensible default. */
624 /* If -march= is used, and -mcpu= has not been used,
625 assume that we should tune for a representative
626 CPU from that architecture. */
628 /* -mtune= overrides -mcpu= and -march=. */
630 arm_tune = (enum processor_type) (sel - ptr->processors);
634 /* If we have been given an architecture and a processor
635 make sure that they are compatible. We only generate
636 a warning though, and we prefer the CPU over the
638 if (insn_flags != 0 && (insn_flags ^ sel->flags))
639 warning ("switch -mcpu=%s conflicts with -march= switch",
642 insn_flags = sel->flags;
648 if (sel->name == NULL)
649 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
653 /* If the user did not specify a processor, choose one for them. */
656 const struct processors * sel;
658 enum processor_type cpu;
660 cpu = TARGET_CPU_DEFAULT;
663 #ifdef SUBTARGET_CPU_DEFAULT
664 /* Use the subtarget default CPU if none was specified by
666 cpu = SUBTARGET_CPU_DEFAULT;
668 /* Default to ARM6. */
672 sel = &all_cores[cpu];
674 insn_flags = sel->flags;
676 /* Now check to see if the user has specified some command line
677 switch that require certain abilities from the cpu. */
680 if (TARGET_INTERWORK || TARGET_THUMB)
682 sought |= (FL_THUMB | FL_MODE32);
684 /* There are no ARM processors that support both APCS-26 and
685 interworking. Therefore we force FL_MODE26 to be removed
686 from insn_flags here (if it was set), so that the search
687 below will always be able to find a compatible processor. */
688 insn_flags &= ~FL_MODE26;
691 if (sought != 0 && ((sought & insn_flags) != sought))
693 /* Try to locate a CPU type that supports all of the abilities
694 of the default CPU, plus the extra abilities requested by
696 for (sel = all_cores; sel->name != NULL; sel++)
697 if ((sel->flags & sought) == (sought | insn_flags))
700 if (sel->name == NULL)
702 unsigned current_bit_count = 0;
703 const struct processors * best_fit = NULL;
705 /* Ideally we would like to issue an error message here
706 saying that it was not possible to find a CPU compatible
707 with the default CPU, but which also supports the command
708 line options specified by the programmer, and so they
709 ought to use the -mcpu=<name> command line option to
710 override the default CPU type.
712 If we cannot find a cpu that has both the
713 characteristics of the default cpu and the given
714 command line options we scan the array again looking
716 for (sel = all_cores; sel->name != NULL; sel++)
717 if ((sel->flags & sought) == sought)
721 count = bit_count (sel->flags & insn_flags);
723 if (count >= current_bit_count)
726 current_bit_count = count;
730 if (best_fit == NULL)
736 insn_flags = sel->flags;
738 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
739 if (arm_tune == arm_none)
740 arm_tune = (enum processor_type) (sel - all_cores);
743 /* The processor for which we should tune should now have been
745 if (arm_tune == arm_none)
748 tune_flags = all_cores[(int)arm_tune].flags;
749 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
751 /* Make sure that the processor choice does not conflict with any of the
752 other command line choices. */
753 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
755 warning ("target CPU does not support interworking" );
756 target_flags &= ~ARM_FLAG_INTERWORK;
759 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
761 warning ("target CPU does not support THUMB instructions");
762 target_flags &= ~ARM_FLAG_THUMB;
765 if (TARGET_APCS_FRAME && TARGET_THUMB)
767 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
768 target_flags &= ~ARM_FLAG_APCS_FRAME;
771 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
772 from here where no function is being compiled currently. */
773 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
775 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
777 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
778 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
780 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
781 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
783 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
785 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
786 target_flags |= ARM_FLAG_APCS_FRAME;
789 if (TARGET_POKE_FUNCTION_NAME)
790 target_flags |= ARM_FLAG_APCS_FRAME;
792 if (TARGET_APCS_REENT && flag_pic)
793 error ("-fpic and -mapcs-reent are incompatible");
795 if (TARGET_APCS_REENT)
796 warning ("APCS reentrant code not supported. Ignored");
798 /* If this target is normally configured to use APCS frames, warn if they
799 are turned off and debugging is turned on. */
801 && write_symbols != NO_DEBUG
802 && !TARGET_APCS_FRAME
803 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
804 warning ("-g with -mno-apcs-frame may not give sensible debugging");
806 /* If stack checking is disabled, we can use r10 as the PIC register,
807 which keeps r9 available. */
809 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
811 if (TARGET_APCS_FLOAT)
812 warning ("passing floating point arguments in fp regs not yet supported");
814 /* Initialize boolean versions of the flags, for use in the arm.md file. */
815 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
816 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
817 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
818 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
819 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
820 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
821 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
822 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
824 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
825 arm_is_strong = (tune_flags & FL_STRONG) != 0;
826 thumb_code = (TARGET_ARM == 0);
827 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
828 && !(tune_flags & FL_ARCH4))) != 0;
829 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
830 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
832 /* V5 code we generate is completely interworking capable, so we turn off
833 TARGET_INTERWORK here to avoid many tests later on. */
835 target_flags &= ~ARM_FLAG_INTERWORK;
839 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
841 if (streq (arm_all_abis[i].name, target_abi_name))
843 arm_abi = arm_all_abis[i].abi_type;
847 if (i == ARRAY_SIZE (arm_all_abis))
848 error ("invalid ABI option: -mabi=%s", target_abi_name);
851 arm_abi = ARM_DEFAULT_ABI;
853 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
854 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
856 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
857 error ("iwmmxt abi requires an iwmmxt capable cpu");
859 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
860 if (target_fpu_name == NULL && target_fpe_name != NULL)
862 if (streq (target_fpe_name, "2"))
863 target_fpu_name = "fpe2";
864 else if (streq (target_fpe_name, "3"))
865 target_fpu_name = "fpe3";
867 error ("invalid floating point emulation option: -mfpe=%s",
870 if (target_fpu_name != NULL)
872 /* The user specified a FPU. */
873 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
875 if (streq (all_fpus[i].name, target_fpu_name))
877 arm_fpu_arch = all_fpus[i].fpu;
878 arm_fpu_tune = arm_fpu_arch;
879 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
883 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
884 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
888 #ifdef FPUTYPE_DEFAULT
889 /* Use the default if it is specified for this platform. */
890 arm_fpu_arch = FPUTYPE_DEFAULT;
891 arm_fpu_tune = FPUTYPE_DEFAULT;
893 /* Pick one based on CPU type. */
894 /* ??? Some targets assume FPA is the default.
895 if ((insn_flags & FL_VFP) != 0)
896 arm_fpu_arch = FPUTYPE_VFP;
900 arm_fpu_arch = FPUTYPE_MAVERICK;
902 arm_fpu_arch = FPUTYPE_FPA_EMU2;
904 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
905 arm_fpu_tune = FPUTYPE_FPA;
907 arm_fpu_tune = arm_fpu_arch;
908 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
909 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
913 if (target_float_abi_name != NULL)
915 /* The user specified a FP ABI. */
916 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
918 if (streq (all_float_abis[i].name, target_float_abi_name))
920 arm_float_abi = all_float_abis[i].abi_type;
924 if (i == ARRAY_SIZE (all_float_abis))
925 error ("invalid floating point abi: -mfloat-abi=%s",
926 target_float_abi_name);
930 /* Use soft-float target flag. */
931 if (target_flags & ARM_FLAG_SOFT_FLOAT)
932 arm_float_abi = ARM_FLOAT_ABI_SOFT;
934 arm_float_abi = ARM_FLOAT_ABI_HARD;
937 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
938 sorry ("-mfloat-abi=softfp");
939 /* If soft-float is specified then don't use FPU. */
940 if (TARGET_SOFT_FLOAT)
941 arm_fpu_arch = FPUTYPE_NONE;
943 /* For arm2/3 there is no need to do any scheduling if there is only
944 a floating point emulator, or we are doing software floating-point. */
945 if ((TARGET_SOFT_FLOAT
946 || arm_fpu_tune == FPUTYPE_FPA_EMU2
947 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
948 && (tune_flags & FL_MODE32) == 0)
949 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
951 /* Override the default structure alignment for AAPCS ABI. */
952 if (arm_abi == ARM_ABI_AAPCS)
953 arm_structure_size_boundary = 8;
955 if (structure_size_string != NULL)
957 int size = strtol (structure_size_string, NULL, 0);
959 if (size == 8 || size == 32
960 || (ARM_DOUBLEWORD_ALIGN && size == 64))
961 arm_structure_size_boundary = size;
963 warning ("structure size boundary can only be set to %s",
964 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
967 if (arm_pic_register_string != NULL)
969 int pic_register = decode_reg_name (arm_pic_register_string);
972 warning ("-mpic-register= is useless without -fpic");
974 /* Prevent the user from choosing an obviously stupid PIC register. */
975 else if (pic_register < 0 || call_used_regs[pic_register]
976 || pic_register == HARD_FRAME_POINTER_REGNUM
977 || pic_register == STACK_POINTER_REGNUM
978 || pic_register >= PC_REGNUM)
979 error ("unable to use '%s' for PIC register", arm_pic_register_string);
981 arm_pic_register = pic_register;
984 if (TARGET_THUMB && flag_schedule_insns)
986 /* Don't warn since it's on by default in -O2. */
987 flag_schedule_insns = 0;
992 /* There's some dispute as to whether this should be 1 or 2. However,
993 experiments seem to show that in pathological cases a setting of
994 1 degrades less severely than a setting of 2. This could change if
995 other parts of the compiler change their behavior. */
996 arm_constant_limit = 1;
998 /* If optimizing for size, bump the number of instructions that we
999 are prepared to conditionally execute (even on a StrongARM). */
1000 max_insns_skipped = 6;
1004 /* For processors with load scheduling, it never costs more than
1005 2 cycles to load a constant, and the load scheduler may well
1006 reduce that to 1. */
1007 if (tune_flags & FL_LDSCHED)
1008 arm_constant_limit = 1;
1010 /* On XScale the longer latency of a load makes it more difficult
1011 to achieve a good schedule, so it's faster to synthesize
1012 constants that can be done in two insns. */
1013 if (arm_tune_xscale)
1014 arm_constant_limit = 2;
1016 /* StrongARM has early execution of branches, so a sequence
1017 that is worth skipping is shorter. */
1019 max_insns_skipped = 3;
1022 /* Register global variables with the garbage collector. */
1023 arm_add_gc_roots ();
1027 arm_add_gc_roots (void)
1029 gcc_obstack_init(&minipool_obstack);
1030 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1033 /* A table of known ARM exception types.
1034 For use with the interrupt function attribute. */
1038 const char *const arg;
1039 const unsigned long return_value;
1043 static const isr_attribute_arg isr_attribute_args [] =
1045 { "IRQ", ARM_FT_ISR },
1046 { "irq", ARM_FT_ISR },
1047 { "FIQ", ARM_FT_FIQ },
1048 { "fiq", ARM_FT_FIQ },
1049 { "ABORT", ARM_FT_ISR },
1050 { "abort", ARM_FT_ISR },
1051 { "ABORT", ARM_FT_ISR },
1052 { "abort", ARM_FT_ISR },
1053 { "UNDEF", ARM_FT_EXCEPTION },
1054 { "undef", ARM_FT_EXCEPTION },
1055 { "SWI", ARM_FT_EXCEPTION },
1056 { "swi", ARM_FT_EXCEPTION },
1057 { NULL, ARM_FT_NORMAL }
1060 /* Returns the (interrupt) function type of the current
1061 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1063 static unsigned long
1064 arm_isr_value (tree argument)
1066 const isr_attribute_arg * ptr;
1069 /* No argument - default to IRQ. */
1070 if (argument == NULL_TREE)
1073 /* Get the value of the argument. */
1074 if (TREE_VALUE (argument) == NULL_TREE
1075 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1076 return ARM_FT_UNKNOWN;
1078 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1080 /* Check it against the list of known arguments. */
1081 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1082 if (streq (arg, ptr->arg))
1083 return ptr->return_value;
1085 /* An unrecognized interrupt type. */
1086 return ARM_FT_UNKNOWN;
1089 /* Computes the type of the current function. */
1091 static unsigned long
1092 arm_compute_func_type (void)
1094 unsigned long type = ARM_FT_UNKNOWN;
1098 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1101 /* Decide if the current function is volatile. Such functions
1102 never return, and many memory cycles can be saved by not storing
1103 register values that will never be needed again. This optimization
1104 was added to speed up context switching in a kernel application. */
1106 && current_function_nothrow
1107 && TREE_THIS_VOLATILE (current_function_decl))
1108 type |= ARM_FT_VOLATILE;
1110 if (cfun->static_chain_decl != NULL)
1111 type |= ARM_FT_NESTED;
1113 attr = DECL_ATTRIBUTES (current_function_decl);
1115 a = lookup_attribute ("naked", attr);
1117 type |= ARM_FT_NAKED;
1119 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1120 type |= ARM_FT_EXCEPTION_HANDLER;
1123 a = lookup_attribute ("isr", attr);
1125 a = lookup_attribute ("interrupt", attr);
1128 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1130 type |= arm_isr_value (TREE_VALUE (a));
1136 /* Returns the type of the current function. */
1139 arm_current_func_type (void)
1141 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1142 cfun->machine->func_type = arm_compute_func_type ();
1144 return cfun->machine->func_type;
1147 /* Return 1 if it is possible to return using a single instruction.
1148 If SIBLING is non-null, this is a test for a return before a sibling
1149 call. SIBLING is the call insn, so we can examine its register usage. */
1152 use_return_insn (int iscond, rtx sibling)
1155 unsigned int func_type;
1156 unsigned long saved_int_regs;
1157 unsigned HOST_WIDE_INT stack_adjust;
1158 arm_stack_offsets *offsets;
1160 /* Never use a return instruction before reload has run. */
1161 if (!reload_completed)
1164 func_type = arm_current_func_type ();
1166 /* Naked functions and volatile functions need special
1168 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1171 /* So do interrupt functions that use the frame pointer. */
1172 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1175 offsets = arm_get_frame_offsets ();
1176 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1178 /* As do variadic functions. */
1179 if (current_function_pretend_args_size
1180 || cfun->machine->uses_anonymous_args
1181 /* Or if the function calls __builtin_eh_return () */
1182 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1183 /* Or if the function calls alloca */
1184 || current_function_calls_alloca
1185 /* Or if there is a stack adjustment. However, if the stack pointer
1186 is saved on the stack, we can use a pre-incrementing stack load. */
1187 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1190 saved_int_regs = arm_compute_save_reg_mask ();
1192 /* Unfortunately, the insn
1194 ldmib sp, {..., sp, ...}
1196 triggers a bug on most SA-110 based devices, such that the stack
1197 pointer won't be correctly restored if the instruction takes a
1198 page fault. We work around this problem by popping r3 along with
1199 the other registers, since that is never slower than executing
1200 another instruction.
1202 We test for !arm_arch5 here, because code for any architecture
1203 less than this could potentially be run on one of the buggy
1205 if (stack_adjust == 4 && !arm_arch5)
1207 /* Validate that r3 is a call-clobbered register (always true in
1208 the default abi) ... */
1209 if (!call_used_regs[3])
1212 /* ... that it isn't being used for a return value (always true
1213 until we implement return-in-regs), or for a tail-call
1217 if (GET_CODE (sibling) != CALL_INSN)
1220 if (find_regno_fusage (sibling, USE, 3))
1224 /* ... and that there are no call-saved registers in r0-r2
1225 (always true in the default ABI). */
1226 if (saved_int_regs & 0x7)
1230 /* Can't be done if interworking with Thumb, and any registers have been
1232 if (TARGET_INTERWORK && saved_int_regs != 0)
1235 /* On StrongARM, conditional returns are expensive if they aren't
1236 taken and multiple registers have been stacked. */
1237 if (iscond && arm_is_strong)
1239 /* Conditional return when just the LR is stored is a simple
1240 conditional-load instruction, that's not expensive. */
1241 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1244 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1248 /* If there are saved registers but the LR isn't saved, then we need
1249 two instructions for the return. */
1250 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1253 /* Can't be done if any of the FPA regs are pushed,
1254 since this also requires an insn. */
1255 if (TARGET_HARD_FLOAT && TARGET_FPA)
1256 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1257 if (regs_ever_live[regno] && !call_used_regs[regno])
1260 /* Likewise VFP regs. */
1261 if (TARGET_HARD_FLOAT && TARGET_VFP)
1262 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1263 if (regs_ever_live[regno] && !call_used_regs[regno])
1266 if (TARGET_REALLY_IWMMXT)
1267 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1268 if (regs_ever_live[regno] && ! call_used_regs [regno])
1274 /* Return TRUE if int I is a valid immediate ARM constant. */
1277 const_ok_for_arm (HOST_WIDE_INT i)
1279 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1281 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1282 be all zero, or all one. */
1283 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1284 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1285 != ((~(unsigned HOST_WIDE_INT) 0)
1286 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1289 /* Fast return for 0 and powers of 2 */
1290 if ((i & (i - 1)) == 0)
1295 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1298 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1299 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1301 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1306 /* Return true if I is a valid constant for the operation CODE. */
1308 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1310 if (const_ok_for_arm (i))
1316 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1318 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1324 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1331 /* Emit a sequence of insns to handle a large constant.
1332 CODE is the code of the operation required, it can be any of SET, PLUS,
1333 IOR, AND, XOR, MINUS;
1334 MODE is the mode in which the operation is being performed;
1335 VAL is the integer to operate on;
1336 SOURCE is the other operand (a register, or a null-pointer for SET);
1337 SUBTARGETS means it is safe to create scratch registers if that will
1338 either produce a simpler sequence, or we will want to cse the values.
1339 Return value is the number of insns emitted. */
1342 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1343 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1347 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1348 cond = COND_EXEC_TEST (PATTERN (insn));
1352 if (subtargets || code == SET
1353 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1354 && REGNO (target) != REGNO (source)))
1356 /* After arm_reorg has been called, we can't fix up expensive
1357 constants by pushing them into memory so we must synthesize
1358 them in-line, regardless of the cost. This is only likely to
1359 be more costly on chips that have load delay slots and we are
1360 compiling without running the scheduler (so no splitting
1361 occurred before the final instruction emission).
1363 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1365 if (!after_arm_reorg
1367 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1369 > arm_constant_limit + (code != SET)))
1373 /* Currently SET is the only monadic value for CODE, all
1374 the rest are diadic. */
1375 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1380 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1382 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1383 /* For MINUS, the value is subtracted from, since we never
1384 have subtraction of a constant. */
1386 emit_insn (gen_rtx_SET (VOIDmode, target,
1387 gen_rtx_MINUS (mode, temp, source)));
1389 emit_insn (gen_rtx_SET (VOIDmode, target,
1390 gen_rtx_fmt_ee (code, mode, source, temp)));
1396 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1401 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1403 HOST_WIDE_INT temp1;
1411 if (remainder & (3 << (i - 2)))
1416 temp1 = remainder & ((0x0ff << end)
1417 | ((i < end) ? (0xff >> (32 - end)) : 0));
1418 remainder &= ~temp1;
1423 } while (remainder);
1427 /* Emit an instruction with the indicated PATTERN. If COND is
1428 non-NULL, conditionalize the execution of the instruction on COND
1432 emit_constant_insn (rtx cond, rtx pattern)
1435 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1436 emit_insn (pattern);
1439 /* As above, but extra parameter GENERATE which, if clear, suppresses
1443 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1444 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1449 int can_negate_initial = 0;
1452 int num_bits_set = 0;
1453 int set_sign_bit_copies = 0;
1454 int clear_sign_bit_copies = 0;
1455 int clear_zero_bit_copies = 0;
1456 int set_zero_bit_copies = 0;
1458 unsigned HOST_WIDE_INT temp1, temp2;
1459 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1461 /* Find out which operations are safe for a given CODE. Also do a quick
1462 check for degenerate cases; these can occur when DImode operations
1474 can_negate_initial = 1;
1478 if (remainder == 0xffffffff)
1481 emit_constant_insn (cond,
1482 gen_rtx_SET (VOIDmode, target,
1483 GEN_INT (ARM_SIGN_EXTEND (val))));
1488 if (reload_completed && rtx_equal_p (target, source))
1491 emit_constant_insn (cond,
1492 gen_rtx_SET (VOIDmode, target, source));
1501 emit_constant_insn (cond,
1502 gen_rtx_SET (VOIDmode, target, const0_rtx));
1505 if (remainder == 0xffffffff)
1507 if (reload_completed && rtx_equal_p (target, source))
1510 emit_constant_insn (cond,
1511 gen_rtx_SET (VOIDmode, target, source));
1520 if (reload_completed && rtx_equal_p (target, source))
1523 emit_constant_insn (cond,
1524 gen_rtx_SET (VOIDmode, target, source));
1527 if (remainder == 0xffffffff)
1530 emit_constant_insn (cond,
1531 gen_rtx_SET (VOIDmode, target,
1532 gen_rtx_NOT (mode, source)));
1536 /* We don't know how to handle this yet below. */
1540 /* We treat MINUS as (val - source), since (source - val) is always
1541 passed as (source + (-val)). */
1545 emit_constant_insn (cond,
1546 gen_rtx_SET (VOIDmode, target,
1547 gen_rtx_NEG (mode, source)));
1550 if (const_ok_for_arm (val))
1553 emit_constant_insn (cond,
1554 gen_rtx_SET (VOIDmode, target,
1555 gen_rtx_MINUS (mode, GEN_INT (val),
1567 /* If we can do it in one insn get out quickly. */
1568 if (const_ok_for_arm (val)
1569 || (can_negate_initial && const_ok_for_arm (-val))
1570 || (can_invert && const_ok_for_arm (~val)))
1573 emit_constant_insn (cond,
1574 gen_rtx_SET (VOIDmode, target,
1576 ? gen_rtx_fmt_ee (code, mode, source,
1582 /* Calculate a few attributes that may be useful for specific
1584 for (i = 31; i >= 0; i--)
1586 if ((remainder & (1 << i)) == 0)
1587 clear_sign_bit_copies++;
1592 for (i = 31; i >= 0; i--)
1594 if ((remainder & (1 << i)) != 0)
1595 set_sign_bit_copies++;
1600 for (i = 0; i <= 31; i++)
1602 if ((remainder & (1 << i)) == 0)
1603 clear_zero_bit_copies++;
1608 for (i = 0; i <= 31; i++)
1610 if ((remainder & (1 << i)) != 0)
1611 set_zero_bit_copies++;
1619 /* See if we can do this by sign_extending a constant that is known
1620 to be negative. This is a good, way of doing it, since the shift
1621 may well merge into a subsequent insn. */
1622 if (set_sign_bit_copies > 1)
1624 if (const_ok_for_arm
1625 (temp1 = ARM_SIGN_EXTEND (remainder
1626 << (set_sign_bit_copies - 1))))
1630 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1631 emit_constant_insn (cond,
1632 gen_rtx_SET (VOIDmode, new_src,
1634 emit_constant_insn (cond,
1635 gen_ashrsi3 (target, new_src,
1636 GEN_INT (set_sign_bit_copies - 1)));
1640 /* For an inverted constant, we will need to set the low bits,
1641 these will be shifted out of harm's way. */
1642 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1643 if (const_ok_for_arm (~temp1))
1647 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1648 emit_constant_insn (cond,
1649 gen_rtx_SET (VOIDmode, new_src,
1651 emit_constant_insn (cond,
1652 gen_ashrsi3 (target, new_src,
1653 GEN_INT (set_sign_bit_copies - 1)));
1659 /* See if we can generate this by setting the bottom (or the top)
1660 16 bits, and then shifting these into the other half of the
1661 word. We only look for the simplest cases, to do more would cost
1662 too much. Be careful, however, not to generate this when the
1663 alternative would take fewer insns. */
1664 if (val & 0xffff0000)
1666 temp1 = remainder & 0xffff0000;
1667 temp2 = remainder & 0x0000ffff;
1669 /* Overlaps outside this range are best done using other methods. */
1670 for (i = 9; i < 24; i++)
1672 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1673 && !const_ok_for_arm (temp2))
1675 rtx new_src = (subtargets
1676 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1678 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1679 source, subtargets, generate);
1687 gen_rtx_ASHIFT (mode, source,
1694 /* Don't duplicate cases already considered. */
1695 for (i = 17; i < 24; i++)
1697 if (((temp1 | (temp1 >> i)) == remainder)
1698 && !const_ok_for_arm (temp1))
1700 rtx new_src = (subtargets
1701 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1703 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1704 source, subtargets, generate);
1709 gen_rtx_SET (VOIDmode, target,
1712 gen_rtx_LSHIFTRT (mode, source,
1723 /* If we have IOR or XOR, and the constant can be loaded in a
1724 single instruction, and we can find a temporary to put it in,
1725 then this can be done in two instructions instead of 3-4. */
1727 /* TARGET can't be NULL if SUBTARGETS is 0 */
1728 || (reload_completed && !reg_mentioned_p (target, source)))
1730 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1734 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1736 emit_constant_insn (cond,
1737 gen_rtx_SET (VOIDmode, sub,
1739 emit_constant_insn (cond,
1740 gen_rtx_SET (VOIDmode, target,
1741 gen_rtx_fmt_ee (code, mode,
1751 if (set_sign_bit_copies > 8
1752 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1756 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1757 rtx shift = GEN_INT (set_sign_bit_copies);
1761 gen_rtx_SET (VOIDmode, sub,
1763 gen_rtx_ASHIFT (mode,
1768 gen_rtx_SET (VOIDmode, target,
1770 gen_rtx_LSHIFTRT (mode, sub,
1776 if (set_zero_bit_copies > 8
1777 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1781 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1782 rtx shift = GEN_INT (set_zero_bit_copies);
1786 gen_rtx_SET (VOIDmode, sub,
1788 gen_rtx_LSHIFTRT (mode,
1793 gen_rtx_SET (VOIDmode, target,
1795 gen_rtx_ASHIFT (mode, sub,
1801 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1805 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1806 emit_constant_insn (cond,
1807 gen_rtx_SET (VOIDmode, sub,
1808 gen_rtx_NOT (mode, source)));
1811 sub = gen_reg_rtx (mode);
1812 emit_constant_insn (cond,
1813 gen_rtx_SET (VOIDmode, sub,
1814 gen_rtx_AND (mode, source,
1816 emit_constant_insn (cond,
1817 gen_rtx_SET (VOIDmode, target,
1818 gen_rtx_NOT (mode, sub)));
1825 /* See if two shifts will do 2 or more insn's worth of work. */
1826 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1828 HOST_WIDE_INT shift_mask = ((0xffffffff
1829 << (32 - clear_sign_bit_copies))
1832 if ((remainder | shift_mask) != 0xffffffff)
1836 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1837 insns = arm_gen_constant (AND, mode, cond,
1838 remainder | shift_mask,
1839 new_src, source, subtargets, 1);
1844 rtx targ = subtargets ? NULL_RTX : target;
1845 insns = arm_gen_constant (AND, mode, cond,
1846 remainder | shift_mask,
1847 targ, source, subtargets, 0);
1853 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1854 rtx shift = GEN_INT (clear_sign_bit_copies);
1856 emit_insn (gen_ashlsi3 (new_src, source, shift));
1857 emit_insn (gen_lshrsi3 (target, new_src, shift));
1863 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1865 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1867 if ((remainder | shift_mask) != 0xffffffff)
1871 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1873 insns = arm_gen_constant (AND, mode, cond,
1874 remainder | shift_mask,
1875 new_src, source, subtargets, 1);
1880 rtx targ = subtargets ? NULL_RTX : target;
1882 insns = arm_gen_constant (AND, mode, cond,
1883 remainder | shift_mask,
1884 targ, source, subtargets, 0);
1890 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1891 rtx shift = GEN_INT (clear_zero_bit_copies);
1893 emit_insn (gen_lshrsi3 (new_src, source, shift));
1894 emit_insn (gen_ashlsi3 (target, new_src, shift));
1906 for (i = 0; i < 32; i++)
1907 if (remainder & (1 << i))
1910 if (code == AND || (can_invert && num_bits_set > 16))
1911 remainder = (~remainder) & 0xffffffff;
1912 else if (code == PLUS && num_bits_set > 16)
1913 remainder = (-remainder) & 0xffffffff;
1920 /* Now try and find a way of doing the job in either two or three
1922 We start by looking for the largest block of zeros that are aligned on
1923 a 2-bit boundary, we then fill up the temps, wrapping around to the
1924 top of the word when we drop off the bottom.
1925 In the worst case this code should produce no more than four insns. */
1928 int best_consecutive_zeros = 0;
1930 for (i = 0; i < 32; i += 2)
1932 int consecutive_zeros = 0;
1934 if (!(remainder & (3 << i)))
1936 while ((i < 32) && !(remainder & (3 << i)))
1938 consecutive_zeros += 2;
1941 if (consecutive_zeros > best_consecutive_zeros)
1943 best_consecutive_zeros = consecutive_zeros;
1944 best_start = i - consecutive_zeros;
1950 /* So long as it won't require any more insns to do so, it's
1951 desirable to emit a small constant (in bits 0...9) in the last
1952 insn. This way there is more chance that it can be combined with
1953 a later addressing insn to form a pre-indexed load or store
1954 operation. Consider:
1956 *((volatile int *)0xe0000100) = 1;
1957 *((volatile int *)0xe0000110) = 2;
1959 We want this to wind up as:
1963 str rB, [rA, #0x100]
1965 str rB, [rA, #0x110]
1967 rather than having to synthesize both large constants from scratch.
1969 Therefore, we calculate how many insns would be required to emit
1970 the constant starting from `best_start', and also starting from
1971 zero (ie with bit 31 first to be output). If `best_start' doesn't
1972 yield a shorter sequence, we may as well use zero. */
1974 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1975 && (count_insns_for_constant (remainder, 0) <=
1976 count_insns_for_constant (remainder, best_start)))
1979 /* Now start emitting the insns. */
1987 if (remainder & (3 << (i - 2)))
1992 temp1 = remainder & ((0x0ff << end)
1993 | ((i < end) ? (0xff >> (32 - end)) : 0));
1994 remainder &= ~temp1;
1998 rtx new_src, temp1_rtx;
2000 if (code == SET || code == MINUS)
2002 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2003 if (can_invert && code != MINUS)
2008 if (remainder && subtargets)
2009 new_src = gen_reg_rtx (mode);
2014 else if (can_negate)
2018 temp1 = trunc_int_for_mode (temp1, mode);
2019 temp1_rtx = GEN_INT (temp1);
2023 else if (code == MINUS)
2024 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2026 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2028 emit_constant_insn (cond,
2029 gen_rtx_SET (VOIDmode, new_src,
2039 else if (code == MINUS)
2053 /* Canonicalize a comparison so that we are more likely to recognize it.
2054 This can be done for a few constant compares, where we can make the
2055 immediate value easier to load. */
2058 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2060 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2070 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2071 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2073 *op1 = GEN_INT (i + 1);
2074 return code == GT ? GE : LT;
2080 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2081 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2083 *op1 = GEN_INT (i - 1);
2084 return code == GE ? GT : LE;
2090 if (i != ~((unsigned HOST_WIDE_INT) 0)
2091 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2093 *op1 = GEN_INT (i + 1);
2094 return code == GTU ? GEU : LTU;
2101 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2103 *op1 = GEN_INT (i - 1);
2104 return code == GEU ? GTU : LEU;
2116 /* Define how to find the value returned by a function. */
2118 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2120 enum machine_mode mode;
2121 int unsignedp ATTRIBUTE_UNUSED;
2122 rtx r ATTRIBUTE_UNUSED;
2125 mode = TYPE_MODE (type);
2126 /* Promote integer types. */
2127 if (INTEGRAL_TYPE_P (type))
2128 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2129 return LIBCALL_VALUE(mode);
2133 /* Decide whether a type should be returned in memory (true)
2134 or in a register (false). This is called by the macro
2135 RETURN_IN_MEMORY. */
2137 arm_return_in_memory (tree type)
2141 if (!AGGREGATE_TYPE_P (type))
2142 /* All simple types are returned in registers. */
2145 size = int_size_in_bytes (type);
2147 if (arm_abi != ARM_ABI_APCS)
2149 /* ATPCS and later return aggregate types in memory only if they are
2150 larger than a word (or are variable size). */
2151 return (size < 0 || size > UNITS_PER_WORD);
2154 /* For the arm-wince targets we choose to be compatible with Microsoft's
2155 ARM and Thumb compilers, which always return aggregates in memory. */
2157 /* All structures/unions bigger than one word are returned in memory.
2158 Also catch the case where int_size_in_bytes returns -1. In this case
2159 the aggregate is either huge or of variable size, and in either case
2160 we will want to return it via memory and not in a register. */
2161 if (size < 0 || size > UNITS_PER_WORD)
2164 if (TREE_CODE (type) == RECORD_TYPE)
2168 /* For a struct the APCS says that we only return in a register
2169 if the type is 'integer like' and every addressable element
2170 has an offset of zero. For practical purposes this means
2171 that the structure can have at most one non bit-field element
2172 and that this element must be the first one in the structure. */
2174 /* Find the first field, ignoring non FIELD_DECL things which will
2175 have been created by C++. */
2176 for (field = TYPE_FIELDS (type);
2177 field && TREE_CODE (field) != FIELD_DECL;
2178 field = TREE_CHAIN (field))
2182 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2184 /* Check that the first field is valid for returning in a register. */
2186 /* ... Floats are not allowed */
2187 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2190 /* ... Aggregates that are not themselves valid for returning in
2191 a register are not allowed. */
2192 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2195 /* Now check the remaining fields, if any. Only bitfields are allowed,
2196 since they are not addressable. */
2197 for (field = TREE_CHAIN (field);
2199 field = TREE_CHAIN (field))
2201 if (TREE_CODE (field) != FIELD_DECL)
2204 if (!DECL_BIT_FIELD_TYPE (field))
2211 if (TREE_CODE (type) == UNION_TYPE)
2215 /* Unions can be returned in registers if every element is
2216 integral, or can be returned in an integer register. */
2217 for (field = TYPE_FIELDS (type);
2219 field = TREE_CHAIN (field))
2221 if (TREE_CODE (field) != FIELD_DECL)
2224 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2227 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2233 #endif /* not ARM_WINCE */
2235 /* Return all other types in memory. */
2239 /* Indicate whether or not words of a double are in big-endian order. */
2242 arm_float_words_big_endian (void)
2244 if (TARGET_MAVERICK)
2247 /* For FPA, float words are always big-endian. For VFP, floats words
2248 follow the memory system mode. */
2256 return (TARGET_BIG_END ? 1 : 0);
2261 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2262 for a call to a function whose data type is FNTYPE.
2263 For a library call, FNTYPE is NULL. */
2265 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2266 rtx libname ATTRIBUTE_UNUSED,
2267 tree fndecl ATTRIBUTE_UNUSED)
2269 /* On the ARM, the offset starts at 0. */
2270 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2271 pcum->iwmmxt_nregs = 0;
2272 pcum->can_split = true;
2274 pcum->call_cookie = CALL_NORMAL;
2276 if (TARGET_LONG_CALLS)
2277 pcum->call_cookie = CALL_LONG;
2279 /* Check for long call/short call attributes. The attributes
2280 override any command line option. */
2283 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2284 pcum->call_cookie = CALL_SHORT;
2285 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2286 pcum->call_cookie = CALL_LONG;
2289 /* Varargs vectors are treated the same as long long.
2290 named_count avoids having to change the way arm handles 'named' */
2291 pcum->named_count = 0;
2294 if (TARGET_REALLY_IWMMXT && fntype)
2298 for (fn_arg = TYPE_ARG_TYPES (fntype);
2300 fn_arg = TREE_CHAIN (fn_arg))
2301 pcum->named_count += 1;
2303 if (! pcum->named_count)
2304 pcum->named_count = INT_MAX;
2309 /* Return true if mode/type need doubleword alignment. */
2311 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2313 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2314 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2318 /* Determine where to put an argument to a function.
2319 Value is zero to push the argument on the stack,
2320 or a hard register in which to store the argument.
2322 MODE is the argument's machine mode.
2323 TYPE is the data type of the argument (as a tree).
2324 This is null for libcalls where that information may
2326 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2327 the preceding args and about the function being called.
2328 NAMED is nonzero if this argument is a named parameter
2329 (otherwise it is an extra parameter matching an ellipsis). */
2332 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2333 tree type, int named)
2337 /* Varargs vectors are treated the same as long long.
2338 named_count avoids having to change the way arm handles 'named' */
2339 if (TARGET_IWMMXT_ABI
2340 && VECTOR_MODE_SUPPORTED_P (mode)
2341 && pcum->named_count > pcum->nargs + 1)
2343 if (pcum->iwmmxt_nregs <= 9)
2344 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2347 pcum->can_split = false;
2352 /* Put doubleword aligned quantities in even register pairs. */
2354 && ARM_DOUBLEWORD_ALIGN
2355 && arm_needs_doubleword_align (mode, type))
2358 if (mode == VOIDmode)
2359 /* Compute operand 2 of the call insn. */
2360 return GEN_INT (pcum->call_cookie);
2362 /* Only allow splitting an arg between regs and memory if all preceding
2363 args were allocated to regs. For args passed by reference we only count
2364 the reference pointer. */
2365 if (pcum->can_split)
2368 nregs = ARM_NUM_REGS2 (mode, type);
2370 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2373 return gen_rtx_REG (mode, pcum->nregs);
2376 /* Variable sized types are passed by reference. This is a GCC
2377 extension to the ARM ABI. */
2380 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2381 enum machine_mode mode ATTRIBUTE_UNUSED,
2382 tree type, int named ATTRIBUTE_UNUSED)
2384 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2387 /* Implement va_arg. */
2390 arm_va_arg (tree valist, tree type)
2394 /* Variable sized types are passed by reference. */
2395 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2397 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2398 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2401 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2402 if (align > PARM_BOUNDARY)
2407 /* Maintain 64-bit alignment of the valist pointer by
2408 constructing: valist = ((valist + (8 - 1)) & -8). */
2409 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2410 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2411 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2412 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2413 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2414 TREE_SIDE_EFFECTS (t) = 1;
2415 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2417 /* This is to stop the combine pass optimizing
2418 away the alignment adjustment. */
2419 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2422 return std_expand_builtin_va_arg (valist, type);
2425 /* Encode the current state of the #pragma [no_]long_calls. */
2428 OFF, /* No #pramgma [no_]long_calls is in effect. */
2429 LONG, /* #pragma long_calls is in effect. */
2430 SHORT /* #pragma no_long_calls is in effect. */
2433 static arm_pragma_enum arm_pragma_long_calls = OFF;
2436 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2438 arm_pragma_long_calls = LONG;
2442 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2444 arm_pragma_long_calls = SHORT;
2448 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2450 arm_pragma_long_calls = OFF;
2453 /* Table of machine attributes. */
2454 const struct attribute_spec arm_attribute_table[] =
2456 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2457 /* Function calls made to this symbol must be done indirectly, because
2458 it may lie outside of the 26 bit addressing range of a normal function
2460 { "long_call", 0, 0, false, true, true, NULL },
2461 /* Whereas these functions are always known to reside within the 26 bit
2462 addressing range. */
2463 { "short_call", 0, 0, false, true, true, NULL },
2464 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2465 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2466 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2467 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2469 /* ARM/PE has three new attributes:
2471 dllexport - for exporting a function/variable that will live in a dll
2472 dllimport - for importing a function/variable from a dll
2474 Microsoft allows multiple declspecs in one __declspec, separating
2475 them with spaces. We do NOT support this. Instead, use __declspec
2478 { "dllimport", 0, 0, true, false, false, NULL },
2479 { "dllexport", 0, 0, true, false, false, NULL },
2480 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2482 { NULL, 0, 0, false, false, false, NULL }
2485 /* Handle an attribute requiring a FUNCTION_DECL;
2486 arguments as in struct attribute_spec.handler. */
2488 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2489 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2491 if (TREE_CODE (*node) != FUNCTION_DECL)
2493 warning ("`%s' attribute only applies to functions",
2494 IDENTIFIER_POINTER (name));
2495 *no_add_attrs = true;
2501 /* Handle an "interrupt" or "isr" attribute;
2502 arguments as in struct attribute_spec.handler. */
2504 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2509 if (TREE_CODE (*node) != FUNCTION_DECL)
2511 warning ("`%s' attribute only applies to functions",
2512 IDENTIFIER_POINTER (name));
2513 *no_add_attrs = true;
2515 /* FIXME: the argument if any is checked for type attributes;
2516 should it be checked for decl ones? */
2520 if (TREE_CODE (*node) == FUNCTION_TYPE
2521 || TREE_CODE (*node) == METHOD_TYPE)
2523 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2525 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2526 *no_add_attrs = true;
2529 else if (TREE_CODE (*node) == POINTER_TYPE
2530 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2531 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2532 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2534 *node = build_type_copy (*node);
2535 TREE_TYPE (*node) = build_type_attribute_variant
2537 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2538 *no_add_attrs = true;
2542 /* Possibly pass this attribute on from the type to a decl. */
2543 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2544 | (int) ATTR_FLAG_FUNCTION_NEXT
2545 | (int) ATTR_FLAG_ARRAY_NEXT))
2547 *no_add_attrs = true;
2548 return tree_cons (name, args, NULL_TREE);
2552 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2560 /* Return 0 if the attributes for two types are incompatible, 1 if they
2561 are compatible, and 2 if they are nearly compatible (which causes a
2562 warning to be generated). */
2564 arm_comp_type_attributes (tree type1, tree type2)
2568 /* Check for mismatch of non-default calling convention. */
2569 if (TREE_CODE (type1) != FUNCTION_TYPE)
2572 /* Check for mismatched call attributes. */
2573 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2574 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2575 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2576 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2578 /* Only bother to check if an attribute is defined. */
2579 if (l1 | l2 | s1 | s2)
2581 /* If one type has an attribute, the other must have the same attribute. */
2582 if ((l1 != l2) || (s1 != s2))
2585 /* Disallow mixed attributes. */
2586 if ((l1 & s2) || (l2 & s1))
2590 /* Check for mismatched ISR attribute. */
2591 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2593 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2594 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2596 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2603 /* Encode long_call or short_call attribute by prefixing
2604 symbol name in DECL with a special character FLAG. */
2606 arm_encode_call_attribute (tree decl, int flag)
2608 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2609 int len = strlen (str);
2612 /* Do not allow weak functions to be treated as short call. */
2613 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2616 newstr = alloca (len + 2);
2618 strcpy (newstr + 1, str);
2620 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2621 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2624 /* Assigns default attributes to newly defined type. This is used to
2625 set short_call/long_call attributes for function types of
2626 functions defined inside corresponding #pragma scopes. */
2628 arm_set_default_type_attributes (tree type)
2630 /* Add __attribute__ ((long_call)) to all functions, when
2631 inside #pragma long_calls or __attribute__ ((short_call)),
2632 when inside #pragma no_long_calls. */
2633 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2635 tree type_attr_list, attr_name;
2636 type_attr_list = TYPE_ATTRIBUTES (type);
2638 if (arm_pragma_long_calls == LONG)
2639 attr_name = get_identifier ("long_call");
2640 else if (arm_pragma_long_calls == SHORT)
2641 attr_name = get_identifier ("short_call");
2645 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2646 TYPE_ATTRIBUTES (type) = type_attr_list;
2650 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2651 defined within the current compilation unit. If this cannot be
2652 determined, then 0 is returned. */
2654 current_file_function_operand (rtx sym_ref)
2656 /* This is a bit of a fib. A function will have a short call flag
2657 applied to its name if it has the short call attribute, or it has
2658 already been defined within the current compilation unit. */
2659 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2662 /* The current function is always defined within the current compilation
2663 unit. if it s a weak definition however, then this may not be the real
2664 definition of the function, and so we have to say no. */
2665 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2666 && !DECL_WEAK (current_function_decl))
2669 /* We cannot make the determination - default to returning 0. */
2673 /* Return nonzero if a 32 bit "long_call" should be generated for
2674 this call. We generate a long_call if the function:
2676 a. has an __attribute__((long call))
2677 or b. is within the scope of a #pragma long_calls
2678 or c. the -mlong-calls command line switch has been specified
2680 However we do not generate a long call if the function:
2682 d. has an __attribute__ ((short_call))
2683 or e. is inside the scope of a #pragma no_long_calls
2684 or f. has an __attribute__ ((section))
2685 or g. is defined within the current compilation unit.
2687 This function will be called by C fragments contained in the machine
2688 description file. CALL_REF and CALL_COOKIE correspond to the matched
2689 rtl operands. CALL_SYMBOL is used to distinguish between
2690 two different callers of the function. It is set to 1 in the
2691 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2692 and "call_value" patterns. This is because of the difference in the
2693 SYM_REFs passed by these patterns. */
2695 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2699 if (GET_CODE (sym_ref) != MEM)
2702 sym_ref = XEXP (sym_ref, 0);
2705 if (GET_CODE (sym_ref) != SYMBOL_REF)
2708 if (call_cookie & CALL_SHORT)
2711 if (TARGET_LONG_CALLS && flag_function_sections)
2714 if (current_file_function_operand (sym_ref))
2717 return (call_cookie & CALL_LONG)
2718 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2719 || TARGET_LONG_CALLS;
2722 /* Return nonzero if it is ok to make a tail-call to DECL. */
2724 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2726 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2728 if (cfun->machine->sibcall_blocked)
2731 /* Never tailcall something for which we have no decl, or if we
2732 are in Thumb mode. */
2733 if (decl == NULL || TARGET_THUMB)
2736 /* Get the calling method. */
2737 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2738 call_type = CALL_SHORT;
2739 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2740 call_type = CALL_LONG;
2742 /* Cannot tail-call to long calls, since these are out of range of
2743 a branch instruction. However, if not compiling PIC, we know
2744 we can reach the symbol if it is in this compilation unit. */
2745 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2748 /* If we are interworking and the function is not declared static
2749 then we can't tail-call it unless we know that it exists in this
2750 compilation unit (since it might be a Thumb routine). */
2751 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2754 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2755 if (IS_INTERRUPT (arm_current_func_type ()))
2758 /* Everything else is ok. */
2763 /* Addressing mode support functions. */
2765 /* Return nonzero if X is a legitimate immediate operand when compiling
2768 legitimate_pic_operand_p (rtx x)
2772 && (GET_CODE (x) == SYMBOL_REF
2773 || (GET_CODE (x) == CONST
2774 && GET_CODE (XEXP (x, 0)) == PLUS
2775 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2782 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2784 if (GET_CODE (orig) == SYMBOL_REF
2785 || GET_CODE (orig) == LABEL_REF)
2787 #ifndef AOF_ASSEMBLER
2788 rtx pic_ref, address;
2798 reg = gen_reg_rtx (Pmode);
2803 #ifdef AOF_ASSEMBLER
2804 /* The AOF assembler can generate relocations for these directly, and
2805 understands that the PIC register has to be added into the offset. */
2806 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2809 address = gen_reg_rtx (Pmode);
2814 emit_insn (gen_pic_load_addr_arm (address, orig));
2816 emit_insn (gen_pic_load_addr_thumb (address, orig));
2818 if ((GET_CODE (orig) == LABEL_REF
2819 || (GET_CODE (orig) == SYMBOL_REF &&
2820 SYMBOL_REF_LOCAL_P (orig)))
2822 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2825 pic_ref = gen_rtx_MEM (Pmode,
2826 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2828 RTX_UNCHANGING_P (pic_ref) = 1;
2831 insn = emit_move_insn (reg, pic_ref);
2833 current_function_uses_pic_offset_table = 1;
2834 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2836 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2840 else if (GET_CODE (orig) == CONST)
2844 if (GET_CODE (XEXP (orig, 0)) == PLUS
2845 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2853 reg = gen_reg_rtx (Pmode);
2856 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2858 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2859 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2860 base == reg ? 0 : reg);
2865 if (GET_CODE (offset) == CONST_INT)
2867 /* The base register doesn't really matter, we only want to
2868 test the index for the appropriate mode. */
2869 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2871 if (!no_new_pseudos)
2872 offset = force_reg (Pmode, offset);
2877 if (GET_CODE (offset) == CONST_INT)
2878 return plus_constant (base, INTVAL (offset));
2881 if (GET_MODE_SIZE (mode) > 4
2882 && (GET_MODE_CLASS (mode) == MODE_INT
2883 || TARGET_SOFT_FLOAT))
2885 emit_insn (gen_addsi3 (reg, base, offset));
2889 return gen_rtx_PLUS (Pmode, base, offset);
2895 /* Generate code to load the PIC register. PROLOGUE is true if
2896 called from arm_expand_prologue (in which case we want the
2897 generated insns at the start of the function); false if called
2898 by an exception receiver that needs the PIC register reloaded
2899 (in which case the insns are just dumped at the current location). */
2901 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2903 #ifndef AOF_ASSEMBLER
2904 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2905 rtx global_offset_table;
2907 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2914 l1 = gen_label_rtx ();
2916 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2917 /* On the ARM the PC register contains 'dot + 8' at the time of the
2918 addition, on the Thumb it is 'dot + 4'. */
2919 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2921 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2922 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2924 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2926 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2930 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2931 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2935 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2936 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2942 emit_insn_after (seq, get_insns ());
2946 /* Need to emit this whether or not we obey regdecls,
2947 since setjmp/longjmp can cause life info to screw up. */
2948 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2949 #endif /* AOF_ASSEMBLER */
2952 /* Return nonzero if X is valid as an ARM state addressing register. */
2954 arm_address_register_rtx_p (rtx x, int strict_p)
2958 if (GET_CODE (x) != REG)
2964 return ARM_REGNO_OK_FOR_BASE_P (regno);
2966 return (regno <= LAST_ARM_REGNUM
2967 || regno >= FIRST_PSEUDO_REGISTER
2968 || regno == FRAME_POINTER_REGNUM
2969 || regno == ARG_POINTER_REGNUM);
2972 /* Return nonzero if X is a valid ARM state address operand. */
2974 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2978 enum rtx_code code = GET_CODE (x);
2980 if (arm_address_register_rtx_p (x, strict_p))
2983 use_ldrd = (TARGET_LDRD
2985 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
2987 if (code == POST_INC || code == PRE_DEC
2988 || ((code == PRE_INC || code == POST_DEC)
2989 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
2990 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2992 else if ((code == POST_MODIFY || code == PRE_MODIFY)
2993 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2994 && GET_CODE (XEXP (x, 1)) == PLUS
2995 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2997 rtx addend = XEXP (XEXP (x, 1), 1);
2999 /* Don't allow ldrd post increment by register becuase it's hard
3000 to fixup invalid register choices. */
3002 && GET_CODE (x) == POST_MODIFY
3003 && GET_CODE (addend) == REG)
3006 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3007 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3010 /* After reload constants split into minipools will have addresses
3011 from a LABEL_REF. */
3012 else if (reload_completed
3013 && (code == LABEL_REF
3015 && GET_CODE (XEXP (x, 0)) == PLUS
3016 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3017 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3020 else if (mode == TImode)
3023 else if (code == PLUS)
3025 rtx xop0 = XEXP (x, 0);
3026 rtx xop1 = XEXP (x, 1);
3028 return ((arm_address_register_rtx_p (xop0, strict_p)
3029 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3030 || (arm_address_register_rtx_p (xop1, strict_p)
3031 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3035 /* Reload currently can't handle MINUS, so disable this for now */
3036 else if (GET_CODE (x) == MINUS)
3038 rtx xop0 = XEXP (x, 0);
3039 rtx xop1 = XEXP (x, 1);
3041 return (arm_address_register_rtx_p (xop0, strict_p)
3042 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3046 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3047 && code == SYMBOL_REF
3048 && CONSTANT_POOL_ADDRESS_P (x)
3050 && symbol_mentioned_p (get_pool_constant (x))))
3056 /* Return nonzero if INDEX is valid for an address index operand in
3059 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3062 HOST_WIDE_INT range;
3063 enum rtx_code code = GET_CODE (index);
3065 /* Standard coprocessor addressing modes. */
3066 if (TARGET_HARD_FLOAT
3067 && (TARGET_FPA || TARGET_MAVERICK)
3068 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3069 || (TARGET_MAVERICK && mode == DImode)))
3070 return (code == CONST_INT && INTVAL (index) < 1024
3071 && INTVAL (index) > -1024
3072 && (INTVAL (index) & 3) == 0);
3074 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3075 return (code == CONST_INT
3076 && INTVAL (index) < 1024
3077 && INTVAL (index) > -1024
3078 && (INTVAL (index) & 3) == 0);
3080 if (arm_address_register_rtx_p (index, strict_p)
3081 && (GET_MODE_SIZE (mode) <= 4))
3084 if (mode == DImode || mode == DFmode)
3086 if (code == CONST_INT)
3088 HOST_WIDE_INT val = INTVAL (index);
3091 return val > -256 && val < 256;
3093 return val == 4 || val == -4 || val == -8;
3096 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3099 if (GET_MODE_SIZE (mode) <= 4
3102 || (mode == QImode && outer == SIGN_EXTEND))))
3106 rtx xiop0 = XEXP (index, 0);
3107 rtx xiop1 = XEXP (index, 1);
3109 return ((arm_address_register_rtx_p (xiop0, strict_p)
3110 && power_of_two_operand (xiop1, SImode))
3111 || (arm_address_register_rtx_p (xiop1, strict_p)
3112 && power_of_two_operand (xiop0, SImode)));
3114 else if (code == LSHIFTRT || code == ASHIFTRT
3115 || code == ASHIFT || code == ROTATERT)
3117 rtx op = XEXP (index, 1);
3119 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3120 && GET_CODE (op) == CONST_INT
3122 && INTVAL (op) <= 31);
3126 /* For ARM v4 we may be doing a sign-extend operation during the
3130 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3136 range = (mode == HImode) ? 4095 : 4096;
3138 return (code == CONST_INT
3139 && INTVAL (index) < range
3140 && INTVAL (index) > -range);
3143 /* Return nonzero if X is valid as a Thumb state base register. */
3145 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3149 if (GET_CODE (x) != REG)
3155 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3157 return (regno <= LAST_LO_REGNUM
3158 || regno > LAST_VIRTUAL_REGISTER
3159 || regno == FRAME_POINTER_REGNUM
3160 || (GET_MODE_SIZE (mode) >= 4
3161 && (regno == STACK_POINTER_REGNUM
3162 || regno >= FIRST_PSEUDO_REGISTER
3163 || x == hard_frame_pointer_rtx
3164 || x == arg_pointer_rtx)));
3167 /* Return nonzero if x is a legitimate index register. This is the case
3168 for any base register that can access a QImode object. */
3170 thumb_index_register_rtx_p (rtx x, int strict_p)
3172 return thumb_base_register_rtx_p (x, QImode, strict_p);
3175 /* Return nonzero if x is a legitimate Thumb-state address.
3177 The AP may be eliminated to either the SP or the FP, so we use the
3178 least common denominator, e.g. SImode, and offsets from 0 to 64.
3180 ??? Verify whether the above is the right approach.
3182 ??? Also, the FP may be eliminated to the SP, so perhaps that
3183 needs special handling also.
3185 ??? Look at how the mips16 port solves this problem. It probably uses
3186 better ways to solve some of these problems.
3188 Although it is not incorrect, we don't accept QImode and HImode
3189 addresses based on the frame pointer or arg pointer until the
3190 reload pass starts. This is so that eliminating such addresses
3191 into stack based ones won't produce impossible code. */
3193 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3195 /* ??? Not clear if this is right. Experiment. */
3196 if (GET_MODE_SIZE (mode) < 4
3197 && !(reload_in_progress || reload_completed)
3198 && (reg_mentioned_p (frame_pointer_rtx, x)
3199 || reg_mentioned_p (arg_pointer_rtx, x)
3200 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3201 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3202 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3203 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3206 /* Accept any base register. SP only in SImode or larger. */
3207 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3210 /* This is PC relative data before arm_reorg runs. */
3211 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3212 && GET_CODE (x) == SYMBOL_REF
3213 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3216 /* This is PC relative data after arm_reorg runs. */
3217 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3218 && (GET_CODE (x) == LABEL_REF
3219 || (GET_CODE (x) == CONST
3220 && GET_CODE (XEXP (x, 0)) == PLUS
3221 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3222 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3225 /* Post-inc indexing only supported for SImode and larger. */
3226 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3227 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3230 else if (GET_CODE (x) == PLUS)
3232 /* REG+REG address can be any two index registers. */
3233 /* We disallow FRAME+REG addressing since we know that FRAME
3234 will be replaced with STACK, and SP relative addressing only
3235 permits SP+OFFSET. */
3236 if (GET_MODE_SIZE (mode) <= 4
3237 && XEXP (x, 0) != frame_pointer_rtx
3238 && XEXP (x, 1) != frame_pointer_rtx
3239 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3240 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3243 /* REG+const has 5-7 bit offset for non-SP registers. */
3244 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3245 || XEXP (x, 0) == arg_pointer_rtx)
3246 && GET_CODE (XEXP (x, 1)) == CONST_INT
3247 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3250 /* REG+const has 10 bit offset for SP, but only SImode and
3251 larger is supported. */
3252 /* ??? Should probably check for DI/DFmode overflow here
3253 just like GO_IF_LEGITIMATE_OFFSET does. */
3254 else if (GET_CODE (XEXP (x, 0)) == REG
3255 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3256 && GET_MODE_SIZE (mode) >= 4
3257 && GET_CODE (XEXP (x, 1)) == CONST_INT
3258 && INTVAL (XEXP (x, 1)) >= 0
3259 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3260 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3263 else if (GET_CODE (XEXP (x, 0)) == REG
3264 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3265 && GET_MODE_SIZE (mode) >= 4
3266 && GET_CODE (XEXP (x, 1)) == CONST_INT
3267 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3271 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3272 && GET_MODE_SIZE (mode) == 4
3273 && GET_CODE (x) == SYMBOL_REF
3274 && CONSTANT_POOL_ADDRESS_P (x)
3276 && symbol_mentioned_p (get_pool_constant (x))))
3282 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3283 instruction of mode MODE. */
3285 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3287 switch (GET_MODE_SIZE (mode))
3290 return val >= 0 && val < 32;
3293 return val >= 0 && val < 64 && (val & 1) == 0;
3297 && (val + GET_MODE_SIZE (mode)) <= 128
3302 /* Try machine-dependent ways of modifying an illegitimate address
3303 to be legitimate. If we find one, return the new, valid address. */
3305 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3307 if (GET_CODE (x) == PLUS)
3309 rtx xop0 = XEXP (x, 0);
3310 rtx xop1 = XEXP (x, 1);
3312 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3313 xop0 = force_reg (SImode, xop0);
3315 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3316 xop1 = force_reg (SImode, xop1);
3318 if (ARM_BASE_REGISTER_RTX_P (xop0)
3319 && GET_CODE (xop1) == CONST_INT)
3321 HOST_WIDE_INT n, low_n;
3325 /* VFP addressing modes actually allow greater offsets, but for
3326 now we just stick with the lowest common denominator. */
3328 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3340 low_n = ((mode) == TImode ? 0
3341 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3345 base_reg = gen_reg_rtx (SImode);
3346 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3347 GEN_INT (n)), NULL_RTX);
3348 emit_move_insn (base_reg, val);
3349 x = (low_n == 0 ? base_reg
3350 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3352 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3353 x = gen_rtx_PLUS (SImode, xop0, xop1);
3356 /* XXX We don't allow MINUS any more -- see comment in
3357 arm_legitimate_address_p (). */
3358 else if (GET_CODE (x) == MINUS)
3360 rtx xop0 = XEXP (x, 0);
3361 rtx xop1 = XEXP (x, 1);
3363 if (CONSTANT_P (xop0))
3364 xop0 = force_reg (SImode, xop0);
3366 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3367 xop1 = force_reg (SImode, xop1);
3369 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3370 x = gen_rtx_MINUS (SImode, xop0, xop1);
3375 /* We need to find and carefully transform any SYMBOL and LABEL
3376 references; so go back to the original address expression. */
3377 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3379 if (new_x != orig_x)
3387 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3388 to be legitimate. If we find one, return the new, valid address. */
3390 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3392 if (GET_CODE (x) == PLUS
3393 && GET_CODE (XEXP (x, 1)) == CONST_INT
3394 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3395 || INTVAL (XEXP (x, 1)) < 0))
3397 rtx xop0 = XEXP (x, 0);
3398 rtx xop1 = XEXP (x, 1);
3399 HOST_WIDE_INT offset = INTVAL (xop1);
3401 /* Try and fold the offset into a biasing of the base register and
3402 then offsetting that. Don't do this when optimizing for space
3403 since it can cause too many CSEs. */
3404 if (optimize_size && offset >= 0
3405 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3407 HOST_WIDE_INT delta;
3410 delta = offset - (256 - GET_MODE_SIZE (mode));
3411 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3412 delta = 31 * GET_MODE_SIZE (mode);
3414 delta = offset & (~31 * GET_MODE_SIZE (mode));
3416 xop0 = force_operand (plus_constant (xop0, offset - delta),
3418 x = plus_constant (xop0, delta);
3420 else if (offset < 0 && offset > -256)
3421 /* Small negative offsets are best done with a subtract before the
3422 dereference, forcing these into a register normally takes two
3424 x = force_operand (x, NULL_RTX);
3427 /* For the remaining cases, force the constant into a register. */
3428 xop1 = force_reg (SImode, xop1);
3429 x = gen_rtx_PLUS (SImode, xop0, xop1);
3432 else if (GET_CODE (x) == PLUS
3433 && s_register_operand (XEXP (x, 1), SImode)
3434 && !s_register_operand (XEXP (x, 0), SImode))
3436 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3438 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3443 /* We need to find and carefully transform any SYMBOL and LABEL
3444 references; so go back to the original address expression. */
3445 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3447 if (new_x != orig_x)
3456 #define REG_OR_SUBREG_REG(X) \
3457 (GET_CODE (X) == REG \
3458 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3460 #define REG_OR_SUBREG_RTX(X) \
3461 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3463 #ifndef COSTS_N_INSNS
3464 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3467 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3469 enum machine_mode mode = GET_MODE (x);
3482 return COSTS_N_INSNS (1);
3485 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3488 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3495 return COSTS_N_INSNS (2) + cycles;
3497 return COSTS_N_INSNS (1) + 16;
3500 return (COSTS_N_INSNS (1)
3501 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3502 + GET_CODE (SET_DEST (x)) == MEM));
3507 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3509 if (thumb_shiftable_const (INTVAL (x)))
3510 return COSTS_N_INSNS (2);
3511 return COSTS_N_INSNS (3);
3513 else if ((outer == PLUS || outer == COMPARE)
3514 && INTVAL (x) < 256 && INTVAL (x) > -256)
3516 else if (outer == AND
3517 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3518 return COSTS_N_INSNS (1);
3519 else if (outer == ASHIFT || outer == ASHIFTRT
3520 || outer == LSHIFTRT)
3522 return COSTS_N_INSNS (2);
3528 return COSTS_N_INSNS (3);
3547 /* XXX another guess. */
3548 /* Memory costs quite a lot for the first word, but subsequent words
3549 load at the equivalent of a single insn each. */
3550 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3551 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3556 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3561 /* XXX still guessing. */
3562 switch (GET_MODE (XEXP (x, 0)))
3565 return (1 + (mode == DImode ? 4 : 0)
3566 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3569 return (4 + (mode == DImode ? 4 : 0)
3570 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3573 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3585 /* Worker routine for arm_rtx_costs. */
3587 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3589 enum machine_mode mode = GET_MODE (x);
3590 enum rtx_code subcode;
3596 /* Memory costs quite a lot for the first word, but subsequent words
3597 load at the equivalent of a single insn each. */
3598 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3599 + (GET_CODE (x) == SYMBOL_REF
3600 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3606 return optimize_size ? COSTS_N_INSNS (2) : 100;
3609 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3616 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3618 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3619 + ((GET_CODE (XEXP (x, 0)) == REG
3620 || (GET_CODE (XEXP (x, 0)) == SUBREG
3621 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3623 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3624 || (GET_CODE (XEXP (x, 0)) == SUBREG
3625 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3627 + ((GET_CODE (XEXP (x, 1)) == REG
3628 || (GET_CODE (XEXP (x, 1)) == SUBREG
3629 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3630 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3635 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3636 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3637 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3638 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3641 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3642 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3643 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3644 && arm_const_double_rtx (XEXP (x, 1))))
3646 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3647 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3648 && arm_const_double_rtx (XEXP (x, 0))))
3651 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3652 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3653 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3654 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3655 || subcode == ASHIFTRT || subcode == LSHIFTRT
3656 || subcode == ROTATE || subcode == ROTATERT
3658 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3659 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3660 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3661 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3662 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3663 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3664 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3669 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3670 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3671 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3672 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3673 && arm_const_double_rtx (XEXP (x, 1))))
3677 case AND: case XOR: case IOR:
3680 /* Normally the frame registers will be spilt into reg+const during
3681 reload, so it is a bad idea to combine them with other instructions,
3682 since then they might not be moved outside of loops. As a compromise
3683 we allow integration with ops that have a constant as their second
3685 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3686 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3687 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3688 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3689 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3693 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3694 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3695 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3696 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3699 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3700 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3701 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3702 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3703 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3706 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3707 return (1 + extra_cost
3708 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3709 || subcode == LSHIFTRT || subcode == ASHIFTRT
3710 || subcode == ROTATE || subcode == ROTATERT
3712 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3713 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3714 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3715 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3716 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3717 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3723 /* This should have been handled by the CPU specific routines. */
3727 if (arm_arch3m && mode == SImode
3728 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3729 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3730 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3731 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3732 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3733 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3738 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3739 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3743 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3745 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3748 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3756 return 4 + (mode == DImode ? 4 : 0);
3759 if (GET_MODE (XEXP (x, 0)) == QImode)
3760 return (4 + (mode == DImode ? 4 : 0)
3761 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3764 switch (GET_MODE (XEXP (x, 0)))
3767 return (1 + (mode == DImode ? 4 : 0)
3768 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3771 return (4 + (mode == DImode ? 4 : 0)
3772 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3775 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3790 if (const_ok_for_arm (INTVAL (x)))
3791 return outer == SET ? 2 : -1;
3792 else if (outer == AND
3793 && const_ok_for_arm (~INTVAL (x)))
3795 else if ((outer == COMPARE
3796 || outer == PLUS || outer == MINUS)
3797 && const_ok_for_arm (-INTVAL (x)))
3808 if (arm_const_double_rtx (x))
3809 return outer == SET ? 2 : -1;
3810 else if ((outer == COMPARE || outer == PLUS)
3811 && neg_const_double_rtx_ok_for_fpa (x))
3820 /* RTX costs for cores with a slow MUL implementation. */
3823 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3825 enum machine_mode mode = GET_MODE (x);
3829 *total = thumb_rtx_costs (x, code, outer_code);
3836 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3843 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3845 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3846 & (unsigned HOST_WIDE_INT) 0xffffffff);
3847 int cost, const_ok = const_ok_for_arm (i);
3848 int j, booth_unit_size;
3850 /* Tune as appropriate. */
3851 cost = const_ok ? 4 : 8;
3852 booth_unit_size = 2;
3853 for (j = 0; i && j < 32; j += booth_unit_size)
3855 i >>= booth_unit_size;
3863 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3864 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3868 *total = arm_rtx_costs_1 (x, code, outer_code);
3874 /* RTX cost for cores with a fast multiply unit (M variants). */
3877 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3879 enum machine_mode mode = GET_MODE (x);
3883 *total = thumb_rtx_costs (x, code, outer_code);
3890 /* There is no point basing this on the tuning, since it is always the
3891 fast variant if it exists at all. */
3893 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3894 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3895 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3902 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3909 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3911 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3912 & (unsigned HOST_WIDE_INT) 0xffffffff);
3913 int cost, const_ok = const_ok_for_arm (i);
3914 int j, booth_unit_size;
3916 /* Tune as appropriate. */
3917 cost = const_ok ? 4 : 8;
3918 booth_unit_size = 8;
3919 for (j = 0; i && j < 32; j += booth_unit_size)
3921 i >>= booth_unit_size;
3929 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3930 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3934 *total = arm_rtx_costs_1 (x, code, outer_code);
3940 /* RTX cost for XScale CPUs. */
3943 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3945 enum machine_mode mode = GET_MODE (x);
3949 *total = thumb_rtx_costs (x, code, outer_code);
3956 /* There is no point basing this on the tuning, since it is always the
3957 fast variant if it exists at all. */
3959 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3960 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3961 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3968 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3975 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3977 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3978 & (unsigned HOST_WIDE_INT) 0xffffffff);
3979 int cost, const_ok = const_ok_for_arm (i);
3980 unsigned HOST_WIDE_INT masked_const;
3982 /* The cost will be related to two insns.
3983 First a load of the constant (MOV or LDR), then a multiply. */
3986 cost += 1; /* LDR is probably more expensive because
3987 of longer result latency. */
3988 masked_const = i & 0xffff8000;
3989 if (masked_const != 0 && masked_const != 0xffff8000)
3991 masked_const = i & 0xf8000000;
3992 if (masked_const == 0 || masked_const == 0xf8000000)
4001 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4002 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4006 *total = arm_rtx_costs_1 (x, code, outer_code);
4012 /* RTX costs for 9e (and later) cores. */
4015 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4017 enum machine_mode mode = GET_MODE (x);
4026 *total = COSTS_N_INSNS (3);
4030 *total = thumb_rtx_costs (x, code, outer_code);
4038 /* There is no point basing this on the tuning, since it is always the
4039 fast variant if it exists at all. */
4041 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4042 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4043 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4050 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4067 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4068 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4072 *total = arm_rtx_costs_1 (x, code, outer_code);
4076 /* All address computations that can be done are free, but rtx cost returns
4077 the same for practically all of them. So we weight the different types
4078 of address here in the order (most pref first):
4079 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4081 arm_arm_address_cost (rtx x)
4083 enum rtx_code c = GET_CODE (x);
4085 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4087 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4090 if (c == PLUS || c == MINUS)
4092 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4095 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4105 arm_thumb_address_cost (rtx x)
4107 enum rtx_code c = GET_CODE (x);
4112 && GET_CODE (XEXP (x, 0)) == REG
4113 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4120 arm_address_cost (rtx x)
4122 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4126 arm_use_dfa_pipeline_interface (void)
4132 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4136 /* Some true dependencies can have a higher cost depending
4137 on precisely how certain input operands are used. */
4139 && REG_NOTE_KIND (link) == 0
4140 && recog_memoized (insn) >= 0
4141 && recog_memoized (dep) >= 0)
4143 int shift_opnum = get_attr_shift (insn);
4144 enum attr_type attr_type = get_attr_type (dep);
4146 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4147 operand for INSN. If we have a shifted input operand and the
4148 instruction we depend on is another ALU instruction, then we may
4149 have to account for an additional stall. */
4150 if (shift_opnum != 0
4151 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4153 rtx shifted_operand;
4156 /* Get the shifted operand. */
4157 extract_insn (insn);
4158 shifted_operand = recog_data.operand[shift_opnum];
4160 /* Iterate over all the operands in DEP. If we write an operand
4161 that overlaps with SHIFTED_OPERAND, then we have increase the
4162 cost of this dependency. */
4164 preprocess_constraints ();
4165 for (opno = 0; opno < recog_data.n_operands; opno++)
4167 /* We can ignore strict inputs. */
4168 if (recog_data.operand_type[opno] == OP_IN)
4171 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4178 /* XXX This is not strictly true for the FPA. */
4179 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4180 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4183 /* Call insns don't incur a stall, even if they follow a load. */
4184 if (REG_NOTE_KIND (link) == 0
4185 && GET_CODE (insn) == CALL_INSN)
4188 if ((i_pat = single_set (insn)) != NULL
4189 && GET_CODE (SET_SRC (i_pat)) == MEM
4190 && (d_pat = single_set (dep)) != NULL
4191 && GET_CODE (SET_DEST (d_pat)) == MEM)
4193 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4194 /* This is a load after a store, there is no conflict if the load reads
4195 from a cached area. Assume that loads from the stack, and from the
4196 constant pool are cached, and that others will miss. This is a
4199 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4200 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4201 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4202 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4209 static int fp_consts_inited = 0;
4211 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4212 static const char * const strings_fp[8] =
4215 "4", "5", "0.5", "10"
4218 static REAL_VALUE_TYPE values_fp[8];
4221 init_fp_table (void)
4227 fp_consts_inited = 1;
4229 fp_consts_inited = 8;
4231 for (i = 0; i < fp_consts_inited; i++)
4233 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4238 /* Return TRUE if rtx X is a valid immediate FP constant. */
4240 arm_const_double_rtx (rtx x)
4245 if (!fp_consts_inited)
4248 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4249 if (REAL_VALUE_MINUS_ZERO (r))
4252 for (i = 0; i < fp_consts_inited; i++)
4253 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4259 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4261 neg_const_double_rtx_ok_for_fpa (rtx x)
4266 if (!fp_consts_inited)
4269 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4270 r = REAL_VALUE_NEGATE (r);
4271 if (REAL_VALUE_MINUS_ZERO (r))
4274 for (i = 0; i < 8; i++)
4275 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4281 /* Predicates for `match_operand' and `match_operator'. */
4283 /* s_register_operand is the same as register_operand, but it doesn't accept
4286 This function exists because at the time it was put in it led to better
4287 code. SUBREG(MEM) always needs a reload in the places where
4288 s_register_operand is used, and this seemed to lead to excessive
4291 s_register_operand (rtx op, enum machine_mode mode)
4293 if (GET_MODE (op) != mode && mode != VOIDmode)
4296 if (GET_CODE (op) == SUBREG)
4297 op = SUBREG_REG (op);
4299 /* We don't consider registers whose class is NO_REGS
4300 to be a register operand. */
4301 /* XXX might have to check for lo regs only for thumb ??? */
4302 return (GET_CODE (op) == REG
4303 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4304 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4307 /* A hard register operand (even before reload. */
4309 arm_hard_register_operand (rtx op, enum machine_mode mode)
4311 if (GET_MODE (op) != mode && mode != VOIDmode)
4314 return (GET_CODE (op) == REG
4315 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4318 /* An arm register operand. */
4320 arm_general_register_operand (rtx op, enum machine_mode mode)
4322 if (GET_MODE (op) != mode && mode != VOIDmode)
4325 if (GET_CODE (op) == SUBREG)
4326 op = SUBREG_REG (op);
4328 return (GET_CODE (op) == REG
4329 && (REGNO (op) <= LAST_ARM_REGNUM
4330 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4333 /* Only accept reg, subreg(reg), const_int. */
4335 reg_or_int_operand (rtx op, enum machine_mode mode)
4337 if (GET_CODE (op) == CONST_INT)
4340 if (GET_MODE (op) != mode && mode != VOIDmode)
4343 if (GET_CODE (op) == SUBREG)
4344 op = SUBREG_REG (op);
4346 /* We don't consider registers whose class is NO_REGS
4347 to be a register operand. */
4348 return (GET_CODE (op) == REG
4349 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4350 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4353 /* Return 1 if OP is an item in memory, given that we are in reload. */
4355 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4357 int regno = true_regnum (op);
4359 return (!CONSTANT_P (op)
4361 || (GET_CODE (op) == REG
4362 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4365 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4367 arm_rhs_operand (rtx op, enum machine_mode mode)
4369 return (s_register_operand (op, mode)
4370 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4373 /* Return TRUE for valid operands for the
4374 rhs of an ARM instruction, or a load. */
4376 arm_rhsm_operand (rtx op, enum machine_mode mode)
4378 return (s_register_operand (op, mode)
4379 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4380 || memory_operand (op, mode));
4383 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4384 constant that is valid when negated. */
4386 arm_add_operand (rtx op, enum machine_mode mode)
4389 return thumb_cmp_operand (op, mode);
4391 return (s_register_operand (op, mode)
4392 || (GET_CODE (op) == CONST_INT
4393 && (const_ok_for_arm (INTVAL (op))
4394 || const_ok_for_arm (-INTVAL (op)))));
4397 /* Return TRUE for valid ARM constants (or when valid if negated). */
4399 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4401 return (GET_CODE (op) == CONST_INT
4402 && (const_ok_for_arm (INTVAL (op))
4403 || const_ok_for_arm (-INTVAL (op))));
4407 arm_not_operand (rtx op, enum machine_mode mode)
4409 return (s_register_operand (op, mode)
4410 || (GET_CODE (op) == CONST_INT
4411 && (const_ok_for_arm (INTVAL (op))
4412 || const_ok_for_arm (~INTVAL (op)))));
4415 /* Return TRUE if the operand is a memory reference which contains an
4416 offsettable address. */
4418 offsettable_memory_operand (rtx op, enum machine_mode mode)
4420 if (mode == VOIDmode)
4421 mode = GET_MODE (op);
4423 return (mode == GET_MODE (op)
4424 && GET_CODE (op) == MEM
4425 && offsettable_address_p (reload_completed | reload_in_progress,
4426 mode, XEXP (op, 0)));
4429 /* Return TRUE if the operand is a memory reference which is, or can be
4430 made word aligned by adjusting the offset. */
4432 alignable_memory_operand (rtx op, enum machine_mode mode)
4436 if (mode == VOIDmode)
4437 mode = GET_MODE (op);
4439 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4444 return ((GET_CODE (reg = op) == REG
4445 || (GET_CODE (op) == SUBREG
4446 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4447 || (GET_CODE (op) == PLUS
4448 && GET_CODE (XEXP (op, 1)) == CONST_INT
4449 && (GET_CODE (reg = XEXP (op, 0)) == REG
4450 || (GET_CODE (XEXP (op, 0)) == SUBREG
4451 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4452 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4455 /* Similar to s_register_operand, but does not allow hard integer
4458 f_register_operand (rtx op, enum machine_mode mode)
4460 if (GET_MODE (op) != mode && mode != VOIDmode)
4463 if (GET_CODE (op) == SUBREG)
4464 op = SUBREG_REG (op);
4466 /* We don't consider registers whose class is NO_REGS
4467 to be a register operand. */
4468 return (GET_CODE (op) == REG
4469 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4470 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4473 /* Return TRUE for valid operands for the rhs of an floating point insns.
4474 Allows regs or certain consts on FPA, just regs for everything else. */
4476 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4478 if (s_register_operand (op, mode))
4481 if (GET_MODE (op) != mode && mode != VOIDmode)
4484 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4485 return arm_const_double_rtx (op);
4491 arm_float_add_operand (rtx op, enum machine_mode mode)
4493 if (s_register_operand (op, mode))
4496 if (GET_MODE (op) != mode && mode != VOIDmode)
4499 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4500 return (arm_const_double_rtx (op)
4501 || neg_const_double_rtx_ok_for_fpa (op));
4507 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4508 Depends which fpu we are targeting. */
4511 arm_float_compare_operand (rtx op, enum machine_mode mode)
4514 return vfp_compare_operand (op, mode);
4516 return arm_float_rhs_operand (op, mode);
4520 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4522 cirrus_memory_offset (rtx op)
4524 /* Reject eliminable registers. */
4525 if (! (reload_in_progress || reload_completed)
4526 && ( reg_mentioned_p (frame_pointer_rtx, op)
4527 || reg_mentioned_p (arg_pointer_rtx, op)
4528 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4529 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4530 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4531 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4534 if (GET_CODE (op) == MEM)
4540 /* Match: (mem (reg)). */
4541 if (GET_CODE (ind) == REG)
4547 if (GET_CODE (ind) == PLUS
4548 && GET_CODE (XEXP (ind, 0)) == REG
4549 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4550 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4558 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4560 if (!memory_operand (op, mode))
4563 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4566 /* Return nonzero if OP is a Cirrus or general register. */
4568 cirrus_register_operand (rtx op, enum machine_mode mode)
4570 if (GET_MODE (op) != mode && mode != VOIDmode)
4573 if (GET_CODE (op) == SUBREG)
4574 op = SUBREG_REG (op);
4576 return (GET_CODE (op) == REG
4577 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4578 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4581 /* Return nonzero if OP is a cirrus FP register. */
4583 cirrus_fp_register (rtx op, enum machine_mode mode)
4585 if (GET_MODE (op) != mode && mode != VOIDmode)
4588 if (GET_CODE (op) == SUBREG)
4589 op = SUBREG_REG (op);
4591 return (GET_CODE (op) == REG
4592 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4593 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4596 /* Return nonzero if OP is a 6bit constant (0..63). */
4598 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4600 return (GET_CODE (op) == CONST_INT
4602 && INTVAL (op) < 64);
4606 /* Return TRUE if OP is a valid VFP memory address pattern.
4607 WB if true if writeback address modes are allowed. */
4610 arm_coproc_mem_operand (rtx op, bool wb)
4614 /* Reject eliminable registers. */
4615 if (! (reload_in_progress || reload_completed)
4616 && ( reg_mentioned_p (frame_pointer_rtx, op)
4617 || reg_mentioned_p (arg_pointer_rtx, op)
4618 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4619 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4620 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4621 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4624 /* Constants are converted into offsets from labels. */
4625 if (GET_CODE (op) != MEM)
4630 if (reload_completed
4631 && (GET_CODE (ind) == LABEL_REF
4632 || (GET_CODE (ind) == CONST
4633 && GET_CODE (XEXP (ind, 0)) == PLUS
4634 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4635 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4638 /* Match: (mem (reg)). */
4639 if (GET_CODE (ind) == REG)
4640 return arm_address_register_rtx_p (ind, 0);
4642 /* Autoincremment addressing modes. */
4644 && (GET_CODE (ind) == PRE_INC
4645 || GET_CODE (ind) == POST_INC
4646 || GET_CODE (ind) == PRE_DEC
4647 || GET_CODE (ind) == POST_DEC))
4648 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4651 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4652 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4653 && GET_CODE (XEXP (ind, 1)) == PLUS
4654 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4655 ind = XEXP (ind, 1);
4660 if (GET_CODE (ind) == PLUS
4661 && GET_CODE (XEXP (ind, 0)) == REG
4662 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4663 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4664 && INTVAL (XEXP (ind, 1)) > -1024
4665 && INTVAL (XEXP (ind, 1)) < 1024
4666 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4673 /* Return TRUE if OP is a REG or constant zero. */
4675 vfp_compare_operand (rtx op, enum machine_mode mode)
4677 if (s_register_operand (op, mode))
4680 return (GET_CODE (op) == CONST_DOUBLE
4681 && arm_const_double_rtx (op));
4685 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4686 VFP registers. Otherwise return NO_REGS. */
4689 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4691 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4694 return GENERAL_REGS;
4698 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4699 Use by the Cirrus Maverick code which has to workaround
4700 a hardware bug triggered by such instructions. */
4702 arm_memory_load_p (rtx insn)
4704 rtx body, lhs, rhs;;
4706 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4709 body = PATTERN (insn);
4711 if (GET_CODE (body) != SET)
4714 lhs = XEXP (body, 0);
4715 rhs = XEXP (body, 1);
4717 lhs = REG_OR_SUBREG_RTX (lhs);
4719 /* If the destination is not a general purpose
4720 register we do not have to worry. */
4721 if (GET_CODE (lhs) != REG
4722 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4725 /* As well as loads from memory we also have to react
4726 to loads of invalid constants which will be turned
4727 into loads from the minipool. */
4728 return (GET_CODE (rhs) == MEM
4729 || GET_CODE (rhs) == SYMBOL_REF
4730 || note_invalid_constants (insn, -1, false));
4733 /* Return TRUE if INSN is a Cirrus instruction. */
4735 arm_cirrus_insn_p (rtx insn)
4737 enum attr_cirrus attr;
4739 /* get_attr aborts on USE and CLOBBER. */
4741 || GET_CODE (insn) != INSN
4742 || GET_CODE (PATTERN (insn)) == USE
4743 || GET_CODE (PATTERN (insn)) == CLOBBER)
4746 attr = get_attr_cirrus (insn);
4748 return attr != CIRRUS_NOT;
4751 /* Cirrus reorg for invalid instruction combinations. */
4753 cirrus_reorg (rtx first)
4755 enum attr_cirrus attr;
4756 rtx body = PATTERN (first);
4760 /* Any branch must be followed by 2 non Cirrus instructions. */
4761 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4764 t = next_nonnote_insn (first);
4766 if (arm_cirrus_insn_p (t))
4769 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4773 emit_insn_after (gen_nop (), first);
4778 /* (float (blah)) is in parallel with a clobber. */
4779 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4780 body = XVECEXP (body, 0, 0);
4782 if (GET_CODE (body) == SET)
4784 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4786 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4787 be followed by a non Cirrus insn. */
4788 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4790 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4791 emit_insn_after (gen_nop (), first);
4795 else if (arm_memory_load_p (first))
4797 unsigned int arm_regno;
4799 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4800 ldr/cfmv64hr combination where the Rd field is the same
4801 in both instructions must be split with a non Cirrus
4808 /* Get Arm register number for ldr insn. */
4809 if (GET_CODE (lhs) == REG)
4810 arm_regno = REGNO (lhs);
4811 else if (GET_CODE (rhs) == REG)
4812 arm_regno = REGNO (rhs);
4817 first = next_nonnote_insn (first);
4819 if (! arm_cirrus_insn_p (first))
4822 body = PATTERN (first);
4824 /* (float (blah)) is in parallel with a clobber. */
4825 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4826 body = XVECEXP (body, 0, 0);
4828 if (GET_CODE (body) == FLOAT)
4829 body = XEXP (body, 0);
4831 if (get_attr_cirrus (first) == CIRRUS_MOVE
4832 && GET_CODE (XEXP (body, 1)) == REG
4833 && arm_regno == REGNO (XEXP (body, 1)))
4834 emit_insn_after (gen_nop (), first);
4840 /* get_attr aborts on USE and CLOBBER. */
4842 || GET_CODE (first) != INSN
4843 || GET_CODE (PATTERN (first)) == USE
4844 || GET_CODE (PATTERN (first)) == CLOBBER)
4847 attr = get_attr_cirrus (first);
4849 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4850 must be followed by a non-coprocessor instruction. */
4851 if (attr == CIRRUS_COMPARE)
4855 t = next_nonnote_insn (first);
4857 if (arm_cirrus_insn_p (t))
4860 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4864 emit_insn_after (gen_nop (), first);
4870 /* Return nonzero if OP is a constant power of two. */
4872 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4874 if (GET_CODE (op) == CONST_INT)
4876 HOST_WIDE_INT value = INTVAL (op);
4878 return value != 0 && (value & (value - 1)) == 0;
4884 /* Return TRUE for a valid operand of a DImode operation.
4885 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4886 Note that this disallows MEM(REG+REG), but allows
4887 MEM(PRE/POST_INC/DEC(REG)). */
4889 di_operand (rtx op, enum machine_mode mode)
4891 if (s_register_operand (op, mode))
4894 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4897 if (GET_CODE (op) == SUBREG)
4898 op = SUBREG_REG (op);
4900 switch (GET_CODE (op))
4907 return memory_address_p (DImode, XEXP (op, 0));
4914 /* Like di_operand, but don't accept constants. */
4916 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4918 if (s_register_operand (op, mode))
4921 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4924 if (GET_CODE (op) == SUBREG)
4925 op = SUBREG_REG (op);
4927 if (GET_CODE (op) == MEM)
4928 return memory_address_p (DImode, XEXP (op, 0));
4933 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4934 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4935 Note that this disallows MEM(REG+REG), but allows
4936 MEM(PRE/POST_INC/DEC(REG)). */
4938 soft_df_operand (rtx op, enum machine_mode mode)
4940 if (s_register_operand (op, mode))
4943 if (mode != VOIDmode && GET_MODE (op) != mode)
4946 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4949 if (GET_CODE (op) == SUBREG)
4950 op = SUBREG_REG (op);
4952 switch (GET_CODE (op))
4958 return memory_address_p (DFmode, XEXP (op, 0));
4965 /* Like soft_df_operand, but don't accept constants. */
4967 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4969 if (s_register_operand (op, mode))
4972 if (mode != VOIDmode && GET_MODE (op) != mode)
4975 if (GET_CODE (op) == SUBREG)
4976 op = SUBREG_REG (op);
4978 if (GET_CODE (op) == MEM)
4979 return memory_address_p (DFmode, XEXP (op, 0));
4983 /* Return TRUE for valid index operands. */
4985 index_operand (rtx op, enum machine_mode mode)
4987 return (s_register_operand (op, mode)
4988 || (immediate_operand (op, mode)
4989 && (GET_CODE (op) != CONST_INT
4990 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4993 /* Return TRUE for valid shifts by a constant. This also accepts any
4994 power of two on the (somewhat overly relaxed) assumption that the
4995 shift operator in this case was a mult. */
4997 const_shift_operand (rtx op, enum machine_mode mode)
4999 return (power_of_two_operand (op, mode)
5000 || (immediate_operand (op, mode)
5001 && (GET_CODE (op) != CONST_INT
5002 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5005 /* Return TRUE for arithmetic operators which can be combined with a multiply
5008 shiftable_operator (rtx x, enum machine_mode mode)
5012 if (GET_MODE (x) != mode)
5015 code = GET_CODE (x);
5017 return (code == PLUS || code == MINUS
5018 || code == IOR || code == XOR || code == AND);
5021 /* Return TRUE for binary logical operators. */
5023 logical_binary_operator (rtx x, enum machine_mode mode)
5027 if (GET_MODE (x) != mode)
5030 code = GET_CODE (x);
5032 return (code == IOR || code == XOR || code == AND);
5035 /* Return TRUE for shift operators. */
5037 shift_operator (rtx x,enum machine_mode mode)
5041 if (GET_MODE (x) != mode)
5044 code = GET_CODE (x);
5047 return power_of_two_operand (XEXP (x, 1), mode);
5049 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5050 || code == ROTATERT);
5053 /* Return TRUE if x is EQ or NE. */
5055 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5057 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5060 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5062 arm_comparison_operator (rtx x, enum machine_mode mode)
5064 return (comparison_operator (x, mode)
5065 && GET_CODE (x) != LTGT
5066 && GET_CODE (x) != UNEQ);
5069 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5071 minmax_operator (rtx x, enum machine_mode mode)
5073 enum rtx_code code = GET_CODE (x);
5075 if (GET_MODE (x) != mode)
5078 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5081 /* Return TRUE if this is the condition code register, if we aren't given
5082 a mode, accept any class CCmode register. */
5084 cc_register (rtx x, enum machine_mode mode)
5086 if (mode == VOIDmode)
5088 mode = GET_MODE (x);
5090 if (GET_MODE_CLASS (mode) != MODE_CC)
5094 if ( GET_MODE (x) == mode
5095 && GET_CODE (x) == REG
5096 && REGNO (x) == CC_REGNUM)
5102 /* Return TRUE if this is the condition code register, if we aren't given
5103 a mode, accept any class CCmode register which indicates a dominance
5106 dominant_cc_register (rtx x, enum machine_mode mode)
5108 if (mode == VOIDmode)
5110 mode = GET_MODE (x);
5112 if (GET_MODE_CLASS (mode) != MODE_CC)
5116 if (mode != CC_DNEmode && mode != CC_DEQmode
5117 && mode != CC_DLEmode && mode != CC_DLTmode
5118 && mode != CC_DGEmode && mode != CC_DGTmode
5119 && mode != CC_DLEUmode && mode != CC_DLTUmode
5120 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5123 return cc_register (x, mode);
5126 /* Return TRUE if X references a SYMBOL_REF. */
5128 symbol_mentioned_p (rtx x)
5133 if (GET_CODE (x) == SYMBOL_REF)
5136 fmt = GET_RTX_FORMAT (GET_CODE (x));
5138 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5144 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5145 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5148 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5155 /* Return TRUE if X references a LABEL_REF. */
5157 label_mentioned_p (rtx x)
5162 if (GET_CODE (x) == LABEL_REF)
5165 fmt = GET_RTX_FORMAT (GET_CODE (x));
5166 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5172 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5173 if (label_mentioned_p (XVECEXP (x, i, j)))
5176 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5186 enum rtx_code code = GET_CODE (x);
5190 else if (code == SMIN)
5192 else if (code == UMIN)
5194 else if (code == UMAX)
5200 /* Return 1 if memory locations are adjacent. */
5202 adjacent_mem_locations (rtx a, rtx b)
5204 if ((GET_CODE (XEXP (a, 0)) == REG
5205 || (GET_CODE (XEXP (a, 0)) == PLUS
5206 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5207 && (GET_CODE (XEXP (b, 0)) == REG
5208 || (GET_CODE (XEXP (b, 0)) == PLUS
5209 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5211 int val0 = 0, val1 = 0;
5214 if (GET_CODE (XEXP (a, 0)) == PLUS)
5216 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5217 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5220 reg0 = REGNO (XEXP (a, 0));
5222 if (GET_CODE (XEXP (b, 0)) == PLUS)
5224 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5225 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5228 reg1 = REGNO (XEXP (b, 0));
5230 /* Don't accept any offset that will require multiple
5231 instructions to handle, since this would cause the
5232 arith_adjacentmem pattern to output an overlong sequence. */
5233 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5236 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5241 /* Return 1 if OP is a load multiple operation. It is known to be
5242 parallel and the first section will be tested. */
5244 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5246 HOST_WIDE_INT count = XVECLEN (op, 0);
5249 HOST_WIDE_INT i = 1, base = 0;
5253 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5256 /* Check to see if this might be a write-back. */
5257 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5262 /* Now check it more carefully. */
5263 if (GET_CODE (SET_DEST (elt)) != REG
5264 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5265 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5266 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5270 /* Perform a quick check so we don't blow up below. */
5272 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5273 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5274 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5277 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5278 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5280 for (; i < count; i++)
5282 elt = XVECEXP (op, 0, i);
5284 if (GET_CODE (elt) != SET
5285 || GET_CODE (SET_DEST (elt)) != REG
5286 || GET_MODE (SET_DEST (elt)) != SImode
5287 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5288 || GET_CODE (SET_SRC (elt)) != MEM
5289 || GET_MODE (SET_SRC (elt)) != SImode
5290 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5291 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5292 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5293 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5300 /* Return 1 if OP is a store multiple operation. It is known to be
5301 parallel and the first section will be tested. */
5303 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5305 HOST_WIDE_INT count = XVECLEN (op, 0);
5308 HOST_WIDE_INT i = 1, base = 0;
5312 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5315 /* Check to see if this might be a write-back. */
5316 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5321 /* Now check it more carefully. */
5322 if (GET_CODE (SET_DEST (elt)) != REG
5323 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5324 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5325 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5329 /* Perform a quick check so we don't blow up below. */
5331 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5332 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5333 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5336 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5337 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5339 for (; i < count; i++)
5341 elt = XVECEXP (op, 0, i);
5343 if (GET_CODE (elt) != SET
5344 || GET_CODE (SET_SRC (elt)) != REG
5345 || GET_MODE (SET_SRC (elt)) != SImode
5346 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5347 || GET_CODE (SET_DEST (elt)) != MEM
5348 || GET_MODE (SET_DEST (elt)) != SImode
5349 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5350 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5351 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5352 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5360 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5361 HOST_WIDE_INT *load_offset)
5363 int unsorted_regs[4];
5364 HOST_WIDE_INT unsorted_offsets[4];
5369 /* Can only handle 2, 3, or 4 insns at present,
5370 though could be easily extended if required. */
5371 if (nops < 2 || nops > 4)
5374 /* Loop over the operands and check that the memory references are
5375 suitable (ie immediate offsets from the same base register). At
5376 the same time, extract the target register, and the memory
5378 for (i = 0; i < nops; i++)
5383 /* Convert a subreg of a mem into the mem itself. */
5384 if (GET_CODE (operands[nops + i]) == SUBREG)
5385 operands[nops + i] = alter_subreg (operands + (nops + i));
5387 if (GET_CODE (operands[nops + i]) != MEM)
5390 /* Don't reorder volatile memory references; it doesn't seem worth
5391 looking for the case where the order is ok anyway. */
5392 if (MEM_VOLATILE_P (operands[nops + i]))
5395 offset = const0_rtx;
5397 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5398 || (GET_CODE (reg) == SUBREG
5399 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5400 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5401 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5403 || (GET_CODE (reg) == SUBREG
5404 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5405 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5410 base_reg = REGNO (reg);
5411 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5412 ? REGNO (operands[i])
5413 : REGNO (SUBREG_REG (operands[i])));
5418 if (base_reg != (int) REGNO (reg))
5419 /* Not addressed from the same base register. */
5422 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5423 ? REGNO (operands[i])
5424 : REGNO (SUBREG_REG (operands[i])));
5425 if (unsorted_regs[i] < unsorted_regs[order[0]])
5429 /* If it isn't an integer register, or if it overwrites the
5430 base register but isn't the last insn in the list, then
5431 we can't do this. */
5432 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5433 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5436 unsorted_offsets[i] = INTVAL (offset);
5439 /* Not a suitable memory address. */
5443 /* All the useful information has now been extracted from the
5444 operands into unsorted_regs and unsorted_offsets; additionally,
5445 order[0] has been set to the lowest numbered register in the
5446 list. Sort the registers into order, and check that the memory
5447 offsets are ascending and adjacent. */
5449 for (i = 1; i < nops; i++)
5453 order[i] = order[i - 1];
5454 for (j = 0; j < nops; j++)
5455 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5456 && (order[i] == order[i - 1]
5457 || unsorted_regs[j] < unsorted_regs[order[i]]))
5460 /* Have we found a suitable register? if not, one must be used more
5462 if (order[i] == order[i - 1])
5465 /* Is the memory address adjacent and ascending? */
5466 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5474 for (i = 0; i < nops; i++)
5475 regs[i] = unsorted_regs[order[i]];
5477 *load_offset = unsorted_offsets[order[0]];
5480 if (unsorted_offsets[order[0]] == 0)
5481 return 1; /* ldmia */
5483 if (unsorted_offsets[order[0]] == 4)
5484 return 2; /* ldmib */
5486 if (unsorted_offsets[order[nops - 1]] == 0)
5487 return 3; /* ldmda */
5489 if (unsorted_offsets[order[nops - 1]] == -4)
5490 return 4; /* ldmdb */
5492 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5493 if the offset isn't small enough. The reason 2 ldrs are faster
5494 is because these ARMs are able to do more than one cache access
5495 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5496 whilst the ARM8 has a double bandwidth cache. This means that
5497 these cores can do both an instruction fetch and a data fetch in
5498 a single cycle, so the trick of calculating the address into a
5499 scratch register (one of the result regs) and then doing a load
5500 multiple actually becomes slower (and no smaller in code size).
5501 That is the transformation
5503 ldr rd1, [rbase + offset]
5504 ldr rd2, [rbase + offset + 4]
5508 add rd1, rbase, offset
5509 ldmia rd1, {rd1, rd2}
5511 produces worse code -- '3 cycles + any stalls on rd2' instead of
5512 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5513 access per cycle, the first sequence could never complete in less
5514 than 6 cycles, whereas the ldm sequence would only take 5 and
5515 would make better use of sequential accesses if not hitting the
5518 We cheat here and test 'arm_ld_sched' which we currently know to
5519 only be true for the ARM8, ARM9 and StrongARM. If this ever
5520 changes, then the test below needs to be reworked. */
5521 if (nops == 2 && arm_ld_sched)
5524 /* Can't do it without setting up the offset, only do this if it takes
5525 no more than one insn. */
5526 return (const_ok_for_arm (unsorted_offsets[order[0]])
5527 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5531 emit_ldm_seq (rtx *operands, int nops)
5535 HOST_WIDE_INT offset;
5539 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5542 strcpy (buf, "ldm%?ia\t");
5546 strcpy (buf, "ldm%?ib\t");
5550 strcpy (buf, "ldm%?da\t");
5554 strcpy (buf, "ldm%?db\t");
5559 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5560 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5563 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5564 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5566 output_asm_insn (buf, operands);
5568 strcpy (buf, "ldm%?ia\t");
5575 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5576 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5578 for (i = 1; i < nops; i++)
5579 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5580 reg_names[regs[i]]);
5582 strcat (buf, "}\t%@ phole ldm");
5584 output_asm_insn (buf, operands);
5589 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5590 HOST_WIDE_INT * load_offset)
5592 int unsorted_regs[4];
5593 HOST_WIDE_INT unsorted_offsets[4];
5598 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5599 extended if required. */
5600 if (nops < 2 || nops > 4)
5603 /* Loop over the operands and check that the memory references are
5604 suitable (ie immediate offsets from the same base register). At
5605 the same time, extract the target register, and the memory
5607 for (i = 0; i < nops; i++)
5612 /* Convert a subreg of a mem into the mem itself. */
5613 if (GET_CODE (operands[nops + i]) == SUBREG)
5614 operands[nops + i] = alter_subreg (operands + (nops + i));
5616 if (GET_CODE (operands[nops + i]) != MEM)
5619 /* Don't reorder volatile memory references; it doesn't seem worth
5620 looking for the case where the order is ok anyway. */
5621 if (MEM_VOLATILE_P (operands[nops + i]))
5624 offset = const0_rtx;
5626 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5627 || (GET_CODE (reg) == SUBREG
5628 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5629 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5630 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5632 || (GET_CODE (reg) == SUBREG
5633 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5634 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5639 base_reg = REGNO (reg);
5640 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5641 ? REGNO (operands[i])
5642 : REGNO (SUBREG_REG (operands[i])));
5647 if (base_reg != (int) REGNO (reg))
5648 /* Not addressed from the same base register. */
5651 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5652 ? REGNO (operands[i])
5653 : REGNO (SUBREG_REG (operands[i])));
5654 if (unsorted_regs[i] < unsorted_regs[order[0]])
5658 /* If it isn't an integer register, then we can't do this. */
5659 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5662 unsorted_offsets[i] = INTVAL (offset);
5665 /* Not a suitable memory address. */
5669 /* All the useful information has now been extracted from the
5670 operands into unsorted_regs and unsorted_offsets; additionally,
5671 order[0] has been set to the lowest numbered register in the
5672 list. Sort the registers into order, and check that the memory
5673 offsets are ascending and adjacent. */
5675 for (i = 1; i < nops; i++)
5679 order[i] = order[i - 1];
5680 for (j = 0; j < nops; j++)
5681 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5682 && (order[i] == order[i - 1]
5683 || unsorted_regs[j] < unsorted_regs[order[i]]))
5686 /* Have we found a suitable register? if not, one must be used more
5688 if (order[i] == order[i - 1])
5691 /* Is the memory address adjacent and ascending? */
5692 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5700 for (i = 0; i < nops; i++)
5701 regs[i] = unsorted_regs[order[i]];
5703 *load_offset = unsorted_offsets[order[0]];
5706 if (unsorted_offsets[order[0]] == 0)
5707 return 1; /* stmia */
5709 if (unsorted_offsets[order[0]] == 4)
5710 return 2; /* stmib */
5712 if (unsorted_offsets[order[nops - 1]] == 0)
5713 return 3; /* stmda */
5715 if (unsorted_offsets[order[nops - 1]] == -4)
5716 return 4; /* stmdb */
5722 emit_stm_seq (rtx *operands, int nops)
5726 HOST_WIDE_INT offset;
5730 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5733 strcpy (buf, "stm%?ia\t");
5737 strcpy (buf, "stm%?ib\t");
5741 strcpy (buf, "stm%?da\t");
5745 strcpy (buf, "stm%?db\t");
5752 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5753 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5755 for (i = 1; i < nops; i++)
5756 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5757 reg_names[regs[i]]);
5759 strcat (buf, "}\t%@ phole stm");
5761 output_asm_insn (buf, operands);
5766 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5768 if (GET_CODE (op) != PARALLEL
5769 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5770 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5771 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5777 /* Routines for use in generating RTL. */
5780 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5781 int write_back, int unchanging_p, int in_struct_p,
5786 int sign = up ? 1 : -1;
5789 /* XScale has load-store double instructions, but they have stricter
5790 alignment requirements than load-store multiple, so we can not
5793 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5794 the pipeline until completion.
5802 An ldr instruction takes 1-3 cycles, but does not block the
5811 Best case ldr will always win. However, the more ldr instructions
5812 we issue, the less likely we are to be able to schedule them well.
5813 Using ldr instructions also increases code size.
5815 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5816 for counts of 3 or 4 regs. */
5817 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5823 for (i = 0; i < count; i++)
5825 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5826 RTX_UNCHANGING_P (mem) = unchanging_p;
5827 MEM_IN_STRUCT_P (mem) = in_struct_p;
5828 MEM_SCALAR_P (mem) = scalar_p;
5829 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5833 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5841 result = gen_rtx_PARALLEL (VOIDmode,
5842 rtvec_alloc (count + (write_back ? 1 : 0)));
5845 XVECEXP (result, 0, 0)
5846 = gen_rtx_SET (GET_MODE (from), from,
5847 plus_constant (from, count * 4 * sign));
5852 for (j = 0; i < count; i++, j++)
5854 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5855 RTX_UNCHANGING_P (mem) = unchanging_p;
5856 MEM_IN_STRUCT_P (mem) = in_struct_p;
5857 MEM_SCALAR_P (mem) = scalar_p;
5858 XVECEXP (result, 0, i)
5859 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5866 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5867 int write_back, int unchanging_p, int in_struct_p,
5872 int sign = up ? 1 : -1;
5875 /* See arm_gen_load_multiple for discussion of
5876 the pros/cons of ldm/stm usage for XScale. */
5877 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5883 for (i = 0; i < count; i++)
5885 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5886 RTX_UNCHANGING_P (mem) = unchanging_p;
5887 MEM_IN_STRUCT_P (mem) = in_struct_p;
5888 MEM_SCALAR_P (mem) = scalar_p;
5889 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5893 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5901 result = gen_rtx_PARALLEL (VOIDmode,
5902 rtvec_alloc (count + (write_back ? 1 : 0)));
5905 XVECEXP (result, 0, 0)
5906 = gen_rtx_SET (GET_MODE (to), to,
5907 plus_constant (to, count * 4 * sign));
5912 for (j = 0; i < count; i++, j++)
5914 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5915 RTX_UNCHANGING_P (mem) = unchanging_p;
5916 MEM_IN_STRUCT_P (mem) = in_struct_p;
5917 MEM_SCALAR_P (mem) = scalar_p;
5919 XVECEXP (result, 0, i)
5920 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5927 arm_gen_movstrqi (rtx *operands)
5929 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5932 rtx st_src, st_dst, fin_src, fin_dst;
5933 rtx part_bytes_reg = NULL;
5935 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5936 int dst_scalar_p, src_scalar_p;
5938 if (GET_CODE (operands[2]) != CONST_INT
5939 || GET_CODE (operands[3]) != CONST_INT
5940 || INTVAL (operands[2]) > 64
5941 || INTVAL (operands[3]) & 3)
5944 st_dst = XEXP (operands[0], 0);
5945 st_src = XEXP (operands[1], 0);
5947 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5948 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5949 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5950 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5951 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5952 src_scalar_p = MEM_SCALAR_P (operands[1]);
5954 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5955 fin_src = src = copy_to_mode_reg (SImode, st_src);
5957 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5958 out_words_to_go = INTVAL (operands[2]) / 4;
5959 last_bytes = INTVAL (operands[2]) & 3;
5961 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5962 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5964 for (i = 0; in_words_to_go >= 2; i+=4)
5966 if (in_words_to_go > 4)
5967 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5972 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5973 FALSE, src_unchanging_p,
5974 src_in_struct_p, src_scalar_p));
5976 if (out_words_to_go)
5978 if (out_words_to_go > 4)
5979 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5983 else if (out_words_to_go != 1)
5984 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5993 mem = gen_rtx_MEM (SImode, dst);
5994 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5995 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5996 MEM_SCALAR_P (mem) = dst_scalar_p;
5997 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5998 if (last_bytes != 0)
5999 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6003 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6004 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6007 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6008 if (out_words_to_go)
6012 mem = gen_rtx_MEM (SImode, src);
6013 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6014 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6015 MEM_SCALAR_P (mem) = src_scalar_p;
6016 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
6017 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6019 mem = gen_rtx_MEM (SImode, dst);
6020 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6021 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6022 MEM_SCALAR_P (mem) = dst_scalar_p;
6023 emit_move_insn (mem, sreg);
6024 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6027 if (in_words_to_go) /* Sanity check */
6033 if (in_words_to_go < 0)
6036 mem = gen_rtx_MEM (SImode, src);
6037 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6038 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6039 MEM_SCALAR_P (mem) = src_scalar_p;
6040 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6043 if (last_bytes && part_bytes_reg == NULL)
6046 if (BYTES_BIG_ENDIAN && last_bytes)
6048 rtx tmp = gen_reg_rtx (SImode);
6050 /* The bytes we want are in the top end of the word. */
6051 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6052 GEN_INT (8 * (4 - last_bytes))));
6053 part_bytes_reg = tmp;
6057 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6058 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6059 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6060 MEM_SCALAR_P (mem) = dst_scalar_p;
6061 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6065 tmp = gen_reg_rtx (SImode);
6066 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6067 part_bytes_reg = tmp;
6076 mem = gen_rtx_MEM (HImode, dst);
6077 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6078 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6079 MEM_SCALAR_P (mem) = dst_scalar_p;
6080 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6084 rtx tmp = gen_reg_rtx (SImode);
6086 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6087 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6088 part_bytes_reg = tmp;
6094 mem = gen_rtx_MEM (QImode, dst);
6095 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6096 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6097 MEM_SCALAR_P (mem) = dst_scalar_p;
6098 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6105 /* Generate a memory reference for a half word, such that it will be loaded
6106 into the top 16 bits of the word. We can assume that the address is
6107 known to be alignable and of the form reg, or plus (reg, const). */
6110 arm_gen_rotated_half_load (rtx memref)
6112 HOST_WIDE_INT offset = 0;
6113 rtx base = XEXP (memref, 0);
6115 if (GET_CODE (base) == PLUS)
6117 offset = INTVAL (XEXP (base, 1));
6118 base = XEXP (base, 0);
6121 /* If we aren't allowed to generate unaligned addresses, then fail. */
6122 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6125 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6127 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6130 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6133 /* Select a dominance comparison mode if possible for a test of the general
6134 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6135 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6136 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6137 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6138 In all cases OP will be either EQ or NE, but we don't need to know which
6139 here. If we are unable to support a dominance comparison we return
6140 CC mode. This will then fail to match for the RTL expressions that
6141 generate this call. */
6143 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6145 enum rtx_code cond1, cond2;
6148 /* Currently we will probably get the wrong result if the individual
6149 comparisons are not simple. This also ensures that it is safe to
6150 reverse a comparison if necessary. */
6151 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6153 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6157 /* The if_then_else variant of this tests the second condition if the
6158 first passes, but is true if the first fails. Reverse the first
6159 condition to get a true "inclusive-or" expression. */
6160 if (cond_or == DOM_CC_NX_OR_Y)
6161 cond1 = reverse_condition (cond1);
6163 /* If the comparisons are not equal, and one doesn't dominate the other,
6164 then we can't do this. */
6166 && !comparison_dominates_p (cond1, cond2)
6167 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6172 enum rtx_code temp = cond1;
6180 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6185 case LE: return CC_DLEmode;
6186 case LEU: return CC_DLEUmode;
6187 case GE: return CC_DGEmode;
6188 case GEU: return CC_DGEUmode;
6195 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6204 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6213 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6222 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6230 /* The remaining cases only occur when both comparisons are the
6255 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6257 /* All floating point compares return CCFP if it is an equality
6258 comparison, and CCFPE otherwise. */
6259 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6279 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6288 /* A compare with a shifted operand. Because of canonicalization, the
6289 comparison will have to be swapped when we emit the assembler. */
6290 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6291 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6292 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6293 || GET_CODE (x) == ROTATERT))
6296 /* This is a special case that is used by combine to allow a
6297 comparison of a shifted byte load to be split into a zero-extend
6298 followed by a comparison of the shifted integer (only valid for
6299 equalities and unsigned inequalities). */
6300 if (GET_MODE (x) == SImode
6301 && GET_CODE (x) == ASHIFT
6302 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6303 && GET_CODE (XEXP (x, 0)) == SUBREG
6304 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6305 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6306 && (op == EQ || op == NE
6307 || op == GEU || op == GTU || op == LTU || op == LEU)
6308 && GET_CODE (y) == CONST_INT)
6311 /* A construct for a conditional compare, if the false arm contains
6312 0, then both conditions must be true, otherwise either condition
6313 must be true. Not all conditions are possible, so CCmode is
6314 returned if it can't be done. */
6315 if (GET_CODE (x) == IF_THEN_ELSE
6316 && (XEXP (x, 2) == const0_rtx
6317 || XEXP (x, 2) == const1_rtx)
6318 && COMPARISON_P (XEXP (x, 0))
6319 && COMPARISON_P (XEXP (x, 1)))
6320 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6321 INTVAL (XEXP (x, 2)));
6323 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6324 if (GET_CODE (x) == AND
6325 && COMPARISON_P (XEXP (x, 0))
6326 && COMPARISON_P (XEXP (x, 1)))
6327 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6330 if (GET_CODE (x) == IOR
6331 && COMPARISON_P (XEXP (x, 0))
6332 && COMPARISON_P (XEXP (x, 1)))
6333 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6336 /* An operation (on Thumb) where we want to test for a single bit.
6337 This is done by shifting that bit up into the top bit of a
6338 scratch register; we can then branch on the sign bit. */
6340 && GET_MODE (x) == SImode
6341 && (op == EQ || op == NE)
6342 && (GET_CODE (x) == ZERO_EXTRACT))
6345 /* An operation that sets the condition codes as a side-effect, the
6346 V flag is not set correctly, so we can only use comparisons where
6347 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6349 if (GET_MODE (x) == SImode
6351 && (op == EQ || op == NE || op == LT || op == GE)
6352 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6353 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6354 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6355 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6356 || GET_CODE (x) == LSHIFTRT
6357 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6358 || GET_CODE (x) == ROTATERT
6359 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6362 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6365 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6366 && GET_CODE (x) == PLUS
6367 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6373 /* X and Y are two things to compare using CODE. Emit the compare insn and
6374 return the rtx for register 0 in the proper mode. FP means this is a
6375 floating point compare: I don't think that it is needed on the arm. */
6377 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6379 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6380 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6382 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6383 gen_rtx_COMPARE (mode, x, y)));
6388 /* Generate a sequence of insns that will generate the correct return
6389 address mask depending on the physical architecture that the program
6392 arm_gen_return_addr_mask (void)
6394 rtx reg = gen_reg_rtx (Pmode);
6396 emit_insn (gen_return_addr_mask (reg));
6401 arm_reload_in_hi (rtx *operands)
6403 rtx ref = operands[1];
6405 HOST_WIDE_INT offset = 0;
6407 if (GET_CODE (ref) == SUBREG)
6409 offset = SUBREG_BYTE (ref);
6410 ref = SUBREG_REG (ref);
6413 if (GET_CODE (ref) == REG)
6415 /* We have a pseudo which has been spilt onto the stack; there
6416 are two cases here: the first where there is a simple
6417 stack-slot replacement and a second where the stack-slot is
6418 out of range, or is used as a subreg. */
6419 if (reg_equiv_mem[REGNO (ref)])
6421 ref = reg_equiv_mem[REGNO (ref)];
6422 base = find_replacement (&XEXP (ref, 0));
6425 /* The slot is out of range, or was dressed up in a SUBREG. */
6426 base = reg_equiv_address[REGNO (ref)];
6429 base = find_replacement (&XEXP (ref, 0));
6431 /* Handle the case where the address is too complex to be offset by 1. */
6432 if (GET_CODE (base) == MINUS
6433 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6435 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6437 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6440 else if (GET_CODE (base) == PLUS)
6442 /* The addend must be CONST_INT, or we would have dealt with it above. */
6443 HOST_WIDE_INT hi, lo;
6445 offset += INTVAL (XEXP (base, 1));
6446 base = XEXP (base, 0);
6448 /* Rework the address into a legal sequence of insns. */
6449 /* Valid range for lo is -4095 -> 4095 */
6452 : -((-offset) & 0xfff));
6454 /* Corner case, if lo is the max offset then we would be out of range
6455 once we have added the additional 1 below, so bump the msb into the
6456 pre-loading insn(s). */
6460 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6461 ^ (HOST_WIDE_INT) 0x80000000)
6462 - (HOST_WIDE_INT) 0x80000000);
6464 if (hi + lo != offset)
6469 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6471 /* Get the base address; addsi3 knows how to handle constants
6472 that require more than one insn. */
6473 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6479 /* Operands[2] may overlap operands[0] (though it won't overlap
6480 operands[1]), that's why we asked for a DImode reg -- so we can
6481 use the bit that does not overlap. */
6482 if (REGNO (operands[2]) == REGNO (operands[0]))
6483 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6485 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6487 emit_insn (gen_zero_extendqisi2 (scratch,
6488 gen_rtx_MEM (QImode,
6489 plus_constant (base,
6491 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6492 gen_rtx_MEM (QImode,
6493 plus_constant (base,
6495 if (!BYTES_BIG_ENDIAN)
6496 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6497 gen_rtx_IOR (SImode,
6500 gen_rtx_SUBREG (SImode, operands[0], 0),
6504 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6505 gen_rtx_IOR (SImode,
6506 gen_rtx_ASHIFT (SImode, scratch,
6508 gen_rtx_SUBREG (SImode, operands[0],
6512 /* Handle storing a half-word to memory during reload by synthesizing as two
6513 byte stores. Take care not to clobber the input values until after we
6514 have moved them somewhere safe. This code assumes that if the DImode
6515 scratch in operands[2] overlaps either the input value or output address
6516 in some way, then that value must die in this insn (we absolutely need
6517 two scratch registers for some corner cases). */
6519 arm_reload_out_hi (rtx *operands)
6521 rtx ref = operands[0];
6522 rtx outval = operands[1];
6524 HOST_WIDE_INT offset = 0;
6526 if (GET_CODE (ref) == SUBREG)
6528 offset = SUBREG_BYTE (ref);
6529 ref = SUBREG_REG (ref);
6532 if (GET_CODE (ref) == REG)
6534 /* We have a pseudo which has been spilt onto the stack; there
6535 are two cases here: the first where there is a simple
6536 stack-slot replacement and a second where the stack-slot is
6537 out of range, or is used as a subreg. */
6538 if (reg_equiv_mem[REGNO (ref)])
6540 ref = reg_equiv_mem[REGNO (ref)];
6541 base = find_replacement (&XEXP (ref, 0));
6544 /* The slot is out of range, or was dressed up in a SUBREG. */
6545 base = reg_equiv_address[REGNO (ref)];
6548 base = find_replacement (&XEXP (ref, 0));
6550 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6552 /* Handle the case where the address is too complex to be offset by 1. */
6553 if (GET_CODE (base) == MINUS
6554 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6556 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6558 /* Be careful not to destroy OUTVAL. */
6559 if (reg_overlap_mentioned_p (base_plus, outval))
6561 /* Updating base_plus might destroy outval, see if we can
6562 swap the scratch and base_plus. */
6563 if (!reg_overlap_mentioned_p (scratch, outval))
6566 scratch = base_plus;
6571 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6573 /* Be conservative and copy OUTVAL into the scratch now,
6574 this should only be necessary if outval is a subreg
6575 of something larger than a word. */
6576 /* XXX Might this clobber base? I can't see how it can,
6577 since scratch is known to overlap with OUTVAL, and
6578 must be wider than a word. */
6579 emit_insn (gen_movhi (scratch_hi, outval));
6580 outval = scratch_hi;
6584 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6587 else if (GET_CODE (base) == PLUS)
6589 /* The addend must be CONST_INT, or we would have dealt with it above. */
6590 HOST_WIDE_INT hi, lo;
6592 offset += INTVAL (XEXP (base, 1));
6593 base = XEXP (base, 0);
6595 /* Rework the address into a legal sequence of insns. */
6596 /* Valid range for lo is -4095 -> 4095 */
6599 : -((-offset) & 0xfff));
6601 /* Corner case, if lo is the max offset then we would be out of range
6602 once we have added the additional 1 below, so bump the msb into the
6603 pre-loading insn(s). */
6607 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6608 ^ (HOST_WIDE_INT) 0x80000000)
6609 - (HOST_WIDE_INT) 0x80000000);
6611 if (hi + lo != offset)
6616 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6618 /* Be careful not to destroy OUTVAL. */
6619 if (reg_overlap_mentioned_p (base_plus, outval))
6621 /* Updating base_plus might destroy outval, see if we
6622 can swap the scratch and base_plus. */
6623 if (!reg_overlap_mentioned_p (scratch, outval))
6626 scratch = base_plus;
6631 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6633 /* Be conservative and copy outval into scratch now,
6634 this should only be necessary if outval is a
6635 subreg of something larger than a word. */
6636 /* XXX Might this clobber base? I can't see how it
6637 can, since scratch is known to overlap with
6639 emit_insn (gen_movhi (scratch_hi, outval));
6640 outval = scratch_hi;
6644 /* Get the base address; addsi3 knows how to handle constants
6645 that require more than one insn. */
6646 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6652 if (BYTES_BIG_ENDIAN)
6654 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6655 plus_constant (base, offset + 1)),
6656 gen_lowpart (QImode, outval)));
6657 emit_insn (gen_lshrsi3 (scratch,
6658 gen_rtx_SUBREG (SImode, outval, 0),
6660 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6661 gen_lowpart (QImode, scratch)));
6665 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6666 gen_lowpart (QImode, outval)));
6667 emit_insn (gen_lshrsi3 (scratch,
6668 gen_rtx_SUBREG (SImode, outval, 0),
6670 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6671 plus_constant (base, offset + 1)),
6672 gen_lowpart (QImode, scratch)));
6676 /* Print a symbolic form of X to the debug file, F. */
6678 arm_print_value (FILE *f, rtx x)
6680 switch (GET_CODE (x))
6683 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6687 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6695 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6697 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6698 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6706 fprintf (f, "\"%s\"", XSTR (x, 0));
6710 fprintf (f, "`%s'", XSTR (x, 0));
6714 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6718 arm_print_value (f, XEXP (x, 0));
6722 arm_print_value (f, XEXP (x, 0));
6724 arm_print_value (f, XEXP (x, 1));
6732 fprintf (f, "????");
6737 /* Routines for manipulation of the constant pool. */
6739 /* Arm instructions cannot load a large constant directly into a
6740 register; they have to come from a pc relative load. The constant
6741 must therefore be placed in the addressable range of the pc
6742 relative load. Depending on the precise pc relative load
6743 instruction the range is somewhere between 256 bytes and 4k. This
6744 means that we often have to dump a constant inside a function, and
6745 generate code to branch around it.
6747 It is important to minimize this, since the branches will slow
6748 things down and make the code larger.
6750 Normally we can hide the table after an existing unconditional
6751 branch so that there is no interruption of the flow, but in the
6752 worst case the code looks like this:
6770 We fix this by performing a scan after scheduling, which notices
6771 which instructions need to have their operands fetched from the
6772 constant table and builds the table.
6774 The algorithm starts by building a table of all the constants that
6775 need fixing up and all the natural barriers in the function (places
6776 where a constant table can be dropped without breaking the flow).
6777 For each fixup we note how far the pc-relative replacement will be
6778 able to reach and the offset of the instruction into the function.
6780 Having built the table we then group the fixes together to form
6781 tables that are as large as possible (subject to addressing
6782 constraints) and emit each table of constants after the last
6783 barrier that is within range of all the instructions in the group.
6784 If a group does not contain a barrier, then we forcibly create one
6785 by inserting a jump instruction into the flow. Once the table has
6786 been inserted, the insns are then modified to reference the
6787 relevant entry in the pool.
6789 Possible enhancements to the algorithm (not implemented) are:
6791 1) For some processors and object formats, there may be benefit in
6792 aligning the pools to the start of cache lines; this alignment
6793 would need to be taken into account when calculating addressability
6796 /* These typedefs are located at the start of this file, so that
6797 they can be used in the prototypes there. This comment is to
6798 remind readers of that fact so that the following structures
6799 can be understood more easily.
6801 typedef struct minipool_node Mnode;
6802 typedef struct minipool_fixup Mfix; */
6804 struct minipool_node
6806 /* Doubly linked chain of entries. */
6809 /* The maximum offset into the code that this entry can be placed. While
6810 pushing fixes for forward references, all entries are sorted in order
6811 of increasing max_address. */
6812 HOST_WIDE_INT max_address;
6813 /* Similarly for an entry inserted for a backwards ref. */
6814 HOST_WIDE_INT min_address;
6815 /* The number of fixes referencing this entry. This can become zero
6816 if we "unpush" an entry. In this case we ignore the entry when we
6817 come to emit the code. */
6819 /* The offset from the start of the minipool. */
6820 HOST_WIDE_INT offset;
6821 /* The value in table. */
6823 /* The mode of value. */
6824 enum machine_mode mode;
6825 /* The size of the value. With iWMMXt enabled
6826 sizes > 4 also imply an alignment of 8-bytes. */
6830 struct minipool_fixup
6834 HOST_WIDE_INT address;
6836 enum machine_mode mode;
6840 HOST_WIDE_INT forwards;
6841 HOST_WIDE_INT backwards;
6844 /* Fixes less than a word need padding out to a word boundary. */
6845 #define MINIPOOL_FIX_SIZE(mode) \
6846 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6848 static Mnode * minipool_vector_head;
6849 static Mnode * minipool_vector_tail;
6850 static rtx minipool_vector_label;
6852 /* The linked list of all minipool fixes required for this function. */
6853 Mfix * minipool_fix_head;
6854 Mfix * minipool_fix_tail;
6855 /* The fix entry for the current minipool, once it has been placed. */
6856 Mfix * minipool_barrier;
6858 /* Determines if INSN is the start of a jump table. Returns the end
6859 of the TABLE or NULL_RTX. */
6861 is_jump_table (rtx insn)
6865 if (GET_CODE (insn) == JUMP_INSN
6866 && JUMP_LABEL (insn) != NULL
6867 && ((table = next_real_insn (JUMP_LABEL (insn)))
6868 == next_real_insn (insn))
6870 && GET_CODE (table) == JUMP_INSN
6871 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6872 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6878 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6879 #define JUMP_TABLES_IN_TEXT_SECTION 0
6882 static HOST_WIDE_INT
6883 get_jump_table_size (rtx insn)
6885 /* ADDR_VECs only take room if read-only data does into the text
6887 if (JUMP_TABLES_IN_TEXT_SECTION
6888 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6893 rtx body = PATTERN (insn);
6894 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6896 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6902 /* Move a minipool fix MP from its current location to before MAX_MP.
6903 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6904 constraints may need updating. */
6906 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6907 HOST_WIDE_INT max_address)
6909 /* This should never be true and the code below assumes these are
6916 if (max_address < mp->max_address)
6917 mp->max_address = max_address;
6921 if (max_address > max_mp->max_address - mp->fix_size)
6922 mp->max_address = max_mp->max_address - mp->fix_size;
6924 mp->max_address = max_address;
6926 /* Unlink MP from its current position. Since max_mp is non-null,
6927 mp->prev must be non-null. */
6928 mp->prev->next = mp->next;
6929 if (mp->next != NULL)
6930 mp->next->prev = mp->prev;
6932 minipool_vector_tail = mp->prev;
6934 /* Re-insert it before MAX_MP. */
6936 mp->prev = max_mp->prev;
6939 if (mp->prev != NULL)
6940 mp->prev->next = mp;
6942 minipool_vector_head = mp;
6945 /* Save the new entry. */
6948 /* Scan over the preceding entries and adjust their addresses as
6950 while (mp->prev != NULL
6951 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6953 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6960 /* Add a constant to the minipool for a forward reference. Returns the
6961 node added or NULL if the constant will not fit in this pool. */
6963 add_minipool_forward_ref (Mfix *fix)
6965 /* If set, max_mp is the first pool_entry that has a lower
6966 constraint than the one we are trying to add. */
6967 Mnode * max_mp = NULL;
6968 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6971 /* If this fix's address is greater than the address of the first
6972 entry, then we can't put the fix in this pool. We subtract the
6973 size of the current fix to ensure that if the table is fully
6974 packed we still have enough room to insert this value by suffling
6975 the other fixes forwards. */
6976 if (minipool_vector_head &&
6977 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6980 /* Scan the pool to see if a constant with the same value has
6981 already been added. While we are doing this, also note the
6982 location where we must insert the constant if it doesn't already
6984 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6986 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6987 && fix->mode == mp->mode
6988 && (GET_CODE (fix->value) != CODE_LABEL
6989 || (CODE_LABEL_NUMBER (fix->value)
6990 == CODE_LABEL_NUMBER (mp->value)))
6991 && rtx_equal_p (fix->value, mp->value))
6993 /* More than one fix references this entry. */
6995 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6998 /* Note the insertion point if necessary. */
7000 && mp->max_address > max_address)
7003 /* If we are inserting an 8-bytes aligned quantity and
7004 we have not already found an insertion point, then
7005 make sure that all such 8-byte aligned quantities are
7006 placed at the start of the pool. */
7007 if (ARM_DOUBLEWORD_ALIGN
7009 && fix->fix_size == 8
7010 && mp->fix_size != 8)
7013 max_address = mp->max_address;
7017 /* The value is not currently in the minipool, so we need to create
7018 a new entry for it. If MAX_MP is NULL, the entry will be put on
7019 the end of the list since the placement is less constrained than
7020 any existing entry. Otherwise, we insert the new fix before
7021 MAX_MP and, if necessary, adjust the constraints on the other
7023 mp = xmalloc (sizeof (* mp));
7024 mp->fix_size = fix->fix_size;
7025 mp->mode = fix->mode;
7026 mp->value = fix->value;
7028 /* Not yet required for a backwards ref. */
7029 mp->min_address = -65536;
7033 mp->max_address = max_address;
7035 mp->prev = minipool_vector_tail;
7037 if (mp->prev == NULL)
7039 minipool_vector_head = mp;
7040 minipool_vector_label = gen_label_rtx ();
7043 mp->prev->next = mp;
7045 minipool_vector_tail = mp;
7049 if (max_address > max_mp->max_address - mp->fix_size)
7050 mp->max_address = max_mp->max_address - mp->fix_size;
7052 mp->max_address = max_address;
7055 mp->prev = max_mp->prev;
7057 if (mp->prev != NULL)
7058 mp->prev->next = mp;
7060 minipool_vector_head = mp;
7063 /* Save the new entry. */
7066 /* Scan over the preceding entries and adjust their addresses as
7068 while (mp->prev != NULL
7069 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7071 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7079 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7080 HOST_WIDE_INT min_address)
7082 HOST_WIDE_INT offset;
7084 /* This should never be true, and the code below assumes these are
7091 if (min_address > mp->min_address)
7092 mp->min_address = min_address;
7096 /* We will adjust this below if it is too loose. */
7097 mp->min_address = min_address;
7099 /* Unlink MP from its current position. Since min_mp is non-null,
7100 mp->next must be non-null. */
7101 mp->next->prev = mp->prev;
7102 if (mp->prev != NULL)
7103 mp->prev->next = mp->next;
7105 minipool_vector_head = mp->next;
7107 /* Reinsert it after MIN_MP. */
7109 mp->next = min_mp->next;
7111 if (mp->next != NULL)
7112 mp->next->prev = mp;
7114 minipool_vector_tail = mp;
7120 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7122 mp->offset = offset;
7123 if (mp->refcount > 0)
7124 offset += mp->fix_size;
7126 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7127 mp->next->min_address = mp->min_address + mp->fix_size;
7133 /* Add a constant to the minipool for a backward reference. Returns the
7134 node added or NULL if the constant will not fit in this pool.
7136 Note that the code for insertion for a backwards reference can be
7137 somewhat confusing because the calculated offsets for each fix do
7138 not take into account the size of the pool (which is still under
7141 add_minipool_backward_ref (Mfix *fix)
7143 /* If set, min_mp is the last pool_entry that has a lower constraint
7144 than the one we are trying to add. */
7145 Mnode *min_mp = NULL;
7146 /* This can be negative, since it is only a constraint. */
7147 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7150 /* If we can't reach the current pool from this insn, or if we can't
7151 insert this entry at the end of the pool without pushing other
7152 fixes out of range, then we don't try. This ensures that we
7153 can't fail later on. */
7154 if (min_address >= minipool_barrier->address
7155 || (minipool_vector_tail->min_address + fix->fix_size
7156 >= minipool_barrier->address))
7159 /* Scan the pool to see if a constant with the same value has
7160 already been added. While we are doing this, also note the
7161 location where we must insert the constant if it doesn't already
7163 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7165 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7166 && fix->mode == mp->mode
7167 && (GET_CODE (fix->value) != CODE_LABEL
7168 || (CODE_LABEL_NUMBER (fix->value)
7169 == CODE_LABEL_NUMBER (mp->value)))
7170 && rtx_equal_p (fix->value, mp->value)
7171 /* Check that there is enough slack to move this entry to the
7172 end of the table (this is conservative). */
7174 > (minipool_barrier->address
7175 + minipool_vector_tail->offset
7176 + minipool_vector_tail->fix_size)))
7179 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7183 mp->min_address += fix->fix_size;
7186 /* Note the insertion point if necessary. */
7187 if (mp->min_address < min_address)
7189 /* For now, we do not allow the insertion of 8-byte alignment
7190 requiring nodes anywhere but at the start of the pool. */
7191 if (ARM_DOUBLEWORD_ALIGN
7192 && fix->fix_size == 8 && mp->fix_size != 8)
7197 else if (mp->max_address
7198 < minipool_barrier->address + mp->offset + fix->fix_size)
7200 /* Inserting before this entry would push the fix beyond
7201 its maximum address (which can happen if we have
7202 re-located a forwards fix); force the new fix to come
7205 min_address = mp->min_address + fix->fix_size;
7207 /* If we are inserting an 8-bytes aligned quantity and
7208 we have not already found an insertion point, then
7209 make sure that all such 8-byte aligned quantities are
7210 placed at the start of the pool. */
7211 else if (ARM_DOUBLEWORD_ALIGN
7213 && fix->fix_size == 8
7214 && mp->fix_size < 8)
7217 min_address = mp->min_address + fix->fix_size;
7222 /* We need to create a new entry. */
7223 mp = xmalloc (sizeof (* mp));
7224 mp->fix_size = fix->fix_size;
7225 mp->mode = fix->mode;
7226 mp->value = fix->value;
7228 mp->max_address = minipool_barrier->address + 65536;
7230 mp->min_address = min_address;
7235 mp->next = minipool_vector_head;
7237 if (mp->next == NULL)
7239 minipool_vector_tail = mp;
7240 minipool_vector_label = gen_label_rtx ();
7243 mp->next->prev = mp;
7245 minipool_vector_head = mp;
7249 mp->next = min_mp->next;
7253 if (mp->next != NULL)
7254 mp->next->prev = mp;
7256 minipool_vector_tail = mp;
7259 /* Save the new entry. */
7267 /* Scan over the following entries and adjust their offsets. */
7268 while (mp->next != NULL)
7270 if (mp->next->min_address < mp->min_address + mp->fix_size)
7271 mp->next->min_address = mp->min_address + mp->fix_size;
7274 mp->next->offset = mp->offset + mp->fix_size;
7276 mp->next->offset = mp->offset;
7285 assign_minipool_offsets (Mfix *barrier)
7287 HOST_WIDE_INT offset = 0;
7290 minipool_barrier = barrier;
7292 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7294 mp->offset = offset;
7296 if (mp->refcount > 0)
7297 offset += mp->fix_size;
7301 /* Output the literal table */
7303 dump_minipool (rtx scan)
7309 if (ARM_DOUBLEWORD_ALIGN)
7310 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7311 if (mp->refcount > 0 && mp->fix_size == 8)
7319 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7320 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7322 scan = emit_label_after (gen_label_rtx (), scan);
7323 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7324 scan = emit_label_after (minipool_vector_label, scan);
7326 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7328 if (mp->refcount > 0)
7333 ";; Offset %u, min %ld, max %ld ",
7334 (unsigned) mp->offset, (unsigned long) mp->min_address,
7335 (unsigned long) mp->max_address);
7336 arm_print_value (dump_file, mp->value);
7337 fputc ('\n', dump_file);
7340 switch (mp->fix_size)
7342 #ifdef HAVE_consttable_1
7344 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7348 #ifdef HAVE_consttable_2
7350 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7354 #ifdef HAVE_consttable_4
7356 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7360 #ifdef HAVE_consttable_8
7362 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7376 minipool_vector_head = minipool_vector_tail = NULL;
7377 scan = emit_insn_after (gen_consttable_end (), scan);
7378 scan = emit_barrier_after (scan);
7381 /* Return the cost of forcibly inserting a barrier after INSN. */
7383 arm_barrier_cost (rtx insn)
7385 /* Basing the location of the pool on the loop depth is preferable,
7386 but at the moment, the basic block information seems to be
7387 corrupt by this stage of the compilation. */
7389 rtx next = next_nonnote_insn (insn);
7391 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7394 switch (GET_CODE (insn))
7397 /* It will always be better to place the table before the label, rather
7406 return base_cost - 10;
7409 return base_cost + 10;
7413 /* Find the best place in the insn stream in the range
7414 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7415 Create the barrier by inserting a jump and add a new fix entry for
7418 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7420 HOST_WIDE_INT count = 0;
7422 rtx from = fix->insn;
7423 rtx selected = from;
7425 HOST_WIDE_INT selected_address;
7427 HOST_WIDE_INT max_count = max_address - fix->address;
7428 rtx label = gen_label_rtx ();
7430 selected_cost = arm_barrier_cost (from);
7431 selected_address = fix->address;
7433 while (from && count < max_count)
7438 /* This code shouldn't have been called if there was a natural barrier
7440 if (GET_CODE (from) == BARRIER)
7443 /* Count the length of this insn. */
7444 count += get_attr_length (from);
7446 /* If there is a jump table, add its length. */
7447 tmp = is_jump_table (from);
7450 count += get_jump_table_size (tmp);
7452 /* Jump tables aren't in a basic block, so base the cost on
7453 the dispatch insn. If we select this location, we will
7454 still put the pool after the table. */
7455 new_cost = arm_barrier_cost (from);
7457 if (count < max_count && new_cost <= selected_cost)
7460 selected_cost = new_cost;
7461 selected_address = fix->address + count;
7464 /* Continue after the dispatch table. */
7465 from = NEXT_INSN (tmp);
7469 new_cost = arm_barrier_cost (from);
7471 if (count < max_count && new_cost <= selected_cost)
7474 selected_cost = new_cost;
7475 selected_address = fix->address + count;
7478 from = NEXT_INSN (from);
7481 /* Create a new JUMP_INSN that branches around a barrier. */
7482 from = emit_jump_insn_after (gen_jump (label), selected);
7483 JUMP_LABEL (from) = label;
7484 barrier = emit_barrier_after (from);
7485 emit_label_after (label, barrier);
7487 /* Create a minipool barrier entry for the new barrier. */
7488 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7489 new_fix->insn = barrier;
7490 new_fix->address = selected_address;
7491 new_fix->next = fix->next;
7492 fix->next = new_fix;
7497 /* Record that there is a natural barrier in the insn stream at
7500 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7502 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7505 fix->address = address;
7508 if (minipool_fix_head != NULL)
7509 minipool_fix_tail->next = fix;
7511 minipool_fix_head = fix;
7513 minipool_fix_tail = fix;
7516 /* Record INSN, which will need fixing up to load a value from the
7517 minipool. ADDRESS is the offset of the insn since the start of the
7518 function; LOC is a pointer to the part of the insn which requires
7519 fixing; VALUE is the constant that must be loaded, which is of type
7522 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7523 enum machine_mode mode, rtx value)
7525 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7527 #ifdef AOF_ASSEMBLER
7528 /* PIC symbol references need to be converted into offsets into the
7530 /* XXX This shouldn't be done here. */
7531 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7532 value = aof_pic_entry (value);
7533 #endif /* AOF_ASSEMBLER */
7536 fix->address = address;
7539 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7541 fix->forwards = get_attr_pool_range (insn);
7542 fix->backwards = get_attr_neg_pool_range (insn);
7543 fix->minipool = NULL;
7545 /* If an insn doesn't have a range defined for it, then it isn't
7546 expecting to be reworked by this code. Better to abort now than
7547 to generate duff assembly code. */
7548 if (fix->forwards == 0 && fix->backwards == 0)
7551 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7552 So there might be an empty word before the start of the pool.
7553 Hence we reduce the forward range by 4 to allow for this
7555 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7561 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7562 GET_MODE_NAME (mode),
7563 INSN_UID (insn), (unsigned long) address,
7564 -1 * (long)fix->backwards, (long)fix->forwards);
7565 arm_print_value (dump_file, fix->value);
7566 fprintf (dump_file, "\n");
7569 /* Add it to the chain of fixes. */
7572 if (minipool_fix_head != NULL)
7573 minipool_fix_tail->next = fix;
7575 minipool_fix_head = fix;
7577 minipool_fix_tail = fix;
7580 /* Scan INSN and note any of its operands that need fixing.
7581 If DO_PUSHES is false we do not actually push any of the fixups
7582 needed. The function returns TRUE is any fixups were needed/pushed.
7583 This is used by arm_memory_load_p() which needs to know about loads
7584 of constants that will be converted into minipool loads. */
7586 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7588 bool result = false;
7591 extract_insn (insn);
7593 if (!constrain_operands (1))
7594 fatal_insn_not_found (insn);
7596 if (recog_data.n_alternatives == 0)
7599 /* Fill in recog_op_alt with information about the constraints of this insn. */
7600 preprocess_constraints ();
7602 for (opno = 0; opno < recog_data.n_operands; opno++)
7604 /* Things we need to fix can only occur in inputs. */
7605 if (recog_data.operand_type[opno] != OP_IN)
7608 /* If this alternative is a memory reference, then any mention
7609 of constants in this alternative is really to fool reload
7610 into allowing us to accept one there. We need to fix them up
7611 now so that we output the right code. */
7612 if (recog_op_alt[opno][which_alternative].memory_ok)
7614 rtx op = recog_data.operand[opno];
7616 if (CONSTANT_P (op))
7619 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7620 recog_data.operand_mode[opno], op);
7623 else if (GET_CODE (op) == MEM
7624 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7625 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7629 rtx cop = avoid_constant_pool_reference (op);
7631 /* Casting the address of something to a mode narrower
7632 than a word can cause avoid_constant_pool_reference()
7633 to return the pool reference itself. That's no good to
7634 us here. Lets just hope that we can use the
7635 constant pool value directly. */
7637 cop = get_pool_constant (XEXP (op, 0));
7639 push_minipool_fix (insn, address,
7640 recog_data.operand_loc[opno],
7641 recog_data.operand_mode[opno], cop);
7652 /* Gcc puts the pool in the wrong place for ARM, since we can only
7653 load addresses a limited distance around the pc. We do some
7654 special munging to move the constant pool values to the correct
7655 point in the code. */
7660 HOST_WIDE_INT address = 0;
7663 minipool_fix_head = minipool_fix_tail = NULL;
7665 /* The first insn must always be a note, or the code below won't
7666 scan it properly. */
7667 insn = get_insns ();
7668 if (GET_CODE (insn) != NOTE)
7671 /* Scan all the insns and record the operands that will need fixing. */
7672 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7674 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7675 && (arm_cirrus_insn_p (insn)
7676 || GET_CODE (insn) == JUMP_INSN
7677 || arm_memory_load_p (insn)))
7678 cirrus_reorg (insn);
7680 if (GET_CODE (insn) == BARRIER)
7681 push_minipool_barrier (insn, address);
7682 else if (INSN_P (insn))
7686 note_invalid_constants (insn, address, true);
7687 address += get_attr_length (insn);
7689 /* If the insn is a vector jump, add the size of the table
7690 and skip the table. */
7691 if ((table = is_jump_table (insn)) != NULL)
7693 address += get_jump_table_size (table);
7699 fix = minipool_fix_head;
7701 /* Now scan the fixups and perform the required changes. */
7706 Mfix * last_added_fix;
7707 Mfix * last_barrier = NULL;
7710 /* Skip any further barriers before the next fix. */
7711 while (fix && GET_CODE (fix->insn) == BARRIER)
7714 /* No more fixes. */
7718 last_added_fix = NULL;
7720 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7722 if (GET_CODE (ftmp->insn) == BARRIER)
7724 if (ftmp->address >= minipool_vector_head->max_address)
7727 last_barrier = ftmp;
7729 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7732 last_added_fix = ftmp; /* Keep track of the last fix added. */
7735 /* If we found a barrier, drop back to that; any fixes that we
7736 could have reached but come after the barrier will now go in
7737 the next mini-pool. */
7738 if (last_barrier != NULL)
7740 /* Reduce the refcount for those fixes that won't go into this
7742 for (fdel = last_barrier->next;
7743 fdel && fdel != ftmp;
7746 fdel->minipool->refcount--;
7747 fdel->minipool = NULL;
7750 ftmp = last_barrier;
7754 /* ftmp is first fix that we can't fit into this pool and
7755 there no natural barriers that we could use. Insert a
7756 new barrier in the code somewhere between the previous
7757 fix and this one, and arrange to jump around it. */
7758 HOST_WIDE_INT max_address;
7760 /* The last item on the list of fixes must be a barrier, so
7761 we can never run off the end of the list of fixes without
7762 last_barrier being set. */
7766 max_address = minipool_vector_head->max_address;
7767 /* Check that there isn't another fix that is in range that
7768 we couldn't fit into this pool because the pool was
7769 already too large: we need to put the pool before such an
7771 if (ftmp->address < max_address)
7772 max_address = ftmp->address;
7774 last_barrier = create_fix_barrier (last_added_fix, max_address);
7777 assign_minipool_offsets (last_barrier);
7781 if (GET_CODE (ftmp->insn) != BARRIER
7782 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7789 /* Scan over the fixes we have identified for this pool, fixing them
7790 up and adding the constants to the pool itself. */
7791 for (this_fix = fix; this_fix && ftmp != this_fix;
7792 this_fix = this_fix->next)
7793 if (GET_CODE (this_fix->insn) != BARRIER)
7796 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7797 minipool_vector_label),
7798 this_fix->minipool->offset);
7799 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7802 dump_minipool (last_barrier->insn);
7806 /* From now on we must synthesize any constants that we can't handle
7807 directly. This can happen if the RTL gets split during final
7808 instruction generation. */
7809 after_arm_reorg = 1;
7811 /* Free the minipool memory. */
7812 obstack_free (&minipool_obstack, minipool_startobj);
7815 /* Routines to output assembly language. */
7817 /* If the rtx is the correct value then return the string of the number.
7818 In this way we can ensure that valid double constants are generated even
7819 when cross compiling. */
7821 fp_immediate_constant (rtx x)
7826 if (!fp_consts_inited)
7829 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7830 for (i = 0; i < 8; i++)
7831 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7832 return strings_fp[i];
7837 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7839 fp_const_from_val (REAL_VALUE_TYPE *r)
7843 if (!fp_consts_inited)
7846 for (i = 0; i < 8; i++)
7847 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7848 return strings_fp[i];
7853 /* Output the operands of a LDM/STM instruction to STREAM.
7854 MASK is the ARM register set mask of which only bits 0-15 are important.
7855 REG is the base register, either the frame pointer or the stack pointer,
7856 INSTR is the possibly suffixed load or store instruction. */
7858 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7861 int not_first = FALSE;
7863 fputc ('\t', stream);
7864 asm_fprintf (stream, instr, reg);
7865 fputs (", {", stream);
7867 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7868 if (mask & (1 << i))
7871 fprintf (stream, ", ");
7873 asm_fprintf (stream, "%r", i);
7877 fprintf (stream, "}\n");
7881 /* Output a FLDMX instruction to STREAM.
7882 BASE if the register containing the address.
7883 REG and COUNT specify the register range.
7884 Extra registers may be added to avoid hardware bugs. */
7887 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7891 /* Workaround ARM10 VFPr1 bug. */
7892 if (count == 2 && !arm_arch6)
7899 fputc ('\t', stream);
7900 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7902 for (i = reg; i < reg + count; i++)
7905 fputs (", ", stream);
7906 asm_fprintf (stream, "d%d", i);
7908 fputs ("}\n", stream);
7913 /* Output the assembly for a store multiple. */
7916 vfp_output_fstmx (rtx * operands)
7923 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7924 p = strlen (pattern);
7926 if (GET_CODE (operands[1]) != REG)
7929 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7930 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7932 p += sprintf (&pattern[p], ", d%d", base + i);
7934 strcpy (&pattern[p], "}");
7936 output_asm_insn (pattern, operands);
7941 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7942 number of bytes pushed. */
7945 vfp_emit_fstmx (int base_reg, int count)
7952 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7953 register pairs are stored by a store multiple insn. We avoid this
7954 by pushing an extra pair. */
7955 if (count == 2 && !arm_arch6)
7957 if (base_reg == LAST_VFP_REGNUM - 3)
7962 /* ??? The frame layout is implementation defined. We describe
7963 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7964 We really need some way of representing the whole block so that the
7965 unwinder can figure it out at runtime. */
7966 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7967 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7969 reg = gen_rtx_REG (DFmode, base_reg);
7973 = gen_rtx_SET (VOIDmode,
7974 gen_rtx_MEM (BLKmode,
7975 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7976 gen_rtx_UNSPEC (BLKmode,
7980 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7981 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7982 GEN_INT (-(count * 8 + 4))));
7983 RTX_FRAME_RELATED_P (tmp) = 1;
7984 XVECEXP (dwarf, 0, 0) = tmp;
7986 tmp = gen_rtx_SET (VOIDmode,
7987 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7989 RTX_FRAME_RELATED_P (tmp) = 1;
7990 XVECEXP (dwarf, 0, 1) = tmp;
7992 for (i = 1; i < count; i++)
7994 reg = gen_rtx_REG (DFmode, base_reg);
7996 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7998 tmp = gen_rtx_SET (VOIDmode,
7999 gen_rtx_MEM (DFmode,
8000 gen_rtx_PLUS (SImode,
8004 RTX_FRAME_RELATED_P (tmp) = 1;
8005 XVECEXP (dwarf, 0, i + 1) = tmp;
8008 par = emit_insn (par);
8009 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8011 RTX_FRAME_RELATED_P (par) = 1;
8013 return count * 8 + 4;
8017 /* Output a 'call' insn. */
8019 output_call (rtx *operands)
8022 abort (); /* Patterns should call blx <reg> directly. */
8024 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8025 if (REGNO (operands[0]) == LR_REGNUM)
8027 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8028 output_asm_insn ("mov%?\t%0, %|lr", operands);
8031 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8033 if (TARGET_INTERWORK || arm_arch4t)
8034 output_asm_insn ("bx%?\t%0", operands);
8036 output_asm_insn ("mov%?\t%|pc, %0", operands);
8041 /* Output a 'call' insn that is a reference in memory. */
8043 output_call_mem (rtx *operands)
8045 if (TARGET_INTERWORK && !arm_arch5)
8047 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8048 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8049 output_asm_insn ("bx%?\t%|ip", operands);
8051 else if (regno_use_in (LR_REGNUM, operands[0]))
8053 /* LR is used in the memory address. We load the address in the
8054 first instruction. It's safe to use IP as the target of the
8055 load since the call will kill it anyway. */
8056 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8058 output_asm_insn ("blx%?%|ip", operands);
8061 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8063 output_asm_insn ("bx%?\t%|ip", operands);
8065 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8070 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8071 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8078 /* Output a move from arm registers to an fpa registers.
8079 OPERANDS[0] is an fpa register.
8080 OPERANDS[1] is the first registers of an arm register pair. */
8082 output_mov_long_double_fpa_from_arm (rtx *operands)
8084 int arm_reg0 = REGNO (operands[1]);
8087 if (arm_reg0 == IP_REGNUM)
8090 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8091 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8092 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8094 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8095 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8100 /* Output a move from an fpa register to arm registers.
8101 OPERANDS[0] is the first registers of an arm register pair.
8102 OPERANDS[1] is an fpa register. */
8104 output_mov_long_double_arm_from_fpa (rtx *operands)
8106 int arm_reg0 = REGNO (operands[0]);
8109 if (arm_reg0 == IP_REGNUM)
8112 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8113 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8114 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8116 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8117 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8121 /* Output a move from arm registers to arm registers of a long double
8122 OPERANDS[0] is the destination.
8123 OPERANDS[1] is the source. */
8125 output_mov_long_double_arm_from_arm (rtx *operands)
8127 /* We have to be careful here because the two might overlap. */
8128 int dest_start = REGNO (operands[0]);
8129 int src_start = REGNO (operands[1]);
8133 if (dest_start < src_start)
8135 for (i = 0; i < 3; i++)
8137 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8138 ops[1] = gen_rtx_REG (SImode, src_start + i);
8139 output_asm_insn ("mov%?\t%0, %1", ops);
8144 for (i = 2; i >= 0; i--)
8146 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8147 ops[1] = gen_rtx_REG (SImode, src_start + i);
8148 output_asm_insn ("mov%?\t%0, %1", ops);
8156 /* Output a move from arm registers to an fpa registers.
8157 OPERANDS[0] is an fpa register.
8158 OPERANDS[1] is the first registers of an arm register pair. */
8160 output_mov_double_fpa_from_arm (rtx *operands)
8162 int arm_reg0 = REGNO (operands[1]);
8165 if (arm_reg0 == IP_REGNUM)
8168 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8169 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8170 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8171 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8175 /* Output a move from an fpa register to arm registers.
8176 OPERANDS[0] is the first registers of an arm register pair.
8177 OPERANDS[1] is an fpa register. */
8179 output_mov_double_arm_from_fpa (rtx *operands)
8181 int arm_reg0 = REGNO (operands[0]);
8184 if (arm_reg0 == IP_REGNUM)
8187 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8188 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8189 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8190 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8194 /* Output a move between double words.
8195 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8196 or MEM<-REG and all MEMs must be offsettable addresses. */
8198 output_move_double (rtx *operands)
8200 enum rtx_code code0 = GET_CODE (operands[0]);
8201 enum rtx_code code1 = GET_CODE (operands[1]);
8206 int reg0 = REGNO (operands[0]);
8208 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8212 int reg1 = REGNO (operands[1]);
8213 if (reg1 == IP_REGNUM)
8216 /* Ensure the second source is not overwritten. */
8217 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8218 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8220 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8222 else if (code1 == CONST_VECTOR)
8224 HOST_WIDE_INT hint = 0;
8226 switch (GET_MODE (operands[1]))
8229 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8230 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8234 if (BYTES_BIG_ENDIAN)
8236 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8238 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8242 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8244 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8247 otherops[1] = GEN_INT (hint);
8250 if (BYTES_BIG_ENDIAN)
8252 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8254 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8258 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8260 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8263 operands[1] = GEN_INT (hint);
8267 if (BYTES_BIG_ENDIAN)
8269 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8271 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8273 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8275 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8279 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8281 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8283 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8285 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8288 otherops[1] = GEN_INT (hint);
8291 if (BYTES_BIG_ENDIAN)
8293 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8295 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8297 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8299 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8303 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8305 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8307 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8309 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8312 operands[1] = GEN_INT (hint);
8318 output_mov_immediate (operands);
8319 output_mov_immediate (otherops);
8321 else if (code1 == CONST_DOUBLE)
8323 if (GET_MODE (operands[1]) == DFmode)
8328 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8329 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8330 otherops[1] = GEN_INT (l[1]);
8331 operands[1] = GEN_INT (l[0]);
8333 else if (GET_MODE (operands[1]) != VOIDmode)
8335 else if (WORDS_BIG_ENDIAN)
8337 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8338 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8342 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8343 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8346 output_mov_immediate (operands);
8347 output_mov_immediate (otherops);
8349 else if (code1 == CONST_INT)
8351 #if HOST_BITS_PER_WIDE_INT > 32
8352 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8353 what the upper word is. */
8354 if (WORDS_BIG_ENDIAN)
8356 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8357 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8361 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8362 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8365 /* Sign extend the intval into the high-order word. */
8366 if (WORDS_BIG_ENDIAN)
8368 otherops[1] = operands[1];
8369 operands[1] = (INTVAL (operands[1]) < 0
8370 ? constm1_rtx : const0_rtx);
8373 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8375 output_mov_immediate (otherops);
8376 output_mov_immediate (operands);
8378 else if (code1 == MEM)
8380 switch (GET_CODE (XEXP (operands[1], 0)))
8383 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8388 abort (); /* Should never happen now. */
8389 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8393 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8397 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8402 abort (); /* Should never happen now. */
8403 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8408 otherops[0] = operands[0];
8409 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8410 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8412 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8414 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8416 /* Registers overlap so split out the increment. */
8417 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8418 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8421 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8425 /* We only allow constant increments, so this is safe. */
8426 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8432 output_asm_insn ("adr%?\t%0, %1", operands);
8433 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8437 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8438 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8440 otherops[0] = operands[0];
8441 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8442 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8444 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8446 if (GET_CODE (otherops[2]) == CONST_INT)
8448 switch ((int) INTVAL (otherops[2]))
8451 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8454 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8457 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8462 && (GET_CODE (otherops[2]) == REG
8463 || (GET_CODE (otherops[2]) == CONST_INT
8464 && INTVAL (otherops[2]) > -256
8465 && INTVAL (otherops[2]) < 256)))
8467 if (reg_overlap_mentioned_p (otherops[0],
8470 /* Swap base and index registers over to
8471 avoid a conflict. */
8472 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8473 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8476 /* If both registers conflict, it will usually
8477 have been fixed by a splitter. */
8478 if (reg_overlap_mentioned_p (otherops[0],
8481 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8482 output_asm_insn ("ldr%?d\t%0, [%1]",
8488 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8493 if (GET_CODE (otherops[2]) == CONST_INT)
8495 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8496 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8498 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8501 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8504 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8506 return "ldm%?ia\t%0, %M0";
8510 otherops[1] = adjust_address (operands[1], SImode, 4);
8511 /* Take care of overlapping base/data reg. */
8512 if (reg_mentioned_p (operands[0], operands[1]))
8514 output_asm_insn ("ldr%?\t%0, %1", otherops);
8515 output_asm_insn ("ldr%?\t%0, %1", operands);
8519 output_asm_insn ("ldr%?\t%0, %1", operands);
8520 output_asm_insn ("ldr%?\t%0, %1", otherops);
8526 abort (); /* Constraints should prevent this. */
8528 else if (code0 == MEM && code1 == REG)
8530 if (REGNO (operands[1]) == IP_REGNUM)
8533 switch (GET_CODE (XEXP (operands[0], 0)))
8536 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8541 abort (); /* Should never happen now. */
8542 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8546 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8550 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8555 abort (); /* Should never happen now. */
8556 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8561 otherops[0] = operands[1];
8562 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8563 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8565 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8566 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8568 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8572 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8573 if (GET_CODE (otherops[2]) == CONST_INT)
8575 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8578 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8582 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8586 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8591 && (GET_CODE (otherops[2]) == REG
8592 || (GET_CODE (otherops[2]) == CONST_INT
8593 && INTVAL (otherops[2]) > -256
8594 && INTVAL (otherops[2]) < 256)))
8596 otherops[0] = operands[1];
8597 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8598 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8604 otherops[0] = adjust_address (operands[0], SImode, 4);
8605 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8606 output_asm_insn ("str%?\t%1, %0", operands);
8607 output_asm_insn ("str%?\t%1, %0", otherops);
8611 /* Constraints should prevent this. */
8618 /* Output an arbitrary MOV reg, #n.
8619 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8621 output_mov_immediate (rtx *operands)
8623 HOST_WIDE_INT n = INTVAL (operands[1]);
8625 /* Try to use one MOV. */
8626 if (const_ok_for_arm (n))
8627 output_asm_insn ("mov%?\t%0, %1", operands);
8629 /* Try to use one MVN. */
8630 else if (const_ok_for_arm (~n))
8632 operands[1] = GEN_INT (~n);
8633 output_asm_insn ("mvn%?\t%0, %1", operands);
8640 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8641 for (i = 0; i < 32; i++)
8645 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8646 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8648 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8654 /* Output an ADD r, s, #n where n may be too big for one instruction.
8655 If adding zero to one register, output nothing. */
8657 output_add_immediate (rtx *operands)
8659 HOST_WIDE_INT n = INTVAL (operands[2]);
8661 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8664 output_multi_immediate (operands,
8665 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8668 output_multi_immediate (operands,
8669 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8676 /* Output a multiple immediate operation.
8677 OPERANDS is the vector of operands referred to in the output patterns.
8678 INSTR1 is the output pattern to use for the first constant.
8679 INSTR2 is the output pattern to use for subsequent constants.
8680 IMMED_OP is the index of the constant slot in OPERANDS.
8681 N is the constant value. */
8683 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8684 int immed_op, HOST_WIDE_INT n)
8686 #if HOST_BITS_PER_WIDE_INT > 32
8692 /* Quick and easy output. */
8693 operands[immed_op] = const0_rtx;
8694 output_asm_insn (instr1, operands);
8699 const char * instr = instr1;
8701 /* Note that n is never zero here (which would give no output). */
8702 for (i = 0; i < 32; i += 2)
8706 operands[immed_op] = GEN_INT (n & (255 << i));
8707 output_asm_insn (instr, operands);
8717 /* Return the appropriate ARM instruction for the operation code.
8718 The returned result should not be overwritten. OP is the rtx of the
8719 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8722 arithmetic_instr (rtx op, int shift_first_arg)
8724 switch (GET_CODE (op))
8730 return shift_first_arg ? "rsb" : "sub";
8746 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8747 for the operation code. The returned result should not be overwritten.
8748 OP is the rtx code of the shift.
8749 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8752 shift_op (rtx op, HOST_WIDE_INT *amountp)
8755 enum rtx_code code = GET_CODE (op);
8757 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8759 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8760 *amountp = INTVAL (XEXP (op, 1));
8783 /* We never have to worry about the amount being other than a
8784 power of 2, since this case can never be reloaded from a reg. */
8786 *amountp = int_log2 (*amountp);
8797 /* This is not 100% correct, but follows from the desire to merge
8798 multiplication by a power of 2 with the recognizer for a
8799 shift. >=32 is not a valid shift for "asl", so we must try and
8800 output a shift that produces the correct arithmetical result.
8801 Using lsr #32 is identical except for the fact that the carry bit
8802 is not set correctly if we set the flags; but we never use the
8803 carry bit from such an operation, so we can ignore that. */
8804 if (code == ROTATERT)
8805 /* Rotate is just modulo 32. */
8807 else if (*amountp != (*amountp & 31))
8814 /* Shifts of 0 are no-ops. */
8822 /* Obtain the shift from the POWER of two. */
8824 static HOST_WIDE_INT
8825 int_log2 (HOST_WIDE_INT power)
8827 HOST_WIDE_INT shift = 0;
8829 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8839 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8840 /bin/as is horribly restrictive. */
8841 #define MAX_ASCII_LEN 51
8844 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8849 fputs ("\t.ascii\t\"", stream);
8851 for (i = 0; i < len; i++)
8855 if (len_so_far >= MAX_ASCII_LEN)
8857 fputs ("\"\n\t.ascii\t\"", stream);
8864 fputs ("\\t", stream);
8869 fputs ("\\f", stream);
8874 fputs ("\\b", stream);
8879 fputs ("\\r", stream);
8883 case TARGET_NEWLINE:
8884 fputs ("\\n", stream);
8886 if ((c >= ' ' && c <= '~')
8888 /* This is a good place for a line break. */
8889 len_so_far = MAX_ASCII_LEN;
8896 putc ('\\', stream);
8901 if (c >= ' ' && c <= '~')
8908 fprintf (stream, "\\%03o", c);
8915 fputs ("\"\n", stream);
8918 /* Compute the register sabe mask for registers 0 through 12
8919 inclusive. This code is used by arm_compute_save_reg_mask. */
8920 static unsigned long
8921 arm_compute_save_reg0_reg12_mask (void)
8923 unsigned long func_type = arm_current_func_type ();
8924 unsigned int save_reg_mask = 0;
8927 if (IS_INTERRUPT (func_type))
8929 unsigned int max_reg;
8930 /* Interrupt functions must not corrupt any registers,
8931 even call clobbered ones. If this is a leaf function
8932 we can just examine the registers used by the RTL, but
8933 otherwise we have to assume that whatever function is
8934 called might clobber anything, and so we have to save
8935 all the call-clobbered registers as well. */
8936 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8937 /* FIQ handlers have registers r8 - r12 banked, so
8938 we only need to check r0 - r7, Normal ISRs only
8939 bank r14 and r15, so we must check up to r12.
8940 r13 is the stack pointer which is always preserved,
8941 so we do not need to consider it here. */
8946 for (reg = 0; reg <= max_reg; reg++)
8947 if (regs_ever_live[reg]
8948 || (! current_function_is_leaf && call_used_regs [reg]))
8949 save_reg_mask |= (1 << reg);
8953 /* In the normal case we only need to save those registers
8954 which are call saved and which are used by this function. */
8955 for (reg = 0; reg <= 10; reg++)
8956 if (regs_ever_live[reg] && ! call_used_regs [reg])
8957 save_reg_mask |= (1 << reg);
8959 /* Handle the frame pointer as a special case. */
8960 if (! TARGET_APCS_FRAME
8961 && ! frame_pointer_needed
8962 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8963 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8964 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8966 /* If we aren't loading the PIC register,
8967 don't stack it even though it may be live. */
8969 && ! TARGET_SINGLE_PIC_BASE
8970 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8971 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8974 return save_reg_mask;
8977 /* Compute a bit mask of which registers need to be
8978 saved on the stack for the current function. */
8980 static unsigned long
8981 arm_compute_save_reg_mask (void)
8983 unsigned int save_reg_mask = 0;
8984 unsigned long func_type = arm_current_func_type ();
8986 if (IS_NAKED (func_type))
8987 /* This should never really happen. */
8990 /* If we are creating a stack frame, then we must save the frame pointer,
8991 IP (which will hold the old stack pointer), LR and the PC. */
8992 if (frame_pointer_needed)
8994 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8999 /* Volatile functions do not return, so there
9000 is no need to save any other registers. */
9001 if (IS_VOLATILE (func_type))
9002 return save_reg_mask;
9004 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9006 /* Decide if we need to save the link register.
9007 Interrupt routines have their own banked link register,
9008 so they never need to save it.
9009 Otherwise if we do not use the link register we do not need to save
9010 it. If we are pushing other registers onto the stack however, we
9011 can save an instruction in the epilogue by pushing the link register
9012 now and then popping it back into the PC. This incurs extra memory
9013 accesses though, so we only do it when optimizing for size, and only
9014 if we know that we will not need a fancy return sequence. */
9015 if (regs_ever_live [LR_REGNUM]
9018 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
9019 save_reg_mask |= 1 << LR_REGNUM;
9021 if (cfun->machine->lr_save_eliminated)
9022 save_reg_mask &= ~ (1 << LR_REGNUM);
9024 if (TARGET_REALLY_IWMMXT
9025 && ((bit_count (save_reg_mask)
9026 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9030 /* The total number of registers that are going to be pushed
9031 onto the stack is odd. We need to ensure that the stack
9032 is 64-bit aligned before we start to save iWMMXt registers,
9033 and also before we start to create locals. (A local variable
9034 might be a double or long long which we will load/store using
9035 an iWMMXt instruction). Therefore we need to push another
9036 ARM register, so that the stack will be 64-bit aligned. We
9037 try to avoid using the arg registers (r0 -r3) as they might be
9038 used to pass values in a tail call. */
9039 for (reg = 4; reg <= 12; reg++)
9040 if ((save_reg_mask & (1 << reg)) == 0)
9044 save_reg_mask |= (1 << reg);
9047 cfun->machine->sibcall_blocked = 1;
9048 save_reg_mask |= (1 << 3);
9052 return save_reg_mask;
9056 /* Return the number of bytes required to save VFP registers. */
9058 arm_get_vfp_saved_size (void)
9065 /* Space for saved VFP registers. */
9066 if (TARGET_HARD_FLOAT && TARGET_VFP)
9069 for (regno = FIRST_VFP_REGNUM;
9070 regno < LAST_VFP_REGNUM;
9073 if ((!regs_ever_live[regno] || call_used_regs[regno])
9074 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9078 /* Workaround ARM10 VFPr1 bug. */
9079 if (count == 2 && !arm_arch6)
9081 saved += count * 8 + 4;
9090 if (count == 2 && !arm_arch6)
9092 saved += count * 8 + 4;
9099 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9100 everything bar the final return instruction. */
9102 output_return_instruction (rtx operand, int really_return, int reverse)
9104 char conditional[10];
9107 unsigned long live_regs_mask;
9108 unsigned long func_type;
9109 arm_stack_offsets *offsets;
9111 func_type = arm_current_func_type ();
9113 if (IS_NAKED (func_type))
9116 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9118 /* If this function was declared non-returning, and we have
9119 found a tail call, then we have to trust that the called
9120 function won't return. */
9125 /* Otherwise, trap an attempted return by aborting. */
9127 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9129 assemble_external_libcall (ops[1]);
9130 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9136 if (current_function_calls_alloca && !really_return)
9139 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9141 return_used_this_function = 1;
9143 live_regs_mask = arm_compute_save_reg_mask ();
9147 const char * return_reg;
9149 /* If we do not have any special requirements for function exit
9150 (eg interworking, or ISR) then we can load the return address
9151 directly into the PC. Otherwise we must load it into LR. */
9153 && ! TARGET_INTERWORK)
9154 return_reg = reg_names[PC_REGNUM];
9156 return_reg = reg_names[LR_REGNUM];
9158 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9160 /* There are three possible reasons for the IP register
9161 being saved. 1) a stack frame was created, in which case
9162 IP contains the old stack pointer, or 2) an ISR routine
9163 corrupted it, or 3) it was saved to align the stack on
9164 iWMMXt. In case 1, restore IP into SP, otherwise just
9166 if (frame_pointer_needed)
9168 live_regs_mask &= ~ (1 << IP_REGNUM);
9169 live_regs_mask |= (1 << SP_REGNUM);
9173 if (! IS_INTERRUPT (func_type)
9174 && ! TARGET_REALLY_IWMMXT)
9179 /* On some ARM architectures it is faster to use LDR rather than
9180 LDM to load a single register. On other architectures, the
9181 cost is the same. In 26 bit mode, or for exception handlers,
9182 we have to use LDM to load the PC so that the CPSR is also
9184 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9186 if (live_regs_mask == (unsigned int)(1 << reg))
9189 if (reg <= LAST_ARM_REGNUM
9190 && (reg != LR_REGNUM
9192 || ! IS_INTERRUPT (func_type)))
9194 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9195 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9202 /* Generate the load multiple instruction to restore the
9203 registers. Note we can get here, even if
9204 frame_pointer_needed is true, but only if sp already
9205 points to the base of the saved core registers. */
9206 if (live_regs_mask & (1 << SP_REGNUM))
9208 unsigned HOST_WIDE_INT stack_adjust;
9210 offsets = arm_get_frame_offsets ();
9211 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9212 if (stack_adjust != 0 && stack_adjust != 4)
9215 if (stack_adjust && arm_arch5)
9216 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9219 /* If we can't use ldmib (SA110 bug), then try to pop r3
9222 live_regs_mask |= 1 << 3;
9223 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9227 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9229 p = instr + strlen (instr);
9231 for (reg = 0; reg <= SP_REGNUM; reg++)
9232 if (live_regs_mask & (1 << reg))
9234 int l = strlen (reg_names[reg]);
9240 memcpy (p, ", ", 2);
9244 memcpy (p, "%|", 2);
9245 memcpy (p + 2, reg_names[reg], l);
9249 if (live_regs_mask & (1 << LR_REGNUM))
9251 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9252 /* If returning from an interrupt, restore the CPSR. */
9253 if (IS_INTERRUPT (func_type))
9260 output_asm_insn (instr, & operand);
9262 /* See if we need to generate an extra instruction to
9263 perform the actual function return. */
9265 && func_type != ARM_FT_INTERWORKED
9266 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9268 /* The return has already been handled
9269 by loading the LR into the PC. */
9276 switch ((int) ARM_FUNC_TYPE (func_type))
9280 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9283 case ARM_FT_INTERWORKED:
9284 sprintf (instr, "bx%s\t%%|lr", conditional);
9287 case ARM_FT_EXCEPTION:
9288 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9292 /* Use bx if it's available. */
9293 if (arm_arch5 || arm_arch4t)
9294 sprintf (instr, "bx%s\t%%|lr", conditional);
9296 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9300 output_asm_insn (instr, & operand);
9306 /* Write the function name into the code section, directly preceding
9307 the function prologue.
9309 Code will be output similar to this:
9311 .ascii "arm_poke_function_name", 0
9314 .word 0xff000000 + (t1 - t0)
9315 arm_poke_function_name
9317 stmfd sp!, {fp, ip, lr, pc}
9320 When performing a stack backtrace, code can inspect the value
9321 of 'pc' stored at 'fp' + 0. If the trace function then looks
9322 at location pc - 12 and the top 8 bits are set, then we know
9323 that there is a function name embedded immediately preceding this
9324 location and has length ((pc[-3]) & 0xff000000).
9326 We assume that pc is declared as a pointer to an unsigned long.
9328 It is of no benefit to output the function name if we are assembling
9329 a leaf function. These function types will not contain a stack
9330 backtrace structure, therefore it is not possible to determine the
9333 arm_poke_function_name (FILE *stream, const char *name)
9335 unsigned long alignlength;
9336 unsigned long length;
9339 length = strlen (name) + 1;
9340 alignlength = ROUND_UP_WORD (length);
9342 ASM_OUTPUT_ASCII (stream, name, length);
9343 ASM_OUTPUT_ALIGN (stream, 2);
9344 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9345 assemble_aligned_integer (UNITS_PER_WORD, x);
9348 /* Place some comments into the assembler stream
9349 describing the current function. */
9351 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9353 unsigned long func_type;
9357 thumb_output_function_prologue (f, frame_size);
9362 if (arm_ccfsm_state || arm_target_insn)
9365 func_type = arm_current_func_type ();
9367 switch ((int) ARM_FUNC_TYPE (func_type))
9372 case ARM_FT_INTERWORKED:
9373 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9375 case ARM_FT_EXCEPTION_HANDLER:
9376 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9379 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9382 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9384 case ARM_FT_EXCEPTION:
9385 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9389 if (IS_NAKED (func_type))
9390 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9392 if (IS_VOLATILE (func_type))
9393 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9395 if (IS_NESTED (func_type))
9396 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9398 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9399 current_function_args_size,
9400 current_function_pretend_args_size, frame_size);
9402 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9403 frame_pointer_needed,
9404 cfun->machine->uses_anonymous_args);
9406 if (cfun->machine->lr_save_eliminated)
9407 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9409 #ifdef AOF_ASSEMBLER
9411 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9414 return_used_this_function = 0;
9418 arm_output_epilogue (rtx sibling)
9421 unsigned long saved_regs_mask;
9422 unsigned long func_type;
9423 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9424 frame that is $fp + 4 for a non-variadic function. */
9425 int floats_offset = 0;
9427 FILE * f = asm_out_file;
9428 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9429 unsigned int lrm_count = 0;
9430 int really_return = (sibling == NULL);
9432 arm_stack_offsets *offsets;
9434 /* If we have already generated the return instruction
9435 then it is futile to generate anything else. */
9436 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9439 func_type = arm_current_func_type ();
9441 if (IS_NAKED (func_type))
9442 /* Naked functions don't have epilogues. */
9445 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9449 /* A volatile function should never return. Call abort. */
9450 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9451 assemble_external_libcall (op);
9452 output_asm_insn ("bl\t%a0", &op);
9457 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9459 /* If we are throwing an exception, then we really must
9460 be doing a return, so we can't tail-call. */
9463 offsets = arm_get_frame_offsets ();
9464 saved_regs_mask = arm_compute_save_reg_mask ();
9467 lrm_count = bit_count (saved_regs_mask);
9469 floats_offset = offsets->saved_args;
9470 /* Compute how far away the floats will be. */
9471 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9472 if (saved_regs_mask & (1 << reg))
9475 if (frame_pointer_needed)
9477 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9478 int vfp_offset = offsets->frame;
9480 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9482 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9483 if (regs_ever_live[reg] && !call_used_regs[reg])
9485 floats_offset += 12;
9486 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9487 reg, FP_REGNUM, floats_offset - vfp_offset);
9492 start_reg = LAST_FPA_REGNUM;
9494 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9496 if (regs_ever_live[reg] && !call_used_regs[reg])
9498 floats_offset += 12;
9500 /* We can't unstack more than four registers at once. */
9501 if (start_reg - reg == 3)
9503 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9504 reg, FP_REGNUM, floats_offset - vfp_offset);
9505 start_reg = reg - 1;
9510 if (reg != start_reg)
9511 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9512 reg + 1, start_reg - reg,
9513 FP_REGNUM, floats_offset - vfp_offset);
9514 start_reg = reg - 1;
9518 /* Just in case the last register checked also needs unstacking. */
9519 if (reg != start_reg)
9520 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9521 reg + 1, start_reg - reg,
9522 FP_REGNUM, floats_offset - vfp_offset);
9525 if (TARGET_HARD_FLOAT && TARGET_VFP)
9529 /* The fldmx insn does not have base+offset addressing modes,
9530 so we use IP to hold the address. */
9531 saved_size = arm_get_vfp_saved_size ();
9535 floats_offset += saved_size;
9536 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9537 FP_REGNUM, floats_offset - vfp_offset);
9539 start_reg = FIRST_VFP_REGNUM;
9540 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9542 if ((!regs_ever_live[reg] || call_used_regs[reg])
9543 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9545 if (start_reg != reg)
9546 arm_output_fldmx (f, IP_REGNUM,
9547 (start_reg - FIRST_VFP_REGNUM) / 2,
9548 (reg - start_reg) / 2);
9549 start_reg = reg + 2;
9552 if (start_reg != reg)
9553 arm_output_fldmx (f, IP_REGNUM,
9554 (start_reg - FIRST_VFP_REGNUM) / 2,
9555 (reg - start_reg) / 2);
9560 /* The frame pointer is guaranteed to be non-double-word aligned.
9561 This is because it is set to (old_stack_pointer - 4) and the
9562 old_stack_pointer was double word aligned. Thus the offset to
9563 the iWMMXt registers to be loaded must also be non-double-word
9564 sized, so that the resultant address *is* double-word aligned.
9565 We can ignore floats_offset since that was already included in
9566 the live_regs_mask. */
9567 lrm_count += (lrm_count % 2 ? 2 : 1);
9569 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9570 if (regs_ever_live[reg] && !call_used_regs[reg])
9572 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9573 reg, FP_REGNUM, lrm_count * 4);
9578 /* saved_regs_mask should contain the IP, which at the time of stack
9579 frame generation actually contains the old stack pointer. So a
9580 quick way to unwind the stack is just pop the IP register directly
9581 into the stack pointer. */
9582 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9584 saved_regs_mask &= ~ (1 << IP_REGNUM);
9585 saved_regs_mask |= (1 << SP_REGNUM);
9587 /* There are two registers left in saved_regs_mask - LR and PC. We
9588 only need to restore the LR register (the return address), but to
9589 save time we can load it directly into the PC, unless we need a
9590 special function exit sequence, or we are not really returning. */
9591 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9592 /* Delete the LR from the register mask, so that the LR on
9593 the stack is loaded into the PC in the register mask. */
9594 saved_regs_mask &= ~ (1 << LR_REGNUM);
9596 saved_regs_mask &= ~ (1 << PC_REGNUM);
9598 /* We must use SP as the base register, because SP is one of the
9599 registers being restored. If an interrupt or page fault
9600 happens in the ldm instruction, the SP might or might not
9601 have been restored. That would be bad, as then SP will no
9602 longer indicate the safe area of stack, and we can get stack
9603 corruption. Using SP as the base register means that it will
9604 be reset correctly to the original value, should an interrupt
9605 occur. If the stack pointer already points at the right
9606 place, then omit the subtraction. */
9607 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9608 || current_function_calls_alloca)
9609 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9610 4 * bit_count (saved_regs_mask));
9611 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9613 if (IS_INTERRUPT (func_type))
9614 /* Interrupt handlers will have pushed the
9615 IP onto the stack, so restore it now. */
9616 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9620 /* Restore stack pointer if necessary. */
9621 if (offsets->outgoing_args != offsets->saved_regs)
9623 operands[0] = operands[1] = stack_pointer_rtx;
9624 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9625 output_add_immediate (operands);
9628 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9630 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9631 if (regs_ever_live[reg] && !call_used_regs[reg])
9632 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9637 start_reg = FIRST_FPA_REGNUM;
9639 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9641 if (regs_ever_live[reg] && !call_used_regs[reg])
9643 if (reg - start_reg == 3)
9645 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9646 start_reg, SP_REGNUM);
9647 start_reg = reg + 1;
9652 if (reg != start_reg)
9653 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9654 start_reg, reg - start_reg,
9657 start_reg = reg + 1;
9661 /* Just in case the last register checked also needs unstacking. */
9662 if (reg != start_reg)
9663 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9664 start_reg, reg - start_reg, SP_REGNUM);
9667 if (TARGET_HARD_FLOAT && TARGET_VFP)
9669 start_reg = FIRST_VFP_REGNUM;
9670 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9672 if ((!regs_ever_live[reg] || call_used_regs[reg])
9673 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9675 if (start_reg != reg)
9676 arm_output_fldmx (f, SP_REGNUM,
9677 (start_reg - FIRST_VFP_REGNUM) / 2,
9678 (reg - start_reg) / 2);
9679 start_reg = reg + 2;
9682 if (start_reg != reg)
9683 arm_output_fldmx (f, SP_REGNUM,
9684 (start_reg - FIRST_VFP_REGNUM) / 2,
9685 (reg - start_reg) / 2);
9688 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9689 if (regs_ever_live[reg] && !call_used_regs[reg])
9690 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9692 /* If we can, restore the LR into the PC. */
9693 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9695 && current_function_pretend_args_size == 0
9696 && saved_regs_mask & (1 << LR_REGNUM))
9698 saved_regs_mask &= ~ (1 << LR_REGNUM);
9699 saved_regs_mask |= (1 << PC_REGNUM);
9702 /* Load the registers off the stack. If we only have one register
9703 to load use the LDR instruction - it is faster. */
9704 if (saved_regs_mask == (1 << LR_REGNUM))
9706 /* The exception handler ignores the LR, so we do
9707 not really need to load it off the stack. */
9709 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9711 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9713 else if (saved_regs_mask)
9715 if (saved_regs_mask & (1 << SP_REGNUM))
9716 /* Note - write back to the stack register is not enabled
9717 (ie "ldmfd sp!..."). We know that the stack pointer is
9718 in the list of registers and if we add writeback the
9719 instruction becomes UNPREDICTABLE. */
9720 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9722 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9725 if (current_function_pretend_args_size)
9727 /* Unwind the pre-pushed regs. */
9728 operands[0] = operands[1] = stack_pointer_rtx;
9729 operands[2] = GEN_INT (current_function_pretend_args_size);
9730 output_add_immediate (operands);
9734 /* We may have already restored PC directly from the stack. */
9735 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9738 /* Generate the return instruction. */
9739 switch ((int) ARM_FUNC_TYPE (func_type))
9741 case ARM_FT_EXCEPTION_HANDLER:
9742 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9747 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9750 case ARM_FT_EXCEPTION:
9751 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9754 case ARM_FT_INTERWORKED:
9755 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9759 if (arm_arch5 || arm_arch4t)
9760 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9762 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9770 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9771 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9773 arm_stack_offsets *offsets;
9777 /* ??? Probably not safe to set this here, since it assumes that a
9778 function will be emitted as assembly immediately after we generate
9779 RTL for it. This does not happen for inline functions. */
9780 return_used_this_function = 0;
9784 /* We need to take into account any stack-frame rounding. */
9785 offsets = arm_get_frame_offsets ();
9787 if (use_return_insn (FALSE, NULL)
9788 && return_used_this_function
9789 && offsets->saved_regs != offsets->outgoing_args
9790 && !frame_pointer_needed)
9793 /* Reset the ARM-specific per-function variables. */
9794 after_arm_reorg = 0;
9798 /* Generate and emit an insn that we will recognize as a push_multi.
9799 Unfortunately, since this insn does not reflect very well the actual
9800 semantics of the operation, we need to annotate the insn for the benefit
9801 of DWARF2 frame unwind information. */
9803 emit_multi_reg_push (int mask)
9810 int dwarf_par_index;
9813 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9814 if (mask & (1 << i))
9817 if (num_regs == 0 || num_regs > 16)
9820 /* We don't record the PC in the dwarf frame information. */
9821 num_dwarf_regs = num_regs;
9822 if (mask & (1 << PC_REGNUM))
9825 /* For the body of the insn we are going to generate an UNSPEC in
9826 parallel with several USEs. This allows the insn to be recognized
9827 by the push_multi pattern in the arm.md file. The insn looks
9828 something like this:
9831 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9832 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9833 (use (reg:SI 11 fp))
9834 (use (reg:SI 12 ip))
9835 (use (reg:SI 14 lr))
9836 (use (reg:SI 15 pc))
9839 For the frame note however, we try to be more explicit and actually
9840 show each register being stored into the stack frame, plus a (single)
9841 decrement of the stack pointer. We do it this way in order to be
9842 friendly to the stack unwinding code, which only wants to see a single
9843 stack decrement per instruction. The RTL we generate for the note looks
9844 something like this:
9847 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9848 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9849 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9850 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9851 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9854 This sequence is used both by the code to support stack unwinding for
9855 exceptions handlers and the code to generate dwarf2 frame debugging. */
9857 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9858 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9859 dwarf_par_index = 1;
9861 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9863 if (mask & (1 << i))
9865 reg = gen_rtx_REG (SImode, i);
9868 = gen_rtx_SET (VOIDmode,
9869 gen_rtx_MEM (BLKmode,
9870 gen_rtx_PRE_DEC (BLKmode,
9871 stack_pointer_rtx)),
9872 gen_rtx_UNSPEC (BLKmode,
9878 tmp = gen_rtx_SET (VOIDmode,
9879 gen_rtx_MEM (SImode, stack_pointer_rtx),
9881 RTX_FRAME_RELATED_P (tmp) = 1;
9882 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9890 for (j = 1, i++; j < num_regs; i++)
9892 if (mask & (1 << i))
9894 reg = gen_rtx_REG (SImode, i);
9896 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9900 tmp = gen_rtx_SET (VOIDmode,
9901 gen_rtx_MEM (SImode,
9902 plus_constant (stack_pointer_rtx,
9905 RTX_FRAME_RELATED_P (tmp) = 1;
9906 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9913 par = emit_insn (par);
9915 tmp = gen_rtx_SET (SImode,
9917 gen_rtx_PLUS (SImode,
9919 GEN_INT (-4 * num_regs)));
9920 RTX_FRAME_RELATED_P (tmp) = 1;
9921 XVECEXP (dwarf, 0, 0) = tmp;
9923 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9929 emit_sfm (int base_reg, int count)
9936 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9937 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9939 reg = gen_rtx_REG (XFmode, base_reg++);
9942 = gen_rtx_SET (VOIDmode,
9943 gen_rtx_MEM (BLKmode,
9944 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9945 gen_rtx_UNSPEC (BLKmode,
9949 = gen_rtx_SET (VOIDmode,
9950 gen_rtx_MEM (XFmode,
9951 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9953 RTX_FRAME_RELATED_P (tmp) = 1;
9954 XVECEXP (dwarf, 0, count - 1) = tmp;
9956 for (i = 1; i < count; i++)
9958 reg = gen_rtx_REG (XFmode, base_reg++);
9959 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9961 tmp = gen_rtx_SET (VOIDmode,
9962 gen_rtx_MEM (XFmode,
9963 gen_rtx_PRE_DEC (BLKmode,
9964 stack_pointer_rtx)),
9966 RTX_FRAME_RELATED_P (tmp) = 1;
9967 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9970 par = emit_insn (par);
9971 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9977 /* Return true if the current function needs to save/restore LR. */
9980 thumb_force_lr_save (void)
9982 return !cfun->machine->lr_save_eliminated
9983 && (!leaf_function_p ()
9984 || thumb_far_jump_used_p ()
9985 || regs_ever_live [LR_REGNUM]);
9989 /* Compute the distance from register FROM to register TO.
9990 These can be the arg pointer (26), the soft frame pointer (25),
9991 the stack pointer (13) or the hard frame pointer (11).
9992 Typical stack layout looks like this:
9994 old stack pointer -> | |
9997 | | saved arguments for
9998 | | vararg functions
10001 hard FP & arg pointer -> | | \
10009 soft frame pointer -> | | /
10019 current stack pointer -> | | /
10022 For a given function some or all of these stack components
10023 may not be needed, giving rise to the possibility of
10024 eliminating some of the registers.
10026 The values returned by this function must reflect the behavior
10027 of arm_expand_prologue() and arm_compute_save_reg_mask().
10029 The sign of the number returned reflects the direction of stack
10030 growth, so the values are positive for all eliminations except
10031 from the soft frame pointer to the hard frame pointer.
10033 SFP may point just inside the local variables block to ensure correct
10037 /* Calculate stack offsets. These are used to calculate register elimination
10038 offsets and in prologue/epilogue code. */
10040 static arm_stack_offsets *
10041 arm_get_frame_offsets (void)
10043 struct arm_stack_offsets *offsets;
10044 unsigned long func_type;
10047 HOST_WIDE_INT frame_size;
10049 offsets = &cfun->machine->stack_offsets;
10051 /* We need to know if we are a leaf function. Unfortunately, it
10052 is possible to be called after start_sequence has been called,
10053 which causes get_insns to return the insns for the sequence,
10054 not the function, which will cause leaf_function_p to return
10055 the incorrect result.
10057 to know about leaf functions once reload has completed, and the
10058 frame size cannot be changed after that time, so we can safely
10059 use the cached value. */
10061 if (reload_completed)
10064 /* Initially this is the size of the local variables. It will translated
10065 into an offset once we have determined the size of preceding data. */
10066 frame_size = ROUND_UP_WORD (get_frame_size ());
10068 leaf = leaf_function_p ();
10070 /* Space for variadic functions. */
10071 offsets->saved_args = current_function_pretend_args_size;
10073 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10077 unsigned int regno;
10079 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10081 /* We know that SP will be doubleword aligned on entry, and we must
10082 preserve that condition at any subroutine call. We also require the
10083 soft frame pointer to be doubleword aligned. */
10085 if (TARGET_REALLY_IWMMXT)
10087 /* Check for the call-saved iWMMXt registers. */
10088 for (regno = FIRST_IWMMXT_REGNUM;
10089 regno <= LAST_IWMMXT_REGNUM;
10091 if (regs_ever_live [regno] && ! call_used_regs [regno])
10095 func_type = arm_current_func_type ();
10096 if (! IS_VOLATILE (func_type))
10098 /* Space for saved FPA registers. */
10099 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10100 if (regs_ever_live[regno] && ! call_used_regs[regno])
10103 /* Space for saved VFP registers. */
10104 if (TARGET_HARD_FLOAT && TARGET_VFP)
10105 saved += arm_get_vfp_saved_size ();
10108 else /* TARGET_THUMB */
10115 for (reg = 8; reg < 13; reg ++)
10116 if (THUMB_REG_PUSHED_P (reg))
10119 saved += 4 * count_regs;
10121 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10122 if (THUMB_REG_PUSHED_P (reg))
10124 if (count_regs || thumb_force_lr_save ())
10125 saved += 4 * (count_regs + 1);
10126 if (TARGET_BACKTRACE)
10128 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10135 /* Saved registers include the stack frame. */
10136 offsets->saved_regs = offsets->saved_args + saved;
10137 offsets->soft_frame = offsets->saved_regs;
10138 /* A leaf function does not need any stack alignment if it has nothing
10140 if (leaf && frame_size == 0)
10142 offsets->outgoing_args = offsets->soft_frame;
10146 /* Ensure SFP has the correct alignment. */
10147 if (ARM_DOUBLEWORD_ALIGN
10148 && (offsets->soft_frame & 7))
10149 offsets->soft_frame += 4;
10151 offsets->outgoing_args = offsets->soft_frame + frame_size
10152 + current_function_outgoing_args_size;
10154 if (ARM_DOUBLEWORD_ALIGN)
10156 /* Ensure SP remains doubleword aligned. */
10157 if (offsets->outgoing_args & 7)
10158 offsets->outgoing_args += 4;
10159 if (offsets->outgoing_args & 7)
10167 /* Calculate the relative offsets for the different stack pointers. Positive
10168 offsets are in the direction of stack growth. */
10171 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10173 arm_stack_offsets *offsets;
10175 offsets = arm_get_frame_offsets ();
10177 /* OK, now we have enough information to compute the distances.
10178 There must be an entry in these switch tables for each pair
10179 of registers in ELIMINABLE_REGS, even if some of the entries
10180 seem to be redundant or useless. */
10183 case ARG_POINTER_REGNUM:
10186 case THUMB_HARD_FRAME_POINTER_REGNUM:
10189 case FRAME_POINTER_REGNUM:
10190 /* This is the reverse of the soft frame pointer
10191 to hard frame pointer elimination below. */
10192 return offsets->soft_frame - offsets->saved_args;
10194 case ARM_HARD_FRAME_POINTER_REGNUM:
10195 /* If there is no stack frame then the hard
10196 frame pointer and the arg pointer coincide. */
10197 if (offsets->frame == offsets->saved_regs)
10199 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10200 return (frame_pointer_needed
10201 && cfun->static_chain_decl != NULL
10202 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10204 case STACK_POINTER_REGNUM:
10205 /* If nothing has been pushed on the stack at all
10206 then this will return -4. This *is* correct! */
10207 return offsets->outgoing_args - (offsets->saved_args + 4);
10214 case FRAME_POINTER_REGNUM:
10217 case THUMB_HARD_FRAME_POINTER_REGNUM:
10220 case ARM_HARD_FRAME_POINTER_REGNUM:
10221 /* The hard frame pointer points to the top entry in the
10222 stack frame. The soft frame pointer to the bottom entry
10223 in the stack frame. If there is no stack frame at all,
10224 then they are identical. */
10226 return offsets->frame - offsets->soft_frame;
10228 case STACK_POINTER_REGNUM:
10229 return offsets->outgoing_args - offsets->soft_frame;
10237 /* You cannot eliminate from the stack pointer.
10238 In theory you could eliminate from the hard frame
10239 pointer to the stack pointer, but this will never
10240 happen, since if a stack frame is not needed the
10241 hard frame pointer will never be used. */
10247 /* Generate the prologue instructions for entry into an ARM function. */
10249 arm_expand_prologue (void)
10255 unsigned long live_regs_mask;
10256 unsigned long func_type;
10258 int saved_pretend_args = 0;
10259 int saved_regs = 0;
10260 unsigned int args_to_push;
10261 arm_stack_offsets *offsets;
10263 func_type = arm_current_func_type ();
10265 /* Naked functions don't have prologues. */
10266 if (IS_NAKED (func_type))
10269 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10270 args_to_push = current_function_pretend_args_size;
10272 /* Compute which register we will have to save onto the stack. */
10273 live_regs_mask = arm_compute_save_reg_mask ();
10275 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10277 if (frame_pointer_needed)
10279 if (IS_INTERRUPT (func_type))
10281 /* Interrupt functions must not corrupt any registers.
10282 Creating a frame pointer however, corrupts the IP
10283 register, so we must push it first. */
10284 insn = emit_multi_reg_push (1 << IP_REGNUM);
10286 /* Do not set RTX_FRAME_RELATED_P on this insn.
10287 The dwarf stack unwinding code only wants to see one
10288 stack decrement per function, and this is not it. If
10289 this instruction is labeled as being part of the frame
10290 creation sequence then dwarf2out_frame_debug_expr will
10291 abort when it encounters the assignment of IP to FP
10292 later on, since the use of SP here establishes SP as
10293 the CFA register and not IP.
10295 Anyway this instruction is not really part of the stack
10296 frame creation although it is part of the prologue. */
10298 else if (IS_NESTED (func_type))
10300 /* The Static chain register is the same as the IP register
10301 used as a scratch register during stack frame creation.
10302 To get around this need to find somewhere to store IP
10303 whilst the frame is being created. We try the following
10306 1. The last argument register.
10307 2. A slot on the stack above the frame. (This only
10308 works if the function is not a varargs function).
10309 3. Register r3, after pushing the argument registers
10312 Note - we only need to tell the dwarf2 backend about the SP
10313 adjustment in the second variant; the static chain register
10314 doesn't need to be unwound, as it doesn't contain a value
10315 inherited from the caller. */
10317 if (regs_ever_live[3] == 0)
10319 insn = gen_rtx_REG (SImode, 3);
10320 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10321 insn = emit_insn (insn);
10323 else if (args_to_push == 0)
10326 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10327 insn = gen_rtx_MEM (SImode, insn);
10328 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10329 insn = emit_insn (insn);
10333 /* Just tell the dwarf backend that we adjusted SP. */
10334 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10335 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10336 GEN_INT (-fp_offset)));
10337 RTX_FRAME_RELATED_P (insn) = 1;
10338 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10339 dwarf, REG_NOTES (insn));
10343 /* Store the args on the stack. */
10344 if (cfun->machine->uses_anonymous_args)
10345 insn = emit_multi_reg_push
10346 ((0xf0 >> (args_to_push / 4)) & 0xf);
10349 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10350 GEN_INT (- args_to_push)));
10352 RTX_FRAME_RELATED_P (insn) = 1;
10354 saved_pretend_args = 1;
10355 fp_offset = args_to_push;
10358 /* Now reuse r3 to preserve IP. */
10359 insn = gen_rtx_REG (SImode, 3);
10360 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10361 (void) emit_insn (insn);
10367 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10368 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10371 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10373 insn = emit_insn (insn);
10374 RTX_FRAME_RELATED_P (insn) = 1;
10379 /* Push the argument registers, or reserve space for them. */
10380 if (cfun->machine->uses_anonymous_args)
10381 insn = emit_multi_reg_push
10382 ((0xf0 >> (args_to_push / 4)) & 0xf);
10385 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10386 GEN_INT (- args_to_push)));
10387 RTX_FRAME_RELATED_P (insn) = 1;
10390 /* If this is an interrupt service routine, and the link register
10391 is going to be pushed, and we are not creating a stack frame,
10392 (which would involve an extra push of IP and a pop in the epilogue)
10393 subtracting four from LR now will mean that the function return
10394 can be done with a single instruction. */
10395 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10396 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10397 && ! frame_pointer_needed)
10398 emit_insn (gen_rtx_SET (SImode,
10399 gen_rtx_REG (SImode, LR_REGNUM),
10400 gen_rtx_PLUS (SImode,
10401 gen_rtx_REG (SImode, LR_REGNUM),
10404 if (live_regs_mask)
10406 insn = emit_multi_reg_push (live_regs_mask);
10407 saved_regs += bit_count (live_regs_mask) * 4;
10408 RTX_FRAME_RELATED_P (insn) = 1;
10412 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10413 if (regs_ever_live[reg] && ! call_used_regs [reg])
10415 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10416 insn = gen_rtx_MEM (V2SImode, insn);
10417 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10418 gen_rtx_REG (V2SImode, reg)));
10419 RTX_FRAME_RELATED_P (insn) = 1;
10423 if (! IS_VOLATILE (func_type))
10427 /* Save any floating point call-saved registers used by this
10429 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10431 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10432 if (regs_ever_live[reg] && !call_used_regs[reg])
10434 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10435 insn = gen_rtx_MEM (XFmode, insn);
10436 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10437 gen_rtx_REG (XFmode, reg)));
10438 RTX_FRAME_RELATED_P (insn) = 1;
10444 start_reg = LAST_FPA_REGNUM;
10446 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10448 if (regs_ever_live[reg] && !call_used_regs[reg])
10450 if (start_reg - reg == 3)
10452 insn = emit_sfm (reg, 4);
10453 RTX_FRAME_RELATED_P (insn) = 1;
10455 start_reg = reg - 1;
10460 if (start_reg != reg)
10462 insn = emit_sfm (reg + 1, start_reg - reg);
10463 RTX_FRAME_RELATED_P (insn) = 1;
10464 saved_regs += (start_reg - reg) * 12;
10466 start_reg = reg - 1;
10470 if (start_reg != reg)
10472 insn = emit_sfm (reg + 1, start_reg - reg);
10473 saved_regs += (start_reg - reg) * 12;
10474 RTX_FRAME_RELATED_P (insn) = 1;
10477 if (TARGET_HARD_FLOAT && TARGET_VFP)
10479 start_reg = FIRST_VFP_REGNUM;
10481 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10483 if ((!regs_ever_live[reg] || call_used_regs[reg])
10484 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10486 if (start_reg != reg)
10487 saved_regs += vfp_emit_fstmx (start_reg,
10488 (reg - start_reg) / 2);
10489 start_reg = reg + 2;
10492 if (start_reg != reg)
10493 saved_regs += vfp_emit_fstmx (start_reg,
10494 (reg - start_reg) / 2);
10498 if (frame_pointer_needed)
10500 /* Create the new frame pointer. */
10501 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10502 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10503 RTX_FRAME_RELATED_P (insn) = 1;
10505 if (IS_NESTED (func_type))
10507 /* Recover the static chain register. */
10508 if (regs_ever_live [3] == 0
10509 || saved_pretend_args)
10510 insn = gen_rtx_REG (SImode, 3);
10511 else /* if (current_function_pretend_args_size == 0) */
10513 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10515 insn = gen_rtx_MEM (SImode, insn);
10518 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10519 /* Add a USE to stop propagate_one_insn() from barfing. */
10520 emit_insn (gen_prologue_use (ip_rtx));
10524 offsets = arm_get_frame_offsets ();
10525 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10527 /* This add can produce multiple insns for a large constant, so we
10528 need to get tricky. */
10529 rtx last = get_last_insn ();
10531 amount = GEN_INT (offsets->saved_args + saved_regs
10532 - offsets->outgoing_args);
10534 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10538 last = last ? NEXT_INSN (last) : get_insns ();
10539 RTX_FRAME_RELATED_P (last) = 1;
10541 while (last != insn);
10543 /* If the frame pointer is needed, emit a special barrier that
10544 will prevent the scheduler from moving stores to the frame
10545 before the stack adjustment. */
10546 if (frame_pointer_needed)
10547 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10548 hard_frame_pointer_rtx));
10551 /* If we are profiling, make sure no instructions are scheduled before
10552 the call to mcount. Similarly if the user has requested no
10553 scheduling in the prolog. */
10554 if (current_function_profile || TARGET_NO_SCHED_PRO)
10555 emit_insn (gen_blockage ());
10557 /* If the link register is being kept alive, with the return address in it,
10558 then make sure that it does not get reused by the ce2 pass. */
10559 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10561 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10562 cfun->machine->lr_save_eliminated = 1;
10566 /* If CODE is 'd', then the X is a condition operand and the instruction
10567 should only be executed if the condition is true.
10568 if CODE is 'D', then the X is a condition operand and the instruction
10569 should only be executed if the condition is false: however, if the mode
10570 of the comparison is CCFPEmode, then always execute the instruction -- we
10571 do this because in these circumstances !GE does not necessarily imply LT;
10572 in these cases the instruction pattern will take care to make sure that
10573 an instruction containing %d will follow, thereby undoing the effects of
10574 doing this instruction unconditionally.
10575 If CODE is 'N' then X is a floating point operand that must be negated
10577 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10578 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10580 arm_print_operand (FILE *stream, rtx x, int code)
10585 fputs (ASM_COMMENT_START, stream);
10589 fputs (user_label_prefix, stream);
10593 fputs (REGISTER_PREFIX, stream);
10597 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10599 if (TARGET_THUMB || current_insn_predicate != NULL)
10602 fputs (arm_condition_codes[arm_current_cc], stream);
10604 else if (current_insn_predicate)
10606 enum arm_cond_code code;
10611 code = get_arm_condition_code (current_insn_predicate);
10612 fputs (arm_condition_codes[code], stream);
10619 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10620 r = REAL_VALUE_NEGATE (r);
10621 fprintf (stream, "%s", fp_const_from_val (&r));
10626 if (GET_CODE (x) == CONST_INT)
10629 val = ARM_SIGN_EXTEND (~INTVAL (x));
10630 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10634 putc ('~', stream);
10635 output_addr_const (stream, x);
10640 fprintf (stream, "%s", arithmetic_instr (x, 1));
10643 /* Truncate Cirrus shift counts. */
10645 if (GET_CODE (x) == CONST_INT)
10647 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10650 arm_print_operand (stream, x, 0);
10654 fprintf (stream, "%s", arithmetic_instr (x, 0));
10660 const char * shift = shift_op (x, &val);
10664 fprintf (stream, ", %s ", shift_op (x, &val));
10666 arm_print_operand (stream, XEXP (x, 1), 0);
10668 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10673 /* An explanation of the 'Q', 'R' and 'H' register operands:
10675 In a pair of registers containing a DI or DF value the 'Q'
10676 operand returns the register number of the register containing
10677 the least significant part of the value. The 'R' operand returns
10678 the register number of the register containing the most
10679 significant part of the value.
10681 The 'H' operand returns the higher of the two register numbers.
10682 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10683 same as the 'Q' operand, since the most significant part of the
10684 value is held in the lower number register. The reverse is true
10685 on systems where WORDS_BIG_ENDIAN is false.
10687 The purpose of these operands is to distinguish between cases
10688 where the endian-ness of the values is important (for example
10689 when they are added together), and cases where the endian-ness
10690 is irrelevant, but the order of register operations is important.
10691 For example when loading a value from memory into a register
10692 pair, the endian-ness does not matter. Provided that the value
10693 from the lower memory address is put into the lower numbered
10694 register, and the value from the higher address is put into the
10695 higher numbered register, the load will work regardless of whether
10696 the value being loaded is big-wordian or little-wordian. The
10697 order of the two register loads can matter however, if the address
10698 of the memory location is actually held in one of the registers
10699 being overwritten by the load. */
10701 if (REGNO (x) > LAST_ARM_REGNUM)
10703 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10707 if (REGNO (x) > LAST_ARM_REGNUM)
10709 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10713 if (REGNO (x) > LAST_ARM_REGNUM)
10715 asm_fprintf (stream, "%r", REGNO (x) + 1);
10719 asm_fprintf (stream, "%r",
10720 GET_CODE (XEXP (x, 0)) == REG
10721 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10725 asm_fprintf (stream, "{%r-%r}",
10727 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10731 /* CONST_TRUE_RTX means always -- that's the default. */
10732 if (x == const_true_rtx)
10735 fputs (arm_condition_codes[get_arm_condition_code (x)],
10740 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10741 want to do that. */
10742 if (x == const_true_rtx)
10745 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10746 (get_arm_condition_code (x))],
10750 /* Cirrus registers can be accessed in a variety of ways:
10751 single floating point (f)
10752 double floating point (d)
10754 64bit integer (dx). */
10755 case 'W': /* Cirrus register in F mode. */
10756 case 'X': /* Cirrus register in D mode. */
10757 case 'Y': /* Cirrus register in FX mode. */
10758 case 'Z': /* Cirrus register in DX mode. */
10759 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10762 fprintf (stream, "mv%s%s",
10764 : code == 'X' ? "d"
10765 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10769 /* Print cirrus register in the mode specified by the register's mode. */
10772 int mode = GET_MODE (x);
10774 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10777 fprintf (stream, "mv%s%s",
10778 mode == DFmode ? "d"
10779 : mode == SImode ? "fx"
10780 : mode == DImode ? "dx"
10781 : "f", reg_names[REGNO (x)] + 2);
10787 if (GET_CODE (x) != REG
10788 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10789 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10790 /* Bad value for wCG register number. */
10793 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10796 /* Print an iWMMXt control register name. */
10798 if (GET_CODE (x) != CONST_INT
10800 || INTVAL (x) >= 16)
10801 /* Bad value for wC register number. */
10805 static const char * wc_reg_names [16] =
10807 "wCID", "wCon", "wCSSF", "wCASF",
10808 "wC4", "wC5", "wC6", "wC7",
10809 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10810 "wC12", "wC13", "wC14", "wC15"
10813 fprintf (stream, wc_reg_names [INTVAL (x)]);
10817 /* Print a VFP double precision register name. */
10820 int mode = GET_MODE (x);
10823 if (mode != DImode && mode != DFmode)
10826 if (GET_CODE (x) != REG
10827 || !IS_VFP_REGNUM (REGNO (x)))
10830 num = REGNO(x) - FIRST_VFP_REGNUM;
10834 fprintf (stream, "d%d", num >> 1);
10842 if (GET_CODE (x) == REG)
10843 asm_fprintf (stream, "%r", REGNO (x));
10844 else if (GET_CODE (x) == MEM)
10846 output_memory_reference_mode = GET_MODE (x);
10847 output_address (XEXP (x, 0));
10849 else if (GET_CODE (x) == CONST_DOUBLE)
10850 fprintf (stream, "#%s", fp_immediate_constant (x));
10851 else if (GET_CODE (x) == NEG)
10852 abort (); /* This should never happen now. */
10855 fputc ('#', stream);
10856 output_addr_const (stream, x);
10861 #ifndef AOF_ASSEMBLER
10862 /* Target hook for assembling integer objects. The ARM version needs to
10863 handle word-sized values specially. */
10865 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10867 if (size == UNITS_PER_WORD && aligned_p)
10869 fputs ("\t.word\t", asm_out_file);
10870 output_addr_const (asm_out_file, x);
10872 /* Mark symbols as position independent. We only do this in the
10873 .text segment, not in the .data segment. */
10874 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10875 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10877 if (GET_CODE (x) == SYMBOL_REF
10878 && (CONSTANT_POOL_ADDRESS_P (x)
10879 || SYMBOL_REF_LOCAL_P (x)))
10880 fputs ("(GOTOFF)", asm_out_file);
10881 else if (GET_CODE (x) == LABEL_REF)
10882 fputs ("(GOTOFF)", asm_out_file);
10884 fputs ("(GOT)", asm_out_file);
10886 fputc ('\n', asm_out_file);
10890 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10894 if (GET_CODE (x) != CONST_VECTOR)
10897 units = CONST_VECTOR_NUNITS (x);
10899 switch (GET_MODE (x))
10901 case V2SImode: size = 4; break;
10902 case V4HImode: size = 2; break;
10903 case V8QImode: size = 1; break;
10908 for (i = 0; i < units; i++)
10912 elt = CONST_VECTOR_ELT (x, i);
10914 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10920 return default_assemble_integer (x, size, aligned_p);
10924 /* A finite state machine takes care of noticing whether or not instructions
10925 can be conditionally executed, and thus decrease execution time and code
10926 size by deleting branch instructions. The fsm is controlled by
10927 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10929 /* The state of the fsm controlling condition codes are:
10930 0: normal, do nothing special
10931 1: make ASM_OUTPUT_OPCODE not output this instruction
10932 2: make ASM_OUTPUT_OPCODE not output this instruction
10933 3: make instructions conditional
10934 4: make instructions conditional
10936 State transitions (state->state by whom under condition):
10937 0 -> 1 final_prescan_insn if the `target' is a label
10938 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10939 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10940 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10941 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10942 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10943 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10944 (the target insn is arm_target_insn).
10946 If the jump clobbers the conditions then we use states 2 and 4.
10948 A similar thing can be done with conditional return insns.
10950 XXX In case the `target' is an unconditional branch, this conditionalising
10951 of the instructions always reduces code size, but not always execution
10952 time. But then, I want to reduce the code size to somewhere near what
10953 /bin/cc produces. */
10955 /* Returns the index of the ARM condition code string in
10956 `arm_condition_codes'. COMPARISON should be an rtx like
10957 `(eq (...) (...))'. */
10958 static enum arm_cond_code
10959 get_arm_condition_code (rtx comparison)
10961 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10963 enum rtx_code comp_code = GET_CODE (comparison);
10965 if (GET_MODE_CLASS (mode) != MODE_CC)
10966 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10967 XEXP (comparison, 1));
10971 case CC_DNEmode: code = ARM_NE; goto dominance;
10972 case CC_DEQmode: code = ARM_EQ; goto dominance;
10973 case CC_DGEmode: code = ARM_GE; goto dominance;
10974 case CC_DGTmode: code = ARM_GT; goto dominance;
10975 case CC_DLEmode: code = ARM_LE; goto dominance;
10976 case CC_DLTmode: code = ARM_LT; goto dominance;
10977 case CC_DGEUmode: code = ARM_CS; goto dominance;
10978 case CC_DGTUmode: code = ARM_HI; goto dominance;
10979 case CC_DLEUmode: code = ARM_LS; goto dominance;
10980 case CC_DLTUmode: code = ARM_CC;
10983 if (comp_code != EQ && comp_code != NE)
10986 if (comp_code == EQ)
10987 return ARM_INVERSE_CONDITION_CODE (code);
10993 case NE: return ARM_NE;
10994 case EQ: return ARM_EQ;
10995 case GE: return ARM_PL;
10996 case LT: return ARM_MI;
11003 case NE: return ARM_NE;
11004 case EQ: return ARM_EQ;
11011 case NE: return ARM_MI;
11012 case EQ: return ARM_PL;
11018 /* These encodings assume that AC=1 in the FPA system control
11019 byte. This allows us to handle all cases except UNEQ and
11023 case GE: return ARM_GE;
11024 case GT: return ARM_GT;
11025 case LE: return ARM_LS;
11026 case LT: return ARM_MI;
11027 case NE: return ARM_NE;
11028 case EQ: return ARM_EQ;
11029 case ORDERED: return ARM_VC;
11030 case UNORDERED: return ARM_VS;
11031 case UNLT: return ARM_LT;
11032 case UNLE: return ARM_LE;
11033 case UNGT: return ARM_HI;
11034 case UNGE: return ARM_PL;
11035 /* UNEQ and LTGT do not have a representation. */
11036 case UNEQ: /* Fall through. */
11037 case LTGT: /* Fall through. */
11044 case NE: return ARM_NE;
11045 case EQ: return ARM_EQ;
11046 case GE: return ARM_LE;
11047 case GT: return ARM_LT;
11048 case LE: return ARM_GE;
11049 case LT: return ARM_GT;
11050 case GEU: return ARM_LS;
11051 case GTU: return ARM_CC;
11052 case LEU: return ARM_CS;
11053 case LTU: return ARM_HI;
11060 case LTU: return ARM_CS;
11061 case GEU: return ARM_CC;
11068 case NE: return ARM_NE;
11069 case EQ: return ARM_EQ;
11070 case GE: return ARM_GE;
11071 case GT: return ARM_GT;
11072 case LE: return ARM_LE;
11073 case LT: return ARM_LT;
11074 case GEU: return ARM_CS;
11075 case GTU: return ARM_HI;
11076 case LEU: return ARM_LS;
11077 case LTU: return ARM_CC;
11088 arm_final_prescan_insn (rtx insn)
11090 /* BODY will hold the body of INSN. */
11091 rtx body = PATTERN (insn);
11093 /* This will be 1 if trying to repeat the trick, and things need to be
11094 reversed if it appears to fail. */
11097 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11098 taken are clobbered, even if the rtl suggests otherwise. It also
11099 means that we have to grub around within the jump expression to find
11100 out what the conditions are when the jump isn't taken. */
11101 int jump_clobbers = 0;
11103 /* If we start with a return insn, we only succeed if we find another one. */
11104 int seeking_return = 0;
11106 /* START_INSN will hold the insn from where we start looking. This is the
11107 first insn after the following code_label if REVERSE is true. */
11108 rtx start_insn = insn;
11110 /* If in state 4, check if the target branch is reached, in order to
11111 change back to state 0. */
11112 if (arm_ccfsm_state == 4)
11114 if (insn == arm_target_insn)
11116 arm_target_insn = NULL;
11117 arm_ccfsm_state = 0;
11122 /* If in state 3, it is possible to repeat the trick, if this insn is an
11123 unconditional branch to a label, and immediately following this branch
11124 is the previous target label which is only used once, and the label this
11125 branch jumps to is not too far off. */
11126 if (arm_ccfsm_state == 3)
11128 if (simplejump_p (insn))
11130 start_insn = next_nonnote_insn (start_insn);
11131 if (GET_CODE (start_insn) == BARRIER)
11133 /* XXX Isn't this always a barrier? */
11134 start_insn = next_nonnote_insn (start_insn);
11136 if (GET_CODE (start_insn) == CODE_LABEL
11137 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11138 && LABEL_NUSES (start_insn) == 1)
11143 else if (GET_CODE (body) == RETURN)
11145 start_insn = next_nonnote_insn (start_insn);
11146 if (GET_CODE (start_insn) == BARRIER)
11147 start_insn = next_nonnote_insn (start_insn);
11148 if (GET_CODE (start_insn) == CODE_LABEL
11149 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11150 && LABEL_NUSES (start_insn) == 1)
11153 seeking_return = 1;
11162 if (arm_ccfsm_state != 0 && !reverse)
11164 if (GET_CODE (insn) != JUMP_INSN)
11167 /* This jump might be paralleled with a clobber of the condition codes
11168 the jump should always come first */
11169 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11170 body = XVECEXP (body, 0, 0);
11173 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11174 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11177 int fail = FALSE, succeed = FALSE;
11178 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11179 int then_not_else = TRUE;
11180 rtx this_insn = start_insn, label = 0;
11182 /* If the jump cannot be done with one instruction, we cannot
11183 conditionally execute the instruction in the inverse case. */
11184 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11190 /* Register the insn jumped to. */
11193 if (!seeking_return)
11194 label = XEXP (SET_SRC (body), 0);
11196 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11197 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11198 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11200 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11201 then_not_else = FALSE;
11203 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11204 seeking_return = 1;
11205 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11207 seeking_return = 1;
11208 then_not_else = FALSE;
11213 /* See how many insns this branch skips, and what kind of insns. If all
11214 insns are okay, and the label or unconditional branch to the same
11215 label is not too far away, succeed. */
11216 for (insns_skipped = 0;
11217 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11221 this_insn = next_nonnote_insn (this_insn);
11225 switch (GET_CODE (this_insn))
11228 /* Succeed if it is the target label, otherwise fail since
11229 control falls in from somewhere else. */
11230 if (this_insn == label)
11234 arm_ccfsm_state = 2;
11235 this_insn = next_nonnote_insn (this_insn);
11238 arm_ccfsm_state = 1;
11246 /* Succeed if the following insn is the target label.
11248 If return insns are used then the last insn in a function
11249 will be a barrier. */
11250 this_insn = next_nonnote_insn (this_insn);
11251 if (this_insn && this_insn == label)
11255 arm_ccfsm_state = 2;
11256 this_insn = next_nonnote_insn (this_insn);
11259 arm_ccfsm_state = 1;
11267 /* The AAPCS says that conditional calls should not be
11268 used since they make interworking inefficient (the
11269 linker can't transform BL<cond> into BLX). That's
11270 only a problem if the machine has BLX. */
11277 /* Succeed if the following insn is the target label, or
11278 if the following two insns are a barrier and the
11280 this_insn = next_nonnote_insn (this_insn);
11281 if (this_insn && GET_CODE (this_insn) == BARRIER)
11282 this_insn = next_nonnote_insn (this_insn);
11284 if (this_insn && this_insn == label
11285 && insns_skipped < max_insns_skipped)
11289 arm_ccfsm_state = 2;
11290 this_insn = next_nonnote_insn (this_insn);
11293 arm_ccfsm_state = 1;
11301 /* If this is an unconditional branch to the same label, succeed.
11302 If it is to another label, do nothing. If it is conditional,
11304 /* XXX Probably, the tests for SET and the PC are
11307 scanbody = PATTERN (this_insn);
11308 if (GET_CODE (scanbody) == SET
11309 && GET_CODE (SET_DEST (scanbody)) == PC)
11311 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11312 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11314 arm_ccfsm_state = 2;
11317 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11320 /* Fail if a conditional return is undesirable (eg on a
11321 StrongARM), but still allow this if optimizing for size. */
11322 else if (GET_CODE (scanbody) == RETURN
11323 && !use_return_insn (TRUE, NULL)
11326 else if (GET_CODE (scanbody) == RETURN
11329 arm_ccfsm_state = 2;
11332 else if (GET_CODE (scanbody) == PARALLEL)
11334 switch (get_attr_conds (this_insn))
11344 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11349 /* Instructions using or affecting the condition codes make it
11351 scanbody = PATTERN (this_insn);
11352 if (!(GET_CODE (scanbody) == SET
11353 || GET_CODE (scanbody) == PARALLEL)
11354 || get_attr_conds (this_insn) != CONDS_NOCOND)
11357 /* A conditional cirrus instruction must be followed by
11358 a non Cirrus instruction. However, since we
11359 conditionalize instructions in this function and by
11360 the time we get here we can't add instructions
11361 (nops), because shorten_branches() has already been
11362 called, we will disable conditionalizing Cirrus
11363 instructions to be safe. */
11364 if (GET_CODE (scanbody) != USE
11365 && GET_CODE (scanbody) != CLOBBER
11366 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11376 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11377 arm_target_label = CODE_LABEL_NUMBER (label);
11378 else if (seeking_return || arm_ccfsm_state == 2)
11380 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11382 this_insn = next_nonnote_insn (this_insn);
11383 if (this_insn && (GET_CODE (this_insn) == BARRIER
11384 || GET_CODE (this_insn) == CODE_LABEL))
11389 /* Oh, dear! we ran off the end.. give up. */
11390 recog (PATTERN (insn), insn, NULL);
11391 arm_ccfsm_state = 0;
11392 arm_target_insn = NULL;
11395 arm_target_insn = this_insn;
11404 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11406 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11407 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11408 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11409 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11413 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11416 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11420 if (reverse || then_not_else)
11421 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11424 /* Restore recog_data (getting the attributes of other insns can
11425 destroy this array, but final.c assumes that it remains intact
11426 across this call; since the insn has been recognized already we
11427 call recog direct). */
11428 recog (PATTERN (insn), insn, NULL);
11432 /* Returns true if REGNO is a valid register
11433 for holding a quantity of tyoe MODE. */
11435 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11437 if (GET_MODE_CLASS (mode) == MODE_CC)
11438 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11441 /* For the Thumb we only allow values bigger than SImode in
11442 registers 0 - 6, so that there is always a second low
11443 register available to hold the upper part of the value.
11444 We probably we ought to ensure that the register is the
11445 start of an even numbered register pair. */
11446 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11448 if (IS_CIRRUS_REGNUM (regno))
11449 /* We have outlawed SI values in Cirrus registers because they
11450 reside in the lower 32 bits, but SF values reside in the
11451 upper 32 bits. This causes gcc all sorts of grief. We can't
11452 even split the registers into pairs because Cirrus SI values
11453 get sign extended to 64bits-- aldyh. */
11454 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11456 if (IS_VFP_REGNUM (regno))
11458 if (mode == SFmode || mode == SImode)
11461 /* DFmode values are only valid in even register pairs. */
11462 if (mode == DFmode)
11463 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11467 if (IS_IWMMXT_GR_REGNUM (regno))
11468 return mode == SImode;
11470 if (IS_IWMMXT_REGNUM (regno))
11471 return VALID_IWMMXT_REG_MODE (mode);
11473 /* We allow any value to be stored in the general registers.
11474 Restrict doubleword quantities to even register pairs so that we can
11476 if (regno <= LAST_ARM_REGNUM)
11477 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11479 if ( regno == FRAME_POINTER_REGNUM
11480 || regno == ARG_POINTER_REGNUM)
11481 /* We only allow integers in the fake hard registers. */
11482 return GET_MODE_CLASS (mode) == MODE_INT;
11484 /* The only registers left are the FPA registers
11485 which we only allow to hold FP values. */
11486 return GET_MODE_CLASS (mode) == MODE_FLOAT
11487 && regno >= FIRST_FPA_REGNUM
11488 && regno <= LAST_FPA_REGNUM;
11492 arm_regno_class (int regno)
11496 if (regno == STACK_POINTER_REGNUM)
11498 if (regno == CC_REGNUM)
11505 if ( regno <= LAST_ARM_REGNUM
11506 || regno == FRAME_POINTER_REGNUM
11507 || regno == ARG_POINTER_REGNUM)
11508 return GENERAL_REGS;
11510 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11513 if (IS_CIRRUS_REGNUM (regno))
11514 return CIRRUS_REGS;
11516 if (IS_VFP_REGNUM (regno))
11519 if (IS_IWMMXT_REGNUM (regno))
11520 return IWMMXT_REGS;
11522 if (IS_IWMMXT_GR_REGNUM (regno))
11523 return IWMMXT_GR_REGS;
11528 /* Handle a special case when computing the offset
11529 of an argument from the frame pointer. */
11531 arm_debugger_arg_offset (int value, rtx addr)
11535 /* We are only interested if dbxout_parms() failed to compute the offset. */
11539 /* We can only cope with the case where the address is held in a register. */
11540 if (GET_CODE (addr) != REG)
11543 /* If we are using the frame pointer to point at the argument, then
11544 an offset of 0 is correct. */
11545 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11548 /* If we are using the stack pointer to point at the
11549 argument, then an offset of 0 is correct. */
11550 if ((TARGET_THUMB || !frame_pointer_needed)
11551 && REGNO (addr) == SP_REGNUM)
11554 /* Oh dear. The argument is pointed to by a register rather
11555 than being held in a register, or being stored at a known
11556 offset from the frame pointer. Since GDB only understands
11557 those two kinds of argument we must translate the address
11558 held in the register into an offset from the frame pointer.
11559 We do this by searching through the insns for the function
11560 looking to see where this register gets its value. If the
11561 register is initialized from the frame pointer plus an offset
11562 then we are in luck and we can continue, otherwise we give up.
11564 This code is exercised by producing debugging information
11565 for a function with arguments like this:
11567 double func (double a, double b, int c, double d) {return d;}
11569 Without this code the stab for parameter 'd' will be set to
11570 an offset of 0 from the frame pointer, rather than 8. */
11572 /* The if() statement says:
11574 If the insn is a normal instruction
11575 and if the insn is setting the value in a register
11576 and if the register being set is the register holding the address of the argument
11577 and if the address is computing by an addition
11578 that involves adding to a register
11579 which is the frame pointer
11584 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11586 if ( GET_CODE (insn) == INSN
11587 && GET_CODE (PATTERN (insn)) == SET
11588 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11589 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11590 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11591 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11592 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11595 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11604 warning ("unable to compute real location of stacked parameter");
11605 value = 8; /* XXX magic hack */
11611 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11614 if ((MASK) & insn_flags) \
11615 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11619 struct builtin_description
11621 const unsigned int mask;
11622 const enum insn_code icode;
11623 const char * const name;
11624 const enum arm_builtins code;
11625 const enum rtx_code comparison;
11626 const unsigned int flag;
11629 static const struct builtin_description bdesc_2arg[] =
11631 #define IWMMXT_BUILTIN(code, string, builtin) \
11632 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11633 ARM_BUILTIN_##builtin, 0, 0 },
11635 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11636 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11637 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11638 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11639 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11640 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11641 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11642 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11643 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11644 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11645 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11646 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11647 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11648 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11649 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11650 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11651 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11652 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11653 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11654 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11655 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11656 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11657 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11658 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11659 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11660 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11661 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11662 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11663 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11664 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11665 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11666 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11667 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11668 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11669 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11670 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11671 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11672 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11673 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11674 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11675 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11676 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11677 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11678 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11679 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11680 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11681 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11682 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11683 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11684 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11685 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11686 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11687 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11688 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11689 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11690 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11691 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11692 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11694 #define IWMMXT_BUILTIN2(code, builtin) \
11695 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11697 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11698 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11699 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11700 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11701 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11702 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11703 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11704 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11705 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11706 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11707 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11708 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11709 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11710 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11711 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11712 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11713 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11714 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11715 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11716 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11717 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11718 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11719 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11720 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11721 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11722 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11723 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11724 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11725 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11726 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11727 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11728 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11731 static const struct builtin_description bdesc_1arg[] =
11733 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11734 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11735 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11736 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11737 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11738 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11739 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11740 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11741 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11742 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11743 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11744 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11745 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11746 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11747 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11748 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11749 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11750 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11753 /* Set up all the iWMMXt builtins. This is
11754 not called if TARGET_IWMMXT is zero. */
11757 arm_init_iwmmxt_builtins (void)
11759 const struct builtin_description * d;
11761 tree endlink = void_list_node;
11763 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11764 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11765 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11768 = build_function_type (integer_type_node,
11769 tree_cons (NULL_TREE, integer_type_node, endlink));
11770 tree v8qi_ftype_v8qi_v8qi_int
11771 = build_function_type (V8QI_type_node,
11772 tree_cons (NULL_TREE, V8QI_type_node,
11773 tree_cons (NULL_TREE, V8QI_type_node,
11774 tree_cons (NULL_TREE,
11777 tree v4hi_ftype_v4hi_int
11778 = build_function_type (V4HI_type_node,
11779 tree_cons (NULL_TREE, V4HI_type_node,
11780 tree_cons (NULL_TREE, integer_type_node,
11782 tree v2si_ftype_v2si_int
11783 = build_function_type (V2SI_type_node,
11784 tree_cons (NULL_TREE, V2SI_type_node,
11785 tree_cons (NULL_TREE, integer_type_node,
11787 tree v2si_ftype_di_di
11788 = build_function_type (V2SI_type_node,
11789 tree_cons (NULL_TREE, long_long_integer_type_node,
11790 tree_cons (NULL_TREE, long_long_integer_type_node,
11792 tree di_ftype_di_int
11793 = build_function_type (long_long_integer_type_node,
11794 tree_cons (NULL_TREE, long_long_integer_type_node,
11795 tree_cons (NULL_TREE, integer_type_node,
11797 tree di_ftype_di_int_int
11798 = build_function_type (long_long_integer_type_node,
11799 tree_cons (NULL_TREE, long_long_integer_type_node,
11800 tree_cons (NULL_TREE, integer_type_node,
11801 tree_cons (NULL_TREE,
11804 tree int_ftype_v8qi
11805 = build_function_type (integer_type_node,
11806 tree_cons (NULL_TREE, V8QI_type_node,
11808 tree int_ftype_v4hi
11809 = build_function_type (integer_type_node,
11810 tree_cons (NULL_TREE, V4HI_type_node,
11812 tree int_ftype_v2si
11813 = build_function_type (integer_type_node,
11814 tree_cons (NULL_TREE, V2SI_type_node,
11816 tree int_ftype_v8qi_int
11817 = build_function_type (integer_type_node,
11818 tree_cons (NULL_TREE, V8QI_type_node,
11819 tree_cons (NULL_TREE, integer_type_node,
11821 tree int_ftype_v4hi_int
11822 = build_function_type (integer_type_node,
11823 tree_cons (NULL_TREE, V4HI_type_node,
11824 tree_cons (NULL_TREE, integer_type_node,
11826 tree int_ftype_v2si_int
11827 = build_function_type (integer_type_node,
11828 tree_cons (NULL_TREE, V2SI_type_node,
11829 tree_cons (NULL_TREE, integer_type_node,
11831 tree v8qi_ftype_v8qi_int_int
11832 = build_function_type (V8QI_type_node,
11833 tree_cons (NULL_TREE, V8QI_type_node,
11834 tree_cons (NULL_TREE, integer_type_node,
11835 tree_cons (NULL_TREE,
11838 tree v4hi_ftype_v4hi_int_int
11839 = build_function_type (V4HI_type_node,
11840 tree_cons (NULL_TREE, V4HI_type_node,
11841 tree_cons (NULL_TREE, integer_type_node,
11842 tree_cons (NULL_TREE,
11845 tree v2si_ftype_v2si_int_int
11846 = build_function_type (V2SI_type_node,
11847 tree_cons (NULL_TREE, V2SI_type_node,
11848 tree_cons (NULL_TREE, integer_type_node,
11849 tree_cons (NULL_TREE,
11852 /* Miscellaneous. */
11853 tree v8qi_ftype_v4hi_v4hi
11854 = build_function_type (V8QI_type_node,
11855 tree_cons (NULL_TREE, V4HI_type_node,
11856 tree_cons (NULL_TREE, V4HI_type_node,
11858 tree v4hi_ftype_v2si_v2si
11859 = build_function_type (V4HI_type_node,
11860 tree_cons (NULL_TREE, V2SI_type_node,
11861 tree_cons (NULL_TREE, V2SI_type_node,
11863 tree v2si_ftype_v4hi_v4hi
11864 = build_function_type (V2SI_type_node,
11865 tree_cons (NULL_TREE, V4HI_type_node,
11866 tree_cons (NULL_TREE, V4HI_type_node,
11868 tree v2si_ftype_v8qi_v8qi
11869 = build_function_type (V2SI_type_node,
11870 tree_cons (NULL_TREE, V8QI_type_node,
11871 tree_cons (NULL_TREE, V8QI_type_node,
11873 tree v4hi_ftype_v4hi_di
11874 = build_function_type (V4HI_type_node,
11875 tree_cons (NULL_TREE, V4HI_type_node,
11876 tree_cons (NULL_TREE,
11877 long_long_integer_type_node,
11879 tree v2si_ftype_v2si_di
11880 = build_function_type (V2SI_type_node,
11881 tree_cons (NULL_TREE, V2SI_type_node,
11882 tree_cons (NULL_TREE,
11883 long_long_integer_type_node,
11885 tree void_ftype_int_int
11886 = build_function_type (void_type_node,
11887 tree_cons (NULL_TREE, integer_type_node,
11888 tree_cons (NULL_TREE, integer_type_node,
11891 = build_function_type (long_long_unsigned_type_node, endlink);
11893 = build_function_type (long_long_integer_type_node,
11894 tree_cons (NULL_TREE, V8QI_type_node,
11897 = build_function_type (long_long_integer_type_node,
11898 tree_cons (NULL_TREE, V4HI_type_node,
11901 = build_function_type (long_long_integer_type_node,
11902 tree_cons (NULL_TREE, V2SI_type_node,
11904 tree v2si_ftype_v4hi
11905 = build_function_type (V2SI_type_node,
11906 tree_cons (NULL_TREE, V4HI_type_node,
11908 tree v4hi_ftype_v8qi
11909 = build_function_type (V4HI_type_node,
11910 tree_cons (NULL_TREE, V8QI_type_node,
11913 tree di_ftype_di_v4hi_v4hi
11914 = build_function_type (long_long_unsigned_type_node,
11915 tree_cons (NULL_TREE,
11916 long_long_unsigned_type_node,
11917 tree_cons (NULL_TREE, V4HI_type_node,
11918 tree_cons (NULL_TREE,
11922 tree di_ftype_v4hi_v4hi
11923 = build_function_type (long_long_unsigned_type_node,
11924 tree_cons (NULL_TREE, V4HI_type_node,
11925 tree_cons (NULL_TREE, V4HI_type_node,
11928 /* Normal vector binops. */
11929 tree v8qi_ftype_v8qi_v8qi
11930 = build_function_type (V8QI_type_node,
11931 tree_cons (NULL_TREE, V8QI_type_node,
11932 tree_cons (NULL_TREE, V8QI_type_node,
11934 tree v4hi_ftype_v4hi_v4hi
11935 = build_function_type (V4HI_type_node,
11936 tree_cons (NULL_TREE, V4HI_type_node,
11937 tree_cons (NULL_TREE, V4HI_type_node,
11939 tree v2si_ftype_v2si_v2si
11940 = build_function_type (V2SI_type_node,
11941 tree_cons (NULL_TREE, V2SI_type_node,
11942 tree_cons (NULL_TREE, V2SI_type_node,
11944 tree di_ftype_di_di
11945 = build_function_type (long_long_unsigned_type_node,
11946 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11947 tree_cons (NULL_TREE,
11948 long_long_unsigned_type_node,
11951 /* Add all builtins that are more or less simple operations on two
11953 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11955 /* Use one of the operands; the target can have a different mode for
11956 mask-generating compares. */
11957 enum machine_mode mode;
11963 mode = insn_data[d->icode].operand[1].mode;
11968 type = v8qi_ftype_v8qi_v8qi;
11971 type = v4hi_ftype_v4hi_v4hi;
11974 type = v2si_ftype_v2si_v2si;
11977 type = di_ftype_di_di;
11984 def_mbuiltin (d->mask, d->name, type, d->code);
11987 /* Add the remaining MMX insns with somewhat more complicated types. */
11988 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12002 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12006 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12013 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12015 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12020 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12022 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12027 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12056 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12057 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12061 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12063 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12065 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12066 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12067 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12068 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12070 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12071 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12072 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12073 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12074 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12075 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12076 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12080 arm_init_builtins (void)
12082 if (TARGET_REALLY_IWMMXT)
12083 arm_init_iwmmxt_builtins ();
12086 /* Errors in the source file can cause expand_expr to return const0_rtx
12087 where we expect a vector. To avoid crashing, use one of the vector
12088 clear instructions. */
12091 safe_vector_operand (rtx x, enum machine_mode mode)
12093 if (x != const0_rtx)
12095 x = gen_reg_rtx (mode);
12097 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12098 : gen_rtx_SUBREG (DImode, x, 0)));
12102 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12105 arm_expand_binop_builtin (enum insn_code icode,
12106 tree arglist, rtx target)
12109 tree arg0 = TREE_VALUE (arglist);
12110 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12111 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12112 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12113 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12114 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12115 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12117 if (VECTOR_MODE_P (mode0))
12118 op0 = safe_vector_operand (op0, mode0);
12119 if (VECTOR_MODE_P (mode1))
12120 op1 = safe_vector_operand (op1, mode1);
12123 || GET_MODE (target) != tmode
12124 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12125 target = gen_reg_rtx (tmode);
12127 /* In case the insn wants input operands in modes different from
12128 the result, abort. */
12129 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12132 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12133 op0 = copy_to_mode_reg (mode0, op0);
12134 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12135 op1 = copy_to_mode_reg (mode1, op1);
12137 pat = GEN_FCN (icode) (target, op0, op1);
12144 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12147 arm_expand_unop_builtin (enum insn_code icode,
12148 tree arglist, rtx target, int do_load)
12151 tree arg0 = TREE_VALUE (arglist);
12152 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12153 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12154 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12157 || GET_MODE (target) != tmode
12158 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12159 target = gen_reg_rtx (tmode);
12161 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12164 if (VECTOR_MODE_P (mode0))
12165 op0 = safe_vector_operand (op0, mode0);
12167 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12168 op0 = copy_to_mode_reg (mode0, op0);
12171 pat = GEN_FCN (icode) (target, op0);
12178 /* Expand an expression EXP that calls a built-in function,
12179 with result going to TARGET if that's convenient
12180 (and in mode MODE if that's convenient).
12181 SUBTARGET may be used as the target for computing one of EXP's operands.
12182 IGNORE is nonzero if the value is to be ignored. */
12185 arm_expand_builtin (tree exp,
12187 rtx subtarget ATTRIBUTE_UNUSED,
12188 enum machine_mode mode ATTRIBUTE_UNUSED,
12189 int ignore ATTRIBUTE_UNUSED)
12191 const struct builtin_description * d;
12192 enum insn_code icode;
12193 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12194 tree arglist = TREE_OPERAND (exp, 1);
12202 int fcode = DECL_FUNCTION_CODE (fndecl);
12204 enum machine_mode tmode;
12205 enum machine_mode mode0;
12206 enum machine_mode mode1;
12207 enum machine_mode mode2;
12211 case ARM_BUILTIN_TEXTRMSB:
12212 case ARM_BUILTIN_TEXTRMUB:
12213 case ARM_BUILTIN_TEXTRMSH:
12214 case ARM_BUILTIN_TEXTRMUH:
12215 case ARM_BUILTIN_TEXTRMSW:
12216 case ARM_BUILTIN_TEXTRMUW:
12217 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12218 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12219 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12220 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12221 : CODE_FOR_iwmmxt_textrmw);
12223 arg0 = TREE_VALUE (arglist);
12224 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12225 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12226 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12227 tmode = insn_data[icode].operand[0].mode;
12228 mode0 = insn_data[icode].operand[1].mode;
12229 mode1 = insn_data[icode].operand[2].mode;
12231 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12232 op0 = copy_to_mode_reg (mode0, op0);
12233 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12235 /* @@@ better error message */
12236 error ("selector must be an immediate");
12237 return gen_reg_rtx (tmode);
12240 || GET_MODE (target) != tmode
12241 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12242 target = gen_reg_rtx (tmode);
12243 pat = GEN_FCN (icode) (target, op0, op1);
12249 case ARM_BUILTIN_TINSRB:
12250 case ARM_BUILTIN_TINSRH:
12251 case ARM_BUILTIN_TINSRW:
12252 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12253 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12254 : CODE_FOR_iwmmxt_tinsrw);
12255 arg0 = TREE_VALUE (arglist);
12256 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12257 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12258 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12259 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12260 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12261 tmode = insn_data[icode].operand[0].mode;
12262 mode0 = insn_data[icode].operand[1].mode;
12263 mode1 = insn_data[icode].operand[2].mode;
12264 mode2 = insn_data[icode].operand[3].mode;
12266 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12267 op0 = copy_to_mode_reg (mode0, op0);
12268 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12269 op1 = copy_to_mode_reg (mode1, op1);
12270 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12272 /* @@@ better error message */
12273 error ("selector must be an immediate");
12277 || GET_MODE (target) != tmode
12278 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12279 target = gen_reg_rtx (tmode);
12280 pat = GEN_FCN (icode) (target, op0, op1, op2);
12286 case ARM_BUILTIN_SETWCX:
12287 arg0 = TREE_VALUE (arglist);
12288 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12289 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12290 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12291 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12294 case ARM_BUILTIN_GETWCX:
12295 arg0 = TREE_VALUE (arglist);
12296 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12297 target = gen_reg_rtx (SImode);
12298 emit_insn (gen_iwmmxt_tmrc (target, op0));
12301 case ARM_BUILTIN_WSHUFH:
12302 icode = CODE_FOR_iwmmxt_wshufh;
12303 arg0 = TREE_VALUE (arglist);
12304 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12305 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12306 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12307 tmode = insn_data[icode].operand[0].mode;
12308 mode1 = insn_data[icode].operand[1].mode;
12309 mode2 = insn_data[icode].operand[2].mode;
12311 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12312 op0 = copy_to_mode_reg (mode1, op0);
12313 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12315 /* @@@ better error message */
12316 error ("mask must be an immediate");
12320 || GET_MODE (target) != tmode
12321 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12322 target = gen_reg_rtx (tmode);
12323 pat = GEN_FCN (icode) (target, op0, op1);
12329 case ARM_BUILTIN_WSADB:
12330 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12331 case ARM_BUILTIN_WSADH:
12332 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12333 case ARM_BUILTIN_WSADBZ:
12334 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12335 case ARM_BUILTIN_WSADHZ:
12336 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12338 /* Several three-argument builtins. */
12339 case ARM_BUILTIN_WMACS:
12340 case ARM_BUILTIN_WMACU:
12341 case ARM_BUILTIN_WALIGN:
12342 case ARM_BUILTIN_TMIA:
12343 case ARM_BUILTIN_TMIAPH:
12344 case ARM_BUILTIN_TMIATT:
12345 case ARM_BUILTIN_TMIATB:
12346 case ARM_BUILTIN_TMIABT:
12347 case ARM_BUILTIN_TMIABB:
12348 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12349 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12350 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12351 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12352 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12353 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12354 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12355 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12356 : CODE_FOR_iwmmxt_walign);
12357 arg0 = TREE_VALUE (arglist);
12358 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12359 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12360 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12361 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12362 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12363 tmode = insn_data[icode].operand[0].mode;
12364 mode0 = insn_data[icode].operand[1].mode;
12365 mode1 = insn_data[icode].operand[2].mode;
12366 mode2 = insn_data[icode].operand[3].mode;
12368 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12369 op0 = copy_to_mode_reg (mode0, op0);
12370 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12371 op1 = copy_to_mode_reg (mode1, op1);
12372 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12373 op2 = copy_to_mode_reg (mode2, op2);
12375 || GET_MODE (target) != tmode
12376 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12377 target = gen_reg_rtx (tmode);
12378 pat = GEN_FCN (icode) (target, op0, op1, op2);
12384 case ARM_BUILTIN_WZERO:
12385 target = gen_reg_rtx (DImode);
12386 emit_insn (gen_iwmmxt_clrdi (target));
12393 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12394 if (d->code == (const enum arm_builtins) fcode)
12395 return arm_expand_binop_builtin (d->icode, arglist, target);
12397 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12398 if (d->code == (const enum arm_builtins) fcode)
12399 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12401 /* @@@ Should really do something sensible here. */
12405 /* Recursively search through all of the blocks in a function
12406 checking to see if any of the variables created in that
12407 function match the RTX called 'orig'. If they do then
12408 replace them with the RTX called 'new'. */
12410 replace_symbols_in_block (tree block, rtx orig, rtx new)
12412 for (; block; block = BLOCK_CHAIN (block))
12416 if (!TREE_USED (block))
12419 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12421 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12422 || DECL_IGNORED_P (sym)
12423 || TREE_CODE (sym) != VAR_DECL
12424 || DECL_EXTERNAL (sym)
12425 || !rtx_equal_p (DECL_RTL (sym), orig)
12429 SET_DECL_RTL (sym, new);
12432 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12436 /* Return the number (counting from 0) of
12437 the least significant set bit in MASK. */
12440 number_of_first_bit_set (int mask)
12445 (mask & (1 << bit)) == 0;
12452 /* Generate code to return from a thumb function.
12453 If 'reg_containing_return_addr' is -1, then the return address is
12454 actually on the stack, at the stack pointer. */
12456 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12458 unsigned regs_available_for_popping;
12459 unsigned regs_to_pop;
12461 unsigned available;
12465 int restore_a4 = FALSE;
12467 /* Compute the registers we need to pop. */
12471 /* There is an assumption here, that if eh_ofs is not NULL, the
12472 normal return address will have been pushed. */
12473 if (reg_containing_return_addr == -1 || eh_ofs)
12475 /* When we are generating a return for __builtin_eh_return,
12476 reg_containing_return_addr must specify the return regno. */
12477 if (eh_ofs && reg_containing_return_addr == -1)
12480 regs_to_pop |= 1 << LR_REGNUM;
12484 if (TARGET_BACKTRACE)
12486 /* Restore the (ARM) frame pointer and stack pointer. */
12487 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12491 /* If there is nothing to pop then just emit the BX instruction and
12493 if (pops_needed == 0)
12496 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12498 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12501 /* Otherwise if we are not supporting interworking and we have not created
12502 a backtrace structure and the function was not entered in ARM mode then
12503 just pop the return address straight into the PC. */
12504 else if (!TARGET_INTERWORK
12505 && !TARGET_BACKTRACE
12506 && !is_called_in_ARM_mode (current_function_decl))
12510 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12511 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12512 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12515 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12520 /* Find out how many of the (return) argument registers we can corrupt. */
12521 regs_available_for_popping = 0;
12523 /* If returning via __builtin_eh_return, the bottom three registers
12524 all contain information needed for the return. */
12529 /* If we can deduce the registers used from the function's
12530 return value. This is more reliable that examining
12531 regs_ever_live[] because that will be set if the register is
12532 ever used in the function, not just if the register is used
12533 to hold a return value. */
12535 if (current_function_return_rtx != 0)
12536 mode = GET_MODE (current_function_return_rtx);
12538 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12540 size = GET_MODE_SIZE (mode);
12544 /* In a void function we can use any argument register.
12545 In a function that returns a structure on the stack
12546 we can use the second and third argument registers. */
12547 if (mode == VOIDmode)
12548 regs_available_for_popping =
12549 (1 << ARG_REGISTER (1))
12550 | (1 << ARG_REGISTER (2))
12551 | (1 << ARG_REGISTER (3));
12553 regs_available_for_popping =
12554 (1 << ARG_REGISTER (2))
12555 | (1 << ARG_REGISTER (3));
12557 else if (size <= 4)
12558 regs_available_for_popping =
12559 (1 << ARG_REGISTER (2))
12560 | (1 << ARG_REGISTER (3));
12561 else if (size <= 8)
12562 regs_available_for_popping =
12563 (1 << ARG_REGISTER (3));
12566 /* Match registers to be popped with registers into which we pop them. */
12567 for (available = regs_available_for_popping,
12568 required = regs_to_pop;
12569 required != 0 && available != 0;
12570 available &= ~(available & - available),
12571 required &= ~(required & - required))
12574 /* If we have any popping registers left over, remove them. */
12576 regs_available_for_popping &= ~available;
12578 /* Otherwise if we need another popping register we can use
12579 the fourth argument register. */
12580 else if (pops_needed)
12582 /* If we have not found any free argument registers and
12583 reg a4 contains the return address, we must move it. */
12584 if (regs_available_for_popping == 0
12585 && reg_containing_return_addr == LAST_ARG_REGNUM)
12587 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12588 reg_containing_return_addr = LR_REGNUM;
12590 else if (size > 12)
12592 /* Register a4 is being used to hold part of the return value,
12593 but we have dire need of a free, low register. */
12596 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12599 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12601 /* The fourth argument register is available. */
12602 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12608 /* Pop as many registers as we can. */
12609 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12610 regs_available_for_popping);
12612 /* Process the registers we popped. */
12613 if (reg_containing_return_addr == -1)
12615 /* The return address was popped into the lowest numbered register. */
12616 regs_to_pop &= ~(1 << LR_REGNUM);
12618 reg_containing_return_addr =
12619 number_of_first_bit_set (regs_available_for_popping);
12621 /* Remove this register for the mask of available registers, so that
12622 the return address will not be corrupted by further pops. */
12623 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12626 /* If we popped other registers then handle them here. */
12627 if (regs_available_for_popping)
12631 /* Work out which register currently contains the frame pointer. */
12632 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12634 /* Move it into the correct place. */
12635 asm_fprintf (f, "\tmov\t%r, %r\n",
12636 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12638 /* (Temporarily) remove it from the mask of popped registers. */
12639 regs_available_for_popping &= ~(1 << frame_pointer);
12640 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12642 if (regs_available_for_popping)
12646 /* We popped the stack pointer as well,
12647 find the register that contains it. */
12648 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12650 /* Move it into the stack register. */
12651 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12653 /* At this point we have popped all necessary registers, so
12654 do not worry about restoring regs_available_for_popping
12655 to its correct value:
12657 assert (pops_needed == 0)
12658 assert (regs_available_for_popping == (1 << frame_pointer))
12659 assert (regs_to_pop == (1 << STACK_POINTER)) */
12663 /* Since we have just move the popped value into the frame
12664 pointer, the popping register is available for reuse, and
12665 we know that we still have the stack pointer left to pop. */
12666 regs_available_for_popping |= (1 << frame_pointer);
12670 /* If we still have registers left on the stack, but we no longer have
12671 any registers into which we can pop them, then we must move the return
12672 address into the link register and make available the register that
12674 if (regs_available_for_popping == 0 && pops_needed > 0)
12676 regs_available_for_popping |= 1 << reg_containing_return_addr;
12678 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12679 reg_containing_return_addr);
12681 reg_containing_return_addr = LR_REGNUM;
12684 /* If we have registers left on the stack then pop some more.
12685 We know that at most we will want to pop FP and SP. */
12686 if (pops_needed > 0)
12691 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12692 regs_available_for_popping);
12694 /* We have popped either FP or SP.
12695 Move whichever one it is into the correct register. */
12696 popped_into = number_of_first_bit_set (regs_available_for_popping);
12697 move_to = number_of_first_bit_set (regs_to_pop);
12699 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12701 regs_to_pop &= ~(1 << move_to);
12706 /* If we still have not popped everything then we must have only
12707 had one register available to us and we are now popping the SP. */
12708 if (pops_needed > 0)
12712 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12713 regs_available_for_popping);
12715 popped_into = number_of_first_bit_set (regs_available_for_popping);
12717 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12719 assert (regs_to_pop == (1 << STACK_POINTER))
12720 assert (pops_needed == 1)
12724 /* If necessary restore the a4 register. */
12727 if (reg_containing_return_addr != LR_REGNUM)
12729 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12730 reg_containing_return_addr = LR_REGNUM;
12733 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12737 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12739 /* Return to caller. */
12740 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12743 /* Emit code to push or pop registers to or from the stack. F is the
12744 assembly file. MASK is the registers to push or pop. PUSH is
12745 nonzero if we should push, and zero if we should pop. For debugging
12746 output, if pushing, adjust CFA_OFFSET by the amount of space added
12747 to the stack. REAL_REGS should have the same number of bits set as
12748 MASK, and will be used instead (in the same order) to describe which
12749 registers were saved - this is used to mark the save slots when we
12750 push high registers after moving them to low registers. */
12752 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12755 int lo_mask = mask & 0xFF;
12756 int pushed_words = 0;
12758 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12760 /* Special case. Do not generate a POP PC statement here, do it in
12762 thumb_exit (f, -1, NULL_RTX);
12766 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12768 /* Look at the low registers first. */
12769 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12773 asm_fprintf (f, "%r", regno);
12775 if ((lo_mask & ~1) != 0)
12782 if (push && (mask & (1 << LR_REGNUM)))
12784 /* Catch pushing the LR. */
12788 asm_fprintf (f, "%r", LR_REGNUM);
12792 else if (!push && (mask & (1 << PC_REGNUM)))
12794 /* Catch popping the PC. */
12795 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12797 /* The PC is never poped directly, instead
12798 it is popped into r3 and then BX is used. */
12799 fprintf (f, "}\n");
12801 thumb_exit (f, -1, NULL_RTX);
12810 asm_fprintf (f, "%r", PC_REGNUM);
12814 fprintf (f, "}\n");
12816 if (push && pushed_words && dwarf2out_do_frame ())
12818 char *l = dwarf2out_cfi_label ();
12819 int pushed_mask = real_regs;
12821 *cfa_offset += pushed_words * 4;
12822 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12825 pushed_mask = real_regs;
12826 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12828 if (pushed_mask & 1)
12829 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12835 thumb_final_prescan_insn (rtx insn)
12837 if (flag_print_asm_name)
12838 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12839 INSN_ADDRESSES (INSN_UID (insn)));
12843 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12845 unsigned HOST_WIDE_INT mask = 0xff;
12848 if (val == 0) /* XXX */
12851 for (i = 0; i < 25; i++)
12852 if ((val & (mask << i)) == val)
12858 /* Returns nonzero if the current function contains,
12859 or might contain a far jump. */
12861 thumb_far_jump_used_p (void)
12865 /* This test is only important for leaf functions. */
12866 /* assert (!leaf_function_p ()); */
12868 /* If we have already decided that far jumps may be used,
12869 do not bother checking again, and always return true even if
12870 it turns out that they are not being used. Once we have made
12871 the decision that far jumps are present (and that hence the link
12872 register will be pushed onto the stack) we cannot go back on it. */
12873 if (cfun->machine->far_jump_used)
12876 /* If this function is not being called from the prologue/epilogue
12877 generation code then it must be being called from the
12878 INITIAL_ELIMINATION_OFFSET macro. */
12879 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12881 /* In this case we know that we are being asked about the elimination
12882 of the arg pointer register. If that register is not being used,
12883 then there are no arguments on the stack, and we do not have to
12884 worry that a far jump might force the prologue to push the link
12885 register, changing the stack offsets. In this case we can just
12886 return false, since the presence of far jumps in the function will
12887 not affect stack offsets.
12889 If the arg pointer is live (or if it was live, but has now been
12890 eliminated and so set to dead) then we do have to test to see if
12891 the function might contain a far jump. This test can lead to some
12892 false negatives, since before reload is completed, then length of
12893 branch instructions is not known, so gcc defaults to returning their
12894 longest length, which in turn sets the far jump attribute to true.
12896 A false negative will not result in bad code being generated, but it
12897 will result in a needless push and pop of the link register. We
12898 hope that this does not occur too often.
12900 If we need doubleword stack alignment this could affect the other
12901 elimination offsets so we can't risk getting it wrong. */
12902 if (regs_ever_live [ARG_POINTER_REGNUM])
12903 cfun->machine->arg_pointer_live = 1;
12904 else if (!cfun->machine->arg_pointer_live)
12908 /* Check to see if the function contains a branch
12909 insn with the far jump attribute set. */
12910 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12912 if (GET_CODE (insn) == JUMP_INSN
12913 /* Ignore tablejump patterns. */
12914 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12915 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12916 && get_attr_far_jump (insn) == FAR_JUMP_YES
12919 /* Record the fact that we have decided that
12920 the function does use far jumps. */
12921 cfun->machine->far_jump_used = 1;
12929 /* Return nonzero if FUNC must be entered in ARM mode. */
12931 is_called_in_ARM_mode (tree func)
12933 if (TREE_CODE (func) != FUNCTION_DECL)
12936 /* Ignore the problem about functions whoes address is taken. */
12937 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12941 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12947 /* The bits which aren't usefully expanded as rtl. */
12949 thumb_unexpanded_epilogue (void)
12952 int live_regs_mask = 0;
12953 int high_regs_pushed = 0;
12954 int had_to_push_lr;
12955 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12957 if (return_used_this_function)
12960 if (IS_NAKED (arm_current_func_type ()))
12963 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12964 if (THUMB_REG_PUSHED_P (regno))
12965 live_regs_mask |= 1 << regno;
12967 for (regno = 8; regno < 13; regno++)
12968 if (THUMB_REG_PUSHED_P (regno))
12969 high_regs_pushed++;
12971 /* The prolog may have pushed some high registers to use as
12972 work registers. eg the testsuite file:
12973 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12974 compiles to produce:
12975 push {r4, r5, r6, r7, lr}
12979 as part of the prolog. We have to undo that pushing here. */
12981 if (high_regs_pushed)
12983 int mask = live_regs_mask;
12988 /* If we can deduce the registers used from the function's return value.
12989 This is more reliable that examining regs_ever_live[] because that
12990 will be set if the register is ever used in the function, not just if
12991 the register is used to hold a return value. */
12993 if (current_function_return_rtx != 0)
12994 mode = GET_MODE (current_function_return_rtx);
12996 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12998 size = GET_MODE_SIZE (mode);
13000 /* Unless we are returning a type of size > 12 register r3 is
13006 /* Oh dear! We have no low registers into which we can pop
13009 ("no low registers available for popping high registers");
13011 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13012 if (THUMB_REG_PUSHED_P (next_hi_reg))
13015 while (high_regs_pushed)
13017 /* Find lo register(s) into which the high register(s) can
13019 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13021 if (mask & (1 << regno))
13022 high_regs_pushed--;
13023 if (high_regs_pushed == 0)
13027 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13029 /* Pop the values into the low register(s). */
13030 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13032 /* Move the value(s) into the high registers. */
13033 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13035 if (mask & (1 << regno))
13037 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13040 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13041 if (THUMB_REG_PUSHED_P (next_hi_reg))
13048 had_to_push_lr = (live_regs_mask || thumb_force_lr_save ());
13050 if (TARGET_BACKTRACE
13051 && ((live_regs_mask & 0xFF) == 0)
13052 && regs_ever_live [LAST_ARG_REGNUM] != 0)
13054 /* The stack backtrace structure creation code had to
13055 push R7 in order to get a work register, so we pop
13057 live_regs_mask |= (1 << LAST_LO_REGNUM);
13060 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13063 && !is_called_in_ARM_mode (current_function_decl)
13065 live_regs_mask |= 1 << PC_REGNUM;
13067 /* Either no argument registers were pushed or a backtrace
13068 structure was created which includes an adjusted stack
13069 pointer, so just pop everything. */
13070 if (live_regs_mask)
13071 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13075 thumb_exit (asm_out_file, 2, eh_ofs);
13076 /* We have either just popped the return address into the
13077 PC or it is was kept in LR for the entire function or
13078 it is still on the stack because we do not want to
13079 return by doing a pop {pc}. */
13080 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13081 thumb_exit (asm_out_file,
13083 && is_called_in_ARM_mode (current_function_decl)) ?
13084 -1 : LR_REGNUM, NULL_RTX);
13088 /* Pop everything but the return address. */
13089 live_regs_mask &= ~(1 << PC_REGNUM);
13091 if (live_regs_mask)
13092 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13095 if (had_to_push_lr)
13096 /* Get the return address into a temporary register. */
13097 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13098 1 << LAST_ARG_REGNUM);
13100 /* Remove the argument registers that were pushed onto the stack. */
13101 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13102 SP_REGNUM, SP_REGNUM,
13103 current_function_pretend_args_size);
13106 thumb_exit (asm_out_file, 2, eh_ofs);
13108 thumb_exit (asm_out_file,
13109 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13115 /* Functions to save and restore machine-specific function data. */
13116 static struct machine_function *
13117 arm_init_machine_status (void)
13119 struct machine_function *machine;
13120 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13122 #if ARM_FT_UNKNOWN != 0
13123 machine->func_type = ARM_FT_UNKNOWN;
13128 /* Return an RTX indicating where the return address to the
13129 calling function can be found. */
13131 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13136 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13139 /* Do anything needed before RTL is emitted for each function. */
13141 arm_init_expanders (void)
13143 /* Arrange to initialize and mark the machine per-function status. */
13144 init_machine_status = arm_init_machine_status;
13148 /* Like arm_compute_initial_elimination offset. Simpler because
13149 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13152 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13154 arm_stack_offsets *offsets;
13156 offsets = arm_get_frame_offsets ();
13160 case ARG_POINTER_REGNUM:
13163 case STACK_POINTER_REGNUM:
13164 return offsets->outgoing_args - offsets->saved_args;
13166 case FRAME_POINTER_REGNUM:
13167 return offsets->soft_frame - offsets->saved_args;
13169 case THUMB_HARD_FRAME_POINTER_REGNUM:
13170 case ARM_HARD_FRAME_POINTER_REGNUM:
13171 return offsets->saved_regs - offsets->saved_args;
13178 case FRAME_POINTER_REGNUM:
13181 case STACK_POINTER_REGNUM:
13182 return offsets->outgoing_args - offsets->soft_frame;
13184 case THUMB_HARD_FRAME_POINTER_REGNUM:
13185 case ARM_HARD_FRAME_POINTER_REGNUM:
13186 return offsets->saved_regs - offsets->soft_frame;
13199 /* Generate the rest of a function's prologue. */
13201 thumb_expand_prologue (void)
13205 HOST_WIDE_INT amount;
13206 arm_stack_offsets *offsets;
13207 unsigned long func_type;
13210 func_type = arm_current_func_type ();
13212 /* Naked functions don't have prologues. */
13213 if (IS_NAKED (func_type))
13216 if (IS_INTERRUPT (func_type))
13218 error ("interrupt Service Routines cannot be coded in Thumb mode");
13222 offsets = arm_get_frame_offsets ();
13224 if (frame_pointer_needed)
13226 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13227 stack_pointer_rtx));
13228 RTX_FRAME_RELATED_P (insn) = 1;
13231 amount = offsets->outgoing_args - offsets->saved_regs;
13236 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13237 GEN_INT (- amount)));
13238 RTX_FRAME_RELATED_P (insn) = 1;
13244 /* The stack decrement is too big for an immediate value in a single
13245 insn. In theory we could issue multiple subtracts, but after
13246 three of them it becomes more space efficient to place the full
13247 value in the constant pool and load into a register. (Also the
13248 ARM debugger really likes to see only one stack decrement per
13249 function). So instead we look for a scratch register into which
13250 we can load the decrement, and then we subtract this from the
13251 stack pointer. Unfortunately on the thumb the only available
13252 scratch registers are the argument registers, and we cannot use
13253 these as they may hold arguments to the function. Instead we
13254 attempt to locate a call preserved register which is used by this
13255 function. If we can find one, then we know that it will have
13256 been pushed at the start of the prologue and so we can corrupt
13258 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13259 if (THUMB_REG_PUSHED_P (regno)
13260 && !(frame_pointer_needed
13261 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13264 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13266 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13268 /* Choose an arbitrary, non-argument low register. */
13269 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13271 /* Save it by copying it into a high, scratch register. */
13272 emit_insn (gen_movsi (spare, reg));
13273 /* Add a USE to stop propagate_one_insn() from barfing. */
13274 emit_insn (gen_prologue_use (spare));
13276 /* Decrement the stack. */
13277 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13278 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13279 stack_pointer_rtx, reg));
13280 RTX_FRAME_RELATED_P (insn) = 1;
13281 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13282 plus_constant (stack_pointer_rtx,
13283 GEN_INT (- amount)));
13284 RTX_FRAME_RELATED_P (dwarf) = 1;
13286 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13289 /* Restore the low register's original value. */
13290 emit_insn (gen_movsi (reg, spare));
13292 /* Emit a USE of the restored scratch register, so that flow
13293 analysis will not consider the restore redundant. The
13294 register won't be used again in this function and isn't
13295 restored by the epilogue. */
13296 emit_insn (gen_prologue_use (reg));
13300 reg = gen_rtx_REG (SImode, regno);
13302 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13304 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13305 stack_pointer_rtx, reg));
13306 RTX_FRAME_RELATED_P (insn) = 1;
13307 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13308 plus_constant (stack_pointer_rtx,
13309 GEN_INT (- amount)));
13310 RTX_FRAME_RELATED_P (dwarf) = 1;
13312 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13316 /* If the frame pointer is needed, emit a special barrier that
13317 will prevent the scheduler from moving stores to the frame
13318 before the stack adjustment. */
13319 if (frame_pointer_needed)
13320 emit_insn (gen_stack_tie (stack_pointer_rtx,
13321 hard_frame_pointer_rtx));
13324 if (current_function_profile || TARGET_NO_SCHED_PRO)
13325 emit_insn (gen_blockage ());
13327 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13328 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13330 if (THUMB_REG_PUSHED_P (regno))
13332 cfun->machine->lr_save_eliminated = 0;
13337 /* If the link register is being kept alive, with the return address in it,
13338 then make sure that it does not get reused by the ce2 pass. */
13339 if (cfun->machine->lr_save_eliminated)
13340 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13344 thumb_expand_epilogue (void)
13346 HOST_WIDE_INT amount;
13347 arm_stack_offsets *offsets;
13350 /* Naked functions don't have prologues. */
13351 if (IS_NAKED (arm_current_func_type ()))
13354 offsets = arm_get_frame_offsets ();
13355 amount = offsets->outgoing_args - offsets->saved_regs;
13357 if (frame_pointer_needed)
13358 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13362 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13363 GEN_INT (amount)));
13366 /* r3 is always free in the epilogue. */
13367 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13369 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13370 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13374 /* Emit a USE (stack_pointer_rtx), so that
13375 the stack adjustment will not be deleted. */
13376 emit_insn (gen_prologue_use (stack_pointer_rtx));
13378 if (current_function_profile || TARGET_NO_SCHED_PRO)
13379 emit_insn (gen_blockage ());
13381 /* Emit a clobber for each insn that will be restored in the epilogue,
13382 so that flow2 will get register lifetimes correct. */
13383 for (regno = 0; regno < 13; regno++)
13384 if (regs_ever_live[regno] && !call_used_regs[regno])
13385 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13387 if (! regs_ever_live[LR_REGNUM])
13388 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13392 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13394 int live_regs_mask = 0;
13395 int high_regs_pushed = 0;
13396 int cfa_offset = 0;
13399 if (IS_NAKED (arm_current_func_type ()))
13402 if (is_called_in_ARM_mode (current_function_decl))
13406 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13408 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13410 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13412 /* Generate code sequence to switch us into Thumb mode. */
13413 /* The .code 32 directive has already been emitted by
13414 ASM_DECLARE_FUNCTION_NAME. */
13415 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13416 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13418 /* Generate a label, so that the debugger will notice the
13419 change in instruction sets. This label is also used by
13420 the assembler to bypass the ARM code when this function
13421 is called from a Thumb encoded function elsewhere in the
13422 same file. Hence the definition of STUB_NAME here must
13423 agree with the definition in gas/config/tc-arm.c. */
13425 #define STUB_NAME ".real_start_of"
13427 fprintf (f, "\t.code\t16\n");
13429 if (arm_dllexport_name_p (name))
13430 name = arm_strip_name_encoding (name);
13432 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13433 fprintf (f, "\t.thumb_func\n");
13434 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13437 if (current_function_pretend_args_size)
13439 if (cfun->machine->uses_anonymous_args)
13443 fprintf (f, "\tpush\t{");
13445 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13447 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13448 regno <= LAST_ARG_REGNUM;
13450 asm_fprintf (f, "%r%s", regno,
13451 regno == LAST_ARG_REGNUM ? "" : ", ");
13453 fprintf (f, "}\n");
13456 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13457 SP_REGNUM, SP_REGNUM,
13458 current_function_pretend_args_size);
13460 /* We don't need to record the stores for unwinding (would it
13461 help the debugger any if we did?), but record the change in
13462 the stack pointer. */
13463 if (dwarf2out_do_frame ())
13465 char *l = dwarf2out_cfi_label ();
13466 cfa_offset = cfa_offset + current_function_pretend_args_size;
13467 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13471 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13472 if (THUMB_REG_PUSHED_P (regno))
13473 live_regs_mask |= 1 << regno;
13475 if (live_regs_mask || thumb_force_lr_save ())
13476 live_regs_mask |= 1 << LR_REGNUM;
13478 if (TARGET_BACKTRACE)
13481 int work_register = 0;
13484 /* We have been asked to create a stack backtrace structure.
13485 The code looks like this:
13489 0 sub SP, #16 Reserve space for 4 registers.
13490 2 push {R7} Get a work register.
13491 4 add R7, SP, #20 Get the stack pointer before the push.
13492 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13493 8 mov R7, PC Get hold of the start of this code plus 12.
13494 10 str R7, [SP, #16] Store it.
13495 12 mov R7, FP Get hold of the current frame pointer.
13496 14 str R7, [SP, #4] Store it.
13497 16 mov R7, LR Get hold of the current return address.
13498 18 str R7, [SP, #12] Store it.
13499 20 add R7, SP, #16 Point at the start of the backtrace structure.
13500 22 mov FP, R7 Put this value into the frame pointer. */
13502 if ((live_regs_mask & 0xFF) == 0)
13504 /* See if the a4 register is free. */
13506 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13507 work_register = LAST_ARG_REGNUM;
13508 else /* We must push a register of our own. */
13509 live_regs_mask |= (1 << LAST_LO_REGNUM);
13512 if (work_register == 0)
13514 /* Select a register from the list that will be pushed to
13515 use as our work register. */
13516 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13517 if ((1 << work_register) & live_regs_mask)
13522 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13523 SP_REGNUM, SP_REGNUM);
13525 if (dwarf2out_do_frame ())
13527 char *l = dwarf2out_cfi_label ();
13528 cfa_offset = cfa_offset + 16;
13529 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13532 if (live_regs_mask)
13533 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13535 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13536 if (wr & live_regs_mask)
13539 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13540 offset + 16 + current_function_pretend_args_size);
13542 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13545 /* Make sure that the instruction fetching the PC is in the right place
13546 to calculate "start of backtrace creation code + 12". */
13547 if (live_regs_mask)
13549 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13550 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13552 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13553 ARM_HARD_FRAME_POINTER_REGNUM);
13554 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13559 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13560 ARM_HARD_FRAME_POINTER_REGNUM);
13561 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13563 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13564 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13568 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13569 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13571 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13573 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13574 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13576 else if (live_regs_mask)
13577 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13579 for (regno = 8; regno < 13; regno++)
13580 if (THUMB_REG_PUSHED_P (regno))
13581 high_regs_pushed++;
13583 if (high_regs_pushed)
13585 int pushable_regs = 0;
13586 int mask = live_regs_mask & 0xff;
13589 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13590 if (THUMB_REG_PUSHED_P (next_hi_reg))
13593 pushable_regs = mask;
13595 if (pushable_regs == 0)
13597 /* Desperation time -- this probably will never happen. */
13598 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13599 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13600 mask = 1 << LAST_ARG_REGNUM;
13603 while (high_regs_pushed > 0)
13605 int real_regs_mask = 0;
13607 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13609 if (mask & (1 << regno))
13611 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13613 high_regs_pushed--;
13614 real_regs_mask |= (1 << next_hi_reg);
13616 if (high_regs_pushed)
13618 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13620 if (THUMB_REG_PUSHED_P (next_hi_reg))
13625 mask &= ~((1 << regno) - 1);
13631 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13634 if (pushable_regs == 0
13635 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13636 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13640 /* Handle the case of a double word load into a low register from
13641 a computed memory address. The computed address may involve a
13642 register which is overwritten by the load. */
13644 thumb_load_double_from_address (rtx *operands)
13652 if (GET_CODE (operands[0]) != REG)
13655 if (GET_CODE (operands[1]) != MEM)
13658 /* Get the memory address. */
13659 addr = XEXP (operands[1], 0);
13661 /* Work out how the memory address is computed. */
13662 switch (GET_CODE (addr))
13665 operands[2] = gen_rtx_MEM (SImode,
13666 plus_constant (XEXP (operands[1], 0), 4));
13668 if (REGNO (operands[0]) == REGNO (addr))
13670 output_asm_insn ("ldr\t%H0, %2", operands);
13671 output_asm_insn ("ldr\t%0, %1", operands);
13675 output_asm_insn ("ldr\t%0, %1", operands);
13676 output_asm_insn ("ldr\t%H0, %2", operands);
13681 /* Compute <address> + 4 for the high order load. */
13682 operands[2] = gen_rtx_MEM (SImode,
13683 plus_constant (XEXP (operands[1], 0), 4));
13685 output_asm_insn ("ldr\t%0, %1", operands);
13686 output_asm_insn ("ldr\t%H0, %2", operands);
13690 arg1 = XEXP (addr, 0);
13691 arg2 = XEXP (addr, 1);
13693 if (CONSTANT_P (arg1))
13694 base = arg2, offset = arg1;
13696 base = arg1, offset = arg2;
13698 if (GET_CODE (base) != REG)
13701 /* Catch the case of <address> = <reg> + <reg> */
13702 if (GET_CODE (offset) == REG)
13704 int reg_offset = REGNO (offset);
13705 int reg_base = REGNO (base);
13706 int reg_dest = REGNO (operands[0]);
13708 /* Add the base and offset registers together into the
13709 higher destination register. */
13710 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13711 reg_dest + 1, reg_base, reg_offset);
13713 /* Load the lower destination register from the address in
13714 the higher destination register. */
13715 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13716 reg_dest, reg_dest + 1);
13718 /* Load the higher destination register from its own address
13720 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13721 reg_dest + 1, reg_dest + 1);
13725 /* Compute <address> + 4 for the high order load. */
13726 operands[2] = gen_rtx_MEM (SImode,
13727 plus_constant (XEXP (operands[1], 0), 4));
13729 /* If the computed address is held in the low order register
13730 then load the high order register first, otherwise always
13731 load the low order register first. */
13732 if (REGNO (operands[0]) == REGNO (base))
13734 output_asm_insn ("ldr\t%H0, %2", operands);
13735 output_asm_insn ("ldr\t%0, %1", operands);
13739 output_asm_insn ("ldr\t%0, %1", operands);
13740 output_asm_insn ("ldr\t%H0, %2", operands);
13746 /* With no registers to worry about we can just load the value
13748 operands[2] = gen_rtx_MEM (SImode,
13749 plus_constant (XEXP (operands[1], 0), 4));
13751 output_asm_insn ("ldr\t%H0, %2", operands);
13752 output_asm_insn ("ldr\t%0, %1", operands);
13764 thumb_output_move_mem_multiple (int n, rtx *operands)
13771 if (REGNO (operands[4]) > REGNO (operands[5]))
13774 operands[4] = operands[5];
13777 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13778 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13782 if (REGNO (operands[4]) > REGNO (operands[5]))
13785 operands[4] = operands[5];
13788 if (REGNO (operands[5]) > REGNO (operands[6]))
13791 operands[5] = operands[6];
13794 if (REGNO (operands[4]) > REGNO (operands[5]))
13797 operands[4] = operands[5];
13801 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13802 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13812 /* Routines for generating rtl. */
13814 thumb_expand_movstrqi (rtx *operands)
13816 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13817 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13818 HOST_WIDE_INT len = INTVAL (operands[2]);
13819 HOST_WIDE_INT offset = 0;
13823 emit_insn (gen_movmem12b (out, in, out, in));
13829 emit_insn (gen_movmem8b (out, in, out, in));
13835 rtx reg = gen_reg_rtx (SImode);
13836 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13837 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13844 rtx reg = gen_reg_rtx (HImode);
13845 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13846 plus_constant (in, offset))));
13847 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13855 rtx reg = gen_reg_rtx (QImode);
13856 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13857 plus_constant (in, offset))));
13858 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13864 thumb_cmp_operand (rtx op, enum machine_mode mode)
13866 return ((GET_CODE (op) == CONST_INT
13867 && INTVAL (op) < 256
13868 && INTVAL (op) >= 0)
13869 || s_register_operand (op, mode));
13873 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13875 return (GET_CODE (op) == CONST_INT
13877 && INTVAL (op) > -256);
13880 /* Return TRUE if a result can be stored in OP without clobbering the
13881 condition code register. Prior to reload we only accept a
13882 register. After reload we have to be able to handle memory as
13883 well, since a pseudo may not get a hard reg and reload cannot
13884 handle output-reloads on jump insns.
13886 We could possibly handle mem before reload as well, but that might
13887 complicate things with the need to handle increment
13891 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13893 return (s_register_operand (op, mode)
13894 || ((reload_in_progress || reload_completed)
13895 && memory_operand (op, mode)));
13898 /* Handle storing a half-word to memory during reload. */
13900 thumb_reload_out_hi (rtx *operands)
13902 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13905 /* Handle reading a half-word from memory during reload. */
13907 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13912 /* Return the length of a function name prefix
13913 that starts with the character 'c'. */
13915 arm_get_strip_length (int c)
13919 ARM_NAME_ENCODING_LENGTHS
13924 /* Return a pointer to a function's name with any
13925 and all prefix encodings stripped from it. */
13927 arm_strip_name_encoding (const char *name)
13931 while ((skip = arm_get_strip_length (* name)))
13937 /* If there is a '*' anywhere in the name's prefix, then
13938 emit the stripped name verbatim, otherwise prepend an
13939 underscore if leading underscores are being used. */
13941 arm_asm_output_labelref (FILE *stream, const char *name)
13946 while ((skip = arm_get_strip_length (* name)))
13948 verbatim |= (*name == '*');
13953 fputs (name, stream);
13955 asm_fprintf (stream, "%U%s", name);
13960 #ifdef AOF_ASSEMBLER
13961 /* Special functions only needed when producing AOF syntax assembler. */
13965 struct pic_chain * next;
13966 const char * symname;
13969 static struct pic_chain * aof_pic_chain = NULL;
13972 aof_pic_entry (rtx x)
13974 struct pic_chain ** chainp;
13977 if (aof_pic_label == NULL_RTX)
13979 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13982 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13983 offset += 4, chainp = &(*chainp)->next)
13984 if ((*chainp)->symname == XSTR (x, 0))
13985 return plus_constant (aof_pic_label, offset);
13987 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13988 (*chainp)->next = NULL;
13989 (*chainp)->symname = XSTR (x, 0);
13990 return plus_constant (aof_pic_label, offset);
13994 aof_dump_pic_table (FILE *f)
13996 struct pic_chain * chain;
13998 if (aof_pic_chain == NULL)
14001 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14002 PIC_OFFSET_TABLE_REGNUM,
14003 PIC_OFFSET_TABLE_REGNUM);
14004 fputs ("|x$adcons|\n", f);
14006 for (chain = aof_pic_chain; chain; chain = chain->next)
14008 fputs ("\tDCD\t", f);
14009 assemble_name (f, chain->symname);
14014 int arm_text_section_count = 1;
14017 aof_text_section (void )
14019 static char buf[100];
14020 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14021 arm_text_section_count++);
14023 strcat (buf, ", PIC, REENTRANT");
14027 static int arm_data_section_count = 1;
14030 aof_data_section (void)
14032 static char buf[100];
14033 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14037 /* The AOF assembler is religiously strict about declarations of
14038 imported and exported symbols, so that it is impossible to declare
14039 a function as imported near the beginning of the file, and then to
14040 export it later on. It is, however, possible to delay the decision
14041 until all the functions in the file have been compiled. To get
14042 around this, we maintain a list of the imports and exports, and
14043 delete from it any that are subsequently defined. At the end of
14044 compilation we spit the remainder of the list out before the END
14049 struct import * next;
14053 static struct import * imports_list = NULL;
14056 aof_add_import (const char *name)
14058 struct import * new;
14060 for (new = imports_list; new; new = new->next)
14061 if (new->name == name)
14064 new = (struct import *) xmalloc (sizeof (struct import));
14065 new->next = imports_list;
14066 imports_list = new;
14071 aof_delete_import (const char *name)
14073 struct import ** old;
14075 for (old = &imports_list; *old; old = & (*old)->next)
14077 if ((*old)->name == name)
14079 *old = (*old)->next;
14085 int arm_main_function = 0;
14088 aof_dump_imports (FILE *f)
14090 /* The AOF assembler needs this to cause the startup code to be extracted
14091 from the library. Brining in __main causes the whole thing to work
14093 if (arm_main_function)
14096 fputs ("\tIMPORT __main\n", f);
14097 fputs ("\tDCD __main\n", f);
14100 /* Now dump the remaining imports. */
14101 while (imports_list)
14103 fprintf (f, "\tIMPORT\t");
14104 assemble_name (f, imports_list->name);
14106 imports_list = imports_list->next;
14111 aof_globalize_label (FILE *stream, const char *name)
14113 default_globalize_label (stream, name);
14114 if (! strcmp (name, "main"))
14115 arm_main_function = 1;
14119 aof_file_start (void)
14121 fputs ("__r0\tRN\t0\n", asm_out_file);
14122 fputs ("__a1\tRN\t0\n", asm_out_file);
14123 fputs ("__a2\tRN\t1\n", asm_out_file);
14124 fputs ("__a3\tRN\t2\n", asm_out_file);
14125 fputs ("__a4\tRN\t3\n", asm_out_file);
14126 fputs ("__v1\tRN\t4\n", asm_out_file);
14127 fputs ("__v2\tRN\t5\n", asm_out_file);
14128 fputs ("__v3\tRN\t6\n", asm_out_file);
14129 fputs ("__v4\tRN\t7\n", asm_out_file);
14130 fputs ("__v5\tRN\t8\n", asm_out_file);
14131 fputs ("__v6\tRN\t9\n", asm_out_file);
14132 fputs ("__sl\tRN\t10\n", asm_out_file);
14133 fputs ("__fp\tRN\t11\n", asm_out_file);
14134 fputs ("__ip\tRN\t12\n", asm_out_file);
14135 fputs ("__sp\tRN\t13\n", asm_out_file);
14136 fputs ("__lr\tRN\t14\n", asm_out_file);
14137 fputs ("__pc\tRN\t15\n", asm_out_file);
14138 fputs ("__f0\tFN\t0\n", asm_out_file);
14139 fputs ("__f1\tFN\t1\n", asm_out_file);
14140 fputs ("__f2\tFN\t2\n", asm_out_file);
14141 fputs ("__f3\tFN\t3\n", asm_out_file);
14142 fputs ("__f4\tFN\t4\n", asm_out_file);
14143 fputs ("__f5\tFN\t5\n", asm_out_file);
14144 fputs ("__f6\tFN\t6\n", asm_out_file);
14145 fputs ("__f7\tFN\t7\n", asm_out_file);
14150 aof_file_end (void)
14153 aof_dump_pic_table (asm_out_file);
14154 aof_dump_imports (asm_out_file);
14155 fputs ("\tEND\n", asm_out_file);
14157 #endif /* AOF_ASSEMBLER */
14159 #ifdef OBJECT_FORMAT_ELF
14160 /* Switch to an arbitrary section NAME with attributes as specified
14161 by FLAGS. ALIGN specifies any known alignment requirements for
14162 the section; 0 if the default should be used.
14164 Differs from the default elf version only in the prefix character
14165 used before the section type. */
14168 arm_elf_asm_named_section (const char *name, unsigned int flags)
14170 char flagchars[10], *f = flagchars;
14172 if (! named_section_first_declaration (name))
14174 fprintf (asm_out_file, "\t.section\t%s\n", name);
14178 if (!(flags & SECTION_DEBUG))
14180 if (flags & SECTION_WRITE)
14182 if (flags & SECTION_CODE)
14184 if (flags & SECTION_SMALL)
14186 if (flags & SECTION_MERGE)
14188 if (flags & SECTION_STRINGS)
14190 if (flags & SECTION_TLS)
14194 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14196 if (!(flags & SECTION_NOTYPE))
14200 if (flags & SECTION_BSS)
14205 fprintf (asm_out_file, ",%%%s", type);
14207 if (flags & SECTION_ENTSIZE)
14208 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14211 putc ('\n', asm_out_file);
14216 /* Symbols in the text segment can be accessed without indirecting via the
14217 constant pool; it may take an extra binary operation, but this is still
14218 faster than indirecting via memory. Don't do this when not optimizing,
14219 since we won't be calculating al of the offsets necessary to do this
14223 arm_encode_section_info (tree decl, rtx rtl, int first)
14225 /* This doesn't work with AOF syntax, since the string table may be in
14226 a different AREA. */
14227 #ifndef AOF_ASSEMBLER
14228 if (optimize > 0 && TREE_CONSTANT (decl))
14229 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14232 /* If we are referencing a function that is weak then encode a long call
14233 flag in the function name, otherwise if the function is static or
14234 or known to be defined in this file then encode a short call flag. */
14235 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14237 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14238 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14239 else if (! TREE_PUBLIC (decl))
14240 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14243 #endif /* !ARM_PE */
14246 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14248 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14249 && !strcmp (prefix, "L"))
14251 arm_ccfsm_state = 0;
14252 arm_target_insn = NULL;
14254 default_internal_label (stream, prefix, labelno);
14257 /* Output code to add DELTA to the first argument, and then jump
14258 to FUNCTION. Used for C++ multiple inheritance. */
14260 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14261 HOST_WIDE_INT delta,
14262 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14265 static int thunk_label = 0;
14267 int mi_delta = delta;
14268 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14270 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14273 mi_delta = - mi_delta;
14276 int labelno = thunk_label++;
14277 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14278 fputs ("\tldr\tr12, ", file);
14279 assemble_name (file, label);
14280 fputc ('\n', file);
14282 while (mi_delta != 0)
14284 if ((mi_delta & (3 << shift)) == 0)
14288 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14289 mi_op, this_regno, this_regno,
14290 mi_delta & (0xff << shift));
14291 mi_delta &= ~(0xff << shift);
14297 fprintf (file, "\tbx\tr12\n");
14298 ASM_OUTPUT_ALIGN (file, 2);
14299 assemble_name (file, label);
14300 fputs (":\n", file);
14301 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14305 fputs ("\tb\t", file);
14306 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14307 if (NEED_PLT_RELOC)
14308 fputs ("(PLT)", file);
14309 fputc ('\n', file);
14314 arm_emit_vector_const (FILE *file, rtx x)
14317 const char * pattern;
14319 if (GET_CODE (x) != CONST_VECTOR)
14322 switch (GET_MODE (x))
14324 case V2SImode: pattern = "%08x"; break;
14325 case V4HImode: pattern = "%04x"; break;
14326 case V8QImode: pattern = "%02x"; break;
14330 fprintf (file, "0x");
14331 for (i = CONST_VECTOR_NUNITS (x); i--;)
14335 element = CONST_VECTOR_ELT (x, i);
14336 fprintf (file, pattern, INTVAL (element));
14343 arm_output_load_gr (rtx *operands)
14350 if (GET_CODE (operands [1]) != MEM
14351 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14352 || GET_CODE (reg = XEXP (sum, 0)) != REG
14353 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14354 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14355 return "wldrw%?\t%0, %1";
14357 /* Fix up an out-of-range load of a GR register. */
14358 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14359 wcgr = operands[0];
14361 output_asm_insn ("ldr%?\t%0, %1", operands);
14363 operands[0] = wcgr;
14365 output_asm_insn ("tmcr%?\t%0, %1", operands);
14366 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14372 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14373 int incoming ATTRIBUTE_UNUSED)
14376 /* FIXME: The ARM backend has special code to handle structure
14377 returns, and will reserve its own hidden first argument. So
14378 if this macro is enabled a *second* hidden argument will be
14379 reserved, which will break binary compatibility with old
14380 toolchains and also thunk handling. One day this should be
14384 /* Register in which address to store a structure value
14385 is passed to a function. */
14386 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14390 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14392 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14393 named arg and all anonymous args onto the stack.
14394 XXX I know the prologue shouldn't be pushing registers, but it is faster
14398 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14399 enum machine_mode mode ATTRIBUTE_UNUSED,
14400 tree type ATTRIBUTE_UNUSED,
14402 int second_time ATTRIBUTE_UNUSED)
14404 cfun->machine->uses_anonymous_args = 1;
14405 if (cum->nregs < NUM_ARG_REGS)
14406 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14409 /* Return nonzero if the CONSUMER instruction (a store) does not need
14410 PRODUCER's value to calculate the address. */
14413 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14415 rtx value = PATTERN (producer);
14416 rtx addr = PATTERN (consumer);
14418 if (GET_CODE (value) == COND_EXEC)
14419 value = COND_EXEC_CODE (value);
14420 if (GET_CODE (value) == PARALLEL)
14421 value = XVECEXP (value, 0, 0);
14422 value = XEXP (value, 0);
14423 if (GET_CODE (addr) == COND_EXEC)
14424 addr = COND_EXEC_CODE (addr);
14425 if (GET_CODE (addr) == PARALLEL)
14426 addr = XVECEXP (addr, 0, 0);
14427 addr = XEXP (addr, 0);
14429 return !reg_overlap_mentioned_p (value, addr);
14432 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14433 have an early register shift value or amount dependency on the
14434 result of PRODUCER. */
14437 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14439 rtx value = PATTERN (producer);
14440 rtx op = PATTERN (consumer);
14443 if (GET_CODE (value) == COND_EXEC)
14444 value = COND_EXEC_CODE (value);
14445 if (GET_CODE (value) == PARALLEL)
14446 value = XVECEXP (value, 0, 0);
14447 value = XEXP (value, 0);
14448 if (GET_CODE (op) == COND_EXEC)
14449 op = COND_EXEC_CODE (op);
14450 if (GET_CODE (op) == PARALLEL)
14451 op = XVECEXP (op, 0, 0);
14454 early_op = XEXP (op, 0);
14455 /* This is either an actual independent shift, or a shift applied to
14456 the first operand of another operation. We want the whole shift
14458 if (GET_CODE (early_op) == REG)
14461 return !reg_overlap_mentioned_p (value, early_op);
14464 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14465 have an early register shift value dependency on the result of
14469 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14471 rtx value = PATTERN (producer);
14472 rtx op = PATTERN (consumer);
14475 if (GET_CODE (value) == COND_EXEC)
14476 value = COND_EXEC_CODE (value);
14477 if (GET_CODE (value) == PARALLEL)
14478 value = XVECEXP (value, 0, 0);
14479 value = XEXP (value, 0);
14480 if (GET_CODE (op) == COND_EXEC)
14481 op = COND_EXEC_CODE (op);
14482 if (GET_CODE (op) == PARALLEL)
14483 op = XVECEXP (op, 0, 0);
14486 early_op = XEXP (op, 0);
14488 /* This is either an actual independent shift, or a shift applied to
14489 the first operand of another operation. We want the value being
14490 shifted, in either case. */
14491 if (GET_CODE (early_op) != REG)
14492 early_op = XEXP (early_op, 0);
14494 return !reg_overlap_mentioned_p (value, early_op);
14497 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14498 have an early register mult dependency on the result of
14502 arm_no_early_mul_dep (rtx producer, rtx consumer)
14504 rtx value = PATTERN (producer);
14505 rtx op = PATTERN (consumer);
14507 if (GET_CODE (value) == COND_EXEC)
14508 value = COND_EXEC_CODE (value);
14509 if (GET_CODE (value) == PARALLEL)
14510 value = XVECEXP (value, 0, 0);
14511 value = XEXP (value, 0);
14512 if (GET_CODE (op) == COND_EXEC)
14513 op = COND_EXEC_CODE (op);
14514 if (GET_CODE (op) == PARALLEL)
14515 op = XVECEXP (op, 0, 0);
14518 return (GET_CODE (op) == PLUS
14519 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14523 /* We can't rely on the caller doing the proper promotion when
14524 using APCS or ATPCS. */
14527 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14529 return !TARGET_AAPCS_BASED;
14533 /* AAPCS based ABIs use short enums by default. */
14536 arm_default_short_enums (void)
14538 return TARGET_AAPCS_BASED;
14542 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14545 arm_align_anon_bitfield (void)
14547 return TARGET_AAPCS_BASED;
14551 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14554 arm_cxx_guard_type (void)
14556 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14560 /* The EABI says test the least significan bit of a guard variable. */
14563 arm_cxx_guard_mask_bit (void)
14565 return TARGET_AAPCS_BASED;