1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
75 static rtx emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
81 static arm_cc get_arm_condition_code (rtx);
82 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
83 static rtx is_jump_table (rtx);
84 static const char *output_multi_immediate (rtx *, const char *, const char *,
86 static const char *shift_op (rtx, HOST_WIDE_INT *);
87 static struct machine_function *arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static int arm_comp_type_attributes (tree, tree);
119 static void arm_set_default_type_attributes (tree);
120 static int arm_adjust_cost (rtx, rtx, rtx, int);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_size_rtx_costs (rtx, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx, int, int, int *);
133 static int arm_address_cost (rtx);
134 static bool arm_memory_load_p (rtx);
135 static bool arm_cirrus_insn_p (rtx);
136 static void cirrus_reorg (rtx);
137 static void arm_init_builtins (void);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx safe_vector_operand (rtx, enum machine_mode);
141 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
142 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void emit_constant_insn (rtx cond, rtx pattern);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx, int);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx arm_struct_value_rtx (tree, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
168 enum machine_mode, tree, bool);
169 static bool arm_promote_prototypes (tree);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree);
173 static bool arm_must_pass_in_stack (enum machine_mode, tree);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx);
176 static bool arm_output_ttype (rtx);
179 static tree arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree arm_get_cookie_size (tree);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
192 /* Initialize the GCC target structure. */
193 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
194 #undef TARGET_MERGE_DECL_ATTRIBUTES
195 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
198 #undef TARGET_ATTRIBUTE_TABLE
199 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
201 #undef TARGET_ASM_FILE_END
202 #define TARGET_ASM_FILE_END arm_file_end
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\tDCB\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
211 #undef TARGET_ASM_GLOBALIZE_LABEL
212 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START aof_file_start
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END aof_file_end
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP NULL
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER arm_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
230 #undef TARGET_DEFAULT_TARGET_FLAGS
231 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
232 #undef TARGET_HANDLE_OPTION
233 #define TARGET_HANDLE_OPTION arm_handle_option
235 #undef TARGET_COMP_TYPE_ATTRIBUTES
236 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
238 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
239 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
244 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
248 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
251 #undef TARGET_STRIP_NAME_ENCODING
252 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
254 #undef TARGET_ASM_INTERNAL_LABEL
255 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
260 #undef TARGET_ASM_OUTPUT_MI_THUNK
261 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
265 /* This will be overridden in arm_override_options. */
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST arm_address_cost
271 #undef TARGET_SHIFT_TRUNCATION_MASK
272 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
273 #undef TARGET_VECTOR_MODE_SUPPORTED_P
274 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
276 #undef TARGET_MACHINE_DEPENDENT_REORG
277 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS arm_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
287 #undef TARGET_PROMOTE_FUNCTION_ARGS
288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
289 #undef TARGET_PROMOTE_FUNCTION_RETURN
290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
295 #undef TARGET_ARG_PARTIAL_BYTES
296 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
298 #undef TARGET_STRUCT_VALUE_RTX
299 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
301 #undef TARGET_SETUP_INCOMING_VARARGS
302 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
304 #undef TARGET_DEFAULT_SHORT_ENUMS
305 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
307 #undef TARGET_ALIGN_ANON_BITFIELD
308 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
310 #undef TARGET_CXX_GUARD_TYPE
311 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
313 #undef TARGET_CXX_GUARD_MASK_BIT
314 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
316 #undef TARGET_CXX_GET_COOKIE_SIZE
317 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
319 #undef TARGET_CXX_COOKIE_HAS_SIZE
320 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
322 #undef TARGET_CXX_CDTOR_RETURNS_THIS
323 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
325 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
326 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
328 #undef TARGET_CXX_USE_AEABI_ATEXIT
329 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
331 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
332 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
333 arm_cxx_determine_class_data_visibility
335 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
336 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
338 #undef TARGET_RETURN_IN_MSB
339 #define TARGET_RETURN_IN_MSB arm_return_in_msb
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
344 #ifdef TARGET_UNWIND_INFO
345 #undef TARGET_UNWIND_EMIT
346 #define TARGET_UNWIND_EMIT arm_unwind_emit
348 /* EABI unwinding tables use a different format for the typeinfo tables. */
349 #undef TARGET_ASM_TTYPE
350 #define TARGET_ASM_TTYPE arm_output_ttype
352 #undef TARGET_ARM_EABI_UNWINDER
353 #define TARGET_ARM_EABI_UNWINDER true
354 #endif /* TARGET_UNWIND_INFO */
356 struct gcc_target targetm = TARGET_INITIALIZER;
358 /* Obstack for minipool constant handling. */
359 static struct obstack minipool_obstack;
360 static char * minipool_startobj;
362 /* The maximum number of insns skipped which
363 will be conditionalised if possible. */
364 static int max_insns_skipped = 5;
366 extern FILE * asm_out_file;
368 /* True if we are currently building a constant table. */
369 int making_const_table;
371 /* Define the information needed to generate branch insns. This is
372 stored from the compare operation. */
373 rtx arm_compare_op0, arm_compare_op1;
375 /* The processor for which instructions should be scheduled. */
376 enum processor_type arm_tune = arm_none;
378 /* Which floating point model to use. */
379 enum arm_fp_model arm_fp_model;
381 /* Which floating point hardware is available. */
382 enum fputype arm_fpu_arch;
384 /* Which floating point hardware to schedule for. */
385 enum fputype arm_fpu_tune;
387 /* Whether to use floating point hardware. */
388 enum float_abi_type arm_float_abi;
390 /* Which ABI to use. */
391 enum arm_abi_type arm_abi;
393 /* Used to parse -mstructure_size_boundary command line option. */
394 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
396 /* Used for Thumb call_via trampolines. */
397 rtx thumb_call_via_label[14];
398 static int thumb_call_reg_needed;
400 /* Bit values used to identify processor capabilities. */
401 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
402 #define FL_ARCH3M (1 << 1) /* Extended multiply */
403 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
404 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
405 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
406 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
407 #define FL_THUMB (1 << 6) /* Thumb aware */
408 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
409 #define FL_STRONG (1 << 8) /* StrongARM */
410 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
411 #define FL_XSCALE (1 << 10) /* XScale */
412 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
413 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
414 media instructions. */
415 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
416 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
417 Note: ARM6 & 7 derivatives only. */
419 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
421 #define FL_FOR_ARCH2 0
422 #define FL_FOR_ARCH3 FL_MODE32
423 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
424 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
425 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
426 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
427 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
428 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
429 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
430 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
431 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
432 #define FL_FOR_ARCH6J FL_FOR_ARCH6
433 #define FL_FOR_ARCH6K FL_FOR_ARCH6
434 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
435 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
437 /* The bits in this mask specify which
438 instructions we are allowed to generate. */
439 static unsigned long insn_flags = 0;
441 /* The bits in this mask specify which instruction scheduling options should
443 static unsigned long tune_flags = 0;
445 /* The following are used in the arm.md file as equivalents to bits
446 in the above two flag variables. */
448 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
451 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
454 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
457 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
460 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
463 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
466 /* Nonzero if this chip can benefit from load scheduling. */
467 int arm_ld_sched = 0;
469 /* Nonzero if this chip is a StrongARM. */
470 int arm_tune_strongarm = 0;
472 /* Nonzero if this chip is a Cirrus variant. */
473 int arm_arch_cirrus = 0;
475 /* Nonzero if this chip supports Intel Wireless MMX technology. */
476 int arm_arch_iwmmxt = 0;
478 /* Nonzero if this chip is an XScale. */
479 int arm_arch_xscale = 0;
481 /* Nonzero if tuning for XScale */
482 int arm_tune_xscale = 0;
484 /* Nonzero if we want to tune for stores that access the write-buffer.
485 This typically means an ARM6 or ARM7 with MMU or MPU. */
486 int arm_tune_wbuf = 0;
488 /* Nonzero if generating Thumb instructions. */
491 /* Nonzero if we should define __THUMB_INTERWORK__ in the
493 XXX This is a bit of a hack, it's intended to help work around
494 problems in GLD which doesn't understand that armv5t code is
495 interworking clean. */
496 int arm_cpp_interwork = 0;
498 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
499 must report the mode of the memory reference from PRINT_OPERAND to
500 PRINT_OPERAND_ADDRESS. */
501 enum machine_mode output_memory_reference_mode;
503 /* The register number to be used for the PIC offset register. */
504 int arm_pic_register = INVALID_REGNUM;
506 /* Set to 1 when a return insn is output, this means that the epilogue
508 int return_used_this_function;
510 /* Set to 1 after arm_reorg has started. Reset to start at the start of
511 the next function. */
512 static int after_arm_reorg = 0;
514 /* The maximum number of insns to be used when loading a constant. */
515 static int arm_constant_limit = 3;
517 /* For an explanation of these variables, see final_prescan_insn below. */
519 enum arm_cond_code arm_current_cc;
521 int arm_target_label;
523 /* The condition codes of the ARM, and the inverse function. */
524 static const char * const arm_condition_codes[] =
526 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
527 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
530 #define streq(string1, string2) (strcmp (string1, string2) == 0)
532 /* Initialization code. */
536 const char *const name;
537 enum processor_type core;
539 const unsigned long flags;
540 bool (* rtx_costs) (rtx, int, int, int *);
543 /* Not all of these give usefully different compilation alternatives,
544 but there is no simple way of generalizing them. */
545 static const struct processors all_cores[] =
548 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
549 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
550 #include "arm-cores.def"
552 {NULL, arm_none, NULL, 0, NULL}
555 static const struct processors all_architectures[] =
557 /* ARM Architectures */
558 /* We don't specify rtx_costs here as it will be figured out
561 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
562 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
563 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
564 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
565 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
566 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
567 implementations that support it, so we will leave it out for now. */
568 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
569 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
570 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
571 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
572 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
573 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
574 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
575 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
576 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
577 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
578 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
579 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
580 {NULL, arm_none, NULL, 0 , NULL}
583 struct arm_cpu_select
587 const struct processors * processors;
590 /* This is a magic structure. The 'string' field is magically filled in
591 with a pointer to the value specified by the user on the command line
592 assuming that the user has specified such a value. */
594 static struct arm_cpu_select arm_select[] =
596 /* string name processors */
597 { NULL, "-mcpu=", all_cores },
598 { NULL, "-march=", all_architectures },
599 { NULL, "-mtune=", all_cores }
602 /* Defines representing the indexes into the above table. */
603 #define ARM_OPT_SET_CPU 0
604 #define ARM_OPT_SET_ARCH 1
605 #define ARM_OPT_SET_TUNE 2
607 /* The name of the proprocessor macro to define for this architecture. */
609 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
618 /* Available values for for -mfpu=. */
620 static const struct fpu_desc all_fpus[] =
622 {"fpa", FPUTYPE_FPA},
623 {"fpe2", FPUTYPE_FPA_EMU2},
624 {"fpe3", FPUTYPE_FPA_EMU2},
625 {"maverick", FPUTYPE_MAVERICK},
630 /* Floating point models used by the different hardware.
631 See fputype in arm.h. */
633 static const enum fputype fp_model_for_fpu[] =
635 /* No FP hardware. */
636 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
637 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
638 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
639 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
640 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
641 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
648 enum float_abi_type abi_type;
652 /* Available values for -mfloat-abi=. */
654 static const struct float_abi all_float_abis[] =
656 {"soft", ARM_FLOAT_ABI_SOFT},
657 {"softfp", ARM_FLOAT_ABI_SOFTFP},
658 {"hard", ARM_FLOAT_ABI_HARD}
665 enum arm_abi_type abi_type;
669 /* Available values for -mabi=. */
671 static const struct abi_name arm_all_abis[] =
673 {"apcs-gnu", ARM_ABI_APCS},
674 {"atpcs", ARM_ABI_ATPCS},
675 {"aapcs", ARM_ABI_AAPCS},
676 {"iwmmxt", ARM_ABI_IWMMXT}
679 /* Return the number of bits set in VALUE. */
681 bit_count (unsigned long value)
683 unsigned long count = 0;
688 value &= value - 1; /* Clear the least-significant set bit. */
694 /* Set up library functions unique to ARM. */
697 arm_init_libfuncs (void)
699 /* There are no special library functions unless we are using the
704 /* The functions below are described in Section 4 of the "Run-Time
705 ABI for the ARM architecture", Version 1.0. */
707 /* Double-precision floating-point arithmetic. Table 2. */
708 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
709 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
710 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
711 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
712 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
714 /* Double-precision comparisons. Table 3. */
715 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
716 set_optab_libfunc (ne_optab, DFmode, NULL);
717 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
718 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
719 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
720 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
721 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
723 /* Single-precision floating-point arithmetic. Table 4. */
724 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
725 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
726 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
727 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
728 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
730 /* Single-precision comparisons. Table 5. */
731 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
732 set_optab_libfunc (ne_optab, SFmode, NULL);
733 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
734 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
735 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
736 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
737 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
739 /* Floating-point to integer conversions. Table 6. */
740 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
741 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
742 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
743 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
744 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
745 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
746 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
747 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
749 /* Conversions between floating types. Table 7. */
750 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
751 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
753 /* Integer to floating-point conversions. Table 8. */
754 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
755 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
756 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
757 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
758 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
759 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
760 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
761 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
763 /* Long long. Table 9. */
764 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
765 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
766 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
767 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
768 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
769 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
770 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
771 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
773 /* Integer (32/32->32) division. \S 4.3.1. */
774 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
775 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
777 /* The divmod functions are designed so that they can be used for
778 plain division, even though they return both the quotient and the
779 remainder. The quotient is returned in the usual location (i.e.,
780 r0 for SImode, {r0, r1} for DImode), just as would be expected
781 for an ordinary division routine. Because the AAPCS calling
782 conventions specify that all of { r0, r1, r2, r3 } are
783 callee-saved registers, there is no need to tell the compiler
784 explicitly that those registers are clobbered by these
786 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
787 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
788 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
789 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
791 /* We don't have mod libcalls. Fortunately gcc knows how to use the
792 divmod libcalls instead. */
793 set_optab_libfunc (smod_optab, DImode, NULL);
794 set_optab_libfunc (umod_optab, DImode, NULL);
795 set_optab_libfunc (smod_optab, SImode, NULL);
796 set_optab_libfunc (umod_optab, SImode, NULL);
799 /* Implement TARGET_HANDLE_OPTION. */
802 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
807 arm_select[1].string = arg;
811 arm_select[0].string = arg;
814 case OPT_mhard_float:
815 target_float_abi_name = "hard";
818 case OPT_msoft_float:
819 target_float_abi_name = "soft";
823 arm_select[2].string = arg;
831 /* Fix up any incompatible options that the user has specified.
832 This has now turned into a maze. */
834 arm_override_options (void)
837 enum processor_type target_arch_cpu = arm_none;
839 /* Set up the flags based on the cpu/architecture selected by the user. */
840 for (i = ARRAY_SIZE (arm_select); i--;)
842 struct arm_cpu_select * ptr = arm_select + i;
844 if (ptr->string != NULL && ptr->string[0] != '\0')
846 const struct processors * sel;
848 for (sel = ptr->processors; sel->name != NULL; sel++)
849 if (streq (ptr->string, sel->name))
851 /* Set the architecture define. */
852 if (i != ARM_OPT_SET_TUNE)
853 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
855 /* Determine the processor core for which we should
856 tune code-generation. */
857 if (/* -mcpu= is a sensible default. */
859 /* -mtune= overrides -mcpu= and -march=. */
860 || i == ARM_OPT_SET_TUNE)
861 arm_tune = (enum processor_type) (sel - ptr->processors);
863 /* Remember the CPU associated with this architecture.
864 If no other option is used to set the CPU type,
865 we'll use this to guess the most suitable tuning
867 if (i == ARM_OPT_SET_ARCH)
868 target_arch_cpu = sel->core;
870 if (i != ARM_OPT_SET_TUNE)
872 /* If we have been given an architecture and a processor
873 make sure that they are compatible. We only generate
874 a warning though, and we prefer the CPU over the
876 if (insn_flags != 0 && (insn_flags ^ sel->flags))
877 warning (0, "switch -mcpu=%s conflicts with -march= switch",
880 insn_flags = sel->flags;
886 if (sel->name == NULL)
887 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
891 /* Guess the tuning options from the architecture if necessary. */
892 if (arm_tune == arm_none)
893 arm_tune = target_arch_cpu;
895 /* If the user did not specify a processor, choose one for them. */
898 const struct processors * sel;
900 enum processor_type cpu;
902 cpu = TARGET_CPU_DEFAULT;
905 #ifdef SUBTARGET_CPU_DEFAULT
906 /* Use the subtarget default CPU if none was specified by
908 cpu = SUBTARGET_CPU_DEFAULT;
910 /* Default to ARM6. */
914 sel = &all_cores[cpu];
916 insn_flags = sel->flags;
918 /* Now check to see if the user has specified some command line
919 switch that require certain abilities from the cpu. */
922 if (TARGET_INTERWORK || TARGET_THUMB)
924 sought |= (FL_THUMB | FL_MODE32);
926 /* There are no ARM processors that support both APCS-26 and
927 interworking. Therefore we force FL_MODE26 to be removed
928 from insn_flags here (if it was set), so that the search
929 below will always be able to find a compatible processor. */
930 insn_flags &= ~FL_MODE26;
933 if (sought != 0 && ((sought & insn_flags) != sought))
935 /* Try to locate a CPU type that supports all of the abilities
936 of the default CPU, plus the extra abilities requested by
938 for (sel = all_cores; sel->name != NULL; sel++)
939 if ((sel->flags & sought) == (sought | insn_flags))
942 if (sel->name == NULL)
944 unsigned current_bit_count = 0;
945 const struct processors * best_fit = NULL;
947 /* Ideally we would like to issue an error message here
948 saying that it was not possible to find a CPU compatible
949 with the default CPU, but which also supports the command
950 line options specified by the programmer, and so they
951 ought to use the -mcpu=<name> command line option to
952 override the default CPU type.
954 If we cannot find a cpu that has both the
955 characteristics of the default cpu and the given
956 command line options we scan the array again looking
958 for (sel = all_cores; sel->name != NULL; sel++)
959 if ((sel->flags & sought) == sought)
963 count = bit_count (sel->flags & insn_flags);
965 if (count >= current_bit_count)
968 current_bit_count = count;
972 gcc_assert (best_fit);
976 insn_flags = sel->flags;
978 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
979 if (arm_tune == arm_none)
980 arm_tune = (enum processor_type) (sel - all_cores);
983 /* The processor for which we should tune should now have been
985 gcc_assert (arm_tune != arm_none);
987 tune_flags = all_cores[(int)arm_tune].flags;
989 targetm.rtx_costs = arm_size_rtx_costs;
991 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
993 /* Make sure that the processor choice does not conflict with any of the
994 other command line choices. */
995 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
997 warning (0, "target CPU does not support interworking" );
998 target_flags &= ~MASK_INTERWORK;
1001 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1003 warning (0, "target CPU does not support THUMB instructions");
1004 target_flags &= ~MASK_THUMB;
1007 if (TARGET_APCS_FRAME && TARGET_THUMB)
1009 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1010 target_flags &= ~MASK_APCS_FRAME;
1013 /* Callee super interworking implies thumb interworking. Adding
1014 this to the flags here simplifies the logic elsewhere. */
1015 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1016 target_flags |= MASK_INTERWORK;
1018 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1019 from here where no function is being compiled currently. */
1020 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1021 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1023 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1024 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1026 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1027 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1029 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1031 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1032 target_flags |= MASK_APCS_FRAME;
1035 if (TARGET_POKE_FUNCTION_NAME)
1036 target_flags |= MASK_APCS_FRAME;
1038 if (TARGET_APCS_REENT && flag_pic)
1039 error ("-fpic and -mapcs-reent are incompatible");
1041 if (TARGET_APCS_REENT)
1042 warning (0, "APCS reentrant code not supported. Ignored");
1044 /* If this target is normally configured to use APCS frames, warn if they
1045 are turned off and debugging is turned on. */
1047 && write_symbols != NO_DEBUG
1048 && !TARGET_APCS_FRAME
1049 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1050 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1052 /* If stack checking is disabled, we can use r10 as the PIC register,
1053 which keeps r9 available. */
1055 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1057 if (TARGET_APCS_FLOAT)
1058 warning (0, "passing floating point arguments in fp regs not yet supported");
1060 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1061 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1062 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1063 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1064 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1065 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1066 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1067 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1068 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1070 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1071 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1072 thumb_code = (TARGET_ARM == 0);
1073 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1074 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1075 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1077 /* V5 code we generate is completely interworking capable, so we turn off
1078 TARGET_INTERWORK here to avoid many tests later on. */
1080 /* XXX However, we must pass the right pre-processor defines to CPP
1081 or GLD can get confused. This is a hack. */
1082 if (TARGET_INTERWORK)
1083 arm_cpp_interwork = 1;
1086 target_flags &= ~MASK_INTERWORK;
1088 if (target_abi_name)
1090 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1092 if (streq (arm_all_abis[i].name, target_abi_name))
1094 arm_abi = arm_all_abis[i].abi_type;
1098 if (i == ARRAY_SIZE (arm_all_abis))
1099 error ("invalid ABI option: -mabi=%s", target_abi_name);
1102 arm_abi = ARM_DEFAULT_ABI;
1104 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1105 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1107 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1108 error ("iwmmxt abi requires an iwmmxt capable cpu");
1110 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1111 if (target_fpu_name == NULL && target_fpe_name != NULL)
1113 if (streq (target_fpe_name, "2"))
1114 target_fpu_name = "fpe2";
1115 else if (streq (target_fpe_name, "3"))
1116 target_fpu_name = "fpe3";
1118 error ("invalid floating point emulation option: -mfpe=%s",
1121 if (target_fpu_name != NULL)
1123 /* The user specified a FPU. */
1124 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1126 if (streq (all_fpus[i].name, target_fpu_name))
1128 arm_fpu_arch = all_fpus[i].fpu;
1129 arm_fpu_tune = arm_fpu_arch;
1130 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1134 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1135 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1139 #ifdef FPUTYPE_DEFAULT
1140 /* Use the default if it is specified for this platform. */
1141 arm_fpu_arch = FPUTYPE_DEFAULT;
1142 arm_fpu_tune = FPUTYPE_DEFAULT;
1144 /* Pick one based on CPU type. */
1145 /* ??? Some targets assume FPA is the default.
1146 if ((insn_flags & FL_VFP) != 0)
1147 arm_fpu_arch = FPUTYPE_VFP;
1150 if (arm_arch_cirrus)
1151 arm_fpu_arch = FPUTYPE_MAVERICK;
1153 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1155 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1156 arm_fpu_tune = FPUTYPE_FPA;
1158 arm_fpu_tune = arm_fpu_arch;
1159 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1160 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1163 if (target_float_abi_name != NULL)
1165 /* The user specified a FP ABI. */
1166 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1168 if (streq (all_float_abis[i].name, target_float_abi_name))
1170 arm_float_abi = all_float_abis[i].abi_type;
1174 if (i == ARRAY_SIZE (all_float_abis))
1175 error ("invalid floating point abi: -mfloat-abi=%s",
1176 target_float_abi_name);
1179 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1181 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1182 sorry ("-mfloat-abi=hard and VFP");
1184 /* If soft-float is specified then don't use FPU. */
1185 if (TARGET_SOFT_FLOAT)
1186 arm_fpu_arch = FPUTYPE_NONE;
1188 /* For arm2/3 there is no need to do any scheduling if there is only
1189 a floating point emulator, or we are doing software floating-point. */
1190 if ((TARGET_SOFT_FLOAT
1191 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1192 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1193 && (tune_flags & FL_MODE32) == 0)
1194 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1196 /* Override the default structure alignment for AAPCS ABI. */
1197 if (arm_abi == ARM_ABI_AAPCS)
1198 arm_structure_size_boundary = 8;
1200 if (structure_size_string != NULL)
1202 int size = strtol (structure_size_string, NULL, 0);
1204 if (size == 8 || size == 32
1205 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1206 arm_structure_size_boundary = size;
1208 warning (0, "structure size boundary can only be set to %s",
1209 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1212 if (arm_pic_register_string != NULL)
1214 int pic_register = decode_reg_name (arm_pic_register_string);
1217 warning (0, "-mpic-register= is useless without -fpic");
1219 /* Prevent the user from choosing an obviously stupid PIC register. */
1220 else if (pic_register < 0 || call_used_regs[pic_register]
1221 || pic_register == HARD_FRAME_POINTER_REGNUM
1222 || pic_register == STACK_POINTER_REGNUM
1223 || pic_register >= PC_REGNUM)
1224 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1226 arm_pic_register = pic_register;
1229 if (TARGET_THUMB && flag_schedule_insns)
1231 /* Don't warn since it's on by default in -O2. */
1232 flag_schedule_insns = 0;
1237 /* There's some dispute as to whether this should be 1 or 2. However,
1238 experiments seem to show that in pathological cases a setting of
1239 1 degrades less severely than a setting of 2. This could change if
1240 other parts of the compiler change their behavior. */
1241 arm_constant_limit = 1;
1243 /* If optimizing for size, bump the number of instructions that we
1244 are prepared to conditionally execute (even on a StrongARM). */
1245 max_insns_skipped = 6;
1249 /* For processors with load scheduling, it never costs more than
1250 2 cycles to load a constant, and the load scheduler may well
1251 reduce that to 1. */
1253 arm_constant_limit = 1;
1255 /* On XScale the longer latency of a load makes it more difficult
1256 to achieve a good schedule, so it's faster to synthesize
1257 constants that can be done in two insns. */
1258 if (arm_tune_xscale)
1259 arm_constant_limit = 2;
1261 /* StrongARM has early execution of branches, so a sequence
1262 that is worth skipping is shorter. */
1263 if (arm_tune_strongarm)
1264 max_insns_skipped = 3;
1267 /* Register global variables with the garbage collector. */
1268 arm_add_gc_roots ();
1272 arm_add_gc_roots (void)
1274 gcc_obstack_init(&minipool_obstack);
1275 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1278 /* A table of known ARM exception types.
1279 For use with the interrupt function attribute. */
1283 const char *const arg;
1284 const unsigned long return_value;
1288 static const isr_attribute_arg isr_attribute_args [] =
1290 { "IRQ", ARM_FT_ISR },
1291 { "irq", ARM_FT_ISR },
1292 { "FIQ", ARM_FT_FIQ },
1293 { "fiq", ARM_FT_FIQ },
1294 { "ABORT", ARM_FT_ISR },
1295 { "abort", ARM_FT_ISR },
1296 { "ABORT", ARM_FT_ISR },
1297 { "abort", ARM_FT_ISR },
1298 { "UNDEF", ARM_FT_EXCEPTION },
1299 { "undef", ARM_FT_EXCEPTION },
1300 { "SWI", ARM_FT_EXCEPTION },
1301 { "swi", ARM_FT_EXCEPTION },
1302 { NULL, ARM_FT_NORMAL }
1305 /* Returns the (interrupt) function type of the current
1306 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1308 static unsigned long
1309 arm_isr_value (tree argument)
1311 const isr_attribute_arg * ptr;
1314 /* No argument - default to IRQ. */
1315 if (argument == NULL_TREE)
1318 /* Get the value of the argument. */
1319 if (TREE_VALUE (argument) == NULL_TREE
1320 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1321 return ARM_FT_UNKNOWN;
1323 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1325 /* Check it against the list of known arguments. */
1326 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1327 if (streq (arg, ptr->arg))
1328 return ptr->return_value;
1330 /* An unrecognized interrupt type. */
1331 return ARM_FT_UNKNOWN;
1334 /* Computes the type of the current function. */
1336 static unsigned long
1337 arm_compute_func_type (void)
1339 unsigned long type = ARM_FT_UNKNOWN;
1343 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1345 /* Decide if the current function is volatile. Such functions
1346 never return, and many memory cycles can be saved by not storing
1347 register values that will never be needed again. This optimization
1348 was added to speed up context switching in a kernel application. */
1350 && TREE_NOTHROW (current_function_decl)
1351 && TREE_THIS_VOLATILE (current_function_decl))
1352 type |= ARM_FT_VOLATILE;
1354 if (cfun->static_chain_decl != NULL)
1355 type |= ARM_FT_NESTED;
1357 attr = DECL_ATTRIBUTES (current_function_decl);
1359 a = lookup_attribute ("naked", attr);
1361 type |= ARM_FT_NAKED;
1363 a = lookup_attribute ("isr", attr);
1365 a = lookup_attribute ("interrupt", attr);
1368 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1370 type |= arm_isr_value (TREE_VALUE (a));
1375 /* Returns the type of the current function. */
1378 arm_current_func_type (void)
1380 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1381 cfun->machine->func_type = arm_compute_func_type ();
1383 return cfun->machine->func_type;
1386 /* Return 1 if it is possible to return using a single instruction.
1387 If SIBLING is non-null, this is a test for a return before a sibling
1388 call. SIBLING is the call insn, so we can examine its register usage. */
1391 use_return_insn (int iscond, rtx sibling)
1394 unsigned int func_type;
1395 unsigned long saved_int_regs;
1396 unsigned HOST_WIDE_INT stack_adjust;
1397 arm_stack_offsets *offsets;
1399 /* Never use a return instruction before reload has run. */
1400 if (!reload_completed)
1403 func_type = arm_current_func_type ();
1405 /* Naked functions and volatile functions need special
1407 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1410 /* So do interrupt functions that use the frame pointer. */
1411 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1414 offsets = arm_get_frame_offsets ();
1415 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1417 /* As do variadic functions. */
1418 if (current_function_pretend_args_size
1419 || cfun->machine->uses_anonymous_args
1420 /* Or if the function calls __builtin_eh_return () */
1421 || current_function_calls_eh_return
1422 /* Or if the function calls alloca */
1423 || current_function_calls_alloca
1424 /* Or if there is a stack adjustment. However, if the stack pointer
1425 is saved on the stack, we can use a pre-incrementing stack load. */
1426 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1429 saved_int_regs = arm_compute_save_reg_mask ();
1431 /* Unfortunately, the insn
1433 ldmib sp, {..., sp, ...}
1435 triggers a bug on most SA-110 based devices, such that the stack
1436 pointer won't be correctly restored if the instruction takes a
1437 page fault. We work around this problem by popping r3 along with
1438 the other registers, since that is never slower than executing
1439 another instruction.
1441 We test for !arm_arch5 here, because code for any architecture
1442 less than this could potentially be run on one of the buggy
1444 if (stack_adjust == 4 && !arm_arch5)
1446 /* Validate that r3 is a call-clobbered register (always true in
1447 the default abi) ... */
1448 if (!call_used_regs[3])
1451 /* ... that it isn't being used for a return value ... */
1452 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1455 /* ... or for a tail-call argument ... */
1458 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1460 if (find_regno_fusage (sibling, USE, 3))
1464 /* ... and that there are no call-saved registers in r0-r2
1465 (always true in the default ABI). */
1466 if (saved_int_regs & 0x7)
1470 /* Can't be done if interworking with Thumb, and any registers have been
1472 if (TARGET_INTERWORK && saved_int_regs != 0)
1475 /* On StrongARM, conditional returns are expensive if they aren't
1476 taken and multiple registers have been stacked. */
1477 if (iscond && arm_tune_strongarm)
1479 /* Conditional return when just the LR is stored is a simple
1480 conditional-load instruction, that's not expensive. */
1481 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1484 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1488 /* If there are saved registers but the LR isn't saved, then we need
1489 two instructions for the return. */
1490 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1493 /* Can't be done if any of the FPA regs are pushed,
1494 since this also requires an insn. */
1495 if (TARGET_HARD_FLOAT && TARGET_FPA)
1496 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1497 if (regs_ever_live[regno] && !call_used_regs[regno])
1500 /* Likewise VFP regs. */
1501 if (TARGET_HARD_FLOAT && TARGET_VFP)
1502 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1503 if (regs_ever_live[regno] && !call_used_regs[regno])
1506 if (TARGET_REALLY_IWMMXT)
1507 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1508 if (regs_ever_live[regno] && ! call_used_regs [regno])
1514 /* Return TRUE if int I is a valid immediate ARM constant. */
1517 const_ok_for_arm (HOST_WIDE_INT i)
1521 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1522 be all zero, or all one. */
1523 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1524 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1525 != ((~(unsigned HOST_WIDE_INT) 0)
1526 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1529 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1531 /* Fast return for 0 and small values. We must do this for zero, since
1532 the code below can't handle that one case. */
1533 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1536 /* Get the number of trailing zeros, rounded down to the nearest even
1538 lowbit = (ffs ((int) i) - 1) & ~1;
1540 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1542 else if (lowbit <= 4
1543 && ((i & ~0xc000003f) == 0
1544 || (i & ~0xf000000f) == 0
1545 || (i & ~0xfc000003) == 0))
1551 /* Return true if I is a valid constant for the operation CODE. */
1553 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1555 if (const_ok_for_arm (i))
1561 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1563 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1569 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1576 /* Emit a sequence of insns to handle a large constant.
1577 CODE is the code of the operation required, it can be any of SET, PLUS,
1578 IOR, AND, XOR, MINUS;
1579 MODE is the mode in which the operation is being performed;
1580 VAL is the integer to operate on;
1581 SOURCE is the other operand (a register, or a null-pointer for SET);
1582 SUBTARGETS means it is safe to create scratch registers if that will
1583 either produce a simpler sequence, or we will want to cse the values.
1584 Return value is the number of insns emitted. */
1587 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1588 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1592 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1593 cond = COND_EXEC_TEST (PATTERN (insn));
1597 if (subtargets || code == SET
1598 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1599 && REGNO (target) != REGNO (source)))
1601 /* After arm_reorg has been called, we can't fix up expensive
1602 constants by pushing them into memory so we must synthesize
1603 them in-line, regardless of the cost. This is only likely to
1604 be more costly on chips that have load delay slots and we are
1605 compiling without running the scheduler (so no splitting
1606 occurred before the final instruction emission).
1608 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1610 if (!after_arm_reorg
1612 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1614 > arm_constant_limit + (code != SET)))
1618 /* Currently SET is the only monadic value for CODE, all
1619 the rest are diadic. */
1620 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1625 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1627 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1628 /* For MINUS, the value is subtracted from, since we never
1629 have subtraction of a constant. */
1631 emit_insn (gen_rtx_SET (VOIDmode, target,
1632 gen_rtx_MINUS (mode, temp, source)));
1634 emit_insn (gen_rtx_SET (VOIDmode, target,
1635 gen_rtx_fmt_ee (code, mode, source, temp)));
1641 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1646 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1648 HOST_WIDE_INT temp1;
1656 if (remainder & (3 << (i - 2)))
1661 temp1 = remainder & ((0x0ff << end)
1662 | ((i < end) ? (0xff >> (32 - end)) : 0));
1663 remainder &= ~temp1;
1668 } while (remainder);
1672 /* Emit an instruction with the indicated PATTERN. If COND is
1673 non-NULL, conditionalize the execution of the instruction on COND
1677 emit_constant_insn (rtx cond, rtx pattern)
1680 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1681 emit_insn (pattern);
1684 /* As above, but extra parameter GENERATE which, if clear, suppresses
1688 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1689 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1694 int can_negate_initial = 0;
1697 int num_bits_set = 0;
1698 int set_sign_bit_copies = 0;
1699 int clear_sign_bit_copies = 0;
1700 int clear_zero_bit_copies = 0;
1701 int set_zero_bit_copies = 0;
1703 unsigned HOST_WIDE_INT temp1, temp2;
1704 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1706 /* Find out which operations are safe for a given CODE. Also do a quick
1707 check for degenerate cases; these can occur when DImode operations
1719 can_negate_initial = 1;
1723 if (remainder == 0xffffffff)
1726 emit_constant_insn (cond,
1727 gen_rtx_SET (VOIDmode, target,
1728 GEN_INT (ARM_SIGN_EXTEND (val))));
1733 if (reload_completed && rtx_equal_p (target, source))
1736 emit_constant_insn (cond,
1737 gen_rtx_SET (VOIDmode, target, source));
1746 emit_constant_insn (cond,
1747 gen_rtx_SET (VOIDmode, target, const0_rtx));
1750 if (remainder == 0xffffffff)
1752 if (reload_completed && rtx_equal_p (target, source))
1755 emit_constant_insn (cond,
1756 gen_rtx_SET (VOIDmode, target, source));
1765 if (reload_completed && rtx_equal_p (target, source))
1768 emit_constant_insn (cond,
1769 gen_rtx_SET (VOIDmode, target, source));
1773 /* We don't know how to handle other cases yet. */
1774 gcc_assert (remainder == 0xffffffff);
1777 emit_constant_insn (cond,
1778 gen_rtx_SET (VOIDmode, target,
1779 gen_rtx_NOT (mode, source)));
1783 /* We treat MINUS as (val - source), since (source - val) is always
1784 passed as (source + (-val)). */
1788 emit_constant_insn (cond,
1789 gen_rtx_SET (VOIDmode, target,
1790 gen_rtx_NEG (mode, source)));
1793 if (const_ok_for_arm (val))
1796 emit_constant_insn (cond,
1797 gen_rtx_SET (VOIDmode, target,
1798 gen_rtx_MINUS (mode, GEN_INT (val),
1810 /* If we can do it in one insn get out quickly. */
1811 if (const_ok_for_arm (val)
1812 || (can_negate_initial && const_ok_for_arm (-val))
1813 || (can_invert && const_ok_for_arm (~val)))
1816 emit_constant_insn (cond,
1817 gen_rtx_SET (VOIDmode, target,
1819 ? gen_rtx_fmt_ee (code, mode, source,
1825 /* Calculate a few attributes that may be useful for specific
1827 for (i = 31; i >= 0; i--)
1829 if ((remainder & (1 << i)) == 0)
1830 clear_sign_bit_copies++;
1835 for (i = 31; i >= 0; i--)
1837 if ((remainder & (1 << i)) != 0)
1838 set_sign_bit_copies++;
1843 for (i = 0; i <= 31; i++)
1845 if ((remainder & (1 << i)) == 0)
1846 clear_zero_bit_copies++;
1851 for (i = 0; i <= 31; i++)
1853 if ((remainder & (1 << i)) != 0)
1854 set_zero_bit_copies++;
1862 /* See if we can do this by sign_extending a constant that is known
1863 to be negative. This is a good, way of doing it, since the shift
1864 may well merge into a subsequent insn. */
1865 if (set_sign_bit_copies > 1)
1867 if (const_ok_for_arm
1868 (temp1 = ARM_SIGN_EXTEND (remainder
1869 << (set_sign_bit_copies - 1))))
1873 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1874 emit_constant_insn (cond,
1875 gen_rtx_SET (VOIDmode, new_src,
1877 emit_constant_insn (cond,
1878 gen_ashrsi3 (target, new_src,
1879 GEN_INT (set_sign_bit_copies - 1)));
1883 /* For an inverted constant, we will need to set the low bits,
1884 these will be shifted out of harm's way. */
1885 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1886 if (const_ok_for_arm (~temp1))
1890 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1891 emit_constant_insn (cond,
1892 gen_rtx_SET (VOIDmode, new_src,
1894 emit_constant_insn (cond,
1895 gen_ashrsi3 (target, new_src,
1896 GEN_INT (set_sign_bit_copies - 1)));
1902 /* See if we can calculate the value as the difference between two
1903 valid immediates. */
1904 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
1906 int topshift = clear_sign_bit_copies & ~1;
1908 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
1909 & (0xff000000 >> topshift));
1911 /* If temp1 is zero, then that means the 9 most significant
1912 bits of remainder were 1 and we've caused it to overflow.
1913 When topshift is 0 we don't need to do anything since we
1914 can borrow from 'bit 32'. */
1915 if (temp1 == 0 && topshift != 0)
1916 temp1 = 0x80000000 >> (topshift - 1);
1918 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
1920 if (const_ok_for_arm (temp2))
1924 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1925 emit_constant_insn (cond,
1926 gen_rtx_SET (VOIDmode, new_src,
1928 emit_constant_insn (cond,
1929 gen_addsi3 (target, new_src,
1937 /* See if we can generate this by setting the bottom (or the top)
1938 16 bits, and then shifting these into the other half of the
1939 word. We only look for the simplest cases, to do more would cost
1940 too much. Be careful, however, not to generate this when the
1941 alternative would take fewer insns. */
1942 if (val & 0xffff0000)
1944 temp1 = remainder & 0xffff0000;
1945 temp2 = remainder & 0x0000ffff;
1947 /* Overlaps outside this range are best done using other methods. */
1948 for (i = 9; i < 24; i++)
1950 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1951 && !const_ok_for_arm (temp2))
1953 rtx new_src = (subtargets
1954 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1956 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1957 source, subtargets, generate);
1965 gen_rtx_ASHIFT (mode, source,
1972 /* Don't duplicate cases already considered. */
1973 for (i = 17; i < 24; i++)
1975 if (((temp1 | (temp1 >> i)) == remainder)
1976 && !const_ok_for_arm (temp1))
1978 rtx new_src = (subtargets
1979 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1981 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1982 source, subtargets, generate);
1987 gen_rtx_SET (VOIDmode, target,
1990 gen_rtx_LSHIFTRT (mode, source,
2001 /* If we have IOR or XOR, and the constant can be loaded in a
2002 single instruction, and we can find a temporary to put it in,
2003 then this can be done in two instructions instead of 3-4. */
2005 /* TARGET can't be NULL if SUBTARGETS is 0 */
2006 || (reload_completed && !reg_mentioned_p (target, source)))
2008 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2012 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2014 emit_constant_insn (cond,
2015 gen_rtx_SET (VOIDmode, sub,
2017 emit_constant_insn (cond,
2018 gen_rtx_SET (VOIDmode, target,
2019 gen_rtx_fmt_ee (code, mode,
2029 if (set_sign_bit_copies > 8
2030 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2034 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2035 rtx shift = GEN_INT (set_sign_bit_copies);
2039 gen_rtx_SET (VOIDmode, sub,
2041 gen_rtx_ASHIFT (mode,
2046 gen_rtx_SET (VOIDmode, target,
2048 gen_rtx_LSHIFTRT (mode, sub,
2054 if (set_zero_bit_copies > 8
2055 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2059 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2060 rtx shift = GEN_INT (set_zero_bit_copies);
2064 gen_rtx_SET (VOIDmode, sub,
2066 gen_rtx_LSHIFTRT (mode,
2071 gen_rtx_SET (VOIDmode, target,
2073 gen_rtx_ASHIFT (mode, sub,
2079 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2083 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2084 emit_constant_insn (cond,
2085 gen_rtx_SET (VOIDmode, sub,
2086 gen_rtx_NOT (mode, source)));
2089 sub = gen_reg_rtx (mode);
2090 emit_constant_insn (cond,
2091 gen_rtx_SET (VOIDmode, sub,
2092 gen_rtx_AND (mode, source,
2094 emit_constant_insn (cond,
2095 gen_rtx_SET (VOIDmode, target,
2096 gen_rtx_NOT (mode, sub)));
2103 /* See if two shifts will do 2 or more insn's worth of work. */
2104 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2106 HOST_WIDE_INT shift_mask = ((0xffffffff
2107 << (32 - clear_sign_bit_copies))
2110 if ((remainder | shift_mask) != 0xffffffff)
2114 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2115 insns = arm_gen_constant (AND, mode, cond,
2116 remainder | shift_mask,
2117 new_src, source, subtargets, 1);
2122 rtx targ = subtargets ? NULL_RTX : target;
2123 insns = arm_gen_constant (AND, mode, cond,
2124 remainder | shift_mask,
2125 targ, source, subtargets, 0);
2131 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2132 rtx shift = GEN_INT (clear_sign_bit_copies);
2134 emit_insn (gen_ashlsi3 (new_src, source, shift));
2135 emit_insn (gen_lshrsi3 (target, new_src, shift));
2141 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2143 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2145 if ((remainder | shift_mask) != 0xffffffff)
2149 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2151 insns = arm_gen_constant (AND, mode, cond,
2152 remainder | shift_mask,
2153 new_src, source, subtargets, 1);
2158 rtx targ = subtargets ? NULL_RTX : target;
2160 insns = arm_gen_constant (AND, mode, cond,
2161 remainder | shift_mask,
2162 targ, source, subtargets, 0);
2168 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2169 rtx shift = GEN_INT (clear_zero_bit_copies);
2171 emit_insn (gen_lshrsi3 (new_src, source, shift));
2172 emit_insn (gen_ashlsi3 (target, new_src, shift));
2184 for (i = 0; i < 32; i++)
2185 if (remainder & (1 << i))
2188 if (code == AND || (can_invert && num_bits_set > 16))
2189 remainder = (~remainder) & 0xffffffff;
2190 else if (code == PLUS && num_bits_set > 16)
2191 remainder = (-remainder) & 0xffffffff;
2198 /* Now try and find a way of doing the job in either two or three
2200 We start by looking for the largest block of zeros that are aligned on
2201 a 2-bit boundary, we then fill up the temps, wrapping around to the
2202 top of the word when we drop off the bottom.
2203 In the worst case this code should produce no more than four insns. */
2206 int best_consecutive_zeros = 0;
2208 for (i = 0; i < 32; i += 2)
2210 int consecutive_zeros = 0;
2212 if (!(remainder & (3 << i)))
2214 while ((i < 32) && !(remainder & (3 << i)))
2216 consecutive_zeros += 2;
2219 if (consecutive_zeros > best_consecutive_zeros)
2221 best_consecutive_zeros = consecutive_zeros;
2222 best_start = i - consecutive_zeros;
2228 /* So long as it won't require any more insns to do so, it's
2229 desirable to emit a small constant (in bits 0...9) in the last
2230 insn. This way there is more chance that it can be combined with
2231 a later addressing insn to form a pre-indexed load or store
2232 operation. Consider:
2234 *((volatile int *)0xe0000100) = 1;
2235 *((volatile int *)0xe0000110) = 2;
2237 We want this to wind up as:
2241 str rB, [rA, #0x100]
2243 str rB, [rA, #0x110]
2245 rather than having to synthesize both large constants from scratch.
2247 Therefore, we calculate how many insns would be required to emit
2248 the constant starting from `best_start', and also starting from
2249 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2250 yield a shorter sequence, we may as well use zero. */
2252 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2253 && (count_insns_for_constant (remainder, 0) <=
2254 count_insns_for_constant (remainder, best_start)))
2257 /* Now start emitting the insns. */
2265 if (remainder & (3 << (i - 2)))
2270 temp1 = remainder & ((0x0ff << end)
2271 | ((i < end) ? (0xff >> (32 - end)) : 0));
2272 remainder &= ~temp1;
2276 rtx new_src, temp1_rtx;
2278 if (code == SET || code == MINUS)
2280 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2281 if (can_invert && code != MINUS)
2286 if (remainder && subtargets)
2287 new_src = gen_reg_rtx (mode);
2292 else if (can_negate)
2296 temp1 = trunc_int_for_mode (temp1, mode);
2297 temp1_rtx = GEN_INT (temp1);
2301 else if (code == MINUS)
2302 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2304 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2306 emit_constant_insn (cond,
2307 gen_rtx_SET (VOIDmode, new_src,
2317 else if (code == MINUS)
2331 /* Canonicalize a comparison so that we are more likely to recognize it.
2332 This can be done for a few constant compares, where we can make the
2333 immediate value easier to load. */
2336 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2339 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2340 unsigned HOST_WIDE_INT maxval;
2341 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2352 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2354 *op1 = GEN_INT (i + 1);
2355 return code == GT ? GE : LT;
2362 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2364 *op1 = GEN_INT (i - 1);
2365 return code == GE ? GT : LE;
2371 if (i != ~((unsigned HOST_WIDE_INT) 0)
2372 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2374 *op1 = GEN_INT (i + 1);
2375 return code == GTU ? GEU : LTU;
2382 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2384 *op1 = GEN_INT (i - 1);
2385 return code == GEU ? GTU : LEU;
2397 /* Define how to find the value returned by a function. */
2400 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2402 enum machine_mode mode;
2403 int unsignedp ATTRIBUTE_UNUSED;
2404 rtx r ATTRIBUTE_UNUSED;
2406 mode = TYPE_MODE (type);
2407 /* Promote integer types. */
2408 if (INTEGRAL_TYPE_P (type))
2409 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2411 /* Promotes small structs returned in a register to full-word size
2412 for big-endian AAPCS. */
2413 if (arm_return_in_msb (type))
2415 HOST_WIDE_INT size = int_size_in_bytes (type);
2416 if (size % UNITS_PER_WORD != 0)
2418 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2419 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2423 return LIBCALL_VALUE(mode);
2426 /* Determine the amount of memory needed to store the possible return
2427 registers of an untyped call. */
2429 arm_apply_result_size (void)
2435 if (TARGET_HARD_FLOAT_ABI)
2439 if (TARGET_MAVERICK)
2442 if (TARGET_IWMMXT_ABI)
2449 /* Decide whether a type should be returned in memory (true)
2450 or in a register (false). This is called by the macro
2451 RETURN_IN_MEMORY. */
2453 arm_return_in_memory (tree type)
2457 if (!AGGREGATE_TYPE_P (type) &&
2458 (TREE_CODE (type) != VECTOR_TYPE) &&
2459 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2460 /* All simple types are returned in registers.
2461 For AAPCS, complex types are treated the same as aggregates. */
2464 size = int_size_in_bytes (type);
2466 if (arm_abi != ARM_ABI_APCS)
2468 /* ATPCS and later return aggregate types in memory only if they are
2469 larger than a word (or are variable size). */
2470 return (size < 0 || size > UNITS_PER_WORD);
2473 /* To maximize backwards compatibility with previous versions of gcc,
2474 return vectors up to 4 words in registers. */
2475 if (TREE_CODE (type) == VECTOR_TYPE)
2476 return (size < 0 || size > (4 * UNITS_PER_WORD));
2478 /* For the arm-wince targets we choose to be compatible with Microsoft's
2479 ARM and Thumb compilers, which always return aggregates in memory. */
2481 /* All structures/unions bigger than one word are returned in memory.
2482 Also catch the case where int_size_in_bytes returns -1. In this case
2483 the aggregate is either huge or of variable size, and in either case
2484 we will want to return it via memory and not in a register. */
2485 if (size < 0 || size > UNITS_PER_WORD)
2488 if (TREE_CODE (type) == RECORD_TYPE)
2492 /* For a struct the APCS says that we only return in a register
2493 if the type is 'integer like' and every addressable element
2494 has an offset of zero. For practical purposes this means
2495 that the structure can have at most one non bit-field element
2496 and that this element must be the first one in the structure. */
2498 /* Find the first field, ignoring non FIELD_DECL things which will
2499 have been created by C++. */
2500 for (field = TYPE_FIELDS (type);
2501 field && TREE_CODE (field) != FIELD_DECL;
2502 field = TREE_CHAIN (field))
2506 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2508 /* Check that the first field is valid for returning in a register. */
2510 /* ... Floats are not allowed */
2511 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2514 /* ... Aggregates that are not themselves valid for returning in
2515 a register are not allowed. */
2516 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2519 /* Now check the remaining fields, if any. Only bitfields are allowed,
2520 since they are not addressable. */
2521 for (field = TREE_CHAIN (field);
2523 field = TREE_CHAIN (field))
2525 if (TREE_CODE (field) != FIELD_DECL)
2528 if (!DECL_BIT_FIELD_TYPE (field))
2535 if (TREE_CODE (type) == UNION_TYPE)
2539 /* Unions can be returned in registers if every element is
2540 integral, or can be returned in an integer register. */
2541 for (field = TYPE_FIELDS (type);
2543 field = TREE_CHAIN (field))
2545 if (TREE_CODE (field) != FIELD_DECL)
2548 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2551 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2557 #endif /* not ARM_WINCE */
2559 /* Return all other types in memory. */
2563 /* Indicate whether or not words of a double are in big-endian order. */
2566 arm_float_words_big_endian (void)
2568 if (TARGET_MAVERICK)
2571 /* For FPA, float words are always big-endian. For VFP, floats words
2572 follow the memory system mode. */
2580 return (TARGET_BIG_END ? 1 : 0);
2585 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2586 for a call to a function whose data type is FNTYPE.
2587 For a library call, FNTYPE is NULL. */
2589 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2590 rtx libname ATTRIBUTE_UNUSED,
2591 tree fndecl ATTRIBUTE_UNUSED)
2593 /* On the ARM, the offset starts at 0. */
2594 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2595 pcum->iwmmxt_nregs = 0;
2596 pcum->can_split = true;
2598 pcum->call_cookie = CALL_NORMAL;
2600 if (TARGET_LONG_CALLS)
2601 pcum->call_cookie = CALL_LONG;
2603 /* Check for long call/short call attributes. The attributes
2604 override any command line option. */
2607 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2608 pcum->call_cookie = CALL_SHORT;
2609 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2610 pcum->call_cookie = CALL_LONG;
2613 /* Varargs vectors are treated the same as long long.
2614 named_count avoids having to change the way arm handles 'named' */
2615 pcum->named_count = 0;
2618 if (TARGET_REALLY_IWMMXT && fntype)
2622 for (fn_arg = TYPE_ARG_TYPES (fntype);
2624 fn_arg = TREE_CHAIN (fn_arg))
2625 pcum->named_count += 1;
2627 if (! pcum->named_count)
2628 pcum->named_count = INT_MAX;
2633 /* Return true if mode/type need doubleword alignment. */
2635 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2637 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2638 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2642 /* Determine where to put an argument to a function.
2643 Value is zero to push the argument on the stack,
2644 or a hard register in which to store the argument.
2646 MODE is the argument's machine mode.
2647 TYPE is the data type of the argument (as a tree).
2648 This is null for libcalls where that information may
2650 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2651 the preceding args and about the function being called.
2652 NAMED is nonzero if this argument is a named parameter
2653 (otherwise it is an extra parameter matching an ellipsis). */
2656 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2657 tree type, int named)
2661 /* Varargs vectors are treated the same as long long.
2662 named_count avoids having to change the way arm handles 'named' */
2663 if (TARGET_IWMMXT_ABI
2664 && arm_vector_mode_supported_p (mode)
2665 && pcum->named_count > pcum->nargs + 1)
2667 if (pcum->iwmmxt_nregs <= 9)
2668 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2671 pcum->can_split = false;
2676 /* Put doubleword aligned quantities in even register pairs. */
2678 && ARM_DOUBLEWORD_ALIGN
2679 && arm_needs_doubleword_align (mode, type))
2682 if (mode == VOIDmode)
2683 /* Compute operand 2 of the call insn. */
2684 return GEN_INT (pcum->call_cookie);
2686 /* Only allow splitting an arg between regs and memory if all preceding
2687 args were allocated to regs. For args passed by reference we only count
2688 the reference pointer. */
2689 if (pcum->can_split)
2692 nregs = ARM_NUM_REGS2 (mode, type);
2694 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2697 return gen_rtx_REG (mode, pcum->nregs);
2701 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2702 tree type, bool named ATTRIBUTE_UNUSED)
2704 int nregs = pcum->nregs;
2706 if (arm_vector_mode_supported_p (mode))
2709 if (NUM_ARG_REGS > nregs
2710 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2712 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2717 /* Variable sized types are passed by reference. This is a GCC
2718 extension to the ARM ABI. */
2721 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2722 enum machine_mode mode ATTRIBUTE_UNUSED,
2723 tree type, bool named ATTRIBUTE_UNUSED)
2725 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2728 /* Encode the current state of the #pragma [no_]long_calls. */
2731 OFF, /* No #pramgma [no_]long_calls is in effect. */
2732 LONG, /* #pragma long_calls is in effect. */
2733 SHORT /* #pragma no_long_calls is in effect. */
2736 static arm_pragma_enum arm_pragma_long_calls = OFF;
2739 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2741 arm_pragma_long_calls = LONG;
2745 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2747 arm_pragma_long_calls = SHORT;
2751 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2753 arm_pragma_long_calls = OFF;
2756 /* Table of machine attributes. */
2757 const struct attribute_spec arm_attribute_table[] =
2759 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2760 /* Function calls made to this symbol must be done indirectly, because
2761 it may lie outside of the 26 bit addressing range of a normal function
2763 { "long_call", 0, 0, false, true, true, NULL },
2764 /* Whereas these functions are always known to reside within the 26 bit
2765 addressing range. */
2766 { "short_call", 0, 0, false, true, true, NULL },
2767 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2768 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2769 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2770 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2772 /* ARM/PE has three new attributes:
2774 dllexport - for exporting a function/variable that will live in a dll
2775 dllimport - for importing a function/variable from a dll
2777 Microsoft allows multiple declspecs in one __declspec, separating
2778 them with spaces. We do NOT support this. Instead, use __declspec
2781 { "dllimport", 0, 0, true, false, false, NULL },
2782 { "dllexport", 0, 0, true, false, false, NULL },
2783 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2784 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2785 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2786 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2787 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2789 { NULL, 0, 0, false, false, false, NULL }
2792 /* Handle an attribute requiring a FUNCTION_DECL;
2793 arguments as in struct attribute_spec.handler. */
2795 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2796 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2798 if (TREE_CODE (*node) != FUNCTION_DECL)
2800 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2801 IDENTIFIER_POINTER (name));
2802 *no_add_attrs = true;
2808 /* Handle an "interrupt" or "isr" attribute;
2809 arguments as in struct attribute_spec.handler. */
2811 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2816 if (TREE_CODE (*node) != FUNCTION_DECL)
2818 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2819 IDENTIFIER_POINTER (name));
2820 *no_add_attrs = true;
2822 /* FIXME: the argument if any is checked for type attributes;
2823 should it be checked for decl ones? */
2827 if (TREE_CODE (*node) == FUNCTION_TYPE
2828 || TREE_CODE (*node) == METHOD_TYPE)
2830 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2832 warning (OPT_Wattributes, "%qs attribute ignored",
2833 IDENTIFIER_POINTER (name));
2834 *no_add_attrs = true;
2837 else if (TREE_CODE (*node) == POINTER_TYPE
2838 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2839 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2840 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2842 *node = build_variant_type_copy (*node);
2843 TREE_TYPE (*node) = build_type_attribute_variant
2845 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2846 *no_add_attrs = true;
2850 /* Possibly pass this attribute on from the type to a decl. */
2851 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2852 | (int) ATTR_FLAG_FUNCTION_NEXT
2853 | (int) ATTR_FLAG_ARRAY_NEXT))
2855 *no_add_attrs = true;
2856 return tree_cons (name, args, NULL_TREE);
2860 warning (OPT_Wattributes, "%qs attribute ignored",
2861 IDENTIFIER_POINTER (name));
2869 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2870 /* Handle the "notshared" attribute. This attribute is another way of
2871 requesting hidden visibility. ARM's compiler supports
2872 "__declspec(notshared)"; we support the same thing via an
2876 arm_handle_notshared_attribute (tree *node,
2877 tree name ATTRIBUTE_UNUSED,
2878 tree args ATTRIBUTE_UNUSED,
2879 int flags ATTRIBUTE_UNUSED,
2882 tree decl = TYPE_NAME (*node);
2886 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2887 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2888 *no_add_attrs = false;
2894 /* Return 0 if the attributes for two types are incompatible, 1 if they
2895 are compatible, and 2 if they are nearly compatible (which causes a
2896 warning to be generated). */
2898 arm_comp_type_attributes (tree type1, tree type2)
2902 /* Check for mismatch of non-default calling convention. */
2903 if (TREE_CODE (type1) != FUNCTION_TYPE)
2906 /* Check for mismatched call attributes. */
2907 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2908 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2909 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2910 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2912 /* Only bother to check if an attribute is defined. */
2913 if (l1 | l2 | s1 | s2)
2915 /* If one type has an attribute, the other must have the same attribute. */
2916 if ((l1 != l2) || (s1 != s2))
2919 /* Disallow mixed attributes. */
2920 if ((l1 & s2) || (l2 & s1))
2924 /* Check for mismatched ISR attribute. */
2925 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2927 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2928 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2930 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2937 /* Encode long_call or short_call attribute by prefixing
2938 symbol name in DECL with a special character FLAG. */
2940 arm_encode_call_attribute (tree decl, int flag)
2942 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2943 int len = strlen (str);
2946 /* Do not allow weak functions to be treated as short call. */
2947 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2950 newstr = alloca (len + 2);
2952 strcpy (newstr + 1, str);
2954 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2955 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2958 /* Assigns default attributes to newly defined type. This is used to
2959 set short_call/long_call attributes for function types of
2960 functions defined inside corresponding #pragma scopes. */
2962 arm_set_default_type_attributes (tree type)
2964 /* Add __attribute__ ((long_call)) to all functions, when
2965 inside #pragma long_calls or __attribute__ ((short_call)),
2966 when inside #pragma no_long_calls. */
2967 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2969 tree type_attr_list, attr_name;
2970 type_attr_list = TYPE_ATTRIBUTES (type);
2972 if (arm_pragma_long_calls == LONG)
2973 attr_name = get_identifier ("long_call");
2974 else if (arm_pragma_long_calls == SHORT)
2975 attr_name = get_identifier ("short_call");
2979 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2980 TYPE_ATTRIBUTES (type) = type_attr_list;
2984 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2985 defined within the current compilation unit. If this cannot be
2986 determined, then 0 is returned. */
2988 current_file_function_operand (rtx sym_ref)
2990 /* This is a bit of a fib. A function will have a short call flag
2991 applied to its name if it has the short call attribute, or it has
2992 already been defined within the current compilation unit. */
2993 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2996 /* The current function is always defined within the current compilation
2997 unit. If it s a weak definition however, then this may not be the real
2998 definition of the function, and so we have to say no. */
2999 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3000 && !DECL_WEAK (current_function_decl))
3003 /* We cannot make the determination - default to returning 0. */
3007 /* Return nonzero if a 32 bit "long_call" should be generated for
3008 this call. We generate a long_call if the function:
3010 a. has an __attribute__((long call))
3011 or b. is within the scope of a #pragma long_calls
3012 or c. the -mlong-calls command line switch has been specified
3014 1. -ffunction-sections is in effect
3015 or 2. the current function has __attribute__ ((section))
3016 or 3. the target function has __attribute__ ((section))
3018 However we do not generate a long call if the function:
3020 d. has an __attribute__ ((short_call))
3021 or e. is inside the scope of a #pragma no_long_calls
3022 or f. is defined within the current compilation unit.
3024 This function will be called by C fragments contained in the machine
3025 description file. SYM_REF and CALL_COOKIE correspond to the matched
3026 rtl operands. CALL_SYMBOL is used to distinguish between
3027 two different callers of the function. It is set to 1 in the
3028 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3029 and "call_value" patterns. This is because of the difference in the
3030 SYM_REFs passed by these patterns. */
3032 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3036 if (GET_CODE (sym_ref) != MEM)
3039 sym_ref = XEXP (sym_ref, 0);
3042 if (GET_CODE (sym_ref) != SYMBOL_REF)
3045 if (call_cookie & CALL_SHORT)
3048 if (TARGET_LONG_CALLS)
3050 if (flag_function_sections
3051 || DECL_SECTION_NAME (current_function_decl))
3052 /* c.3 is handled by the definition of the
3053 ARM_DECLARE_FUNCTION_SIZE macro. */
3057 if (current_file_function_operand (sym_ref))
3060 return (call_cookie & CALL_LONG)
3061 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3062 || TARGET_LONG_CALLS;
3065 /* Return nonzero if it is ok to make a tail-call to DECL. */
3067 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3069 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3071 if (cfun->machine->sibcall_blocked)
3074 /* Never tailcall something for which we have no decl, or if we
3075 are in Thumb mode. */
3076 if (decl == NULL || TARGET_THUMB)
3079 /* Get the calling method. */
3080 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3081 call_type = CALL_SHORT;
3082 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3083 call_type = CALL_LONG;
3085 /* Cannot tail-call to long calls, since these are out of range of
3086 a branch instruction. However, if not compiling PIC, we know
3087 we can reach the symbol if it is in this compilation unit. */
3088 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3091 /* If we are interworking and the function is not declared static
3092 then we can't tail-call it unless we know that it exists in this
3093 compilation unit (since it might be a Thumb routine). */
3094 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3097 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3098 if (IS_INTERRUPT (arm_current_func_type ()))
3101 /* Everything else is ok. */
3106 /* Addressing mode support functions. */
3108 /* Return nonzero if X is a legitimate immediate operand when compiling
3111 legitimate_pic_operand_p (rtx x)
3115 && (GET_CODE (x) == SYMBOL_REF
3116 || (GET_CODE (x) == CONST
3117 && GET_CODE (XEXP (x, 0)) == PLUS
3118 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
3125 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3127 if (GET_CODE (orig) == SYMBOL_REF
3128 || GET_CODE (orig) == LABEL_REF)
3130 #ifndef AOF_ASSEMBLER
3131 rtx pic_ref, address;
3138 gcc_assert (!no_new_pseudos);
3139 reg = gen_reg_rtx (Pmode);
3144 #ifdef AOF_ASSEMBLER
3145 /* The AOF assembler can generate relocations for these directly, and
3146 understands that the PIC register has to be added into the offset. */
3147 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3150 address = gen_reg_rtx (Pmode);
3155 emit_insn (gen_pic_load_addr_arm (address, orig));
3157 emit_insn (gen_pic_load_addr_thumb (address, orig));
3159 if ((GET_CODE (orig) == LABEL_REF
3160 || (GET_CODE (orig) == SYMBOL_REF &&
3161 SYMBOL_REF_LOCAL_P (orig)))
3163 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
3166 pic_ref = gen_const_mem (Pmode,
3167 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3171 insn = emit_move_insn (reg, pic_ref);
3173 current_function_uses_pic_offset_table = 1;
3174 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3176 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3180 else if (GET_CODE (orig) == CONST)
3184 if (GET_CODE (XEXP (orig, 0)) == PLUS
3185 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3190 gcc_assert (!no_new_pseudos);
3191 reg = gen_reg_rtx (Pmode);
3194 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3196 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3197 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3198 base == reg ? 0 : reg);
3200 if (GET_CODE (offset) == CONST_INT)
3202 /* The base register doesn't really matter, we only want to
3203 test the index for the appropriate mode. */
3204 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3206 gcc_assert (!no_new_pseudos);
3207 offset = force_reg (Pmode, offset);
3210 if (GET_CODE (offset) == CONST_INT)
3211 return plus_constant (base, INTVAL (offset));
3214 if (GET_MODE_SIZE (mode) > 4
3215 && (GET_MODE_CLASS (mode) == MODE_INT
3216 || TARGET_SOFT_FLOAT))
3218 emit_insn (gen_addsi3 (reg, base, offset));
3222 return gen_rtx_PLUS (Pmode, base, offset);
3229 /* Find a spare low register to use during the prolog of a function. */
3232 thumb_find_work_register (unsigned long pushed_regs_mask)
3236 /* Check the argument registers first as these are call-used. The
3237 register allocation order means that sometimes r3 might be used
3238 but earlier argument registers might not, so check them all. */
3239 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3240 if (!regs_ever_live[reg])
3243 /* Before going on to check the call-saved registers we can try a couple
3244 more ways of deducing that r3 is available. The first is when we are
3245 pushing anonymous arguments onto the stack and we have less than 4
3246 registers worth of fixed arguments(*). In this case r3 will be part of
3247 the variable argument list and so we can be sure that it will be
3248 pushed right at the start of the function. Hence it will be available
3249 for the rest of the prologue.
3250 (*): ie current_function_pretend_args_size is greater than 0. */
3251 if (cfun->machine->uses_anonymous_args
3252 && current_function_pretend_args_size > 0)
3253 return LAST_ARG_REGNUM;
3255 /* The other case is when we have fixed arguments but less than 4 registers
3256 worth. In this case r3 might be used in the body of the function, but
3257 it is not being used to convey an argument into the function. In theory
3258 we could just check current_function_args_size to see how many bytes are
3259 being passed in argument registers, but it seems that it is unreliable.
3260 Sometimes it will have the value 0 when in fact arguments are being
3261 passed. (See testcase execute/20021111-1.c for an example). So we also
3262 check the args_info.nregs field as well. The problem with this field is
3263 that it makes no allowances for arguments that are passed to the
3264 function but which are not used. Hence we could miss an opportunity
3265 when a function has an unused argument in r3. But it is better to be
3266 safe than to be sorry. */
3267 if (! cfun->machine->uses_anonymous_args
3268 && current_function_args_size >= 0
3269 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3270 && cfun->args_info.nregs < 4)
3271 return LAST_ARG_REGNUM;
3273 /* Otherwise look for a call-saved register that is going to be pushed. */
3274 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3275 if (pushed_regs_mask & (1 << reg))
3278 /* Something went wrong - thumb_compute_save_reg_mask()
3279 should have arranged for a suitable register to be pushed. */
3284 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3288 arm_load_pic_register (unsigned int scratch)
3290 #ifndef AOF_ASSEMBLER
3291 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3292 rtx global_offset_table;
3294 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3297 gcc_assert (flag_pic);
3299 l1 = gen_label_rtx ();
3301 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3302 /* On the ARM the PC register contains 'dot + 8' at the time of the
3303 addition, on the Thumb it is 'dot + 4'. */
3304 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3306 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3307 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3309 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3311 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3315 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3316 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3320 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3322 /* We will have pushed the pic register, so should always be
3323 able to find a work register. */
3324 pic_tmp = gen_rtx_REG (SImode, scratch);
3325 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3326 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3329 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3330 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3333 /* Need to emit this whether or not we obey regdecls,
3334 since setjmp/longjmp can cause life info to screw up. */
3335 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3336 #endif /* AOF_ASSEMBLER */
3340 /* Return nonzero if X is valid as an ARM state addressing register. */
3342 arm_address_register_rtx_p (rtx x, int strict_p)
3346 if (GET_CODE (x) != REG)
3352 return ARM_REGNO_OK_FOR_BASE_P (regno);
3354 return (regno <= LAST_ARM_REGNUM
3355 || regno >= FIRST_PSEUDO_REGISTER
3356 || regno == FRAME_POINTER_REGNUM
3357 || regno == ARG_POINTER_REGNUM);
3360 /* Return nonzero if X is a valid ARM state address operand. */
3362 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3366 enum rtx_code code = GET_CODE (x);
3368 if (arm_address_register_rtx_p (x, strict_p))
3371 use_ldrd = (TARGET_LDRD
3373 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3375 if (code == POST_INC || code == PRE_DEC
3376 || ((code == PRE_INC || code == POST_DEC)
3377 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3378 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3380 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3381 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3382 && GET_CODE (XEXP (x, 1)) == PLUS
3383 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3385 rtx addend = XEXP (XEXP (x, 1), 1);
3387 /* Don't allow ldrd post increment by register because it's hard
3388 to fixup invalid register choices. */
3390 && GET_CODE (x) == POST_MODIFY
3391 && GET_CODE (addend) == REG)
3394 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3395 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3398 /* After reload constants split into minipools will have addresses
3399 from a LABEL_REF. */
3400 else if (reload_completed
3401 && (code == LABEL_REF
3403 && GET_CODE (XEXP (x, 0)) == PLUS
3404 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3405 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3408 else if (mode == TImode)
3411 else if (code == PLUS)
3413 rtx xop0 = XEXP (x, 0);
3414 rtx xop1 = XEXP (x, 1);
3416 return ((arm_address_register_rtx_p (xop0, strict_p)
3417 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3418 || (arm_address_register_rtx_p (xop1, strict_p)
3419 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3423 /* Reload currently can't handle MINUS, so disable this for now */
3424 else if (GET_CODE (x) == MINUS)
3426 rtx xop0 = XEXP (x, 0);
3427 rtx xop1 = XEXP (x, 1);
3429 return (arm_address_register_rtx_p (xop0, strict_p)
3430 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3434 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3435 && code == SYMBOL_REF
3436 && CONSTANT_POOL_ADDRESS_P (x)
3438 && symbol_mentioned_p (get_pool_constant (x))))
3444 /* Return nonzero if INDEX is valid for an address index operand in
3447 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3450 HOST_WIDE_INT range;
3451 enum rtx_code code = GET_CODE (index);
3453 /* Standard coprocessor addressing modes. */
3454 if (TARGET_HARD_FLOAT
3455 && (TARGET_FPA || TARGET_MAVERICK)
3456 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3457 || (TARGET_MAVERICK && mode == DImode)))
3458 return (code == CONST_INT && INTVAL (index) < 1024
3459 && INTVAL (index) > -1024
3460 && (INTVAL (index) & 3) == 0);
3462 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3463 return (code == CONST_INT
3464 && INTVAL (index) < 1024
3465 && INTVAL (index) > -1024
3466 && (INTVAL (index) & 3) == 0);
3468 if (arm_address_register_rtx_p (index, strict_p)
3469 && (GET_MODE_SIZE (mode) <= 4))
3472 if (mode == DImode || mode == DFmode)
3474 if (code == CONST_INT)
3476 HOST_WIDE_INT val = INTVAL (index);
3479 return val > -256 && val < 256;
3481 return val > -4096 && val < 4092;
3484 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3487 if (GET_MODE_SIZE (mode) <= 4
3490 || (mode == QImode && outer == SIGN_EXTEND))))
3494 rtx xiop0 = XEXP (index, 0);
3495 rtx xiop1 = XEXP (index, 1);
3497 return ((arm_address_register_rtx_p (xiop0, strict_p)
3498 && power_of_two_operand (xiop1, SImode))
3499 || (arm_address_register_rtx_p (xiop1, strict_p)
3500 && power_of_two_operand (xiop0, SImode)));
3502 else if (code == LSHIFTRT || code == ASHIFTRT
3503 || code == ASHIFT || code == ROTATERT)
3505 rtx op = XEXP (index, 1);
3507 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3508 && GET_CODE (op) == CONST_INT
3510 && INTVAL (op) <= 31);
3514 /* For ARM v4 we may be doing a sign-extend operation during the
3518 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3524 range = (mode == HImode) ? 4095 : 4096;
3526 return (code == CONST_INT
3527 && INTVAL (index) < range
3528 && INTVAL (index) > -range);
3531 /* Return nonzero if X is valid as a Thumb state base register. */
3533 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3537 if (GET_CODE (x) != REG)
3543 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3545 return (regno <= LAST_LO_REGNUM
3546 || regno > LAST_VIRTUAL_REGISTER
3547 || regno == FRAME_POINTER_REGNUM
3548 || (GET_MODE_SIZE (mode) >= 4
3549 && (regno == STACK_POINTER_REGNUM
3550 || regno >= FIRST_PSEUDO_REGISTER
3551 || x == hard_frame_pointer_rtx
3552 || x == arg_pointer_rtx)));
3555 /* Return nonzero if x is a legitimate index register. This is the case
3556 for any base register that can access a QImode object. */
3558 thumb_index_register_rtx_p (rtx x, int strict_p)
3560 return thumb_base_register_rtx_p (x, QImode, strict_p);
3563 /* Return nonzero if x is a legitimate Thumb-state address.
3565 The AP may be eliminated to either the SP or the FP, so we use the
3566 least common denominator, e.g. SImode, and offsets from 0 to 64.
3568 ??? Verify whether the above is the right approach.
3570 ??? Also, the FP may be eliminated to the SP, so perhaps that
3571 needs special handling also.
3573 ??? Look at how the mips16 port solves this problem. It probably uses
3574 better ways to solve some of these problems.
3576 Although it is not incorrect, we don't accept QImode and HImode
3577 addresses based on the frame pointer or arg pointer until the
3578 reload pass starts. This is so that eliminating such addresses
3579 into stack based ones won't produce impossible code. */
3581 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3583 /* ??? Not clear if this is right. Experiment. */
3584 if (GET_MODE_SIZE (mode) < 4
3585 && !(reload_in_progress || reload_completed)
3586 && (reg_mentioned_p (frame_pointer_rtx, x)
3587 || reg_mentioned_p (arg_pointer_rtx, x)
3588 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3589 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3590 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3591 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3594 /* Accept any base register. SP only in SImode or larger. */
3595 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3598 /* This is PC relative data before arm_reorg runs. */
3599 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3600 && GET_CODE (x) == SYMBOL_REF
3601 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3604 /* This is PC relative data after arm_reorg runs. */
3605 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3606 && (GET_CODE (x) == LABEL_REF
3607 || (GET_CODE (x) == CONST
3608 && GET_CODE (XEXP (x, 0)) == PLUS
3609 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3610 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3613 /* Post-inc indexing only supported for SImode and larger. */
3614 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3615 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3618 else if (GET_CODE (x) == PLUS)
3620 /* REG+REG address can be any two index registers. */
3621 /* We disallow FRAME+REG addressing since we know that FRAME
3622 will be replaced with STACK, and SP relative addressing only
3623 permits SP+OFFSET. */
3624 if (GET_MODE_SIZE (mode) <= 4
3625 && XEXP (x, 0) != frame_pointer_rtx
3626 && XEXP (x, 1) != frame_pointer_rtx
3627 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3628 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3631 /* REG+const has 5-7 bit offset for non-SP registers. */
3632 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3633 || XEXP (x, 0) == arg_pointer_rtx)
3634 && GET_CODE (XEXP (x, 1)) == CONST_INT
3635 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3638 /* REG+const has 10 bit offset for SP, but only SImode and
3639 larger is supported. */
3640 /* ??? Should probably check for DI/DFmode overflow here
3641 just like GO_IF_LEGITIMATE_OFFSET does. */
3642 else if (GET_CODE (XEXP (x, 0)) == REG
3643 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3644 && GET_MODE_SIZE (mode) >= 4
3645 && GET_CODE (XEXP (x, 1)) == CONST_INT
3646 && INTVAL (XEXP (x, 1)) >= 0
3647 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3648 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3651 else if (GET_CODE (XEXP (x, 0)) == REG
3652 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3653 && GET_MODE_SIZE (mode) >= 4
3654 && GET_CODE (XEXP (x, 1)) == CONST_INT
3655 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3659 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3660 && GET_MODE_SIZE (mode) == 4
3661 && GET_CODE (x) == SYMBOL_REF
3662 && CONSTANT_POOL_ADDRESS_P (x)
3664 && symbol_mentioned_p (get_pool_constant (x))))
3670 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3671 instruction of mode MODE. */
3673 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3675 switch (GET_MODE_SIZE (mode))
3678 return val >= 0 && val < 32;
3681 return val >= 0 && val < 64 && (val & 1) == 0;
3685 && (val + GET_MODE_SIZE (mode)) <= 128
3690 /* Try machine-dependent ways of modifying an illegitimate address
3691 to be legitimate. If we find one, return the new, valid address. */
3693 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3695 if (GET_CODE (x) == PLUS)
3697 rtx xop0 = XEXP (x, 0);
3698 rtx xop1 = XEXP (x, 1);
3700 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3701 xop0 = force_reg (SImode, xop0);
3703 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3704 xop1 = force_reg (SImode, xop1);
3706 if (ARM_BASE_REGISTER_RTX_P (xop0)
3707 && GET_CODE (xop1) == CONST_INT)
3709 HOST_WIDE_INT n, low_n;
3713 /* VFP addressing modes actually allow greater offsets, but for
3714 now we just stick with the lowest common denominator. */
3716 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3728 low_n = ((mode) == TImode ? 0
3729 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3733 base_reg = gen_reg_rtx (SImode);
3734 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3735 GEN_INT (n)), NULL_RTX);
3736 emit_move_insn (base_reg, val);
3737 x = (low_n == 0 ? base_reg
3738 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3740 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3741 x = gen_rtx_PLUS (SImode, xop0, xop1);
3744 /* XXX We don't allow MINUS any more -- see comment in
3745 arm_legitimate_address_p (). */
3746 else if (GET_CODE (x) == MINUS)
3748 rtx xop0 = XEXP (x, 0);
3749 rtx xop1 = XEXP (x, 1);
3751 if (CONSTANT_P (xop0))
3752 xop0 = force_reg (SImode, xop0);
3754 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3755 xop1 = force_reg (SImode, xop1);
3757 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3758 x = gen_rtx_MINUS (SImode, xop0, xop1);
3763 /* We need to find and carefully transform any SYMBOL and LABEL
3764 references; so go back to the original address expression. */
3765 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3767 if (new_x != orig_x)
3775 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3776 to be legitimate. If we find one, return the new, valid address. */
3778 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3780 if (GET_CODE (x) == PLUS
3781 && GET_CODE (XEXP (x, 1)) == CONST_INT
3782 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3783 || INTVAL (XEXP (x, 1)) < 0))
3785 rtx xop0 = XEXP (x, 0);
3786 rtx xop1 = XEXP (x, 1);
3787 HOST_WIDE_INT offset = INTVAL (xop1);
3789 /* Try and fold the offset into a biasing of the base register and
3790 then offsetting that. Don't do this when optimizing for space
3791 since it can cause too many CSEs. */
3792 if (optimize_size && offset >= 0
3793 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3795 HOST_WIDE_INT delta;
3798 delta = offset - (256 - GET_MODE_SIZE (mode));
3799 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3800 delta = 31 * GET_MODE_SIZE (mode);
3802 delta = offset & (~31 * GET_MODE_SIZE (mode));
3804 xop0 = force_operand (plus_constant (xop0, offset - delta),
3806 x = plus_constant (xop0, delta);
3808 else if (offset < 0 && offset > -256)
3809 /* Small negative offsets are best done with a subtract before the
3810 dereference, forcing these into a register normally takes two
3812 x = force_operand (x, NULL_RTX);
3815 /* For the remaining cases, force the constant into a register. */
3816 xop1 = force_reg (SImode, xop1);
3817 x = gen_rtx_PLUS (SImode, xop0, xop1);
3820 else if (GET_CODE (x) == PLUS
3821 && s_register_operand (XEXP (x, 1), SImode)
3822 && !s_register_operand (XEXP (x, 0), SImode))
3824 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3826 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3831 /* We need to find and carefully transform any SYMBOL and LABEL
3832 references; so go back to the original address expression. */
3833 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3835 if (new_x != orig_x)
3844 #define REG_OR_SUBREG_REG(X) \
3845 (GET_CODE (X) == REG \
3846 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3848 #define REG_OR_SUBREG_RTX(X) \
3849 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3851 #ifndef COSTS_N_INSNS
3852 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3855 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3857 enum machine_mode mode = GET_MODE (x);
3870 return COSTS_N_INSNS (1);
3873 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3876 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3883 return COSTS_N_INSNS (2) + cycles;
3885 return COSTS_N_INSNS (1) + 16;
3888 return (COSTS_N_INSNS (1)
3889 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3890 + GET_CODE (SET_DEST (x)) == MEM));
3895 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3897 if (thumb_shiftable_const (INTVAL (x)))
3898 return COSTS_N_INSNS (2);
3899 return COSTS_N_INSNS (3);
3901 else if ((outer == PLUS || outer == COMPARE)
3902 && INTVAL (x) < 256 && INTVAL (x) > -256)
3904 else if (outer == AND
3905 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3906 return COSTS_N_INSNS (1);
3907 else if (outer == ASHIFT || outer == ASHIFTRT
3908 || outer == LSHIFTRT)
3910 return COSTS_N_INSNS (2);
3916 return COSTS_N_INSNS (3);
3934 /* XXX another guess. */
3935 /* Memory costs quite a lot for the first word, but subsequent words
3936 load at the equivalent of a single insn each. */
3937 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3938 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3943 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3948 /* XXX still guessing. */
3949 switch (GET_MODE (XEXP (x, 0)))
3952 return (1 + (mode == DImode ? 4 : 0)
3953 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3956 return (4 + (mode == DImode ? 4 : 0)
3957 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3960 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3972 /* Worker routine for arm_rtx_costs. */
3974 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3976 enum machine_mode mode = GET_MODE (x);
3977 enum rtx_code subcode;
3983 /* Memory costs quite a lot for the first word, but subsequent words
3984 load at the equivalent of a single insn each. */
3985 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3986 + (GET_CODE (x) == SYMBOL_REF
3987 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3993 return optimize_size ? COSTS_N_INSNS (2) : 100;
3996 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4003 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4005 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4006 + ((GET_CODE (XEXP (x, 0)) == REG
4007 || (GET_CODE (XEXP (x, 0)) == SUBREG
4008 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4010 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4011 || (GET_CODE (XEXP (x, 0)) == SUBREG
4012 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4014 + ((GET_CODE (XEXP (x, 1)) == REG
4015 || (GET_CODE (XEXP (x, 1)) == SUBREG
4016 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4017 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4022 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4023 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4024 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4025 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4028 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4029 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4030 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4031 && arm_const_double_rtx (XEXP (x, 1))))
4033 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4034 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4035 && arm_const_double_rtx (XEXP (x, 0))))
4038 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4039 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4040 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4041 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4042 || subcode == ASHIFTRT || subcode == LSHIFTRT
4043 || subcode == ROTATE || subcode == ROTATERT
4045 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4046 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4047 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4048 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4049 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4050 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4051 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4056 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4057 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4058 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4059 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4060 && arm_const_double_rtx (XEXP (x, 1))))
4064 case AND: case XOR: case IOR:
4067 /* Normally the frame registers will be spilt into reg+const during
4068 reload, so it is a bad idea to combine them with other instructions,
4069 since then they might not be moved outside of loops. As a compromise
4070 we allow integration with ops that have a constant as their second
4072 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4073 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4074 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4075 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4076 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4080 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4081 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4082 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4083 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4086 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4087 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4088 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4089 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4090 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4093 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4094 return (1 + extra_cost
4095 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4096 || subcode == LSHIFTRT || subcode == ASHIFTRT
4097 || subcode == ROTATE || subcode == ROTATERT
4099 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4100 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4101 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4102 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4103 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4104 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4110 /* This should have been handled by the CPU specific routines. */
4114 if (arm_arch3m && mode == SImode
4115 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4116 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4117 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4118 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4119 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4120 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4125 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4126 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4130 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4132 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4135 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4143 return 4 + (mode == DImode ? 4 : 0);
4146 if (GET_MODE (XEXP (x, 0)) == QImode)
4147 return (4 + (mode == DImode ? 4 : 0)
4148 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4151 switch (GET_MODE (XEXP (x, 0)))
4154 return (1 + (mode == DImode ? 4 : 0)
4155 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4158 return (4 + (mode == DImode ? 4 : 0)
4159 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4162 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4177 if (const_ok_for_arm (INTVAL (x)))
4178 return outer == SET ? 2 : -1;
4179 else if (outer == AND
4180 && const_ok_for_arm (~INTVAL (x)))
4182 else if ((outer == COMPARE
4183 || outer == PLUS || outer == MINUS)
4184 && const_ok_for_arm (-INTVAL (x)))
4195 if (arm_const_double_rtx (x))
4196 return outer == SET ? 2 : -1;
4197 else if ((outer == COMPARE || outer == PLUS)
4198 && neg_const_double_rtx_ok_for_fpa (x))
4207 /* RTX costs when optimizing for size. */
4209 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4211 enum machine_mode mode = GET_MODE (x);
4215 /* XXX TBD. For now, use the standard costs. */
4216 *total = thumb_rtx_costs (x, code, outer_code);
4223 /* A memory access costs 1 insn if the mode is small, or the address is
4224 a single register, otherwise it costs one insn per word. */
4225 if (REG_P (XEXP (x, 0)))
4226 *total = COSTS_N_INSNS (1);
4228 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4235 /* Needs a libcall, so it costs about this. */
4236 *total = COSTS_N_INSNS (2);
4240 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4242 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4250 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4252 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4255 else if (mode == SImode)
4257 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4258 /* Slightly disparage register shifts, but not by much. */
4259 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4260 *total += 1 + rtx_cost (XEXP (x, 1), code);
4264 /* Needs a libcall. */
4265 *total = COSTS_N_INSNS (2);
4269 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4271 *total = COSTS_N_INSNS (1);
4277 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4278 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4280 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4281 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4282 || subcode1 == ROTATE || subcode1 == ROTATERT
4283 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4284 || subcode1 == ASHIFTRT)
4286 /* It's just the cost of the two operands. */
4291 *total = COSTS_N_INSNS (1);
4295 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4299 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4301 *total = COSTS_N_INSNS (1);
4306 case AND: case XOR: case IOR:
4309 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4311 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4312 || subcode == LSHIFTRT || subcode == ASHIFTRT
4313 || (code == AND && subcode == NOT))
4315 /* It's just the cost of the two operands. */
4321 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4325 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4329 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4330 *total = COSTS_N_INSNS (1);
4333 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4342 if (cc_register (XEXP (x, 0), VOIDmode))
4345 *total = COSTS_N_INSNS (1);
4349 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4350 *total = COSTS_N_INSNS (1);
4352 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4357 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4359 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4360 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4363 *total += COSTS_N_INSNS (1);
4368 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4370 switch (GET_MODE (XEXP (x, 0)))
4373 *total += COSTS_N_INSNS (1);
4377 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4383 *total += COSTS_N_INSNS (2);
4388 *total += COSTS_N_INSNS (1);
4393 if (const_ok_for_arm (INTVAL (x)))
4394 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4395 else if (const_ok_for_arm (~INTVAL (x)))
4396 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4397 else if (const_ok_for_arm (-INTVAL (x)))
4399 if (outer_code == COMPARE || outer_code == PLUS
4400 || outer_code == MINUS)
4403 *total = COSTS_N_INSNS (1);
4406 *total = COSTS_N_INSNS (2);
4412 *total = COSTS_N_INSNS (2);
4416 *total = COSTS_N_INSNS (4);
4420 if (mode != VOIDmode)
4421 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4423 *total = COSTS_N_INSNS (4); /* How knows? */
4428 /* RTX costs for cores with a slow MUL implementation. */
4431 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4433 enum machine_mode mode = GET_MODE (x);
4437 *total = thumb_rtx_costs (x, code, outer_code);
4444 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4451 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4453 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4454 & (unsigned HOST_WIDE_INT) 0xffffffff);
4455 int cost, const_ok = const_ok_for_arm (i);
4456 int j, booth_unit_size;
4458 /* Tune as appropriate. */
4459 cost = const_ok ? 4 : 8;
4460 booth_unit_size = 2;
4461 for (j = 0; i && j < 32; j += booth_unit_size)
4463 i >>= booth_unit_size;
4471 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4472 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4476 *total = arm_rtx_costs_1 (x, code, outer_code);
4482 /* RTX cost for cores with a fast multiply unit (M variants). */
4485 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4487 enum machine_mode mode = GET_MODE (x);
4491 *total = thumb_rtx_costs (x, code, outer_code);
4498 /* There is no point basing this on the tuning, since it is always the
4499 fast variant if it exists at all. */
4501 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4502 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4503 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4510 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4517 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4519 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4520 & (unsigned HOST_WIDE_INT) 0xffffffff);
4521 int cost, const_ok = const_ok_for_arm (i);
4522 int j, booth_unit_size;
4524 /* Tune as appropriate. */
4525 cost = const_ok ? 4 : 8;
4526 booth_unit_size = 8;
4527 for (j = 0; i && j < 32; j += booth_unit_size)
4529 i >>= booth_unit_size;
4537 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4538 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4542 *total = arm_rtx_costs_1 (x, code, outer_code);
4548 /* RTX cost for XScale CPUs. */
4551 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4553 enum machine_mode mode = GET_MODE (x);
4557 *total = thumb_rtx_costs (x, code, outer_code);
4564 /* There is no point basing this on the tuning, since it is always the
4565 fast variant if it exists at all. */
4567 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4568 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4569 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4576 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4583 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4585 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4586 & (unsigned HOST_WIDE_INT) 0xffffffff);
4587 int cost, const_ok = const_ok_for_arm (i);
4588 unsigned HOST_WIDE_INT masked_const;
4590 /* The cost will be related to two insns.
4591 First a load of the constant (MOV or LDR), then a multiply. */
4594 cost += 1; /* LDR is probably more expensive because
4595 of longer result latency. */
4596 masked_const = i & 0xffff8000;
4597 if (masked_const != 0 && masked_const != 0xffff8000)
4599 masked_const = i & 0xf8000000;
4600 if (masked_const == 0 || masked_const == 0xf8000000)
4609 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4610 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4614 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4615 will stall until the multiplication is complete. */
4616 if (GET_CODE (XEXP (x, 0)) == MULT)
4617 *total = 4 + rtx_cost (XEXP (x, 0), code);
4619 *total = arm_rtx_costs_1 (x, code, outer_code);
4623 *total = arm_rtx_costs_1 (x, code, outer_code);
4629 /* RTX costs for 9e (and later) cores. */
4632 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4634 enum machine_mode mode = GET_MODE (x);
4643 *total = COSTS_N_INSNS (3);
4647 *total = thumb_rtx_costs (x, code, outer_code);
4655 /* There is no point basing this on the tuning, since it is always the
4656 fast variant if it exists at all. */
4658 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4659 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4660 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4667 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4684 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4685 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4689 *total = arm_rtx_costs_1 (x, code, outer_code);
4693 /* All address computations that can be done are free, but rtx cost returns
4694 the same for practically all of them. So we weight the different types
4695 of address here in the order (most pref first):
4696 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4698 arm_arm_address_cost (rtx x)
4700 enum rtx_code c = GET_CODE (x);
4702 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4704 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4707 if (c == PLUS || c == MINUS)
4709 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4712 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4722 arm_thumb_address_cost (rtx x)
4724 enum rtx_code c = GET_CODE (x);
4729 && GET_CODE (XEXP (x, 0)) == REG
4730 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4737 arm_address_cost (rtx x)
4739 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4743 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4747 /* Some true dependencies can have a higher cost depending
4748 on precisely how certain input operands are used. */
4750 && REG_NOTE_KIND (link) == 0
4751 && recog_memoized (insn) >= 0
4752 && recog_memoized (dep) >= 0)
4754 int shift_opnum = get_attr_shift (insn);
4755 enum attr_type attr_type = get_attr_type (dep);
4757 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4758 operand for INSN. If we have a shifted input operand and the
4759 instruction we depend on is another ALU instruction, then we may
4760 have to account for an additional stall. */
4761 if (shift_opnum != 0
4762 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4764 rtx shifted_operand;
4767 /* Get the shifted operand. */
4768 extract_insn (insn);
4769 shifted_operand = recog_data.operand[shift_opnum];
4771 /* Iterate over all the operands in DEP. If we write an operand
4772 that overlaps with SHIFTED_OPERAND, then we have increase the
4773 cost of this dependency. */
4775 preprocess_constraints ();
4776 for (opno = 0; opno < recog_data.n_operands; opno++)
4778 /* We can ignore strict inputs. */
4779 if (recog_data.operand_type[opno] == OP_IN)
4782 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4789 /* XXX This is not strictly true for the FPA. */
4790 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4791 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4794 /* Call insns don't incur a stall, even if they follow a load. */
4795 if (REG_NOTE_KIND (link) == 0
4796 && GET_CODE (insn) == CALL_INSN)
4799 if ((i_pat = single_set (insn)) != NULL
4800 && GET_CODE (SET_SRC (i_pat)) == MEM
4801 && (d_pat = single_set (dep)) != NULL
4802 && GET_CODE (SET_DEST (d_pat)) == MEM)
4804 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4805 /* This is a load after a store, there is no conflict if the load reads
4806 from a cached area. Assume that loads from the stack, and from the
4807 constant pool are cached, and that others will miss. This is a
4810 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4811 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4812 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4813 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4820 static int fp_consts_inited = 0;
4822 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4823 static const char * const strings_fp[8] =
4826 "4", "5", "0.5", "10"
4829 static REAL_VALUE_TYPE values_fp[8];
4832 init_fp_table (void)
4838 fp_consts_inited = 1;
4840 fp_consts_inited = 8;
4842 for (i = 0; i < fp_consts_inited; i++)
4844 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4849 /* Return TRUE if rtx X is a valid immediate FP constant. */
4851 arm_const_double_rtx (rtx x)
4856 if (!fp_consts_inited)
4859 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4860 if (REAL_VALUE_MINUS_ZERO (r))
4863 for (i = 0; i < fp_consts_inited; i++)
4864 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4870 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4872 neg_const_double_rtx_ok_for_fpa (rtx x)
4877 if (!fp_consts_inited)
4880 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4881 r = REAL_VALUE_NEGATE (r);
4882 if (REAL_VALUE_MINUS_ZERO (r))
4885 for (i = 0; i < 8; i++)
4886 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4892 /* Predicates for `match_operand' and `match_operator'. */
4894 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4896 cirrus_memory_offset (rtx op)
4898 /* Reject eliminable registers. */
4899 if (! (reload_in_progress || reload_completed)
4900 && ( reg_mentioned_p (frame_pointer_rtx, op)
4901 || reg_mentioned_p (arg_pointer_rtx, op)
4902 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4903 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4904 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4905 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4908 if (GET_CODE (op) == MEM)
4914 /* Match: (mem (reg)). */
4915 if (GET_CODE (ind) == REG)
4921 if (GET_CODE (ind) == PLUS
4922 && GET_CODE (XEXP (ind, 0)) == REG
4923 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4924 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4931 /* Return TRUE if OP is a valid coprocessor memory address pattern.
4932 WB if true if writeback address modes are allowed. */
4935 arm_coproc_mem_operand (rtx op, bool wb)
4939 /* Reject eliminable registers. */
4940 if (! (reload_in_progress || reload_completed)
4941 && ( reg_mentioned_p (frame_pointer_rtx, op)
4942 || reg_mentioned_p (arg_pointer_rtx, op)
4943 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4944 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4945 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4946 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4949 /* Constants are converted into offsets from labels. */
4950 if (GET_CODE (op) != MEM)
4955 if (reload_completed
4956 && (GET_CODE (ind) == LABEL_REF
4957 || (GET_CODE (ind) == CONST
4958 && GET_CODE (XEXP (ind, 0)) == PLUS
4959 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4960 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4963 /* Match: (mem (reg)). */
4964 if (GET_CODE (ind) == REG)
4965 return arm_address_register_rtx_p (ind, 0);
4967 /* Autoincremment addressing modes. */
4969 && (GET_CODE (ind) == PRE_INC
4970 || GET_CODE (ind) == POST_INC
4971 || GET_CODE (ind) == PRE_DEC
4972 || GET_CODE (ind) == POST_DEC))
4973 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4976 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4977 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4978 && GET_CODE (XEXP (ind, 1)) == PLUS
4979 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4980 ind = XEXP (ind, 1);
4985 if (GET_CODE (ind) == PLUS
4986 && GET_CODE (XEXP (ind, 0)) == REG
4987 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4988 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4989 && INTVAL (XEXP (ind, 1)) > -1024
4990 && INTVAL (XEXP (ind, 1)) < 1024
4991 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4997 /* Return true if X is a register that will be eliminated later on. */
4999 arm_eliminable_register (rtx x)
5001 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5002 || REGNO (x) == ARG_POINTER_REGNUM
5003 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5004 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5007 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5008 VFP registers. Otherwise return NO_REGS. */
5011 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
5013 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
5016 return GENERAL_REGS;
5019 /* Values which must be returned in the most-significant end of the return
5023 arm_return_in_msb (tree valtype)
5025 return (TARGET_AAPCS_BASED
5027 && (AGGREGATE_TYPE_P (valtype)
5028 || TREE_CODE (valtype) == COMPLEX_TYPE));
5031 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5032 Use by the Cirrus Maverick code which has to workaround
5033 a hardware bug triggered by such instructions. */
5035 arm_memory_load_p (rtx insn)
5037 rtx body, lhs, rhs;;
5039 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5042 body = PATTERN (insn);
5044 if (GET_CODE (body) != SET)
5047 lhs = XEXP (body, 0);
5048 rhs = XEXP (body, 1);
5050 lhs = REG_OR_SUBREG_RTX (lhs);
5052 /* If the destination is not a general purpose
5053 register we do not have to worry. */
5054 if (GET_CODE (lhs) != REG
5055 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5058 /* As well as loads from memory we also have to react
5059 to loads of invalid constants which will be turned
5060 into loads from the minipool. */
5061 return (GET_CODE (rhs) == MEM
5062 || GET_CODE (rhs) == SYMBOL_REF
5063 || note_invalid_constants (insn, -1, false));
5066 /* Return TRUE if INSN is a Cirrus instruction. */
5068 arm_cirrus_insn_p (rtx insn)
5070 enum attr_cirrus attr;
5072 /* get_attr cannot accept USE or CLOBBER. */
5074 || GET_CODE (insn) != INSN
5075 || GET_CODE (PATTERN (insn)) == USE
5076 || GET_CODE (PATTERN (insn)) == CLOBBER)
5079 attr = get_attr_cirrus (insn);
5081 return attr != CIRRUS_NOT;
5084 /* Cirrus reorg for invalid instruction combinations. */
5086 cirrus_reorg (rtx first)
5088 enum attr_cirrus attr;
5089 rtx body = PATTERN (first);
5093 /* Any branch must be followed by 2 non Cirrus instructions. */
5094 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5097 t = next_nonnote_insn (first);
5099 if (arm_cirrus_insn_p (t))
5102 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5106 emit_insn_after (gen_nop (), first);
5111 /* (float (blah)) is in parallel with a clobber. */
5112 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5113 body = XVECEXP (body, 0, 0);
5115 if (GET_CODE (body) == SET)
5117 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5119 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5120 be followed by a non Cirrus insn. */
5121 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5123 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5124 emit_insn_after (gen_nop (), first);
5128 else if (arm_memory_load_p (first))
5130 unsigned int arm_regno;
5132 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5133 ldr/cfmv64hr combination where the Rd field is the same
5134 in both instructions must be split with a non Cirrus
5141 /* Get Arm register number for ldr insn. */
5142 if (GET_CODE (lhs) == REG)
5143 arm_regno = REGNO (lhs);
5146 gcc_assert (GET_CODE (rhs) == REG);
5147 arm_regno = REGNO (rhs);
5151 first = next_nonnote_insn (first);
5153 if (! arm_cirrus_insn_p (first))
5156 body = PATTERN (first);
5158 /* (float (blah)) is in parallel with a clobber. */
5159 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5160 body = XVECEXP (body, 0, 0);
5162 if (GET_CODE (body) == FLOAT)
5163 body = XEXP (body, 0);
5165 if (get_attr_cirrus (first) == CIRRUS_MOVE
5166 && GET_CODE (XEXP (body, 1)) == REG
5167 && arm_regno == REGNO (XEXP (body, 1)))
5168 emit_insn_after (gen_nop (), first);
5174 /* get_attr cannot accept USE or CLOBBER. */
5176 || GET_CODE (first) != INSN
5177 || GET_CODE (PATTERN (first)) == USE
5178 || GET_CODE (PATTERN (first)) == CLOBBER)
5181 attr = get_attr_cirrus (first);
5183 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5184 must be followed by a non-coprocessor instruction. */
5185 if (attr == CIRRUS_COMPARE)
5189 t = next_nonnote_insn (first);
5191 if (arm_cirrus_insn_p (t))
5194 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5198 emit_insn_after (gen_nop (), first);
5204 /* Return TRUE if X references a SYMBOL_REF. */
5206 symbol_mentioned_p (rtx x)
5211 if (GET_CODE (x) == SYMBOL_REF)
5214 fmt = GET_RTX_FORMAT (GET_CODE (x));
5216 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5222 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5223 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5226 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5233 /* Return TRUE if X references a LABEL_REF. */
5235 label_mentioned_p (rtx x)
5240 if (GET_CODE (x) == LABEL_REF)
5243 fmt = GET_RTX_FORMAT (GET_CODE (x));
5244 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5250 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5251 if (label_mentioned_p (XVECEXP (x, i, j)))
5254 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5264 enum rtx_code code = GET_CODE (x);
5281 /* Return 1 if memory locations are adjacent. */
5283 adjacent_mem_locations (rtx a, rtx b)
5285 /* We don't guarantee to preserve the order of these memory refs. */
5286 if (volatile_refs_p (a) || volatile_refs_p (b))
5289 if ((GET_CODE (XEXP (a, 0)) == REG
5290 || (GET_CODE (XEXP (a, 0)) == PLUS
5291 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5292 && (GET_CODE (XEXP (b, 0)) == REG
5293 || (GET_CODE (XEXP (b, 0)) == PLUS
5294 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5296 HOST_WIDE_INT val0 = 0, val1 = 0;
5300 if (GET_CODE (XEXP (a, 0)) == PLUS)
5302 reg0 = XEXP (XEXP (a, 0), 0);
5303 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5308 if (GET_CODE (XEXP (b, 0)) == PLUS)
5310 reg1 = XEXP (XEXP (b, 0), 0);
5311 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5316 /* Don't accept any offset that will require multiple
5317 instructions to handle, since this would cause the
5318 arith_adjacentmem pattern to output an overlong sequence. */
5319 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5322 /* Don't allow an eliminable register: register elimination can make
5323 the offset too large. */
5324 if (arm_eliminable_register (reg0))
5327 val_diff = val1 - val0;
5331 /* If the target has load delay slots, then there's no benefit
5332 to using an ldm instruction unless the offset is zero and
5333 we are optimizing for size. */
5334 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
5335 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
5336 && (val_diff == 4 || val_diff == -4));
5339 return ((REGNO (reg0) == REGNO (reg1))
5340 && (val_diff == 4 || val_diff == -4));
5347 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5348 HOST_WIDE_INT *load_offset)
5350 int unsorted_regs[4];
5351 HOST_WIDE_INT unsorted_offsets[4];
5356 /* Can only handle 2, 3, or 4 insns at present,
5357 though could be easily extended if required. */
5358 gcc_assert (nops >= 2 && nops <= 4);
5360 /* Loop over the operands and check that the memory references are
5361 suitable (i.e. immediate offsets from the same base register). At
5362 the same time, extract the target register, and the memory
5364 for (i = 0; i < nops; i++)
5369 /* Convert a subreg of a mem into the mem itself. */
5370 if (GET_CODE (operands[nops + i]) == SUBREG)
5371 operands[nops + i] = alter_subreg (operands + (nops + i));
5373 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5375 /* Don't reorder volatile memory references; it doesn't seem worth
5376 looking for the case where the order is ok anyway. */
5377 if (MEM_VOLATILE_P (operands[nops + i]))
5380 offset = const0_rtx;
5382 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5383 || (GET_CODE (reg) == SUBREG
5384 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5385 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5386 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5388 || (GET_CODE (reg) == SUBREG
5389 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5390 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5395 base_reg = REGNO (reg);
5396 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5397 ? REGNO (operands[i])
5398 : REGNO (SUBREG_REG (operands[i])));
5403 if (base_reg != (int) REGNO (reg))
5404 /* Not addressed from the same base register. */
5407 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5408 ? REGNO (operands[i])
5409 : REGNO (SUBREG_REG (operands[i])));
5410 if (unsorted_regs[i] < unsorted_regs[order[0]])
5414 /* If it isn't an integer register, or if it overwrites the
5415 base register but isn't the last insn in the list, then
5416 we can't do this. */
5417 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5418 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5421 unsorted_offsets[i] = INTVAL (offset);
5424 /* Not a suitable memory address. */
5428 /* All the useful information has now been extracted from the
5429 operands into unsorted_regs and unsorted_offsets; additionally,
5430 order[0] has been set to the lowest numbered register in the
5431 list. Sort the registers into order, and check that the memory
5432 offsets are ascending and adjacent. */
5434 for (i = 1; i < nops; i++)
5438 order[i] = order[i - 1];
5439 for (j = 0; j < nops; j++)
5440 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5441 && (order[i] == order[i - 1]
5442 || unsorted_regs[j] < unsorted_regs[order[i]]))
5445 /* Have we found a suitable register? if not, one must be used more
5447 if (order[i] == order[i - 1])
5450 /* Is the memory address adjacent and ascending? */
5451 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5459 for (i = 0; i < nops; i++)
5460 regs[i] = unsorted_regs[order[i]];
5462 *load_offset = unsorted_offsets[order[0]];
5465 if (unsorted_offsets[order[0]] == 0)
5466 return 1; /* ldmia */
5468 if (unsorted_offsets[order[0]] == 4)
5469 return 2; /* ldmib */
5471 if (unsorted_offsets[order[nops - 1]] == 0)
5472 return 3; /* ldmda */
5474 if (unsorted_offsets[order[nops - 1]] == -4)
5475 return 4; /* ldmdb */
5477 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5478 if the offset isn't small enough. The reason 2 ldrs are faster
5479 is because these ARMs are able to do more than one cache access
5480 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5481 whilst the ARM8 has a double bandwidth cache. This means that
5482 these cores can do both an instruction fetch and a data fetch in
5483 a single cycle, so the trick of calculating the address into a
5484 scratch register (one of the result regs) and then doing a load
5485 multiple actually becomes slower (and no smaller in code size).
5486 That is the transformation
5488 ldr rd1, [rbase + offset]
5489 ldr rd2, [rbase + offset + 4]
5493 add rd1, rbase, offset
5494 ldmia rd1, {rd1, rd2}
5496 produces worse code -- '3 cycles + any stalls on rd2' instead of
5497 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5498 access per cycle, the first sequence could never complete in less
5499 than 6 cycles, whereas the ldm sequence would only take 5 and
5500 would make better use of sequential accesses if not hitting the
5503 We cheat here and test 'arm_ld_sched' which we currently know to
5504 only be true for the ARM8, ARM9 and StrongARM. If this ever
5505 changes, then the test below needs to be reworked. */
5506 if (nops == 2 && arm_ld_sched)
5509 /* Can't do it without setting up the offset, only do this if it takes
5510 no more than one insn. */
5511 return (const_ok_for_arm (unsorted_offsets[order[0]])
5512 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5516 emit_ldm_seq (rtx *operands, int nops)
5520 HOST_WIDE_INT offset;
5524 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5527 strcpy (buf, "ldm%?ia\t");
5531 strcpy (buf, "ldm%?ib\t");
5535 strcpy (buf, "ldm%?da\t");
5539 strcpy (buf, "ldm%?db\t");
5544 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5545 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5548 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5549 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5551 output_asm_insn (buf, operands);
5553 strcpy (buf, "ldm%?ia\t");
5560 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5561 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5563 for (i = 1; i < nops; i++)
5564 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5565 reg_names[regs[i]]);
5567 strcat (buf, "}\t%@ phole ldm");
5569 output_asm_insn (buf, operands);
5574 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5575 HOST_WIDE_INT * load_offset)
5577 int unsorted_regs[4];
5578 HOST_WIDE_INT unsorted_offsets[4];
5583 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5584 extended if required. */
5585 gcc_assert (nops >= 2 && nops <= 4);
5587 /* Loop over the operands and check that the memory references are
5588 suitable (i.e. immediate offsets from the same base register). At
5589 the same time, extract the target register, and the memory
5591 for (i = 0; i < nops; i++)
5596 /* Convert a subreg of a mem into the mem itself. */
5597 if (GET_CODE (operands[nops + i]) == SUBREG)
5598 operands[nops + i] = alter_subreg (operands + (nops + i));
5600 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5602 /* Don't reorder volatile memory references; it doesn't seem worth
5603 looking for the case where the order is ok anyway. */
5604 if (MEM_VOLATILE_P (operands[nops + i]))
5607 offset = const0_rtx;
5609 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5610 || (GET_CODE (reg) == SUBREG
5611 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5612 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5613 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5615 || (GET_CODE (reg) == SUBREG
5616 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5617 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5622 base_reg = REGNO (reg);
5623 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5624 ? REGNO (operands[i])
5625 : REGNO (SUBREG_REG (operands[i])));
5630 if (base_reg != (int) REGNO (reg))
5631 /* Not addressed from the same base register. */
5634 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5635 ? REGNO (operands[i])
5636 : REGNO (SUBREG_REG (operands[i])));
5637 if (unsorted_regs[i] < unsorted_regs[order[0]])
5641 /* If it isn't an integer register, then we can't do this. */
5642 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5645 unsorted_offsets[i] = INTVAL (offset);
5648 /* Not a suitable memory address. */
5652 /* All the useful information has now been extracted from the
5653 operands into unsorted_regs and unsorted_offsets; additionally,
5654 order[0] has been set to the lowest numbered register in the
5655 list. Sort the registers into order, and check that the memory
5656 offsets are ascending and adjacent. */
5658 for (i = 1; i < nops; i++)
5662 order[i] = order[i - 1];
5663 for (j = 0; j < nops; j++)
5664 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5665 && (order[i] == order[i - 1]
5666 || unsorted_regs[j] < unsorted_regs[order[i]]))
5669 /* Have we found a suitable register? if not, one must be used more
5671 if (order[i] == order[i - 1])
5674 /* Is the memory address adjacent and ascending? */
5675 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5683 for (i = 0; i < nops; i++)
5684 regs[i] = unsorted_regs[order[i]];
5686 *load_offset = unsorted_offsets[order[0]];
5689 if (unsorted_offsets[order[0]] == 0)
5690 return 1; /* stmia */
5692 if (unsorted_offsets[order[0]] == 4)
5693 return 2; /* stmib */
5695 if (unsorted_offsets[order[nops - 1]] == 0)
5696 return 3; /* stmda */
5698 if (unsorted_offsets[order[nops - 1]] == -4)
5699 return 4; /* stmdb */
5705 emit_stm_seq (rtx *operands, int nops)
5709 HOST_WIDE_INT offset;
5713 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5716 strcpy (buf, "stm%?ia\t");
5720 strcpy (buf, "stm%?ib\t");
5724 strcpy (buf, "stm%?da\t");
5728 strcpy (buf, "stm%?db\t");
5735 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5736 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5738 for (i = 1; i < nops; i++)
5739 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5740 reg_names[regs[i]]);
5742 strcat (buf, "}\t%@ phole stm");
5744 output_asm_insn (buf, operands);
5749 /* Routines for use in generating RTL. */
5752 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5753 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5755 HOST_WIDE_INT offset = *offsetp;
5758 int sign = up ? 1 : -1;
5761 /* XScale has load-store double instructions, but they have stricter
5762 alignment requirements than load-store multiple, so we cannot
5765 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5766 the pipeline until completion.
5774 An ldr instruction takes 1-3 cycles, but does not block the
5783 Best case ldr will always win. However, the more ldr instructions
5784 we issue, the less likely we are to be able to schedule them well.
5785 Using ldr instructions also increases code size.
5787 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5788 for counts of 3 or 4 regs. */
5789 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5795 for (i = 0; i < count; i++)
5797 addr = plus_constant (from, i * 4 * sign);
5798 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5799 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5805 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5815 result = gen_rtx_PARALLEL (VOIDmode,
5816 rtvec_alloc (count + (write_back ? 1 : 0)));
5819 XVECEXP (result, 0, 0)
5820 = gen_rtx_SET (GET_MODE (from), from,
5821 plus_constant (from, count * 4 * sign));
5826 for (j = 0; i < count; i++, j++)
5828 addr = plus_constant (from, j * 4 * sign);
5829 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5830 XVECEXP (result, 0, i)
5831 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5842 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5843 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5845 HOST_WIDE_INT offset = *offsetp;
5848 int sign = up ? 1 : -1;
5851 /* See arm_gen_load_multiple for discussion of
5852 the pros/cons of ldm/stm usage for XScale. */
5853 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5859 for (i = 0; i < count; i++)
5861 addr = plus_constant (to, i * 4 * sign);
5862 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5863 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5869 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5879 result = gen_rtx_PARALLEL (VOIDmode,
5880 rtvec_alloc (count + (write_back ? 1 : 0)));
5883 XVECEXP (result, 0, 0)
5884 = gen_rtx_SET (GET_MODE (to), to,
5885 plus_constant (to, count * 4 * sign));
5890 for (j = 0; i < count; i++, j++)
5892 addr = plus_constant (to, j * 4 * sign);
5893 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5894 XVECEXP (result, 0, i)
5895 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5906 arm_gen_movmemqi (rtx *operands)
5908 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5909 HOST_WIDE_INT srcoffset, dstoffset;
5911 rtx src, dst, srcbase, dstbase;
5912 rtx part_bytes_reg = NULL;
5915 if (GET_CODE (operands[2]) != CONST_INT
5916 || GET_CODE (operands[3]) != CONST_INT
5917 || INTVAL (operands[2]) > 64
5918 || INTVAL (operands[3]) & 3)
5921 dstbase = operands[0];
5922 srcbase = operands[1];
5924 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5925 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5927 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5928 out_words_to_go = INTVAL (operands[2]) / 4;
5929 last_bytes = INTVAL (operands[2]) & 3;
5930 dstoffset = srcoffset = 0;
5932 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5933 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5935 for (i = 0; in_words_to_go >= 2; i+=4)
5937 if (in_words_to_go > 4)
5938 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5939 srcbase, &srcoffset));
5941 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5942 FALSE, srcbase, &srcoffset));
5944 if (out_words_to_go)
5946 if (out_words_to_go > 4)
5947 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5948 dstbase, &dstoffset));
5949 else if (out_words_to_go != 1)
5950 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5954 dstbase, &dstoffset));
5957 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5958 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5959 if (last_bytes != 0)
5961 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5967 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5968 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5971 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5972 if (out_words_to_go)
5976 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5977 sreg = copy_to_reg (mem);
5979 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5980 emit_move_insn (mem, sreg);
5983 gcc_assert (!in_words_to_go); /* Sanity check */
5988 gcc_assert (in_words_to_go > 0);
5990 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5991 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5994 gcc_assert (!last_bytes || part_bytes_reg);
5996 if (BYTES_BIG_ENDIAN && last_bytes)
5998 rtx tmp = gen_reg_rtx (SImode);
6000 /* The bytes we want are in the top end of the word. */
6001 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6002 GEN_INT (8 * (4 - last_bytes))));
6003 part_bytes_reg = tmp;
6007 mem = adjust_automodify_address (dstbase, QImode,
6008 plus_constant (dst, last_bytes - 1),
6009 dstoffset + last_bytes - 1);
6010 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6014 tmp = gen_reg_rtx (SImode);
6015 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6016 part_bytes_reg = tmp;
6025 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6026 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6030 rtx tmp = gen_reg_rtx (SImode);
6031 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6032 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6033 part_bytes_reg = tmp;
6040 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6041 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6048 /* Generate a memory reference for a half word, such that it will be loaded
6049 into the top 16 bits of the word. We can assume that the address is
6050 known to be alignable and of the form reg, or plus (reg, const). */
6053 arm_gen_rotated_half_load (rtx memref)
6055 HOST_WIDE_INT offset = 0;
6056 rtx base = XEXP (memref, 0);
6058 if (GET_CODE (base) == PLUS)
6060 offset = INTVAL (XEXP (base, 1));
6061 base = XEXP (base, 0);
6064 /* If we aren't allowed to generate unaligned addresses, then fail. */
6065 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6068 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6070 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6073 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6076 /* Select a dominance comparison mode if possible for a test of the general
6077 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6078 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6079 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6080 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6081 In all cases OP will be either EQ or NE, but we don't need to know which
6082 here. If we are unable to support a dominance comparison we return
6083 CC mode. This will then fail to match for the RTL expressions that
6084 generate this call. */
6086 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6088 enum rtx_code cond1, cond2;
6091 /* Currently we will probably get the wrong result if the individual
6092 comparisons are not simple. This also ensures that it is safe to
6093 reverse a comparison if necessary. */
6094 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6096 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6100 /* The if_then_else variant of this tests the second condition if the
6101 first passes, but is true if the first fails. Reverse the first
6102 condition to get a true "inclusive-or" expression. */
6103 if (cond_or == DOM_CC_NX_OR_Y)
6104 cond1 = reverse_condition (cond1);
6106 /* If the comparisons are not equal, and one doesn't dominate the other,
6107 then we can't do this. */
6109 && !comparison_dominates_p (cond1, cond2)
6110 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6115 enum rtx_code temp = cond1;
6123 if (cond_or == DOM_CC_X_AND_Y)
6128 case EQ: return CC_DEQmode;
6129 case LE: return CC_DLEmode;
6130 case LEU: return CC_DLEUmode;
6131 case GE: return CC_DGEmode;
6132 case GEU: return CC_DGEUmode;
6133 default: gcc_unreachable ();
6137 if (cond_or == DOM_CC_X_AND_Y)
6153 if (cond_or == DOM_CC_X_AND_Y)
6169 if (cond_or == DOM_CC_X_AND_Y)
6185 if (cond_or == DOM_CC_X_AND_Y)
6200 /* The remaining cases only occur when both comparisons are the
6203 gcc_assert (cond1 == cond2);
6207 gcc_assert (cond1 == cond2);
6211 gcc_assert (cond1 == cond2);
6215 gcc_assert (cond1 == cond2);
6219 gcc_assert (cond1 == cond2);
6228 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6230 /* All floating point compares return CCFP if it is an equality
6231 comparison, and CCFPE otherwise. */
6232 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6252 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6261 /* A compare with a shifted operand. Because of canonicalization, the
6262 comparison will have to be swapped when we emit the assembler. */
6263 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6264 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6265 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6266 || GET_CODE (x) == ROTATERT))
6269 /* This operation is performed swapped, but since we only rely on the Z
6270 flag we don't need an additional mode. */
6271 if (GET_MODE (y) == SImode && REG_P (y)
6272 && GET_CODE (x) == NEG
6273 && (op == EQ || op == NE))
6276 /* This is a special case that is used by combine to allow a
6277 comparison of a shifted byte load to be split into a zero-extend
6278 followed by a comparison of the shifted integer (only valid for
6279 equalities and unsigned inequalities). */
6280 if (GET_MODE (x) == SImode
6281 && GET_CODE (x) == ASHIFT
6282 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6283 && GET_CODE (XEXP (x, 0)) == SUBREG
6284 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6285 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6286 && (op == EQ || op == NE
6287 || op == GEU || op == GTU || op == LTU || op == LEU)
6288 && GET_CODE (y) == CONST_INT)
6291 /* A construct for a conditional compare, if the false arm contains
6292 0, then both conditions must be true, otherwise either condition
6293 must be true. Not all conditions are possible, so CCmode is
6294 returned if it can't be done. */
6295 if (GET_CODE (x) == IF_THEN_ELSE
6296 && (XEXP (x, 2) == const0_rtx
6297 || XEXP (x, 2) == const1_rtx)
6298 && COMPARISON_P (XEXP (x, 0))
6299 && COMPARISON_P (XEXP (x, 1)))
6300 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6301 INTVAL (XEXP (x, 2)));
6303 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6304 if (GET_CODE (x) == AND
6305 && COMPARISON_P (XEXP (x, 0))
6306 && COMPARISON_P (XEXP (x, 1)))
6307 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6310 if (GET_CODE (x) == IOR
6311 && COMPARISON_P (XEXP (x, 0))
6312 && COMPARISON_P (XEXP (x, 1)))
6313 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6316 /* An operation (on Thumb) where we want to test for a single bit.
6317 This is done by shifting that bit up into the top bit of a
6318 scratch register; we can then branch on the sign bit. */
6320 && GET_MODE (x) == SImode
6321 && (op == EQ || op == NE)
6322 && (GET_CODE (x) == ZERO_EXTRACT))
6325 /* An operation that sets the condition codes as a side-effect, the
6326 V flag is not set correctly, so we can only use comparisons where
6327 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6329 if (GET_MODE (x) == SImode
6331 && (op == EQ || op == NE || op == LT || op == GE)
6332 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6333 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6334 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6335 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6336 || GET_CODE (x) == LSHIFTRT
6337 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6338 || GET_CODE (x) == ROTATERT
6339 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6342 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6345 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6346 && GET_CODE (x) == PLUS
6347 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6353 /* X and Y are two things to compare using CODE. Emit the compare insn and
6354 return the rtx for register 0 in the proper mode. FP means this is a
6355 floating point compare: I don't think that it is needed on the arm. */
6357 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6359 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6360 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6362 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6363 gen_rtx_COMPARE (mode, x, y)));
6368 /* Generate a sequence of insns that will generate the correct return
6369 address mask depending on the physical architecture that the program
6372 arm_gen_return_addr_mask (void)
6374 rtx reg = gen_reg_rtx (Pmode);
6376 emit_insn (gen_return_addr_mask (reg));
6381 arm_reload_in_hi (rtx *operands)
6383 rtx ref = operands[1];
6385 HOST_WIDE_INT offset = 0;
6387 if (GET_CODE (ref) == SUBREG)
6389 offset = SUBREG_BYTE (ref);
6390 ref = SUBREG_REG (ref);
6393 if (GET_CODE (ref) == REG)
6395 /* We have a pseudo which has been spilt onto the stack; there
6396 are two cases here: the first where there is a simple
6397 stack-slot replacement and a second where the stack-slot is
6398 out of range, or is used as a subreg. */
6399 if (reg_equiv_mem[REGNO (ref)])
6401 ref = reg_equiv_mem[REGNO (ref)];
6402 base = find_replacement (&XEXP (ref, 0));
6405 /* The slot is out of range, or was dressed up in a SUBREG. */
6406 base = reg_equiv_address[REGNO (ref)];
6409 base = find_replacement (&XEXP (ref, 0));
6411 /* Handle the case where the address is too complex to be offset by 1. */
6412 if (GET_CODE (base) == MINUS
6413 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6415 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6417 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6420 else if (GET_CODE (base) == PLUS)
6422 /* The addend must be CONST_INT, or we would have dealt with it above. */
6423 HOST_WIDE_INT hi, lo;
6425 offset += INTVAL (XEXP (base, 1));
6426 base = XEXP (base, 0);
6428 /* Rework the address into a legal sequence of insns. */
6429 /* Valid range for lo is -4095 -> 4095 */
6432 : -((-offset) & 0xfff));
6434 /* Corner case, if lo is the max offset then we would be out of range
6435 once we have added the additional 1 below, so bump the msb into the
6436 pre-loading insn(s). */
6440 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6441 ^ (HOST_WIDE_INT) 0x80000000)
6442 - (HOST_WIDE_INT) 0x80000000);
6444 gcc_assert (hi + lo == offset);
6448 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6450 /* Get the base address; addsi3 knows how to handle constants
6451 that require more than one insn. */
6452 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6458 /* Operands[2] may overlap operands[0] (though it won't overlap
6459 operands[1]), that's why we asked for a DImode reg -- so we can
6460 use the bit that does not overlap. */
6461 if (REGNO (operands[2]) == REGNO (operands[0]))
6462 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6464 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6466 emit_insn (gen_zero_extendqisi2 (scratch,
6467 gen_rtx_MEM (QImode,
6468 plus_constant (base,
6470 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6471 gen_rtx_MEM (QImode,
6472 plus_constant (base,
6474 if (!BYTES_BIG_ENDIAN)
6475 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6476 gen_rtx_IOR (SImode,
6479 gen_rtx_SUBREG (SImode, operands[0], 0),
6483 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6484 gen_rtx_IOR (SImode,
6485 gen_rtx_ASHIFT (SImode, scratch,
6487 gen_rtx_SUBREG (SImode, operands[0],
6491 /* Handle storing a half-word to memory during reload by synthesizing as two
6492 byte stores. Take care not to clobber the input values until after we
6493 have moved them somewhere safe. This code assumes that if the DImode
6494 scratch in operands[2] overlaps either the input value or output address
6495 in some way, then that value must die in this insn (we absolutely need
6496 two scratch registers for some corner cases). */
6498 arm_reload_out_hi (rtx *operands)
6500 rtx ref = operands[0];
6501 rtx outval = operands[1];
6503 HOST_WIDE_INT offset = 0;
6505 if (GET_CODE (ref) == SUBREG)
6507 offset = SUBREG_BYTE (ref);
6508 ref = SUBREG_REG (ref);
6511 if (GET_CODE (ref) == REG)
6513 /* We have a pseudo which has been spilt onto the stack; there
6514 are two cases here: the first where there is a simple
6515 stack-slot replacement and a second where the stack-slot is
6516 out of range, or is used as a subreg. */
6517 if (reg_equiv_mem[REGNO (ref)])
6519 ref = reg_equiv_mem[REGNO (ref)];
6520 base = find_replacement (&XEXP (ref, 0));
6523 /* The slot is out of range, or was dressed up in a SUBREG. */
6524 base = reg_equiv_address[REGNO (ref)];
6527 base = find_replacement (&XEXP (ref, 0));
6529 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6531 /* Handle the case where the address is too complex to be offset by 1. */
6532 if (GET_CODE (base) == MINUS
6533 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6535 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6537 /* Be careful not to destroy OUTVAL. */
6538 if (reg_overlap_mentioned_p (base_plus, outval))
6540 /* Updating base_plus might destroy outval, see if we can
6541 swap the scratch and base_plus. */
6542 if (!reg_overlap_mentioned_p (scratch, outval))
6545 scratch = base_plus;
6550 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6552 /* Be conservative and copy OUTVAL into the scratch now,
6553 this should only be necessary if outval is a subreg
6554 of something larger than a word. */
6555 /* XXX Might this clobber base? I can't see how it can,
6556 since scratch is known to overlap with OUTVAL, and
6557 must be wider than a word. */
6558 emit_insn (gen_movhi (scratch_hi, outval));
6559 outval = scratch_hi;
6563 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6566 else if (GET_CODE (base) == PLUS)
6568 /* The addend must be CONST_INT, or we would have dealt with it above. */
6569 HOST_WIDE_INT hi, lo;
6571 offset += INTVAL (XEXP (base, 1));
6572 base = XEXP (base, 0);
6574 /* Rework the address into a legal sequence of insns. */
6575 /* Valid range for lo is -4095 -> 4095 */
6578 : -((-offset) & 0xfff));
6580 /* Corner case, if lo is the max offset then we would be out of range
6581 once we have added the additional 1 below, so bump the msb into the
6582 pre-loading insn(s). */
6586 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6587 ^ (HOST_WIDE_INT) 0x80000000)
6588 - (HOST_WIDE_INT) 0x80000000);
6590 gcc_assert (hi + lo == offset);
6594 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6596 /* Be careful not to destroy OUTVAL. */
6597 if (reg_overlap_mentioned_p (base_plus, outval))
6599 /* Updating base_plus might destroy outval, see if we
6600 can swap the scratch and base_plus. */
6601 if (!reg_overlap_mentioned_p (scratch, outval))
6604 scratch = base_plus;
6609 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6611 /* Be conservative and copy outval into scratch now,
6612 this should only be necessary if outval is a
6613 subreg of something larger than a word. */
6614 /* XXX Might this clobber base? I can't see how it
6615 can, since scratch is known to overlap with
6617 emit_insn (gen_movhi (scratch_hi, outval));
6618 outval = scratch_hi;
6622 /* Get the base address; addsi3 knows how to handle constants
6623 that require more than one insn. */
6624 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6630 if (BYTES_BIG_ENDIAN)
6632 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6633 plus_constant (base, offset + 1)),
6634 gen_lowpart (QImode, outval)));
6635 emit_insn (gen_lshrsi3 (scratch,
6636 gen_rtx_SUBREG (SImode, outval, 0),
6638 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6639 gen_lowpart (QImode, scratch)));
6643 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6644 gen_lowpart (QImode, outval)));
6645 emit_insn (gen_lshrsi3 (scratch,
6646 gen_rtx_SUBREG (SImode, outval, 0),
6648 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6649 plus_constant (base, offset + 1)),
6650 gen_lowpart (QImode, scratch)));
6654 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
6655 (padded to the size of a word) should be passed in a register. */
6658 arm_must_pass_in_stack (enum machine_mode mode, tree type)
6660 if (TARGET_AAPCS_BASED)
6661 return must_pass_in_stack_var_size (mode, type);
6663 return must_pass_in_stack_var_size_or_pad (mode, type);
6667 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
6668 Return true if an argument passed on the stack should be padded upwards,
6669 i.e. if the least-significant byte has useful data.
6670 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
6671 aggregate types are placed in the lowest memory address. */
6674 arm_pad_arg_upward (enum machine_mode mode, tree type)
6676 if (!TARGET_AAPCS_BASED)
6677 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
6679 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
6686 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6687 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
6688 byte of the register has useful data, and return the opposite if the
6689 most significant byte does.
6690 For AAPCS, small aggregates and small complex types are always padded
6694 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
6695 tree type, int first ATTRIBUTE_UNUSED)
6697 if (TARGET_AAPCS_BASED
6699 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
6700 && int_size_in_bytes (type) <= 4)
6703 /* Otherwise, use default padding. */
6704 return !BYTES_BIG_ENDIAN;
6709 /* Print a symbolic form of X to the debug file, F. */
6711 arm_print_value (FILE *f, rtx x)
6713 switch (GET_CODE (x))
6716 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6720 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6728 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6730 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6731 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6739 fprintf (f, "\"%s\"", XSTR (x, 0));
6743 fprintf (f, "`%s'", XSTR (x, 0));
6747 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6751 arm_print_value (f, XEXP (x, 0));
6755 arm_print_value (f, XEXP (x, 0));
6757 arm_print_value (f, XEXP (x, 1));
6765 fprintf (f, "????");
6770 /* Routines for manipulation of the constant pool. */
6772 /* Arm instructions cannot load a large constant directly into a
6773 register; they have to come from a pc relative load. The constant
6774 must therefore be placed in the addressable range of the pc
6775 relative load. Depending on the precise pc relative load
6776 instruction the range is somewhere between 256 bytes and 4k. This
6777 means that we often have to dump a constant inside a function, and
6778 generate code to branch around it.
6780 It is important to minimize this, since the branches will slow
6781 things down and make the code larger.
6783 Normally we can hide the table after an existing unconditional
6784 branch so that there is no interruption of the flow, but in the
6785 worst case the code looks like this:
6803 We fix this by performing a scan after scheduling, which notices
6804 which instructions need to have their operands fetched from the
6805 constant table and builds the table.
6807 The algorithm starts by building a table of all the constants that
6808 need fixing up and all the natural barriers in the function (places
6809 where a constant table can be dropped without breaking the flow).
6810 For each fixup we note how far the pc-relative replacement will be
6811 able to reach and the offset of the instruction into the function.
6813 Having built the table we then group the fixes together to form
6814 tables that are as large as possible (subject to addressing
6815 constraints) and emit each table of constants after the last
6816 barrier that is within range of all the instructions in the group.
6817 If a group does not contain a barrier, then we forcibly create one
6818 by inserting a jump instruction into the flow. Once the table has
6819 been inserted, the insns are then modified to reference the
6820 relevant entry in the pool.
6822 Possible enhancements to the algorithm (not implemented) are:
6824 1) For some processors and object formats, there may be benefit in
6825 aligning the pools to the start of cache lines; this alignment
6826 would need to be taken into account when calculating addressability
6829 /* These typedefs are located at the start of this file, so that
6830 they can be used in the prototypes there. This comment is to
6831 remind readers of that fact so that the following structures
6832 can be understood more easily.
6834 typedef struct minipool_node Mnode;
6835 typedef struct minipool_fixup Mfix; */
6837 struct minipool_node
6839 /* Doubly linked chain of entries. */
6842 /* The maximum offset into the code that this entry can be placed. While
6843 pushing fixes for forward references, all entries are sorted in order
6844 of increasing max_address. */
6845 HOST_WIDE_INT max_address;
6846 /* Similarly for an entry inserted for a backwards ref. */
6847 HOST_WIDE_INT min_address;
6848 /* The number of fixes referencing this entry. This can become zero
6849 if we "unpush" an entry. In this case we ignore the entry when we
6850 come to emit the code. */
6852 /* The offset from the start of the minipool. */
6853 HOST_WIDE_INT offset;
6854 /* The value in table. */
6856 /* The mode of value. */
6857 enum machine_mode mode;
6858 /* The size of the value. With iWMMXt enabled
6859 sizes > 4 also imply an alignment of 8-bytes. */
6863 struct minipool_fixup
6867 HOST_WIDE_INT address;
6869 enum machine_mode mode;
6873 HOST_WIDE_INT forwards;
6874 HOST_WIDE_INT backwards;
6877 /* Fixes less than a word need padding out to a word boundary. */
6878 #define MINIPOOL_FIX_SIZE(mode) \
6879 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6881 static Mnode * minipool_vector_head;
6882 static Mnode * minipool_vector_tail;
6883 static rtx minipool_vector_label;
6885 /* The linked list of all minipool fixes required for this function. */
6886 Mfix * minipool_fix_head;
6887 Mfix * minipool_fix_tail;
6888 /* The fix entry for the current minipool, once it has been placed. */
6889 Mfix * minipool_barrier;
6891 /* Determines if INSN is the start of a jump table. Returns the end
6892 of the TABLE or NULL_RTX. */
6894 is_jump_table (rtx insn)
6898 if (GET_CODE (insn) == JUMP_INSN
6899 && JUMP_LABEL (insn) != NULL
6900 && ((table = next_real_insn (JUMP_LABEL (insn)))
6901 == next_real_insn (insn))
6903 && GET_CODE (table) == JUMP_INSN
6904 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6905 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6911 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6912 #define JUMP_TABLES_IN_TEXT_SECTION 0
6915 static HOST_WIDE_INT
6916 get_jump_table_size (rtx insn)
6918 /* ADDR_VECs only take room if read-only data does into the text
6920 if (JUMP_TABLES_IN_TEXT_SECTION
6921 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6926 rtx body = PATTERN (insn);
6927 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6929 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6935 /* Move a minipool fix MP from its current location to before MAX_MP.
6936 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6937 constraints may need updating. */
6939 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6940 HOST_WIDE_INT max_address)
6942 /* The code below assumes these are different. */
6943 gcc_assert (mp != max_mp);
6947 if (max_address < mp->max_address)
6948 mp->max_address = max_address;
6952 if (max_address > max_mp->max_address - mp->fix_size)
6953 mp->max_address = max_mp->max_address - mp->fix_size;
6955 mp->max_address = max_address;
6957 /* Unlink MP from its current position. Since max_mp is non-null,
6958 mp->prev must be non-null. */
6959 mp->prev->next = mp->next;
6960 if (mp->next != NULL)
6961 mp->next->prev = mp->prev;
6963 minipool_vector_tail = mp->prev;
6965 /* Re-insert it before MAX_MP. */
6967 mp->prev = max_mp->prev;
6970 if (mp->prev != NULL)
6971 mp->prev->next = mp;
6973 minipool_vector_head = mp;
6976 /* Save the new entry. */
6979 /* Scan over the preceding entries and adjust their addresses as
6981 while (mp->prev != NULL
6982 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6984 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6991 /* Add a constant to the minipool for a forward reference. Returns the
6992 node added or NULL if the constant will not fit in this pool. */
6994 add_minipool_forward_ref (Mfix *fix)
6996 /* If set, max_mp is the first pool_entry that has a lower
6997 constraint than the one we are trying to add. */
6998 Mnode * max_mp = NULL;
6999 HOST_WIDE_INT max_address = fix->address + fix->forwards;
7002 /* If this fix's address is greater than the address of the first
7003 entry, then we can't put the fix in this pool. We subtract the
7004 size of the current fix to ensure that if the table is fully
7005 packed we still have enough room to insert this value by shuffling
7006 the other fixes forwards. */
7007 if (minipool_vector_head &&
7008 fix->address >= minipool_vector_head->max_address - fix->fix_size)
7011 /* Scan the pool to see if a constant with the same value has
7012 already been added. While we are doing this, also note the
7013 location where we must insert the constant if it doesn't already
7015 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7017 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7018 && fix->mode == mp->mode
7019 && (GET_CODE (fix->value) != CODE_LABEL
7020 || (CODE_LABEL_NUMBER (fix->value)
7021 == CODE_LABEL_NUMBER (mp->value)))
7022 && rtx_equal_p (fix->value, mp->value))
7024 /* More than one fix references this entry. */
7026 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7029 /* Note the insertion point if necessary. */
7031 && mp->max_address > max_address)
7034 /* If we are inserting an 8-bytes aligned quantity and
7035 we have not already found an insertion point, then
7036 make sure that all such 8-byte aligned quantities are
7037 placed at the start of the pool. */
7038 if (ARM_DOUBLEWORD_ALIGN
7040 && fix->fix_size == 8
7041 && mp->fix_size != 8)
7044 max_address = mp->max_address;
7048 /* The value is not currently in the minipool, so we need to create
7049 a new entry for it. If MAX_MP is NULL, the entry will be put on
7050 the end of the list since the placement is less constrained than
7051 any existing entry. Otherwise, we insert the new fix before
7052 MAX_MP and, if necessary, adjust the constraints on the other
7054 mp = xmalloc (sizeof (* mp));
7055 mp->fix_size = fix->fix_size;
7056 mp->mode = fix->mode;
7057 mp->value = fix->value;
7059 /* Not yet required for a backwards ref. */
7060 mp->min_address = -65536;
7064 mp->max_address = max_address;
7066 mp->prev = minipool_vector_tail;
7068 if (mp->prev == NULL)
7070 minipool_vector_head = mp;
7071 minipool_vector_label = gen_label_rtx ();
7074 mp->prev->next = mp;
7076 minipool_vector_tail = mp;
7080 if (max_address > max_mp->max_address - mp->fix_size)
7081 mp->max_address = max_mp->max_address - mp->fix_size;
7083 mp->max_address = max_address;
7086 mp->prev = max_mp->prev;
7088 if (mp->prev != NULL)
7089 mp->prev->next = mp;
7091 minipool_vector_head = mp;
7094 /* Save the new entry. */
7097 /* Scan over the preceding entries and adjust their addresses as
7099 while (mp->prev != NULL
7100 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7102 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7110 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7111 HOST_WIDE_INT min_address)
7113 HOST_WIDE_INT offset;
7115 /* The code below assumes these are different. */
7116 gcc_assert (mp != min_mp);
7120 if (min_address > mp->min_address)
7121 mp->min_address = min_address;
7125 /* We will adjust this below if it is too loose. */
7126 mp->min_address = min_address;
7128 /* Unlink MP from its current position. Since min_mp is non-null,
7129 mp->next must be non-null. */
7130 mp->next->prev = mp->prev;
7131 if (mp->prev != NULL)
7132 mp->prev->next = mp->next;
7134 minipool_vector_head = mp->next;
7136 /* Reinsert it after MIN_MP. */
7138 mp->next = min_mp->next;
7140 if (mp->next != NULL)
7141 mp->next->prev = mp;
7143 minipool_vector_tail = mp;
7149 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7151 mp->offset = offset;
7152 if (mp->refcount > 0)
7153 offset += mp->fix_size;
7155 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7156 mp->next->min_address = mp->min_address + mp->fix_size;
7162 /* Add a constant to the minipool for a backward reference. Returns the
7163 node added or NULL if the constant will not fit in this pool.
7165 Note that the code for insertion for a backwards reference can be
7166 somewhat confusing because the calculated offsets for each fix do
7167 not take into account the size of the pool (which is still under
7170 add_minipool_backward_ref (Mfix *fix)
7172 /* If set, min_mp is the last pool_entry that has a lower constraint
7173 than the one we are trying to add. */
7174 Mnode *min_mp = NULL;
7175 /* This can be negative, since it is only a constraint. */
7176 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7179 /* If we can't reach the current pool from this insn, or if we can't
7180 insert this entry at the end of the pool without pushing other
7181 fixes out of range, then we don't try. This ensures that we
7182 can't fail later on. */
7183 if (min_address >= minipool_barrier->address
7184 || (minipool_vector_tail->min_address + fix->fix_size
7185 >= minipool_barrier->address))
7188 /* Scan the pool to see if a constant with the same value has
7189 already been added. While we are doing this, also note the
7190 location where we must insert the constant if it doesn't already
7192 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7194 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7195 && fix->mode == mp->mode
7196 && (GET_CODE (fix->value) != CODE_LABEL
7197 || (CODE_LABEL_NUMBER (fix->value)
7198 == CODE_LABEL_NUMBER (mp->value)))
7199 && rtx_equal_p (fix->value, mp->value)
7200 /* Check that there is enough slack to move this entry to the
7201 end of the table (this is conservative). */
7203 > (minipool_barrier->address
7204 + minipool_vector_tail->offset
7205 + minipool_vector_tail->fix_size)))
7208 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7212 mp->min_address += fix->fix_size;
7215 /* Note the insertion point if necessary. */
7216 if (mp->min_address < min_address)
7218 /* For now, we do not allow the insertion of 8-byte alignment
7219 requiring nodes anywhere but at the start of the pool. */
7220 if (ARM_DOUBLEWORD_ALIGN
7221 && fix->fix_size == 8 && mp->fix_size != 8)
7226 else if (mp->max_address
7227 < minipool_barrier->address + mp->offset + fix->fix_size)
7229 /* Inserting before this entry would push the fix beyond
7230 its maximum address (which can happen if we have
7231 re-located a forwards fix); force the new fix to come
7234 min_address = mp->min_address + fix->fix_size;
7236 /* If we are inserting an 8-bytes aligned quantity and
7237 we have not already found an insertion point, then
7238 make sure that all such 8-byte aligned quantities are
7239 placed at the start of the pool. */
7240 else if (ARM_DOUBLEWORD_ALIGN
7242 && fix->fix_size == 8
7243 && mp->fix_size < 8)
7246 min_address = mp->min_address + fix->fix_size;
7251 /* We need to create a new entry. */
7252 mp = xmalloc (sizeof (* mp));
7253 mp->fix_size = fix->fix_size;
7254 mp->mode = fix->mode;
7255 mp->value = fix->value;
7257 mp->max_address = minipool_barrier->address + 65536;
7259 mp->min_address = min_address;
7264 mp->next = minipool_vector_head;
7266 if (mp->next == NULL)
7268 minipool_vector_tail = mp;
7269 minipool_vector_label = gen_label_rtx ();
7272 mp->next->prev = mp;
7274 minipool_vector_head = mp;
7278 mp->next = min_mp->next;
7282 if (mp->next != NULL)
7283 mp->next->prev = mp;
7285 minipool_vector_tail = mp;
7288 /* Save the new entry. */
7296 /* Scan over the following entries and adjust their offsets. */
7297 while (mp->next != NULL)
7299 if (mp->next->min_address < mp->min_address + mp->fix_size)
7300 mp->next->min_address = mp->min_address + mp->fix_size;
7303 mp->next->offset = mp->offset + mp->fix_size;
7305 mp->next->offset = mp->offset;
7314 assign_minipool_offsets (Mfix *barrier)
7316 HOST_WIDE_INT offset = 0;
7319 minipool_barrier = barrier;
7321 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7323 mp->offset = offset;
7325 if (mp->refcount > 0)
7326 offset += mp->fix_size;
7330 /* Output the literal table */
7332 dump_minipool (rtx scan)
7338 if (ARM_DOUBLEWORD_ALIGN)
7339 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7340 if (mp->refcount > 0 && mp->fix_size == 8)
7348 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7349 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7351 scan = emit_label_after (gen_label_rtx (), scan);
7352 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7353 scan = emit_label_after (minipool_vector_label, scan);
7355 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7357 if (mp->refcount > 0)
7362 ";; Offset %u, min %ld, max %ld ",
7363 (unsigned) mp->offset, (unsigned long) mp->min_address,
7364 (unsigned long) mp->max_address);
7365 arm_print_value (dump_file, mp->value);
7366 fputc ('\n', dump_file);
7369 switch (mp->fix_size)
7371 #ifdef HAVE_consttable_1
7373 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7377 #ifdef HAVE_consttable_2
7379 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7383 #ifdef HAVE_consttable_4
7385 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7389 #ifdef HAVE_consttable_8
7391 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7404 minipool_vector_head = minipool_vector_tail = NULL;
7405 scan = emit_insn_after (gen_consttable_end (), scan);
7406 scan = emit_barrier_after (scan);
7409 /* Return the cost of forcibly inserting a barrier after INSN. */
7411 arm_barrier_cost (rtx insn)
7413 /* Basing the location of the pool on the loop depth is preferable,
7414 but at the moment, the basic block information seems to be
7415 corrupt by this stage of the compilation. */
7417 rtx next = next_nonnote_insn (insn);
7419 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7422 switch (GET_CODE (insn))
7425 /* It will always be better to place the table before the label, rather
7434 return base_cost - 10;
7437 return base_cost + 10;
7441 /* Find the best place in the insn stream in the range
7442 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7443 Create the barrier by inserting a jump and add a new fix entry for
7446 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7448 HOST_WIDE_INT count = 0;
7450 rtx from = fix->insn;
7451 rtx selected = from;
7453 HOST_WIDE_INT selected_address;
7455 HOST_WIDE_INT max_count = max_address - fix->address;
7456 rtx label = gen_label_rtx ();
7458 selected_cost = arm_barrier_cost (from);
7459 selected_address = fix->address;
7461 while (from && count < max_count)
7466 /* This code shouldn't have been called if there was a natural barrier
7468 gcc_assert (GET_CODE (from) != BARRIER);
7470 /* Count the length of this insn. */
7471 count += get_attr_length (from);
7473 /* If there is a jump table, add its length. */
7474 tmp = is_jump_table (from);
7477 count += get_jump_table_size (tmp);
7479 /* Jump tables aren't in a basic block, so base the cost on
7480 the dispatch insn. If we select this location, we will
7481 still put the pool after the table. */
7482 new_cost = arm_barrier_cost (from);
7484 if (count < max_count && new_cost <= selected_cost)
7487 selected_cost = new_cost;
7488 selected_address = fix->address + count;
7491 /* Continue after the dispatch table. */
7492 from = NEXT_INSN (tmp);
7496 new_cost = arm_barrier_cost (from);
7498 if (count < max_count && new_cost <= selected_cost)
7501 selected_cost = new_cost;
7502 selected_address = fix->address + count;
7505 from = NEXT_INSN (from);
7508 /* Create a new JUMP_INSN that branches around a barrier. */
7509 from = emit_jump_insn_after (gen_jump (label), selected);
7510 JUMP_LABEL (from) = label;
7511 barrier = emit_barrier_after (from);
7512 emit_label_after (label, barrier);
7514 /* Create a minipool barrier entry for the new barrier. */
7515 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7516 new_fix->insn = barrier;
7517 new_fix->address = selected_address;
7518 new_fix->next = fix->next;
7519 fix->next = new_fix;
7524 /* Record that there is a natural barrier in the insn stream at
7527 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7529 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7532 fix->address = address;
7535 if (minipool_fix_head != NULL)
7536 minipool_fix_tail->next = fix;
7538 minipool_fix_head = fix;
7540 minipool_fix_tail = fix;
7543 /* Record INSN, which will need fixing up to load a value from the
7544 minipool. ADDRESS is the offset of the insn since the start of the
7545 function; LOC is a pointer to the part of the insn which requires
7546 fixing; VALUE is the constant that must be loaded, which is of type
7549 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7550 enum machine_mode mode, rtx value)
7552 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7554 #ifdef AOF_ASSEMBLER
7555 /* PIC symbol references need to be converted into offsets into the
7557 /* XXX This shouldn't be done here. */
7558 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7559 value = aof_pic_entry (value);
7560 #endif /* AOF_ASSEMBLER */
7563 fix->address = address;
7566 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7568 fix->forwards = get_attr_pool_range (insn);
7569 fix->backwards = get_attr_neg_pool_range (insn);
7570 fix->minipool = NULL;
7572 /* If an insn doesn't have a range defined for it, then it isn't
7573 expecting to be reworked by this code. Better to stop now than
7574 to generate duff assembly code. */
7575 gcc_assert (fix->forwards || fix->backwards);
7577 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7578 So there might be an empty word before the start of the pool.
7579 Hence we reduce the forward range by 4 to allow for this
7581 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7587 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7588 GET_MODE_NAME (mode),
7589 INSN_UID (insn), (unsigned long) address,
7590 -1 * (long)fix->backwards, (long)fix->forwards);
7591 arm_print_value (dump_file, fix->value);
7592 fprintf (dump_file, "\n");
7595 /* Add it to the chain of fixes. */
7598 if (minipool_fix_head != NULL)
7599 minipool_fix_tail->next = fix;
7601 minipool_fix_head = fix;
7603 minipool_fix_tail = fix;
7606 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7607 Returns the number of insns needed, or 99 if we don't know how to
7610 arm_const_double_inline_cost (rtx val)
7612 rtx lowpart, highpart;
7613 enum machine_mode mode;
7615 mode = GET_MODE (val);
7617 if (mode == VOIDmode)
7620 gcc_assert (GET_MODE_SIZE (mode) == 8);
7622 lowpart = gen_lowpart (SImode, val);
7623 highpart = gen_highpart_mode (SImode, mode, val);
7625 gcc_assert (GET_CODE (lowpart) == CONST_INT);
7626 gcc_assert (GET_CODE (highpart) == CONST_INT);
7628 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
7629 NULL_RTX, NULL_RTX, 0, 0)
7630 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
7631 NULL_RTX, NULL_RTX, 0, 0));
7634 /* Return true if it is worthwhile to split a 64-bit constant into two
7635 32-bit operations. This is the case if optimizing for size, or
7636 if we have load delay slots, or if one 32-bit part can be done with
7637 a single data operation. */
7639 arm_const_double_by_parts (rtx val)
7641 enum machine_mode mode = GET_MODE (val);
7644 if (optimize_size || arm_ld_sched)
7647 if (mode == VOIDmode)
7650 part = gen_highpart_mode (SImode, mode, val);
7652 gcc_assert (GET_CODE (part) == CONST_INT);
7654 if (const_ok_for_arm (INTVAL (part))
7655 || const_ok_for_arm (~INTVAL (part)))
7658 part = gen_lowpart (SImode, val);
7660 gcc_assert (GET_CODE (part) == CONST_INT);
7662 if (const_ok_for_arm (INTVAL (part))
7663 || const_ok_for_arm (~INTVAL (part)))
7669 /* Scan INSN and note any of its operands that need fixing.
7670 If DO_PUSHES is false we do not actually push any of the fixups
7671 needed. The function returns TRUE if any fixups were needed/pushed.
7672 This is used by arm_memory_load_p() which needs to know about loads
7673 of constants that will be converted into minipool loads. */
7675 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7677 bool result = false;
7680 extract_insn (insn);
7682 if (!constrain_operands (1))
7683 fatal_insn_not_found (insn);
7685 if (recog_data.n_alternatives == 0)
7688 /* Fill in recog_op_alt with information about the constraints of
7690 preprocess_constraints ();
7692 for (opno = 0; opno < recog_data.n_operands; opno++)
7694 /* Things we need to fix can only occur in inputs. */
7695 if (recog_data.operand_type[opno] != OP_IN)
7698 /* If this alternative is a memory reference, then any mention
7699 of constants in this alternative is really to fool reload
7700 into allowing us to accept one there. We need to fix them up
7701 now so that we output the right code. */
7702 if (recog_op_alt[opno][which_alternative].memory_ok)
7704 rtx op = recog_data.operand[opno];
7706 if (CONSTANT_P (op))
7709 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7710 recog_data.operand_mode[opno], op);
7713 else if (GET_CODE (op) == MEM
7714 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7715 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7719 rtx cop = avoid_constant_pool_reference (op);
7721 /* Casting the address of something to a mode narrower
7722 than a word can cause avoid_constant_pool_reference()
7723 to return the pool reference itself. That's no good to
7724 us here. Lets just hope that we can use the
7725 constant pool value directly. */
7727 cop = get_pool_constant (XEXP (op, 0));
7729 push_minipool_fix (insn, address,
7730 recog_data.operand_loc[opno],
7731 recog_data.operand_mode[opno], cop);
7742 /* Gcc puts the pool in the wrong place for ARM, since we can only
7743 load addresses a limited distance around the pc. We do some
7744 special munging to move the constant pool values to the correct
7745 point in the code. */
7750 HOST_WIDE_INT address = 0;
7753 minipool_fix_head = minipool_fix_tail = NULL;
7755 /* The first insn must always be a note, or the code below won't
7756 scan it properly. */
7757 insn = get_insns ();
7758 gcc_assert (GET_CODE (insn) == NOTE);
7760 /* Scan all the insns and record the operands that will need fixing. */
7761 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7763 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7764 && (arm_cirrus_insn_p (insn)
7765 || GET_CODE (insn) == JUMP_INSN
7766 || arm_memory_load_p (insn)))
7767 cirrus_reorg (insn);
7769 if (GET_CODE (insn) == BARRIER)
7770 push_minipool_barrier (insn, address);
7771 else if (INSN_P (insn))
7775 note_invalid_constants (insn, address, true);
7776 address += get_attr_length (insn);
7778 /* If the insn is a vector jump, add the size of the table
7779 and skip the table. */
7780 if ((table = is_jump_table (insn)) != NULL)
7782 address += get_jump_table_size (table);
7788 fix = minipool_fix_head;
7790 /* Now scan the fixups and perform the required changes. */
7795 Mfix * last_added_fix;
7796 Mfix * last_barrier = NULL;
7799 /* Skip any further barriers before the next fix. */
7800 while (fix && GET_CODE (fix->insn) == BARRIER)
7803 /* No more fixes. */
7807 last_added_fix = NULL;
7809 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7811 if (GET_CODE (ftmp->insn) == BARRIER)
7813 if (ftmp->address >= minipool_vector_head->max_address)
7816 last_barrier = ftmp;
7818 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7821 last_added_fix = ftmp; /* Keep track of the last fix added. */
7824 /* If we found a barrier, drop back to that; any fixes that we
7825 could have reached but come after the barrier will now go in
7826 the next mini-pool. */
7827 if (last_barrier != NULL)
7829 /* Reduce the refcount for those fixes that won't go into this
7831 for (fdel = last_barrier->next;
7832 fdel && fdel != ftmp;
7835 fdel->minipool->refcount--;
7836 fdel->minipool = NULL;
7839 ftmp = last_barrier;
7843 /* ftmp is first fix that we can't fit into this pool and
7844 there no natural barriers that we could use. Insert a
7845 new barrier in the code somewhere between the previous
7846 fix and this one, and arrange to jump around it. */
7847 HOST_WIDE_INT max_address;
7849 /* The last item on the list of fixes must be a barrier, so
7850 we can never run off the end of the list of fixes without
7851 last_barrier being set. */
7854 max_address = minipool_vector_head->max_address;
7855 /* Check that there isn't another fix that is in range that
7856 we couldn't fit into this pool because the pool was
7857 already too large: we need to put the pool before such an
7859 if (ftmp->address < max_address)
7860 max_address = ftmp->address;
7862 last_barrier = create_fix_barrier (last_added_fix, max_address);
7865 assign_minipool_offsets (last_barrier);
7869 if (GET_CODE (ftmp->insn) != BARRIER
7870 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7877 /* Scan over the fixes we have identified for this pool, fixing them
7878 up and adding the constants to the pool itself. */
7879 for (this_fix = fix; this_fix && ftmp != this_fix;
7880 this_fix = this_fix->next)
7881 if (GET_CODE (this_fix->insn) != BARRIER)
7884 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7885 minipool_vector_label),
7886 this_fix->minipool->offset);
7887 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7890 dump_minipool (last_barrier->insn);
7894 /* From now on we must synthesize any constants that we can't handle
7895 directly. This can happen if the RTL gets split during final
7896 instruction generation. */
7897 after_arm_reorg = 1;
7899 /* Free the minipool memory. */
7900 obstack_free (&minipool_obstack, minipool_startobj);
7903 /* Routines to output assembly language. */
7905 /* If the rtx is the correct value then return the string of the number.
7906 In this way we can ensure that valid double constants are generated even
7907 when cross compiling. */
7909 fp_immediate_constant (rtx x)
7914 if (!fp_consts_inited)
7917 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7918 for (i = 0; i < 8; i++)
7919 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7920 return strings_fp[i];
7925 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7927 fp_const_from_val (REAL_VALUE_TYPE *r)
7931 if (!fp_consts_inited)
7934 for (i = 0; i < 8; i++)
7935 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7936 return strings_fp[i];
7941 /* Output the operands of a LDM/STM instruction to STREAM.
7942 MASK is the ARM register set mask of which only bits 0-15 are important.
7943 REG is the base register, either the frame pointer or the stack pointer,
7944 INSTR is the possibly suffixed load or store instruction. */
7947 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
7951 bool not_first = FALSE;
7953 fputc ('\t', stream);
7954 asm_fprintf (stream, instr, reg);
7955 fputs (", {", stream);
7957 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7958 if (mask & (1 << i))
7961 fprintf (stream, ", ");
7963 asm_fprintf (stream, "%r", i);
7967 fprintf (stream, "}\n");
7971 /* Output a FLDMX instruction to STREAM.
7972 BASE if the register containing the address.
7973 REG and COUNT specify the register range.
7974 Extra registers may be added to avoid hardware bugs. */
7977 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7981 /* Workaround ARM10 VFPr1 bug. */
7982 if (count == 2 && !arm_arch6)
7989 fputc ('\t', stream);
7990 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7992 for (i = reg; i < reg + count; i++)
7995 fputs (", ", stream);
7996 asm_fprintf (stream, "d%d", i);
7998 fputs ("}\n", stream);
8003 /* Output the assembly for a store multiple. */
8006 vfp_output_fstmx (rtx * operands)
8013 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8014 p = strlen (pattern);
8016 gcc_assert (GET_CODE (operands[1]) == REG);
8018 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8019 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8021 p += sprintf (&pattern[p], ", d%d", base + i);
8023 strcpy (&pattern[p], "}");
8025 output_asm_insn (pattern, operands);
8030 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8031 number of bytes pushed. */
8034 vfp_emit_fstmx (int base_reg, int count)
8041 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8042 register pairs are stored by a store multiple insn. We avoid this
8043 by pushing an extra pair. */
8044 if (count == 2 && !arm_arch6)
8046 if (base_reg == LAST_VFP_REGNUM - 3)
8051 /* ??? The frame layout is implementation defined. We describe
8052 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8053 We really need some way of representing the whole block so that the
8054 unwinder can figure it out at runtime. */
8055 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8056 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8058 reg = gen_rtx_REG (DFmode, base_reg);
8062 = gen_rtx_SET (VOIDmode,
8063 gen_rtx_MEM (BLKmode,
8064 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8065 gen_rtx_UNSPEC (BLKmode,
8069 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8070 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8071 GEN_INT (-(count * 8 + 4))));
8072 RTX_FRAME_RELATED_P (tmp) = 1;
8073 XVECEXP (dwarf, 0, 0) = tmp;
8075 tmp = gen_rtx_SET (VOIDmode,
8076 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8078 RTX_FRAME_RELATED_P (tmp) = 1;
8079 XVECEXP (dwarf, 0, 1) = tmp;
8081 for (i = 1; i < count; i++)
8083 reg = gen_rtx_REG (DFmode, base_reg);
8085 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8087 tmp = gen_rtx_SET (VOIDmode,
8088 gen_rtx_MEM (DFmode,
8089 gen_rtx_PLUS (SImode,
8093 RTX_FRAME_RELATED_P (tmp) = 1;
8094 XVECEXP (dwarf, 0, i + 1) = tmp;
8097 par = emit_insn (par);
8098 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8100 RTX_FRAME_RELATED_P (par) = 1;
8102 return count * 8 + 4;
8106 /* Output a 'call' insn. */
8108 output_call (rtx *operands)
8110 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8112 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8113 if (REGNO (operands[0]) == LR_REGNUM)
8115 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8116 output_asm_insn ("mov%?\t%0, %|lr", operands);
8119 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8121 if (TARGET_INTERWORK || arm_arch4t)
8122 output_asm_insn ("bx%?\t%0", operands);
8124 output_asm_insn ("mov%?\t%|pc, %0", operands);
8129 /* Output a 'call' insn that is a reference in memory. */
8131 output_call_mem (rtx *operands)
8133 if (TARGET_INTERWORK && !arm_arch5)
8135 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8136 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8137 output_asm_insn ("bx%?\t%|ip", operands);
8139 else if (regno_use_in (LR_REGNUM, operands[0]))
8141 /* LR is used in the memory address. We load the address in the
8142 first instruction. It's safe to use IP as the target of the
8143 load since the call will kill it anyway. */
8144 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8146 output_asm_insn ("blx%?\t%|ip", operands);
8149 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8151 output_asm_insn ("bx%?\t%|ip", operands);
8153 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8158 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8159 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8166 /* Output a move from arm registers to an fpa registers.
8167 OPERANDS[0] is an fpa register.
8168 OPERANDS[1] is the first registers of an arm register pair. */
8170 output_mov_long_double_fpa_from_arm (rtx *operands)
8172 int arm_reg0 = REGNO (operands[1]);
8175 gcc_assert (arm_reg0 != IP_REGNUM);
8177 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8178 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8179 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8181 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8182 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8187 /* Output a move from an fpa register to arm registers.
8188 OPERANDS[0] is the first registers of an arm register pair.
8189 OPERANDS[1] is an fpa register. */
8191 output_mov_long_double_arm_from_fpa (rtx *operands)
8193 int arm_reg0 = REGNO (operands[0]);
8196 gcc_assert (arm_reg0 != IP_REGNUM);
8198 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8199 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8200 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8202 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8203 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8207 /* Output a move from arm registers to arm registers of a long double
8208 OPERANDS[0] is the destination.
8209 OPERANDS[1] is the source. */
8211 output_mov_long_double_arm_from_arm (rtx *operands)
8213 /* We have to be careful here because the two might overlap. */
8214 int dest_start = REGNO (operands[0]);
8215 int src_start = REGNO (operands[1]);
8219 if (dest_start < src_start)
8221 for (i = 0; i < 3; i++)
8223 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8224 ops[1] = gen_rtx_REG (SImode, src_start + i);
8225 output_asm_insn ("mov%?\t%0, %1", ops);
8230 for (i = 2; i >= 0; i--)
8232 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8233 ops[1] = gen_rtx_REG (SImode, src_start + i);
8234 output_asm_insn ("mov%?\t%0, %1", ops);
8242 /* Output a move from arm registers to an fpa registers.
8243 OPERANDS[0] is an fpa register.
8244 OPERANDS[1] is the first registers of an arm register pair. */
8246 output_mov_double_fpa_from_arm (rtx *operands)
8248 int arm_reg0 = REGNO (operands[1]);
8251 gcc_assert (arm_reg0 != IP_REGNUM);
8253 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8254 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8255 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8256 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8260 /* Output a move from an fpa register to arm registers.
8261 OPERANDS[0] is the first registers of an arm register pair.
8262 OPERANDS[1] is an fpa register. */
8264 output_mov_double_arm_from_fpa (rtx *operands)
8266 int arm_reg0 = REGNO (operands[0]);
8269 gcc_assert (arm_reg0 != IP_REGNUM);
8271 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8272 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8273 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8274 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8278 /* Output a move between double words.
8279 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8280 or MEM<-REG and all MEMs must be offsettable addresses. */
8282 output_move_double (rtx *operands)
8284 enum rtx_code code0 = GET_CODE (operands[0]);
8285 enum rtx_code code1 = GET_CODE (operands[1]);
8290 int reg0 = REGNO (operands[0]);
8292 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8294 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
8296 switch (GET_CODE (XEXP (operands[1], 0)))
8299 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8303 gcc_assert (TARGET_LDRD);
8304 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8308 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8312 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8316 gcc_assert (TARGET_LDRD);
8317 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8322 otherops[0] = operands[0];
8323 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8324 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8326 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8328 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8330 /* Registers overlap so split out the increment. */
8331 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8332 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8335 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8339 /* We only allow constant increments, so this is safe. */
8340 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8346 output_asm_insn ("adr%?\t%0, %1", operands);
8347 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8351 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8352 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8354 otherops[0] = operands[0];
8355 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8356 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8358 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8360 if (GET_CODE (otherops[2]) == CONST_INT)
8362 switch ((int) INTVAL (otherops[2]))
8365 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8368 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8371 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8376 && (GET_CODE (otherops[2]) == REG
8377 || (GET_CODE (otherops[2]) == CONST_INT
8378 && INTVAL (otherops[2]) > -256
8379 && INTVAL (otherops[2]) < 256)))
8381 if (reg_overlap_mentioned_p (otherops[0],
8384 /* Swap base and index registers over to
8385 avoid a conflict. */
8386 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8387 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8390 /* If both registers conflict, it will usually
8391 have been fixed by a splitter. */
8392 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8394 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8395 output_asm_insn ("ldr%?d\t%0, [%1]",
8399 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
8403 if (GET_CODE (otherops[2]) == CONST_INT)
8405 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8406 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8408 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8411 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8414 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8416 return "ldm%?ia\t%0, %M0";
8420 otherops[1] = adjust_address (operands[1], SImode, 4);
8421 /* Take care of overlapping base/data reg. */
8422 if (reg_mentioned_p (operands[0], operands[1]))
8424 output_asm_insn ("ldr%?\t%0, %1", otherops);
8425 output_asm_insn ("ldr%?\t%0, %1", operands);
8429 output_asm_insn ("ldr%?\t%0, %1", operands);
8430 output_asm_insn ("ldr%?\t%0, %1", otherops);
8437 /* Constraints should ensure this. */
8438 gcc_assert (code0 == MEM && code1 == REG);
8439 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
8441 switch (GET_CODE (XEXP (operands[0], 0)))
8444 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8448 gcc_assert (TARGET_LDRD);
8449 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8453 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8457 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8461 gcc_assert (TARGET_LDRD);
8462 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8467 otherops[0] = operands[1];
8468 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8469 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8471 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8472 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8474 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8478 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8479 if (GET_CODE (otherops[2]) == CONST_INT)
8481 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8484 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8488 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8492 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8497 && (GET_CODE (otherops[2]) == REG
8498 || (GET_CODE (otherops[2]) == CONST_INT
8499 && INTVAL (otherops[2]) > -256
8500 && INTVAL (otherops[2]) < 256)))
8502 otherops[0] = operands[1];
8503 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8504 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8510 otherops[0] = adjust_address (operands[0], SImode, 4);
8511 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8512 output_asm_insn ("str%?\t%1, %0", operands);
8513 output_asm_insn ("str%?\t%1, %0", otherops);
8520 /* Output an ADD r, s, #n where n may be too big for one instruction.
8521 If adding zero to one register, output nothing. */
8523 output_add_immediate (rtx *operands)
8525 HOST_WIDE_INT n = INTVAL (operands[2]);
8527 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8530 output_multi_immediate (operands,
8531 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8534 output_multi_immediate (operands,
8535 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8542 /* Output a multiple immediate operation.
8543 OPERANDS is the vector of operands referred to in the output patterns.
8544 INSTR1 is the output pattern to use for the first constant.
8545 INSTR2 is the output pattern to use for subsequent constants.
8546 IMMED_OP is the index of the constant slot in OPERANDS.
8547 N is the constant value. */
8549 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8550 int immed_op, HOST_WIDE_INT n)
8552 #if HOST_BITS_PER_WIDE_INT > 32
8558 /* Quick and easy output. */
8559 operands[immed_op] = const0_rtx;
8560 output_asm_insn (instr1, operands);
8565 const char * instr = instr1;
8567 /* Note that n is never zero here (which would give no output). */
8568 for (i = 0; i < 32; i += 2)
8572 operands[immed_op] = GEN_INT (n & (255 << i));
8573 output_asm_insn (instr, operands);
8583 /* Return the appropriate ARM instruction for the operation code.
8584 The returned result should not be overwritten. OP is the rtx of the
8585 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8588 arithmetic_instr (rtx op, int shift_first_arg)
8590 switch (GET_CODE (op))
8596 return shift_first_arg ? "rsb" : "sub";
8612 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8613 for the operation code. The returned result should not be overwritten.
8614 OP is the rtx code of the shift.
8615 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8618 shift_op (rtx op, HOST_WIDE_INT *amountp)
8621 enum rtx_code code = GET_CODE (op);
8623 switch (GET_CODE (XEXP (op, 1)))
8631 *amountp = INTVAL (XEXP (op, 1));
8653 gcc_assert (*amountp != -1);
8654 *amountp = 32 - *amountp;
8663 /* We never have to worry about the amount being other than a
8664 power of 2, since this case can never be reloaded from a reg. */
8665 gcc_assert (*amountp != -1);
8666 *amountp = int_log2 (*amountp);
8675 /* This is not 100% correct, but follows from the desire to merge
8676 multiplication by a power of 2 with the recognizer for a
8677 shift. >=32 is not a valid shift for "asl", so we must try and
8678 output a shift that produces the correct arithmetical result.
8679 Using lsr #32 is identical except for the fact that the carry bit
8680 is not set correctly if we set the flags; but we never use the
8681 carry bit from such an operation, so we can ignore that. */
8682 if (code == ROTATERT)
8683 /* Rotate is just modulo 32. */
8685 else if (*amountp != (*amountp & 31))
8692 /* Shifts of 0 are no-ops. */
8700 /* Obtain the shift from the POWER of two. */
8702 static HOST_WIDE_INT
8703 int_log2 (HOST_WIDE_INT power)
8705 HOST_WIDE_INT shift = 0;
8707 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8709 gcc_assert (shift <= 31);
8716 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8717 because /bin/as is horribly restrictive. The judgement about
8718 whether or not each character is 'printable' (and can be output as
8719 is) or not (and must be printed with an octal escape) must be made
8720 with reference to the *host* character set -- the situation is
8721 similar to that discussed in the comments above pp_c_char in
8722 c-pretty-print.c. */
8724 #define MAX_ASCII_LEN 51
8727 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8732 fputs ("\t.ascii\t\"", stream);
8734 for (i = 0; i < len; i++)
8738 if (len_so_far >= MAX_ASCII_LEN)
8740 fputs ("\"\n\t.ascii\t\"", stream);
8746 if (c == '\\' || c == '\"')
8748 putc ('\\', stream);
8756 fprintf (stream, "\\%03o", c);
8761 fputs ("\"\n", stream);
8764 /* Compute the register save mask for registers 0 through 12
8765 inclusive. This code is used by arm_compute_save_reg_mask. */
8767 static unsigned long
8768 arm_compute_save_reg0_reg12_mask (void)
8770 unsigned long func_type = arm_current_func_type ();
8771 unsigned long save_reg_mask = 0;
8774 if (IS_INTERRUPT (func_type))
8776 unsigned int max_reg;
8777 /* Interrupt functions must not corrupt any registers,
8778 even call clobbered ones. If this is a leaf function
8779 we can just examine the registers used by the RTL, but
8780 otherwise we have to assume that whatever function is
8781 called might clobber anything, and so we have to save
8782 all the call-clobbered registers as well. */
8783 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8784 /* FIQ handlers have registers r8 - r12 banked, so
8785 we only need to check r0 - r7, Normal ISRs only
8786 bank r14 and r15, so we must check up to r12.
8787 r13 is the stack pointer which is always preserved,
8788 so we do not need to consider it here. */
8793 for (reg = 0; reg <= max_reg; reg++)
8794 if (regs_ever_live[reg]
8795 || (! current_function_is_leaf && call_used_regs [reg]))
8796 save_reg_mask |= (1 << reg);
8798 /* Also save the pic base register if necessary. */
8800 && !TARGET_SINGLE_PIC_BASE
8801 && current_function_uses_pic_offset_table)
8802 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8806 /* In the normal case we only need to save those registers
8807 which are call saved and which are used by this function. */
8808 for (reg = 0; reg <= 10; reg++)
8809 if (regs_ever_live[reg] && ! call_used_regs [reg])
8810 save_reg_mask |= (1 << reg);
8812 /* Handle the frame pointer as a special case. */
8813 if (! TARGET_APCS_FRAME
8814 && ! frame_pointer_needed
8815 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8816 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8817 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8819 /* If we aren't loading the PIC register,
8820 don't stack it even though it may be live. */
8822 && !TARGET_SINGLE_PIC_BASE
8823 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
8824 || current_function_uses_pic_offset_table))
8825 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8828 /* Save registers so the exception handler can modify them. */
8829 if (current_function_calls_eh_return)
8835 reg = EH_RETURN_DATA_REGNO (i);
8836 if (reg == INVALID_REGNUM)
8838 save_reg_mask |= 1 << reg;
8842 return save_reg_mask;
8845 /* Compute a bit mask of which registers need to be
8846 saved on the stack for the current function. */
8848 static unsigned long
8849 arm_compute_save_reg_mask (void)
8851 unsigned int save_reg_mask = 0;
8852 unsigned long func_type = arm_current_func_type ();
8854 if (IS_NAKED (func_type))
8855 /* This should never really happen. */
8858 /* If we are creating a stack frame, then we must save the frame pointer,
8859 IP (which will hold the old stack pointer), LR and the PC. */
8860 if (frame_pointer_needed)
8862 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8867 /* Volatile functions do not return, so there
8868 is no need to save any other registers. */
8869 if (IS_VOLATILE (func_type))
8870 return save_reg_mask;
8872 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8874 /* Decide if we need to save the link register.
8875 Interrupt routines have their own banked link register,
8876 so they never need to save it.
8877 Otherwise if we do not use the link register we do not need to save
8878 it. If we are pushing other registers onto the stack however, we
8879 can save an instruction in the epilogue by pushing the link register
8880 now and then popping it back into the PC. This incurs extra memory
8881 accesses though, so we only do it when optimizing for size, and only
8882 if we know that we will not need a fancy return sequence. */
8883 if (regs_ever_live [LR_REGNUM]
8886 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8887 && !current_function_calls_eh_return))
8888 save_reg_mask |= 1 << LR_REGNUM;
8890 if (cfun->machine->lr_save_eliminated)
8891 save_reg_mask &= ~ (1 << LR_REGNUM);
8893 if (TARGET_REALLY_IWMMXT
8894 && ((bit_count (save_reg_mask)
8895 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8899 /* The total number of registers that are going to be pushed
8900 onto the stack is odd. We need to ensure that the stack
8901 is 64-bit aligned before we start to save iWMMXt registers,
8902 and also before we start to create locals. (A local variable
8903 might be a double or long long which we will load/store using
8904 an iWMMXt instruction). Therefore we need to push another
8905 ARM register, so that the stack will be 64-bit aligned. We
8906 try to avoid using the arg registers (r0 -r3) as they might be
8907 used to pass values in a tail call. */
8908 for (reg = 4; reg <= 12; reg++)
8909 if ((save_reg_mask & (1 << reg)) == 0)
8913 save_reg_mask |= (1 << reg);
8916 cfun->machine->sibcall_blocked = 1;
8917 save_reg_mask |= (1 << 3);
8921 return save_reg_mask;
8925 /* Compute a bit mask of which registers need to be
8926 saved on the stack for the current function. */
8927 static unsigned long
8928 thumb_compute_save_reg_mask (void)
8934 for (reg = 0; reg < 12; reg ++)
8935 if (regs_ever_live[reg] && !call_used_regs[reg])
8939 && !TARGET_SINGLE_PIC_BASE
8940 && current_function_uses_pic_offset_table)
8941 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8943 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8944 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
8945 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
8947 /* LR will also be pushed if any lo regs are pushed. */
8948 if (mask & 0xff || thumb_force_lr_save ())
8949 mask |= (1 << LR_REGNUM);
8951 /* Make sure we have a low work register if we need one.
8952 We will need one if we are going to push a high register,
8953 but we are not currently intending to push a low register. */
8954 if ((mask & 0xff) == 0
8955 && ((mask & 0x0f00) || TARGET_BACKTRACE))
8957 /* Use thumb_find_work_register to choose which register
8958 we will use. If the register is live then we will
8959 have to push it. Use LAST_LO_REGNUM as our fallback
8960 choice for the register to select. */
8961 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
8963 if (! call_used_regs[reg])
8971 /* Return the number of bytes required to save VFP registers. */
8973 arm_get_vfp_saved_size (void)
8980 /* Space for saved VFP registers. */
8981 if (TARGET_HARD_FLOAT && TARGET_VFP)
8984 for (regno = FIRST_VFP_REGNUM;
8985 regno < LAST_VFP_REGNUM;
8988 if ((!regs_ever_live[regno] || call_used_regs[regno])
8989 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8993 /* Workaround ARM10 VFPr1 bug. */
8994 if (count == 2 && !arm_arch6)
8996 saved += count * 8 + 4;
9005 if (count == 2 && !arm_arch6)
9007 saved += count * 8 + 4;
9014 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9015 everything bar the final return instruction. */
9017 output_return_instruction (rtx operand, int really_return, int reverse)
9019 char conditional[10];
9022 unsigned long live_regs_mask;
9023 unsigned long func_type;
9024 arm_stack_offsets *offsets;
9026 func_type = arm_current_func_type ();
9028 if (IS_NAKED (func_type))
9031 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9033 /* If this function was declared non-returning, and we have
9034 found a tail call, then we have to trust that the called
9035 function won't return. */
9040 /* Otherwise, trap an attempted return by aborting. */
9042 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9044 assemble_external_libcall (ops[1]);
9045 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9051 gcc_assert (!current_function_calls_alloca || really_return);
9053 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9055 return_used_this_function = 1;
9057 live_regs_mask = arm_compute_save_reg_mask ();
9061 const char * return_reg;
9063 /* If we do not have any special requirements for function exit
9064 (e.g. interworking, or ISR) then we can load the return address
9065 directly into the PC. Otherwise we must load it into LR. */
9067 && ! TARGET_INTERWORK)
9068 return_reg = reg_names[PC_REGNUM];
9070 return_reg = reg_names[LR_REGNUM];
9072 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9074 /* There are three possible reasons for the IP register
9075 being saved. 1) a stack frame was created, in which case
9076 IP contains the old stack pointer, or 2) an ISR routine
9077 corrupted it, or 3) it was saved to align the stack on
9078 iWMMXt. In case 1, restore IP into SP, otherwise just
9080 if (frame_pointer_needed)
9082 live_regs_mask &= ~ (1 << IP_REGNUM);
9083 live_regs_mask |= (1 << SP_REGNUM);
9086 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
9089 /* On some ARM architectures it is faster to use LDR rather than
9090 LDM to load a single register. On other architectures, the
9091 cost is the same. In 26 bit mode, or for exception handlers,
9092 we have to use LDM to load the PC so that the CPSR is also
9094 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9095 if (live_regs_mask == (1U << reg))
9098 if (reg <= LAST_ARM_REGNUM
9099 && (reg != LR_REGNUM
9101 || ! IS_INTERRUPT (func_type)))
9103 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9104 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9111 /* Generate the load multiple instruction to restore the
9112 registers. Note we can get here, even if
9113 frame_pointer_needed is true, but only if sp already
9114 points to the base of the saved core registers. */
9115 if (live_regs_mask & (1 << SP_REGNUM))
9117 unsigned HOST_WIDE_INT stack_adjust;
9119 offsets = arm_get_frame_offsets ();
9120 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9121 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
9123 if (stack_adjust && arm_arch5)
9124 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9127 /* If we can't use ldmib (SA110 bug),
9128 then try to pop r3 instead. */
9130 live_regs_mask |= 1 << 3;
9131 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9135 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9137 p = instr + strlen (instr);
9139 for (reg = 0; reg <= SP_REGNUM; reg++)
9140 if (live_regs_mask & (1 << reg))
9142 int l = strlen (reg_names[reg]);
9148 memcpy (p, ", ", 2);
9152 memcpy (p, "%|", 2);
9153 memcpy (p + 2, reg_names[reg], l);
9157 if (live_regs_mask & (1 << LR_REGNUM))
9159 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9160 /* If returning from an interrupt, restore the CPSR. */
9161 if (IS_INTERRUPT (func_type))
9168 output_asm_insn (instr, & operand);
9170 /* See if we need to generate an extra instruction to
9171 perform the actual function return. */
9173 && func_type != ARM_FT_INTERWORKED
9174 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9176 /* The return has already been handled
9177 by loading the LR into the PC. */
9184 switch ((int) ARM_FUNC_TYPE (func_type))
9188 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9191 case ARM_FT_INTERWORKED:
9192 sprintf (instr, "bx%s\t%%|lr", conditional);
9195 case ARM_FT_EXCEPTION:
9196 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9200 /* Use bx if it's available. */
9201 if (arm_arch5 || arm_arch4t)
9202 sprintf (instr, "bx%s\t%%|lr", conditional);
9204 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9208 output_asm_insn (instr, & operand);
9214 /* Write the function name into the code section, directly preceding
9215 the function prologue.
9217 Code will be output similar to this:
9219 .ascii "arm_poke_function_name", 0
9222 .word 0xff000000 + (t1 - t0)
9223 arm_poke_function_name
9225 stmfd sp!, {fp, ip, lr, pc}
9228 When performing a stack backtrace, code can inspect the value
9229 of 'pc' stored at 'fp' + 0. If the trace function then looks
9230 at location pc - 12 and the top 8 bits are set, then we know
9231 that there is a function name embedded immediately preceding this
9232 location and has length ((pc[-3]) & 0xff000000).
9234 We assume that pc is declared as a pointer to an unsigned long.
9236 It is of no benefit to output the function name if we are assembling
9237 a leaf function. These function types will not contain a stack
9238 backtrace structure, therefore it is not possible to determine the
9241 arm_poke_function_name (FILE *stream, const char *name)
9243 unsigned long alignlength;
9244 unsigned long length;
9247 length = strlen (name) + 1;
9248 alignlength = ROUND_UP_WORD (length);
9250 ASM_OUTPUT_ASCII (stream, name, length);
9251 ASM_OUTPUT_ALIGN (stream, 2);
9252 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9253 assemble_aligned_integer (UNITS_PER_WORD, x);
9256 /* Place some comments into the assembler stream
9257 describing the current function. */
9259 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9261 unsigned long func_type;
9265 thumb_output_function_prologue (f, frame_size);
9270 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9272 func_type = arm_current_func_type ();
9274 switch ((int) ARM_FUNC_TYPE (func_type))
9279 case ARM_FT_INTERWORKED:
9280 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9283 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9286 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9288 case ARM_FT_EXCEPTION:
9289 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9293 if (IS_NAKED (func_type))
9294 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9296 if (IS_VOLATILE (func_type))
9297 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9299 if (IS_NESTED (func_type))
9300 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9302 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9303 current_function_args_size,
9304 current_function_pretend_args_size, frame_size);
9306 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9307 frame_pointer_needed,
9308 cfun->machine->uses_anonymous_args);
9310 if (cfun->machine->lr_save_eliminated)
9311 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9313 if (current_function_calls_eh_return)
9314 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9316 #ifdef AOF_ASSEMBLER
9318 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9321 return_used_this_function = 0;
9325 arm_output_epilogue (rtx sibling)
9328 unsigned long saved_regs_mask;
9329 unsigned long func_type;
9330 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9331 frame that is $fp + 4 for a non-variadic function. */
9332 int floats_offset = 0;
9334 FILE * f = asm_out_file;
9335 unsigned int lrm_count = 0;
9336 int really_return = (sibling == NULL);
9338 arm_stack_offsets *offsets;
9340 /* If we have already generated the return instruction
9341 then it is futile to generate anything else. */
9342 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9345 func_type = arm_current_func_type ();
9347 if (IS_NAKED (func_type))
9348 /* Naked functions don't have epilogues. */
9351 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9355 /* A volatile function should never return. Call abort. */
9356 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9357 assemble_external_libcall (op);
9358 output_asm_insn ("bl\t%a0", &op);
9363 /* If we are throwing an exception, then we really must be doing a
9364 return, so we can't tail-call. */
9365 gcc_assert (!current_function_calls_eh_return || really_return);
9367 offsets = arm_get_frame_offsets ();
9368 saved_regs_mask = arm_compute_save_reg_mask ();
9371 lrm_count = bit_count (saved_regs_mask);
9373 floats_offset = offsets->saved_args;
9374 /* Compute how far away the floats will be. */
9375 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9376 if (saved_regs_mask & (1 << reg))
9379 if (frame_pointer_needed)
9381 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9382 int vfp_offset = offsets->frame;
9384 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9386 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9387 if (regs_ever_live[reg] && !call_used_regs[reg])
9389 floats_offset += 12;
9390 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9391 reg, FP_REGNUM, floats_offset - vfp_offset);
9396 start_reg = LAST_FPA_REGNUM;
9398 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9400 if (regs_ever_live[reg] && !call_used_regs[reg])
9402 floats_offset += 12;
9404 /* We can't unstack more than four registers at once. */
9405 if (start_reg - reg == 3)
9407 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9408 reg, FP_REGNUM, floats_offset - vfp_offset);
9409 start_reg = reg - 1;
9414 if (reg != start_reg)
9415 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9416 reg + 1, start_reg - reg,
9417 FP_REGNUM, floats_offset - vfp_offset);
9418 start_reg = reg - 1;
9422 /* Just in case the last register checked also needs unstacking. */
9423 if (reg != start_reg)
9424 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9425 reg + 1, start_reg - reg,
9426 FP_REGNUM, floats_offset - vfp_offset);
9429 if (TARGET_HARD_FLOAT && TARGET_VFP)
9433 /* The fldmx insn does not have base+offset addressing modes,
9434 so we use IP to hold the address. */
9435 saved_size = arm_get_vfp_saved_size ();
9439 floats_offset += saved_size;
9440 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9441 FP_REGNUM, floats_offset - vfp_offset);
9443 start_reg = FIRST_VFP_REGNUM;
9444 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9446 if ((!regs_ever_live[reg] || call_used_regs[reg])
9447 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9449 if (start_reg != reg)
9450 arm_output_fldmx (f, IP_REGNUM,
9451 (start_reg - FIRST_VFP_REGNUM) / 2,
9452 (reg - start_reg) / 2);
9453 start_reg = reg + 2;
9456 if (start_reg != reg)
9457 arm_output_fldmx (f, IP_REGNUM,
9458 (start_reg - FIRST_VFP_REGNUM) / 2,
9459 (reg - start_reg) / 2);
9464 /* The frame pointer is guaranteed to be non-double-word aligned.
9465 This is because it is set to (old_stack_pointer - 4) and the
9466 old_stack_pointer was double word aligned. Thus the offset to
9467 the iWMMXt registers to be loaded must also be non-double-word
9468 sized, so that the resultant address *is* double-word aligned.
9469 We can ignore floats_offset since that was already included in
9470 the live_regs_mask. */
9471 lrm_count += (lrm_count % 2 ? 2 : 1);
9473 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9474 if (regs_ever_live[reg] && !call_used_regs[reg])
9476 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9477 reg, FP_REGNUM, lrm_count * 4);
9482 /* saved_regs_mask should contain the IP, which at the time of stack
9483 frame generation actually contains the old stack pointer. So a
9484 quick way to unwind the stack is just pop the IP register directly
9485 into the stack pointer. */
9486 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
9487 saved_regs_mask &= ~ (1 << IP_REGNUM);
9488 saved_regs_mask |= (1 << SP_REGNUM);
9490 /* There are two registers left in saved_regs_mask - LR and PC. We
9491 only need to restore the LR register (the return address), but to
9492 save time we can load it directly into the PC, unless we need a
9493 special function exit sequence, or we are not really returning. */
9495 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9496 && !current_function_calls_eh_return)
9497 /* Delete the LR from the register mask, so that the LR on
9498 the stack is loaded into the PC in the register mask. */
9499 saved_regs_mask &= ~ (1 << LR_REGNUM);
9501 saved_regs_mask &= ~ (1 << PC_REGNUM);
9503 /* We must use SP as the base register, because SP is one of the
9504 registers being restored. If an interrupt or page fault
9505 happens in the ldm instruction, the SP might or might not
9506 have been restored. That would be bad, as then SP will no
9507 longer indicate the safe area of stack, and we can get stack
9508 corruption. Using SP as the base register means that it will
9509 be reset correctly to the original value, should an interrupt
9510 occur. If the stack pointer already points at the right
9511 place, then omit the subtraction. */
9512 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9513 || current_function_calls_alloca)
9514 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9515 4 * bit_count (saved_regs_mask));
9516 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9518 if (IS_INTERRUPT (func_type))
9519 /* Interrupt handlers will have pushed the
9520 IP onto the stack, so restore it now. */
9521 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9525 /* Restore stack pointer if necessary. */
9526 if (offsets->outgoing_args != offsets->saved_regs)
9528 operands[0] = operands[1] = stack_pointer_rtx;
9529 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9530 output_add_immediate (operands);
9533 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9535 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9536 if (regs_ever_live[reg] && !call_used_regs[reg])
9537 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9542 start_reg = FIRST_FPA_REGNUM;
9544 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9546 if (regs_ever_live[reg] && !call_used_regs[reg])
9548 if (reg - start_reg == 3)
9550 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9551 start_reg, SP_REGNUM);
9552 start_reg = reg + 1;
9557 if (reg != start_reg)
9558 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9559 start_reg, reg - start_reg,
9562 start_reg = reg + 1;
9566 /* Just in case the last register checked also needs unstacking. */
9567 if (reg != start_reg)
9568 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9569 start_reg, reg - start_reg, SP_REGNUM);
9572 if (TARGET_HARD_FLOAT && TARGET_VFP)
9574 start_reg = FIRST_VFP_REGNUM;
9575 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9577 if ((!regs_ever_live[reg] || call_used_regs[reg])
9578 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9580 if (start_reg != reg)
9581 arm_output_fldmx (f, SP_REGNUM,
9582 (start_reg - FIRST_VFP_REGNUM) / 2,
9583 (reg - start_reg) / 2);
9584 start_reg = reg + 2;
9587 if (start_reg != reg)
9588 arm_output_fldmx (f, SP_REGNUM,
9589 (start_reg - FIRST_VFP_REGNUM) / 2,
9590 (reg - start_reg) / 2);
9593 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9594 if (regs_ever_live[reg] && !call_used_regs[reg])
9595 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9597 /* If we can, restore the LR into the PC. */
9598 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9600 && current_function_pretend_args_size == 0
9601 && saved_regs_mask & (1 << LR_REGNUM)
9602 && !current_function_calls_eh_return)
9604 saved_regs_mask &= ~ (1 << LR_REGNUM);
9605 saved_regs_mask |= (1 << PC_REGNUM);
9608 /* Load the registers off the stack. If we only have one register
9609 to load use the LDR instruction - it is faster. */
9610 if (saved_regs_mask == (1 << LR_REGNUM))
9612 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9614 else if (saved_regs_mask)
9616 if (saved_regs_mask & (1 << SP_REGNUM))
9617 /* Note - write back to the stack register is not enabled
9618 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9619 in the list of registers and if we add writeback the
9620 instruction becomes UNPREDICTABLE. */
9621 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9623 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9626 if (current_function_pretend_args_size)
9628 /* Unwind the pre-pushed regs. */
9629 operands[0] = operands[1] = stack_pointer_rtx;
9630 operands[2] = GEN_INT (current_function_pretend_args_size);
9631 output_add_immediate (operands);
9635 /* We may have already restored PC directly from the stack. */
9636 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9639 /* Stack adjustment for exception handler. */
9640 if (current_function_calls_eh_return)
9641 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9642 ARM_EH_STACKADJ_REGNUM);
9644 /* Generate the return instruction. */
9645 switch ((int) ARM_FUNC_TYPE (func_type))
9649 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9652 case ARM_FT_EXCEPTION:
9653 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9656 case ARM_FT_INTERWORKED:
9657 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9661 if (arm_arch5 || arm_arch4t)
9662 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9664 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9672 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9673 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9675 arm_stack_offsets *offsets;
9681 /* Emit any call-via-reg trampolines that are needed for v4t support
9682 of call_reg and call_value_reg type insns. */
9683 for (regno = 0; regno < LR_REGNUM; regno++)
9685 rtx label = cfun->machine->call_via[regno];
9689 function_section (current_function_decl);
9690 targetm.asm_out.internal_label (asm_out_file, "L",
9691 CODE_LABEL_NUMBER (label));
9692 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
9696 /* ??? Probably not safe to set this here, since it assumes that a
9697 function will be emitted as assembly immediately after we generate
9698 RTL for it. This does not happen for inline functions. */
9699 return_used_this_function = 0;
9703 /* We need to take into account any stack-frame rounding. */
9704 offsets = arm_get_frame_offsets ();
9706 gcc_assert (!use_return_insn (FALSE, NULL)
9707 || !return_used_this_function
9708 || offsets->saved_regs == offsets->outgoing_args
9709 || frame_pointer_needed);
9711 /* Reset the ARM-specific per-function variables. */
9712 after_arm_reorg = 0;
9716 /* Generate and emit an insn that we will recognize as a push_multi.
9717 Unfortunately, since this insn does not reflect very well the actual
9718 semantics of the operation, we need to annotate the insn for the benefit
9719 of DWARF2 frame unwind information. */
9721 emit_multi_reg_push (unsigned long mask)
9728 int dwarf_par_index;
9731 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9732 if (mask & (1 << i))
9735 gcc_assert (num_regs && num_regs <= 16);
9737 /* We don't record the PC in the dwarf frame information. */
9738 num_dwarf_regs = num_regs;
9739 if (mask & (1 << PC_REGNUM))
9742 /* For the body of the insn we are going to generate an UNSPEC in
9743 parallel with several USEs. This allows the insn to be recognized
9744 by the push_multi pattern in the arm.md file. The insn looks
9745 something like this:
9748 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9749 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9750 (use (reg:SI 11 fp))
9751 (use (reg:SI 12 ip))
9752 (use (reg:SI 14 lr))
9753 (use (reg:SI 15 pc))
9756 For the frame note however, we try to be more explicit and actually
9757 show each register being stored into the stack frame, plus a (single)
9758 decrement of the stack pointer. We do it this way in order to be
9759 friendly to the stack unwinding code, which only wants to see a single
9760 stack decrement per instruction. The RTL we generate for the note looks
9761 something like this:
9764 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9765 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9766 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9767 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9768 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9771 This sequence is used both by the code to support stack unwinding for
9772 exceptions handlers and the code to generate dwarf2 frame debugging. */
9774 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9775 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9776 dwarf_par_index = 1;
9778 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9780 if (mask & (1 << i))
9782 reg = gen_rtx_REG (SImode, i);
9785 = gen_rtx_SET (VOIDmode,
9786 gen_rtx_MEM (BLKmode,
9787 gen_rtx_PRE_DEC (BLKmode,
9788 stack_pointer_rtx)),
9789 gen_rtx_UNSPEC (BLKmode,
9795 tmp = gen_rtx_SET (VOIDmode,
9796 gen_rtx_MEM (SImode, stack_pointer_rtx),
9798 RTX_FRAME_RELATED_P (tmp) = 1;
9799 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9807 for (j = 1, i++; j < num_regs; i++)
9809 if (mask & (1 << i))
9811 reg = gen_rtx_REG (SImode, i);
9813 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9817 tmp = gen_rtx_SET (VOIDmode,
9818 gen_rtx_MEM (SImode,
9819 plus_constant (stack_pointer_rtx,
9822 RTX_FRAME_RELATED_P (tmp) = 1;
9823 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9830 par = emit_insn (par);
9832 tmp = gen_rtx_SET (SImode,
9834 gen_rtx_PLUS (SImode,
9836 GEN_INT (-4 * num_regs)));
9837 RTX_FRAME_RELATED_P (tmp) = 1;
9838 XVECEXP (dwarf, 0, 0) = tmp;
9840 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9845 /* Calculate the size of the return value that is passed in registers. */
9847 arm_size_return_regs (void)
9849 enum machine_mode mode;
9851 if (current_function_return_rtx != 0)
9852 mode = GET_MODE (current_function_return_rtx);
9854 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9856 return GET_MODE_SIZE (mode);
9860 emit_sfm (int base_reg, int count)
9867 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9868 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9870 reg = gen_rtx_REG (XFmode, base_reg++);
9873 = gen_rtx_SET (VOIDmode,
9874 gen_rtx_MEM (BLKmode,
9875 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9876 gen_rtx_UNSPEC (BLKmode,
9879 tmp = gen_rtx_SET (VOIDmode,
9880 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
9881 RTX_FRAME_RELATED_P (tmp) = 1;
9882 XVECEXP (dwarf, 0, 1) = tmp;
9884 for (i = 1; i < count; i++)
9886 reg = gen_rtx_REG (XFmode, base_reg++);
9887 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9889 tmp = gen_rtx_SET (VOIDmode,
9890 gen_rtx_MEM (XFmode,
9891 plus_constant (stack_pointer_rtx,
9894 RTX_FRAME_RELATED_P (tmp) = 1;
9895 XVECEXP (dwarf, 0, i + 1) = tmp;
9898 tmp = gen_rtx_SET (VOIDmode,
9900 gen_rtx_PLUS (SImode,
9902 GEN_INT (-12 * count)));
9903 RTX_FRAME_RELATED_P (tmp) = 1;
9904 XVECEXP (dwarf, 0, 0) = tmp;
9906 par = emit_insn (par);
9907 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9913 /* Return true if the current function needs to save/restore LR. */
9916 thumb_force_lr_save (void)
9918 return !cfun->machine->lr_save_eliminated
9919 && (!leaf_function_p ()
9920 || thumb_far_jump_used_p ()
9921 || regs_ever_live [LR_REGNUM]);
9925 /* Compute the distance from register FROM to register TO.
9926 These can be the arg pointer (26), the soft frame pointer (25),
9927 the stack pointer (13) or the hard frame pointer (11).
9928 In thumb mode r7 is used as the soft frame pointer, if needed.
9929 Typical stack layout looks like this:
9931 old stack pointer -> | |
9934 | | saved arguments for
9935 | | vararg functions
9938 hard FP & arg pointer -> | | \
9946 soft frame pointer -> | | /
9956 current stack pointer -> | | /
9959 For a given function some or all of these stack components
9960 may not be needed, giving rise to the possibility of
9961 eliminating some of the registers.
9963 The values returned by this function must reflect the behavior
9964 of arm_expand_prologue() and arm_compute_save_reg_mask().
9966 The sign of the number returned reflects the direction of stack
9967 growth, so the values are positive for all eliminations except
9968 from the soft frame pointer to the hard frame pointer.
9970 SFP may point just inside the local variables block to ensure correct
9974 /* Calculate stack offsets. These are used to calculate register elimination
9975 offsets and in prologue/epilogue code. */
9977 static arm_stack_offsets *
9978 arm_get_frame_offsets (void)
9980 struct arm_stack_offsets *offsets;
9981 unsigned long func_type;
9984 HOST_WIDE_INT frame_size;
9986 offsets = &cfun->machine->stack_offsets;
9988 /* We need to know if we are a leaf function. Unfortunately, it
9989 is possible to be called after start_sequence has been called,
9990 which causes get_insns to return the insns for the sequence,
9991 not the function, which will cause leaf_function_p to return
9992 the incorrect result.
9994 to know about leaf functions once reload has completed, and the
9995 frame size cannot be changed after that time, so we can safely
9996 use the cached value. */
9998 if (reload_completed)
10001 /* Initially this is the size of the local variables. It will translated
10002 into an offset once we have determined the size of preceding data. */
10003 frame_size = ROUND_UP_WORD (get_frame_size ());
10005 leaf = leaf_function_p ();
10007 /* Space for variadic functions. */
10008 offsets->saved_args = current_function_pretend_args_size;
10010 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10014 unsigned int regno;
10016 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10018 /* We know that SP will be doubleword aligned on entry, and we must
10019 preserve that condition at any subroutine call. We also require the
10020 soft frame pointer to be doubleword aligned. */
10022 if (TARGET_REALLY_IWMMXT)
10024 /* Check for the call-saved iWMMXt registers. */
10025 for (regno = FIRST_IWMMXT_REGNUM;
10026 regno <= LAST_IWMMXT_REGNUM;
10028 if (regs_ever_live [regno] && ! call_used_regs [regno])
10032 func_type = arm_current_func_type ();
10033 if (! IS_VOLATILE (func_type))
10035 /* Space for saved FPA registers. */
10036 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10037 if (regs_ever_live[regno] && ! call_used_regs[regno])
10040 /* Space for saved VFP registers. */
10041 if (TARGET_HARD_FLOAT && TARGET_VFP)
10042 saved += arm_get_vfp_saved_size ();
10045 else /* TARGET_THUMB */
10047 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10048 if (TARGET_BACKTRACE)
10052 /* Saved registers include the stack frame. */
10053 offsets->saved_regs = offsets->saved_args + saved;
10054 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
10055 /* A leaf function does not need any stack alignment if it has nothing
10057 if (leaf && frame_size == 0)
10059 offsets->outgoing_args = offsets->soft_frame;
10063 /* Ensure SFP has the correct alignment. */
10064 if (ARM_DOUBLEWORD_ALIGN
10065 && (offsets->soft_frame & 7))
10066 offsets->soft_frame += 4;
10068 offsets->outgoing_args = offsets->soft_frame + frame_size
10069 + current_function_outgoing_args_size;
10071 if (ARM_DOUBLEWORD_ALIGN)
10073 /* Ensure SP remains doubleword aligned. */
10074 if (offsets->outgoing_args & 7)
10075 offsets->outgoing_args += 4;
10076 gcc_assert (!(offsets->outgoing_args & 7));
10083 /* Calculate the relative offsets for the different stack pointers. Positive
10084 offsets are in the direction of stack growth. */
10087 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10089 arm_stack_offsets *offsets;
10091 offsets = arm_get_frame_offsets ();
10093 /* OK, now we have enough information to compute the distances.
10094 There must be an entry in these switch tables for each pair
10095 of registers in ELIMINABLE_REGS, even if some of the entries
10096 seem to be redundant or useless. */
10099 case ARG_POINTER_REGNUM:
10102 case THUMB_HARD_FRAME_POINTER_REGNUM:
10105 case FRAME_POINTER_REGNUM:
10106 /* This is the reverse of the soft frame pointer
10107 to hard frame pointer elimination below. */
10108 return offsets->soft_frame - offsets->saved_args;
10110 case ARM_HARD_FRAME_POINTER_REGNUM:
10111 /* If there is no stack frame then the hard
10112 frame pointer and the arg pointer coincide. */
10113 if (offsets->frame == offsets->saved_regs)
10115 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10116 return (frame_pointer_needed
10117 && cfun->static_chain_decl != NULL
10118 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10120 case STACK_POINTER_REGNUM:
10121 /* If nothing has been pushed on the stack at all
10122 then this will return -4. This *is* correct! */
10123 return offsets->outgoing_args - (offsets->saved_args + 4);
10126 gcc_unreachable ();
10128 gcc_unreachable ();
10130 case FRAME_POINTER_REGNUM:
10133 case THUMB_HARD_FRAME_POINTER_REGNUM:
10136 case ARM_HARD_FRAME_POINTER_REGNUM:
10137 /* The hard frame pointer points to the top entry in the
10138 stack frame. The soft frame pointer to the bottom entry
10139 in the stack frame. If there is no stack frame at all,
10140 then they are identical. */
10142 return offsets->frame - offsets->soft_frame;
10144 case STACK_POINTER_REGNUM:
10145 return offsets->outgoing_args - offsets->soft_frame;
10148 gcc_unreachable ();
10150 gcc_unreachable ();
10153 /* You cannot eliminate from the stack pointer.
10154 In theory you could eliminate from the hard frame
10155 pointer to the stack pointer, but this will never
10156 happen, since if a stack frame is not needed the
10157 hard frame pointer will never be used. */
10158 gcc_unreachable ();
10163 /* Generate the prologue instructions for entry into an ARM function. */
10165 arm_expand_prologue (void)
10171 unsigned long live_regs_mask;
10172 unsigned long func_type;
10174 int saved_pretend_args = 0;
10175 int saved_regs = 0;
10176 unsigned HOST_WIDE_INT args_to_push;
10177 arm_stack_offsets *offsets;
10179 func_type = arm_current_func_type ();
10181 /* Naked functions don't have prologues. */
10182 if (IS_NAKED (func_type))
10185 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10186 args_to_push = current_function_pretend_args_size;
10188 /* Compute which register we will have to save onto the stack. */
10189 live_regs_mask = arm_compute_save_reg_mask ();
10191 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10193 if (frame_pointer_needed)
10195 if (IS_INTERRUPT (func_type))
10197 /* Interrupt functions must not corrupt any registers.
10198 Creating a frame pointer however, corrupts the IP
10199 register, so we must push it first. */
10200 insn = emit_multi_reg_push (1 << IP_REGNUM);
10202 /* Do not set RTX_FRAME_RELATED_P on this insn.
10203 The dwarf stack unwinding code only wants to see one
10204 stack decrement per function, and this is not it. If
10205 this instruction is labeled as being part of the frame
10206 creation sequence then dwarf2out_frame_debug_expr will
10207 die when it encounters the assignment of IP to FP
10208 later on, since the use of SP here establishes SP as
10209 the CFA register and not IP.
10211 Anyway this instruction is not really part of the stack
10212 frame creation although it is part of the prologue. */
10214 else if (IS_NESTED (func_type))
10216 /* The Static chain register is the same as the IP register
10217 used as a scratch register during stack frame creation.
10218 To get around this need to find somewhere to store IP
10219 whilst the frame is being created. We try the following
10222 1. The last argument register.
10223 2. A slot on the stack above the frame. (This only
10224 works if the function is not a varargs function).
10225 3. Register r3, after pushing the argument registers
10228 Note - we only need to tell the dwarf2 backend about the SP
10229 adjustment in the second variant; the static chain register
10230 doesn't need to be unwound, as it doesn't contain a value
10231 inherited from the caller. */
10233 if (regs_ever_live[3] == 0)
10235 insn = gen_rtx_REG (SImode, 3);
10236 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10237 insn = emit_insn (insn);
10239 else if (args_to_push == 0)
10242 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10243 insn = gen_rtx_MEM (SImode, insn);
10244 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10245 insn = emit_insn (insn);
10249 /* Just tell the dwarf backend that we adjusted SP. */
10250 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10251 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10252 GEN_INT (-fp_offset)));
10253 RTX_FRAME_RELATED_P (insn) = 1;
10254 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10255 dwarf, REG_NOTES (insn));
10259 /* Store the args on the stack. */
10260 if (cfun->machine->uses_anonymous_args)
10261 insn = emit_multi_reg_push
10262 ((0xf0 >> (args_to_push / 4)) & 0xf);
10265 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10266 GEN_INT (- args_to_push)));
10268 RTX_FRAME_RELATED_P (insn) = 1;
10270 saved_pretend_args = 1;
10271 fp_offset = args_to_push;
10274 /* Now reuse r3 to preserve IP. */
10275 insn = gen_rtx_REG (SImode, 3);
10276 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10277 (void) emit_insn (insn);
10283 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10284 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10287 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10289 insn = emit_insn (insn);
10290 RTX_FRAME_RELATED_P (insn) = 1;
10295 /* Push the argument registers, or reserve space for them. */
10296 if (cfun->machine->uses_anonymous_args)
10297 insn = emit_multi_reg_push
10298 ((0xf0 >> (args_to_push / 4)) & 0xf);
10301 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10302 GEN_INT (- args_to_push)));
10303 RTX_FRAME_RELATED_P (insn) = 1;
10306 /* If this is an interrupt service routine, and the link register
10307 is going to be pushed, and we are not creating a stack frame,
10308 (which would involve an extra push of IP and a pop in the epilogue)
10309 subtracting four from LR now will mean that the function return
10310 can be done with a single instruction. */
10311 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10312 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10313 && ! frame_pointer_needed)
10314 emit_insn (gen_rtx_SET (SImode,
10315 gen_rtx_REG (SImode, LR_REGNUM),
10316 gen_rtx_PLUS (SImode,
10317 gen_rtx_REG (SImode, LR_REGNUM),
10320 if (live_regs_mask)
10322 insn = emit_multi_reg_push (live_regs_mask);
10323 saved_regs += bit_count (live_regs_mask) * 4;
10324 RTX_FRAME_RELATED_P (insn) = 1;
10328 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10329 if (regs_ever_live[reg] && ! call_used_regs [reg])
10331 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10332 insn = gen_rtx_MEM (V2SImode, insn);
10333 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10334 gen_rtx_REG (V2SImode, reg)));
10335 RTX_FRAME_RELATED_P (insn) = 1;
10339 if (! IS_VOLATILE (func_type))
10343 /* Save any floating point call-saved registers used by this
10345 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10347 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10348 if (regs_ever_live[reg] && !call_used_regs[reg])
10350 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10351 insn = gen_rtx_MEM (XFmode, insn);
10352 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10353 gen_rtx_REG (XFmode, reg)));
10354 RTX_FRAME_RELATED_P (insn) = 1;
10360 start_reg = LAST_FPA_REGNUM;
10362 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10364 if (regs_ever_live[reg] && !call_used_regs[reg])
10366 if (start_reg - reg == 3)
10368 insn = emit_sfm (reg, 4);
10369 RTX_FRAME_RELATED_P (insn) = 1;
10371 start_reg = reg - 1;
10376 if (start_reg != reg)
10378 insn = emit_sfm (reg + 1, start_reg - reg);
10379 RTX_FRAME_RELATED_P (insn) = 1;
10380 saved_regs += (start_reg - reg) * 12;
10382 start_reg = reg - 1;
10386 if (start_reg != reg)
10388 insn = emit_sfm (reg + 1, start_reg - reg);
10389 saved_regs += (start_reg - reg) * 12;
10390 RTX_FRAME_RELATED_P (insn) = 1;
10393 if (TARGET_HARD_FLOAT && TARGET_VFP)
10395 start_reg = FIRST_VFP_REGNUM;
10397 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10399 if ((!regs_ever_live[reg] || call_used_regs[reg])
10400 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10402 if (start_reg != reg)
10403 saved_regs += vfp_emit_fstmx (start_reg,
10404 (reg - start_reg) / 2);
10405 start_reg = reg + 2;
10408 if (start_reg != reg)
10409 saved_regs += vfp_emit_fstmx (start_reg,
10410 (reg - start_reg) / 2);
10414 if (frame_pointer_needed)
10416 /* Create the new frame pointer. */
10417 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10418 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10419 RTX_FRAME_RELATED_P (insn) = 1;
10421 if (IS_NESTED (func_type))
10423 /* Recover the static chain register. */
10424 if (regs_ever_live [3] == 0
10425 || saved_pretend_args)
10426 insn = gen_rtx_REG (SImode, 3);
10427 else /* if (current_function_pretend_args_size == 0) */
10429 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10431 insn = gen_rtx_MEM (SImode, insn);
10434 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10435 /* Add a USE to stop propagate_one_insn() from barfing. */
10436 emit_insn (gen_prologue_use (ip_rtx));
10440 offsets = arm_get_frame_offsets ();
10441 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10443 /* This add can produce multiple insns for a large constant, so we
10444 need to get tricky. */
10445 rtx last = get_last_insn ();
10447 amount = GEN_INT (offsets->saved_args + saved_regs
10448 - offsets->outgoing_args);
10450 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10454 last = last ? NEXT_INSN (last) : get_insns ();
10455 RTX_FRAME_RELATED_P (last) = 1;
10457 while (last != insn);
10459 /* If the frame pointer is needed, emit a special barrier that
10460 will prevent the scheduler from moving stores to the frame
10461 before the stack adjustment. */
10462 if (frame_pointer_needed)
10463 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10464 hard_frame_pointer_rtx));
10469 arm_load_pic_register (INVALID_REGNUM);
10471 /* If we are profiling, make sure no instructions are scheduled before
10472 the call to mcount. Similarly if the user has requested no
10473 scheduling in the prolog. */
10474 if (current_function_profile || !TARGET_SCHED_PROLOG)
10475 emit_insn (gen_blockage ());
10477 /* If the link register is being kept alive, with the return address in it,
10478 then make sure that it does not get reused by the ce2 pass. */
10479 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10481 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10482 cfun->machine->lr_save_eliminated = 1;
10486 /* If CODE is 'd', then the X is a condition operand and the instruction
10487 should only be executed if the condition is true.
10488 if CODE is 'D', then the X is a condition operand and the instruction
10489 should only be executed if the condition is false: however, if the mode
10490 of the comparison is CCFPEmode, then always execute the instruction -- we
10491 do this because in these circumstances !GE does not necessarily imply LT;
10492 in these cases the instruction pattern will take care to make sure that
10493 an instruction containing %d will follow, thereby undoing the effects of
10494 doing this instruction unconditionally.
10495 If CODE is 'N' then X is a floating point operand that must be negated
10497 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10498 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10500 arm_print_operand (FILE *stream, rtx x, int code)
10505 fputs (ASM_COMMENT_START, stream);
10509 fputs (user_label_prefix, stream);
10513 fputs (REGISTER_PREFIX, stream);
10517 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10521 output_operand_lossage ("predicated Thumb instruction");
10524 if (current_insn_predicate != NULL)
10526 output_operand_lossage
10527 ("predicated instruction in conditional sequence");
10531 fputs (arm_condition_codes[arm_current_cc], stream);
10533 else if (current_insn_predicate)
10535 enum arm_cond_code code;
10539 output_operand_lossage ("predicated Thumb instruction");
10543 code = get_arm_condition_code (current_insn_predicate);
10544 fputs (arm_condition_codes[code], stream);
10551 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10552 r = REAL_VALUE_NEGATE (r);
10553 fprintf (stream, "%s", fp_const_from_val (&r));
10558 if (GET_CODE (x) == CONST_INT)
10561 val = ARM_SIGN_EXTEND (~INTVAL (x));
10562 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10566 putc ('~', stream);
10567 output_addr_const (stream, x);
10572 fprintf (stream, "%s", arithmetic_instr (x, 1));
10575 /* Truncate Cirrus shift counts. */
10577 if (GET_CODE (x) == CONST_INT)
10579 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10582 arm_print_operand (stream, x, 0);
10586 fprintf (stream, "%s", arithmetic_instr (x, 0));
10592 const char * shift = shift_op (x, &val);
10596 fprintf (stream, ", %s ", shift_op (x, &val));
10598 arm_print_operand (stream, XEXP (x, 1), 0);
10600 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10605 /* An explanation of the 'Q', 'R' and 'H' register operands:
10607 In a pair of registers containing a DI or DF value the 'Q'
10608 operand returns the register number of the register containing
10609 the least significant part of the value. The 'R' operand returns
10610 the register number of the register containing the most
10611 significant part of the value.
10613 The 'H' operand returns the higher of the two register numbers.
10614 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10615 same as the 'Q' operand, since the most significant part of the
10616 value is held in the lower number register. The reverse is true
10617 on systems where WORDS_BIG_ENDIAN is false.
10619 The purpose of these operands is to distinguish between cases
10620 where the endian-ness of the values is important (for example
10621 when they are added together), and cases where the endian-ness
10622 is irrelevant, but the order of register operations is important.
10623 For example when loading a value from memory into a register
10624 pair, the endian-ness does not matter. Provided that the value
10625 from the lower memory address is put into the lower numbered
10626 register, and the value from the higher address is put into the
10627 higher numbered register, the load will work regardless of whether
10628 the value being loaded is big-wordian or little-wordian. The
10629 order of the two register loads can matter however, if the address
10630 of the memory location is actually held in one of the registers
10631 being overwritten by the load. */
10633 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10635 output_operand_lossage ("invalid operand for code '%c'", code);
10639 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10643 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10645 output_operand_lossage ("invalid operand for code '%c'", code);
10649 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10653 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10655 output_operand_lossage ("invalid operand for code '%c'", code);
10659 asm_fprintf (stream, "%r", REGNO (x) + 1);
10663 asm_fprintf (stream, "%r",
10664 GET_CODE (XEXP (x, 0)) == REG
10665 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10669 asm_fprintf (stream, "{%r-%r}",
10671 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10675 /* CONST_TRUE_RTX means always -- that's the default. */
10676 if (x == const_true_rtx)
10679 if (!COMPARISON_P (x))
10681 output_operand_lossage ("invalid operand for code '%c'", code);
10685 fputs (arm_condition_codes[get_arm_condition_code (x)],
10690 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10691 want to do that. */
10692 if (x == const_true_rtx)
10694 output_operand_lossage ("instruction never exectued");
10697 if (!COMPARISON_P (x))
10699 output_operand_lossage ("invalid operand for code '%c'", code);
10703 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10704 (get_arm_condition_code (x))],
10708 /* Cirrus registers can be accessed in a variety of ways:
10709 single floating point (f)
10710 double floating point (d)
10712 64bit integer (dx). */
10713 case 'W': /* Cirrus register in F mode. */
10714 case 'X': /* Cirrus register in D mode. */
10715 case 'Y': /* Cirrus register in FX mode. */
10716 case 'Z': /* Cirrus register in DX mode. */
10717 gcc_assert (GET_CODE (x) == REG
10718 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
10720 fprintf (stream, "mv%s%s",
10722 : code == 'X' ? "d"
10723 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10727 /* Print cirrus register in the mode specified by the register's mode. */
10730 int mode = GET_MODE (x);
10732 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10734 output_operand_lossage ("invalid operand for code '%c'", code);
10738 fprintf (stream, "mv%s%s",
10739 mode == DFmode ? "d"
10740 : mode == SImode ? "fx"
10741 : mode == DImode ? "dx"
10742 : "f", reg_names[REGNO (x)] + 2);
10748 if (GET_CODE (x) != REG
10749 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10750 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10751 /* Bad value for wCG register number. */
10753 output_operand_lossage ("invalid operand for code '%c'", code);
10758 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10761 /* Print an iWMMXt control register name. */
10763 if (GET_CODE (x) != CONST_INT
10765 || INTVAL (x) >= 16)
10766 /* Bad value for wC register number. */
10768 output_operand_lossage ("invalid operand for code '%c'", code);
10774 static const char * wc_reg_names [16] =
10776 "wCID", "wCon", "wCSSF", "wCASF",
10777 "wC4", "wC5", "wC6", "wC7",
10778 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10779 "wC12", "wC13", "wC14", "wC15"
10782 fprintf (stream, wc_reg_names [INTVAL (x)]);
10786 /* Print a VFP double precision register name. */
10789 int mode = GET_MODE (x);
10792 if (mode != DImode && mode != DFmode)
10794 output_operand_lossage ("invalid operand for code '%c'", code);
10798 if (GET_CODE (x) != REG
10799 || !IS_VFP_REGNUM (REGNO (x)))
10801 output_operand_lossage ("invalid operand for code '%c'", code);
10805 num = REGNO(x) - FIRST_VFP_REGNUM;
10808 output_operand_lossage ("invalid operand for code '%c'", code);
10812 fprintf (stream, "d%d", num >> 1);
10819 output_operand_lossage ("missing operand");
10823 switch (GET_CODE (x))
10826 asm_fprintf (stream, "%r", REGNO (x));
10830 output_memory_reference_mode = GET_MODE (x);
10831 output_address (XEXP (x, 0));
10835 fprintf (stream, "#%s", fp_immediate_constant (x));
10839 gcc_assert (GET_CODE (x) != NEG);
10840 fputc ('#', stream);
10841 output_addr_const (stream, x);
10847 #ifndef AOF_ASSEMBLER
10848 /* Target hook for assembling integer objects. The ARM version needs to
10849 handle word-sized values specially. */
10851 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10853 if (size == UNITS_PER_WORD && aligned_p)
10855 fputs ("\t.word\t", asm_out_file);
10856 output_addr_const (asm_out_file, x);
10858 /* Mark symbols as position independent. We only do this in the
10859 .text segment, not in the .data segment. */
10860 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10861 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10863 if (GET_CODE (x) == SYMBOL_REF
10864 && (CONSTANT_POOL_ADDRESS_P (x)
10865 || SYMBOL_REF_LOCAL_P (x)))
10866 fputs ("(GOTOFF)", asm_out_file);
10867 else if (GET_CODE (x) == LABEL_REF)
10868 fputs ("(GOTOFF)", asm_out_file);
10870 fputs ("(GOT)", asm_out_file);
10872 fputc ('\n', asm_out_file);
10876 if (arm_vector_mode_supported_p (GET_MODE (x)))
10880 gcc_assert (GET_CODE (x) == CONST_VECTOR);
10882 units = CONST_VECTOR_NUNITS (x);
10884 switch (GET_MODE (x))
10886 case V2SImode: size = 4; break;
10887 case V4HImode: size = 2; break;
10888 case V8QImode: size = 1; break;
10890 gcc_unreachable ();
10893 for (i = 0; i < units; i++)
10897 elt = CONST_VECTOR_ELT (x, i);
10899 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10905 return default_assemble_integer (x, size, aligned_p);
10909 /* Add a function to the list of static constructors. */
10912 arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10914 if (!TARGET_AAPCS_BASED)
10916 default_named_section_asm_out_constructor (symbol, priority);
10920 /* Put these in the .init_array section, using a special relocation. */
10922 assemble_align (POINTER_SIZE);
10923 fputs ("\t.word\t", asm_out_file);
10924 output_addr_const (asm_out_file, symbol);
10925 fputs ("(target1)\n", asm_out_file);
10929 /* A finite state machine takes care of noticing whether or not instructions
10930 can be conditionally executed, and thus decrease execution time and code
10931 size by deleting branch instructions. The fsm is controlled by
10932 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10934 /* The state of the fsm controlling condition codes are:
10935 0: normal, do nothing special
10936 1: make ASM_OUTPUT_OPCODE not output this instruction
10937 2: make ASM_OUTPUT_OPCODE not output this instruction
10938 3: make instructions conditional
10939 4: make instructions conditional
10941 State transitions (state->state by whom under condition):
10942 0 -> 1 final_prescan_insn if the `target' is a label
10943 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10944 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10945 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10946 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10947 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10948 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10949 (the target insn is arm_target_insn).
10951 If the jump clobbers the conditions then we use states 2 and 4.
10953 A similar thing can be done with conditional return insns.
10955 XXX In case the `target' is an unconditional branch, this conditionalising
10956 of the instructions always reduces code size, but not always execution
10957 time. But then, I want to reduce the code size to somewhere near what
10958 /bin/cc produces. */
10960 /* Returns the index of the ARM condition code string in
10961 `arm_condition_codes'. COMPARISON should be an rtx like
10962 `(eq (...) (...))'. */
10963 static enum arm_cond_code
10964 get_arm_condition_code (rtx comparison)
10966 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10968 enum rtx_code comp_code = GET_CODE (comparison);
10970 if (GET_MODE_CLASS (mode) != MODE_CC)
10971 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10972 XEXP (comparison, 1));
10976 case CC_DNEmode: code = ARM_NE; goto dominance;
10977 case CC_DEQmode: code = ARM_EQ; goto dominance;
10978 case CC_DGEmode: code = ARM_GE; goto dominance;
10979 case CC_DGTmode: code = ARM_GT; goto dominance;
10980 case CC_DLEmode: code = ARM_LE; goto dominance;
10981 case CC_DLTmode: code = ARM_LT; goto dominance;
10982 case CC_DGEUmode: code = ARM_CS; goto dominance;
10983 case CC_DGTUmode: code = ARM_HI; goto dominance;
10984 case CC_DLEUmode: code = ARM_LS; goto dominance;
10985 case CC_DLTUmode: code = ARM_CC;
10988 gcc_assert (comp_code == EQ || comp_code == NE);
10990 if (comp_code == EQ)
10991 return ARM_INVERSE_CONDITION_CODE (code);
10997 case NE: return ARM_NE;
10998 case EQ: return ARM_EQ;
10999 case GE: return ARM_PL;
11000 case LT: return ARM_MI;
11001 default: gcc_unreachable ();
11007 case NE: return ARM_NE;
11008 case EQ: return ARM_EQ;
11009 default: gcc_unreachable ();
11015 case NE: return ARM_MI;
11016 case EQ: return ARM_PL;
11017 default: gcc_unreachable ();
11022 /* These encodings assume that AC=1 in the FPA system control
11023 byte. This allows us to handle all cases except UNEQ and
11027 case GE: return ARM_GE;
11028 case GT: return ARM_GT;
11029 case LE: return ARM_LS;
11030 case LT: return ARM_MI;
11031 case NE: return ARM_NE;
11032 case EQ: return ARM_EQ;
11033 case ORDERED: return ARM_VC;
11034 case UNORDERED: return ARM_VS;
11035 case UNLT: return ARM_LT;
11036 case UNLE: return ARM_LE;
11037 case UNGT: return ARM_HI;
11038 case UNGE: return ARM_PL;
11039 /* UNEQ and LTGT do not have a representation. */
11040 case UNEQ: /* Fall through. */
11041 case LTGT: /* Fall through. */
11042 default: gcc_unreachable ();
11048 case NE: return ARM_NE;
11049 case EQ: return ARM_EQ;
11050 case GE: return ARM_LE;
11051 case GT: return ARM_LT;
11052 case LE: return ARM_GE;
11053 case LT: return ARM_GT;
11054 case GEU: return ARM_LS;
11055 case GTU: return ARM_CC;
11056 case LEU: return ARM_CS;
11057 case LTU: return ARM_HI;
11058 default: gcc_unreachable ();
11064 case LTU: return ARM_CS;
11065 case GEU: return ARM_CC;
11066 default: gcc_unreachable ();
11072 case NE: return ARM_NE;
11073 case EQ: return ARM_EQ;
11074 case GE: return ARM_GE;
11075 case GT: return ARM_GT;
11076 case LE: return ARM_LE;
11077 case LT: return ARM_LT;
11078 case GEU: return ARM_CS;
11079 case GTU: return ARM_HI;
11080 case LEU: return ARM_LS;
11081 case LTU: return ARM_CC;
11082 default: gcc_unreachable ();
11085 default: gcc_unreachable ();
11090 arm_final_prescan_insn (rtx insn)
11092 /* BODY will hold the body of INSN. */
11093 rtx body = PATTERN (insn);
11095 /* This will be 1 if trying to repeat the trick, and things need to be
11096 reversed if it appears to fail. */
11099 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11100 taken are clobbered, even if the rtl suggests otherwise. It also
11101 means that we have to grub around within the jump expression to find
11102 out what the conditions are when the jump isn't taken. */
11103 int jump_clobbers = 0;
11105 /* If we start with a return insn, we only succeed if we find another one. */
11106 int seeking_return = 0;
11108 /* START_INSN will hold the insn from where we start looking. This is the
11109 first insn after the following code_label if REVERSE is true. */
11110 rtx start_insn = insn;
11112 /* If in state 4, check if the target branch is reached, in order to
11113 change back to state 0. */
11114 if (arm_ccfsm_state == 4)
11116 if (insn == arm_target_insn)
11118 arm_target_insn = NULL;
11119 arm_ccfsm_state = 0;
11124 /* If in state 3, it is possible to repeat the trick, if this insn is an
11125 unconditional branch to a label, and immediately following this branch
11126 is the previous target label which is only used once, and the label this
11127 branch jumps to is not too far off. */
11128 if (arm_ccfsm_state == 3)
11130 if (simplejump_p (insn))
11132 start_insn = next_nonnote_insn (start_insn);
11133 if (GET_CODE (start_insn) == BARRIER)
11135 /* XXX Isn't this always a barrier? */
11136 start_insn = next_nonnote_insn (start_insn);
11138 if (GET_CODE (start_insn) == CODE_LABEL
11139 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11140 && LABEL_NUSES (start_insn) == 1)
11145 else if (GET_CODE (body) == RETURN)
11147 start_insn = next_nonnote_insn (start_insn);
11148 if (GET_CODE (start_insn) == BARRIER)
11149 start_insn = next_nonnote_insn (start_insn);
11150 if (GET_CODE (start_insn) == CODE_LABEL
11151 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11152 && LABEL_NUSES (start_insn) == 1)
11155 seeking_return = 1;
11164 gcc_assert (!arm_ccfsm_state || reverse);
11165 if (GET_CODE (insn) != JUMP_INSN)
11168 /* This jump might be paralleled with a clobber of the condition codes
11169 the jump should always come first */
11170 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11171 body = XVECEXP (body, 0, 0);
11174 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11175 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11178 int fail = FALSE, succeed = FALSE;
11179 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11180 int then_not_else = TRUE;
11181 rtx this_insn = start_insn, label = 0;
11183 /* If the jump cannot be done with one instruction, we cannot
11184 conditionally execute the instruction in the inverse case. */
11185 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11191 /* Register the insn jumped to. */
11194 if (!seeking_return)
11195 label = XEXP (SET_SRC (body), 0);
11197 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11198 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11199 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11201 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11202 then_not_else = FALSE;
11204 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11205 seeking_return = 1;
11206 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11208 seeking_return = 1;
11209 then_not_else = FALSE;
11212 gcc_unreachable ();
11214 /* See how many insns this branch skips, and what kind of insns. If all
11215 insns are okay, and the label or unconditional branch to the same
11216 label is not too far away, succeed. */
11217 for (insns_skipped = 0;
11218 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11222 this_insn = next_nonnote_insn (this_insn);
11226 switch (GET_CODE (this_insn))
11229 /* Succeed if it is the target label, otherwise fail since
11230 control falls in from somewhere else. */
11231 if (this_insn == label)
11235 arm_ccfsm_state = 2;
11236 this_insn = next_nonnote_insn (this_insn);
11239 arm_ccfsm_state = 1;
11247 /* Succeed if the following insn is the target label.
11249 If return insns are used then the last insn in a function
11250 will be a barrier. */
11251 this_insn = next_nonnote_insn (this_insn);
11252 if (this_insn && this_insn == label)
11256 arm_ccfsm_state = 2;
11257 this_insn = next_nonnote_insn (this_insn);
11260 arm_ccfsm_state = 1;
11268 /* The AAPCS says that conditional calls should not be
11269 used since they make interworking inefficient (the
11270 linker can't transform BL<cond> into BLX). That's
11271 only a problem if the machine has BLX. */
11278 /* Succeed if the following insn is the target label, or
11279 if the following two insns are a barrier and the
11281 this_insn = next_nonnote_insn (this_insn);
11282 if (this_insn && GET_CODE (this_insn) == BARRIER)
11283 this_insn = next_nonnote_insn (this_insn);
11285 if (this_insn && this_insn == label
11286 && insns_skipped < max_insns_skipped)
11290 arm_ccfsm_state = 2;
11291 this_insn = next_nonnote_insn (this_insn);
11294 arm_ccfsm_state = 1;
11302 /* If this is an unconditional branch to the same label, succeed.
11303 If it is to another label, do nothing. If it is conditional,
11305 /* XXX Probably, the tests for SET and the PC are
11308 scanbody = PATTERN (this_insn);
11309 if (GET_CODE (scanbody) == SET
11310 && GET_CODE (SET_DEST (scanbody)) == PC)
11312 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11313 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11315 arm_ccfsm_state = 2;
11318 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11321 /* Fail if a conditional return is undesirable (e.g. on a
11322 StrongARM), but still allow this if optimizing for size. */
11323 else if (GET_CODE (scanbody) == RETURN
11324 && !use_return_insn (TRUE, NULL)
11327 else if (GET_CODE (scanbody) == RETURN
11330 arm_ccfsm_state = 2;
11333 else if (GET_CODE (scanbody) == PARALLEL)
11335 switch (get_attr_conds (this_insn))
11345 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11350 /* Instructions using or affecting the condition codes make it
11352 scanbody = PATTERN (this_insn);
11353 if (!(GET_CODE (scanbody) == SET
11354 || GET_CODE (scanbody) == PARALLEL)
11355 || get_attr_conds (this_insn) != CONDS_NOCOND)
11358 /* A conditional cirrus instruction must be followed by
11359 a non Cirrus instruction. However, since we
11360 conditionalize instructions in this function and by
11361 the time we get here we can't add instructions
11362 (nops), because shorten_branches() has already been
11363 called, we will disable conditionalizing Cirrus
11364 instructions to be safe. */
11365 if (GET_CODE (scanbody) != USE
11366 && GET_CODE (scanbody) != CLOBBER
11367 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11377 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11378 arm_target_label = CODE_LABEL_NUMBER (label);
11381 gcc_assert (seeking_return || arm_ccfsm_state == 2);
11383 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11385 this_insn = next_nonnote_insn (this_insn);
11386 gcc_assert (!this_insn
11387 || (GET_CODE (this_insn) != BARRIER
11388 && GET_CODE (this_insn) != CODE_LABEL));
11392 /* Oh, dear! we ran off the end.. give up. */
11393 recog (PATTERN (insn), insn, NULL);
11394 arm_ccfsm_state = 0;
11395 arm_target_insn = NULL;
11398 arm_target_insn = this_insn;
11402 gcc_assert (!reverse);
11404 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11406 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11407 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11408 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11409 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11413 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11416 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11420 if (reverse || then_not_else)
11421 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11424 /* Restore recog_data (getting the attributes of other insns can
11425 destroy this array, but final.c assumes that it remains intact
11426 across this call; since the insn has been recognized already we
11427 call recog direct). */
11428 recog (PATTERN (insn), insn, NULL);
11432 /* Returns true if REGNO is a valid register
11433 for holding a quantity of type MODE. */
11435 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11437 if (GET_MODE_CLASS (mode) == MODE_CC)
11438 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11441 /* For the Thumb we only allow values bigger than SImode in
11442 registers 0 - 6, so that there is always a second low
11443 register available to hold the upper part of the value.
11444 We probably we ought to ensure that the register is the
11445 start of an even numbered register pair. */
11446 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11448 if (IS_CIRRUS_REGNUM (regno))
11449 /* We have outlawed SI values in Cirrus registers because they
11450 reside in the lower 32 bits, but SF values reside in the
11451 upper 32 bits. This causes gcc all sorts of grief. We can't
11452 even split the registers into pairs because Cirrus SI values
11453 get sign extended to 64bits-- aldyh. */
11454 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11456 if (IS_VFP_REGNUM (regno))
11458 if (mode == SFmode || mode == SImode)
11461 /* DFmode values are only valid in even register pairs. */
11462 if (mode == DFmode)
11463 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11467 if (IS_IWMMXT_GR_REGNUM (regno))
11468 return mode == SImode;
11470 if (IS_IWMMXT_REGNUM (regno))
11471 return VALID_IWMMXT_REG_MODE (mode);
11473 /* We allow any value to be stored in the general registers.
11474 Restrict doubleword quantities to even register pairs so that we can
11476 if (regno <= LAST_ARM_REGNUM)
11477 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11479 if ( regno == FRAME_POINTER_REGNUM
11480 || regno == ARG_POINTER_REGNUM)
11481 /* We only allow integers in the fake hard registers. */
11482 return GET_MODE_CLASS (mode) == MODE_INT;
11484 /* The only registers left are the FPA registers
11485 which we only allow to hold FP values. */
11486 return GET_MODE_CLASS (mode) == MODE_FLOAT
11487 && regno >= FIRST_FPA_REGNUM
11488 && regno <= LAST_FPA_REGNUM;
11492 arm_regno_class (int regno)
11496 if (regno == STACK_POINTER_REGNUM)
11498 if (regno == CC_REGNUM)
11505 if ( regno <= LAST_ARM_REGNUM
11506 || regno == FRAME_POINTER_REGNUM
11507 || regno == ARG_POINTER_REGNUM)
11508 return GENERAL_REGS;
11510 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11513 if (IS_CIRRUS_REGNUM (regno))
11514 return CIRRUS_REGS;
11516 if (IS_VFP_REGNUM (regno))
11519 if (IS_IWMMXT_REGNUM (regno))
11520 return IWMMXT_REGS;
11522 if (IS_IWMMXT_GR_REGNUM (regno))
11523 return IWMMXT_GR_REGS;
11528 /* Handle a special case when computing the offset
11529 of an argument from the frame pointer. */
11531 arm_debugger_arg_offset (int value, rtx addr)
11535 /* We are only interested if dbxout_parms() failed to compute the offset. */
11539 /* We can only cope with the case where the address is held in a register. */
11540 if (GET_CODE (addr) != REG)
11543 /* If we are using the frame pointer to point at the argument, then
11544 an offset of 0 is correct. */
11545 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11548 /* If we are using the stack pointer to point at the
11549 argument, then an offset of 0 is correct. */
11550 if ((TARGET_THUMB || !frame_pointer_needed)
11551 && REGNO (addr) == SP_REGNUM)
11554 /* Oh dear. The argument is pointed to by a register rather
11555 than being held in a register, or being stored at a known
11556 offset from the frame pointer. Since GDB only understands
11557 those two kinds of argument we must translate the address
11558 held in the register into an offset from the frame pointer.
11559 We do this by searching through the insns for the function
11560 looking to see where this register gets its value. If the
11561 register is initialized from the frame pointer plus an offset
11562 then we are in luck and we can continue, otherwise we give up.
11564 This code is exercised by producing debugging information
11565 for a function with arguments like this:
11567 double func (double a, double b, int c, double d) {return d;}
11569 Without this code the stab for parameter 'd' will be set to
11570 an offset of 0 from the frame pointer, rather than 8. */
11572 /* The if() statement says:
11574 If the insn is a normal instruction
11575 and if the insn is setting the value in a register
11576 and if the register being set is the register holding the address of the argument
11577 and if the address is computing by an addition
11578 that involves adding to a register
11579 which is the frame pointer
11584 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11586 if ( GET_CODE (insn) == INSN
11587 && GET_CODE (PATTERN (insn)) == SET
11588 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11589 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11590 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11591 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11592 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11595 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11604 warning (0, "unable to compute real location of stacked parameter");
11605 value = 8; /* XXX magic hack */
11611 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11614 if ((MASK) & insn_flags) \
11615 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11616 BUILT_IN_MD, NULL, NULL_TREE); \
11620 struct builtin_description
11622 const unsigned int mask;
11623 const enum insn_code icode;
11624 const char * const name;
11625 const enum arm_builtins code;
11626 const enum rtx_code comparison;
11627 const unsigned int flag;
11630 static const struct builtin_description bdesc_2arg[] =
11632 #define IWMMXT_BUILTIN(code, string, builtin) \
11633 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11634 ARM_BUILTIN_##builtin, 0, 0 },
11636 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11637 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11638 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11639 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11640 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11641 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11642 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11643 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11644 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11645 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11646 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11647 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11648 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11649 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11650 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11651 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11652 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11653 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11654 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11655 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11656 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11657 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11658 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11659 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11660 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11661 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11662 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11663 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11664 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11665 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11666 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11667 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11668 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11669 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11670 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11671 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11672 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11673 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11674 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11675 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11676 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11677 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11678 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11679 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11680 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11681 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11682 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11683 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11684 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11685 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11686 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11687 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11688 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11689 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11690 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11691 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11692 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11693 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11695 #define IWMMXT_BUILTIN2(code, builtin) \
11696 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11698 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11699 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11700 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11701 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11702 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11703 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11704 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11705 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11706 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11707 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11708 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11709 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11710 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11711 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11712 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11713 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11714 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11715 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11716 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11717 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11718 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11719 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11720 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11721 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11722 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11723 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11724 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11725 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11726 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11727 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11728 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11729 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11732 static const struct builtin_description bdesc_1arg[] =
11734 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11735 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11736 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11737 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11738 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11739 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11740 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11741 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11742 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11743 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11744 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11745 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11746 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11747 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11748 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11749 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11750 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11751 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11754 /* Set up all the iWMMXt builtins. This is
11755 not called if TARGET_IWMMXT is zero. */
11758 arm_init_iwmmxt_builtins (void)
11760 const struct builtin_description * d;
11762 tree endlink = void_list_node;
11764 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11765 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11766 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11769 = build_function_type (integer_type_node,
11770 tree_cons (NULL_TREE, integer_type_node, endlink));
11771 tree v8qi_ftype_v8qi_v8qi_int
11772 = build_function_type (V8QI_type_node,
11773 tree_cons (NULL_TREE, V8QI_type_node,
11774 tree_cons (NULL_TREE, V8QI_type_node,
11775 tree_cons (NULL_TREE,
11778 tree v4hi_ftype_v4hi_int
11779 = build_function_type (V4HI_type_node,
11780 tree_cons (NULL_TREE, V4HI_type_node,
11781 tree_cons (NULL_TREE, integer_type_node,
11783 tree v2si_ftype_v2si_int
11784 = build_function_type (V2SI_type_node,
11785 tree_cons (NULL_TREE, V2SI_type_node,
11786 tree_cons (NULL_TREE, integer_type_node,
11788 tree v2si_ftype_di_di
11789 = build_function_type (V2SI_type_node,
11790 tree_cons (NULL_TREE, long_long_integer_type_node,
11791 tree_cons (NULL_TREE, long_long_integer_type_node,
11793 tree di_ftype_di_int
11794 = build_function_type (long_long_integer_type_node,
11795 tree_cons (NULL_TREE, long_long_integer_type_node,
11796 tree_cons (NULL_TREE, integer_type_node,
11798 tree di_ftype_di_int_int
11799 = build_function_type (long_long_integer_type_node,
11800 tree_cons (NULL_TREE, long_long_integer_type_node,
11801 tree_cons (NULL_TREE, integer_type_node,
11802 tree_cons (NULL_TREE,
11805 tree int_ftype_v8qi
11806 = build_function_type (integer_type_node,
11807 tree_cons (NULL_TREE, V8QI_type_node,
11809 tree int_ftype_v4hi
11810 = build_function_type (integer_type_node,
11811 tree_cons (NULL_TREE, V4HI_type_node,
11813 tree int_ftype_v2si
11814 = build_function_type (integer_type_node,
11815 tree_cons (NULL_TREE, V2SI_type_node,
11817 tree int_ftype_v8qi_int
11818 = build_function_type (integer_type_node,
11819 tree_cons (NULL_TREE, V8QI_type_node,
11820 tree_cons (NULL_TREE, integer_type_node,
11822 tree int_ftype_v4hi_int
11823 = build_function_type (integer_type_node,
11824 tree_cons (NULL_TREE, V4HI_type_node,
11825 tree_cons (NULL_TREE, integer_type_node,
11827 tree int_ftype_v2si_int
11828 = build_function_type (integer_type_node,
11829 tree_cons (NULL_TREE, V2SI_type_node,
11830 tree_cons (NULL_TREE, integer_type_node,
11832 tree v8qi_ftype_v8qi_int_int
11833 = build_function_type (V8QI_type_node,
11834 tree_cons (NULL_TREE, V8QI_type_node,
11835 tree_cons (NULL_TREE, integer_type_node,
11836 tree_cons (NULL_TREE,
11839 tree v4hi_ftype_v4hi_int_int
11840 = build_function_type (V4HI_type_node,
11841 tree_cons (NULL_TREE, V4HI_type_node,
11842 tree_cons (NULL_TREE, integer_type_node,
11843 tree_cons (NULL_TREE,
11846 tree v2si_ftype_v2si_int_int
11847 = build_function_type (V2SI_type_node,
11848 tree_cons (NULL_TREE, V2SI_type_node,
11849 tree_cons (NULL_TREE, integer_type_node,
11850 tree_cons (NULL_TREE,
11853 /* Miscellaneous. */
11854 tree v8qi_ftype_v4hi_v4hi
11855 = build_function_type (V8QI_type_node,
11856 tree_cons (NULL_TREE, V4HI_type_node,
11857 tree_cons (NULL_TREE, V4HI_type_node,
11859 tree v4hi_ftype_v2si_v2si
11860 = build_function_type (V4HI_type_node,
11861 tree_cons (NULL_TREE, V2SI_type_node,
11862 tree_cons (NULL_TREE, V2SI_type_node,
11864 tree v2si_ftype_v4hi_v4hi
11865 = build_function_type (V2SI_type_node,
11866 tree_cons (NULL_TREE, V4HI_type_node,
11867 tree_cons (NULL_TREE, V4HI_type_node,
11869 tree v2si_ftype_v8qi_v8qi
11870 = build_function_type (V2SI_type_node,
11871 tree_cons (NULL_TREE, V8QI_type_node,
11872 tree_cons (NULL_TREE, V8QI_type_node,
11874 tree v4hi_ftype_v4hi_di
11875 = build_function_type (V4HI_type_node,
11876 tree_cons (NULL_TREE, V4HI_type_node,
11877 tree_cons (NULL_TREE,
11878 long_long_integer_type_node,
11880 tree v2si_ftype_v2si_di
11881 = build_function_type (V2SI_type_node,
11882 tree_cons (NULL_TREE, V2SI_type_node,
11883 tree_cons (NULL_TREE,
11884 long_long_integer_type_node,
11886 tree void_ftype_int_int
11887 = build_function_type (void_type_node,
11888 tree_cons (NULL_TREE, integer_type_node,
11889 tree_cons (NULL_TREE, integer_type_node,
11892 = build_function_type (long_long_unsigned_type_node, endlink);
11894 = build_function_type (long_long_integer_type_node,
11895 tree_cons (NULL_TREE, V8QI_type_node,
11898 = build_function_type (long_long_integer_type_node,
11899 tree_cons (NULL_TREE, V4HI_type_node,
11902 = build_function_type (long_long_integer_type_node,
11903 tree_cons (NULL_TREE, V2SI_type_node,
11905 tree v2si_ftype_v4hi
11906 = build_function_type (V2SI_type_node,
11907 tree_cons (NULL_TREE, V4HI_type_node,
11909 tree v4hi_ftype_v8qi
11910 = build_function_type (V4HI_type_node,
11911 tree_cons (NULL_TREE, V8QI_type_node,
11914 tree di_ftype_di_v4hi_v4hi
11915 = build_function_type (long_long_unsigned_type_node,
11916 tree_cons (NULL_TREE,
11917 long_long_unsigned_type_node,
11918 tree_cons (NULL_TREE, V4HI_type_node,
11919 tree_cons (NULL_TREE,
11923 tree di_ftype_v4hi_v4hi
11924 = build_function_type (long_long_unsigned_type_node,
11925 tree_cons (NULL_TREE, V4HI_type_node,
11926 tree_cons (NULL_TREE, V4HI_type_node,
11929 /* Normal vector binops. */
11930 tree v8qi_ftype_v8qi_v8qi
11931 = build_function_type (V8QI_type_node,
11932 tree_cons (NULL_TREE, V8QI_type_node,
11933 tree_cons (NULL_TREE, V8QI_type_node,
11935 tree v4hi_ftype_v4hi_v4hi
11936 = build_function_type (V4HI_type_node,
11937 tree_cons (NULL_TREE, V4HI_type_node,
11938 tree_cons (NULL_TREE, V4HI_type_node,
11940 tree v2si_ftype_v2si_v2si
11941 = build_function_type (V2SI_type_node,
11942 tree_cons (NULL_TREE, V2SI_type_node,
11943 tree_cons (NULL_TREE, V2SI_type_node,
11945 tree di_ftype_di_di
11946 = build_function_type (long_long_unsigned_type_node,
11947 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11948 tree_cons (NULL_TREE,
11949 long_long_unsigned_type_node,
11952 /* Add all builtins that are more or less simple operations on two
11954 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11956 /* Use one of the operands; the target can have a different mode for
11957 mask-generating compares. */
11958 enum machine_mode mode;
11964 mode = insn_data[d->icode].operand[1].mode;
11969 type = v8qi_ftype_v8qi_v8qi;
11972 type = v4hi_ftype_v4hi_v4hi;
11975 type = v2si_ftype_v2si_v2si;
11978 type = di_ftype_di_di;
11982 gcc_unreachable ();
11985 def_mbuiltin (d->mask, d->name, type, d->code);
11988 /* Add the remaining MMX insns with somewhat more complicated types. */
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11991 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11998 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12002 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12005 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12012 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12015 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12019 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12026 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12040 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12056 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12057 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12061 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12063 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12064 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12066 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12067 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12068 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12069 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12071 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12072 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12073 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12074 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12075 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12076 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12077 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12081 arm_init_builtins (void)
12083 if (TARGET_REALLY_IWMMXT)
12084 arm_init_iwmmxt_builtins ();
12087 /* Errors in the source file can cause expand_expr to return const0_rtx
12088 where we expect a vector. To avoid crashing, use one of the vector
12089 clear instructions. */
12092 safe_vector_operand (rtx x, enum machine_mode mode)
12094 if (x != const0_rtx)
12096 x = gen_reg_rtx (mode);
12098 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12099 : gen_rtx_SUBREG (DImode, x, 0)));
12103 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12106 arm_expand_binop_builtin (enum insn_code icode,
12107 tree arglist, rtx target)
12110 tree arg0 = TREE_VALUE (arglist);
12111 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12112 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12113 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12114 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12115 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12116 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12118 if (VECTOR_MODE_P (mode0))
12119 op0 = safe_vector_operand (op0, mode0);
12120 if (VECTOR_MODE_P (mode1))
12121 op1 = safe_vector_operand (op1, mode1);
12124 || GET_MODE (target) != tmode
12125 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12126 target = gen_reg_rtx (tmode);
12128 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
12130 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12131 op0 = copy_to_mode_reg (mode0, op0);
12132 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12133 op1 = copy_to_mode_reg (mode1, op1);
12135 pat = GEN_FCN (icode) (target, op0, op1);
12142 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12145 arm_expand_unop_builtin (enum insn_code icode,
12146 tree arglist, rtx target, int do_load)
12149 tree arg0 = TREE_VALUE (arglist);
12150 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12151 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12152 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12155 || GET_MODE (target) != tmode
12156 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12157 target = gen_reg_rtx (tmode);
12159 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12162 if (VECTOR_MODE_P (mode0))
12163 op0 = safe_vector_operand (op0, mode0);
12165 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12166 op0 = copy_to_mode_reg (mode0, op0);
12169 pat = GEN_FCN (icode) (target, op0);
12176 /* Expand an expression EXP that calls a built-in function,
12177 with result going to TARGET if that's convenient
12178 (and in mode MODE if that's convenient).
12179 SUBTARGET may be used as the target for computing one of EXP's operands.
12180 IGNORE is nonzero if the value is to be ignored. */
12183 arm_expand_builtin (tree exp,
12185 rtx subtarget ATTRIBUTE_UNUSED,
12186 enum machine_mode mode ATTRIBUTE_UNUSED,
12187 int ignore ATTRIBUTE_UNUSED)
12189 const struct builtin_description * d;
12190 enum insn_code icode;
12191 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12192 tree arglist = TREE_OPERAND (exp, 1);
12200 int fcode = DECL_FUNCTION_CODE (fndecl);
12202 enum machine_mode tmode;
12203 enum machine_mode mode0;
12204 enum machine_mode mode1;
12205 enum machine_mode mode2;
12209 case ARM_BUILTIN_TEXTRMSB:
12210 case ARM_BUILTIN_TEXTRMUB:
12211 case ARM_BUILTIN_TEXTRMSH:
12212 case ARM_BUILTIN_TEXTRMUH:
12213 case ARM_BUILTIN_TEXTRMSW:
12214 case ARM_BUILTIN_TEXTRMUW:
12215 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12216 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12217 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12218 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12219 : CODE_FOR_iwmmxt_textrmw);
12221 arg0 = TREE_VALUE (arglist);
12222 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12223 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12224 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12225 tmode = insn_data[icode].operand[0].mode;
12226 mode0 = insn_data[icode].operand[1].mode;
12227 mode1 = insn_data[icode].operand[2].mode;
12229 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12230 op0 = copy_to_mode_reg (mode0, op0);
12231 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12233 /* @@@ better error message */
12234 error ("selector must be an immediate");
12235 return gen_reg_rtx (tmode);
12238 || GET_MODE (target) != tmode
12239 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12240 target = gen_reg_rtx (tmode);
12241 pat = GEN_FCN (icode) (target, op0, op1);
12247 case ARM_BUILTIN_TINSRB:
12248 case ARM_BUILTIN_TINSRH:
12249 case ARM_BUILTIN_TINSRW:
12250 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12251 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12252 : CODE_FOR_iwmmxt_tinsrw);
12253 arg0 = TREE_VALUE (arglist);
12254 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12255 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12256 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12257 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12258 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12259 tmode = insn_data[icode].operand[0].mode;
12260 mode0 = insn_data[icode].operand[1].mode;
12261 mode1 = insn_data[icode].operand[2].mode;
12262 mode2 = insn_data[icode].operand[3].mode;
12264 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12265 op0 = copy_to_mode_reg (mode0, op0);
12266 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12267 op1 = copy_to_mode_reg (mode1, op1);
12268 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12270 /* @@@ better error message */
12271 error ("selector must be an immediate");
12275 || GET_MODE (target) != tmode
12276 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12277 target = gen_reg_rtx (tmode);
12278 pat = GEN_FCN (icode) (target, op0, op1, op2);
12284 case ARM_BUILTIN_SETWCX:
12285 arg0 = TREE_VALUE (arglist);
12286 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12287 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12288 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12289 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12292 case ARM_BUILTIN_GETWCX:
12293 arg0 = TREE_VALUE (arglist);
12294 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12295 target = gen_reg_rtx (SImode);
12296 emit_insn (gen_iwmmxt_tmrc (target, op0));
12299 case ARM_BUILTIN_WSHUFH:
12300 icode = CODE_FOR_iwmmxt_wshufh;
12301 arg0 = TREE_VALUE (arglist);
12302 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12303 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12304 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12305 tmode = insn_data[icode].operand[0].mode;
12306 mode1 = insn_data[icode].operand[1].mode;
12307 mode2 = insn_data[icode].operand[2].mode;
12309 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12310 op0 = copy_to_mode_reg (mode1, op0);
12311 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12313 /* @@@ better error message */
12314 error ("mask must be an immediate");
12318 || GET_MODE (target) != tmode
12319 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12320 target = gen_reg_rtx (tmode);
12321 pat = GEN_FCN (icode) (target, op0, op1);
12327 case ARM_BUILTIN_WSADB:
12328 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12329 case ARM_BUILTIN_WSADH:
12330 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12331 case ARM_BUILTIN_WSADBZ:
12332 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12333 case ARM_BUILTIN_WSADHZ:
12334 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12336 /* Several three-argument builtins. */
12337 case ARM_BUILTIN_WMACS:
12338 case ARM_BUILTIN_WMACU:
12339 case ARM_BUILTIN_WALIGN:
12340 case ARM_BUILTIN_TMIA:
12341 case ARM_BUILTIN_TMIAPH:
12342 case ARM_BUILTIN_TMIATT:
12343 case ARM_BUILTIN_TMIATB:
12344 case ARM_BUILTIN_TMIABT:
12345 case ARM_BUILTIN_TMIABB:
12346 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12347 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12348 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12349 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12350 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12351 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12352 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12353 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12354 : CODE_FOR_iwmmxt_walign);
12355 arg0 = TREE_VALUE (arglist);
12356 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12357 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12358 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12359 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12360 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12361 tmode = insn_data[icode].operand[0].mode;
12362 mode0 = insn_data[icode].operand[1].mode;
12363 mode1 = insn_data[icode].operand[2].mode;
12364 mode2 = insn_data[icode].operand[3].mode;
12366 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12367 op0 = copy_to_mode_reg (mode0, op0);
12368 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12369 op1 = copy_to_mode_reg (mode1, op1);
12370 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12371 op2 = copy_to_mode_reg (mode2, op2);
12373 || GET_MODE (target) != tmode
12374 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12375 target = gen_reg_rtx (tmode);
12376 pat = GEN_FCN (icode) (target, op0, op1, op2);
12382 case ARM_BUILTIN_WZERO:
12383 target = gen_reg_rtx (DImode);
12384 emit_insn (gen_iwmmxt_clrdi (target));
12391 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12392 if (d->code == (const enum arm_builtins) fcode)
12393 return arm_expand_binop_builtin (d->icode, arglist, target);
12395 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12396 if (d->code == (const enum arm_builtins) fcode)
12397 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12399 /* @@@ Should really do something sensible here. */
12403 /* Return the number (counting from 0) of
12404 the least significant set bit in MASK. */
12407 number_of_first_bit_set (unsigned mask)
12412 (mask & (1 << bit)) == 0;
12419 /* Emit code to push or pop registers to or from the stack. F is the
12420 assembly file. MASK is the registers to push or pop. PUSH is
12421 nonzero if we should push, and zero if we should pop. For debugging
12422 output, if pushing, adjust CFA_OFFSET by the amount of space added
12423 to the stack. REAL_REGS should have the same number of bits set as
12424 MASK, and will be used instead (in the same order) to describe which
12425 registers were saved - this is used to mark the save slots when we
12426 push high registers after moving them to low registers. */
12428 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
12429 unsigned long real_regs)
12432 int lo_mask = mask & 0xFF;
12433 int pushed_words = 0;
12437 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12439 /* Special case. Do not generate a POP PC statement here, do it in
12441 thumb_exit (f, -1);
12445 if (ARM_EABI_UNWIND_TABLES && push)
12447 fprintf (f, "\t.save\t{");
12448 for (regno = 0; regno < 15; regno++)
12450 if (real_regs & (1 << regno))
12452 if (real_regs & ((1 << regno) -1))
12454 asm_fprintf (f, "%r", regno);
12457 fprintf (f, "}\n");
12460 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12462 /* Look at the low registers first. */
12463 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12467 asm_fprintf (f, "%r", regno);
12469 if ((lo_mask & ~1) != 0)
12476 if (push && (mask & (1 << LR_REGNUM)))
12478 /* Catch pushing the LR. */
12482 asm_fprintf (f, "%r", LR_REGNUM);
12486 else if (!push && (mask & (1 << PC_REGNUM)))
12488 /* Catch popping the PC. */
12489 if (TARGET_INTERWORK || TARGET_BACKTRACE
12490 || current_function_calls_eh_return)
12492 /* The PC is never poped directly, instead
12493 it is popped into r3 and then BX is used. */
12494 fprintf (f, "}\n");
12496 thumb_exit (f, -1);
12505 asm_fprintf (f, "%r", PC_REGNUM);
12509 fprintf (f, "}\n");
12511 if (push && pushed_words && dwarf2out_do_frame ())
12513 char *l = dwarf2out_cfi_label ();
12514 int pushed_mask = real_regs;
12516 *cfa_offset += pushed_words * 4;
12517 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12520 pushed_mask = real_regs;
12521 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12523 if (pushed_mask & 1)
12524 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12529 /* Generate code to return from a thumb function.
12530 If 'reg_containing_return_addr' is -1, then the return address is
12531 actually on the stack, at the stack pointer. */
12533 thumb_exit (FILE *f, int reg_containing_return_addr)
12535 unsigned regs_available_for_popping;
12536 unsigned regs_to_pop;
12538 unsigned available;
12542 int restore_a4 = FALSE;
12544 /* Compute the registers we need to pop. */
12548 if (reg_containing_return_addr == -1)
12550 regs_to_pop |= 1 << LR_REGNUM;
12554 if (TARGET_BACKTRACE)
12556 /* Restore the (ARM) frame pointer and stack pointer. */
12557 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12561 /* If there is nothing to pop then just emit the BX instruction and
12563 if (pops_needed == 0)
12565 if (current_function_calls_eh_return)
12566 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12568 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12571 /* Otherwise if we are not supporting interworking and we have not created
12572 a backtrace structure and the function was not entered in ARM mode then
12573 just pop the return address straight into the PC. */
12574 else if (!TARGET_INTERWORK
12575 && !TARGET_BACKTRACE
12576 && !is_called_in_ARM_mode (current_function_decl)
12577 && !current_function_calls_eh_return)
12579 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12583 /* Find out how many of the (return) argument registers we can corrupt. */
12584 regs_available_for_popping = 0;
12586 /* If returning via __builtin_eh_return, the bottom three registers
12587 all contain information needed for the return. */
12588 if (current_function_calls_eh_return)
12592 /* If we can deduce the registers used from the function's
12593 return value. This is more reliable that examining
12594 regs_ever_live[] because that will be set if the register is
12595 ever used in the function, not just if the register is used
12596 to hold a return value. */
12598 if (current_function_return_rtx != 0)
12599 mode = GET_MODE (current_function_return_rtx);
12601 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12603 size = GET_MODE_SIZE (mode);
12607 /* In a void function we can use any argument register.
12608 In a function that returns a structure on the stack
12609 we can use the second and third argument registers. */
12610 if (mode == VOIDmode)
12611 regs_available_for_popping =
12612 (1 << ARG_REGISTER (1))
12613 | (1 << ARG_REGISTER (2))
12614 | (1 << ARG_REGISTER (3));
12616 regs_available_for_popping =
12617 (1 << ARG_REGISTER (2))
12618 | (1 << ARG_REGISTER (3));
12620 else if (size <= 4)
12621 regs_available_for_popping =
12622 (1 << ARG_REGISTER (2))
12623 | (1 << ARG_REGISTER (3));
12624 else if (size <= 8)
12625 regs_available_for_popping =
12626 (1 << ARG_REGISTER (3));
12629 /* Match registers to be popped with registers into which we pop them. */
12630 for (available = regs_available_for_popping,
12631 required = regs_to_pop;
12632 required != 0 && available != 0;
12633 available &= ~(available & - available),
12634 required &= ~(required & - required))
12637 /* If we have any popping registers left over, remove them. */
12639 regs_available_for_popping &= ~available;
12641 /* Otherwise if we need another popping register we can use
12642 the fourth argument register. */
12643 else if (pops_needed)
12645 /* If we have not found any free argument registers and
12646 reg a4 contains the return address, we must move it. */
12647 if (regs_available_for_popping == 0
12648 && reg_containing_return_addr == LAST_ARG_REGNUM)
12650 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12651 reg_containing_return_addr = LR_REGNUM;
12653 else if (size > 12)
12655 /* Register a4 is being used to hold part of the return value,
12656 but we have dire need of a free, low register. */
12659 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12662 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12664 /* The fourth argument register is available. */
12665 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12671 /* Pop as many registers as we can. */
12672 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12673 regs_available_for_popping);
12675 /* Process the registers we popped. */
12676 if (reg_containing_return_addr == -1)
12678 /* The return address was popped into the lowest numbered register. */
12679 regs_to_pop &= ~(1 << LR_REGNUM);
12681 reg_containing_return_addr =
12682 number_of_first_bit_set (regs_available_for_popping);
12684 /* Remove this register for the mask of available registers, so that
12685 the return address will not be corrupted by further pops. */
12686 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12689 /* If we popped other registers then handle them here. */
12690 if (regs_available_for_popping)
12694 /* Work out which register currently contains the frame pointer. */
12695 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12697 /* Move it into the correct place. */
12698 asm_fprintf (f, "\tmov\t%r, %r\n",
12699 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12701 /* (Temporarily) remove it from the mask of popped registers. */
12702 regs_available_for_popping &= ~(1 << frame_pointer);
12703 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12705 if (regs_available_for_popping)
12709 /* We popped the stack pointer as well,
12710 find the register that contains it. */
12711 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12713 /* Move it into the stack register. */
12714 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12716 /* At this point we have popped all necessary registers, so
12717 do not worry about restoring regs_available_for_popping
12718 to its correct value:
12720 assert (pops_needed == 0)
12721 assert (regs_available_for_popping == (1 << frame_pointer))
12722 assert (regs_to_pop == (1 << STACK_POINTER)) */
12726 /* Since we have just move the popped value into the frame
12727 pointer, the popping register is available for reuse, and
12728 we know that we still have the stack pointer left to pop. */
12729 regs_available_for_popping |= (1 << frame_pointer);
12733 /* If we still have registers left on the stack, but we no longer have
12734 any registers into which we can pop them, then we must move the return
12735 address into the link register and make available the register that
12737 if (regs_available_for_popping == 0 && pops_needed > 0)
12739 regs_available_for_popping |= 1 << reg_containing_return_addr;
12741 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12742 reg_containing_return_addr);
12744 reg_containing_return_addr = LR_REGNUM;
12747 /* If we have registers left on the stack then pop some more.
12748 We know that at most we will want to pop FP and SP. */
12749 if (pops_needed > 0)
12754 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12755 regs_available_for_popping);
12757 /* We have popped either FP or SP.
12758 Move whichever one it is into the correct register. */
12759 popped_into = number_of_first_bit_set (regs_available_for_popping);
12760 move_to = number_of_first_bit_set (regs_to_pop);
12762 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12764 regs_to_pop &= ~(1 << move_to);
12769 /* If we still have not popped everything then we must have only
12770 had one register available to us and we are now popping the SP. */
12771 if (pops_needed > 0)
12775 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12776 regs_available_for_popping);
12778 popped_into = number_of_first_bit_set (regs_available_for_popping);
12780 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12782 assert (regs_to_pop == (1 << STACK_POINTER))
12783 assert (pops_needed == 1)
12787 /* If necessary restore the a4 register. */
12790 if (reg_containing_return_addr != LR_REGNUM)
12792 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12793 reg_containing_return_addr = LR_REGNUM;
12796 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12799 if (current_function_calls_eh_return)
12800 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12802 /* Return to caller. */
12803 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12808 thumb_final_prescan_insn (rtx insn)
12810 if (flag_print_asm_name)
12811 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12812 INSN_ADDRESSES (INSN_UID (insn)));
12816 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12818 unsigned HOST_WIDE_INT mask = 0xff;
12821 if (val == 0) /* XXX */
12824 for (i = 0; i < 25; i++)
12825 if ((val & (mask << i)) == val)
12831 /* Returns nonzero if the current function contains,
12832 or might contain a far jump. */
12834 thumb_far_jump_used_p (void)
12838 /* This test is only important for leaf functions. */
12839 /* assert (!leaf_function_p ()); */
12841 /* If we have already decided that far jumps may be used,
12842 do not bother checking again, and always return true even if
12843 it turns out that they are not being used. Once we have made
12844 the decision that far jumps are present (and that hence the link
12845 register will be pushed onto the stack) we cannot go back on it. */
12846 if (cfun->machine->far_jump_used)
12849 /* If this function is not being called from the prologue/epilogue
12850 generation code then it must be being called from the
12851 INITIAL_ELIMINATION_OFFSET macro. */
12852 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12854 /* In this case we know that we are being asked about the elimination
12855 of the arg pointer register. If that register is not being used,
12856 then there are no arguments on the stack, and we do not have to
12857 worry that a far jump might force the prologue to push the link
12858 register, changing the stack offsets. In this case we can just
12859 return false, since the presence of far jumps in the function will
12860 not affect stack offsets.
12862 If the arg pointer is live (or if it was live, but has now been
12863 eliminated and so set to dead) then we do have to test to see if
12864 the function might contain a far jump. This test can lead to some
12865 false negatives, since before reload is completed, then length of
12866 branch instructions is not known, so gcc defaults to returning their
12867 longest length, which in turn sets the far jump attribute to true.
12869 A false negative will not result in bad code being generated, but it
12870 will result in a needless push and pop of the link register. We
12871 hope that this does not occur too often.
12873 If we need doubleword stack alignment this could affect the other
12874 elimination offsets so we can't risk getting it wrong. */
12875 if (regs_ever_live [ARG_POINTER_REGNUM])
12876 cfun->machine->arg_pointer_live = 1;
12877 else if (!cfun->machine->arg_pointer_live)
12881 /* Check to see if the function contains a branch
12882 insn with the far jump attribute set. */
12883 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12885 if (GET_CODE (insn) == JUMP_INSN
12886 /* Ignore tablejump patterns. */
12887 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12888 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12889 && get_attr_far_jump (insn) == FAR_JUMP_YES
12892 /* Record the fact that we have decided that
12893 the function does use far jumps. */
12894 cfun->machine->far_jump_used = 1;
12902 /* Return nonzero if FUNC must be entered in ARM mode. */
12904 is_called_in_ARM_mode (tree func)
12906 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
12908 /* Ignore the problem about functions whose address is taken. */
12909 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12913 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12919 /* The bits which aren't usefully expanded as rtl. */
12921 thumb_unexpanded_epilogue (void)
12924 unsigned long live_regs_mask = 0;
12925 int high_regs_pushed = 0;
12926 int had_to_push_lr;
12929 if (return_used_this_function)
12932 if (IS_NAKED (arm_current_func_type ()))
12935 live_regs_mask = thumb_compute_save_reg_mask ();
12936 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
12938 /* If we can deduce the registers used from the function's return value.
12939 This is more reliable that examining regs_ever_live[] because that
12940 will be set if the register is ever used in the function, not just if
12941 the register is used to hold a return value. */
12942 size = arm_size_return_regs ();
12944 /* The prolog may have pushed some high registers to use as
12945 work registers. e.g. the testsuite file:
12946 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12947 compiles to produce:
12948 push {r4, r5, r6, r7, lr}
12952 as part of the prolog. We have to undo that pushing here. */
12954 if (high_regs_pushed)
12956 unsigned long mask = live_regs_mask & 0xff;
12959 /* The available low registers depend on the size of the value we are
12967 /* Oh dear! We have no low registers into which we can pop
12970 ("no low registers available for popping high registers");
12972 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12973 if (live_regs_mask & (1 << next_hi_reg))
12976 while (high_regs_pushed)
12978 /* Find lo register(s) into which the high register(s) can
12980 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12982 if (mask & (1 << regno))
12983 high_regs_pushed--;
12984 if (high_regs_pushed == 0)
12988 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12990 /* Pop the values into the low register(s). */
12991 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12993 /* Move the value(s) into the high registers. */
12994 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12996 if (mask & (1 << regno))
12998 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13001 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13002 if (live_regs_mask & (1 << next_hi_reg))
13007 live_regs_mask &= ~0x0f00;
13010 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13011 live_regs_mask &= 0xff;
13013 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13015 /* Pop the return address into the PC. */
13016 if (had_to_push_lr)
13017 live_regs_mask |= 1 << PC_REGNUM;
13019 /* Either no argument registers were pushed or a backtrace
13020 structure was created which includes an adjusted stack
13021 pointer, so just pop everything. */
13022 if (live_regs_mask)
13023 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13026 /* We have either just popped the return address into the
13027 PC or it is was kept in LR for the entire function. */
13028 if (!had_to_push_lr)
13029 thumb_exit (asm_out_file, LR_REGNUM);
13033 /* Pop everything but the return address. */
13034 if (live_regs_mask)
13035 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13038 if (had_to_push_lr)
13042 /* We have no free low regs, so save one. */
13043 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13047 /* Get the return address into a temporary register. */
13048 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13049 1 << LAST_ARG_REGNUM);
13053 /* Move the return address to lr. */
13054 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13056 /* Restore the low register. */
13057 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13062 regno = LAST_ARG_REGNUM;
13067 /* Remove the argument registers that were pushed onto the stack. */
13068 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13069 SP_REGNUM, SP_REGNUM,
13070 current_function_pretend_args_size);
13072 thumb_exit (asm_out_file, regno);
13078 /* Functions to save and restore machine-specific function data. */
13079 static struct machine_function *
13080 arm_init_machine_status (void)
13082 struct machine_function *machine;
13083 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13085 #if ARM_FT_UNKNOWN != 0
13086 machine->func_type = ARM_FT_UNKNOWN;
13091 /* Return an RTX indicating where the return address to the
13092 calling function can be found. */
13094 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13099 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13102 /* Do anything needed before RTL is emitted for each function. */
13104 arm_init_expanders (void)
13106 /* Arrange to initialize and mark the machine per-function status. */
13107 init_machine_status = arm_init_machine_status;
13109 /* This is to stop the combine pass optimizing away the alignment
13110 adjustment of va_arg. */
13111 /* ??? It is claimed that this should not be necessary. */
13113 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13117 /* Like arm_compute_initial_elimination offset. Simpler because
13118 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13121 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13123 arm_stack_offsets *offsets;
13125 offsets = arm_get_frame_offsets ();
13129 case ARG_POINTER_REGNUM:
13132 case STACK_POINTER_REGNUM:
13133 return offsets->outgoing_args - offsets->saved_args;
13135 case FRAME_POINTER_REGNUM:
13136 return offsets->soft_frame - offsets->saved_args;
13138 case THUMB_HARD_FRAME_POINTER_REGNUM:
13139 case ARM_HARD_FRAME_POINTER_REGNUM:
13140 return offsets->saved_regs - offsets->saved_args;
13143 gcc_unreachable ();
13147 case FRAME_POINTER_REGNUM:
13150 case STACK_POINTER_REGNUM:
13151 return offsets->outgoing_args - offsets->soft_frame;
13153 case THUMB_HARD_FRAME_POINTER_REGNUM:
13154 case ARM_HARD_FRAME_POINTER_REGNUM:
13155 return offsets->saved_regs - offsets->soft_frame;
13158 gcc_unreachable ();
13163 gcc_unreachable ();
13168 /* Generate the rest of a function's prologue. */
13170 thumb_expand_prologue (void)
13174 HOST_WIDE_INT amount;
13175 arm_stack_offsets *offsets;
13176 unsigned long func_type;
13178 unsigned long live_regs_mask;
13180 func_type = arm_current_func_type ();
13182 /* Naked functions don't have prologues. */
13183 if (IS_NAKED (func_type))
13186 if (IS_INTERRUPT (func_type))
13188 error ("interrupt Service Routines cannot be coded in Thumb mode");
13192 live_regs_mask = thumb_compute_save_reg_mask ();
13193 /* Load the pic register before setting the frame pointer,
13194 so we can use r7 as a temporary work register. */
13196 arm_load_pic_register (thumb_find_work_register (live_regs_mask));
13198 offsets = arm_get_frame_offsets ();
13200 if (frame_pointer_needed)
13202 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13203 stack_pointer_rtx));
13204 RTX_FRAME_RELATED_P (insn) = 1;
13206 else if (CALLER_INTERWORKING_SLOT_SIZE > 0)
13207 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13208 stack_pointer_rtx);
13210 amount = offsets->outgoing_args - offsets->saved_regs;
13215 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13216 GEN_INT (- amount)));
13217 RTX_FRAME_RELATED_P (insn) = 1;
13223 /* The stack decrement is too big for an immediate value in a single
13224 insn. In theory we could issue multiple subtracts, but after
13225 three of them it becomes more space efficient to place the full
13226 value in the constant pool and load into a register. (Also the
13227 ARM debugger really likes to see only one stack decrement per
13228 function). So instead we look for a scratch register into which
13229 we can load the decrement, and then we subtract this from the
13230 stack pointer. Unfortunately on the thumb the only available
13231 scratch registers are the argument registers, and we cannot use
13232 these as they may hold arguments to the function. Instead we
13233 attempt to locate a call preserved register which is used by this
13234 function. If we can find one, then we know that it will have
13235 been pushed at the start of the prologue and so we can corrupt
13237 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13238 if (live_regs_mask & (1 << regno)
13239 && !(frame_pointer_needed
13240 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13243 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13245 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13247 /* Choose an arbitrary, non-argument low register. */
13248 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13250 /* Save it by copying it into a high, scratch register. */
13251 emit_insn (gen_movsi (spare, reg));
13252 /* Add a USE to stop propagate_one_insn() from barfing. */
13253 emit_insn (gen_prologue_use (spare));
13255 /* Decrement the stack. */
13256 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13257 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13258 stack_pointer_rtx, reg));
13259 RTX_FRAME_RELATED_P (insn) = 1;
13260 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13261 plus_constant (stack_pointer_rtx,
13263 RTX_FRAME_RELATED_P (dwarf) = 1;
13265 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13268 /* Restore the low register's original value. */
13269 emit_insn (gen_movsi (reg, spare));
13271 /* Emit a USE of the restored scratch register, so that flow
13272 analysis will not consider the restore redundant. The
13273 register won't be used again in this function and isn't
13274 restored by the epilogue. */
13275 emit_insn (gen_prologue_use (reg));
13279 reg = gen_rtx_REG (SImode, regno);
13281 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13283 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13284 stack_pointer_rtx, reg));
13285 RTX_FRAME_RELATED_P (insn) = 1;
13286 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13287 plus_constant (stack_pointer_rtx,
13289 RTX_FRAME_RELATED_P (dwarf) = 1;
13291 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13295 /* If the frame pointer is needed, emit a special barrier that
13296 will prevent the scheduler from moving stores to the frame
13297 before the stack adjustment. */
13298 if (frame_pointer_needed)
13299 emit_insn (gen_stack_tie (stack_pointer_rtx,
13300 hard_frame_pointer_rtx));
13303 if (current_function_profile || !TARGET_SCHED_PROLOG)
13304 emit_insn (gen_blockage ());
13306 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13307 if (live_regs_mask & 0xff)
13308 cfun->machine->lr_save_eliminated = 0;
13310 /* If the link register is being kept alive, with the return address in it,
13311 then make sure that it does not get reused by the ce2 pass. */
13312 if (cfun->machine->lr_save_eliminated)
13313 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13318 thumb_expand_epilogue (void)
13320 HOST_WIDE_INT amount;
13321 arm_stack_offsets *offsets;
13324 /* Naked functions don't have prologues. */
13325 if (IS_NAKED (arm_current_func_type ()))
13328 offsets = arm_get_frame_offsets ();
13329 amount = offsets->outgoing_args - offsets->saved_regs;
13331 if (frame_pointer_needed)
13332 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13336 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13337 GEN_INT (amount)));
13340 /* r3 is always free in the epilogue. */
13341 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13343 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13344 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13348 /* Emit a USE (stack_pointer_rtx), so that
13349 the stack adjustment will not be deleted. */
13350 emit_insn (gen_prologue_use (stack_pointer_rtx));
13352 if (current_function_profile || !TARGET_SCHED_PROLOG)
13353 emit_insn (gen_blockage ());
13355 /* Emit a clobber for each insn that will be restored in the epilogue,
13356 so that flow2 will get register lifetimes correct. */
13357 for (regno = 0; regno < 13; regno++)
13358 if (regs_ever_live[regno] && !call_used_regs[regno])
13359 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13361 if (! regs_ever_live[LR_REGNUM])
13362 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13366 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13368 unsigned long live_regs_mask = 0;
13369 unsigned long l_mask;
13370 unsigned high_regs_pushed = 0;
13371 int cfa_offset = 0;
13374 if (IS_NAKED (arm_current_func_type ()))
13377 if (is_called_in_ARM_mode (current_function_decl))
13381 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
13382 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
13384 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13386 /* Generate code sequence to switch us into Thumb mode. */
13387 /* The .code 32 directive has already been emitted by
13388 ASM_DECLARE_FUNCTION_NAME. */
13389 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13390 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13392 /* Generate a label, so that the debugger will notice the
13393 change in instruction sets. This label is also used by
13394 the assembler to bypass the ARM code when this function
13395 is called from a Thumb encoded function elsewhere in the
13396 same file. Hence the definition of STUB_NAME here must
13397 agree with the definition in gas/config/tc-arm.c. */
13399 #define STUB_NAME ".real_start_of"
13401 fprintf (f, "\t.code\t16\n");
13403 if (arm_dllexport_name_p (name))
13404 name = arm_strip_name_encoding (name);
13406 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13407 fprintf (f, "\t.thumb_func\n");
13408 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13411 if (current_function_pretend_args_size)
13413 /* Output unwind directive for the stack adjustment. */
13414 if (ARM_EABI_UNWIND_TABLES)
13415 fprintf (f, "\t.pad #%d\n",
13416 current_function_pretend_args_size);
13418 if (cfun->machine->uses_anonymous_args)
13422 fprintf (f, "\tpush\t{");
13424 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13426 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13427 regno <= LAST_ARG_REGNUM;
13429 asm_fprintf (f, "%r%s", regno,
13430 regno == LAST_ARG_REGNUM ? "" : ", ");
13432 fprintf (f, "}\n");
13435 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13436 SP_REGNUM, SP_REGNUM,
13437 current_function_pretend_args_size);
13439 /* We don't need to record the stores for unwinding (would it
13440 help the debugger any if we did?), but record the change in
13441 the stack pointer. */
13442 if (dwarf2out_do_frame ())
13444 char *l = dwarf2out_cfi_label ();
13446 cfa_offset = cfa_offset + current_function_pretend_args_size;
13447 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13451 /* Get the registers we are going to push. */
13452 live_regs_mask = thumb_compute_save_reg_mask ();
13453 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13454 l_mask = live_regs_mask & 0x40ff;
13455 /* Then count how many other high registers will need to be pushed. */
13456 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13458 if (TARGET_BACKTRACE)
13461 unsigned work_register;
13463 /* We have been asked to create a stack backtrace structure.
13464 The code looks like this:
13468 0 sub SP, #16 Reserve space for 4 registers.
13469 2 push {R7} Push low registers.
13470 4 add R7, SP, #20 Get the stack pointer before the push.
13471 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13472 8 mov R7, PC Get hold of the start of this code plus 12.
13473 10 str R7, [SP, #16] Store it.
13474 12 mov R7, FP Get hold of the current frame pointer.
13475 14 str R7, [SP, #4] Store it.
13476 16 mov R7, LR Get hold of the current return address.
13477 18 str R7, [SP, #12] Store it.
13478 20 add R7, SP, #16 Point at the start of the backtrace structure.
13479 22 mov FP, R7 Put this value into the frame pointer. */
13481 work_register = thumb_find_work_register (live_regs_mask);
13483 if (ARM_EABI_UNWIND_TABLES)
13484 asm_fprintf (f, "\t.pad #16\n");
13487 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13488 SP_REGNUM, SP_REGNUM);
13490 if (dwarf2out_do_frame ())
13492 char *l = dwarf2out_cfi_label ();
13494 cfa_offset = cfa_offset + 16;
13495 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13500 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13501 offset = bit_count (l_mask) * UNITS_PER_WORD;
13506 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13507 offset + 16 + current_function_pretend_args_size);
13509 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13512 /* Make sure that the instruction fetching the PC is in the right place
13513 to calculate "start of backtrace creation code + 12". */
13516 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13517 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13519 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13520 ARM_HARD_FRAME_POINTER_REGNUM);
13521 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13526 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13527 ARM_HARD_FRAME_POINTER_REGNUM);
13528 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13530 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13531 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13535 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13536 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13538 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13540 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13541 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13543 /* Optimization: If we are not pushing any low registers but we are going
13544 to push some high registers then delay our first push. This will just
13545 be a push of LR and we can combine it with the push of the first high
13547 else if ((l_mask & 0xff) != 0
13548 || (high_regs_pushed == 0 && l_mask))
13549 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13551 if (high_regs_pushed)
13553 unsigned pushable_regs;
13554 unsigned next_hi_reg;
13556 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13557 if (live_regs_mask & (1 << next_hi_reg))
13560 pushable_regs = l_mask & 0xff;
13562 if (pushable_regs == 0)
13563 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13565 while (high_regs_pushed > 0)
13567 unsigned long real_regs_mask = 0;
13569 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
13571 if (pushable_regs & (1 << regno))
13573 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13575 high_regs_pushed --;
13576 real_regs_mask |= (1 << next_hi_reg);
13578 if (high_regs_pushed)
13580 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
13582 if (live_regs_mask & (1 << next_hi_reg))
13587 pushable_regs &= ~((1 << regno) - 1);
13593 /* If we had to find a work register and we have not yet
13594 saved the LR then add it to the list of regs to push. */
13595 if (l_mask == (1 << LR_REGNUM))
13597 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
13599 real_regs_mask | (1 << LR_REGNUM));
13603 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13608 /* Handle the case of a double word load into a low register from
13609 a computed memory address. The computed address may involve a
13610 register which is overwritten by the load. */
13612 thumb_load_double_from_address (rtx *operands)
13620 gcc_assert (GET_CODE (operands[0]) == REG);
13621 gcc_assert (GET_CODE (operands[1]) == MEM);
13623 /* Get the memory address. */
13624 addr = XEXP (operands[1], 0);
13626 /* Work out how the memory address is computed. */
13627 switch (GET_CODE (addr))
13630 operands[2] = gen_rtx_MEM (SImode,
13631 plus_constant (XEXP (operands[1], 0), 4));
13633 if (REGNO (operands[0]) == REGNO (addr))
13635 output_asm_insn ("ldr\t%H0, %2", operands);
13636 output_asm_insn ("ldr\t%0, %1", operands);
13640 output_asm_insn ("ldr\t%0, %1", operands);
13641 output_asm_insn ("ldr\t%H0, %2", operands);
13646 /* Compute <address> + 4 for the high order load. */
13647 operands[2] = gen_rtx_MEM (SImode,
13648 plus_constant (XEXP (operands[1], 0), 4));
13650 output_asm_insn ("ldr\t%0, %1", operands);
13651 output_asm_insn ("ldr\t%H0, %2", operands);
13655 arg1 = XEXP (addr, 0);
13656 arg2 = XEXP (addr, 1);
13658 if (CONSTANT_P (arg1))
13659 base = arg2, offset = arg1;
13661 base = arg1, offset = arg2;
13663 gcc_assert (GET_CODE (base) == REG);
13665 /* Catch the case of <address> = <reg> + <reg> */
13666 if (GET_CODE (offset) == REG)
13668 int reg_offset = REGNO (offset);
13669 int reg_base = REGNO (base);
13670 int reg_dest = REGNO (operands[0]);
13672 /* Add the base and offset registers together into the
13673 higher destination register. */
13674 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13675 reg_dest + 1, reg_base, reg_offset);
13677 /* Load the lower destination register from the address in
13678 the higher destination register. */
13679 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13680 reg_dest, reg_dest + 1);
13682 /* Load the higher destination register from its own address
13684 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13685 reg_dest + 1, reg_dest + 1);
13689 /* Compute <address> + 4 for the high order load. */
13690 operands[2] = gen_rtx_MEM (SImode,
13691 plus_constant (XEXP (operands[1], 0), 4));
13693 /* If the computed address is held in the low order register
13694 then load the high order register first, otherwise always
13695 load the low order register first. */
13696 if (REGNO (operands[0]) == REGNO (base))
13698 output_asm_insn ("ldr\t%H0, %2", operands);
13699 output_asm_insn ("ldr\t%0, %1", operands);
13703 output_asm_insn ("ldr\t%0, %1", operands);
13704 output_asm_insn ("ldr\t%H0, %2", operands);
13710 /* With no registers to worry about we can just load the value
13712 operands[2] = gen_rtx_MEM (SImode,
13713 plus_constant (XEXP (operands[1], 0), 4));
13715 output_asm_insn ("ldr\t%H0, %2", operands);
13716 output_asm_insn ("ldr\t%0, %1", operands);
13720 gcc_unreachable ();
13727 thumb_output_move_mem_multiple (int n, rtx *operands)
13734 if (REGNO (operands[4]) > REGNO (operands[5]))
13737 operands[4] = operands[5];
13740 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13741 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13745 if (REGNO (operands[4]) > REGNO (operands[5]))
13748 operands[4] = operands[5];
13751 if (REGNO (operands[5]) > REGNO (operands[6]))
13754 operands[5] = operands[6];
13757 if (REGNO (operands[4]) > REGNO (operands[5]))
13760 operands[4] = operands[5];
13764 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13765 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13769 gcc_unreachable ();
13775 /* Output a call-via instruction for thumb state. */
13777 thumb_call_via_reg (rtx reg)
13779 int regno = REGNO (reg);
13782 gcc_assert (regno < LR_REGNUM);
13784 /* If we are in the normal text section we can use a single instance
13785 per compilation unit. If we are doing function sections, then we need
13786 an entry per section, since we can't rely on reachability. */
13787 if (in_text_section ())
13789 thumb_call_reg_needed = 1;
13791 if (thumb_call_via_label[regno] == NULL)
13792 thumb_call_via_label[regno] = gen_label_rtx ();
13793 labelp = thumb_call_via_label + regno;
13797 if (cfun->machine->call_via[regno] == NULL)
13798 cfun->machine->call_via[regno] = gen_label_rtx ();
13799 labelp = cfun->machine->call_via + regno;
13802 output_asm_insn ("bl\t%a0", labelp);
13806 /* Routines for generating rtl. */
13808 thumb_expand_movmemqi (rtx *operands)
13810 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13811 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13812 HOST_WIDE_INT len = INTVAL (operands[2]);
13813 HOST_WIDE_INT offset = 0;
13817 emit_insn (gen_movmem12b (out, in, out, in));
13823 emit_insn (gen_movmem8b (out, in, out, in));
13829 rtx reg = gen_reg_rtx (SImode);
13830 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13831 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13838 rtx reg = gen_reg_rtx (HImode);
13839 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13840 plus_constant (in, offset))));
13841 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13849 rtx reg = gen_reg_rtx (QImode);
13850 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13851 plus_constant (in, offset))));
13852 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13858 thumb_reload_out_hi (rtx *operands)
13860 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13863 /* Handle reading a half-word from memory during reload. */
13865 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13867 gcc_unreachable ();
13870 /* Return the length of a function name prefix
13871 that starts with the character 'c'. */
13873 arm_get_strip_length (int c)
13877 ARM_NAME_ENCODING_LENGTHS
13882 /* Return a pointer to a function's name with any
13883 and all prefix encodings stripped from it. */
13885 arm_strip_name_encoding (const char *name)
13889 while ((skip = arm_get_strip_length (* name)))
13895 /* If there is a '*' anywhere in the name's prefix, then
13896 emit the stripped name verbatim, otherwise prepend an
13897 underscore if leading underscores are being used. */
13899 arm_asm_output_labelref (FILE *stream, const char *name)
13904 while ((skip = arm_get_strip_length (* name)))
13906 verbatim |= (*name == '*');
13911 fputs (name, stream);
13913 asm_fprintf (stream, "%U%s", name);
13917 arm_file_end (void)
13921 if (! thumb_call_reg_needed)
13925 asm_fprintf (asm_out_file, "\t.code 16\n");
13926 ASM_OUTPUT_ALIGN (asm_out_file, 1);
13928 for (regno = 0; regno < LR_REGNUM; regno++)
13930 rtx label = thumb_call_via_label[regno];
13934 targetm.asm_out.internal_label (asm_out_file, "L",
13935 CODE_LABEL_NUMBER (label));
13936 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
13943 #ifdef AOF_ASSEMBLER
13944 /* Special functions only needed when producing AOF syntax assembler. */
13948 struct pic_chain * next;
13949 const char * symname;
13952 static struct pic_chain * aof_pic_chain = NULL;
13955 aof_pic_entry (rtx x)
13957 struct pic_chain ** chainp;
13960 if (aof_pic_label == NULL_RTX)
13962 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13965 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13966 offset += 4, chainp = &(*chainp)->next)
13967 if ((*chainp)->symname == XSTR (x, 0))
13968 return plus_constant (aof_pic_label, offset);
13970 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13971 (*chainp)->next = NULL;
13972 (*chainp)->symname = XSTR (x, 0);
13973 return plus_constant (aof_pic_label, offset);
13977 aof_dump_pic_table (FILE *f)
13979 struct pic_chain * chain;
13981 if (aof_pic_chain == NULL)
13984 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13985 PIC_OFFSET_TABLE_REGNUM,
13986 PIC_OFFSET_TABLE_REGNUM);
13987 fputs ("|x$adcons|\n", f);
13989 for (chain = aof_pic_chain; chain; chain = chain->next)
13991 fputs ("\tDCD\t", f);
13992 assemble_name (f, chain->symname);
13997 int arm_text_section_count = 1;
14000 aof_text_section (void )
14002 static char buf[100];
14003 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14004 arm_text_section_count++);
14006 strcat (buf, ", PIC, REENTRANT");
14010 static int arm_data_section_count = 1;
14013 aof_data_section (void)
14015 static char buf[100];
14016 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14020 /* The AOF assembler is religiously strict about declarations of
14021 imported and exported symbols, so that it is impossible to declare
14022 a function as imported near the beginning of the file, and then to
14023 export it later on. It is, however, possible to delay the decision
14024 until all the functions in the file have been compiled. To get
14025 around this, we maintain a list of the imports and exports, and
14026 delete from it any that are subsequently defined. At the end of
14027 compilation we spit the remainder of the list out before the END
14032 struct import * next;
14036 static struct import * imports_list = NULL;
14039 aof_add_import (const char *name)
14041 struct import * new;
14043 for (new = imports_list; new; new = new->next)
14044 if (new->name == name)
14047 new = (struct import *) xmalloc (sizeof (struct import));
14048 new->next = imports_list;
14049 imports_list = new;
14054 aof_delete_import (const char *name)
14056 struct import ** old;
14058 for (old = &imports_list; *old; old = & (*old)->next)
14060 if ((*old)->name == name)
14062 *old = (*old)->next;
14068 int arm_main_function = 0;
14071 aof_dump_imports (FILE *f)
14073 /* The AOF assembler needs this to cause the startup code to be extracted
14074 from the library. Brining in __main causes the whole thing to work
14076 if (arm_main_function)
14079 fputs ("\tIMPORT __main\n", f);
14080 fputs ("\tDCD __main\n", f);
14083 /* Now dump the remaining imports. */
14084 while (imports_list)
14086 fprintf (f, "\tIMPORT\t");
14087 assemble_name (f, imports_list->name);
14089 imports_list = imports_list->next;
14094 aof_globalize_label (FILE *stream, const char *name)
14096 default_globalize_label (stream, name);
14097 if (! strcmp (name, "main"))
14098 arm_main_function = 1;
14102 aof_file_start (void)
14104 fputs ("__r0\tRN\t0\n", asm_out_file);
14105 fputs ("__a1\tRN\t0\n", asm_out_file);
14106 fputs ("__a2\tRN\t1\n", asm_out_file);
14107 fputs ("__a3\tRN\t2\n", asm_out_file);
14108 fputs ("__a4\tRN\t3\n", asm_out_file);
14109 fputs ("__v1\tRN\t4\n", asm_out_file);
14110 fputs ("__v2\tRN\t5\n", asm_out_file);
14111 fputs ("__v3\tRN\t6\n", asm_out_file);
14112 fputs ("__v4\tRN\t7\n", asm_out_file);
14113 fputs ("__v5\tRN\t8\n", asm_out_file);
14114 fputs ("__v6\tRN\t9\n", asm_out_file);
14115 fputs ("__sl\tRN\t10\n", asm_out_file);
14116 fputs ("__fp\tRN\t11\n", asm_out_file);
14117 fputs ("__ip\tRN\t12\n", asm_out_file);
14118 fputs ("__sp\tRN\t13\n", asm_out_file);
14119 fputs ("__lr\tRN\t14\n", asm_out_file);
14120 fputs ("__pc\tRN\t15\n", asm_out_file);
14121 fputs ("__f0\tFN\t0\n", asm_out_file);
14122 fputs ("__f1\tFN\t1\n", asm_out_file);
14123 fputs ("__f2\tFN\t2\n", asm_out_file);
14124 fputs ("__f3\tFN\t3\n", asm_out_file);
14125 fputs ("__f4\tFN\t4\n", asm_out_file);
14126 fputs ("__f5\tFN\t5\n", asm_out_file);
14127 fputs ("__f6\tFN\t6\n", asm_out_file);
14128 fputs ("__f7\tFN\t7\n", asm_out_file);
14133 aof_file_end (void)
14136 aof_dump_pic_table (asm_out_file);
14138 aof_dump_imports (asm_out_file);
14139 fputs ("\tEND\n", asm_out_file);
14141 #endif /* AOF_ASSEMBLER */
14144 /* Symbols in the text segment can be accessed without indirecting via the
14145 constant pool; it may take an extra binary operation, but this is still
14146 faster than indirecting via memory. Don't do this when not optimizing,
14147 since we won't be calculating al of the offsets necessary to do this
14151 arm_encode_section_info (tree decl, rtx rtl, int first)
14153 /* This doesn't work with AOF syntax, since the string table may be in
14154 a different AREA. */
14155 #ifndef AOF_ASSEMBLER
14156 if (optimize > 0 && TREE_CONSTANT (decl))
14157 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14160 /* If we are referencing a function that is weak then encode a long call
14161 flag in the function name, otherwise if the function is static or
14162 or known to be defined in this file then encode a short call flag. */
14163 if (first && DECL_P (decl))
14165 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14166 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14167 else if (! TREE_PUBLIC (decl))
14168 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14171 #endif /* !ARM_PE */
14174 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14176 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14177 && !strcmp (prefix, "L"))
14179 arm_ccfsm_state = 0;
14180 arm_target_insn = NULL;
14182 default_internal_label (stream, prefix, labelno);
14185 /* Output code to add DELTA to the first argument, and then jump
14186 to FUNCTION. Used for C++ multiple inheritance. */
14188 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14189 HOST_WIDE_INT delta,
14190 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14193 static int thunk_label = 0;
14195 int mi_delta = delta;
14196 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14198 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14201 mi_delta = - mi_delta;
14204 int labelno = thunk_label++;
14205 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14206 fputs ("\tldr\tr12, ", file);
14207 assemble_name (file, label);
14208 fputc ('\n', file);
14210 while (mi_delta != 0)
14212 if ((mi_delta & (3 << shift)) == 0)
14216 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14217 mi_op, this_regno, this_regno,
14218 mi_delta & (0xff << shift));
14219 mi_delta &= ~(0xff << shift);
14225 fprintf (file, "\tbx\tr12\n");
14226 ASM_OUTPUT_ALIGN (file, 2);
14227 assemble_name (file, label);
14228 fputs (":\n", file);
14229 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14233 fputs ("\tb\t", file);
14234 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14235 if (NEED_PLT_RELOC)
14236 fputs ("(PLT)", file);
14237 fputc ('\n', file);
14242 arm_emit_vector_const (FILE *file, rtx x)
14245 const char * pattern;
14247 gcc_assert (GET_CODE (x) == CONST_VECTOR);
14249 switch (GET_MODE (x))
14251 case V2SImode: pattern = "%08x"; break;
14252 case V4HImode: pattern = "%04x"; break;
14253 case V8QImode: pattern = "%02x"; break;
14254 default: gcc_unreachable ();
14257 fprintf (file, "0x");
14258 for (i = CONST_VECTOR_NUNITS (x); i--;)
14262 element = CONST_VECTOR_ELT (x, i);
14263 fprintf (file, pattern, INTVAL (element));
14270 arm_output_load_gr (rtx *operands)
14277 if (GET_CODE (operands [1]) != MEM
14278 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14279 || GET_CODE (reg = XEXP (sum, 0)) != REG
14280 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14281 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14282 return "wldrw%?\t%0, %1";
14284 /* Fix up an out-of-range load of a GR register. */
14285 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14286 wcgr = operands[0];
14288 output_asm_insn ("ldr%?\t%0, %1", operands);
14290 operands[0] = wcgr;
14292 output_asm_insn ("tmcr%?\t%0, %1", operands);
14293 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14299 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14300 int incoming ATTRIBUTE_UNUSED)
14303 /* FIXME: The ARM backend has special code to handle structure
14304 returns, and will reserve its own hidden first argument. So
14305 if this macro is enabled a *second* hidden argument will be
14306 reserved, which will break binary compatibility with old
14307 toolchains and also thunk handling. One day this should be
14311 /* Register in which address to store a structure value
14312 is passed to a function. */
14313 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14317 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14319 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14320 named arg and all anonymous args onto the stack.
14321 XXX I know the prologue shouldn't be pushing registers, but it is faster
14325 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14326 enum machine_mode mode ATTRIBUTE_UNUSED,
14327 tree type ATTRIBUTE_UNUSED,
14329 int second_time ATTRIBUTE_UNUSED)
14331 cfun->machine->uses_anonymous_args = 1;
14332 if (cum->nregs < NUM_ARG_REGS)
14333 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14336 /* Return nonzero if the CONSUMER instruction (a store) does not need
14337 PRODUCER's value to calculate the address. */
14340 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14342 rtx value = PATTERN (producer);
14343 rtx addr = PATTERN (consumer);
14345 if (GET_CODE (value) == COND_EXEC)
14346 value = COND_EXEC_CODE (value);
14347 if (GET_CODE (value) == PARALLEL)
14348 value = XVECEXP (value, 0, 0);
14349 value = XEXP (value, 0);
14350 if (GET_CODE (addr) == COND_EXEC)
14351 addr = COND_EXEC_CODE (addr);
14352 if (GET_CODE (addr) == PARALLEL)
14353 addr = XVECEXP (addr, 0, 0);
14354 addr = XEXP (addr, 0);
14356 return !reg_overlap_mentioned_p (value, addr);
14359 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14360 have an early register shift value or amount dependency on the
14361 result of PRODUCER. */
14364 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14366 rtx value = PATTERN (producer);
14367 rtx op = PATTERN (consumer);
14370 if (GET_CODE (value) == COND_EXEC)
14371 value = COND_EXEC_CODE (value);
14372 if (GET_CODE (value) == PARALLEL)
14373 value = XVECEXP (value, 0, 0);
14374 value = XEXP (value, 0);
14375 if (GET_CODE (op) == COND_EXEC)
14376 op = COND_EXEC_CODE (op);
14377 if (GET_CODE (op) == PARALLEL)
14378 op = XVECEXP (op, 0, 0);
14381 early_op = XEXP (op, 0);
14382 /* This is either an actual independent shift, or a shift applied to
14383 the first operand of another operation. We want the whole shift
14385 if (GET_CODE (early_op) == REG)
14388 return !reg_overlap_mentioned_p (value, early_op);
14391 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14392 have an early register shift value dependency on the result of
14396 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14398 rtx value = PATTERN (producer);
14399 rtx op = PATTERN (consumer);
14402 if (GET_CODE (value) == COND_EXEC)
14403 value = COND_EXEC_CODE (value);
14404 if (GET_CODE (value) == PARALLEL)
14405 value = XVECEXP (value, 0, 0);
14406 value = XEXP (value, 0);
14407 if (GET_CODE (op) == COND_EXEC)
14408 op = COND_EXEC_CODE (op);
14409 if (GET_CODE (op) == PARALLEL)
14410 op = XVECEXP (op, 0, 0);
14413 early_op = XEXP (op, 0);
14415 /* This is either an actual independent shift, or a shift applied to
14416 the first operand of another operation. We want the value being
14417 shifted, in either case. */
14418 if (GET_CODE (early_op) != REG)
14419 early_op = XEXP (early_op, 0);
14421 return !reg_overlap_mentioned_p (value, early_op);
14424 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14425 have an early register mult dependency on the result of
14429 arm_no_early_mul_dep (rtx producer, rtx consumer)
14431 rtx value = PATTERN (producer);
14432 rtx op = PATTERN (consumer);
14434 if (GET_CODE (value) == COND_EXEC)
14435 value = COND_EXEC_CODE (value);
14436 if (GET_CODE (value) == PARALLEL)
14437 value = XVECEXP (value, 0, 0);
14438 value = XEXP (value, 0);
14439 if (GET_CODE (op) == COND_EXEC)
14440 op = COND_EXEC_CODE (op);
14441 if (GET_CODE (op) == PARALLEL)
14442 op = XVECEXP (op, 0, 0);
14445 return (GET_CODE (op) == PLUS
14446 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14450 /* We can't rely on the caller doing the proper promotion when
14451 using APCS or ATPCS. */
14454 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14456 return !TARGET_AAPCS_BASED;
14460 /* AAPCS based ABIs use short enums by default. */
14463 arm_default_short_enums (void)
14465 return TARGET_AAPCS_BASED;
14469 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14472 arm_align_anon_bitfield (void)
14474 return TARGET_AAPCS_BASED;
14478 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14481 arm_cxx_guard_type (void)
14483 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14487 /* The EABI says test the least significant bit of a guard variable. */
14490 arm_cxx_guard_mask_bit (void)
14492 return TARGET_AAPCS_BASED;
14496 /* The EABI specifies that all array cookies are 8 bytes long. */
14499 arm_get_cookie_size (tree type)
14503 if (!TARGET_AAPCS_BASED)
14504 return default_cxx_get_cookie_size (type);
14506 size = build_int_cst (sizetype, 8);
14511 /* The EABI says that array cookies should also contain the element size. */
14514 arm_cookie_has_size (void)
14516 return TARGET_AAPCS_BASED;
14520 /* The EABI says constructors and destructors should return a pointer to
14521 the object constructed/destroyed. */
14524 arm_cxx_cdtor_returns_this (void)
14526 return TARGET_AAPCS_BASED;
14529 /* The EABI says that an inline function may never be the key
14533 arm_cxx_key_method_may_be_inline (void)
14535 return !TARGET_AAPCS_BASED;
14539 arm_cxx_determine_class_data_visibility (tree decl)
14541 if (!TARGET_AAPCS_BASED)
14544 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14545 is exported. However, on systems without dynamic vague linkage,
14546 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14547 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
14548 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
14550 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
14551 DECL_VISIBILITY_SPECIFIED (decl) = 1;
14555 arm_cxx_class_data_always_comdat (void)
14557 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14558 vague linkage if the class has no key function. */
14559 return !TARGET_AAPCS_BASED;
14563 /* The EABI says __aeabi_atexit should be used to register static
14567 arm_cxx_use_aeabi_atexit (void)
14569 return TARGET_AAPCS_BASED;
14574 arm_set_return_address (rtx source, rtx scratch)
14576 arm_stack_offsets *offsets;
14577 HOST_WIDE_INT delta;
14579 unsigned long saved_regs;
14581 saved_regs = arm_compute_save_reg_mask ();
14583 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14584 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14587 if (frame_pointer_needed)
14588 addr = plus_constant(hard_frame_pointer_rtx, -4);
14591 /* LR will be the first saved register. */
14592 offsets = arm_get_frame_offsets ();
14593 delta = offsets->outgoing_args - (offsets->frame + 4);
14598 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14599 GEN_INT (delta & ~4095)));
14604 addr = stack_pointer_rtx;
14606 addr = plus_constant (addr, delta);
14608 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14614 thumb_set_return_address (rtx source, rtx scratch)
14616 arm_stack_offsets *offsets;
14617 HOST_WIDE_INT delta;
14620 unsigned long mask;
14622 emit_insn (gen_rtx_USE (VOIDmode, source));
14624 mask = thumb_compute_save_reg_mask ();
14625 if (mask & (1 << LR_REGNUM))
14627 offsets = arm_get_frame_offsets ();
14629 /* Find the saved regs. */
14630 if (frame_pointer_needed)
14632 delta = offsets->soft_frame - offsets->saved_args;
14633 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14637 delta = offsets->outgoing_args - offsets->saved_args;
14640 /* Allow for the stack frame. */
14641 if (TARGET_BACKTRACE)
14643 /* The link register is always the first saved register. */
14646 /* Construct the address. */
14647 addr = gen_rtx_REG (SImode, reg);
14648 if ((reg != SP_REGNUM && delta >= 128)
14651 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14652 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14656 addr = plus_constant (addr, delta);
14658 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14661 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14664 /* Implements target hook vector_mode_supported_p. */
14666 arm_vector_mode_supported_p (enum machine_mode mode)
14668 if ((mode == V2SImode)
14669 || (mode == V4HImode)
14670 || (mode == V8QImode))
14676 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14677 ARM insns and therefore guarantee that the shift count is modulo 256.
14678 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14679 guarantee no particular behavior for out-of-range counts. */
14681 static unsigned HOST_WIDE_INT
14682 arm_shift_truncation_mask (enum machine_mode mode)
14684 return mode == SImode ? 255 : 0;
14688 /* Map internal gcc register numbers to DWARF2 register numbers. */
14691 arm_dbx_register_number (unsigned int regno)
14696 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14697 compatibility. The EABI defines them as registers 96-103. */
14698 if (IS_FPA_REGNUM (regno))
14699 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
14701 if (IS_VFP_REGNUM (regno))
14702 return 64 + regno - FIRST_VFP_REGNUM;
14704 if (IS_IWMMXT_GR_REGNUM (regno))
14705 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
14707 if (IS_IWMMXT_REGNUM (regno))
14708 return 112 + regno - FIRST_IWMMXT_REGNUM;
14710 gcc_unreachable ();
14714 #ifdef TARGET_UNWIND_INFO
14715 /* Emit unwind directives for a store-multiple instruction. This should
14716 only ever be generated by the function prologue code, so we expect it
14717 to have a particular form. */
14720 arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
14723 HOST_WIDE_INT offset;
14724 HOST_WIDE_INT nregs;
14730 /* First insn will adjust the stack pointer. */
14731 e = XVECEXP (p, 0, 0);
14732 if (GET_CODE (e) != SET
14733 || GET_CODE (XEXP (e, 0)) != REG
14734 || REGNO (XEXP (e, 0)) != SP_REGNUM
14735 || GET_CODE (XEXP (e, 1)) != PLUS)
14738 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
14739 nregs = XVECLEN (p, 0) - 1;
14741 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
14744 /* The function prologue may also push pc, but not annotate it as it is
14745 never restored. We turn this into a stack pointer adjustment. */
14746 if (nregs * 4 == offset - 4)
14748 fprintf (asm_out_file, "\t.pad #4\n");
14753 else if (IS_VFP_REGNUM (reg))
14755 /* FPA register saves use an additional word. */
14759 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
14761 /* FPA registers are done differently. */
14762 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
14766 /* Unknown register type. */
14769 /* If the stack increment doesn't match the size of the saved registers,
14770 something has gone horribly wrong. */
14771 if (offset != nregs * reg_size)
14774 fprintf (asm_out_file, "\t.save {");
14778 /* The remaining insns will describe the stores. */
14779 for (i = 1; i <= nregs; i++)
14781 /* Expect (set (mem <addr>) (reg)).
14782 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
14783 e = XVECEXP (p, 0, i);
14784 if (GET_CODE (e) != SET
14785 || GET_CODE (XEXP (e, 0)) != MEM
14786 || GET_CODE (XEXP (e, 1)) != REG)
14789 reg = REGNO (XEXP (e, 1));
14794 fprintf (asm_out_file, ", ");
14795 /* We can't use %r for vfp because we need to use the
14796 double precision register names. */
14797 if (IS_VFP_REGNUM (reg))
14798 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
14800 asm_fprintf (asm_out_file, "%r", reg);
14802 #ifdef ENABLE_CHECKING
14803 /* Check that the addresses are consecutive. */
14804 e = XEXP (XEXP (e, 0), 0);
14805 if (GET_CODE (e) == PLUS)
14807 offset += reg_size;
14808 if (GET_CODE (XEXP (e, 0)) != REG
14809 || REGNO (XEXP (e, 0)) != SP_REGNUM
14810 || GET_CODE (XEXP (e, 1)) != CONST_INT
14811 || offset != INTVAL (XEXP (e, 1)))
14815 || GET_CODE (e) != REG
14816 || REGNO (e) != SP_REGNUM)
14820 fprintf (asm_out_file, "}\n");
14823 /* Emit unwind directives for a SET. */
14826 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
14833 switch (GET_CODE (e0))
14836 /* Pushing a single register. */
14837 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
14838 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
14839 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
14842 asm_fprintf (asm_out_file, "\t.save ");
14843 if (IS_VFP_REGNUM (REGNO (e1)))
14844 asm_fprintf(asm_out_file, "{d%d}\n",
14845 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
14847 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
14851 if (REGNO (e0) == SP_REGNUM)
14853 /* A stack increment. */
14854 if (GET_CODE (e1) != PLUS
14855 || GET_CODE (XEXP (e1, 0)) != REG
14856 || REGNO (XEXP (e1, 0)) != SP_REGNUM
14857 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14860 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
14861 -INTVAL (XEXP (e1, 1)));
14863 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
14865 HOST_WIDE_INT offset;
14868 if (GET_CODE (e1) == PLUS)
14870 if (GET_CODE (XEXP (e1, 0)) != REG
14871 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14873 reg = REGNO (XEXP (e1, 0));
14874 offset = INTVAL (XEXP (e1, 1));
14875 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
14876 HARD_FRAME_POINTER_REGNUM, reg,
14877 INTVAL (XEXP (e1, 1)));
14879 else if (GET_CODE (e1) == REG)
14882 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
14883 HARD_FRAME_POINTER_REGNUM, reg);
14888 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
14890 /* Move from sp to reg. */
14891 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
14903 /* Emit unwind directives for the given insn. */
14906 arm_unwind_emit (FILE * asm_out_file, rtx insn)
14910 if (!ARM_EABI_UNWIND_TABLES)
14913 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
14916 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
14918 pat = XEXP (pat, 0);
14920 pat = PATTERN (insn);
14922 switch (GET_CODE (pat))
14925 arm_unwind_emit_set (asm_out_file, pat);
14929 /* Store multiple. */
14930 arm_unwind_emit_stm (asm_out_file, pat);
14939 /* Output a reference from a function exception table to the type_info
14940 object X. The EABI specifies that the symbol should be relocated by
14941 an R_ARM_TARGET2 relocation. */
14944 arm_output_ttype (rtx x)
14946 fputs ("\t.word\t", asm_out_file);
14947 output_addr_const (asm_out_file, x);
14948 /* Use special relocations for symbol references. */
14949 if (GET_CODE (x) != CONST_INT)
14950 fputs ("(TARGET2)", asm_out_file);
14951 fputc ('\n', asm_out_file);
14955 #endif /* TARGET_UNWIND_INFO */
14958 /* Output unwind directives for the start/end of a function. */
14961 arm_output_fn_unwind (FILE * f, bool prologue)
14963 if (!ARM_EABI_UNWIND_TABLES)
14967 fputs ("\t.fnstart\n", f);
14969 fputs ("\t.fnend\n", f);