1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
71 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
72 inline static int thumb1_index_register_rtx_p (rtx, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
77 static rtx emit_sfm (int, int);
78 static int arm_size_return_regs (void);
80 static bool arm_assemble_integer (rtx, unsigned int, int);
82 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
83 static arm_cc get_arm_condition_code (rtx);
84 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
85 static rtx is_jump_table (rtx);
86 static const char *output_multi_immediate (rtx *, const char *, const char *,
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree);
110 static unsigned long arm_compute_func_type (void);
111 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
113 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
114 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
116 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static int arm_comp_type_attributes (tree, tree);
120 static void arm_set_default_type_attributes (tree);
121 static int arm_adjust_cost (rtx, rtx, rtx, int);
122 static int count_insns_for_constant (HOST_WIDE_INT, int);
123 static int arm_get_strip_length (int);
124 static bool arm_function_ok_for_sibcall (tree, tree);
125 static void arm_internal_label (FILE *, const char *, unsigned long);
126 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
128 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
129 static bool arm_size_rtx_costs (rtx, int, int, int *);
130 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
133 static bool arm_9e_rtx_costs (rtx, int, int, int *);
134 static int arm_address_cost (rtx);
135 static bool arm_memory_load_p (rtx);
136 static bool arm_cirrus_insn_p (rtx);
137 static void cirrus_reorg (rtx);
138 static void arm_init_builtins (void);
139 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140 static void arm_init_iwmmxt_builtins (void);
141 static rtx safe_vector_operand (rtx, enum machine_mode);
142 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
143 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
144 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
145 static void emit_constant_insn (rtx cond, rtx pattern);
146 static rtx emit_set_insn (rtx, rtx);
147 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
150 #ifdef OBJECT_FORMAT_ELF
151 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
152 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
155 static void arm_encode_section_info (tree, rtx, int);
158 static void arm_file_end (void);
159 static void arm_file_start (void);
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
172 enum machine_mode, tree, bool);
173 static bool arm_promote_prototypes (tree);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree);
177 static bool arm_must_pass_in_stack (enum machine_mode, tree);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx);
180 static bool arm_output_ttype (rtx);
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
184 static tree arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree arm_get_cookie_size (tree);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
196 static bool arm_cannot_copy_insn_p (rtx);
197 static bool arm_tls_symbol_p (rtx x);
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
254 #undef TARGET_ENCODE_SECTION_INFO
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
380 struct gcc_target targetm = TARGET_INITIALIZER;
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack;
384 static char * minipool_startobj;
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped = 5;
390 extern FILE * asm_out_file;
392 /* True if we are currently building a constant table. */
393 int making_const_table;
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0, arm_compare_op1;
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune = arm_none;
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu = arm_none;
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model;
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch;
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune;
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi;
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi;
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer = TP_AUTO;
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label[14];
428 static int thumb_call_reg_needed;
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 #define FL_DIV (1 << 18) /* Hardware divide. */
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags = 0;
481 /* The bits in this mask specify which instruction scheduling options should
483 static unsigned long tune_flags = 0;
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
506 /* Nonzero if this chip supports the ARM 6K extensions. */
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm = 0;
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched = 0;
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm = 0;
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus = 0;
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt = 0;
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale = 0;
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale = 0;
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf = 0;
534 /* Nonzero if generating Thumb instructions. */
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork = 0;
544 /* Nonzero if chip supports Thumb 2. */
547 /* Nonzero if chip supports integer division instruction. */
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode;
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register = INVALID_REGNUM;
558 /* Set to 1 when a return insn is output, this means that the epilogue
560 int return_used_this_function;
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg = 0;
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit = 3;
569 /* For an explanation of these variables, see final_prescan_insn below. */
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc;
574 int arm_target_label;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count = 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask = 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen = 0;
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes[] =
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
597 /* Initialization code. */
601 const char *const name;
602 enum processor_type core;
604 const unsigned long flags;
605 bool (* rtx_costs) (rtx, int, int, int *);
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores[] =
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
617 {NULL, arm_none, NULL, 0, NULL}
620 static const struct processors all_architectures[] =
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
626 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
627 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
628 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
629 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
630 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
634 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
635 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
636 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
637 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
638 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
639 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
640 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
641 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
642 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
643 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
644 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
645 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
646 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
647 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
648 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
649 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
650 {NULL, arm_none, NULL, 0 , NULL}
653 struct arm_cpu_select
657 const struct processors * processors;
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
664 static struct arm_cpu_select arm_select[] =
666 /* string name processors */
667 { NULL, "-mcpu=", all_cores },
668 { NULL, "-march=", all_architectures },
669 { NULL, "-mtune=", all_cores }
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
677 /* The name of the preprocessor macro to define for this architecture. */
679 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
688 /* Available values for -mfpu=. */
690 static const struct fpu_desc all_fpus[] =
692 {"fpa", FPUTYPE_FPA},
693 {"fpe2", FPUTYPE_FPA_EMU2},
694 {"fpe3", FPUTYPE_FPA_EMU2},
695 {"maverick", FPUTYPE_MAVERICK},
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
703 static const enum fputype fp_model_for_fpu[] =
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
718 enum float_abi_type abi_type;
722 /* Available values for -mfloat-abi=. */
724 static const struct float_abi all_float_abis[] =
726 {"soft", ARM_FLOAT_ABI_SOFT},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP},
728 {"hard", ARM_FLOAT_ABI_HARD}
735 enum arm_abi_type abi_type;
739 /* Available values for -mabi=. */
741 static const struct abi_name arm_all_abis[] =
743 {"apcs-gnu", ARM_ABI_APCS},
744 {"atpcs", ARM_ABI_ATPCS},
745 {"aapcs", ARM_ABI_AAPCS},
746 {"iwmmxt", ARM_ABI_IWMMXT},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
750 /* Supported TLS relocations. */
760 /* Emit an insn that's a simple single-set. Both the operands must be known
763 emit_set_insn (rtx x, rtx y)
765 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
768 /* Return the number of bits set in VALUE. */
770 bit_count (unsigned long value)
772 unsigned long count = 0;
777 value &= value - 1; /* Clear the least-significant set bit. */
783 /* Set up library functions unique to ARM. */
786 arm_init_libfuncs (void)
788 /* There are no special library functions unless we are using the
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab, DFmode, NULL);
806 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab, SFmode, NULL);
822 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
875 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
878 /* For SImode division the ABI provides div-without-mod routines,
880 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab, DImode, NULL);
886 set_optab_libfunc (umod_optab, DImode, NULL);
887 set_optab_libfunc (smod_optab, SImode, NULL);
888 set_optab_libfunc (umod_optab, SImode, NULL);
891 /* Implement TARGET_HANDLE_OPTION. */
894 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
899 arm_select[1].string = arg;
903 arm_select[0].string = arg;
906 case OPT_mhard_float:
907 target_float_abi_name = "hard";
910 case OPT_msoft_float:
911 target_float_abi_name = "soft";
915 arm_select[2].string = arg;
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
926 arm_override_options (void)
929 enum processor_type target_arch_cpu = arm_none;
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i = ARRAY_SIZE (arm_select); i--;)
934 struct arm_cpu_select * ptr = arm_select + i;
936 if (ptr->string != NULL && ptr->string[0] != '\0')
938 const struct processors * sel;
940 for (sel = ptr->processors; sel->name != NULL; sel++)
941 if (streq (ptr->string, sel->name))
943 /* Set the architecture define. */
944 if (i != ARM_OPT_SET_TUNE)
945 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i == ARM_OPT_SET_TUNE)
953 arm_tune = (enum processor_type) (sel - ptr->processors);
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
959 if (i == ARM_OPT_SET_ARCH)
960 target_arch_cpu = sel->core;
962 if (i != ARM_OPT_SET_TUNE)
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
968 if (insn_flags != 0 && (insn_flags ^ sel->flags))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
972 insn_flags = sel->flags;
978 if (sel->name == NULL)
979 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune == arm_none)
985 arm_tune = target_arch_cpu;
987 /* If the user did not specify a processor, choose one for them. */
990 const struct processors * sel;
992 enum processor_type cpu;
994 cpu = TARGET_CPU_DEFAULT;
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
1000 cpu = SUBTARGET_CPU_DEFAULT;
1002 /* Default to ARM6. */
1003 if (cpu == arm_none)
1006 sel = &all_cores[cpu];
1008 insn_flags = sel->flags;
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1014 if (TARGET_INTERWORK || TARGET_THUMB)
1016 sought |= (FL_THUMB | FL_MODE32);
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags &= ~FL_MODE26;
1025 if (sought != 0 && ((sought & insn_flags) != sought))
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1030 for (sel = all_cores; sel->name != NULL; sel++)
1031 if ((sel->flags & sought) == (sought | insn_flags))
1034 if (sel->name == NULL)
1036 unsigned current_bit_count = 0;
1037 const struct processors * best_fit = NULL;
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel = all_cores; sel->name != NULL; sel++)
1051 if ((sel->flags & sought) == sought)
1055 count = bit_count (sel->flags & insn_flags);
1057 if (count >= current_bit_count)
1060 current_bit_count = count;
1064 gcc_assert (best_fit);
1068 insn_flags = sel->flags;
1070 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1071 arm_default_cpu = (enum processor_type) (sel - all_cores);
1072 if (arm_tune == arm_none)
1073 arm_tune = arm_default_cpu;
1076 /* The processor for which we should tune should now have been
1078 gcc_assert (arm_tune != arm_none);
1080 tune_flags = all_cores[(int)arm_tune].flags;
1082 targetm.rtx_costs = arm_size_rtx_costs;
1084 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1089 error ("target CPU does not support ARM mode");
1091 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags &= ~MASK_INTERWORK;
1097 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags &= ~MASK_THUMB;
1103 if (TARGET_APCS_FRAME && TARGET_THUMB)
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags &= ~MASK_APCS_FRAME;
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1112 target_flags |= MASK_INTERWORK;
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1119 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1122 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1125 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags |= MASK_APCS_FRAME;
1131 if (TARGET_POKE_FUNCTION_NAME)
1132 target_flags |= MASK_APCS_FRAME;
1134 if (TARGET_APCS_REENT && flag_pic)
1135 error ("-fpic and -mapcs-reent are incompatible");
1137 if (TARGET_APCS_REENT)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1143 && write_symbols != NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1148 if (TARGET_APCS_FLOAT)
1149 warning (0, "passing floating point arguments in fp regs not yet supported");
1151 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1152 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1153 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1154 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1155 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1156 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1157 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1158 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1159 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1160 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1161 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1162 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1164 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1165 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1166 thumb_code = (TARGET_ARM == 0);
1167 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1168 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1169 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1170 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1172 /* V5 code we generate is completely interworking capable, so we turn off
1173 TARGET_INTERWORK here to avoid many tests later on. */
1175 /* XXX However, we must pass the right pre-processor defines to CPP
1176 or GLD can get confused. This is a hack. */
1177 if (TARGET_INTERWORK)
1178 arm_cpp_interwork = 1;
1181 target_flags &= ~MASK_INTERWORK;
1183 if (target_abi_name)
1185 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1187 if (streq (arm_all_abis[i].name, target_abi_name))
1189 arm_abi = arm_all_abis[i].abi_type;
1193 if (i == ARRAY_SIZE (arm_all_abis))
1194 error ("invalid ABI option: -mabi=%s", target_abi_name);
1197 arm_abi = ARM_DEFAULT_ABI;
1199 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1200 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1202 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1203 error ("iwmmxt abi requires an iwmmxt capable cpu");
1205 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1206 if (target_fpu_name == NULL && target_fpe_name != NULL)
1208 if (streq (target_fpe_name, "2"))
1209 target_fpu_name = "fpe2";
1210 else if (streq (target_fpe_name, "3"))
1211 target_fpu_name = "fpe3";
1213 error ("invalid floating point emulation option: -mfpe=%s",
1216 if (target_fpu_name != NULL)
1218 /* The user specified a FPU. */
1219 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1221 if (streq (all_fpus[i].name, target_fpu_name))
1223 arm_fpu_arch = all_fpus[i].fpu;
1224 arm_fpu_tune = arm_fpu_arch;
1225 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1229 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1230 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1234 #ifdef FPUTYPE_DEFAULT
1235 /* Use the default if it is specified for this platform. */
1236 arm_fpu_arch = FPUTYPE_DEFAULT;
1237 arm_fpu_tune = FPUTYPE_DEFAULT;
1239 /* Pick one based on CPU type. */
1240 /* ??? Some targets assume FPA is the default.
1241 if ((insn_flags & FL_VFP) != 0)
1242 arm_fpu_arch = FPUTYPE_VFP;
1245 if (arm_arch_cirrus)
1246 arm_fpu_arch = FPUTYPE_MAVERICK;
1248 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1250 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1251 arm_fpu_tune = FPUTYPE_FPA;
1253 arm_fpu_tune = arm_fpu_arch;
1254 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1255 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1258 if (target_float_abi_name != NULL)
1260 /* The user specified a FP ABI. */
1261 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1263 if (streq (all_float_abis[i].name, target_float_abi_name))
1265 arm_float_abi = all_float_abis[i].abi_type;
1269 if (i == ARRAY_SIZE (all_float_abis))
1270 error ("invalid floating point abi: -mfloat-abi=%s",
1271 target_float_abi_name);
1274 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1276 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1277 sorry ("-mfloat-abi=hard and VFP");
1279 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1280 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1281 will ever exist. GCC makes no attempt to support this combination. */
1282 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1283 sorry ("iWMMXt and hardware floating point");
1285 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1286 if (TARGET_THUMB2 && TARGET_IWMMXT)
1287 sorry ("Thumb-2 iWMMXt");
1289 /* If soft-float is specified then don't use FPU. */
1290 if (TARGET_SOFT_FLOAT)
1291 arm_fpu_arch = FPUTYPE_NONE;
1293 /* For arm2/3 there is no need to do any scheduling if there is only
1294 a floating point emulator, or we are doing software floating-point. */
1295 if ((TARGET_SOFT_FLOAT
1296 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1297 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1298 && (tune_flags & FL_MODE32) == 0)
1299 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1301 if (target_thread_switch)
1303 if (strcmp (target_thread_switch, "soft") == 0)
1304 target_thread_pointer = TP_SOFT;
1305 else if (strcmp (target_thread_switch, "auto") == 0)
1306 target_thread_pointer = TP_AUTO;
1307 else if (strcmp (target_thread_switch, "cp15") == 0)
1308 target_thread_pointer = TP_CP15;
1310 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1313 /* Use the cp15 method if it is available. */
1314 if (target_thread_pointer == TP_AUTO)
1316 if (arm_arch6k && !TARGET_THUMB)
1317 target_thread_pointer = TP_CP15;
1319 target_thread_pointer = TP_SOFT;
1322 if (TARGET_HARD_TP && TARGET_THUMB1)
1323 error ("can not use -mtp=cp15 with 16-bit Thumb");
1325 /* Override the default structure alignment for AAPCS ABI. */
1326 if (TARGET_AAPCS_BASED)
1327 arm_structure_size_boundary = 8;
1329 if (structure_size_string != NULL)
1331 int size = strtol (structure_size_string, NULL, 0);
1333 if (size == 8 || size == 32
1334 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1335 arm_structure_size_boundary = size;
1337 warning (0, "structure size boundary can only be set to %s",
1338 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1341 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1343 error ("RTP PIC is incompatible with Thumb");
1347 /* If stack checking is disabled, we can use r10 as the PIC register,
1348 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1349 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1351 if (TARGET_VXWORKS_RTP)
1352 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1353 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1356 if (flag_pic && TARGET_VXWORKS_RTP)
1357 arm_pic_register = 9;
1359 if (arm_pic_register_string != NULL)
1361 int pic_register = decode_reg_name (arm_pic_register_string);
1364 warning (0, "-mpic-register= is useless without -fpic");
1366 /* Prevent the user from choosing an obviously stupid PIC register. */
1367 else if (pic_register < 0 || call_used_regs[pic_register]
1368 || pic_register == HARD_FRAME_POINTER_REGNUM
1369 || pic_register == STACK_POINTER_REGNUM
1370 || pic_register >= PC_REGNUM
1371 || (TARGET_VXWORKS_RTP
1372 && (unsigned int) pic_register != arm_pic_register))
1373 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1375 arm_pic_register = pic_register;
1378 /* ??? We might want scheduling for thumb2. */
1379 if (TARGET_THUMB && flag_schedule_insns)
1381 /* Don't warn since it's on by default in -O2. */
1382 flag_schedule_insns = 0;
1387 arm_constant_limit = 1;
1389 /* If optimizing for size, bump the number of instructions that we
1390 are prepared to conditionally execute (even on a StrongARM). */
1391 max_insns_skipped = 6;
1395 /* For processors with load scheduling, it never costs more than
1396 2 cycles to load a constant, and the load scheduler may well
1397 reduce that to 1. */
1399 arm_constant_limit = 1;
1401 /* On XScale the longer latency of a load makes it more difficult
1402 to achieve a good schedule, so it's faster to synthesize
1403 constants that can be done in two insns. */
1404 if (arm_tune_xscale)
1405 arm_constant_limit = 2;
1407 /* StrongARM has early execution of branches, so a sequence
1408 that is worth skipping is shorter. */
1409 if (arm_tune_strongarm)
1410 max_insns_skipped = 3;
1413 /* Register global variables with the garbage collector. */
1414 arm_add_gc_roots ();
1418 arm_add_gc_roots (void)
1420 gcc_obstack_init(&minipool_obstack);
1421 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1424 /* A table of known ARM exception types.
1425 For use with the interrupt function attribute. */
1429 const char *const arg;
1430 const unsigned long return_value;
1434 static const isr_attribute_arg isr_attribute_args [] =
1436 { "IRQ", ARM_FT_ISR },
1437 { "irq", ARM_FT_ISR },
1438 { "FIQ", ARM_FT_FIQ },
1439 { "fiq", ARM_FT_FIQ },
1440 { "ABORT", ARM_FT_ISR },
1441 { "abort", ARM_FT_ISR },
1442 { "ABORT", ARM_FT_ISR },
1443 { "abort", ARM_FT_ISR },
1444 { "UNDEF", ARM_FT_EXCEPTION },
1445 { "undef", ARM_FT_EXCEPTION },
1446 { "SWI", ARM_FT_EXCEPTION },
1447 { "swi", ARM_FT_EXCEPTION },
1448 { NULL, ARM_FT_NORMAL }
1451 /* Returns the (interrupt) function type of the current
1452 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1454 static unsigned long
1455 arm_isr_value (tree argument)
1457 const isr_attribute_arg * ptr;
1461 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1463 /* No argument - default to IRQ. */
1464 if (argument == NULL_TREE)
1467 /* Get the value of the argument. */
1468 if (TREE_VALUE (argument) == NULL_TREE
1469 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1470 return ARM_FT_UNKNOWN;
1472 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1474 /* Check it against the list of known arguments. */
1475 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1476 if (streq (arg, ptr->arg))
1477 return ptr->return_value;
1479 /* An unrecognized interrupt type. */
1480 return ARM_FT_UNKNOWN;
1483 /* Computes the type of the current function. */
1485 static unsigned long
1486 arm_compute_func_type (void)
1488 unsigned long type = ARM_FT_UNKNOWN;
1492 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1494 /* Decide if the current function is volatile. Such functions
1495 never return, and many memory cycles can be saved by not storing
1496 register values that will never be needed again. This optimization
1497 was added to speed up context switching in a kernel application. */
1499 && (TREE_NOTHROW (current_function_decl)
1500 || !(flag_unwind_tables
1501 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1502 && TREE_THIS_VOLATILE (current_function_decl))
1503 type |= ARM_FT_VOLATILE;
1505 if (cfun->static_chain_decl != NULL)
1506 type |= ARM_FT_NESTED;
1508 attr = DECL_ATTRIBUTES (current_function_decl);
1510 a = lookup_attribute ("naked", attr);
1512 type |= ARM_FT_NAKED;
1514 a = lookup_attribute ("isr", attr);
1516 a = lookup_attribute ("interrupt", attr);
1519 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1521 type |= arm_isr_value (TREE_VALUE (a));
1526 /* Returns the type of the current function. */
1529 arm_current_func_type (void)
1531 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1532 cfun->machine->func_type = arm_compute_func_type ();
1534 return cfun->machine->func_type;
1537 /* Return 1 if it is possible to return using a single instruction.
1538 If SIBLING is non-null, this is a test for a return before a sibling
1539 call. SIBLING is the call insn, so we can examine its register usage. */
1542 use_return_insn (int iscond, rtx sibling)
1545 unsigned int func_type;
1546 unsigned long saved_int_regs;
1547 unsigned HOST_WIDE_INT stack_adjust;
1548 arm_stack_offsets *offsets;
1550 /* Never use a return instruction before reload has run. */
1551 if (!reload_completed)
1554 func_type = arm_current_func_type ();
1556 /* Naked, volatile and stack alignment functions need special
1558 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1561 /* So do interrupt functions that use the frame pointer and Thumb
1562 interrupt functions. */
1563 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1566 offsets = arm_get_frame_offsets ();
1567 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1569 /* As do variadic functions. */
1570 if (current_function_pretend_args_size
1571 || cfun->machine->uses_anonymous_args
1572 /* Or if the function calls __builtin_eh_return () */
1573 || current_function_calls_eh_return
1574 /* Or if the function calls alloca */
1575 || current_function_calls_alloca
1576 /* Or if there is a stack adjustment. However, if the stack pointer
1577 is saved on the stack, we can use a pre-incrementing stack load. */
1578 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1581 saved_int_regs = arm_compute_save_reg_mask ();
1583 /* Unfortunately, the insn
1585 ldmib sp, {..., sp, ...}
1587 triggers a bug on most SA-110 based devices, such that the stack
1588 pointer won't be correctly restored if the instruction takes a
1589 page fault. We work around this problem by popping r3 along with
1590 the other registers, since that is never slower than executing
1591 another instruction.
1593 We test for !arm_arch5 here, because code for any architecture
1594 less than this could potentially be run on one of the buggy
1596 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1598 /* Validate that r3 is a call-clobbered register (always true in
1599 the default abi) ... */
1600 if (!call_used_regs[3])
1603 /* ... that it isn't being used for a return value ... */
1604 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1607 /* ... or for a tail-call argument ... */
1610 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1612 if (find_regno_fusage (sibling, USE, 3))
1616 /* ... and that there are no call-saved registers in r0-r2
1617 (always true in the default ABI). */
1618 if (saved_int_regs & 0x7)
1622 /* Can't be done if interworking with Thumb, and any registers have been
1624 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1627 /* On StrongARM, conditional returns are expensive if they aren't
1628 taken and multiple registers have been stacked. */
1629 if (iscond && arm_tune_strongarm)
1631 /* Conditional return when just the LR is stored is a simple
1632 conditional-load instruction, that's not expensive. */
1633 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1637 && arm_pic_register != INVALID_REGNUM
1638 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1642 /* If there are saved registers but the LR isn't saved, then we need
1643 two instructions for the return. */
1644 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1647 /* Can't be done if any of the FPA regs are pushed,
1648 since this also requires an insn. */
1649 if (TARGET_HARD_FLOAT && TARGET_FPA)
1650 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1651 if (regs_ever_live[regno] && !call_used_regs[regno])
1654 /* Likewise VFP regs. */
1655 if (TARGET_HARD_FLOAT && TARGET_VFP)
1656 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1657 if (regs_ever_live[regno] && !call_used_regs[regno])
1660 if (TARGET_REALLY_IWMMXT)
1661 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1662 if (regs_ever_live[regno] && ! call_used_regs [regno])
1668 /* Return TRUE if int I is a valid immediate ARM constant. */
1671 const_ok_for_arm (HOST_WIDE_INT i)
1675 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1676 be all zero, or all one. */
1677 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1678 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1679 != ((~(unsigned HOST_WIDE_INT) 0)
1680 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1683 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1685 /* Fast return for 0 and small values. We must do this for zero, since
1686 the code below can't handle that one case. */
1687 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1690 /* Get the number of trailing zeros. */
1691 lowbit = ffs((int) i) - 1;
1693 /* Only even shifts are allowed in ARM mode so round down to the
1694 nearest even number. */
1698 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1703 /* Allow rotated constants in ARM mode. */
1705 && ((i & ~0xc000003f) == 0
1706 || (i & ~0xf000000f) == 0
1707 || (i & ~0xfc000003) == 0))
1714 /* Allow repeated pattern. */
1717 if (i == v || i == (v | (v << 8)))
1724 /* Return true if I is a valid constant for the operation CODE. */
1726 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1728 if (const_ok_for_arm (i))
1734 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1736 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1742 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1749 /* Emit a sequence of insns to handle a large constant.
1750 CODE is the code of the operation required, it can be any of SET, PLUS,
1751 IOR, AND, XOR, MINUS;
1752 MODE is the mode in which the operation is being performed;
1753 VAL is the integer to operate on;
1754 SOURCE is the other operand (a register, or a null-pointer for SET);
1755 SUBTARGETS means it is safe to create scratch registers if that will
1756 either produce a simpler sequence, or we will want to cse the values.
1757 Return value is the number of insns emitted. */
1759 /* ??? Tweak this for thumb2. */
1761 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1762 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1766 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1767 cond = COND_EXEC_TEST (PATTERN (insn));
1771 if (subtargets || code == SET
1772 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1773 && REGNO (target) != REGNO (source)))
1775 /* After arm_reorg has been called, we can't fix up expensive
1776 constants by pushing them into memory so we must synthesize
1777 them in-line, regardless of the cost. This is only likely to
1778 be more costly on chips that have load delay slots and we are
1779 compiling without running the scheduler (so no splitting
1780 occurred before the final instruction emission).
1782 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1784 if (!after_arm_reorg
1786 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1788 > arm_constant_limit + (code != SET)))
1792 /* Currently SET is the only monadic value for CODE, all
1793 the rest are diadic. */
1794 emit_set_insn (target, GEN_INT (val));
1799 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1801 emit_set_insn (temp, GEN_INT (val));
1802 /* For MINUS, the value is subtracted from, since we never
1803 have subtraction of a constant. */
1805 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1807 emit_set_insn (target,
1808 gen_rtx_fmt_ee (code, mode, source, temp));
1814 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1818 /* Return the number of ARM instructions required to synthesize the given
1821 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1823 HOST_WIDE_INT temp1;
1831 if (remainder & (3 << (i - 2)))
1836 temp1 = remainder & ((0x0ff << end)
1837 | ((i < end) ? (0xff >> (32 - end)) : 0));
1838 remainder &= ~temp1;
1843 } while (remainder);
1847 /* Emit an instruction with the indicated PATTERN. If COND is
1848 non-NULL, conditionalize the execution of the instruction on COND
1852 emit_constant_insn (rtx cond, rtx pattern)
1855 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1856 emit_insn (pattern);
1859 /* As above, but extra parameter GENERATE which, if clear, suppresses
1861 /* ??? This needs more work for thumb2. */
1864 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1865 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1870 int can_negate_initial = 0;
1873 int num_bits_set = 0;
1874 int set_sign_bit_copies = 0;
1875 int clear_sign_bit_copies = 0;
1876 int clear_zero_bit_copies = 0;
1877 int set_zero_bit_copies = 0;
1879 unsigned HOST_WIDE_INT temp1, temp2;
1880 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1882 /* Find out which operations are safe for a given CODE. Also do a quick
1883 check for degenerate cases; these can occur when DImode operations
1895 can_negate_initial = 1;
1899 if (remainder == 0xffffffff)
1902 emit_constant_insn (cond,
1903 gen_rtx_SET (VOIDmode, target,
1904 GEN_INT (ARM_SIGN_EXTEND (val))));
1909 if (reload_completed && rtx_equal_p (target, source))
1912 emit_constant_insn (cond,
1913 gen_rtx_SET (VOIDmode, target, source));
1922 emit_constant_insn (cond,
1923 gen_rtx_SET (VOIDmode, target, const0_rtx));
1926 if (remainder == 0xffffffff)
1928 if (reload_completed && rtx_equal_p (target, source))
1931 emit_constant_insn (cond,
1932 gen_rtx_SET (VOIDmode, target, source));
1941 if (reload_completed && rtx_equal_p (target, source))
1944 emit_constant_insn (cond,
1945 gen_rtx_SET (VOIDmode, target, source));
1949 /* We don't know how to handle other cases yet. */
1950 gcc_assert (remainder == 0xffffffff);
1953 emit_constant_insn (cond,
1954 gen_rtx_SET (VOIDmode, target,
1955 gen_rtx_NOT (mode, source)));
1959 /* We treat MINUS as (val - source), since (source - val) is always
1960 passed as (source + (-val)). */
1964 emit_constant_insn (cond,
1965 gen_rtx_SET (VOIDmode, target,
1966 gen_rtx_NEG (mode, source)));
1969 if (const_ok_for_arm (val))
1972 emit_constant_insn (cond,
1973 gen_rtx_SET (VOIDmode, target,
1974 gen_rtx_MINUS (mode, GEN_INT (val),
1986 /* If we can do it in one insn get out quickly. */
1987 if (const_ok_for_arm (val)
1988 || (can_negate_initial && const_ok_for_arm (-val))
1989 || (can_invert && const_ok_for_arm (~val)))
1992 emit_constant_insn (cond,
1993 gen_rtx_SET (VOIDmode, target,
1995 ? gen_rtx_fmt_ee (code, mode, source,
2001 /* Calculate a few attributes that may be useful for specific
2003 for (i = 31; i >= 0; i--)
2005 if ((remainder & (1 << i)) == 0)
2006 clear_sign_bit_copies++;
2011 for (i = 31; i >= 0; i--)
2013 if ((remainder & (1 << i)) != 0)
2014 set_sign_bit_copies++;
2019 for (i = 0; i <= 31; i++)
2021 if ((remainder & (1 << i)) == 0)
2022 clear_zero_bit_copies++;
2027 for (i = 0; i <= 31; i++)
2029 if ((remainder & (1 << i)) != 0)
2030 set_zero_bit_copies++;
2038 /* See if we can use movw. */
2039 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2042 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2047 /* See if we can do this by sign_extending a constant that is known
2048 to be negative. This is a good, way of doing it, since the shift
2049 may well merge into a subsequent insn. */
2050 if (set_sign_bit_copies > 1)
2052 if (const_ok_for_arm
2053 (temp1 = ARM_SIGN_EXTEND (remainder
2054 << (set_sign_bit_copies - 1))))
2058 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2059 emit_constant_insn (cond,
2060 gen_rtx_SET (VOIDmode, new_src,
2062 emit_constant_insn (cond,
2063 gen_ashrsi3 (target, new_src,
2064 GEN_INT (set_sign_bit_copies - 1)));
2068 /* For an inverted constant, we will need to set the low bits,
2069 these will be shifted out of harm's way. */
2070 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2071 if (const_ok_for_arm (~temp1))
2075 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2076 emit_constant_insn (cond,
2077 gen_rtx_SET (VOIDmode, new_src,
2079 emit_constant_insn (cond,
2080 gen_ashrsi3 (target, new_src,
2081 GEN_INT (set_sign_bit_copies - 1)));
2087 /* See if we can calculate the value as the difference between two
2088 valid immediates. */
2089 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2091 int topshift = clear_sign_bit_copies & ~1;
2093 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2094 & (0xff000000 >> topshift));
2096 /* If temp1 is zero, then that means the 9 most significant
2097 bits of remainder were 1 and we've caused it to overflow.
2098 When topshift is 0 we don't need to do anything since we
2099 can borrow from 'bit 32'. */
2100 if (temp1 == 0 && topshift != 0)
2101 temp1 = 0x80000000 >> (topshift - 1);
2103 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2105 if (const_ok_for_arm (temp2))
2109 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2110 emit_constant_insn (cond,
2111 gen_rtx_SET (VOIDmode, new_src,
2113 emit_constant_insn (cond,
2114 gen_addsi3 (target, new_src,
2122 /* See if we can generate this by setting the bottom (or the top)
2123 16 bits, and then shifting these into the other half of the
2124 word. We only look for the simplest cases, to do more would cost
2125 too much. Be careful, however, not to generate this when the
2126 alternative would take fewer insns. */
2127 if (val & 0xffff0000)
2129 temp1 = remainder & 0xffff0000;
2130 temp2 = remainder & 0x0000ffff;
2132 /* Overlaps outside this range are best done using other methods. */
2133 for (i = 9; i < 24; i++)
2135 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2136 && !const_ok_for_arm (temp2))
2138 rtx new_src = (subtargets
2139 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2141 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2142 source, subtargets, generate);
2150 gen_rtx_ASHIFT (mode, source,
2157 /* Don't duplicate cases already considered. */
2158 for (i = 17; i < 24; i++)
2160 if (((temp1 | (temp1 >> i)) == remainder)
2161 && !const_ok_for_arm (temp1))
2163 rtx new_src = (subtargets
2164 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2166 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2167 source, subtargets, generate);
2172 gen_rtx_SET (VOIDmode, target,
2175 gen_rtx_LSHIFTRT (mode, source,
2186 /* If we have IOR or XOR, and the constant can be loaded in a
2187 single instruction, and we can find a temporary to put it in,
2188 then this can be done in two instructions instead of 3-4. */
2190 /* TARGET can't be NULL if SUBTARGETS is 0 */
2191 || (reload_completed && !reg_mentioned_p (target, source)))
2193 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2197 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2199 emit_constant_insn (cond,
2200 gen_rtx_SET (VOIDmode, sub,
2202 emit_constant_insn (cond,
2203 gen_rtx_SET (VOIDmode, target,
2204 gen_rtx_fmt_ee (code, mode,
2214 if (set_sign_bit_copies > 8
2215 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2219 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2220 rtx shift = GEN_INT (set_sign_bit_copies);
2224 gen_rtx_SET (VOIDmode, sub,
2226 gen_rtx_ASHIFT (mode,
2231 gen_rtx_SET (VOIDmode, target,
2233 gen_rtx_LSHIFTRT (mode, sub,
2239 if (set_zero_bit_copies > 8
2240 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2244 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2245 rtx shift = GEN_INT (set_zero_bit_copies);
2249 gen_rtx_SET (VOIDmode, sub,
2251 gen_rtx_LSHIFTRT (mode,
2256 gen_rtx_SET (VOIDmode, target,
2258 gen_rtx_ASHIFT (mode, sub,
2264 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2268 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2269 emit_constant_insn (cond,
2270 gen_rtx_SET (VOIDmode, sub,
2271 gen_rtx_NOT (mode, source)));
2274 sub = gen_reg_rtx (mode);
2275 emit_constant_insn (cond,
2276 gen_rtx_SET (VOIDmode, sub,
2277 gen_rtx_AND (mode, source,
2279 emit_constant_insn (cond,
2280 gen_rtx_SET (VOIDmode, target,
2281 gen_rtx_NOT (mode, sub)));
2288 /* See if two shifts will do 2 or more insn's worth of work. */
2289 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2291 HOST_WIDE_INT shift_mask = ((0xffffffff
2292 << (32 - clear_sign_bit_copies))
2295 if ((remainder | shift_mask) != 0xffffffff)
2299 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2300 insns = arm_gen_constant (AND, mode, cond,
2301 remainder | shift_mask,
2302 new_src, source, subtargets, 1);
2307 rtx targ = subtargets ? NULL_RTX : target;
2308 insns = arm_gen_constant (AND, mode, cond,
2309 remainder | shift_mask,
2310 targ, source, subtargets, 0);
2316 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2317 rtx shift = GEN_INT (clear_sign_bit_copies);
2319 emit_insn (gen_ashlsi3 (new_src, source, shift));
2320 emit_insn (gen_lshrsi3 (target, new_src, shift));
2326 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2328 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2330 if ((remainder | shift_mask) != 0xffffffff)
2334 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2336 insns = arm_gen_constant (AND, mode, cond,
2337 remainder | shift_mask,
2338 new_src, source, subtargets, 1);
2343 rtx targ = subtargets ? NULL_RTX : target;
2345 insns = arm_gen_constant (AND, mode, cond,
2346 remainder | shift_mask,
2347 targ, source, subtargets, 0);
2353 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2354 rtx shift = GEN_INT (clear_zero_bit_copies);
2356 emit_insn (gen_lshrsi3 (new_src, source, shift));
2357 emit_insn (gen_ashlsi3 (target, new_src, shift));
2369 for (i = 0; i < 32; i++)
2370 if (remainder & (1 << i))
2373 if (code == AND || (can_invert && num_bits_set > 16))
2374 remainder = (~remainder) & 0xffffffff;
2375 else if (code == PLUS && num_bits_set > 16)
2376 remainder = (-remainder) & 0xffffffff;
2383 /* Now try and find a way of doing the job in either two or three
2385 We start by looking for the largest block of zeros that are aligned on
2386 a 2-bit boundary, we then fill up the temps, wrapping around to the
2387 top of the word when we drop off the bottom.
2388 In the worst case this code should produce no more than four insns.
2389 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2390 best place to start. */
2392 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2398 int best_consecutive_zeros = 0;
2400 for (i = 0; i < 32; i += 2)
2402 int consecutive_zeros = 0;
2404 if (!(remainder & (3 << i)))
2406 while ((i < 32) && !(remainder & (3 << i)))
2408 consecutive_zeros += 2;
2411 if (consecutive_zeros > best_consecutive_zeros)
2413 best_consecutive_zeros = consecutive_zeros;
2414 best_start = i - consecutive_zeros;
2420 /* So long as it won't require any more insns to do so, it's
2421 desirable to emit a small constant (in bits 0...9) in the last
2422 insn. This way there is more chance that it can be combined with
2423 a later addressing insn to form a pre-indexed load or store
2424 operation. Consider:
2426 *((volatile int *)0xe0000100) = 1;
2427 *((volatile int *)0xe0000110) = 2;
2429 We want this to wind up as:
2433 str rB, [rA, #0x100]
2435 str rB, [rA, #0x110]
2437 rather than having to synthesize both large constants from scratch.
2439 Therefore, we calculate how many insns would be required to emit
2440 the constant starting from `best_start', and also starting from
2441 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2442 yield a shorter sequence, we may as well use zero. */
2444 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2445 && (count_insns_for_constant (remainder, 0) <=
2446 count_insns_for_constant (remainder, best_start)))
2450 /* Now start emitting the insns. */
2458 if (remainder & (3 << (i - 2)))
2463 temp1 = remainder & ((0x0ff << end)
2464 | ((i < end) ? (0xff >> (32 - end)) : 0));
2465 remainder &= ~temp1;
2469 rtx new_src, temp1_rtx;
2471 if (code == SET || code == MINUS)
2473 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2474 if (can_invert && code != MINUS)
2479 if (remainder && subtargets)
2480 new_src = gen_reg_rtx (mode);
2485 else if (can_negate)
2489 temp1 = trunc_int_for_mode (temp1, mode);
2490 temp1_rtx = GEN_INT (temp1);
2494 else if (code == MINUS)
2495 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2497 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2499 emit_constant_insn (cond,
2500 gen_rtx_SET (VOIDmode, new_src,
2510 else if (code == MINUS)
2519 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2532 /* Canonicalize a comparison so that we are more likely to recognize it.
2533 This can be done for a few constant compares, where we can make the
2534 immediate value easier to load. */
2537 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2540 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2541 unsigned HOST_WIDE_INT maxval;
2542 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2553 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2555 *op1 = GEN_INT (i + 1);
2556 return code == GT ? GE : LT;
2563 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2565 *op1 = GEN_INT (i - 1);
2566 return code == GE ? GT : LE;
2572 if (i != ~((unsigned HOST_WIDE_INT) 0)
2573 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2575 *op1 = GEN_INT (i + 1);
2576 return code == GTU ? GEU : LTU;
2583 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2585 *op1 = GEN_INT (i - 1);
2586 return code == GEU ? GTU : LEU;
2598 /* Define how to find the value returned by a function. */
2601 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2603 enum machine_mode mode;
2604 int unsignedp ATTRIBUTE_UNUSED;
2605 rtx r ATTRIBUTE_UNUSED;
2607 mode = TYPE_MODE (type);
2608 /* Promote integer types. */
2609 if (INTEGRAL_TYPE_P (type))
2610 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2612 /* Promotes small structs returned in a register to full-word size
2613 for big-endian AAPCS. */
2614 if (arm_return_in_msb (type))
2616 HOST_WIDE_INT size = int_size_in_bytes (type);
2617 if (size % UNITS_PER_WORD != 0)
2619 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2620 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2624 return LIBCALL_VALUE(mode);
2627 /* Determine the amount of memory needed to store the possible return
2628 registers of an untyped call. */
2630 arm_apply_result_size (void)
2636 if (TARGET_HARD_FLOAT_ABI)
2640 if (TARGET_MAVERICK)
2643 if (TARGET_IWMMXT_ABI)
2650 /* Decide whether a type should be returned in memory (true)
2651 or in a register (false). This is called by the macro
2652 RETURN_IN_MEMORY. */
2654 arm_return_in_memory (tree type)
2658 if (!AGGREGATE_TYPE_P (type) &&
2659 (TREE_CODE (type) != VECTOR_TYPE) &&
2660 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2661 /* All simple types are returned in registers.
2662 For AAPCS, complex types are treated the same as aggregates. */
2665 size = int_size_in_bytes (type);
2667 if (arm_abi != ARM_ABI_APCS)
2669 /* ATPCS and later return aggregate types in memory only if they are
2670 larger than a word (or are variable size). */
2671 return (size < 0 || size > UNITS_PER_WORD);
2674 /* To maximize backwards compatibility with previous versions of gcc,
2675 return vectors up to 4 words in registers. */
2676 if (TREE_CODE (type) == VECTOR_TYPE)
2677 return (size < 0 || size > (4 * UNITS_PER_WORD));
2679 /* For the arm-wince targets we choose to be compatible with Microsoft's
2680 ARM and Thumb compilers, which always return aggregates in memory. */
2682 /* All structures/unions bigger than one word are returned in memory.
2683 Also catch the case where int_size_in_bytes returns -1. In this case
2684 the aggregate is either huge or of variable size, and in either case
2685 we will want to return it via memory and not in a register. */
2686 if (size < 0 || size > UNITS_PER_WORD)
2689 if (TREE_CODE (type) == RECORD_TYPE)
2693 /* For a struct the APCS says that we only return in a register
2694 if the type is 'integer like' and every addressable element
2695 has an offset of zero. For practical purposes this means
2696 that the structure can have at most one non bit-field element
2697 and that this element must be the first one in the structure. */
2699 /* Find the first field, ignoring non FIELD_DECL things which will
2700 have been created by C++. */
2701 for (field = TYPE_FIELDS (type);
2702 field && TREE_CODE (field) != FIELD_DECL;
2703 field = TREE_CHAIN (field))
2707 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2709 /* Check that the first field is valid for returning in a register. */
2711 /* ... Floats are not allowed */
2712 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2715 /* ... Aggregates that are not themselves valid for returning in
2716 a register are not allowed. */
2717 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2720 /* Now check the remaining fields, if any. Only bitfields are allowed,
2721 since they are not addressable. */
2722 for (field = TREE_CHAIN (field);
2724 field = TREE_CHAIN (field))
2726 if (TREE_CODE (field) != FIELD_DECL)
2729 if (!DECL_BIT_FIELD_TYPE (field))
2736 if (TREE_CODE (type) == UNION_TYPE)
2740 /* Unions can be returned in registers if every element is
2741 integral, or can be returned in an integer register. */
2742 for (field = TYPE_FIELDS (type);
2744 field = TREE_CHAIN (field))
2746 if (TREE_CODE (field) != FIELD_DECL)
2749 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2752 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2758 #endif /* not ARM_WINCE */
2760 /* Return all other types in memory. */
2764 /* Indicate whether or not words of a double are in big-endian order. */
2767 arm_float_words_big_endian (void)
2769 if (TARGET_MAVERICK)
2772 /* For FPA, float words are always big-endian. For VFP, floats words
2773 follow the memory system mode. */
2781 return (TARGET_BIG_END ? 1 : 0);
2786 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2787 for a call to a function whose data type is FNTYPE.
2788 For a library call, FNTYPE is NULL. */
2790 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2791 rtx libname ATTRIBUTE_UNUSED,
2792 tree fndecl ATTRIBUTE_UNUSED)
2794 /* On the ARM, the offset starts at 0. */
2796 pcum->iwmmxt_nregs = 0;
2797 pcum->can_split = true;
2799 /* Varargs vectors are treated the same as long long.
2800 named_count avoids having to change the way arm handles 'named' */
2801 pcum->named_count = 0;
2804 if (TARGET_REALLY_IWMMXT && fntype)
2808 for (fn_arg = TYPE_ARG_TYPES (fntype);
2810 fn_arg = TREE_CHAIN (fn_arg))
2811 pcum->named_count += 1;
2813 if (! pcum->named_count)
2814 pcum->named_count = INT_MAX;
2819 /* Return true if mode/type need doubleword alignment. */
2821 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2823 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2824 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2828 /* Determine where to put an argument to a function.
2829 Value is zero to push the argument on the stack,
2830 or a hard register in which to store the argument.
2832 MODE is the argument's machine mode.
2833 TYPE is the data type of the argument (as a tree).
2834 This is null for libcalls where that information may
2836 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2837 the preceding args and about the function being called.
2838 NAMED is nonzero if this argument is a named parameter
2839 (otherwise it is an extra parameter matching an ellipsis). */
2842 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2843 tree type, int named)
2847 /* Varargs vectors are treated the same as long long.
2848 named_count avoids having to change the way arm handles 'named' */
2849 if (TARGET_IWMMXT_ABI
2850 && arm_vector_mode_supported_p (mode)
2851 && pcum->named_count > pcum->nargs + 1)
2853 if (pcum->iwmmxt_nregs <= 9)
2854 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2857 pcum->can_split = false;
2862 /* Put doubleword aligned quantities in even register pairs. */
2864 && ARM_DOUBLEWORD_ALIGN
2865 && arm_needs_doubleword_align (mode, type))
2868 if (mode == VOIDmode)
2869 /* Pick an arbitrary value for operand 2 of the call insn. */
2872 /* Only allow splitting an arg between regs and memory if all preceding
2873 args were allocated to regs. For args passed by reference we only count
2874 the reference pointer. */
2875 if (pcum->can_split)
2878 nregs = ARM_NUM_REGS2 (mode, type);
2880 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2883 return gen_rtx_REG (mode, pcum->nregs);
2887 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2888 tree type, bool named ATTRIBUTE_UNUSED)
2890 int nregs = pcum->nregs;
2892 if (arm_vector_mode_supported_p (mode))
2895 if (NUM_ARG_REGS > nregs
2896 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2898 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2903 /* Variable sized types are passed by reference. This is a GCC
2904 extension to the ARM ABI. */
2907 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2908 enum machine_mode mode ATTRIBUTE_UNUSED,
2909 tree type, bool named ATTRIBUTE_UNUSED)
2911 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2914 /* Encode the current state of the #pragma [no_]long_calls. */
2917 OFF, /* No #pragma [no_]long_calls is in effect. */
2918 LONG, /* #pragma long_calls is in effect. */
2919 SHORT /* #pragma no_long_calls is in effect. */
2922 static arm_pragma_enum arm_pragma_long_calls = OFF;
2925 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2927 arm_pragma_long_calls = LONG;
2931 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2933 arm_pragma_long_calls = SHORT;
2937 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2939 arm_pragma_long_calls = OFF;
2942 /* Table of machine attributes. */
2943 const struct attribute_spec arm_attribute_table[] =
2945 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2946 /* Function calls made to this symbol must be done indirectly, because
2947 it may lie outside of the 26 bit addressing range of a normal function
2949 { "long_call", 0, 0, false, true, true, NULL },
2950 /* Whereas these functions are always known to reside within the 26 bit
2951 addressing range. */
2952 { "short_call", 0, 0, false, true, true, NULL },
2953 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2954 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2955 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2956 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2958 /* ARM/PE has three new attributes:
2960 dllexport - for exporting a function/variable that will live in a dll
2961 dllimport - for importing a function/variable from a dll
2963 Microsoft allows multiple declspecs in one __declspec, separating
2964 them with spaces. We do NOT support this. Instead, use __declspec
2967 { "dllimport", 0, 0, true, false, false, NULL },
2968 { "dllexport", 0, 0, true, false, false, NULL },
2969 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2970 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2971 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2972 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2973 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2975 { NULL, 0, 0, false, false, false, NULL }
2978 /* Handle an attribute requiring a FUNCTION_DECL;
2979 arguments as in struct attribute_spec.handler. */
2981 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2982 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2984 if (TREE_CODE (*node) != FUNCTION_DECL)
2986 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2987 IDENTIFIER_POINTER (name));
2988 *no_add_attrs = true;
2994 /* Handle an "interrupt" or "isr" attribute;
2995 arguments as in struct attribute_spec.handler. */
2997 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3002 if (TREE_CODE (*node) != FUNCTION_DECL)
3004 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3005 IDENTIFIER_POINTER (name));
3006 *no_add_attrs = true;
3008 /* FIXME: the argument if any is checked for type attributes;
3009 should it be checked for decl ones? */
3013 if (TREE_CODE (*node) == FUNCTION_TYPE
3014 || TREE_CODE (*node) == METHOD_TYPE)
3016 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3018 warning (OPT_Wattributes, "%qs attribute ignored",
3019 IDENTIFIER_POINTER (name));
3020 *no_add_attrs = true;
3023 else if (TREE_CODE (*node) == POINTER_TYPE
3024 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3025 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3026 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3028 *node = build_variant_type_copy (*node);
3029 TREE_TYPE (*node) = build_type_attribute_variant
3031 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3032 *no_add_attrs = true;
3036 /* Possibly pass this attribute on from the type to a decl. */
3037 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3038 | (int) ATTR_FLAG_FUNCTION_NEXT
3039 | (int) ATTR_FLAG_ARRAY_NEXT))
3041 *no_add_attrs = true;
3042 return tree_cons (name, args, NULL_TREE);
3046 warning (OPT_Wattributes, "%qs attribute ignored",
3047 IDENTIFIER_POINTER (name));
3055 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3056 /* Handle the "notshared" attribute. This attribute is another way of
3057 requesting hidden visibility. ARM's compiler supports
3058 "__declspec(notshared)"; we support the same thing via an
3062 arm_handle_notshared_attribute (tree *node,
3063 tree name ATTRIBUTE_UNUSED,
3064 tree args ATTRIBUTE_UNUSED,
3065 int flags ATTRIBUTE_UNUSED,
3068 tree decl = TYPE_NAME (*node);
3072 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3073 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3074 *no_add_attrs = false;
3080 /* Return 0 if the attributes for two types are incompatible, 1 if they
3081 are compatible, and 2 if they are nearly compatible (which causes a
3082 warning to be generated). */
3084 arm_comp_type_attributes (tree type1, tree type2)
3088 /* Check for mismatch of non-default calling convention. */
3089 if (TREE_CODE (type1) != FUNCTION_TYPE)
3092 /* Check for mismatched call attributes. */
3093 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3094 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3095 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3096 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3098 /* Only bother to check if an attribute is defined. */
3099 if (l1 | l2 | s1 | s2)
3101 /* If one type has an attribute, the other must have the same attribute. */
3102 if ((l1 != l2) || (s1 != s2))
3105 /* Disallow mixed attributes. */
3106 if ((l1 & s2) || (l2 & s1))
3110 /* Check for mismatched ISR attribute. */
3111 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3113 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3114 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3116 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3123 /* Assigns default attributes to newly defined type. This is used to
3124 set short_call/long_call attributes for function types of
3125 functions defined inside corresponding #pragma scopes. */
3127 arm_set_default_type_attributes (tree type)
3129 /* Add __attribute__ ((long_call)) to all functions, when
3130 inside #pragma long_calls or __attribute__ ((short_call)),
3131 when inside #pragma no_long_calls. */
3132 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3134 tree type_attr_list, attr_name;
3135 type_attr_list = TYPE_ATTRIBUTES (type);
3137 if (arm_pragma_long_calls == LONG)
3138 attr_name = get_identifier ("long_call");
3139 else if (arm_pragma_long_calls == SHORT)
3140 attr_name = get_identifier ("short_call");
3144 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3145 TYPE_ATTRIBUTES (type) = type_attr_list;
3149 /* Return true if DECL is known to be linked into section SECTION. */
3152 arm_function_in_section_p (tree decl, section *section)
3154 /* We can only be certain about functions defined in the same
3155 compilation unit. */
3156 if (!TREE_STATIC (decl))
3159 /* Make sure that SYMBOL always binds to the definition in this
3160 compilation unit. */
3161 if (!targetm.binds_local_p (decl))
3164 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3165 if (!DECL_SECTION_NAME (decl))
3167 /* Only cater for unit-at-a-time mode, where we know that the user
3168 cannot later specify a section for DECL. */
3169 if (!flag_unit_at_a_time)
3172 /* Make sure that we will not create a unique section for DECL. */
3173 if (flag_function_sections || DECL_ONE_ONLY (decl))
3177 return function_section (decl) == section;
3180 /* Return nonzero if a 32-bit "long_call" should be generated for
3181 a call from the current function to DECL. We generate a long_call
3184 a. has an __attribute__((long call))
3185 or b. is within the scope of a #pragma long_calls
3186 or c. the -mlong-calls command line switch has been specified
3188 However we do not generate a long call if the function:
3190 d. has an __attribute__ ((short_call))
3191 or e. is inside the scope of a #pragma no_long_calls
3192 or f. is defined in the same section as the current function. */
3195 arm_is_long_call_p (tree decl)
3200 return TARGET_LONG_CALLS;
3202 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3203 if (lookup_attribute ("short_call", attrs))
3206 /* For "f", be conservative, and only cater for cases in which the
3207 whole of the current function is placed in the same section. */
3208 if (!flag_reorder_blocks_and_partition
3209 && arm_function_in_section_p (decl, current_function_section ()))
3212 if (lookup_attribute ("long_call", attrs))
3215 return TARGET_LONG_CALLS;
3218 /* Return nonzero if it is ok to make a tail-call to DECL. */
3220 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3222 unsigned long func_type;
3224 if (cfun->machine->sibcall_blocked)
3227 /* Never tailcall something for which we have no decl, or if we
3228 are in Thumb mode. */
3229 if (decl == NULL || TARGET_THUMB)
3232 /* The PIC register is live on entry to VxWorks PLT entries, so we
3233 must make the call before restoring the PIC register. */
3234 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
3237 /* Cannot tail-call to long calls, since these are out of range of
3238 a branch instruction. */
3239 if (arm_is_long_call_p (decl))
3242 /* If we are interworking and the function is not declared static
3243 then we can't tail-call it unless we know that it exists in this
3244 compilation unit (since it might be a Thumb routine). */
3245 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3248 func_type = arm_current_func_type ();
3249 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3250 if (IS_INTERRUPT (func_type))
3253 /* Never tailcall if function may be called with a misaligned SP. */
3254 if (IS_STACKALIGN (func_type))
3257 /* Everything else is ok. */
3262 /* Addressing mode support functions. */
3264 /* Return nonzero if X is a legitimate immediate operand when compiling
3265 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3267 legitimate_pic_operand_p (rtx x)
3269 if (GET_CODE (x) == SYMBOL_REF
3270 || (GET_CODE (x) == CONST
3271 && GET_CODE (XEXP (x, 0)) == PLUS
3272 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3278 /* Record that the current function needs a PIC register. Initialize
3279 cfun->machine->pic_reg if we have not already done so. */
3282 require_pic_register (void)
3284 /* A lot of the logic here is made obscure by the fact that this
3285 routine gets called as part of the rtx cost estimation process.
3286 We don't want those calls to affect any assumptions about the real
3287 function; and further, we can't call entry_of_function() until we
3288 start the real expansion process. */
3289 if (!current_function_uses_pic_offset_table)
3291 gcc_assert (!no_new_pseudos);
3292 if (arm_pic_register != INVALID_REGNUM)
3294 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3296 /* Play games to avoid marking the function as needing pic
3297 if we are being called as part of the cost-estimation
3299 if (current_ir_type () != IR_GIMPLE)
3300 current_function_uses_pic_offset_table = 1;
3306 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3308 /* Play games to avoid marking the function as needing pic
3309 if we are being called as part of the cost-estimation
3311 if (current_ir_type () != IR_GIMPLE)
3313 current_function_uses_pic_offset_table = 1;
3316 arm_load_pic_register (0UL);
3320 emit_insn_after (seq, entry_of_function ());
3327 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3329 if (GET_CODE (orig) == SYMBOL_REF
3330 || GET_CODE (orig) == LABEL_REF)
3332 #ifndef AOF_ASSEMBLER
3333 rtx pic_ref, address;
3338 /* If this function doesn't have a pic register, create one now. */
3339 require_pic_register ();
3343 gcc_assert (!no_new_pseudos);
3344 reg = gen_reg_rtx (Pmode);
3349 #ifdef AOF_ASSEMBLER
3350 /* The AOF assembler can generate relocations for these directly, and
3351 understands that the PIC register has to be added into the offset. */
3352 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3355 address = gen_reg_rtx (Pmode);
3360 emit_insn (gen_pic_load_addr_arm (address, orig));
3361 else if (TARGET_THUMB2)
3362 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3363 else /* TARGET_THUMB1 */
3364 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3366 /* VxWorks does not impose a fixed gap between segments; the run-time
3367 gap can be different from the object-file gap. We therefore can't
3368 use GOTOFF unless we are absolutely sure that the symbol is in the
3369 same segment as the GOT. Unfortunately, the flexibility of linker
3370 scripts means that we can't be sure of that in general, so assume
3371 that GOTOFF is never valid on VxWorks. */
3372 if ((GET_CODE (orig) == LABEL_REF
3373 || (GET_CODE (orig) == SYMBOL_REF &&
3374 SYMBOL_REF_LOCAL_P (orig)))
3376 && !TARGET_VXWORKS_RTP)
3377 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3380 pic_ref = gen_const_mem (Pmode,
3381 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3385 insn = emit_move_insn (reg, pic_ref);
3387 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3389 set_unique_reg_note (insn, REG_EQUAL, orig);
3393 else if (GET_CODE (orig) == CONST)
3397 if (GET_CODE (XEXP (orig, 0)) == PLUS
3398 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3401 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3402 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3407 gcc_assert (!no_new_pseudos);
3408 reg = gen_reg_rtx (Pmode);
3411 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3413 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3414 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3415 base == reg ? 0 : reg);
3417 if (GET_CODE (offset) == CONST_INT)
3419 /* The base register doesn't really matter, we only want to
3420 test the index for the appropriate mode. */
3421 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3423 gcc_assert (!no_new_pseudos);
3424 offset = force_reg (Pmode, offset);
3427 if (GET_CODE (offset) == CONST_INT)
3428 return plus_constant (base, INTVAL (offset));
3431 if (GET_MODE_SIZE (mode) > 4
3432 && (GET_MODE_CLASS (mode) == MODE_INT
3433 || TARGET_SOFT_FLOAT))
3435 emit_insn (gen_addsi3 (reg, base, offset));
3439 return gen_rtx_PLUS (Pmode, base, offset);
3446 /* Find a spare register to use during the prolog of a function. */
3449 thumb_find_work_register (unsigned long pushed_regs_mask)
3453 /* Check the argument registers first as these are call-used. The
3454 register allocation order means that sometimes r3 might be used
3455 but earlier argument registers might not, so check them all. */
3456 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3457 if (!regs_ever_live[reg])
3460 /* Before going on to check the call-saved registers we can try a couple
3461 more ways of deducing that r3 is available. The first is when we are
3462 pushing anonymous arguments onto the stack and we have less than 4
3463 registers worth of fixed arguments(*). In this case r3 will be part of
3464 the variable argument list and so we can be sure that it will be
3465 pushed right at the start of the function. Hence it will be available
3466 for the rest of the prologue.
3467 (*): ie current_function_pretend_args_size is greater than 0. */
3468 if (cfun->machine->uses_anonymous_args
3469 && current_function_pretend_args_size > 0)
3470 return LAST_ARG_REGNUM;
3472 /* The other case is when we have fixed arguments but less than 4 registers
3473 worth. In this case r3 might be used in the body of the function, but
3474 it is not being used to convey an argument into the function. In theory
3475 we could just check current_function_args_size to see how many bytes are
3476 being passed in argument registers, but it seems that it is unreliable.
3477 Sometimes it will have the value 0 when in fact arguments are being
3478 passed. (See testcase execute/20021111-1.c for an example). So we also
3479 check the args_info.nregs field as well. The problem with this field is
3480 that it makes no allowances for arguments that are passed to the
3481 function but which are not used. Hence we could miss an opportunity
3482 when a function has an unused argument in r3. But it is better to be
3483 safe than to be sorry. */
3484 if (! cfun->machine->uses_anonymous_args
3485 && current_function_args_size >= 0
3486 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3487 && cfun->args_info.nregs < 4)
3488 return LAST_ARG_REGNUM;
3490 /* Otherwise look for a call-saved register that is going to be pushed. */
3491 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3492 if (pushed_regs_mask & (1 << reg))
3497 /* Thumb-2 can use high regs. */
3498 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3499 if (pushed_regs_mask & (1 << reg))
3502 /* Something went wrong - thumb_compute_save_reg_mask()
3503 should have arranged for a suitable register to be pushed. */
3507 static GTY(()) int pic_labelno;
3509 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3513 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3515 #ifndef AOF_ASSEMBLER
3516 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
3517 rtx global_offset_table;
3519 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3522 gcc_assert (flag_pic);
3524 pic_reg = cfun->machine->pic_reg;
3525 if (TARGET_VXWORKS_RTP)
3527 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
3528 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3529 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3531 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
3533 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
3534 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
3538 /* We use an UNSPEC rather than a LABEL_REF because this label
3539 never appears in the code stream. */
3541 labelno = GEN_INT (pic_labelno++);
3542 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3543 l1 = gen_rtx_CONST (VOIDmode, l1);
3546 = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3547 /* On the ARM the PC register contains 'dot + 8' at the time of the
3548 addition, on the Thumb it is 'dot + 4'. */
3549 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3552 pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
3553 pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
3556 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3558 pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
3559 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3563 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3564 emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno));
3566 else if (TARGET_THUMB2)
3568 /* Thumb-2 only allows very limited access to the PC. Calculate the
3569 address in a temporary register. */
3570 if (arm_pic_register != INVALID_REGNUM)
3572 pic_tmp = gen_rtx_REG (SImode,
3573 thumb_find_work_register (saved_regs));
3577 gcc_assert (!no_new_pseudos);
3578 pic_tmp = gen_reg_rtx (Pmode);
3581 emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx));
3582 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3583 emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp));
3585 else /* TARGET_THUMB1 */
3587 if (arm_pic_register != INVALID_REGNUM
3588 && REGNO (pic_reg) > LAST_LO_REGNUM)
3590 /* We will have pushed the pic register, so we should always be
3591 able to find a work register. */
3592 pic_tmp = gen_rtx_REG (SImode,
3593 thumb_find_work_register (saved_regs));
3594 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3595 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3598 emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx));
3599 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
3603 /* Need to emit this whether or not we obey regdecls,
3604 since setjmp/longjmp can cause life info to screw up. */
3605 emit_insn (gen_rtx_USE (VOIDmode, pic_reg));
3606 #endif /* AOF_ASSEMBLER */
3610 /* Return nonzero if X is valid as an ARM state addressing register. */
3612 arm_address_register_rtx_p (rtx x, int strict_p)
3616 if (GET_CODE (x) != REG)
3622 return ARM_REGNO_OK_FOR_BASE_P (regno);
3624 return (regno <= LAST_ARM_REGNUM
3625 || regno >= FIRST_PSEUDO_REGISTER
3626 || regno == FRAME_POINTER_REGNUM
3627 || regno == ARG_POINTER_REGNUM);
3630 /* Return TRUE if this rtx is the difference of a symbol and a label,
3631 and will reduce to a PC-relative relocation in the object file.
3632 Expressions like this can be left alone when generating PIC, rather
3633 than forced through the GOT. */
3635 pcrel_constant_p (rtx x)
3637 if (GET_CODE (x) == MINUS)
3638 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3643 /* Return nonzero if X is a valid ARM state address operand. */
3645 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3649 enum rtx_code code = GET_CODE (x);
3651 if (arm_address_register_rtx_p (x, strict_p))
3654 use_ldrd = (TARGET_LDRD
3656 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3658 if (code == POST_INC || code == PRE_DEC
3659 || ((code == PRE_INC || code == POST_DEC)
3660 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3661 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3663 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3664 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3665 && GET_CODE (XEXP (x, 1)) == PLUS
3666 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3668 rtx addend = XEXP (XEXP (x, 1), 1);
3670 /* Don't allow ldrd post increment by register because it's hard
3671 to fixup invalid register choices. */
3673 && GET_CODE (x) == POST_MODIFY
3674 && GET_CODE (addend) == REG)
3677 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3678 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3681 /* After reload constants split into minipools will have addresses
3682 from a LABEL_REF. */
3683 else if (reload_completed
3684 && (code == LABEL_REF
3686 && GET_CODE (XEXP (x, 0)) == PLUS
3687 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3688 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3691 else if (mode == TImode)
3694 else if (code == PLUS)
3696 rtx xop0 = XEXP (x, 0);
3697 rtx xop1 = XEXP (x, 1);
3699 return ((arm_address_register_rtx_p (xop0, strict_p)
3700 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3701 || (arm_address_register_rtx_p (xop1, strict_p)
3702 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3706 /* Reload currently can't handle MINUS, so disable this for now */
3707 else if (GET_CODE (x) == MINUS)
3709 rtx xop0 = XEXP (x, 0);
3710 rtx xop1 = XEXP (x, 1);
3712 return (arm_address_register_rtx_p (xop0, strict_p)
3713 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3717 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3718 && code == SYMBOL_REF
3719 && CONSTANT_POOL_ADDRESS_P (x)
3721 && symbol_mentioned_p (get_pool_constant (x))
3722 && ! pcrel_constant_p (get_pool_constant (x))))
3728 /* Return nonzero if X is a valid Thumb-2 address operand. */
3730 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3733 enum rtx_code code = GET_CODE (x);
3735 if (arm_address_register_rtx_p (x, strict_p))
3738 use_ldrd = (TARGET_LDRD
3740 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3742 if (code == POST_INC || code == PRE_DEC
3743 || ((code == PRE_INC || code == POST_DEC)
3744 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3745 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3747 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3748 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3749 && GET_CODE (XEXP (x, 1)) == PLUS
3750 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3752 /* Thumb-2 only has autoincrement by constant. */
3753 rtx addend = XEXP (XEXP (x, 1), 1);
3754 HOST_WIDE_INT offset;
3756 if (GET_CODE (addend) != CONST_INT)
3759 offset = INTVAL(addend);
3760 if (GET_MODE_SIZE (mode) <= 4)
3761 return (offset > -256 && offset < 256);
3763 return (use_ldrd && offset > -1024 && offset < 1024
3764 && (offset & 3) == 0);
3767 /* After reload constants split into minipools will have addresses
3768 from a LABEL_REF. */
3769 else if (reload_completed
3770 && (code == LABEL_REF
3772 && GET_CODE (XEXP (x, 0)) == PLUS
3773 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3774 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3777 else if (mode == TImode)
3780 else if (code == PLUS)
3782 rtx xop0 = XEXP (x, 0);
3783 rtx xop1 = XEXP (x, 1);
3785 return ((arm_address_register_rtx_p (xop0, strict_p)
3786 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3787 || (arm_address_register_rtx_p (xop1, strict_p)
3788 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3791 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3792 && code == SYMBOL_REF
3793 && CONSTANT_POOL_ADDRESS_P (x)
3795 && symbol_mentioned_p (get_pool_constant (x))
3796 && ! pcrel_constant_p (get_pool_constant (x))))
3802 /* Return nonzero if INDEX is valid for an address index operand in
3805 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3808 HOST_WIDE_INT range;
3809 enum rtx_code code = GET_CODE (index);
3811 /* Standard coprocessor addressing modes. */
3812 if (TARGET_HARD_FLOAT
3813 && (TARGET_FPA || TARGET_MAVERICK)
3814 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3815 || (TARGET_MAVERICK && mode == DImode)))
3816 return (code == CONST_INT && INTVAL (index) < 1024
3817 && INTVAL (index) > -1024
3818 && (INTVAL (index) & 3) == 0);
3820 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3821 return (code == CONST_INT
3822 && INTVAL (index) < 1024
3823 && INTVAL (index) > -1024
3824 && (INTVAL (index) & 3) == 0);
3826 if (arm_address_register_rtx_p (index, strict_p)
3827 && (GET_MODE_SIZE (mode) <= 4))
3830 if (mode == DImode || mode == DFmode)
3832 if (code == CONST_INT)
3834 HOST_WIDE_INT val = INTVAL (index);
3837 return val > -256 && val < 256;
3839 return val > -4096 && val < 4092;
3842 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3845 if (GET_MODE_SIZE (mode) <= 4
3848 || (mode == QImode && outer == SIGN_EXTEND))))
3852 rtx xiop0 = XEXP (index, 0);
3853 rtx xiop1 = XEXP (index, 1);
3855 return ((arm_address_register_rtx_p (xiop0, strict_p)
3856 && power_of_two_operand (xiop1, SImode))
3857 || (arm_address_register_rtx_p (xiop1, strict_p)
3858 && power_of_two_operand (xiop0, SImode)));
3860 else if (code == LSHIFTRT || code == ASHIFTRT
3861 || code == ASHIFT || code == ROTATERT)
3863 rtx op = XEXP (index, 1);
3865 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3866 && GET_CODE (op) == CONST_INT
3868 && INTVAL (op) <= 31);
3872 /* For ARM v4 we may be doing a sign-extend operation during the
3876 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3882 range = (mode == HImode) ? 4095 : 4096;
3884 return (code == CONST_INT
3885 && INTVAL (index) < range
3886 && INTVAL (index) > -range);
3889 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3890 index operand. i.e. 1, 2, 4 or 8. */
3892 thumb2_index_mul_operand (rtx op)
3896 if (GET_CODE(op) != CONST_INT)
3900 return (val == 1 || val == 2 || val == 4 || val == 8);
3903 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3905 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
3907 enum rtx_code code = GET_CODE (index);
3909 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3910 /* Standard coprocessor addressing modes. */
3911 if (TARGET_HARD_FLOAT
3912 && (TARGET_FPA || TARGET_MAVERICK)
3913 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3914 || (TARGET_MAVERICK && mode == DImode)))
3915 return (code == CONST_INT && INTVAL (index) < 1024
3916 && INTVAL (index) > -1024
3917 && (INTVAL (index) & 3) == 0);
3919 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3921 /* For DImode assume values will usually live in core regs
3922 and only allow LDRD addressing modes. */
3923 if (!TARGET_LDRD || mode != DImode)
3924 return (code == CONST_INT
3925 && INTVAL (index) < 1024
3926 && INTVAL (index) > -1024
3927 && (INTVAL (index) & 3) == 0);
3930 if (arm_address_register_rtx_p (index, strict_p)
3931 && (GET_MODE_SIZE (mode) <= 4))
3934 if (mode == DImode || mode == DFmode)
3936 HOST_WIDE_INT val = INTVAL (index);
3937 /* ??? Can we assume ldrd for thumb2? */
3938 /* Thumb-2 ldrd only has reg+const addressing modes. */
3939 if (code != CONST_INT)
3942 /* ldrd supports offsets of +-1020.
3943 However the ldr fallback does not. */
3944 return val > -256 && val < 256 && (val & 3) == 0;
3949 rtx xiop0 = XEXP (index, 0);
3950 rtx xiop1 = XEXP (index, 1);
3952 return ((arm_address_register_rtx_p (xiop0, strict_p)
3953 && thumb2_index_mul_operand (xiop1))
3954 || (arm_address_register_rtx_p (xiop1, strict_p)
3955 && thumb2_index_mul_operand (xiop0)));
3957 else if (code == ASHIFT)
3959 rtx op = XEXP (index, 1);
3961 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3962 && GET_CODE (op) == CONST_INT
3964 && INTVAL (op) <= 3);
3967 return (code == CONST_INT
3968 && INTVAL (index) < 4096
3969 && INTVAL (index) > -256);
3972 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3974 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3978 if (GET_CODE (x) != REG)
3984 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3986 return (regno <= LAST_LO_REGNUM
3987 || regno > LAST_VIRTUAL_REGISTER
3988 || regno == FRAME_POINTER_REGNUM
3989 || (GET_MODE_SIZE (mode) >= 4
3990 && (regno == STACK_POINTER_REGNUM
3991 || regno >= FIRST_PSEUDO_REGISTER
3992 || x == hard_frame_pointer_rtx
3993 || x == arg_pointer_rtx)));
3996 /* Return nonzero if x is a legitimate index register. This is the case
3997 for any base register that can access a QImode object. */
3999 thumb1_index_register_rtx_p (rtx x, int strict_p)
4001 return thumb1_base_register_rtx_p (x, QImode, strict_p);
4004 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4006 The AP may be eliminated to either the SP or the FP, so we use the
4007 least common denominator, e.g. SImode, and offsets from 0 to 64.
4009 ??? Verify whether the above is the right approach.
4011 ??? Also, the FP may be eliminated to the SP, so perhaps that
4012 needs special handling also.
4014 ??? Look at how the mips16 port solves this problem. It probably uses
4015 better ways to solve some of these problems.
4017 Although it is not incorrect, we don't accept QImode and HImode
4018 addresses based on the frame pointer or arg pointer until the
4019 reload pass starts. This is so that eliminating such addresses
4020 into stack based ones won't produce impossible code. */
4022 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
4024 /* ??? Not clear if this is right. Experiment. */
4025 if (GET_MODE_SIZE (mode) < 4
4026 && !(reload_in_progress || reload_completed)
4027 && (reg_mentioned_p (frame_pointer_rtx, x)
4028 || reg_mentioned_p (arg_pointer_rtx, x)
4029 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4030 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4031 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4032 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4035 /* Accept any base register. SP only in SImode or larger. */
4036 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
4039 /* This is PC relative data before arm_reorg runs. */
4040 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4041 && GET_CODE (x) == SYMBOL_REF
4042 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
4045 /* This is PC relative data after arm_reorg runs. */
4046 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4047 && (GET_CODE (x) == LABEL_REF
4048 || (GET_CODE (x) == CONST
4049 && GET_CODE (XEXP (x, 0)) == PLUS
4050 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4051 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4054 /* Post-inc indexing only supported for SImode and larger. */
4055 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4056 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4059 else if (GET_CODE (x) == PLUS)
4061 /* REG+REG address can be any two index registers. */
4062 /* We disallow FRAME+REG addressing since we know that FRAME
4063 will be replaced with STACK, and SP relative addressing only
4064 permits SP+OFFSET. */
4065 if (GET_MODE_SIZE (mode) <= 4
4066 && XEXP (x, 0) != frame_pointer_rtx
4067 && XEXP (x, 1) != frame_pointer_rtx
4068 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4069 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4072 /* REG+const has 5-7 bit offset for non-SP registers. */
4073 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4074 || XEXP (x, 0) == arg_pointer_rtx)
4075 && GET_CODE (XEXP (x, 1)) == CONST_INT
4076 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4079 /* REG+const has 10-bit offset for SP, but only SImode and
4080 larger is supported. */
4081 /* ??? Should probably check for DI/DFmode overflow here
4082 just like GO_IF_LEGITIMATE_OFFSET does. */
4083 else if (GET_CODE (XEXP (x, 0)) == REG
4084 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4085 && GET_MODE_SIZE (mode) >= 4
4086 && GET_CODE (XEXP (x, 1)) == CONST_INT
4087 && INTVAL (XEXP (x, 1)) >= 0
4088 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4089 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4092 else if (GET_CODE (XEXP (x, 0)) == REG
4093 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4094 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4095 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4096 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4097 && GET_MODE_SIZE (mode) >= 4
4098 && GET_CODE (XEXP (x, 1)) == CONST_INT
4099 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4103 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4104 && GET_MODE_SIZE (mode) == 4
4105 && GET_CODE (x) == SYMBOL_REF
4106 && CONSTANT_POOL_ADDRESS_P (x)
4108 && symbol_mentioned_p (get_pool_constant (x))
4109 && ! pcrel_constant_p (get_pool_constant (x))))
4115 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4116 instruction of mode MODE. */
4118 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4120 switch (GET_MODE_SIZE (mode))
4123 return val >= 0 && val < 32;
4126 return val >= 0 && val < 64 && (val & 1) == 0;
4130 && (val + GET_MODE_SIZE (mode)) <= 128
4135 /* Build the SYMBOL_REF for __tls_get_addr. */
4137 static GTY(()) rtx tls_get_addr_libfunc;
4140 get_tls_get_addr (void)
4142 if (!tls_get_addr_libfunc)
4143 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4144 return tls_get_addr_libfunc;
4148 arm_load_tp (rtx target)
4151 target = gen_reg_rtx (SImode);
4155 /* Can return in any reg. */
4156 emit_insn (gen_load_tp_hard (target));
4160 /* Always returned in r0. Immediately copy the result into a pseudo,
4161 otherwise other uses of r0 (e.g. setting up function arguments) may
4162 clobber the value. */
4166 emit_insn (gen_load_tp_soft ());
4168 tmp = gen_rtx_REG (SImode, 0);
4169 emit_move_insn (target, tmp);
4175 load_tls_operand (rtx x, rtx reg)
4179 if (reg == NULL_RTX)
4180 reg = gen_reg_rtx (SImode);
4182 tmp = gen_rtx_CONST (SImode, x);
4184 emit_move_insn (reg, tmp);
4190 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4192 rtx insns, label, labelno, sum;
4196 labelno = GEN_INT (pic_labelno++);
4197 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4198 label = gen_rtx_CONST (VOIDmode, label);
4200 sum = gen_rtx_UNSPEC (Pmode,
4201 gen_rtvec (4, x, GEN_INT (reloc), label,
4202 GEN_INT (TARGET_ARM ? 8 : 4)),
4204 reg = load_tls_operand (sum, reg);
4207 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4208 else if (TARGET_THUMB2)
4211 /* Thumb-2 only allows very limited access to the PC. Calculate
4212 the address in a temporary register. */
4213 tmp = gen_reg_rtx (SImode);
4214 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4215 emit_insn (gen_addsi3(reg, reg, tmp));
4217 else /* TARGET_THUMB1 */
4218 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4220 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4221 Pmode, 1, reg, Pmode);
4223 insns = get_insns ();
4230 legitimize_tls_address (rtx x, rtx reg)
4232 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4233 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4237 case TLS_MODEL_GLOBAL_DYNAMIC:
4238 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4239 dest = gen_reg_rtx (Pmode);
4240 emit_libcall_block (insns, dest, ret, x);
4243 case TLS_MODEL_LOCAL_DYNAMIC:
4244 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4246 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4247 share the LDM result with other LD model accesses. */
4248 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4250 dest = gen_reg_rtx (Pmode);
4251 emit_libcall_block (insns, dest, ret, eqv);
4253 /* Load the addend. */
4254 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4256 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4257 return gen_rtx_PLUS (Pmode, dest, addend);
4259 case TLS_MODEL_INITIAL_EXEC:
4260 labelno = GEN_INT (pic_labelno++);
4261 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4262 label = gen_rtx_CONST (VOIDmode, label);
4263 sum = gen_rtx_UNSPEC (Pmode,
4264 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4265 GEN_INT (TARGET_ARM ? 8 : 4)),
4267 reg = load_tls_operand (sum, reg);
4270 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4271 else if (TARGET_THUMB2)
4274 /* Thumb-2 only allows very limited access to the PC. Calculate
4275 the address in a temporary register. */
4276 tmp = gen_reg_rtx (SImode);
4277 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4278 emit_insn (gen_addsi3(reg, reg, tmp));
4279 emit_move_insn (reg, gen_const_mem (SImode, reg));
4283 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4284 emit_move_insn (reg, gen_const_mem (SImode, reg));
4287 tp = arm_load_tp (NULL_RTX);
4289 return gen_rtx_PLUS (Pmode, tp, reg);
4291 case TLS_MODEL_LOCAL_EXEC:
4292 tp = arm_load_tp (NULL_RTX);
4294 reg = gen_rtx_UNSPEC (Pmode,
4295 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4297 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4299 return gen_rtx_PLUS (Pmode, tp, reg);
4306 /* Try machine-dependent ways of modifying an illegitimate address
4307 to be legitimate. If we find one, return the new, valid address. */
4309 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4311 if (arm_tls_symbol_p (x))
4312 return legitimize_tls_address (x, NULL_RTX);
4314 if (GET_CODE (x) == PLUS)
4316 rtx xop0 = XEXP (x, 0);
4317 rtx xop1 = XEXP (x, 1);
4319 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4320 xop0 = force_reg (SImode, xop0);
4322 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4323 xop1 = force_reg (SImode, xop1);
4325 if (ARM_BASE_REGISTER_RTX_P (xop0)
4326 && GET_CODE (xop1) == CONST_INT)
4328 HOST_WIDE_INT n, low_n;
4332 /* VFP addressing modes actually allow greater offsets, but for
4333 now we just stick with the lowest common denominator. */
4335 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4347 low_n = ((mode) == TImode ? 0
4348 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4352 base_reg = gen_reg_rtx (SImode);
4353 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4354 emit_move_insn (base_reg, val);
4355 x = plus_constant (base_reg, low_n);
4357 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4358 x = gen_rtx_PLUS (SImode, xop0, xop1);
4361 /* XXX We don't allow MINUS any more -- see comment in
4362 arm_legitimate_address_p (). */
4363 else if (GET_CODE (x) == MINUS)
4365 rtx xop0 = XEXP (x, 0);
4366 rtx xop1 = XEXP (x, 1);
4368 if (CONSTANT_P (xop0))
4369 xop0 = force_reg (SImode, xop0);
4371 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4372 xop1 = force_reg (SImode, xop1);
4374 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4375 x = gen_rtx_MINUS (SImode, xop0, xop1);
4378 /* Make sure to take full advantage of the pre-indexed addressing mode
4379 with absolute addresses which often allows for the base register to
4380 be factorized for multiple adjacent memory references, and it might
4381 even allows for the mini pool to be avoided entirely. */
4382 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4385 HOST_WIDE_INT mask, base, index;
4388 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4389 use a 8-bit index. So let's use a 12-bit index for SImode only and
4390 hope that arm_gen_constant will enable ldrb to use more bits. */
4391 bits = (mode == SImode) ? 12 : 8;
4392 mask = (1 << bits) - 1;
4393 base = INTVAL (x) & ~mask;
4394 index = INTVAL (x) & mask;
4395 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4397 /* It'll most probably be more efficient to generate the base
4398 with more bits set and use a negative index instead. */
4402 base_reg = force_reg (SImode, GEN_INT (base));
4403 x = plus_constant (base_reg, index);
4408 /* We need to find and carefully transform any SYMBOL and LABEL
4409 references; so go back to the original address expression. */
4410 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4412 if (new_x != orig_x)
4420 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4421 to be legitimate. If we find one, return the new, valid address. */
4423 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4425 if (arm_tls_symbol_p (x))
4426 return legitimize_tls_address (x, NULL_RTX);
4428 if (GET_CODE (x) == PLUS
4429 && GET_CODE (XEXP (x, 1)) == CONST_INT
4430 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4431 || INTVAL (XEXP (x, 1)) < 0))
4433 rtx xop0 = XEXP (x, 0);
4434 rtx xop1 = XEXP (x, 1);
4435 HOST_WIDE_INT offset = INTVAL (xop1);
4437 /* Try and fold the offset into a biasing of the base register and
4438 then offsetting that. Don't do this when optimizing for space
4439 since it can cause too many CSEs. */
4440 if (optimize_size && offset >= 0
4441 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4443 HOST_WIDE_INT delta;
4446 delta = offset - (256 - GET_MODE_SIZE (mode));
4447 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4448 delta = 31 * GET_MODE_SIZE (mode);
4450 delta = offset & (~31 * GET_MODE_SIZE (mode));
4452 xop0 = force_operand (plus_constant (xop0, offset - delta),
4454 x = plus_constant (xop0, delta);
4456 else if (offset < 0 && offset > -256)
4457 /* Small negative offsets are best done with a subtract before the
4458 dereference, forcing these into a register normally takes two
4460 x = force_operand (x, NULL_RTX);
4463 /* For the remaining cases, force the constant into a register. */
4464 xop1 = force_reg (SImode, xop1);
4465 x = gen_rtx_PLUS (SImode, xop0, xop1);
4468 else if (GET_CODE (x) == PLUS
4469 && s_register_operand (XEXP (x, 1), SImode)
4470 && !s_register_operand (XEXP (x, 0), SImode))
4472 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4474 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4479 /* We need to find and carefully transform any SYMBOL and LABEL
4480 references; so go back to the original address expression. */
4481 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4483 if (new_x != orig_x)
4491 thumb_legitimize_reload_address (rtx *x_p,
4492 enum machine_mode mode,
4493 int opnum, int type,
4494 int ind_levels ATTRIBUTE_UNUSED)
4498 if (GET_CODE (x) == PLUS
4499 && GET_MODE_SIZE (mode) < 4
4500 && REG_P (XEXP (x, 0))
4501 && XEXP (x, 0) == stack_pointer_rtx
4502 && GET_CODE (XEXP (x, 1)) == CONST_INT
4503 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4508 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4509 Pmode, VOIDmode, 0, 0, opnum, type);
4513 /* If both registers are hi-regs, then it's better to reload the
4514 entire expression rather than each register individually. That
4515 only requires one reload register rather than two. */
4516 if (GET_CODE (x) == PLUS
4517 && REG_P (XEXP (x, 0))
4518 && REG_P (XEXP (x, 1))
4519 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4520 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4525 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4526 Pmode, VOIDmode, 0, 0, opnum, type);
4533 /* Test for various thread-local symbols. */
4535 /* Return TRUE if X is a thread-local symbol. */
4538 arm_tls_symbol_p (rtx x)
4540 if (! TARGET_HAVE_TLS)
4543 if (GET_CODE (x) != SYMBOL_REF)
4546 return SYMBOL_REF_TLS_MODEL (x) != 0;
4549 /* Helper for arm_tls_referenced_p. */
4552 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4554 if (GET_CODE (*x) == SYMBOL_REF)
4555 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4557 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4558 TLS offsets, not real symbol references. */
4559 if (GET_CODE (*x) == UNSPEC
4560 && XINT (*x, 1) == UNSPEC_TLS)
4566 /* Return TRUE if X contains any TLS symbol references. */
4569 arm_tls_referenced_p (rtx x)
4571 if (! TARGET_HAVE_TLS)
4574 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4577 #define REG_OR_SUBREG_REG(X) \
4578 (GET_CODE (X) == REG \
4579 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4581 #define REG_OR_SUBREG_RTX(X) \
4582 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4584 #ifndef COSTS_N_INSNS
4585 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4588 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4590 enum machine_mode mode = GET_MODE (x);
4603 return COSTS_N_INSNS (1);
4606 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4609 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4616 return COSTS_N_INSNS (2) + cycles;
4618 return COSTS_N_INSNS (1) + 16;
4621 return (COSTS_N_INSNS (1)
4622 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4623 + GET_CODE (SET_DEST (x)) == MEM));
4628 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4630 if (thumb_shiftable_const (INTVAL (x)))
4631 return COSTS_N_INSNS (2);
4632 return COSTS_N_INSNS (3);
4634 else if ((outer == PLUS || outer == COMPARE)
4635 && INTVAL (x) < 256 && INTVAL (x) > -256)
4637 else if (outer == AND
4638 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4639 return COSTS_N_INSNS (1);
4640 else if (outer == ASHIFT || outer == ASHIFTRT
4641 || outer == LSHIFTRT)
4643 return COSTS_N_INSNS (2);
4649 return COSTS_N_INSNS (3);
4667 /* XXX another guess. */
4668 /* Memory costs quite a lot for the first word, but subsequent words
4669 load at the equivalent of a single insn each. */
4670 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4671 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4676 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4681 /* XXX still guessing. */
4682 switch (GET_MODE (XEXP (x, 0)))
4685 return (1 + (mode == DImode ? 4 : 0)
4686 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4689 return (4 + (mode == DImode ? 4 : 0)
4690 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4693 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4705 /* Worker routine for arm_rtx_costs. */
4706 /* ??? This needs updating for thumb2. */
4708 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4710 enum machine_mode mode = GET_MODE (x);
4711 enum rtx_code subcode;
4717 /* Memory costs quite a lot for the first word, but subsequent words
4718 load at the equivalent of a single insn each. */
4719 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4720 + (GET_CODE (x) == SYMBOL_REF
4721 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4727 return optimize_size ? COSTS_N_INSNS (2) : 100;
4730 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4737 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4739 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4740 + ((GET_CODE (XEXP (x, 0)) == REG
4741 || (GET_CODE (XEXP (x, 0)) == SUBREG
4742 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4744 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4745 || (GET_CODE (XEXP (x, 0)) == SUBREG
4746 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4748 + ((GET_CODE (XEXP (x, 1)) == REG
4749 || (GET_CODE (XEXP (x, 1)) == SUBREG
4750 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4751 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4755 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4757 extra_cost = rtx_cost (XEXP (x, 1), code);
4758 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4759 extra_cost += 4 * ARM_NUM_REGS (mode);
4764 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4765 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4766 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4767 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4770 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4771 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4772 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4773 && arm_const_double_rtx (XEXP (x, 1))))
4775 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4776 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4777 && arm_const_double_rtx (XEXP (x, 0))))
4780 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4781 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4782 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4783 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4784 || subcode == ASHIFTRT || subcode == LSHIFTRT
4785 || subcode == ROTATE || subcode == ROTATERT
4787 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4788 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4789 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4790 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4791 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4792 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4793 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4798 if (GET_CODE (XEXP (x, 0)) == MULT)
4800 extra_cost = rtx_cost (XEXP (x, 0), code);
4801 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4802 extra_cost += 4 * ARM_NUM_REGS (mode);
4806 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4807 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4808 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4809 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4810 && arm_const_double_rtx (XEXP (x, 1))))
4814 case AND: case XOR: case IOR:
4817 /* Normally the frame registers will be spilt into reg+const during
4818 reload, so it is a bad idea to combine them with other instructions,
4819 since then they might not be moved outside of loops. As a compromise
4820 we allow integration with ops that have a constant as their second
4822 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4823 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4824 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4825 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4826 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4830 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4831 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4832 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4833 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4836 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4837 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4838 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4839 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4840 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4843 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4844 return (1 + extra_cost
4845 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4846 || subcode == LSHIFTRT || subcode == ASHIFTRT
4847 || subcode == ROTATE || subcode == ROTATERT
4849 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4850 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4851 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4852 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4853 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4854 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4860 /* This should have been handled by the CPU specific routines. */
4864 if (arm_arch3m && mode == SImode
4865 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4866 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4867 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4868 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4869 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4870 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4875 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4876 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4880 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4882 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4885 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4893 return 4 + (mode == DImode ? 4 : 0);
4896 /* ??? value extensions are cheaper on armv6. */
4897 if (GET_MODE (XEXP (x, 0)) == QImode)
4898 return (4 + (mode == DImode ? 4 : 0)
4899 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4902 switch (GET_MODE (XEXP (x, 0)))
4905 return (1 + (mode == DImode ? 4 : 0)
4906 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4909 return (4 + (mode == DImode ? 4 : 0)
4910 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4913 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4928 if (const_ok_for_arm (INTVAL (x)))
4929 return outer == SET ? 2 : -1;
4930 else if (outer == AND
4931 && const_ok_for_arm (~INTVAL (x)))
4933 else if ((outer == COMPARE
4934 || outer == PLUS || outer == MINUS)
4935 && const_ok_for_arm (-INTVAL (x)))
4946 if (arm_const_double_rtx (x))
4947 return outer == SET ? 2 : -1;
4948 else if ((outer == COMPARE || outer == PLUS)
4949 && neg_const_double_rtx_ok_for_fpa (x))
4958 /* RTX costs when optimizing for size. */
4960 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4962 enum machine_mode mode = GET_MODE (x);
4966 /* XXX TBD. For now, use the standard costs. */
4967 *total = thumb1_rtx_costs (x, code, outer_code);
4974 /* A memory access costs 1 insn if the mode is small, or the address is
4975 a single register, otherwise it costs one insn per word. */
4976 if (REG_P (XEXP (x, 0)))
4977 *total = COSTS_N_INSNS (1);
4979 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4986 /* Needs a libcall, so it costs about this. */
4987 *total = COSTS_N_INSNS (2);
4991 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4993 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
5001 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
5003 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
5006 else if (mode == SImode)
5008 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5009 /* Slightly disparage register shifts, but not by much. */
5010 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5011 *total += 1 + rtx_cost (XEXP (x, 1), code);
5015 /* Needs a libcall. */
5016 *total = COSTS_N_INSNS (2);
5020 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5022 *total = COSTS_N_INSNS (1);
5028 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5029 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5031 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5032 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5033 || subcode1 == ROTATE || subcode1 == ROTATERT
5034 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5035 || subcode1 == ASHIFTRT)
5037 /* It's just the cost of the two operands. */
5042 *total = COSTS_N_INSNS (1);
5046 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5050 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5052 *total = COSTS_N_INSNS (1);
5057 case AND: case XOR: case IOR:
5060 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5062 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5063 || subcode == LSHIFTRT || subcode == ASHIFTRT
5064 || (code == AND && subcode == NOT))
5066 /* It's just the cost of the two operands. */
5072 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5076 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5080 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5081 *total = COSTS_N_INSNS (1);
5084 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5093 if (cc_register (XEXP (x, 0), VOIDmode))
5096 *total = COSTS_N_INSNS (1);
5100 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5101 *total = COSTS_N_INSNS (1);
5103 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5108 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5110 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5111 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5114 *total += COSTS_N_INSNS (1);
5119 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5121 switch (GET_MODE (XEXP (x, 0)))
5124 *total += COSTS_N_INSNS (1);
5128 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5134 *total += COSTS_N_INSNS (2);
5139 *total += COSTS_N_INSNS (1);
5144 if (const_ok_for_arm (INTVAL (x)))
5145 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5146 else if (const_ok_for_arm (~INTVAL (x)))
5147 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5148 else if (const_ok_for_arm (-INTVAL (x)))
5150 if (outer_code == COMPARE || outer_code == PLUS
5151 || outer_code == MINUS)
5154 *total = COSTS_N_INSNS (1);
5157 *total = COSTS_N_INSNS (2);
5163 *total = COSTS_N_INSNS (2);
5167 *total = COSTS_N_INSNS (4);
5171 if (mode != VOIDmode)
5172 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5174 *total = COSTS_N_INSNS (4); /* How knows? */
5179 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5180 supported on any "slowmul" cores, so it can be ignored. */
5183 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5185 enum machine_mode mode = GET_MODE (x);
5189 *total = thumb1_rtx_costs (x, code, outer_code);
5196 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5203 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5205 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5206 & (unsigned HOST_WIDE_INT) 0xffffffff);
5207 int cost, const_ok = const_ok_for_arm (i);
5208 int j, booth_unit_size;
5210 /* Tune as appropriate. */
5211 cost = const_ok ? 4 : 8;
5212 booth_unit_size = 2;
5213 for (j = 0; i && j < 32; j += booth_unit_size)
5215 i >>= booth_unit_size;
5223 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5224 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5228 *total = arm_rtx_costs_1 (x, code, outer_code);
5234 /* RTX cost for cores with a fast multiply unit (M variants). */
5237 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5239 enum machine_mode mode = GET_MODE (x);
5243 *total = thumb1_rtx_costs (x, code, outer_code);
5247 /* ??? should thumb2 use different costs? */
5251 /* There is no point basing this on the tuning, since it is always the
5252 fast variant if it exists at all. */
5254 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5255 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5256 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5263 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5270 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5272 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5273 & (unsigned HOST_WIDE_INT) 0xffffffff);
5274 int cost, const_ok = const_ok_for_arm (i);
5275 int j, booth_unit_size;
5277 /* Tune as appropriate. */
5278 cost = const_ok ? 4 : 8;
5279 booth_unit_size = 8;
5280 for (j = 0; i && j < 32; j += booth_unit_size)
5282 i >>= booth_unit_size;
5290 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5291 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5295 *total = arm_rtx_costs_1 (x, code, outer_code);
5301 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5302 so it can be ignored. */
5305 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5307 enum machine_mode mode = GET_MODE (x);
5311 *total = thumb1_rtx_costs (x, code, outer_code);
5318 /* There is no point basing this on the tuning, since it is always the
5319 fast variant if it exists at all. */
5321 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5322 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5323 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5330 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5337 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5339 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5340 & (unsigned HOST_WIDE_INT) 0xffffffff);
5341 int cost, const_ok = const_ok_for_arm (i);
5342 unsigned HOST_WIDE_INT masked_const;
5344 /* The cost will be related to two insns.
5345 First a load of the constant (MOV or LDR), then a multiply. */
5348 cost += 1; /* LDR is probably more expensive because
5349 of longer result latency. */
5350 masked_const = i & 0xffff8000;
5351 if (masked_const != 0 && masked_const != 0xffff8000)
5353 masked_const = i & 0xf8000000;
5354 if (masked_const == 0 || masked_const == 0xf8000000)
5363 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5364 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5368 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5369 will stall until the multiplication is complete. */
5370 if (GET_CODE (XEXP (x, 0)) == MULT)
5371 *total = 4 + rtx_cost (XEXP (x, 0), code);
5373 *total = arm_rtx_costs_1 (x, code, outer_code);
5377 *total = arm_rtx_costs_1 (x, code, outer_code);
5383 /* RTX costs for 9e (and later) cores. */
5386 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5388 enum machine_mode mode = GET_MODE (x);
5397 *total = COSTS_N_INSNS (3);
5401 *total = thumb1_rtx_costs (x, code, outer_code);
5409 /* There is no point basing this on the tuning, since it is always the
5410 fast variant if it exists at all. */
5412 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5413 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5414 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5421 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5438 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5439 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5443 *total = arm_rtx_costs_1 (x, code, outer_code);
5447 /* All address computations that can be done are free, but rtx cost returns
5448 the same for practically all of them. So we weight the different types
5449 of address here in the order (most pref first):
5450 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5452 arm_arm_address_cost (rtx x)
5454 enum rtx_code c = GET_CODE (x);
5456 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5458 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5461 if (c == PLUS || c == MINUS)
5463 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5466 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5476 arm_thumb_address_cost (rtx x)
5478 enum rtx_code c = GET_CODE (x);
5483 && GET_CODE (XEXP (x, 0)) == REG
5484 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5491 arm_address_cost (rtx x)
5493 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5497 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5501 /* Some true dependencies can have a higher cost depending
5502 on precisely how certain input operands are used. */
5504 && REG_NOTE_KIND (link) == 0
5505 && recog_memoized (insn) >= 0
5506 && recog_memoized (dep) >= 0)
5508 int shift_opnum = get_attr_shift (insn);
5509 enum attr_type attr_type = get_attr_type (dep);
5511 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5512 operand for INSN. If we have a shifted input operand and the
5513 instruction we depend on is another ALU instruction, then we may
5514 have to account for an additional stall. */
5515 if (shift_opnum != 0
5516 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5518 rtx shifted_operand;
5521 /* Get the shifted operand. */
5522 extract_insn (insn);
5523 shifted_operand = recog_data.operand[shift_opnum];
5525 /* Iterate over all the operands in DEP. If we write an operand
5526 that overlaps with SHIFTED_OPERAND, then we have increase the
5527 cost of this dependency. */
5529 preprocess_constraints ();
5530 for (opno = 0; opno < recog_data.n_operands; opno++)
5532 /* We can ignore strict inputs. */
5533 if (recog_data.operand_type[opno] == OP_IN)
5536 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5543 /* XXX This is not strictly true for the FPA. */
5544 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5545 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5548 /* Call insns don't incur a stall, even if they follow a load. */
5549 if (REG_NOTE_KIND (link) == 0
5550 && GET_CODE (insn) == CALL_INSN)
5553 if ((i_pat = single_set (insn)) != NULL
5554 && GET_CODE (SET_SRC (i_pat)) == MEM
5555 && (d_pat = single_set (dep)) != NULL
5556 && GET_CODE (SET_DEST (d_pat)) == MEM)
5558 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5559 /* This is a load after a store, there is no conflict if the load reads
5560 from a cached area. Assume that loads from the stack, and from the
5561 constant pool are cached, and that others will miss. This is a
5564 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5565 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5566 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5567 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5574 static int fp_consts_inited = 0;
5576 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5577 static const char * const strings_fp[8] =
5580 "4", "5", "0.5", "10"
5583 static REAL_VALUE_TYPE values_fp[8];
5586 init_fp_table (void)
5592 fp_consts_inited = 1;
5594 fp_consts_inited = 8;
5596 for (i = 0; i < fp_consts_inited; i++)
5598 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5603 /* Return TRUE if rtx X is a valid immediate FP constant. */
5605 arm_const_double_rtx (rtx x)
5610 if (!fp_consts_inited)
5613 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5614 if (REAL_VALUE_MINUS_ZERO (r))
5617 for (i = 0; i < fp_consts_inited; i++)
5618 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5624 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5626 neg_const_double_rtx_ok_for_fpa (rtx x)
5631 if (!fp_consts_inited)
5634 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5635 r = REAL_VALUE_NEGATE (r);
5636 if (REAL_VALUE_MINUS_ZERO (r))
5639 for (i = 0; i < 8; i++)
5640 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5646 /* Predicates for `match_operand' and `match_operator'. */
5648 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5650 cirrus_memory_offset (rtx op)
5652 /* Reject eliminable registers. */
5653 if (! (reload_in_progress || reload_completed)
5654 && ( reg_mentioned_p (frame_pointer_rtx, op)
5655 || reg_mentioned_p (arg_pointer_rtx, op)
5656 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5657 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5658 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5659 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5662 if (GET_CODE (op) == MEM)
5668 /* Match: (mem (reg)). */
5669 if (GET_CODE (ind) == REG)
5675 if (GET_CODE (ind) == PLUS
5676 && GET_CODE (XEXP (ind, 0)) == REG
5677 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5678 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5685 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5686 WB is true if full writeback address modes are allowed and is false
5687 if limited writeback address modes (POST_INC and PRE_DEC) are
5691 arm_coproc_mem_operand (rtx op, bool wb)
5695 /* Reject eliminable registers. */
5696 if (! (reload_in_progress || reload_completed)
5697 && ( reg_mentioned_p (frame_pointer_rtx, op)
5698 || reg_mentioned_p (arg_pointer_rtx, op)
5699 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5700 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5701 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5702 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5705 /* Constants are converted into offsets from labels. */
5706 if (GET_CODE (op) != MEM)
5711 if (reload_completed
5712 && (GET_CODE (ind) == LABEL_REF
5713 || (GET_CODE (ind) == CONST
5714 && GET_CODE (XEXP (ind, 0)) == PLUS
5715 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5716 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5719 /* Match: (mem (reg)). */
5720 if (GET_CODE (ind) == REG)
5721 return arm_address_register_rtx_p (ind, 0);
5723 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5724 acceptable in any case (subject to verification by
5725 arm_address_register_rtx_p). We need WB to be true to accept
5726 PRE_INC and POST_DEC. */
5727 if (GET_CODE (ind) == POST_INC
5728 || GET_CODE (ind) == PRE_DEC
5730 && (GET_CODE (ind) == PRE_INC
5731 || GET_CODE (ind) == POST_DEC)))
5732 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5735 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5736 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5737 && GET_CODE (XEXP (ind, 1)) == PLUS
5738 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5739 ind = XEXP (ind, 1);
5744 if (GET_CODE (ind) == PLUS
5745 && GET_CODE (XEXP (ind, 0)) == REG
5746 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5747 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5748 && INTVAL (XEXP (ind, 1)) > -1024
5749 && INTVAL (XEXP (ind, 1)) < 1024
5750 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5756 /* Return true if X is a register that will be eliminated later on. */
5758 arm_eliminable_register (rtx x)
5760 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5761 || REGNO (x) == ARG_POINTER_REGNUM
5762 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5763 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5766 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5767 coprocessor registers. Otherwise return NO_REGS. */
5770 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5772 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5775 return GENERAL_REGS;
5778 /* Values which must be returned in the most-significant end of the return
5782 arm_return_in_msb (tree valtype)
5784 return (TARGET_AAPCS_BASED
5786 && (AGGREGATE_TYPE_P (valtype)
5787 || TREE_CODE (valtype) == COMPLEX_TYPE));
5790 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5791 Use by the Cirrus Maverick code which has to workaround
5792 a hardware bug triggered by such instructions. */
5794 arm_memory_load_p (rtx insn)
5796 rtx body, lhs, rhs;;
5798 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5801 body = PATTERN (insn);
5803 if (GET_CODE (body) != SET)
5806 lhs = XEXP (body, 0);
5807 rhs = XEXP (body, 1);
5809 lhs = REG_OR_SUBREG_RTX (lhs);
5811 /* If the destination is not a general purpose
5812 register we do not have to worry. */
5813 if (GET_CODE (lhs) != REG
5814 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5817 /* As well as loads from memory we also have to react
5818 to loads of invalid constants which will be turned
5819 into loads from the minipool. */
5820 return (GET_CODE (rhs) == MEM
5821 || GET_CODE (rhs) == SYMBOL_REF
5822 || note_invalid_constants (insn, -1, false));
5825 /* Return TRUE if INSN is a Cirrus instruction. */
5827 arm_cirrus_insn_p (rtx insn)
5829 enum attr_cirrus attr;
5831 /* get_attr cannot accept USE or CLOBBER. */
5833 || GET_CODE (insn) != INSN
5834 || GET_CODE (PATTERN (insn)) == USE
5835 || GET_CODE (PATTERN (insn)) == CLOBBER)
5838 attr = get_attr_cirrus (insn);
5840 return attr != CIRRUS_NOT;
5843 /* Cirrus reorg for invalid instruction combinations. */
5845 cirrus_reorg (rtx first)
5847 enum attr_cirrus attr;
5848 rtx body = PATTERN (first);
5852 /* Any branch must be followed by 2 non Cirrus instructions. */
5853 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5856 t = next_nonnote_insn (first);
5858 if (arm_cirrus_insn_p (t))
5861 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5865 emit_insn_after (gen_nop (), first);
5870 /* (float (blah)) is in parallel with a clobber. */
5871 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5872 body = XVECEXP (body, 0, 0);
5874 if (GET_CODE (body) == SET)
5876 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5878 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5879 be followed by a non Cirrus insn. */
5880 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5882 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5883 emit_insn_after (gen_nop (), first);
5887 else if (arm_memory_load_p (first))
5889 unsigned int arm_regno;
5891 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5892 ldr/cfmv64hr combination where the Rd field is the same
5893 in both instructions must be split with a non Cirrus
5900 /* Get Arm register number for ldr insn. */
5901 if (GET_CODE (lhs) == REG)
5902 arm_regno = REGNO (lhs);
5905 gcc_assert (GET_CODE (rhs) == REG);
5906 arm_regno = REGNO (rhs);
5910 first = next_nonnote_insn (first);
5912 if (! arm_cirrus_insn_p (first))
5915 body = PATTERN (first);
5917 /* (float (blah)) is in parallel with a clobber. */
5918 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5919 body = XVECEXP (body, 0, 0);
5921 if (GET_CODE (body) == FLOAT)
5922 body = XEXP (body, 0);
5924 if (get_attr_cirrus (first) == CIRRUS_MOVE
5925 && GET_CODE (XEXP (body, 1)) == REG
5926 && arm_regno == REGNO (XEXP (body, 1)))
5927 emit_insn_after (gen_nop (), first);
5933 /* get_attr cannot accept USE or CLOBBER. */
5935 || GET_CODE (first) != INSN
5936 || GET_CODE (PATTERN (first)) == USE
5937 || GET_CODE (PATTERN (first)) == CLOBBER)
5940 attr = get_attr_cirrus (first);
5942 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5943 must be followed by a non-coprocessor instruction. */
5944 if (attr == CIRRUS_COMPARE)
5948 t = next_nonnote_insn (first);
5950 if (arm_cirrus_insn_p (t))
5953 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5957 emit_insn_after (gen_nop (), first);
5963 /* Return TRUE if X references a SYMBOL_REF. */
5965 symbol_mentioned_p (rtx x)
5970 if (GET_CODE (x) == SYMBOL_REF)
5973 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5974 are constant offsets, not symbols. */
5975 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5978 fmt = GET_RTX_FORMAT (GET_CODE (x));
5980 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5986 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5987 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5990 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5997 /* Return TRUE if X references a LABEL_REF. */
5999 label_mentioned_p (rtx x)
6004 if (GET_CODE (x) == LABEL_REF)
6007 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6008 instruction, but they are constant offsets, not symbols. */
6009 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6012 fmt = GET_RTX_FORMAT (GET_CODE (x));
6013 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6019 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6020 if (label_mentioned_p (XVECEXP (x, i, j)))
6023 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6031 tls_mentioned_p (rtx x)
6033 switch (GET_CODE (x))
6036 return tls_mentioned_p (XEXP (x, 0));
6039 if (XINT (x, 1) == UNSPEC_TLS)
6047 /* Must not copy a SET whose source operand is PC-relative. */
6050 arm_cannot_copy_insn_p (rtx insn)
6052 rtx pat = PATTERN (insn);
6054 if (GET_CODE (pat) == PARALLEL
6055 && GET_CODE (XVECEXP (pat, 0, 0)) == SET)
6057 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0));
6059 if (GET_CODE (rhs) == UNSPEC
6060 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6063 if (GET_CODE (rhs) == MEM
6064 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6065 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6075 enum rtx_code code = GET_CODE (x);
6092 /* Return 1 if memory locations are adjacent. */
6094 adjacent_mem_locations (rtx a, rtx b)
6096 /* We don't guarantee to preserve the order of these memory refs. */
6097 if (volatile_refs_p (a) || volatile_refs_p (b))
6100 if ((GET_CODE (XEXP (a, 0)) == REG
6101 || (GET_CODE (XEXP (a, 0)) == PLUS
6102 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6103 && (GET_CODE (XEXP (b, 0)) == REG
6104 || (GET_CODE (XEXP (b, 0)) == PLUS
6105 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6107 HOST_WIDE_INT val0 = 0, val1 = 0;
6111 if (GET_CODE (XEXP (a, 0)) == PLUS)
6113 reg0 = XEXP (XEXP (a, 0), 0);
6114 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6119 if (GET_CODE (XEXP (b, 0)) == PLUS)
6121 reg1 = XEXP (XEXP (b, 0), 0);
6122 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6127 /* Don't accept any offset that will require multiple
6128 instructions to handle, since this would cause the
6129 arith_adjacentmem pattern to output an overlong sequence. */
6130 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6133 /* Don't allow an eliminable register: register elimination can make
6134 the offset too large. */
6135 if (arm_eliminable_register (reg0))
6138 val_diff = val1 - val0;
6142 /* If the target has load delay slots, then there's no benefit
6143 to using an ldm instruction unless the offset is zero and
6144 we are optimizing for size. */
6145 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6146 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6147 && (val_diff == 4 || val_diff == -4));
6150 return ((REGNO (reg0) == REGNO (reg1))
6151 && (val_diff == 4 || val_diff == -4));
6158 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6159 HOST_WIDE_INT *load_offset)
6161 int unsorted_regs[4];
6162 HOST_WIDE_INT unsorted_offsets[4];
6167 /* Can only handle 2, 3, or 4 insns at present,
6168 though could be easily extended if required. */
6169 gcc_assert (nops >= 2 && nops <= 4);
6171 /* Loop over the operands and check that the memory references are
6172 suitable (i.e. immediate offsets from the same base register). At
6173 the same time, extract the target register, and the memory
6175 for (i = 0; i < nops; i++)
6180 /* Convert a subreg of a mem into the mem itself. */
6181 if (GET_CODE (operands[nops + i]) == SUBREG)
6182 operands[nops + i] = alter_subreg (operands + (nops + i));
6184 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6186 /* Don't reorder volatile memory references; it doesn't seem worth
6187 looking for the case where the order is ok anyway. */
6188 if (MEM_VOLATILE_P (operands[nops + i]))
6191 offset = const0_rtx;
6193 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6194 || (GET_CODE (reg) == SUBREG
6195 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6196 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6197 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6199 || (GET_CODE (reg) == SUBREG
6200 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6201 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6206 base_reg = REGNO (reg);
6207 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6208 ? REGNO (operands[i])
6209 : REGNO (SUBREG_REG (operands[i])));
6214 if (base_reg != (int) REGNO (reg))
6215 /* Not addressed from the same base register. */
6218 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6219 ? REGNO (operands[i])
6220 : REGNO (SUBREG_REG (operands[i])));
6221 if (unsorted_regs[i] < unsorted_regs[order[0]])
6225 /* If it isn't an integer register, or if it overwrites the
6226 base register but isn't the last insn in the list, then
6227 we can't do this. */
6228 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6229 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6232 unsorted_offsets[i] = INTVAL (offset);
6235 /* Not a suitable memory address. */
6239 /* All the useful information has now been extracted from the
6240 operands into unsorted_regs and unsorted_offsets; additionally,
6241 order[0] has been set to the lowest numbered register in the
6242 list. Sort the registers into order, and check that the memory
6243 offsets are ascending and adjacent. */
6245 for (i = 1; i < nops; i++)
6249 order[i] = order[i - 1];
6250 for (j = 0; j < nops; j++)
6251 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6252 && (order[i] == order[i - 1]
6253 || unsorted_regs[j] < unsorted_regs[order[i]]))
6256 /* Have we found a suitable register? if not, one must be used more
6258 if (order[i] == order[i - 1])
6261 /* Is the memory address adjacent and ascending? */
6262 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6270 for (i = 0; i < nops; i++)
6271 regs[i] = unsorted_regs[order[i]];
6273 *load_offset = unsorted_offsets[order[0]];
6276 if (unsorted_offsets[order[0]] == 0)
6277 return 1; /* ldmia */
6279 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
6280 return 2; /* ldmib */
6282 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
6283 return 3; /* ldmda */
6285 if (unsorted_offsets[order[nops - 1]] == -4)
6286 return 4; /* ldmdb */
6288 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6289 if the offset isn't small enough. The reason 2 ldrs are faster
6290 is because these ARMs are able to do more than one cache access
6291 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6292 whilst the ARM8 has a double bandwidth cache. This means that
6293 these cores can do both an instruction fetch and a data fetch in
6294 a single cycle, so the trick of calculating the address into a
6295 scratch register (one of the result regs) and then doing a load
6296 multiple actually becomes slower (and no smaller in code size).
6297 That is the transformation
6299 ldr rd1, [rbase + offset]
6300 ldr rd2, [rbase + offset + 4]
6304 add rd1, rbase, offset
6305 ldmia rd1, {rd1, rd2}
6307 produces worse code -- '3 cycles + any stalls on rd2' instead of
6308 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6309 access per cycle, the first sequence could never complete in less
6310 than 6 cycles, whereas the ldm sequence would only take 5 and
6311 would make better use of sequential accesses if not hitting the
6314 We cheat here and test 'arm_ld_sched' which we currently know to
6315 only be true for the ARM8, ARM9 and StrongARM. If this ever
6316 changes, then the test below needs to be reworked. */
6317 if (nops == 2 && arm_ld_sched)
6320 /* Can't do it without setting up the offset, only do this if it takes
6321 no more than one insn. */
6322 return (const_ok_for_arm (unsorted_offsets[order[0]])
6323 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
6327 emit_ldm_seq (rtx *operands, int nops)
6331 HOST_WIDE_INT offset;
6335 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6338 strcpy (buf, "ldm%(ia%)\t");
6342 strcpy (buf, "ldm%(ib%)\t");
6346 strcpy (buf, "ldm%(da%)\t");
6350 strcpy (buf, "ldm%(db%)\t");
6355 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6356 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6359 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6360 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6362 output_asm_insn (buf, operands);
6364 strcpy (buf, "ldm%(ia%)\t");
6371 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6372 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6374 for (i = 1; i < nops; i++)
6375 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6376 reg_names[regs[i]]);
6378 strcat (buf, "}\t%@ phole ldm");
6380 output_asm_insn (buf, operands);
6385 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6386 HOST_WIDE_INT * load_offset)
6388 int unsorted_regs[4];
6389 HOST_WIDE_INT unsorted_offsets[4];
6394 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6395 extended if required. */
6396 gcc_assert (nops >= 2 && nops <= 4);
6398 /* Loop over the operands and check that the memory references are
6399 suitable (i.e. immediate offsets from the same base register). At
6400 the same time, extract the target register, and the memory
6402 for (i = 0; i < nops; i++)
6407 /* Convert a subreg of a mem into the mem itself. */
6408 if (GET_CODE (operands[nops + i]) == SUBREG)
6409 operands[nops + i] = alter_subreg (operands + (nops + i));
6411 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6413 /* Don't reorder volatile memory references; it doesn't seem worth
6414 looking for the case where the order is ok anyway. */
6415 if (MEM_VOLATILE_P (operands[nops + i]))
6418 offset = const0_rtx;
6420 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6421 || (GET_CODE (reg) == SUBREG
6422 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6423 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6424 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6426 || (GET_CODE (reg) == SUBREG
6427 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6428 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6433 base_reg = REGNO (reg);
6434 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6435 ? REGNO (operands[i])
6436 : REGNO (SUBREG_REG (operands[i])));
6441 if (base_reg != (int) REGNO (reg))
6442 /* Not addressed from the same base register. */
6445 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6446 ? REGNO (operands[i])
6447 : REGNO (SUBREG_REG (operands[i])));
6448 if (unsorted_regs[i] < unsorted_regs[order[0]])
6452 /* If it isn't an integer register, then we can't do this. */
6453 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6456 unsorted_offsets[i] = INTVAL (offset);
6459 /* Not a suitable memory address. */
6463 /* All the useful information has now been extracted from the
6464 operands into unsorted_regs and unsorted_offsets; additionally,
6465 order[0] has been set to the lowest numbered register in the
6466 list. Sort the registers into order, and check that the memory
6467 offsets are ascending and adjacent. */
6469 for (i = 1; i < nops; i++)
6473 order[i] = order[i - 1];
6474 for (j = 0; j < nops; j++)
6475 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6476 && (order[i] == order[i - 1]
6477 || unsorted_regs[j] < unsorted_regs[order[i]]))
6480 /* Have we found a suitable register? if not, one must be used more
6482 if (order[i] == order[i - 1])
6485 /* Is the memory address adjacent and ascending? */
6486 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6494 for (i = 0; i < nops; i++)
6495 regs[i] = unsorted_regs[order[i]];
6497 *load_offset = unsorted_offsets[order[0]];
6500 if (unsorted_offsets[order[0]] == 0)
6501 return 1; /* stmia */
6503 if (unsorted_offsets[order[0]] == 4)
6504 return 2; /* stmib */
6506 if (unsorted_offsets[order[nops - 1]] == 0)
6507 return 3; /* stmda */
6509 if (unsorted_offsets[order[nops - 1]] == -4)
6510 return 4; /* stmdb */
6516 emit_stm_seq (rtx *operands, int nops)
6520 HOST_WIDE_INT offset;
6524 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6527 strcpy (buf, "stm%(ia%)\t");
6531 strcpy (buf, "stm%(ib%)\t");
6535 strcpy (buf, "stm%(da%)\t");
6539 strcpy (buf, "stm%(db%)\t");
6546 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6547 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6549 for (i = 1; i < nops; i++)
6550 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6551 reg_names[regs[i]]);
6553 strcat (buf, "}\t%@ phole stm");
6555 output_asm_insn (buf, operands);
6559 /* Routines for use in generating RTL. */
6562 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6563 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6565 HOST_WIDE_INT offset = *offsetp;
6568 int sign = up ? 1 : -1;
6571 /* XScale has load-store double instructions, but they have stricter
6572 alignment requirements than load-store multiple, so we cannot
6575 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6576 the pipeline until completion.
6584 An ldr instruction takes 1-3 cycles, but does not block the
6593 Best case ldr will always win. However, the more ldr instructions
6594 we issue, the less likely we are to be able to schedule them well.
6595 Using ldr instructions also increases code size.
6597 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6598 for counts of 3 or 4 regs. */
6599 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6605 for (i = 0; i < count; i++)
6607 addr = plus_constant (from, i * 4 * sign);
6608 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6609 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6615 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6625 result = gen_rtx_PARALLEL (VOIDmode,
6626 rtvec_alloc (count + (write_back ? 1 : 0)));
6629 XVECEXP (result, 0, 0)
6630 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6635 for (j = 0; i < count; i++, j++)
6637 addr = plus_constant (from, j * 4 * sign);
6638 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6639 XVECEXP (result, 0, i)
6640 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6651 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6652 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6654 HOST_WIDE_INT offset = *offsetp;
6657 int sign = up ? 1 : -1;
6660 /* See arm_gen_load_multiple for discussion of
6661 the pros/cons of ldm/stm usage for XScale. */
6662 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6668 for (i = 0; i < count; i++)
6670 addr = plus_constant (to, i * 4 * sign);
6671 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6672 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6678 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6688 result = gen_rtx_PARALLEL (VOIDmode,
6689 rtvec_alloc (count + (write_back ? 1 : 0)));
6692 XVECEXP (result, 0, 0)
6693 = gen_rtx_SET (VOIDmode, to,
6694 plus_constant (to, count * 4 * sign));
6699 for (j = 0; i < count; i++, j++)
6701 addr = plus_constant (to, j * 4 * sign);
6702 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6703 XVECEXP (result, 0, i)
6704 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6715 arm_gen_movmemqi (rtx *operands)
6717 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6718 HOST_WIDE_INT srcoffset, dstoffset;
6720 rtx src, dst, srcbase, dstbase;
6721 rtx part_bytes_reg = NULL;
6724 if (GET_CODE (operands[2]) != CONST_INT
6725 || GET_CODE (operands[3]) != CONST_INT
6726 || INTVAL (operands[2]) > 64
6727 || INTVAL (operands[3]) & 3)
6730 dstbase = operands[0];
6731 srcbase = operands[1];
6733 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6734 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6736 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6737 out_words_to_go = INTVAL (operands[2]) / 4;
6738 last_bytes = INTVAL (operands[2]) & 3;
6739 dstoffset = srcoffset = 0;
6741 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6742 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6744 for (i = 0; in_words_to_go >= 2; i+=4)
6746 if (in_words_to_go > 4)
6747 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6748 srcbase, &srcoffset));
6750 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6751 FALSE, srcbase, &srcoffset));
6753 if (out_words_to_go)
6755 if (out_words_to_go > 4)
6756 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6757 dstbase, &dstoffset));
6758 else if (out_words_to_go != 1)
6759 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6763 dstbase, &dstoffset));
6766 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6767 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6768 if (last_bytes != 0)
6770 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6776 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6777 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6780 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6781 if (out_words_to_go)
6785 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6786 sreg = copy_to_reg (mem);
6788 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6789 emit_move_insn (mem, sreg);
6792 gcc_assert (!in_words_to_go); /* Sanity check */
6797 gcc_assert (in_words_to_go > 0);
6799 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6800 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6803 gcc_assert (!last_bytes || part_bytes_reg);
6805 if (BYTES_BIG_ENDIAN && last_bytes)
6807 rtx tmp = gen_reg_rtx (SImode);
6809 /* The bytes we want are in the top end of the word. */
6810 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6811 GEN_INT (8 * (4 - last_bytes))));
6812 part_bytes_reg = tmp;
6816 mem = adjust_automodify_address (dstbase, QImode,
6817 plus_constant (dst, last_bytes - 1),
6818 dstoffset + last_bytes - 1);
6819 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6823 tmp = gen_reg_rtx (SImode);
6824 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6825 part_bytes_reg = tmp;
6834 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6835 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6839 rtx tmp = gen_reg_rtx (SImode);
6840 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6841 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6842 part_bytes_reg = tmp;
6849 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6850 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6857 /* Select a dominance comparison mode if possible for a test of the general
6858 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6859 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6860 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6861 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6862 In all cases OP will be either EQ or NE, but we don't need to know which
6863 here. If we are unable to support a dominance comparison we return
6864 CC mode. This will then fail to match for the RTL expressions that
6865 generate this call. */
6867 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6869 enum rtx_code cond1, cond2;
6872 /* Currently we will probably get the wrong result if the individual
6873 comparisons are not simple. This also ensures that it is safe to
6874 reverse a comparison if necessary. */
6875 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6877 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6881 /* The if_then_else variant of this tests the second condition if the
6882 first passes, but is true if the first fails. Reverse the first
6883 condition to get a true "inclusive-or" expression. */
6884 if (cond_or == DOM_CC_NX_OR_Y)
6885 cond1 = reverse_condition (cond1);
6887 /* If the comparisons are not equal, and one doesn't dominate the other,
6888 then we can't do this. */
6890 && !comparison_dominates_p (cond1, cond2)
6891 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6896 enum rtx_code temp = cond1;
6904 if (cond_or == DOM_CC_X_AND_Y)
6909 case EQ: return CC_DEQmode;
6910 case LE: return CC_DLEmode;
6911 case LEU: return CC_DLEUmode;
6912 case GE: return CC_DGEmode;
6913 case GEU: return CC_DGEUmode;
6914 default: gcc_unreachable ();
6918 if (cond_or == DOM_CC_X_AND_Y)
6934 if (cond_or == DOM_CC_X_AND_Y)
6950 if (cond_or == DOM_CC_X_AND_Y)
6966 if (cond_or == DOM_CC_X_AND_Y)
6981 /* The remaining cases only occur when both comparisons are the
6984 gcc_assert (cond1 == cond2);
6988 gcc_assert (cond1 == cond2);
6992 gcc_assert (cond1 == cond2);
6996 gcc_assert (cond1 == cond2);
7000 gcc_assert (cond1 == cond2);
7009 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
7011 /* All floating point compares return CCFP if it is an equality
7012 comparison, and CCFPE otherwise. */
7013 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
7033 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
7042 /* A compare with a shifted operand. Because of canonicalization, the
7043 comparison will have to be swapped when we emit the assembler. */
7044 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7045 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7046 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7047 || GET_CODE (x) == ROTATERT))
7050 /* This operation is performed swapped, but since we only rely on the Z
7051 flag we don't need an additional mode. */
7052 if (GET_MODE (y) == SImode && REG_P (y)
7053 && GET_CODE (x) == NEG
7054 && (op == EQ || op == NE))
7057 /* This is a special case that is used by combine to allow a
7058 comparison of a shifted byte load to be split into a zero-extend
7059 followed by a comparison of the shifted integer (only valid for
7060 equalities and unsigned inequalities). */
7061 if (GET_MODE (x) == SImode
7062 && GET_CODE (x) == ASHIFT
7063 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7064 && GET_CODE (XEXP (x, 0)) == SUBREG
7065 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7066 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7067 && (op == EQ || op == NE
7068 || op == GEU || op == GTU || op == LTU || op == LEU)
7069 && GET_CODE (y) == CONST_INT)
7072 /* A construct for a conditional compare, if the false arm contains
7073 0, then both conditions must be true, otherwise either condition
7074 must be true. Not all conditions are possible, so CCmode is
7075 returned if it can't be done. */
7076 if (GET_CODE (x) == IF_THEN_ELSE
7077 && (XEXP (x, 2) == const0_rtx
7078 || XEXP (x, 2) == const1_rtx)
7079 && COMPARISON_P (XEXP (x, 0))
7080 && COMPARISON_P (XEXP (x, 1)))
7081 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7082 INTVAL (XEXP (x, 2)));
7084 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7085 if (GET_CODE (x) == AND
7086 && COMPARISON_P (XEXP (x, 0))
7087 && COMPARISON_P (XEXP (x, 1)))
7088 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7091 if (GET_CODE (x) == IOR
7092 && COMPARISON_P (XEXP (x, 0))
7093 && COMPARISON_P (XEXP (x, 1)))
7094 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7097 /* An operation (on Thumb) where we want to test for a single bit.
7098 This is done by shifting that bit up into the top bit of a
7099 scratch register; we can then branch on the sign bit. */
7101 && GET_MODE (x) == SImode
7102 && (op == EQ || op == NE)
7103 && GET_CODE (x) == ZERO_EXTRACT
7104 && XEXP (x, 1) == const1_rtx)
7107 /* An operation that sets the condition codes as a side-effect, the
7108 V flag is not set correctly, so we can only use comparisons where
7109 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7111 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7112 if (GET_MODE (x) == SImode
7114 && (op == EQ || op == NE || op == LT || op == GE)
7115 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7116 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7117 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7118 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7119 || GET_CODE (x) == LSHIFTRT
7120 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7121 || GET_CODE (x) == ROTATERT
7122 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
7125 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7128 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7129 && GET_CODE (x) == PLUS
7130 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7136 /* X and Y are two things to compare using CODE. Emit the compare insn and
7137 return the rtx for register 0 in the proper mode. FP means this is a
7138 floating point compare: I don't think that it is needed on the arm. */
7140 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
7142 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
7143 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
7145 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
7150 /* Generate a sequence of insns that will generate the correct return
7151 address mask depending on the physical architecture that the program
7154 arm_gen_return_addr_mask (void)
7156 rtx reg = gen_reg_rtx (Pmode);
7158 emit_insn (gen_return_addr_mask (reg));
7163 arm_reload_in_hi (rtx *operands)
7165 rtx ref = operands[1];
7167 HOST_WIDE_INT offset = 0;
7169 if (GET_CODE (ref) == SUBREG)
7171 offset = SUBREG_BYTE (ref);
7172 ref = SUBREG_REG (ref);
7175 if (GET_CODE (ref) == REG)
7177 /* We have a pseudo which has been spilt onto the stack; there
7178 are two cases here: the first where there is a simple
7179 stack-slot replacement and a second where the stack-slot is
7180 out of range, or is used as a subreg. */
7181 if (reg_equiv_mem[REGNO (ref)])
7183 ref = reg_equiv_mem[REGNO (ref)];
7184 base = find_replacement (&XEXP (ref, 0));
7187 /* The slot is out of range, or was dressed up in a SUBREG. */
7188 base = reg_equiv_address[REGNO (ref)];
7191 base = find_replacement (&XEXP (ref, 0));
7193 /* Handle the case where the address is too complex to be offset by 1. */
7194 if (GET_CODE (base) == MINUS
7195 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7197 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7199 emit_set_insn (base_plus, base);
7202 else if (GET_CODE (base) == PLUS)
7204 /* The addend must be CONST_INT, or we would have dealt with it above. */
7205 HOST_WIDE_INT hi, lo;
7207 offset += INTVAL (XEXP (base, 1));
7208 base = XEXP (base, 0);
7210 /* Rework the address into a legal sequence of insns. */
7211 /* Valid range for lo is -4095 -> 4095 */
7214 : -((-offset) & 0xfff));
7216 /* Corner case, if lo is the max offset then we would be out of range
7217 once we have added the additional 1 below, so bump the msb into the
7218 pre-loading insn(s). */
7222 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7223 ^ (HOST_WIDE_INT) 0x80000000)
7224 - (HOST_WIDE_INT) 0x80000000);
7226 gcc_assert (hi + lo == offset);
7230 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7232 /* Get the base address; addsi3 knows how to handle constants
7233 that require more than one insn. */
7234 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7240 /* Operands[2] may overlap operands[0] (though it won't overlap
7241 operands[1]), that's why we asked for a DImode reg -- so we can
7242 use the bit that does not overlap. */
7243 if (REGNO (operands[2]) == REGNO (operands[0]))
7244 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7246 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7248 emit_insn (gen_zero_extendqisi2 (scratch,
7249 gen_rtx_MEM (QImode,
7250 plus_constant (base,
7252 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
7253 gen_rtx_MEM (QImode,
7254 plus_constant (base,
7256 if (!BYTES_BIG_ENDIAN)
7257 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7258 gen_rtx_IOR (SImode,
7261 gen_rtx_SUBREG (SImode, operands[0], 0),
7265 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7266 gen_rtx_IOR (SImode,
7267 gen_rtx_ASHIFT (SImode, scratch,
7269 gen_rtx_SUBREG (SImode, operands[0], 0)));
7272 /* Handle storing a half-word to memory during reload by synthesizing as two
7273 byte stores. Take care not to clobber the input values until after we
7274 have moved them somewhere safe. This code assumes that if the DImode
7275 scratch in operands[2] overlaps either the input value or output address
7276 in some way, then that value must die in this insn (we absolutely need
7277 two scratch registers for some corner cases). */
7279 arm_reload_out_hi (rtx *operands)
7281 rtx ref = operands[0];
7282 rtx outval = operands[1];
7284 HOST_WIDE_INT offset = 0;
7286 if (GET_CODE (ref) == SUBREG)
7288 offset = SUBREG_BYTE (ref);
7289 ref = SUBREG_REG (ref);
7292 if (GET_CODE (ref) == REG)
7294 /* We have a pseudo which has been spilt onto the stack; there
7295 are two cases here: the first where there is a simple
7296 stack-slot replacement and a second where the stack-slot is
7297 out of range, or is used as a subreg. */
7298 if (reg_equiv_mem[REGNO (ref)])
7300 ref = reg_equiv_mem[REGNO (ref)];
7301 base = find_replacement (&XEXP (ref, 0));
7304 /* The slot is out of range, or was dressed up in a SUBREG. */
7305 base = reg_equiv_address[REGNO (ref)];
7308 base = find_replacement (&XEXP (ref, 0));
7310 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7312 /* Handle the case where the address is too complex to be offset by 1. */
7313 if (GET_CODE (base) == MINUS
7314 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7316 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7318 /* Be careful not to destroy OUTVAL. */
7319 if (reg_overlap_mentioned_p (base_plus, outval))
7321 /* Updating base_plus might destroy outval, see if we can
7322 swap the scratch and base_plus. */
7323 if (!reg_overlap_mentioned_p (scratch, outval))
7326 scratch = base_plus;
7331 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7333 /* Be conservative and copy OUTVAL into the scratch now,
7334 this should only be necessary if outval is a subreg
7335 of something larger than a word. */
7336 /* XXX Might this clobber base? I can't see how it can,
7337 since scratch is known to overlap with OUTVAL, and
7338 must be wider than a word. */
7339 emit_insn (gen_movhi (scratch_hi, outval));
7340 outval = scratch_hi;
7344 emit_set_insn (base_plus, base);
7347 else if (GET_CODE (base) == PLUS)
7349 /* The addend must be CONST_INT, or we would have dealt with it above. */
7350 HOST_WIDE_INT hi, lo;
7352 offset += INTVAL (XEXP (base, 1));
7353 base = XEXP (base, 0);
7355 /* Rework the address into a legal sequence of insns. */
7356 /* Valid range for lo is -4095 -> 4095 */
7359 : -((-offset) & 0xfff));
7361 /* Corner case, if lo is the max offset then we would be out of range
7362 once we have added the additional 1 below, so bump the msb into the
7363 pre-loading insn(s). */
7367 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7368 ^ (HOST_WIDE_INT) 0x80000000)
7369 - (HOST_WIDE_INT) 0x80000000);
7371 gcc_assert (hi + lo == offset);
7375 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7377 /* Be careful not to destroy OUTVAL. */
7378 if (reg_overlap_mentioned_p (base_plus, outval))
7380 /* Updating base_plus might destroy outval, see if we
7381 can swap the scratch and base_plus. */
7382 if (!reg_overlap_mentioned_p (scratch, outval))
7385 scratch = base_plus;
7390 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7392 /* Be conservative and copy outval into scratch now,
7393 this should only be necessary if outval is a
7394 subreg of something larger than a word. */
7395 /* XXX Might this clobber base? I can't see how it
7396 can, since scratch is known to overlap with
7398 emit_insn (gen_movhi (scratch_hi, outval));
7399 outval = scratch_hi;
7403 /* Get the base address; addsi3 knows how to handle constants
7404 that require more than one insn. */
7405 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7411 if (BYTES_BIG_ENDIAN)
7413 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7414 plus_constant (base, offset + 1)),
7415 gen_lowpart (QImode, outval)));
7416 emit_insn (gen_lshrsi3 (scratch,
7417 gen_rtx_SUBREG (SImode, outval, 0),
7419 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7420 gen_lowpart (QImode, scratch)));
7424 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7425 gen_lowpart (QImode, outval)));
7426 emit_insn (gen_lshrsi3 (scratch,
7427 gen_rtx_SUBREG (SImode, outval, 0),
7429 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7430 plus_constant (base, offset + 1)),
7431 gen_lowpart (QImode, scratch)));
7435 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7436 (padded to the size of a word) should be passed in a register. */
7439 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7441 if (TARGET_AAPCS_BASED)
7442 return must_pass_in_stack_var_size (mode, type);
7444 return must_pass_in_stack_var_size_or_pad (mode, type);
7448 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7449 Return true if an argument passed on the stack should be padded upwards,
7450 i.e. if the least-significant byte has useful data.
7451 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7452 aggregate types are placed in the lowest memory address. */
7455 arm_pad_arg_upward (enum machine_mode mode, tree type)
7457 if (!TARGET_AAPCS_BASED)
7458 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7460 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7467 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7468 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7469 byte of the register has useful data, and return the opposite if the
7470 most significant byte does.
7471 For AAPCS, small aggregates and small complex types are always padded
7475 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7476 tree type, int first ATTRIBUTE_UNUSED)
7478 if (TARGET_AAPCS_BASED
7480 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7481 && int_size_in_bytes (type) <= 4)
7484 /* Otherwise, use default padding. */
7485 return !BYTES_BIG_ENDIAN;
7489 /* Print a symbolic form of X to the debug file, F. */
7491 arm_print_value (FILE *f, rtx x)
7493 switch (GET_CODE (x))
7496 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7500 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7508 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7510 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7511 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7519 fprintf (f, "\"%s\"", XSTR (x, 0));
7523 fprintf (f, "`%s'", XSTR (x, 0));
7527 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7531 arm_print_value (f, XEXP (x, 0));
7535 arm_print_value (f, XEXP (x, 0));
7537 arm_print_value (f, XEXP (x, 1));
7545 fprintf (f, "????");
7550 /* Routines for manipulation of the constant pool. */
7552 /* Arm instructions cannot load a large constant directly into a
7553 register; they have to come from a pc relative load. The constant
7554 must therefore be placed in the addressable range of the pc
7555 relative load. Depending on the precise pc relative load
7556 instruction the range is somewhere between 256 bytes and 4k. This
7557 means that we often have to dump a constant inside a function, and
7558 generate code to branch around it.
7560 It is important to minimize this, since the branches will slow
7561 things down and make the code larger.
7563 Normally we can hide the table after an existing unconditional
7564 branch so that there is no interruption of the flow, but in the
7565 worst case the code looks like this:
7583 We fix this by performing a scan after scheduling, which notices
7584 which instructions need to have their operands fetched from the
7585 constant table and builds the table.
7587 The algorithm starts by building a table of all the constants that
7588 need fixing up and all the natural barriers in the function (places
7589 where a constant table can be dropped without breaking the flow).
7590 For each fixup we note how far the pc-relative replacement will be
7591 able to reach and the offset of the instruction into the function.
7593 Having built the table we then group the fixes together to form
7594 tables that are as large as possible (subject to addressing
7595 constraints) and emit each table of constants after the last
7596 barrier that is within range of all the instructions in the group.
7597 If a group does not contain a barrier, then we forcibly create one
7598 by inserting a jump instruction into the flow. Once the table has
7599 been inserted, the insns are then modified to reference the
7600 relevant entry in the pool.
7602 Possible enhancements to the algorithm (not implemented) are:
7604 1) For some processors and object formats, there may be benefit in
7605 aligning the pools to the start of cache lines; this alignment
7606 would need to be taken into account when calculating addressability
7609 /* These typedefs are located at the start of this file, so that
7610 they can be used in the prototypes there. This comment is to
7611 remind readers of that fact so that the following structures
7612 can be understood more easily.
7614 typedef struct minipool_node Mnode;
7615 typedef struct minipool_fixup Mfix; */
7617 struct minipool_node
7619 /* Doubly linked chain of entries. */
7622 /* The maximum offset into the code that this entry can be placed. While
7623 pushing fixes for forward references, all entries are sorted in order
7624 of increasing max_address. */
7625 HOST_WIDE_INT max_address;
7626 /* Similarly for an entry inserted for a backwards ref. */
7627 HOST_WIDE_INT min_address;
7628 /* The number of fixes referencing this entry. This can become zero
7629 if we "unpush" an entry. In this case we ignore the entry when we
7630 come to emit the code. */
7632 /* The offset from the start of the minipool. */
7633 HOST_WIDE_INT offset;
7634 /* The value in table. */
7636 /* The mode of value. */
7637 enum machine_mode mode;
7638 /* The size of the value. With iWMMXt enabled
7639 sizes > 4 also imply an alignment of 8-bytes. */
7643 struct minipool_fixup
7647 HOST_WIDE_INT address;
7649 enum machine_mode mode;
7653 HOST_WIDE_INT forwards;
7654 HOST_WIDE_INT backwards;
7657 /* Fixes less than a word need padding out to a word boundary. */
7658 #define MINIPOOL_FIX_SIZE(mode) \
7659 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7661 static Mnode * minipool_vector_head;
7662 static Mnode * minipool_vector_tail;
7663 static rtx minipool_vector_label;
7664 static int minipool_pad;
7666 /* The linked list of all minipool fixes required for this function. */
7667 Mfix * minipool_fix_head;
7668 Mfix * minipool_fix_tail;
7669 /* The fix entry for the current minipool, once it has been placed. */
7670 Mfix * minipool_barrier;
7672 /* Determines if INSN is the start of a jump table. Returns the end
7673 of the TABLE or NULL_RTX. */
7675 is_jump_table (rtx insn)
7679 if (GET_CODE (insn) == JUMP_INSN
7680 && JUMP_LABEL (insn) != NULL
7681 && ((table = next_real_insn (JUMP_LABEL (insn)))
7682 == next_real_insn (insn))
7684 && GET_CODE (table) == JUMP_INSN
7685 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7686 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7692 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7693 #define JUMP_TABLES_IN_TEXT_SECTION 0
7696 static HOST_WIDE_INT
7697 get_jump_table_size (rtx insn)
7699 /* ADDR_VECs only take room if read-only data does into the text
7701 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7703 rtx body = PATTERN (insn);
7704 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7706 HOST_WIDE_INT modesize;
7708 modesize = GET_MODE_SIZE (GET_MODE (body));
7709 size = modesize * XVECLEN (body, elt);
7713 /* Round up size of TBB table to a halfword boundary. */
7714 size = (size + 1) & ~(HOST_WIDE_INT)1;
7717 /* No padding necessary for TBH. */
7720 /* Add two bytes for alignment on Thumb. */
7733 /* Move a minipool fix MP from its current location to before MAX_MP.
7734 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7735 constraints may need updating. */
7737 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7738 HOST_WIDE_INT max_address)
7740 /* The code below assumes these are different. */
7741 gcc_assert (mp != max_mp);
7745 if (max_address < mp->max_address)
7746 mp->max_address = max_address;
7750 if (max_address > max_mp->max_address - mp->fix_size)
7751 mp->max_address = max_mp->max_address - mp->fix_size;
7753 mp->max_address = max_address;
7755 /* Unlink MP from its current position. Since max_mp is non-null,
7756 mp->prev must be non-null. */
7757 mp->prev->next = mp->next;
7758 if (mp->next != NULL)
7759 mp->next->prev = mp->prev;
7761 minipool_vector_tail = mp->prev;
7763 /* Re-insert it before MAX_MP. */
7765 mp->prev = max_mp->prev;
7768 if (mp->prev != NULL)
7769 mp->prev->next = mp;
7771 minipool_vector_head = mp;
7774 /* Save the new entry. */
7777 /* Scan over the preceding entries and adjust their addresses as
7779 while (mp->prev != NULL
7780 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7782 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7789 /* Add a constant to the minipool for a forward reference. Returns the
7790 node added or NULL if the constant will not fit in this pool. */
7792 add_minipool_forward_ref (Mfix *fix)
7794 /* If set, max_mp is the first pool_entry that has a lower
7795 constraint than the one we are trying to add. */
7796 Mnode * max_mp = NULL;
7797 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
7800 /* If the minipool starts before the end of FIX->INSN then this FIX
7801 can not be placed into the current pool. Furthermore, adding the
7802 new constant pool entry may cause the pool to start FIX_SIZE bytes
7804 if (minipool_vector_head &&
7805 (fix->address + get_attr_length (fix->insn)
7806 >= minipool_vector_head->max_address - fix->fix_size))
7809 /* Scan the pool to see if a constant with the same value has
7810 already been added. While we are doing this, also note the
7811 location where we must insert the constant if it doesn't already
7813 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7815 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7816 && fix->mode == mp->mode
7817 && (GET_CODE (fix->value) != CODE_LABEL
7818 || (CODE_LABEL_NUMBER (fix->value)
7819 == CODE_LABEL_NUMBER (mp->value)))
7820 && rtx_equal_p (fix->value, mp->value))
7822 /* More than one fix references this entry. */
7824 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7827 /* Note the insertion point if necessary. */
7829 && mp->max_address > max_address)
7832 /* If we are inserting an 8-bytes aligned quantity and
7833 we have not already found an insertion point, then
7834 make sure that all such 8-byte aligned quantities are
7835 placed at the start of the pool. */
7836 if (ARM_DOUBLEWORD_ALIGN
7838 && fix->fix_size == 8
7839 && mp->fix_size != 8)
7842 max_address = mp->max_address;
7846 /* The value is not currently in the minipool, so we need to create
7847 a new entry for it. If MAX_MP is NULL, the entry will be put on
7848 the end of the list since the placement is less constrained than
7849 any existing entry. Otherwise, we insert the new fix before
7850 MAX_MP and, if necessary, adjust the constraints on the other
7853 mp->fix_size = fix->fix_size;
7854 mp->mode = fix->mode;
7855 mp->value = fix->value;
7857 /* Not yet required for a backwards ref. */
7858 mp->min_address = -65536;
7862 mp->max_address = max_address;
7864 mp->prev = minipool_vector_tail;
7866 if (mp->prev == NULL)
7868 minipool_vector_head = mp;
7869 minipool_vector_label = gen_label_rtx ();
7872 mp->prev->next = mp;
7874 minipool_vector_tail = mp;
7878 if (max_address > max_mp->max_address - mp->fix_size)
7879 mp->max_address = max_mp->max_address - mp->fix_size;
7881 mp->max_address = max_address;
7884 mp->prev = max_mp->prev;
7886 if (mp->prev != NULL)
7887 mp->prev->next = mp;
7889 minipool_vector_head = mp;
7892 /* Save the new entry. */
7895 /* Scan over the preceding entries and adjust their addresses as
7897 while (mp->prev != NULL
7898 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7900 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7908 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7909 HOST_WIDE_INT min_address)
7911 HOST_WIDE_INT offset;
7913 /* The code below assumes these are different. */
7914 gcc_assert (mp != min_mp);
7918 if (min_address > mp->min_address)
7919 mp->min_address = min_address;
7923 /* We will adjust this below if it is too loose. */
7924 mp->min_address = min_address;
7926 /* Unlink MP from its current position. Since min_mp is non-null,
7927 mp->next must be non-null. */
7928 mp->next->prev = mp->prev;
7929 if (mp->prev != NULL)
7930 mp->prev->next = mp->next;
7932 minipool_vector_head = mp->next;
7934 /* Reinsert it after MIN_MP. */
7936 mp->next = min_mp->next;
7938 if (mp->next != NULL)
7939 mp->next->prev = mp;
7941 minipool_vector_tail = mp;
7947 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7949 mp->offset = offset;
7950 if (mp->refcount > 0)
7951 offset += mp->fix_size;
7953 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7954 mp->next->min_address = mp->min_address + mp->fix_size;
7960 /* Add a constant to the minipool for a backward reference. Returns the
7961 node added or NULL if the constant will not fit in this pool.
7963 Note that the code for insertion for a backwards reference can be
7964 somewhat confusing because the calculated offsets for each fix do
7965 not take into account the size of the pool (which is still under
7968 add_minipool_backward_ref (Mfix *fix)
7970 /* If set, min_mp is the last pool_entry that has a lower constraint
7971 than the one we are trying to add. */
7972 Mnode *min_mp = NULL;
7973 /* This can be negative, since it is only a constraint. */
7974 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7977 /* If we can't reach the current pool from this insn, or if we can't
7978 insert this entry at the end of the pool without pushing other
7979 fixes out of range, then we don't try. This ensures that we
7980 can't fail later on. */
7981 if (min_address >= minipool_barrier->address
7982 || (minipool_vector_tail->min_address + fix->fix_size
7983 >= minipool_barrier->address))
7986 /* Scan the pool to see if a constant with the same value has
7987 already been added. While we are doing this, also note the
7988 location where we must insert the constant if it doesn't already
7990 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7992 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7993 && fix->mode == mp->mode
7994 && (GET_CODE (fix->value) != CODE_LABEL
7995 || (CODE_LABEL_NUMBER (fix->value)
7996 == CODE_LABEL_NUMBER (mp->value)))
7997 && rtx_equal_p (fix->value, mp->value)
7998 /* Check that there is enough slack to move this entry to the
7999 end of the table (this is conservative). */
8001 > (minipool_barrier->address
8002 + minipool_vector_tail->offset
8003 + minipool_vector_tail->fix_size)))
8006 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8010 mp->min_address += fix->fix_size;
8013 /* Note the insertion point if necessary. */
8014 if (mp->min_address < min_address)
8016 /* For now, we do not allow the insertion of 8-byte alignment
8017 requiring nodes anywhere but at the start of the pool. */
8018 if (ARM_DOUBLEWORD_ALIGN
8019 && fix->fix_size == 8 && mp->fix_size != 8)
8024 else if (mp->max_address
8025 < minipool_barrier->address + mp->offset + fix->fix_size)
8027 /* Inserting before this entry would push the fix beyond
8028 its maximum address (which can happen if we have
8029 re-located a forwards fix); force the new fix to come
8032 min_address = mp->min_address + fix->fix_size;
8034 /* If we are inserting an 8-bytes aligned quantity and
8035 we have not already found an insertion point, then
8036 make sure that all such 8-byte aligned quantities are
8037 placed at the start of the pool. */
8038 else if (ARM_DOUBLEWORD_ALIGN
8040 && fix->fix_size == 8
8041 && mp->fix_size < 8)
8044 min_address = mp->min_address + fix->fix_size;
8049 /* We need to create a new entry. */
8051 mp->fix_size = fix->fix_size;
8052 mp->mode = fix->mode;
8053 mp->value = fix->value;
8055 mp->max_address = minipool_barrier->address + 65536;
8057 mp->min_address = min_address;
8062 mp->next = minipool_vector_head;
8064 if (mp->next == NULL)
8066 minipool_vector_tail = mp;
8067 minipool_vector_label = gen_label_rtx ();
8070 mp->next->prev = mp;
8072 minipool_vector_head = mp;
8076 mp->next = min_mp->next;
8080 if (mp->next != NULL)
8081 mp->next->prev = mp;
8083 minipool_vector_tail = mp;
8086 /* Save the new entry. */
8094 /* Scan over the following entries and adjust their offsets. */
8095 while (mp->next != NULL)
8097 if (mp->next->min_address < mp->min_address + mp->fix_size)
8098 mp->next->min_address = mp->min_address + mp->fix_size;
8101 mp->next->offset = mp->offset + mp->fix_size;
8103 mp->next->offset = mp->offset;
8112 assign_minipool_offsets (Mfix *barrier)
8114 HOST_WIDE_INT offset = 0;
8117 minipool_barrier = barrier;
8119 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8121 mp->offset = offset;
8123 if (mp->refcount > 0)
8124 offset += mp->fix_size;
8128 /* Output the literal table */
8130 dump_minipool (rtx scan)
8136 if (ARM_DOUBLEWORD_ALIGN)
8137 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8138 if (mp->refcount > 0 && mp->fix_size == 8)
8146 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8147 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
8149 scan = emit_label_after (gen_label_rtx (), scan);
8150 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
8151 scan = emit_label_after (minipool_vector_label, scan);
8153 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8155 if (mp->refcount > 0)
8160 ";; Offset %u, min %ld, max %ld ",
8161 (unsigned) mp->offset, (unsigned long) mp->min_address,
8162 (unsigned long) mp->max_address);
8163 arm_print_value (dump_file, mp->value);
8164 fputc ('\n', dump_file);
8167 switch (mp->fix_size)
8169 #ifdef HAVE_consttable_1
8171 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8175 #ifdef HAVE_consttable_2
8177 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8181 #ifdef HAVE_consttable_4
8183 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8187 #ifdef HAVE_consttable_8
8189 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8202 minipool_vector_head = minipool_vector_tail = NULL;
8203 scan = emit_insn_after (gen_consttable_end (), scan);
8204 scan = emit_barrier_after (scan);
8207 /* Return the cost of forcibly inserting a barrier after INSN. */
8209 arm_barrier_cost (rtx insn)
8211 /* Basing the location of the pool on the loop depth is preferable,
8212 but at the moment, the basic block information seems to be
8213 corrupt by this stage of the compilation. */
8215 rtx next = next_nonnote_insn (insn);
8217 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8220 switch (GET_CODE (insn))
8223 /* It will always be better to place the table before the label, rather
8232 return base_cost - 10;
8235 return base_cost + 10;
8239 /* Find the best place in the insn stream in the range
8240 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8241 Create the barrier by inserting a jump and add a new fix entry for
8244 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
8246 HOST_WIDE_INT count = 0;
8248 rtx from = fix->insn;
8249 /* The instruction after which we will insert the jump. */
8250 rtx selected = NULL;
8252 /* The address at which the jump instruction will be placed. */
8253 HOST_WIDE_INT selected_address;
8255 HOST_WIDE_INT max_count = max_address - fix->address;
8256 rtx label = gen_label_rtx ();
8258 selected_cost = arm_barrier_cost (from);
8259 selected_address = fix->address;
8261 while (from && count < max_count)
8266 /* This code shouldn't have been called if there was a natural barrier
8268 gcc_assert (GET_CODE (from) != BARRIER);
8270 /* Count the length of this insn. */
8271 count += get_attr_length (from);
8273 /* If there is a jump table, add its length. */
8274 tmp = is_jump_table (from);
8277 count += get_jump_table_size (tmp);
8279 /* Jump tables aren't in a basic block, so base the cost on
8280 the dispatch insn. If we select this location, we will
8281 still put the pool after the table. */
8282 new_cost = arm_barrier_cost (from);
8284 if (count < max_count
8285 && (!selected || new_cost <= selected_cost))
8288 selected_cost = new_cost;
8289 selected_address = fix->address + count;
8292 /* Continue after the dispatch table. */
8293 from = NEXT_INSN (tmp);
8297 new_cost = arm_barrier_cost (from);
8299 if (count < max_count
8300 && (!selected || new_cost <= selected_cost))
8303 selected_cost = new_cost;
8304 selected_address = fix->address + count;
8307 from = NEXT_INSN (from);
8310 /* Make sure that we found a place to insert the jump. */
8311 gcc_assert (selected);
8313 /* Create a new JUMP_INSN that branches around a barrier. */
8314 from = emit_jump_insn_after (gen_jump (label), selected);
8315 JUMP_LABEL (from) = label;
8316 barrier = emit_barrier_after (from);
8317 emit_label_after (label, barrier);
8319 /* Create a minipool barrier entry for the new barrier. */
8320 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
8321 new_fix->insn = barrier;
8322 new_fix->address = selected_address;
8323 new_fix->next = fix->next;
8324 fix->next = new_fix;
8329 /* Record that there is a natural barrier in the insn stream at
8332 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
8334 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8337 fix->address = address;
8340 if (minipool_fix_head != NULL)
8341 minipool_fix_tail->next = fix;
8343 minipool_fix_head = fix;
8345 minipool_fix_tail = fix;
8348 /* Record INSN, which will need fixing up to load a value from the
8349 minipool. ADDRESS is the offset of the insn since the start of the
8350 function; LOC is a pointer to the part of the insn which requires
8351 fixing; VALUE is the constant that must be loaded, which is of type
8354 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8355 enum machine_mode mode, rtx value)
8357 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8359 #ifdef AOF_ASSEMBLER
8360 /* PIC symbol references need to be converted into offsets into the
8362 /* XXX This shouldn't be done here. */
8363 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8364 value = aof_pic_entry (value);
8365 #endif /* AOF_ASSEMBLER */
8368 fix->address = address;
8371 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8373 fix->forwards = get_attr_pool_range (insn);
8374 fix->backwards = get_attr_neg_pool_range (insn);
8375 fix->minipool = NULL;
8377 /* If an insn doesn't have a range defined for it, then it isn't
8378 expecting to be reworked by this code. Better to stop now than
8379 to generate duff assembly code. */
8380 gcc_assert (fix->forwards || fix->backwards);
8382 /* If an entry requires 8-byte alignment then assume all constant pools
8383 require 4 bytes of padding. Trying to do this later on a per-pool
8384 basis is awkward because existing pool entries have to be modified. */
8385 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8391 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8392 GET_MODE_NAME (mode),
8393 INSN_UID (insn), (unsigned long) address,
8394 -1 * (long)fix->backwards, (long)fix->forwards);
8395 arm_print_value (dump_file, fix->value);
8396 fprintf (dump_file, "\n");
8399 /* Add it to the chain of fixes. */
8402 if (minipool_fix_head != NULL)
8403 minipool_fix_tail->next = fix;
8405 minipool_fix_head = fix;
8407 minipool_fix_tail = fix;
8410 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8411 Returns the number of insns needed, or 99 if we don't know how to
8414 arm_const_double_inline_cost (rtx val)
8416 rtx lowpart, highpart;
8417 enum machine_mode mode;
8419 mode = GET_MODE (val);
8421 if (mode == VOIDmode)
8424 gcc_assert (GET_MODE_SIZE (mode) == 8);
8426 lowpart = gen_lowpart (SImode, val);
8427 highpart = gen_highpart_mode (SImode, mode, val);
8429 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8430 gcc_assert (GET_CODE (highpart) == CONST_INT);
8432 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8433 NULL_RTX, NULL_RTX, 0, 0)
8434 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8435 NULL_RTX, NULL_RTX, 0, 0));
8438 /* Return true if it is worthwhile to split a 64-bit constant into two
8439 32-bit operations. This is the case if optimizing for size, or
8440 if we have load delay slots, or if one 32-bit part can be done with
8441 a single data operation. */
8443 arm_const_double_by_parts (rtx val)
8445 enum machine_mode mode = GET_MODE (val);
8448 if (optimize_size || arm_ld_sched)
8451 if (mode == VOIDmode)
8454 part = gen_highpart_mode (SImode, mode, val);
8456 gcc_assert (GET_CODE (part) == CONST_INT);
8458 if (const_ok_for_arm (INTVAL (part))
8459 || const_ok_for_arm (~INTVAL (part)))
8462 part = gen_lowpart (SImode, val);
8464 gcc_assert (GET_CODE (part) == CONST_INT);
8466 if (const_ok_for_arm (INTVAL (part))
8467 || const_ok_for_arm (~INTVAL (part)))
8473 /* Scan INSN and note any of its operands that need fixing.
8474 If DO_PUSHES is false we do not actually push any of the fixups
8475 needed. The function returns TRUE if any fixups were needed/pushed.
8476 This is used by arm_memory_load_p() which needs to know about loads
8477 of constants that will be converted into minipool loads. */
8479 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8481 bool result = false;
8484 extract_insn (insn);
8486 if (!constrain_operands (1))
8487 fatal_insn_not_found (insn);
8489 if (recog_data.n_alternatives == 0)
8492 /* Fill in recog_op_alt with information about the constraints of
8494 preprocess_constraints ();
8496 for (opno = 0; opno < recog_data.n_operands; opno++)
8498 /* Things we need to fix can only occur in inputs. */
8499 if (recog_data.operand_type[opno] != OP_IN)
8502 /* If this alternative is a memory reference, then any mention
8503 of constants in this alternative is really to fool reload
8504 into allowing us to accept one there. We need to fix them up
8505 now so that we output the right code. */
8506 if (recog_op_alt[opno][which_alternative].memory_ok)
8508 rtx op = recog_data.operand[opno];
8510 if (CONSTANT_P (op))
8513 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8514 recog_data.operand_mode[opno], op);
8517 else if (GET_CODE (op) == MEM
8518 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8519 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8523 rtx cop = avoid_constant_pool_reference (op);
8525 /* Casting the address of something to a mode narrower
8526 than a word can cause avoid_constant_pool_reference()
8527 to return the pool reference itself. That's no good to
8528 us here. Lets just hope that we can use the
8529 constant pool value directly. */
8531 cop = get_pool_constant (XEXP (op, 0));
8533 push_minipool_fix (insn, address,
8534 recog_data.operand_loc[opno],
8535 recog_data.operand_mode[opno], cop);
8546 /* Gcc puts the pool in the wrong place for ARM, since we can only
8547 load addresses a limited distance around the pc. We do some
8548 special munging to move the constant pool values to the correct
8549 point in the code. */
8554 HOST_WIDE_INT address = 0;
8557 minipool_fix_head = minipool_fix_tail = NULL;
8559 /* The first insn must always be a note, or the code below won't
8560 scan it properly. */
8561 insn = get_insns ();
8562 gcc_assert (GET_CODE (insn) == NOTE);
8565 /* Scan all the insns and record the operands that will need fixing. */
8566 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8568 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8569 && (arm_cirrus_insn_p (insn)
8570 || GET_CODE (insn) == JUMP_INSN
8571 || arm_memory_load_p (insn)))
8572 cirrus_reorg (insn);
8574 if (GET_CODE (insn) == BARRIER)
8575 push_minipool_barrier (insn, address);
8576 else if (INSN_P (insn))
8580 note_invalid_constants (insn, address, true);
8581 address += get_attr_length (insn);
8583 /* If the insn is a vector jump, add the size of the table
8584 and skip the table. */
8585 if ((table = is_jump_table (insn)) != NULL)
8587 address += get_jump_table_size (table);
8593 fix = minipool_fix_head;
8595 /* Now scan the fixups and perform the required changes. */
8600 Mfix * last_added_fix;
8601 Mfix * last_barrier = NULL;
8604 /* Skip any further barriers before the next fix. */
8605 while (fix && GET_CODE (fix->insn) == BARRIER)
8608 /* No more fixes. */
8612 last_added_fix = NULL;
8614 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8616 if (GET_CODE (ftmp->insn) == BARRIER)
8618 if (ftmp->address >= minipool_vector_head->max_address)
8621 last_barrier = ftmp;
8623 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8626 last_added_fix = ftmp; /* Keep track of the last fix added. */
8629 /* If we found a barrier, drop back to that; any fixes that we
8630 could have reached but come after the barrier will now go in
8631 the next mini-pool. */
8632 if (last_barrier != NULL)
8634 /* Reduce the refcount for those fixes that won't go into this
8636 for (fdel = last_barrier->next;
8637 fdel && fdel != ftmp;
8640 fdel->minipool->refcount--;
8641 fdel->minipool = NULL;
8644 ftmp = last_barrier;
8648 /* ftmp is first fix that we can't fit into this pool and
8649 there no natural barriers that we could use. Insert a
8650 new barrier in the code somewhere between the previous
8651 fix and this one, and arrange to jump around it. */
8652 HOST_WIDE_INT max_address;
8654 /* The last item on the list of fixes must be a barrier, so
8655 we can never run off the end of the list of fixes without
8656 last_barrier being set. */
8659 max_address = minipool_vector_head->max_address;
8660 /* Check that there isn't another fix that is in range that
8661 we couldn't fit into this pool because the pool was
8662 already too large: we need to put the pool before such an
8663 instruction. The pool itself may come just after the
8664 fix because create_fix_barrier also allows space for a
8665 jump instruction. */
8666 if (ftmp->address < max_address)
8667 max_address = ftmp->address + 1;
8669 last_barrier = create_fix_barrier (last_added_fix, max_address);
8672 assign_minipool_offsets (last_barrier);
8676 if (GET_CODE (ftmp->insn) != BARRIER
8677 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8684 /* Scan over the fixes we have identified for this pool, fixing them
8685 up and adding the constants to the pool itself. */
8686 for (this_fix = fix; this_fix && ftmp != this_fix;
8687 this_fix = this_fix->next)
8688 if (GET_CODE (this_fix->insn) != BARRIER)
8691 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8692 minipool_vector_label),
8693 this_fix->minipool->offset);
8694 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8697 dump_minipool (last_barrier->insn);
8701 /* From now on we must synthesize any constants that we can't handle
8702 directly. This can happen if the RTL gets split during final
8703 instruction generation. */
8704 after_arm_reorg = 1;
8706 /* Free the minipool memory. */
8707 obstack_free (&minipool_obstack, minipool_startobj);
8710 /* Routines to output assembly language. */
8712 /* If the rtx is the correct value then return the string of the number.
8713 In this way we can ensure that valid double constants are generated even
8714 when cross compiling. */
8716 fp_immediate_constant (rtx x)
8721 if (!fp_consts_inited)
8724 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8725 for (i = 0; i < 8; i++)
8726 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8727 return strings_fp[i];
8732 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8734 fp_const_from_val (REAL_VALUE_TYPE *r)
8738 if (!fp_consts_inited)
8741 for (i = 0; i < 8; i++)
8742 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8743 return strings_fp[i];
8748 /* Output the operands of a LDM/STM instruction to STREAM.
8749 MASK is the ARM register set mask of which only bits 0-15 are important.
8750 REG is the base register, either the frame pointer or the stack pointer,
8751 INSTR is the possibly suffixed load or store instruction.
8752 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8755 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8756 unsigned long mask, int rfe)
8759 bool not_first = FALSE;
8761 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
8762 fputc ('\t', stream);
8763 asm_fprintf (stream, instr, reg);
8764 fputc ('{', stream);
8766 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8767 if (mask & (1 << i))
8770 fprintf (stream, ", ");
8772 asm_fprintf (stream, "%r", i);
8777 fprintf (stream, "}^\n");
8779 fprintf (stream, "}\n");
8783 /* Output a FLDMD instruction to STREAM.
8784 BASE if the register containing the address.
8785 REG and COUNT specify the register range.
8786 Extra registers may be added to avoid hardware bugs.
8788 We output FLDMD even for ARMv5 VFP implementations. Although
8789 FLDMD is technically not supported until ARMv6, it is believed
8790 that all VFP implementations support its use in this context. */
8793 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
8797 /* Workaround ARM10 VFPr1 bug. */
8798 if (count == 2 && !arm_arch6)
8805 fputc ('\t', stream);
8806 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
8808 for (i = reg; i < reg + count; i++)
8811 fputs (", ", stream);
8812 asm_fprintf (stream, "d%d", i);
8814 fputs ("}\n", stream);
8819 /* Output the assembly for a store multiple. */
8822 vfp_output_fstmd (rtx * operands)
8829 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
8830 p = strlen (pattern);
8832 gcc_assert (GET_CODE (operands[1]) == REG);
8834 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8835 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8837 p += sprintf (&pattern[p], ", d%d", base + i);
8839 strcpy (&pattern[p], "}");
8841 output_asm_insn (pattern, operands);
8846 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8847 number of bytes pushed. */
8850 vfp_emit_fstmd (int base_reg, int count)
8857 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8858 register pairs are stored by a store multiple insn. We avoid this
8859 by pushing an extra pair. */
8860 if (count == 2 && !arm_arch6)
8862 if (base_reg == LAST_VFP_REGNUM - 3)
8867 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8868 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8870 reg = gen_rtx_REG (DFmode, base_reg);
8874 = gen_rtx_SET (VOIDmode,
8875 gen_frame_mem (BLKmode,
8876 gen_rtx_PRE_DEC (BLKmode,
8877 stack_pointer_rtx)),
8878 gen_rtx_UNSPEC (BLKmode,
8882 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8883 plus_constant (stack_pointer_rtx, -(count * 8)));
8884 RTX_FRAME_RELATED_P (tmp) = 1;
8885 XVECEXP (dwarf, 0, 0) = tmp;
8887 tmp = gen_rtx_SET (VOIDmode,
8888 gen_frame_mem (DFmode, stack_pointer_rtx),
8890 RTX_FRAME_RELATED_P (tmp) = 1;
8891 XVECEXP (dwarf, 0, 1) = tmp;
8893 for (i = 1; i < count; i++)
8895 reg = gen_rtx_REG (DFmode, base_reg);
8897 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8899 tmp = gen_rtx_SET (VOIDmode,
8900 gen_frame_mem (DFmode,
8901 plus_constant (stack_pointer_rtx,
8904 RTX_FRAME_RELATED_P (tmp) = 1;
8905 XVECEXP (dwarf, 0, i + 1) = tmp;
8908 par = emit_insn (par);
8909 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8911 RTX_FRAME_RELATED_P (par) = 1;
8916 /* Emit a call instruction with pattern PAT. ADDR is the address of
8920 arm_emit_call_insn (rtx pat, rtx addr)
8924 insn = emit_call_insn (pat);
8926 /* The PIC register is live on entry to VxWorks PIC PLT entries.
8927 If the call might use such an entry, add a use of the PIC register
8928 to the instruction's CALL_INSN_FUNCTION_USAGE. */
8929 if (TARGET_VXWORKS_RTP
8931 && GET_CODE (addr) == SYMBOL_REF
8932 && (SYMBOL_REF_DECL (addr)
8933 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
8934 : !SYMBOL_REF_LOCAL_P (addr)))
8936 require_pic_register ();
8937 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
8941 /* Output a 'call' insn. */
8943 output_call (rtx *operands)
8945 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8947 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8948 if (REGNO (operands[0]) == LR_REGNUM)
8950 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8951 output_asm_insn ("mov%?\t%0, %|lr", operands);
8954 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8956 if (TARGET_INTERWORK || arm_arch4t)
8957 output_asm_insn ("bx%?\t%0", operands);
8959 output_asm_insn ("mov%?\t%|pc, %0", operands);
8964 /* Output a 'call' insn that is a reference in memory. */
8966 output_call_mem (rtx *operands)
8968 if (TARGET_INTERWORK && !arm_arch5)
8970 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8971 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8972 output_asm_insn ("bx%?\t%|ip", operands);
8974 else if (regno_use_in (LR_REGNUM, operands[0]))
8976 /* LR is used in the memory address. We load the address in the
8977 first instruction. It's safe to use IP as the target of the
8978 load since the call will kill it anyway. */
8979 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8981 output_asm_insn ("blx%?\t%|ip", operands);
8984 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8986 output_asm_insn ("bx%?\t%|ip", operands);
8988 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8993 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8994 output_asm_insn ("ldr%?\t%|pc, %0", operands);
9001 /* Output a move from arm registers to an fpa registers.
9002 OPERANDS[0] is an fpa register.
9003 OPERANDS[1] is the first registers of an arm register pair. */
9005 output_mov_long_double_fpa_from_arm (rtx *operands)
9007 int arm_reg0 = REGNO (operands[1]);
9010 gcc_assert (arm_reg0 != IP_REGNUM);
9012 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9013 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9014 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9016 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9017 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
9022 /* Output a move from an fpa register to arm registers.
9023 OPERANDS[0] is the first registers of an arm register pair.
9024 OPERANDS[1] is an fpa register. */
9026 output_mov_long_double_arm_from_fpa (rtx *operands)
9028 int arm_reg0 = REGNO (operands[0]);
9031 gcc_assert (arm_reg0 != IP_REGNUM);
9033 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9034 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9035 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9037 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
9038 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9042 /* Output a move from arm registers to arm registers of a long double
9043 OPERANDS[0] is the destination.
9044 OPERANDS[1] is the source. */
9046 output_mov_long_double_arm_from_arm (rtx *operands)
9048 /* We have to be careful here because the two might overlap. */
9049 int dest_start = REGNO (operands[0]);
9050 int src_start = REGNO (operands[1]);
9054 if (dest_start < src_start)
9056 for (i = 0; i < 3; i++)
9058 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9059 ops[1] = gen_rtx_REG (SImode, src_start + i);
9060 output_asm_insn ("mov%?\t%0, %1", ops);
9065 for (i = 2; i >= 0; i--)
9067 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9068 ops[1] = gen_rtx_REG (SImode, src_start + i);
9069 output_asm_insn ("mov%?\t%0, %1", ops);
9077 /* Output a move from arm registers to an fpa registers.
9078 OPERANDS[0] is an fpa register.
9079 OPERANDS[1] is the first registers of an arm register pair. */
9081 output_mov_double_fpa_from_arm (rtx *operands)
9083 int arm_reg0 = REGNO (operands[1]);
9086 gcc_assert (arm_reg0 != IP_REGNUM);
9088 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9089 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9090 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
9091 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
9095 /* Output a move from an fpa register to arm registers.
9096 OPERANDS[0] is the first registers of an arm register pair.
9097 OPERANDS[1] is an fpa register. */
9099 output_mov_double_arm_from_fpa (rtx *operands)
9101 int arm_reg0 = REGNO (operands[0]);
9104 gcc_assert (arm_reg0 != IP_REGNUM);
9106 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9107 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9108 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
9109 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
9113 /* Output a move between double words.
9114 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9115 or MEM<-REG and all MEMs must be offsettable addresses. */
9117 output_move_double (rtx *operands)
9119 enum rtx_code code0 = GET_CODE (operands[0]);
9120 enum rtx_code code1 = GET_CODE (operands[1]);
9125 int reg0 = REGNO (operands[0]);
9127 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9129 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9131 switch (GET_CODE (XEXP (operands[1], 0)))
9134 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
9138 gcc_assert (TARGET_LDRD);
9139 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
9144 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9146 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
9150 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
9154 gcc_assert (TARGET_LDRD);
9155 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
9160 otherops[0] = operands[0];
9161 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9162 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
9164 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
9166 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9168 /* Registers overlap so split out the increment. */
9169 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9170 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
9174 /* IWMMXT allows offsets larger than ldrd can handle,
9175 fix these up with a pair of ldr. */
9176 if (GET_CODE (otherops[2]) == CONST_INT
9177 && (INTVAL(otherops[2]) <= -256
9178 || INTVAL(otherops[2]) >= 256))
9180 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9181 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9182 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9185 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9190 /* IWMMXT allows offsets larger than ldrd can handle,
9191 fix these up with a pair of ldr. */
9192 if (GET_CODE (otherops[2]) == CONST_INT
9193 && (INTVAL(otherops[2]) <= -256
9194 || INTVAL(otherops[2]) >= 256))
9196 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9197 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9198 otherops[0] = operands[0];
9199 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9202 /* We only allow constant increments, so this is safe. */
9203 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
9209 output_asm_insn ("adr%?\t%0, %1", operands);
9210 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
9213 /* ??? This needs checking for thumb2. */
9215 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9216 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9218 otherops[0] = operands[0];
9219 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9220 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
9222 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
9224 if (GET_CODE (otherops[2]) == CONST_INT)
9226 switch ((int) INTVAL (otherops[2]))
9229 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
9234 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
9239 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
9244 && (GET_CODE (otherops[2]) == REG
9245 || (GET_CODE (otherops[2]) == CONST_INT
9246 && INTVAL (otherops[2]) > -256
9247 && INTVAL (otherops[2]) < 256)))
9249 if (reg_overlap_mentioned_p (otherops[0],
9252 /* Swap base and index registers over to
9253 avoid a conflict. */
9254 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9255 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
9257 /* If both registers conflict, it will usually
9258 have been fixed by a splitter. */
9259 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9261 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9262 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9266 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
9270 if (GET_CODE (otherops[2]) == CONST_INT)
9272 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
9273 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
9275 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9278 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9281 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
9283 return "ldm%(ia%)\t%0, %M0";
9287 otherops[1] = adjust_address (operands[1], SImode, 4);
9288 /* Take care of overlapping base/data reg. */
9289 if (reg_mentioned_p (operands[0], operands[1]))
9291 output_asm_insn ("ldr%?\t%0, %1", otherops);
9292 output_asm_insn ("ldr%?\t%0, %1", operands);
9296 output_asm_insn ("ldr%?\t%0, %1", operands);
9297 output_asm_insn ("ldr%?\t%0, %1", otherops);
9304 /* Constraints should ensure this. */
9305 gcc_assert (code0 == MEM && code1 == REG);
9306 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
9308 switch (GET_CODE (XEXP (operands[0], 0)))
9311 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9315 gcc_assert (TARGET_LDRD);
9316 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9321 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
9323 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9327 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9331 gcc_assert (TARGET_LDRD);
9332 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
9337 otherops[0] = operands[1];
9338 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
9339 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
9341 /* IWMMXT allows offsets larger than ldrd can handle,
9342 fix these up with a pair of ldr. */
9343 if (GET_CODE (otherops[2]) == CONST_INT
9344 && (INTVAL(otherops[2]) <= -256
9345 || INTVAL(otherops[2]) >= 256))
9348 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9349 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9351 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9353 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9358 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9359 otherops[0] = operands[1];
9360 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9363 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9364 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
9366 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9370 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
9371 if (GET_CODE (otherops[2]) == CONST_INT)
9373 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
9376 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
9382 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
9388 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
9393 && (GET_CODE (otherops[2]) == REG
9394 || (GET_CODE (otherops[2]) == CONST_INT
9395 && INTVAL (otherops[2]) > -256
9396 && INTVAL (otherops[2]) < 256)))
9398 otherops[0] = operands[1];
9399 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9400 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
9406 otherops[0] = adjust_address (operands[0], SImode, 4);
9407 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9408 output_asm_insn ("str%?\t%1, %0", operands);
9409 output_asm_insn ("str%?\t%1, %0", otherops);
9416 /* Output a VFP load or store instruction. */
9419 output_move_vfp (rtx *operands)
9421 rtx reg, mem, addr, ops[2];
9422 int load = REG_P (operands[0]);
9423 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
9424 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
9425 const char *template;
9428 reg = operands[!load];
9429 mem = operands[load];
9431 gcc_assert (REG_P (reg));
9432 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
9433 gcc_assert (GET_MODE (reg) == SFmode
9434 || GET_MODE (reg) == DFmode
9435 || GET_MODE (reg) == SImode
9436 || GET_MODE (reg) == DImode);
9437 gcc_assert (MEM_P (mem));
9439 addr = XEXP (mem, 0);
9441 switch (GET_CODE (addr))
9444 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9445 ops[0] = XEXP (addr, 0);
9450 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9451 ops[0] = XEXP (addr, 0);
9456 template = "f%s%c%%?\t%%%s0, %%1%s";
9462 sprintf (buff, template,
9466 integer_p ? "\t%@ int" : "");
9467 output_asm_insn (buff, ops);
9472 /* Output an ADD r, s, #n where n may be too big for one instruction.
9473 If adding zero to one register, output nothing. */
9475 output_add_immediate (rtx *operands)
9477 HOST_WIDE_INT n = INTVAL (operands[2]);
9479 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9482 output_multi_immediate (operands,
9483 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9486 output_multi_immediate (operands,
9487 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9494 /* Output a multiple immediate operation.
9495 OPERANDS is the vector of operands referred to in the output patterns.
9496 INSTR1 is the output pattern to use for the first constant.
9497 INSTR2 is the output pattern to use for subsequent constants.
9498 IMMED_OP is the index of the constant slot in OPERANDS.
9499 N is the constant value. */
9501 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9502 int immed_op, HOST_WIDE_INT n)
9504 #if HOST_BITS_PER_WIDE_INT > 32
9510 /* Quick and easy output. */
9511 operands[immed_op] = const0_rtx;
9512 output_asm_insn (instr1, operands);
9517 const char * instr = instr1;
9519 /* Note that n is never zero here (which would give no output). */
9520 for (i = 0; i < 32; i += 2)
9524 operands[immed_op] = GEN_INT (n & (255 << i));
9525 output_asm_insn (instr, operands);
9535 /* Return the name of a shifter operation. */
9537 arm_shift_nmem(enum rtx_code code)
9542 return ARM_LSL_NAME;
9558 /* Return the appropriate ARM instruction for the operation code.
9559 The returned result should not be overwritten. OP is the rtx of the
9560 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9563 arithmetic_instr (rtx op, int shift_first_arg)
9565 switch (GET_CODE (op))
9571 return shift_first_arg ? "rsb" : "sub";
9586 return arm_shift_nmem(GET_CODE(op));
9593 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9594 for the operation code. The returned result should not be overwritten.
9595 OP is the rtx code of the shift.
9596 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9599 shift_op (rtx op, HOST_WIDE_INT *amountp)
9602 enum rtx_code code = GET_CODE (op);
9604 switch (GET_CODE (XEXP (op, 1)))
9612 *amountp = INTVAL (XEXP (op, 1));
9622 gcc_assert (*amountp != -1);
9623 *amountp = 32 - *amountp;
9632 mnem = arm_shift_nmem(code);
9636 /* We never have to worry about the amount being other than a
9637 power of 2, since this case can never be reloaded from a reg. */
9638 gcc_assert (*amountp != -1);
9639 *amountp = int_log2 (*amountp);
9640 return ARM_LSL_NAME;
9648 /* This is not 100% correct, but follows from the desire to merge
9649 multiplication by a power of 2 with the recognizer for a
9650 shift. >=32 is not a valid shift for "lsl", so we must try and
9651 output a shift that produces the correct arithmetical result.
9652 Using lsr #32 is identical except for the fact that the carry bit
9653 is not set correctly if we set the flags; but we never use the
9654 carry bit from such an operation, so we can ignore that. */
9655 if (code == ROTATERT)
9656 /* Rotate is just modulo 32. */
9658 else if (*amountp != (*amountp & 31))
9665 /* Shifts of 0 are no-ops. */
9673 /* Obtain the shift from the POWER of two. */
9675 static HOST_WIDE_INT
9676 int_log2 (HOST_WIDE_INT power)
9678 HOST_WIDE_INT shift = 0;
9680 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9682 gcc_assert (shift <= 31);
9689 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9690 because /bin/as is horribly restrictive. The judgement about
9691 whether or not each character is 'printable' (and can be output as
9692 is) or not (and must be printed with an octal escape) must be made
9693 with reference to the *host* character set -- the situation is
9694 similar to that discussed in the comments above pp_c_char in
9695 c-pretty-print.c. */
9697 #define MAX_ASCII_LEN 51
9700 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9705 fputs ("\t.ascii\t\"", stream);
9707 for (i = 0; i < len; i++)
9711 if (len_so_far >= MAX_ASCII_LEN)
9713 fputs ("\"\n\t.ascii\t\"", stream);
9719 if (c == '\\' || c == '\"')
9721 putc ('\\', stream);
9729 fprintf (stream, "\\%03o", c);
9734 fputs ("\"\n", stream);
9737 /* Compute the register save mask for registers 0 through 12
9738 inclusive. This code is used by arm_compute_save_reg_mask. */
9740 static unsigned long
9741 arm_compute_save_reg0_reg12_mask (void)
9743 unsigned long func_type = arm_current_func_type ();
9744 unsigned long save_reg_mask = 0;
9747 if (IS_INTERRUPT (func_type))
9749 unsigned int max_reg;
9750 /* Interrupt functions must not corrupt any registers,
9751 even call clobbered ones. If this is a leaf function
9752 we can just examine the registers used by the RTL, but
9753 otherwise we have to assume that whatever function is
9754 called might clobber anything, and so we have to save
9755 all the call-clobbered registers as well. */
9756 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9757 /* FIQ handlers have registers r8 - r12 banked, so
9758 we only need to check r0 - r7, Normal ISRs only
9759 bank r14 and r15, so we must check up to r12.
9760 r13 is the stack pointer which is always preserved,
9761 so we do not need to consider it here. */
9766 for (reg = 0; reg <= max_reg; reg++)
9767 if (regs_ever_live[reg]
9768 || (! current_function_is_leaf && call_used_regs [reg]))
9769 save_reg_mask |= (1 << reg);
9771 /* Also save the pic base register if necessary. */
9773 && !TARGET_SINGLE_PIC_BASE
9774 && arm_pic_register != INVALID_REGNUM
9775 && current_function_uses_pic_offset_table)
9776 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9780 /* In arm mode we handle r11 (FP) as a special case. */
9781 unsigned last_reg = TARGET_ARM ? 10 : 11;
9783 /* In the normal case we only need to save those registers
9784 which are call saved and which are used by this function. */
9785 for (reg = 0; reg <= last_reg; reg++)
9786 if (regs_ever_live[reg] && ! call_used_regs [reg])
9787 save_reg_mask |= (1 << reg);
9789 /* Handle the frame pointer as a special case. */
9790 if (TARGET_THUMB2 && frame_pointer_needed)
9791 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9792 else if (! TARGET_APCS_FRAME
9793 && ! frame_pointer_needed
9794 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9795 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9796 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9798 /* If we aren't loading the PIC register,
9799 don't stack it even though it may be live. */
9801 && !TARGET_SINGLE_PIC_BASE
9802 && arm_pic_register != INVALID_REGNUM
9803 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
9804 || current_function_uses_pic_offset_table))
9805 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9807 /* The prologue will copy SP into R0, so save it. */
9808 if (IS_STACKALIGN (func_type))
9812 /* Save registers so the exception handler can modify them. */
9813 if (current_function_calls_eh_return)
9819 reg = EH_RETURN_DATA_REGNO (i);
9820 if (reg == INVALID_REGNUM)
9822 save_reg_mask |= 1 << reg;
9826 return save_reg_mask;
9830 /* Compute a bit mask of which registers need to be
9831 saved on the stack for the current function. */
9833 static unsigned long
9834 arm_compute_save_reg_mask (void)
9836 unsigned int save_reg_mask = 0;
9837 unsigned long func_type = arm_current_func_type ();
9840 if (IS_NAKED (func_type))
9841 /* This should never really happen. */
9844 /* If we are creating a stack frame, then we must save the frame pointer,
9845 IP (which will hold the old stack pointer), LR and the PC. */
9846 if (frame_pointer_needed && TARGET_ARM)
9848 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9853 /* Volatile functions do not return, so there
9854 is no need to save any other registers. */
9855 if (IS_VOLATILE (func_type))
9856 return save_reg_mask;
9858 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9860 /* Decide if we need to save the link register.
9861 Interrupt routines have their own banked link register,
9862 so they never need to save it.
9863 Otherwise if we do not use the link register we do not need to save
9864 it. If we are pushing other registers onto the stack however, we
9865 can save an instruction in the epilogue by pushing the link register
9866 now and then popping it back into the PC. This incurs extra memory
9867 accesses though, so we only do it when optimizing for size, and only
9868 if we know that we will not need a fancy return sequence. */
9869 if (regs_ever_live [LR_REGNUM]
9872 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9873 && !current_function_calls_eh_return))
9874 save_reg_mask |= 1 << LR_REGNUM;
9876 if (cfun->machine->lr_save_eliminated)
9877 save_reg_mask &= ~ (1 << LR_REGNUM);
9879 if (TARGET_REALLY_IWMMXT
9880 && ((bit_count (save_reg_mask)
9881 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9883 /* The total number of registers that are going to be pushed
9884 onto the stack is odd. We need to ensure that the stack
9885 is 64-bit aligned before we start to save iWMMXt registers,
9886 and also before we start to create locals. (A local variable
9887 might be a double or long long which we will load/store using
9888 an iWMMXt instruction). Therefore we need to push another
9889 ARM register, so that the stack will be 64-bit aligned. We
9890 try to avoid using the arg registers (r0 -r3) as they might be
9891 used to pass values in a tail call. */
9892 for (reg = 4; reg <= 12; reg++)
9893 if ((save_reg_mask & (1 << reg)) == 0)
9897 save_reg_mask |= (1 << reg);
9900 cfun->machine->sibcall_blocked = 1;
9901 save_reg_mask |= (1 << 3);
9905 /* We may need to push an additional register for use initializing the
9906 PIC base register. */
9907 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
9908 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
9910 reg = thumb_find_work_register (1 << 4);
9911 if (!call_used_regs[reg])
9912 save_reg_mask |= (1 << reg);
9915 return save_reg_mask;
9919 /* Compute a bit mask of which registers need to be
9920 saved on the stack for the current function. */
9921 static unsigned long
9922 thumb1_compute_save_reg_mask (void)
9928 for (reg = 0; reg < 12; reg ++)
9929 if (regs_ever_live[reg] && !call_used_regs[reg])
9933 && !TARGET_SINGLE_PIC_BASE
9934 && arm_pic_register != INVALID_REGNUM
9935 && current_function_uses_pic_offset_table)
9936 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9938 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9939 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
9940 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
9942 /* LR will also be pushed if any lo regs are pushed. */
9943 if (mask & 0xff || thumb_force_lr_save ())
9944 mask |= (1 << LR_REGNUM);
9946 /* Make sure we have a low work register if we need one.
9947 We will need one if we are going to push a high register,
9948 but we are not currently intending to push a low register. */
9949 if ((mask & 0xff) == 0
9950 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9952 /* Use thumb_find_work_register to choose which register
9953 we will use. If the register is live then we will
9954 have to push it. Use LAST_LO_REGNUM as our fallback
9955 choice for the register to select. */
9956 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9958 if (! call_used_regs[reg])
9966 /* Return the number of bytes required to save VFP registers. */
9968 arm_get_vfp_saved_size (void)
9975 /* Space for saved VFP registers. */
9976 if (TARGET_HARD_FLOAT && TARGET_VFP)
9979 for (regno = FIRST_VFP_REGNUM;
9980 regno < LAST_VFP_REGNUM;
9983 if ((!regs_ever_live[regno] || call_used_regs[regno])
9984 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9988 /* Workaround ARM10 VFPr1 bug. */
9989 if (count == 2 && !arm_arch6)
10000 if (count == 2 && !arm_arch6)
10002 saved += count * 8;
10009 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
10010 everything bar the final return instruction. */
10012 output_return_instruction (rtx operand, int really_return, int reverse)
10014 char conditional[10];
10017 unsigned long live_regs_mask;
10018 unsigned long func_type;
10019 arm_stack_offsets *offsets;
10021 func_type = arm_current_func_type ();
10023 if (IS_NAKED (func_type))
10026 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10028 /* If this function was declared non-returning, and we have
10029 found a tail call, then we have to trust that the called
10030 function won't return. */
10035 /* Otherwise, trap an attempted return by aborting. */
10037 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
10039 assemble_external_libcall (ops[1]);
10040 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
10046 gcc_assert (!current_function_calls_alloca || really_return);
10048 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
10050 return_used_this_function = 1;
10052 live_regs_mask = arm_compute_save_reg_mask ();
10054 if (live_regs_mask)
10056 const char * return_reg;
10058 /* If we do not have any special requirements for function exit
10059 (e.g. interworking) then we can load the return address
10060 directly into the PC. Otherwise we must load it into LR. */
10062 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
10063 return_reg = reg_names[PC_REGNUM];
10065 return_reg = reg_names[LR_REGNUM];
10067 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
10069 /* There are three possible reasons for the IP register
10070 being saved. 1) a stack frame was created, in which case
10071 IP contains the old stack pointer, or 2) an ISR routine
10072 corrupted it, or 3) it was saved to align the stack on
10073 iWMMXt. In case 1, restore IP into SP, otherwise just
10075 if (frame_pointer_needed)
10077 live_regs_mask &= ~ (1 << IP_REGNUM);
10078 live_regs_mask |= (1 << SP_REGNUM);
10081 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
10084 /* On some ARM architectures it is faster to use LDR rather than
10085 LDM to load a single register. On other architectures, the
10086 cost is the same. In 26 bit mode, or for exception handlers,
10087 we have to use LDM to load the PC so that the CPSR is also
10089 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10090 if (live_regs_mask == (1U << reg))
10093 if (reg <= LAST_ARM_REGNUM
10094 && (reg != LR_REGNUM
10096 || ! IS_INTERRUPT (func_type)))
10098 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
10099 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
10106 /* Generate the load multiple instruction to restore the
10107 registers. Note we can get here, even if
10108 frame_pointer_needed is true, but only if sp already
10109 points to the base of the saved core registers. */
10110 if (live_regs_mask & (1 << SP_REGNUM))
10112 unsigned HOST_WIDE_INT stack_adjust;
10114 offsets = arm_get_frame_offsets ();
10115 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
10116 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
10118 if (stack_adjust && arm_arch5 && TARGET_ARM)
10119 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
10122 /* If we can't use ldmib (SA110 bug),
10123 then try to pop r3 instead. */
10125 live_regs_mask |= 1 << 3;
10126 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
10130 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
10132 p = instr + strlen (instr);
10134 for (reg = 0; reg <= SP_REGNUM; reg++)
10135 if (live_regs_mask & (1 << reg))
10137 int l = strlen (reg_names[reg]);
10143 memcpy (p, ", ", 2);
10147 memcpy (p, "%|", 2);
10148 memcpy (p + 2, reg_names[reg], l);
10152 if (live_regs_mask & (1 << LR_REGNUM))
10154 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
10155 /* If returning from an interrupt, restore the CPSR. */
10156 if (IS_INTERRUPT (func_type))
10163 output_asm_insn (instr, & operand);
10165 /* See if we need to generate an extra instruction to
10166 perform the actual function return. */
10168 && func_type != ARM_FT_INTERWORKED
10169 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
10171 /* The return has already been handled
10172 by loading the LR into the PC. */
10179 switch ((int) ARM_FUNC_TYPE (func_type))
10183 /* ??? This is wrong for unified assembly syntax. */
10184 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
10187 case ARM_FT_INTERWORKED:
10188 sprintf (instr, "bx%s\t%%|lr", conditional);
10191 case ARM_FT_EXCEPTION:
10192 /* ??? This is wrong for unified assembly syntax. */
10193 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
10197 /* Use bx if it's available. */
10198 if (arm_arch5 || arm_arch4t)
10199 sprintf (instr, "bx%s\t%%|lr", conditional);
10201 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
10205 output_asm_insn (instr, & operand);
10211 /* Write the function name into the code section, directly preceding
10212 the function prologue.
10214 Code will be output similar to this:
10216 .ascii "arm_poke_function_name", 0
10219 .word 0xff000000 + (t1 - t0)
10220 arm_poke_function_name
10222 stmfd sp!, {fp, ip, lr, pc}
10225 When performing a stack backtrace, code can inspect the value
10226 of 'pc' stored at 'fp' + 0. If the trace function then looks
10227 at location pc - 12 and the top 8 bits are set, then we know
10228 that there is a function name embedded immediately preceding this
10229 location and has length ((pc[-3]) & 0xff000000).
10231 We assume that pc is declared as a pointer to an unsigned long.
10233 It is of no benefit to output the function name if we are assembling
10234 a leaf function. These function types will not contain a stack
10235 backtrace structure, therefore it is not possible to determine the
10238 arm_poke_function_name (FILE *stream, const char *name)
10240 unsigned long alignlength;
10241 unsigned long length;
10244 length = strlen (name) + 1;
10245 alignlength = ROUND_UP_WORD (length);
10247 ASM_OUTPUT_ASCII (stream, name, length);
10248 ASM_OUTPUT_ALIGN (stream, 2);
10249 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
10250 assemble_aligned_integer (UNITS_PER_WORD, x);
10253 /* Place some comments into the assembler stream
10254 describing the current function. */
10256 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
10258 unsigned long func_type;
10262 thumb1_output_function_prologue (f, frame_size);
10266 /* Sanity check. */
10267 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
10269 func_type = arm_current_func_type ();
10271 switch ((int) ARM_FUNC_TYPE (func_type))
10274 case ARM_FT_NORMAL:
10276 case ARM_FT_INTERWORKED:
10277 asm_fprintf (f, "\t%@ Function supports interworking.\n");
10280 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
10283 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
10285 case ARM_FT_EXCEPTION:
10286 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
10290 if (IS_NAKED (func_type))
10291 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10293 if (IS_VOLATILE (func_type))
10294 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
10296 if (IS_NESTED (func_type))
10297 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
10298 if (IS_STACKALIGN (func_type))
10299 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10301 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10302 current_function_args_size,
10303 current_function_pretend_args_size, frame_size);
10305 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10306 frame_pointer_needed,
10307 cfun->machine->uses_anonymous_args);
10309 if (cfun->machine->lr_save_eliminated)
10310 asm_fprintf (f, "\t%@ link register save eliminated.\n");
10312 if (current_function_calls_eh_return)
10313 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
10315 #ifdef AOF_ASSEMBLER
10317 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
10320 return_used_this_function = 0;
10324 arm_output_epilogue (rtx sibling)
10327 unsigned long saved_regs_mask;
10328 unsigned long func_type;
10329 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10330 frame that is $fp + 4 for a non-variadic function. */
10331 int floats_offset = 0;
10333 FILE * f = asm_out_file;
10334 unsigned int lrm_count = 0;
10335 int really_return = (sibling == NULL);
10337 arm_stack_offsets *offsets;
10339 /* If we have already generated the return instruction
10340 then it is futile to generate anything else. */
10341 if (use_return_insn (FALSE, sibling) && return_used_this_function)
10344 func_type = arm_current_func_type ();
10346 if (IS_NAKED (func_type))
10347 /* Naked functions don't have epilogues. */
10350 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10354 /* A volatile function should never return. Call abort. */
10355 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
10356 assemble_external_libcall (op);
10357 output_asm_insn ("bl\t%a0", &op);
10362 /* If we are throwing an exception, then we really must be doing a
10363 return, so we can't tail-call. */
10364 gcc_assert (!current_function_calls_eh_return || really_return);
10366 offsets = arm_get_frame_offsets ();
10367 saved_regs_mask = arm_compute_save_reg_mask ();
10370 lrm_count = bit_count (saved_regs_mask);
10372 floats_offset = offsets->saved_args;
10373 /* Compute how far away the floats will be. */
10374 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10375 if (saved_regs_mask & (1 << reg))
10376 floats_offset += 4;
10378 if (frame_pointer_needed && TARGET_ARM)
10380 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10381 int vfp_offset = offsets->frame;
10383 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10385 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10386 if (regs_ever_live[reg] && !call_used_regs[reg])
10388 floats_offset += 12;
10389 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
10390 reg, FP_REGNUM, floats_offset - vfp_offset);
10395 start_reg = LAST_FPA_REGNUM;
10397 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10399 if (regs_ever_live[reg] && !call_used_regs[reg])
10401 floats_offset += 12;
10403 /* We can't unstack more than four registers at once. */
10404 if (start_reg - reg == 3)
10406 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
10407 reg, FP_REGNUM, floats_offset - vfp_offset);
10408 start_reg = reg - 1;
10413 if (reg != start_reg)
10414 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10415 reg + 1, start_reg - reg,
10416 FP_REGNUM, floats_offset - vfp_offset);
10417 start_reg = reg - 1;
10421 /* Just in case the last register checked also needs unstacking. */
10422 if (reg != start_reg)
10423 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10424 reg + 1, start_reg - reg,
10425 FP_REGNUM, floats_offset - vfp_offset);
10428 if (TARGET_HARD_FLOAT && TARGET_VFP)
10432 /* The fldmd insns do not have base+offset addressing
10433 modes, so we use IP to hold the address. */
10434 saved_size = arm_get_vfp_saved_size ();
10436 if (saved_size > 0)
10438 floats_offset += saved_size;
10439 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
10440 FP_REGNUM, floats_offset - vfp_offset);
10442 start_reg = FIRST_VFP_REGNUM;
10443 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10445 if ((!regs_ever_live[reg] || call_used_regs[reg])
10446 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10448 if (start_reg != reg)
10449 vfp_output_fldmd (f, IP_REGNUM,
10450 (start_reg - FIRST_VFP_REGNUM) / 2,
10451 (reg - start_reg) / 2);
10452 start_reg = reg + 2;
10455 if (start_reg != reg)
10456 vfp_output_fldmd (f, IP_REGNUM,
10457 (start_reg - FIRST_VFP_REGNUM) / 2,
10458 (reg - start_reg) / 2);
10463 /* The frame pointer is guaranteed to be non-double-word aligned.
10464 This is because it is set to (old_stack_pointer - 4) and the
10465 old_stack_pointer was double word aligned. Thus the offset to
10466 the iWMMXt registers to be loaded must also be non-double-word
10467 sized, so that the resultant address *is* double-word aligned.
10468 We can ignore floats_offset since that was already included in
10469 the live_regs_mask. */
10470 lrm_count += (lrm_count % 2 ? 2 : 1);
10472 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10473 if (regs_ever_live[reg] && !call_used_regs[reg])
10475 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
10476 reg, FP_REGNUM, lrm_count * 4);
10481 /* saved_regs_mask should contain the IP, which at the time of stack
10482 frame generation actually contains the old stack pointer. So a
10483 quick way to unwind the stack is just pop the IP register directly
10484 into the stack pointer. */
10485 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
10486 saved_regs_mask &= ~ (1 << IP_REGNUM);
10487 saved_regs_mask |= (1 << SP_REGNUM);
10489 /* There are two registers left in saved_regs_mask - LR and PC. We
10490 only need to restore the LR register (the return address), but to
10491 save time we can load it directly into the PC, unless we need a
10492 special function exit sequence, or we are not really returning. */
10494 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10495 && !current_function_calls_eh_return)
10496 /* Delete the LR from the register mask, so that the LR on
10497 the stack is loaded into the PC in the register mask. */
10498 saved_regs_mask &= ~ (1 << LR_REGNUM);
10500 saved_regs_mask &= ~ (1 << PC_REGNUM);
10502 /* We must use SP as the base register, because SP is one of the
10503 registers being restored. If an interrupt or page fault
10504 happens in the ldm instruction, the SP might or might not
10505 have been restored. That would be bad, as then SP will no
10506 longer indicate the safe area of stack, and we can get stack
10507 corruption. Using SP as the base register means that it will
10508 be reset correctly to the original value, should an interrupt
10509 occur. If the stack pointer already points at the right
10510 place, then omit the subtraction. */
10511 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10512 || current_function_calls_alloca)
10513 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10514 4 * bit_count (saved_regs_mask));
10515 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
10517 if (IS_INTERRUPT (func_type))
10518 /* Interrupt handlers will have pushed the
10519 IP onto the stack, so restore it now. */
10520 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
10524 HOST_WIDE_INT amount;
10526 /* Restore stack pointer if necessary. */
10527 if (frame_pointer_needed)
10529 /* For Thumb-2 restore sp from the frame pointer.
10530 Operand restrictions mean we have to increment FP, then copy
10532 amount = offsets->locals_base - offsets->saved_regs;
10533 operands[0] = hard_frame_pointer_rtx;
10537 operands[0] = stack_pointer_rtx;
10538 amount = offsets->outgoing_args - offsets->saved_regs;
10543 operands[1] = operands[0];
10544 operands[2] = GEN_INT (amount);
10545 output_add_immediate (operands);
10547 if (frame_pointer_needed)
10548 asm_fprintf (f, "\tmov\t%r, %r\n",
10549 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
10551 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10553 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10554 if (regs_ever_live[reg] && !call_used_regs[reg])
10555 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10560 start_reg = FIRST_FPA_REGNUM;
10562 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10564 if (regs_ever_live[reg] && !call_used_regs[reg])
10566 if (reg - start_reg == 3)
10568 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10569 start_reg, SP_REGNUM);
10570 start_reg = reg + 1;
10575 if (reg != start_reg)
10576 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10577 start_reg, reg - start_reg,
10580 start_reg = reg + 1;
10584 /* Just in case the last register checked also needs unstacking. */
10585 if (reg != start_reg)
10586 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10587 start_reg, reg - start_reg, SP_REGNUM);
10590 if (TARGET_HARD_FLOAT && TARGET_VFP)
10592 start_reg = FIRST_VFP_REGNUM;
10593 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10595 if ((!regs_ever_live[reg] || call_used_regs[reg])
10596 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10598 if (start_reg != reg)
10599 vfp_output_fldmd (f, SP_REGNUM,
10600 (start_reg - FIRST_VFP_REGNUM) / 2,
10601 (reg - start_reg) / 2);
10602 start_reg = reg + 2;
10605 if (start_reg != reg)
10606 vfp_output_fldmd (f, SP_REGNUM,
10607 (start_reg - FIRST_VFP_REGNUM) / 2,
10608 (reg - start_reg) / 2);
10611 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10612 if (regs_ever_live[reg] && !call_used_regs[reg])
10613 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10615 /* If we can, restore the LR into the PC. */
10616 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
10617 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
10618 && !IS_STACKALIGN (func_type)
10620 && current_function_pretend_args_size == 0
10621 && saved_regs_mask & (1 << LR_REGNUM)
10622 && !current_function_calls_eh_return)
10624 saved_regs_mask &= ~ (1 << LR_REGNUM);
10625 saved_regs_mask |= (1 << PC_REGNUM);
10626 rfe = IS_INTERRUPT (func_type);
10631 /* Load the registers off the stack. If we only have one register
10632 to load use the LDR instruction - it is faster. For Thumb-2
10633 always use pop and the assembler will pick the best instruction.*/
10634 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
10635 && !IS_INTERRUPT(func_type))
10637 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10639 else if (saved_regs_mask)
10641 if (saved_regs_mask & (1 << SP_REGNUM))
10642 /* Note - write back to the stack register is not enabled
10643 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10644 in the list of registers and if we add writeback the
10645 instruction becomes UNPREDICTABLE. */
10646 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
10648 else if (TARGET_ARM)
10649 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
10652 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
10655 if (current_function_pretend_args_size)
10657 /* Unwind the pre-pushed regs. */
10658 operands[0] = operands[1] = stack_pointer_rtx;
10659 operands[2] = GEN_INT (current_function_pretend_args_size);
10660 output_add_immediate (operands);
10664 /* We may have already restored PC directly from the stack. */
10665 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10668 /* Stack adjustment for exception handler. */
10669 if (current_function_calls_eh_return)
10670 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10671 ARM_EH_STACKADJ_REGNUM);
10673 /* Generate the return instruction. */
10674 switch ((int) ARM_FUNC_TYPE (func_type))
10678 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10681 case ARM_FT_EXCEPTION:
10682 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10685 case ARM_FT_INTERWORKED:
10686 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10690 if (IS_STACKALIGN (func_type))
10692 /* See comment in arm_expand_prologue. */
10693 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
10695 if (arm_arch5 || arm_arch4t)
10696 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10698 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10706 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10707 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10709 arm_stack_offsets *offsets;
10715 /* Emit any call-via-reg trampolines that are needed for v4t support
10716 of call_reg and call_value_reg type insns. */
10717 for (regno = 0; regno < LR_REGNUM; regno++)
10719 rtx label = cfun->machine->call_via[regno];
10723 switch_to_section (function_section (current_function_decl));
10724 targetm.asm_out.internal_label (asm_out_file, "L",
10725 CODE_LABEL_NUMBER (label));
10726 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10730 /* ??? Probably not safe to set this here, since it assumes that a
10731 function will be emitted as assembly immediately after we generate
10732 RTL for it. This does not happen for inline functions. */
10733 return_used_this_function = 0;
10735 else /* TARGET_32BIT */
10737 /* We need to take into account any stack-frame rounding. */
10738 offsets = arm_get_frame_offsets ();
10740 gcc_assert (!use_return_insn (FALSE, NULL)
10741 || !return_used_this_function
10742 || offsets->saved_regs == offsets->outgoing_args
10743 || frame_pointer_needed);
10745 /* Reset the ARM-specific per-function variables. */
10746 after_arm_reorg = 0;
10750 /* Generate and emit an insn that we will recognize as a push_multi.
10751 Unfortunately, since this insn does not reflect very well the actual
10752 semantics of the operation, we need to annotate the insn for the benefit
10753 of DWARF2 frame unwind information. */
10755 emit_multi_reg_push (unsigned long mask)
10758 int num_dwarf_regs;
10762 int dwarf_par_index;
10765 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10766 if (mask & (1 << i))
10769 gcc_assert (num_regs && num_regs <= 16);
10771 /* We don't record the PC in the dwarf frame information. */
10772 num_dwarf_regs = num_regs;
10773 if (mask & (1 << PC_REGNUM))
10776 /* For the body of the insn we are going to generate an UNSPEC in
10777 parallel with several USEs. This allows the insn to be recognized
10778 by the push_multi pattern in the arm.md file. The insn looks
10779 something like this:
10782 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10783 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10784 (use (reg:SI 11 fp))
10785 (use (reg:SI 12 ip))
10786 (use (reg:SI 14 lr))
10787 (use (reg:SI 15 pc))
10790 For the frame note however, we try to be more explicit and actually
10791 show each register being stored into the stack frame, plus a (single)
10792 decrement of the stack pointer. We do it this way in order to be
10793 friendly to the stack unwinding code, which only wants to see a single
10794 stack decrement per instruction. The RTL we generate for the note looks
10795 something like this:
10798 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10799 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10800 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10801 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10802 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10805 This sequence is used both by the code to support stack unwinding for
10806 exceptions handlers and the code to generate dwarf2 frame debugging. */
10808 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10809 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10810 dwarf_par_index = 1;
10812 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10814 if (mask & (1 << i))
10816 reg = gen_rtx_REG (SImode, i);
10818 XVECEXP (par, 0, 0)
10819 = gen_rtx_SET (VOIDmode,
10820 gen_frame_mem (BLKmode,
10821 gen_rtx_PRE_DEC (BLKmode,
10822 stack_pointer_rtx)),
10823 gen_rtx_UNSPEC (BLKmode,
10824 gen_rtvec (1, reg),
10825 UNSPEC_PUSH_MULT));
10827 if (i != PC_REGNUM)
10829 tmp = gen_rtx_SET (VOIDmode,
10830 gen_frame_mem (SImode, stack_pointer_rtx),
10832 RTX_FRAME_RELATED_P (tmp) = 1;
10833 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10841 for (j = 1, i++; j < num_regs; i++)
10843 if (mask & (1 << i))
10845 reg = gen_rtx_REG (SImode, i);
10847 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10849 if (i != PC_REGNUM)
10852 = gen_rtx_SET (VOIDmode,
10853 gen_frame_mem (SImode,
10854 plus_constant (stack_pointer_rtx,
10857 RTX_FRAME_RELATED_P (tmp) = 1;
10858 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10865 par = emit_insn (par);
10867 tmp = gen_rtx_SET (VOIDmode,
10869 plus_constant (stack_pointer_rtx, -4 * num_regs));
10870 RTX_FRAME_RELATED_P (tmp) = 1;
10871 XVECEXP (dwarf, 0, 0) = tmp;
10873 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10878 /* Calculate the size of the return value that is passed in registers. */
10880 arm_size_return_regs (void)
10882 enum machine_mode mode;
10884 if (current_function_return_rtx != 0)
10885 mode = GET_MODE (current_function_return_rtx);
10887 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10889 return GET_MODE_SIZE (mode);
10893 emit_sfm (int base_reg, int count)
10900 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10901 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10903 reg = gen_rtx_REG (XFmode, base_reg++);
10905 XVECEXP (par, 0, 0)
10906 = gen_rtx_SET (VOIDmode,
10907 gen_frame_mem (BLKmode,
10908 gen_rtx_PRE_DEC (BLKmode,
10909 stack_pointer_rtx)),
10910 gen_rtx_UNSPEC (BLKmode,
10911 gen_rtvec (1, reg),
10912 UNSPEC_PUSH_MULT));
10913 tmp = gen_rtx_SET (VOIDmode,
10914 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
10915 RTX_FRAME_RELATED_P (tmp) = 1;
10916 XVECEXP (dwarf, 0, 1) = tmp;
10918 for (i = 1; i < count; i++)
10920 reg = gen_rtx_REG (XFmode, base_reg++);
10921 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10923 tmp = gen_rtx_SET (VOIDmode,
10924 gen_frame_mem (XFmode,
10925 plus_constant (stack_pointer_rtx,
10928 RTX_FRAME_RELATED_P (tmp) = 1;
10929 XVECEXP (dwarf, 0, i + 1) = tmp;
10932 tmp = gen_rtx_SET (VOIDmode,
10934 plus_constant (stack_pointer_rtx, -12 * count));
10936 RTX_FRAME_RELATED_P (tmp) = 1;
10937 XVECEXP (dwarf, 0, 0) = tmp;
10939 par = emit_insn (par);
10940 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10946 /* Return true if the current function needs to save/restore LR. */
10949 thumb_force_lr_save (void)
10951 return !cfun->machine->lr_save_eliminated
10952 && (!leaf_function_p ()
10953 || thumb_far_jump_used_p ()
10954 || regs_ever_live [LR_REGNUM]);
10958 /* Compute the distance from register FROM to register TO.
10959 These can be the arg pointer (26), the soft frame pointer (25),
10960 the stack pointer (13) or the hard frame pointer (11).
10961 In thumb mode r7 is used as the soft frame pointer, if needed.
10962 Typical stack layout looks like this:
10964 old stack pointer -> | |
10967 | | saved arguments for
10968 | | vararg functions
10971 hard FP & arg pointer -> | | \
10979 soft frame pointer -> | | /
10984 locals base pointer -> | | /
10989 current stack pointer -> | | /
10992 For a given function some or all of these stack components
10993 may not be needed, giving rise to the possibility of
10994 eliminating some of the registers.
10996 The values returned by this function must reflect the behavior
10997 of arm_expand_prologue() and arm_compute_save_reg_mask().
10999 The sign of the number returned reflects the direction of stack
11000 growth, so the values are positive for all eliminations except
11001 from the soft frame pointer to the hard frame pointer.
11003 SFP may point just inside the local variables block to ensure correct
11007 /* Calculate stack offsets. These are used to calculate register elimination
11008 offsets and in prologue/epilogue code. */
11010 static arm_stack_offsets *
11011 arm_get_frame_offsets (void)
11013 struct arm_stack_offsets *offsets;
11014 unsigned long func_type;
11017 HOST_WIDE_INT frame_size;
11019 offsets = &cfun->machine->stack_offsets;
11021 /* We need to know if we are a leaf function. Unfortunately, it
11022 is possible to be called after start_sequence has been called,
11023 which causes get_insns to return the insns for the sequence,
11024 not the function, which will cause leaf_function_p to return
11025 the incorrect result.
11027 to know about leaf functions once reload has completed, and the
11028 frame size cannot be changed after that time, so we can safely
11029 use the cached value. */
11031 if (reload_completed)
11034 /* Initially this is the size of the local variables. It will translated
11035 into an offset once we have determined the size of preceding data. */
11036 frame_size = ROUND_UP_WORD (get_frame_size ());
11038 leaf = leaf_function_p ();
11040 /* Space for variadic functions. */
11041 offsets->saved_args = current_function_pretend_args_size;
11043 /* In Thumb mode this is incorrect, but never used. */
11044 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
11048 unsigned int regno;
11050 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
11052 /* We know that SP will be doubleword aligned on entry, and we must
11053 preserve that condition at any subroutine call. We also require the
11054 soft frame pointer to be doubleword aligned. */
11056 if (TARGET_REALLY_IWMMXT)
11058 /* Check for the call-saved iWMMXt registers. */
11059 for (regno = FIRST_IWMMXT_REGNUM;
11060 regno <= LAST_IWMMXT_REGNUM;
11062 if (regs_ever_live [regno] && ! call_used_regs [regno])
11066 func_type = arm_current_func_type ();
11067 if (! IS_VOLATILE (func_type))
11069 /* Space for saved FPA registers. */
11070 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
11071 if (regs_ever_live[regno] && ! call_used_regs[regno])
11074 /* Space for saved VFP registers. */
11075 if (TARGET_HARD_FLOAT && TARGET_VFP)
11076 saved += arm_get_vfp_saved_size ();
11079 else /* TARGET_THUMB1 */
11081 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
11082 if (TARGET_BACKTRACE)
11086 /* Saved registers include the stack frame. */
11087 offsets->saved_regs = offsets->saved_args + saved;
11088 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
11089 /* A leaf function does not need any stack alignment if it has nothing
11091 if (leaf && frame_size == 0)
11093 offsets->outgoing_args = offsets->soft_frame;
11097 /* Ensure SFP has the correct alignment. */
11098 if (ARM_DOUBLEWORD_ALIGN
11099 && (offsets->soft_frame & 7))
11100 offsets->soft_frame += 4;
11102 offsets->locals_base = offsets->soft_frame + frame_size;
11103 offsets->outgoing_args = (offsets->locals_base
11104 + current_function_outgoing_args_size);
11106 if (ARM_DOUBLEWORD_ALIGN)
11108 /* Ensure SP remains doubleword aligned. */
11109 if (offsets->outgoing_args & 7)
11110 offsets->outgoing_args += 4;
11111 gcc_assert (!(offsets->outgoing_args & 7));
11118 /* Calculate the relative offsets for the different stack pointers. Positive
11119 offsets are in the direction of stack growth. */
11122 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
11124 arm_stack_offsets *offsets;
11126 offsets = arm_get_frame_offsets ();
11128 /* OK, now we have enough information to compute the distances.
11129 There must be an entry in these switch tables for each pair
11130 of registers in ELIMINABLE_REGS, even if some of the entries
11131 seem to be redundant or useless. */
11134 case ARG_POINTER_REGNUM:
11137 case THUMB_HARD_FRAME_POINTER_REGNUM:
11140 case FRAME_POINTER_REGNUM:
11141 /* This is the reverse of the soft frame pointer
11142 to hard frame pointer elimination below. */
11143 return offsets->soft_frame - offsets->saved_args;
11145 case ARM_HARD_FRAME_POINTER_REGNUM:
11146 /* If there is no stack frame then the hard
11147 frame pointer and the arg pointer coincide. */
11148 if (offsets->frame == offsets->saved_regs)
11150 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11151 return (frame_pointer_needed
11152 && cfun->static_chain_decl != NULL
11153 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
11155 case STACK_POINTER_REGNUM:
11156 /* If nothing has been pushed on the stack at all
11157 then this will return -4. This *is* correct! */
11158 return offsets->outgoing_args - (offsets->saved_args + 4);
11161 gcc_unreachable ();
11163 gcc_unreachable ();
11165 case FRAME_POINTER_REGNUM:
11168 case THUMB_HARD_FRAME_POINTER_REGNUM:
11171 case ARM_HARD_FRAME_POINTER_REGNUM:
11172 /* The hard frame pointer points to the top entry in the
11173 stack frame. The soft frame pointer to the bottom entry
11174 in the stack frame. If there is no stack frame at all,
11175 then they are identical. */
11177 return offsets->frame - offsets->soft_frame;
11179 case STACK_POINTER_REGNUM:
11180 return offsets->outgoing_args - offsets->soft_frame;
11183 gcc_unreachable ();
11185 gcc_unreachable ();
11188 /* You cannot eliminate from the stack pointer.
11189 In theory you could eliminate from the hard frame
11190 pointer to the stack pointer, but this will never
11191 happen, since if a stack frame is not needed the
11192 hard frame pointer will never be used. */
11193 gcc_unreachable ();
11198 /* Emit RTL to save coprocessor registers on function entry. Returns the
11199 number of bytes pushed. */
11202 arm_save_coproc_regs(void)
11204 int saved_size = 0;
11206 unsigned start_reg;
11209 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
11210 if (regs_ever_live[reg] && ! call_used_regs [reg])
11212 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
11213 insn = gen_rtx_MEM (V2SImode, insn);
11214 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
11215 RTX_FRAME_RELATED_P (insn) = 1;
11219 /* Save any floating point call-saved registers used by this
11221 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
11223 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11224 if (regs_ever_live[reg] && !call_used_regs[reg])
11226 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
11227 insn = gen_rtx_MEM (XFmode, insn);
11228 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
11229 RTX_FRAME_RELATED_P (insn) = 1;
11235 start_reg = LAST_FPA_REGNUM;
11237 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11239 if (regs_ever_live[reg] && !call_used_regs[reg])
11241 if (start_reg - reg == 3)
11243 insn = emit_sfm (reg, 4);
11244 RTX_FRAME_RELATED_P (insn) = 1;
11246 start_reg = reg - 1;
11251 if (start_reg != reg)
11253 insn = emit_sfm (reg + 1, start_reg - reg);
11254 RTX_FRAME_RELATED_P (insn) = 1;
11255 saved_size += (start_reg - reg) * 12;
11257 start_reg = reg - 1;
11261 if (start_reg != reg)
11263 insn = emit_sfm (reg + 1, start_reg - reg);
11264 saved_size += (start_reg - reg) * 12;
11265 RTX_FRAME_RELATED_P (insn) = 1;
11268 if (TARGET_HARD_FLOAT && TARGET_VFP)
11270 start_reg = FIRST_VFP_REGNUM;
11272 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11274 if ((!regs_ever_live[reg] || call_used_regs[reg])
11275 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
11277 if (start_reg != reg)
11278 saved_size += vfp_emit_fstmd (start_reg,
11279 (reg - start_reg) / 2);
11280 start_reg = reg + 2;
11283 if (start_reg != reg)
11284 saved_size += vfp_emit_fstmd (start_reg,
11285 (reg - start_reg) / 2);
11291 /* Set the Thumb frame pointer from the stack pointer. */
11294 thumb_set_frame_pointer (arm_stack_offsets *offsets)
11296 HOST_WIDE_INT amount;
11299 amount = offsets->outgoing_args - offsets->locals_base;
11301 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11302 stack_pointer_rtx, GEN_INT (amount)));
11305 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
11306 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11307 hard_frame_pointer_rtx,
11308 stack_pointer_rtx));
11309 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11310 plus_constant (stack_pointer_rtx, amount));
11311 RTX_FRAME_RELATED_P (dwarf) = 1;
11312 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11316 RTX_FRAME_RELATED_P (insn) = 1;
11319 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11322 arm_expand_prologue (void)
11327 unsigned long live_regs_mask;
11328 unsigned long func_type;
11330 int saved_pretend_args = 0;
11331 int saved_regs = 0;
11332 unsigned HOST_WIDE_INT args_to_push;
11333 arm_stack_offsets *offsets;
11335 func_type = arm_current_func_type ();
11337 /* Naked functions don't have prologues. */
11338 if (IS_NAKED (func_type))
11341 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11342 args_to_push = current_function_pretend_args_size;
11344 /* Compute which register we will have to save onto the stack. */
11345 live_regs_mask = arm_compute_save_reg_mask ();
11347 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
11349 if (IS_STACKALIGN (func_type))
11354 /* Handle a word-aligned stack pointer. We generate the following:
11359 <save and restore r0 in normal prologue/epilogue>
11363 The unwinder doesn't need to know about the stack realignment.
11364 Just tell it we saved SP in r0. */
11365 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
11367 r0 = gen_rtx_REG (SImode, 0);
11368 r1 = gen_rtx_REG (SImode, 1);
11369 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
11370 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
11371 insn = gen_movsi (r0, stack_pointer_rtx);
11372 RTX_FRAME_RELATED_P (insn) = 1;
11373 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11374 dwarf, REG_NOTES (insn));
11376 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
11377 emit_insn (gen_movsi (stack_pointer_rtx, r1));
11380 if (frame_pointer_needed && TARGET_ARM)
11382 if (IS_INTERRUPT (func_type))
11384 /* Interrupt functions must not corrupt any registers.
11385 Creating a frame pointer however, corrupts the IP
11386 register, so we must push it first. */
11387 insn = emit_multi_reg_push (1 << IP_REGNUM);
11389 /* Do not set RTX_FRAME_RELATED_P on this insn.
11390 The dwarf stack unwinding code only wants to see one
11391 stack decrement per function, and this is not it. If
11392 this instruction is labeled as being part of the frame
11393 creation sequence then dwarf2out_frame_debug_expr will
11394 die when it encounters the assignment of IP to FP
11395 later on, since the use of SP here establishes SP as
11396 the CFA register and not IP.
11398 Anyway this instruction is not really part of the stack
11399 frame creation although it is part of the prologue. */
11401 else if (IS_NESTED (func_type))
11403 /* The Static chain register is the same as the IP register
11404 used as a scratch register during stack frame creation.
11405 To get around this need to find somewhere to store IP
11406 whilst the frame is being created. We try the following
11409 1. The last argument register.
11410 2. A slot on the stack above the frame. (This only
11411 works if the function is not a varargs function).
11412 3. Register r3, after pushing the argument registers
11415 Note - we only need to tell the dwarf2 backend about the SP
11416 adjustment in the second variant; the static chain register
11417 doesn't need to be unwound, as it doesn't contain a value
11418 inherited from the caller. */
11420 if (regs_ever_live[3] == 0)
11421 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11422 else if (args_to_push == 0)
11426 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
11427 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
11430 /* Just tell the dwarf backend that we adjusted SP. */
11431 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11432 plus_constant (stack_pointer_rtx,
11434 RTX_FRAME_RELATED_P (insn) = 1;
11435 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11436 dwarf, REG_NOTES (insn));
11440 /* Store the args on the stack. */
11441 if (cfun->machine->uses_anonymous_args)
11442 insn = emit_multi_reg_push
11443 ((0xf0 >> (args_to_push / 4)) & 0xf);
11446 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11447 GEN_INT (- args_to_push)));
11449 RTX_FRAME_RELATED_P (insn) = 1;
11451 saved_pretend_args = 1;
11452 fp_offset = args_to_push;
11455 /* Now reuse r3 to preserve IP. */
11456 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11460 insn = emit_set_insn (ip_rtx,
11461 plus_constant (stack_pointer_rtx, fp_offset));
11462 RTX_FRAME_RELATED_P (insn) = 1;
11467 /* Push the argument registers, or reserve space for them. */
11468 if (cfun->machine->uses_anonymous_args)
11469 insn = emit_multi_reg_push
11470 ((0xf0 >> (args_to_push / 4)) & 0xf);
11473 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11474 GEN_INT (- args_to_push)));
11475 RTX_FRAME_RELATED_P (insn) = 1;
11478 /* If this is an interrupt service routine, and the link register
11479 is going to be pushed, and we are not creating a stack frame,
11480 (which would involve an extra push of IP and a pop in the epilogue)
11481 subtracting four from LR now will mean that the function return
11482 can be done with a single instruction. */
11483 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
11484 && (live_regs_mask & (1 << LR_REGNUM)) != 0
11485 && ! frame_pointer_needed
11488 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
11490 emit_set_insn (lr, plus_constant (lr, -4));
11493 if (live_regs_mask)
11495 insn = emit_multi_reg_push (live_regs_mask);
11496 saved_regs += bit_count (live_regs_mask) * 4;
11497 RTX_FRAME_RELATED_P (insn) = 1;
11500 if (! IS_VOLATILE (func_type))
11501 saved_regs += arm_save_coproc_regs ();
11503 if (frame_pointer_needed && TARGET_ARM)
11505 /* Create the new frame pointer. */
11507 insn = GEN_INT (-(4 + args_to_push + fp_offset));
11508 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
11509 RTX_FRAME_RELATED_P (insn) = 1;
11511 if (IS_NESTED (func_type))
11513 /* Recover the static chain register. */
11514 if (regs_ever_live [3] == 0
11515 || saved_pretend_args)
11516 insn = gen_rtx_REG (SImode, 3);
11517 else /* if (current_function_pretend_args_size == 0) */
11519 insn = plus_constant (hard_frame_pointer_rtx, 4);
11520 insn = gen_frame_mem (SImode, insn);
11522 emit_set_insn (ip_rtx, insn);
11523 /* Add a USE to stop propagate_one_insn() from barfing. */
11524 emit_insn (gen_prologue_use (ip_rtx));
11529 offsets = arm_get_frame_offsets ();
11530 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
11532 /* This add can produce multiple insns for a large constant, so we
11533 need to get tricky. */
11534 rtx last = get_last_insn ();
11536 amount = GEN_INT (offsets->saved_args + saved_regs
11537 - offsets->outgoing_args);
11539 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11543 last = last ? NEXT_INSN (last) : get_insns ();
11544 RTX_FRAME_RELATED_P (last) = 1;
11546 while (last != insn);
11548 /* If the frame pointer is needed, emit a special barrier that
11549 will prevent the scheduler from moving stores to the frame
11550 before the stack adjustment. */
11551 if (frame_pointer_needed)
11552 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
11553 hard_frame_pointer_rtx));
11557 if (frame_pointer_needed && TARGET_THUMB2)
11558 thumb_set_frame_pointer (offsets);
11560 if (flag_pic && arm_pic_register != INVALID_REGNUM)
11562 unsigned long mask;
11564 mask = live_regs_mask;
11565 mask &= THUMB2_WORK_REGS;
11566 if (!IS_NESTED (func_type))
11567 mask |= (1 << IP_REGNUM);
11568 arm_load_pic_register (mask);
11571 /* If we are profiling, make sure no instructions are scheduled before
11572 the call to mcount. Similarly if the user has requested no
11573 scheduling in the prolog. Similarly if we want non-call exceptions
11574 using the EABI unwinder, to prevent faulting instructions from being
11575 swapped with a stack adjustment. */
11576 if (current_function_profile || !TARGET_SCHED_PROLOG
11577 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
11578 emit_insn (gen_blockage ());
11580 /* If the link register is being kept alive, with the return address in it,
11581 then make sure that it does not get reused by the ce2 pass. */
11582 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
11584 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
11585 cfun->machine->lr_save_eliminated = 1;
11589 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11591 arm_print_condition (FILE *stream)
11593 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11595 /* Branch conversion is not implemented for Thumb-2. */
11598 output_operand_lossage ("predicated Thumb instruction");
11601 if (current_insn_predicate != NULL)
11603 output_operand_lossage
11604 ("predicated instruction in conditional sequence");
11608 fputs (arm_condition_codes[arm_current_cc], stream);
11610 else if (current_insn_predicate)
11612 enum arm_cond_code code;
11616 output_operand_lossage ("predicated Thumb instruction");
11620 code = get_arm_condition_code (current_insn_predicate);
11621 fputs (arm_condition_codes[code], stream);
11626 /* If CODE is 'd', then the X is a condition operand and the instruction
11627 should only be executed if the condition is true.
11628 if CODE is 'D', then the X is a condition operand and the instruction
11629 should only be executed if the condition is false: however, if the mode
11630 of the comparison is CCFPEmode, then always execute the instruction -- we
11631 do this because in these circumstances !GE does not necessarily imply LT;
11632 in these cases the instruction pattern will take care to make sure that
11633 an instruction containing %d will follow, thereby undoing the effects of
11634 doing this instruction unconditionally.
11635 If CODE is 'N' then X is a floating point operand that must be negated
11637 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11638 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11640 arm_print_operand (FILE *stream, rtx x, int code)
11645 fputs (ASM_COMMENT_START, stream);
11649 fputs (user_label_prefix, stream);
11653 fputs (REGISTER_PREFIX, stream);
11657 arm_print_condition (stream);
11661 /* Nothing in unified syntax, otherwise the current condition code. */
11662 if (!TARGET_UNIFIED_ASM)
11663 arm_print_condition (stream);
11667 /* The current condition code in unified syntax, otherwise nothing. */
11668 if (TARGET_UNIFIED_ASM)
11669 arm_print_condition (stream);
11673 /* The current condition code for a condition code setting instruction.
11674 Preceded by 's' in unified syntax, otherwise followed by 's'. */
11675 if (TARGET_UNIFIED_ASM)
11677 fputc('s', stream);
11678 arm_print_condition (stream);
11682 arm_print_condition (stream);
11683 fputc('s', stream);
11688 /* If the instruction is conditionally executed then print
11689 the current condition code, otherwise print 's'. */
11690 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
11691 if (current_insn_predicate)
11692 arm_print_condition (stream);
11694 fputc('s', stream);
11700 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11701 r = REAL_VALUE_NEGATE (r);
11702 fprintf (stream, "%s", fp_const_from_val (&r));
11707 if (GET_CODE (x) == CONST_INT)
11710 val = ARM_SIGN_EXTEND (~INTVAL (x));
11711 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11715 putc ('~', stream);
11716 output_addr_const (stream, x);
11721 /* The low 16 bits of an immediate constant. */
11722 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
11726 fprintf (stream, "%s", arithmetic_instr (x, 1));
11729 /* Truncate Cirrus shift counts. */
11731 if (GET_CODE (x) == CONST_INT)
11733 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11736 arm_print_operand (stream, x, 0);
11740 fprintf (stream, "%s", arithmetic_instr (x, 0));
11748 if (!shift_operator (x, SImode))
11750 output_operand_lossage ("invalid shift operand");
11754 shift = shift_op (x, &val);
11758 fprintf (stream, ", %s ", shift);
11760 arm_print_operand (stream, XEXP (x, 1), 0);
11762 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11767 /* An explanation of the 'Q', 'R' and 'H' register operands:
11769 In a pair of registers containing a DI or DF value the 'Q'
11770 operand returns the register number of the register containing
11771 the least significant part of the value. The 'R' operand returns
11772 the register number of the register containing the most
11773 significant part of the value.
11775 The 'H' operand returns the higher of the two register numbers.
11776 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11777 same as the 'Q' operand, since the most significant part of the
11778 value is held in the lower number register. The reverse is true
11779 on systems where WORDS_BIG_ENDIAN is false.
11781 The purpose of these operands is to distinguish between cases
11782 where the endian-ness of the values is important (for example
11783 when they are added together), and cases where the endian-ness
11784 is irrelevant, but the order of register operations is important.
11785 For example when loading a value from memory into a register
11786 pair, the endian-ness does not matter. Provided that the value
11787 from the lower memory address is put into the lower numbered
11788 register, and the value from the higher address is put into the
11789 higher numbered register, the load will work regardless of whether
11790 the value being loaded is big-wordian or little-wordian. The
11791 order of the two register loads can matter however, if the address
11792 of the memory location is actually held in one of the registers
11793 being overwritten by the load. */
11795 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11797 output_operand_lossage ("invalid operand for code '%c'", code);
11801 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11805 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11807 output_operand_lossage ("invalid operand for code '%c'", code);
11811 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11815 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11817 output_operand_lossage ("invalid operand for code '%c'", code);
11821 asm_fprintf (stream, "%r", REGNO (x) + 1);
11825 asm_fprintf (stream, "%r",
11826 GET_CODE (XEXP (x, 0)) == REG
11827 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11831 asm_fprintf (stream, "{%r-%r}",
11833 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11837 /* CONST_TRUE_RTX means always -- that's the default. */
11838 if (x == const_true_rtx)
11841 if (!COMPARISON_P (x))
11843 output_operand_lossage ("invalid operand for code '%c'", code);
11847 fputs (arm_condition_codes[get_arm_condition_code (x)],
11852 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11853 want to do that. */
11854 if (x == const_true_rtx)
11856 output_operand_lossage ("instruction never executed");
11859 if (!COMPARISON_P (x))
11861 output_operand_lossage ("invalid operand for code '%c'", code);
11865 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11866 (get_arm_condition_code (x))],
11870 /* Cirrus registers can be accessed in a variety of ways:
11871 single floating point (f)
11872 double floating point (d)
11874 64bit integer (dx). */
11875 case 'W': /* Cirrus register in F mode. */
11876 case 'X': /* Cirrus register in D mode. */
11877 case 'Y': /* Cirrus register in FX mode. */
11878 case 'Z': /* Cirrus register in DX mode. */
11879 gcc_assert (GET_CODE (x) == REG
11880 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
11882 fprintf (stream, "mv%s%s",
11884 : code == 'X' ? "d"
11885 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11889 /* Print cirrus register in the mode specified by the register's mode. */
11892 int mode = GET_MODE (x);
11894 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11896 output_operand_lossage ("invalid operand for code '%c'", code);
11900 fprintf (stream, "mv%s%s",
11901 mode == DFmode ? "d"
11902 : mode == SImode ? "fx"
11903 : mode == DImode ? "dx"
11904 : "f", reg_names[REGNO (x)] + 2);
11910 if (GET_CODE (x) != REG
11911 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11912 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11913 /* Bad value for wCG register number. */
11915 output_operand_lossage ("invalid operand for code '%c'", code);
11920 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11923 /* Print an iWMMXt control register name. */
11925 if (GET_CODE (x) != CONST_INT
11927 || INTVAL (x) >= 16)
11928 /* Bad value for wC register number. */
11930 output_operand_lossage ("invalid operand for code '%c'", code);
11936 static const char * wc_reg_names [16] =
11938 "wCID", "wCon", "wCSSF", "wCASF",
11939 "wC4", "wC5", "wC6", "wC7",
11940 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11941 "wC12", "wC13", "wC14", "wC15"
11944 fprintf (stream, wc_reg_names [INTVAL (x)]);
11948 /* Print a VFP double precision register name. */
11951 int mode = GET_MODE (x);
11954 if (mode != DImode && mode != DFmode)
11956 output_operand_lossage ("invalid operand for code '%c'", code);
11960 if (GET_CODE (x) != REG
11961 || !IS_VFP_REGNUM (REGNO (x)))
11963 output_operand_lossage ("invalid operand for code '%c'", code);
11967 num = REGNO(x) - FIRST_VFP_REGNUM;
11970 output_operand_lossage ("invalid operand for code '%c'", code);
11974 fprintf (stream, "d%d", num >> 1);
11981 output_operand_lossage ("missing operand");
11985 switch (GET_CODE (x))
11988 asm_fprintf (stream, "%r", REGNO (x));
11992 output_memory_reference_mode = GET_MODE (x);
11993 output_address (XEXP (x, 0));
11997 fprintf (stream, "#%s", fp_immediate_constant (x));
12001 gcc_assert (GET_CODE (x) != NEG);
12002 fputc ('#', stream);
12003 output_addr_const (stream, x);
12009 #ifndef AOF_ASSEMBLER
12010 /* Target hook for assembling integer objects. The ARM version needs to
12011 handle word-sized values specially. */
12013 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
12015 if (size == UNITS_PER_WORD && aligned_p)
12017 fputs ("\t.word\t", asm_out_file);
12018 output_addr_const (asm_out_file, x);
12020 /* Mark symbols as position independent. We only do this in the
12021 .text segment, not in the .data segment. */
12022 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
12023 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
12025 /* See legitimize_pic_address for an explanation of the
12026 TARGET_VXWORKS_RTP check. */
12027 if (TARGET_VXWORKS_RTP
12028 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
12029 fputs ("(GOT)", asm_out_file);
12031 fputs ("(GOTOFF)", asm_out_file);
12033 fputc ('\n', asm_out_file);
12037 if (arm_vector_mode_supported_p (GET_MODE (x)))
12041 gcc_assert (GET_CODE (x) == CONST_VECTOR);
12043 units = CONST_VECTOR_NUNITS (x);
12045 switch (GET_MODE (x))
12047 case V2SImode: size = 4; break;
12048 case V4HImode: size = 2; break;
12049 case V8QImode: size = 1; break;
12051 gcc_unreachable ();
12054 for (i = 0; i < units; i++)
12058 elt = CONST_VECTOR_ELT (x, i);
12060 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
12066 return default_assemble_integer (x, size, aligned_p);
12070 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
12074 if (!TARGET_AAPCS_BASED)
12077 default_named_section_asm_out_constructor
12078 : default_named_section_asm_out_destructor) (symbol, priority);
12082 /* Put these in the .init_array section, using a special relocation. */
12083 if (priority != DEFAULT_INIT_PRIORITY)
12086 sprintf (buf, "%s.%.5u",
12087 is_ctor ? ".init_array" : ".fini_array",
12089 s = get_section (buf, SECTION_WRITE, NULL_TREE);
12096 switch_to_section (s);
12097 assemble_align (POINTER_SIZE);
12098 fputs ("\t.word\t", asm_out_file);
12099 output_addr_const (asm_out_file, symbol);
12100 fputs ("(target1)\n", asm_out_file);
12103 /* Add a function to the list of static constructors. */
12106 arm_elf_asm_constructor (rtx symbol, int priority)
12108 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
12111 /* Add a function to the list of static destructors. */
12114 arm_elf_asm_destructor (rtx symbol, int priority)
12116 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
12120 /* A finite state machine takes care of noticing whether or not instructions
12121 can be conditionally executed, and thus decrease execution time and code
12122 size by deleting branch instructions. The fsm is controlled by
12123 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12125 /* The state of the fsm controlling condition codes are:
12126 0: normal, do nothing special
12127 1: make ASM_OUTPUT_OPCODE not output this instruction
12128 2: make ASM_OUTPUT_OPCODE not output this instruction
12129 3: make instructions conditional
12130 4: make instructions conditional
12132 State transitions (state->state by whom under condition):
12133 0 -> 1 final_prescan_insn if the `target' is a label
12134 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12135 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12136 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12137 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12138 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12139 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12140 (the target insn is arm_target_insn).
12142 If the jump clobbers the conditions then we use states 2 and 4.
12144 A similar thing can be done with conditional return insns.
12146 XXX In case the `target' is an unconditional branch, this conditionalising
12147 of the instructions always reduces code size, but not always execution
12148 time. But then, I want to reduce the code size to somewhere near what
12149 /bin/cc produces. */
12151 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12152 instructions. When a COND_EXEC instruction is seen the subsequent
12153 instructions are scanned so that multiple conditional instructions can be
12154 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12155 specify the length and true/false mask for the IT block. These will be
12156 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12158 /* Returns the index of the ARM condition code string in
12159 `arm_condition_codes'. COMPARISON should be an rtx like
12160 `(eq (...) (...))'. */
12161 static enum arm_cond_code
12162 get_arm_condition_code (rtx comparison)
12164 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
12166 enum rtx_code comp_code = GET_CODE (comparison);
12168 if (GET_MODE_CLASS (mode) != MODE_CC)
12169 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
12170 XEXP (comparison, 1));
12174 case CC_DNEmode: code = ARM_NE; goto dominance;
12175 case CC_DEQmode: code = ARM_EQ; goto dominance;
12176 case CC_DGEmode: code = ARM_GE; goto dominance;
12177 case CC_DGTmode: code = ARM_GT; goto dominance;
12178 case CC_DLEmode: code = ARM_LE; goto dominance;
12179 case CC_DLTmode: code = ARM_LT; goto dominance;
12180 case CC_DGEUmode: code = ARM_CS; goto dominance;
12181 case CC_DGTUmode: code = ARM_HI; goto dominance;
12182 case CC_DLEUmode: code = ARM_LS; goto dominance;
12183 case CC_DLTUmode: code = ARM_CC;
12186 gcc_assert (comp_code == EQ || comp_code == NE);
12188 if (comp_code == EQ)
12189 return ARM_INVERSE_CONDITION_CODE (code);
12195 case NE: return ARM_NE;
12196 case EQ: return ARM_EQ;
12197 case GE: return ARM_PL;
12198 case LT: return ARM_MI;
12199 default: gcc_unreachable ();
12205 case NE: return ARM_NE;
12206 case EQ: return ARM_EQ;
12207 default: gcc_unreachable ();
12213 case NE: return ARM_MI;
12214 case EQ: return ARM_PL;
12215 default: gcc_unreachable ();
12220 /* These encodings assume that AC=1 in the FPA system control
12221 byte. This allows us to handle all cases except UNEQ and
12225 case GE: return ARM_GE;
12226 case GT: return ARM_GT;
12227 case LE: return ARM_LS;
12228 case LT: return ARM_MI;
12229 case NE: return ARM_NE;
12230 case EQ: return ARM_EQ;
12231 case ORDERED: return ARM_VC;
12232 case UNORDERED: return ARM_VS;
12233 case UNLT: return ARM_LT;
12234 case UNLE: return ARM_LE;
12235 case UNGT: return ARM_HI;
12236 case UNGE: return ARM_PL;
12237 /* UNEQ and LTGT do not have a representation. */
12238 case UNEQ: /* Fall through. */
12239 case LTGT: /* Fall through. */
12240 default: gcc_unreachable ();
12246 case NE: return ARM_NE;
12247 case EQ: return ARM_EQ;
12248 case GE: return ARM_LE;
12249 case GT: return ARM_LT;
12250 case LE: return ARM_GE;
12251 case LT: return ARM_GT;
12252 case GEU: return ARM_LS;
12253 case GTU: return ARM_CC;
12254 case LEU: return ARM_CS;
12255 case LTU: return ARM_HI;
12256 default: gcc_unreachable ();
12262 case LTU: return ARM_CS;
12263 case GEU: return ARM_CC;
12264 default: gcc_unreachable ();
12270 case NE: return ARM_NE;
12271 case EQ: return ARM_EQ;
12272 case GE: return ARM_GE;
12273 case GT: return ARM_GT;
12274 case LE: return ARM_LE;
12275 case LT: return ARM_LT;
12276 case GEU: return ARM_CS;
12277 case GTU: return ARM_HI;
12278 case LEU: return ARM_LS;
12279 case LTU: return ARM_CC;
12280 default: gcc_unreachable ();
12283 default: gcc_unreachable ();
12287 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
12290 thumb2_final_prescan_insn (rtx insn)
12292 rtx first_insn = insn;
12293 rtx body = PATTERN (insn);
12295 enum arm_cond_code code;
12299 /* Remove the previous insn from the count of insns to be output. */
12300 if (arm_condexec_count)
12301 arm_condexec_count--;
12303 /* Nothing to do if we are already inside a conditional block. */
12304 if (arm_condexec_count)
12307 if (GET_CODE (body) != COND_EXEC)
12310 /* Conditional jumps are implemented directly. */
12311 if (GET_CODE (insn) == JUMP_INSN)
12314 predicate = COND_EXEC_TEST (body);
12315 arm_current_cc = get_arm_condition_code (predicate);
12317 n = get_attr_ce_count (insn);
12318 arm_condexec_count = 1;
12319 arm_condexec_mask = (1 << n) - 1;
12320 arm_condexec_masklen = n;
12321 /* See if subsequent instructions can be combined into the same block. */
12324 insn = next_nonnote_insn (insn);
12326 /* Jumping into the middle of an IT block is illegal, so a label or
12327 barrier terminates the block. */
12328 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
12331 body = PATTERN (insn);
12332 /* USE and CLOBBER aren't really insns, so just skip them. */
12333 if (GET_CODE (body) == USE
12334 || GET_CODE (body) == CLOBBER)
12337 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
12338 if (GET_CODE (body) != COND_EXEC)
12340 /* Allow up to 4 conditionally executed instructions in a block. */
12341 n = get_attr_ce_count (insn);
12342 if (arm_condexec_masklen + n > 4)
12345 predicate = COND_EXEC_TEST (body);
12346 code = get_arm_condition_code (predicate);
12347 mask = (1 << n) - 1;
12348 if (arm_current_cc == code)
12349 arm_condexec_mask |= (mask << arm_condexec_masklen);
12350 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
12353 arm_condexec_count++;
12354 arm_condexec_masklen += n;
12356 /* A jump must be the last instruction in a conditional block. */
12357 if (GET_CODE(insn) == JUMP_INSN)
12360 /* Restore recog_data (getting the attributes of other insns can
12361 destroy this array, but final.c assumes that it remains intact
12362 across this call). */
12363 extract_constrain_insn_cached (first_insn);
12367 arm_final_prescan_insn (rtx insn)
12369 /* BODY will hold the body of INSN. */
12370 rtx body = PATTERN (insn);
12372 /* This will be 1 if trying to repeat the trick, and things need to be
12373 reversed if it appears to fail. */
12376 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12377 taken are clobbered, even if the rtl suggests otherwise. It also
12378 means that we have to grub around within the jump expression to find
12379 out what the conditions are when the jump isn't taken. */
12380 int jump_clobbers = 0;
12382 /* If we start with a return insn, we only succeed if we find another one. */
12383 int seeking_return = 0;
12385 /* START_INSN will hold the insn from where we start looking. This is the
12386 first insn after the following code_label if REVERSE is true. */
12387 rtx start_insn = insn;
12389 /* If in state 4, check if the target branch is reached, in order to
12390 change back to state 0. */
12391 if (arm_ccfsm_state == 4)
12393 if (insn == arm_target_insn)
12395 arm_target_insn = NULL;
12396 arm_ccfsm_state = 0;
12401 /* If in state 3, it is possible to repeat the trick, if this insn is an
12402 unconditional branch to a label, and immediately following this branch
12403 is the previous target label which is only used once, and the label this
12404 branch jumps to is not too far off. */
12405 if (arm_ccfsm_state == 3)
12407 if (simplejump_p (insn))
12409 start_insn = next_nonnote_insn (start_insn);
12410 if (GET_CODE (start_insn) == BARRIER)
12412 /* XXX Isn't this always a barrier? */
12413 start_insn = next_nonnote_insn (start_insn);
12415 if (GET_CODE (start_insn) == CODE_LABEL
12416 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12417 && LABEL_NUSES (start_insn) == 1)
12422 else if (GET_CODE (body) == RETURN)
12424 start_insn = next_nonnote_insn (start_insn);
12425 if (GET_CODE (start_insn) == BARRIER)
12426 start_insn = next_nonnote_insn (start_insn);
12427 if (GET_CODE (start_insn) == CODE_LABEL
12428 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12429 && LABEL_NUSES (start_insn) == 1)
12432 seeking_return = 1;
12441 gcc_assert (!arm_ccfsm_state || reverse);
12442 if (GET_CODE (insn) != JUMP_INSN)
12445 /* This jump might be paralleled with a clobber of the condition codes
12446 the jump should always come first */
12447 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
12448 body = XVECEXP (body, 0, 0);
12451 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
12452 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
12455 int fail = FALSE, succeed = FALSE;
12456 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12457 int then_not_else = TRUE;
12458 rtx this_insn = start_insn, label = 0;
12460 /* If the jump cannot be done with one instruction, we cannot
12461 conditionally execute the instruction in the inverse case. */
12462 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
12468 /* Register the insn jumped to. */
12471 if (!seeking_return)
12472 label = XEXP (SET_SRC (body), 0);
12474 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
12475 label = XEXP (XEXP (SET_SRC (body), 1), 0);
12476 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
12478 label = XEXP (XEXP (SET_SRC (body), 2), 0);
12479 then_not_else = FALSE;
12481 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
12482 seeking_return = 1;
12483 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
12485 seeking_return = 1;
12486 then_not_else = FALSE;
12489 gcc_unreachable ();
12491 /* See how many insns this branch skips, and what kind of insns. If all
12492 insns are okay, and the label or unconditional branch to the same
12493 label is not too far away, succeed. */
12494 for (insns_skipped = 0;
12495 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
12499 this_insn = next_nonnote_insn (this_insn);
12503 switch (GET_CODE (this_insn))
12506 /* Succeed if it is the target label, otherwise fail since
12507 control falls in from somewhere else. */
12508 if (this_insn == label)
12512 arm_ccfsm_state = 2;
12513 this_insn = next_nonnote_insn (this_insn);
12516 arm_ccfsm_state = 1;
12524 /* Succeed if the following insn is the target label.
12526 If return insns are used then the last insn in a function
12527 will be a barrier. */
12528 this_insn = next_nonnote_insn (this_insn);
12529 if (this_insn && this_insn == label)
12533 arm_ccfsm_state = 2;
12534 this_insn = next_nonnote_insn (this_insn);
12537 arm_ccfsm_state = 1;
12545 /* The AAPCS says that conditional calls should not be
12546 used since they make interworking inefficient (the
12547 linker can't transform BL<cond> into BLX). That's
12548 only a problem if the machine has BLX. */
12555 /* Succeed if the following insn is the target label, or
12556 if the following two insns are a barrier and the
12558 this_insn = next_nonnote_insn (this_insn);
12559 if (this_insn && GET_CODE (this_insn) == BARRIER)
12560 this_insn = next_nonnote_insn (this_insn);
12562 if (this_insn && this_insn == label
12563 && insns_skipped < max_insns_skipped)
12567 arm_ccfsm_state = 2;
12568 this_insn = next_nonnote_insn (this_insn);
12571 arm_ccfsm_state = 1;
12579 /* If this is an unconditional branch to the same label, succeed.
12580 If it is to another label, do nothing. If it is conditional,
12582 /* XXX Probably, the tests for SET and the PC are
12585 scanbody = PATTERN (this_insn);
12586 if (GET_CODE (scanbody) == SET
12587 && GET_CODE (SET_DEST (scanbody)) == PC)
12589 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
12590 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
12592 arm_ccfsm_state = 2;
12595 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
12598 /* Fail if a conditional return is undesirable (e.g. on a
12599 StrongARM), but still allow this if optimizing for size. */
12600 else if (GET_CODE (scanbody) == RETURN
12601 && !use_return_insn (TRUE, NULL)
12604 else if (GET_CODE (scanbody) == RETURN
12607 arm_ccfsm_state = 2;
12610 else if (GET_CODE (scanbody) == PARALLEL)
12612 switch (get_attr_conds (this_insn))
12622 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
12627 /* Instructions using or affecting the condition codes make it
12629 scanbody = PATTERN (this_insn);
12630 if (!(GET_CODE (scanbody) == SET
12631 || GET_CODE (scanbody) == PARALLEL)
12632 || get_attr_conds (this_insn) != CONDS_NOCOND)
12635 /* A conditional cirrus instruction must be followed by
12636 a non Cirrus instruction. However, since we
12637 conditionalize instructions in this function and by
12638 the time we get here we can't add instructions
12639 (nops), because shorten_branches() has already been
12640 called, we will disable conditionalizing Cirrus
12641 instructions to be safe. */
12642 if (GET_CODE (scanbody) != USE
12643 && GET_CODE (scanbody) != CLOBBER
12644 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
12654 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
12655 arm_target_label = CODE_LABEL_NUMBER (label);
12658 gcc_assert (seeking_return || arm_ccfsm_state == 2);
12660 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
12662 this_insn = next_nonnote_insn (this_insn);
12663 gcc_assert (!this_insn
12664 || (GET_CODE (this_insn) != BARRIER
12665 && GET_CODE (this_insn) != CODE_LABEL));
12669 /* Oh, dear! we ran off the end.. give up. */
12670 extract_constrain_insn_cached (insn);
12671 arm_ccfsm_state = 0;
12672 arm_target_insn = NULL;
12675 arm_target_insn = this_insn;
12679 gcc_assert (!reverse);
12681 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
12683 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
12684 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12685 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
12686 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12690 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12693 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
12697 if (reverse || then_not_else)
12698 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12701 /* Restore recog_data (getting the attributes of other insns can
12702 destroy this array, but final.c assumes that it remains intact
12703 across this call. */
12704 extract_constrain_insn_cached (insn);
12708 /* Output IT instructions. */
12710 thumb2_asm_output_opcode (FILE * stream)
12715 if (arm_condexec_mask)
12717 for (n = 0; n < arm_condexec_masklen; n++)
12718 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
12720 asm_fprintf(stream, "i%s\t%s\n\t", buff,
12721 arm_condition_codes[arm_current_cc]);
12722 arm_condexec_mask = 0;
12726 /* Returns true if REGNO is a valid register
12727 for holding a quantity of type MODE. */
12729 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
12731 if (GET_MODE_CLASS (mode) == MODE_CC)
12732 return (regno == CC_REGNUM
12733 || (TARGET_HARD_FLOAT && TARGET_VFP
12734 && regno == VFPCC_REGNUM));
12737 /* For the Thumb we only allow values bigger than SImode in
12738 registers 0 - 6, so that there is always a second low
12739 register available to hold the upper part of the value.
12740 We probably we ought to ensure that the register is the
12741 start of an even numbered register pair. */
12742 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
12744 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
12745 && IS_CIRRUS_REGNUM (regno))
12746 /* We have outlawed SI values in Cirrus registers because they
12747 reside in the lower 32 bits, but SF values reside in the
12748 upper 32 bits. This causes gcc all sorts of grief. We can't
12749 even split the registers into pairs because Cirrus SI values
12750 get sign extended to 64bits-- aldyh. */
12751 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
12753 if (TARGET_HARD_FLOAT && TARGET_VFP
12754 && IS_VFP_REGNUM (regno))
12756 if (mode == SFmode || mode == SImode)
12759 /* DFmode values are only valid in even register pairs. */
12760 if (mode == DFmode)
12761 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
12765 if (TARGET_REALLY_IWMMXT)
12767 if (IS_IWMMXT_GR_REGNUM (regno))
12768 return mode == SImode;
12770 if (IS_IWMMXT_REGNUM (regno))
12771 return VALID_IWMMXT_REG_MODE (mode);
12774 /* We allow any value to be stored in the general registers.
12775 Restrict doubleword quantities to even register pairs so that we can
12777 if (regno <= LAST_ARM_REGNUM)
12778 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
12780 if (regno == FRAME_POINTER_REGNUM
12781 || regno == ARG_POINTER_REGNUM)
12782 /* We only allow integers in the fake hard registers. */
12783 return GET_MODE_CLASS (mode) == MODE_INT;
12785 /* The only registers left are the FPA registers
12786 which we only allow to hold FP values. */
12787 return (TARGET_HARD_FLOAT && TARGET_FPA
12788 && GET_MODE_CLASS (mode) == MODE_FLOAT
12789 && regno >= FIRST_FPA_REGNUM
12790 && regno <= LAST_FPA_REGNUM);
12793 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
12794 not used in arm mode. */
12796 arm_regno_class (int regno)
12800 if (regno == STACK_POINTER_REGNUM)
12802 if (regno == CC_REGNUM)
12809 if (TARGET_THUMB2 && regno < 8)
12812 if ( regno <= LAST_ARM_REGNUM
12813 || regno == FRAME_POINTER_REGNUM
12814 || regno == ARG_POINTER_REGNUM)
12815 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
12817 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
12818 return TARGET_THUMB2 ? CC_REG : NO_REGS;
12820 if (IS_CIRRUS_REGNUM (regno))
12821 return CIRRUS_REGS;
12823 if (IS_VFP_REGNUM (regno))
12826 if (IS_IWMMXT_REGNUM (regno))
12827 return IWMMXT_REGS;
12829 if (IS_IWMMXT_GR_REGNUM (regno))
12830 return IWMMXT_GR_REGS;
12835 /* Handle a special case when computing the offset
12836 of an argument from the frame pointer. */
12838 arm_debugger_arg_offset (int value, rtx addr)
12842 /* We are only interested if dbxout_parms() failed to compute the offset. */
12846 /* We can only cope with the case where the address is held in a register. */
12847 if (GET_CODE (addr) != REG)
12850 /* If we are using the frame pointer to point at the argument, then
12851 an offset of 0 is correct. */
12852 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
12855 /* If we are using the stack pointer to point at the
12856 argument, then an offset of 0 is correct. */
12857 /* ??? Check this is consistent with thumb2 frame layout. */
12858 if ((TARGET_THUMB || !frame_pointer_needed)
12859 && REGNO (addr) == SP_REGNUM)
12862 /* Oh dear. The argument is pointed to by a register rather
12863 than being held in a register, or being stored at a known
12864 offset from the frame pointer. Since GDB only understands
12865 those two kinds of argument we must translate the address
12866 held in the register into an offset from the frame pointer.
12867 We do this by searching through the insns for the function
12868 looking to see where this register gets its value. If the
12869 register is initialized from the frame pointer plus an offset
12870 then we are in luck and we can continue, otherwise we give up.
12872 This code is exercised by producing debugging information
12873 for a function with arguments like this:
12875 double func (double a, double b, int c, double d) {return d;}
12877 Without this code the stab for parameter 'd' will be set to
12878 an offset of 0 from the frame pointer, rather than 8. */
12880 /* The if() statement says:
12882 If the insn is a normal instruction
12883 and if the insn is setting the value in a register
12884 and if the register being set is the register holding the address of the argument
12885 and if the address is computing by an addition
12886 that involves adding to a register
12887 which is the frame pointer
12892 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12894 if ( GET_CODE (insn) == INSN
12895 && GET_CODE (PATTERN (insn)) == SET
12896 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
12897 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
12898 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
12899 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12900 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
12903 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
12912 warning (0, "unable to compute real location of stacked parameter");
12913 value = 8; /* XXX magic hack */
12919 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12922 if ((MASK) & insn_flags) \
12923 add_builtin_function ((NAME), (TYPE), (CODE), \
12924 BUILT_IN_MD, NULL, NULL_TREE); \
12928 struct builtin_description
12930 const unsigned int mask;
12931 const enum insn_code icode;
12932 const char * const name;
12933 const enum arm_builtins code;
12934 const enum rtx_code comparison;
12935 const unsigned int flag;
12938 static const struct builtin_description bdesc_2arg[] =
12940 #define IWMMXT_BUILTIN(code, string, builtin) \
12941 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12942 ARM_BUILTIN_##builtin, 0, 0 },
12944 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
12945 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
12946 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
12947 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
12948 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
12949 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
12950 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
12951 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
12952 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
12953 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
12954 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
12955 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
12956 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
12957 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12958 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12959 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12960 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12961 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12962 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12963 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12964 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12965 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12966 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12967 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12968 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12969 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12970 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12971 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12972 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12973 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12974 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12975 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12976 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12977 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12978 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12979 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12980 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12981 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12982 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12983 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12984 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12985 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12986 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12987 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12988 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12989 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12990 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12991 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12992 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12993 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12994 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12995 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12996 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12997 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12998 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12999 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
13000 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
13001 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
13003 #define IWMMXT_BUILTIN2(code, builtin) \
13004 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
13006 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
13007 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
13008 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
13009 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
13010 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
13011 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
13012 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
13013 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
13014 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
13015 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
13016 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
13017 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
13018 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
13019 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
13020 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
13021 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
13022 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
13023 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
13024 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
13025 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
13026 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
13027 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
13028 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
13029 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
13030 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
13031 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
13032 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
13033 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
13034 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
13035 IWMMXT_BUILTIN2 (rordi3, WRORDI)
13036 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
13037 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
13040 static const struct builtin_description bdesc_1arg[] =
13042 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
13043 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
13044 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
13045 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
13046 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
13047 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
13048 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
13049 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
13050 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
13051 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
13052 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
13053 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
13054 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
13055 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
13056 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
13057 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
13058 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
13059 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
13062 /* Set up all the iWMMXt builtins. This is
13063 not called if TARGET_IWMMXT is zero. */
13066 arm_init_iwmmxt_builtins (void)
13068 const struct builtin_description * d;
13070 tree endlink = void_list_node;
13072 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
13073 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
13074 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
13077 = build_function_type (integer_type_node,
13078 tree_cons (NULL_TREE, integer_type_node, endlink));
13079 tree v8qi_ftype_v8qi_v8qi_int
13080 = build_function_type (V8QI_type_node,
13081 tree_cons (NULL_TREE, V8QI_type_node,
13082 tree_cons (NULL_TREE, V8QI_type_node,
13083 tree_cons (NULL_TREE,
13086 tree v4hi_ftype_v4hi_int
13087 = build_function_type (V4HI_type_node,
13088 tree_cons (NULL_TREE, V4HI_type_node,
13089 tree_cons (NULL_TREE, integer_type_node,
13091 tree v2si_ftype_v2si_int
13092 = build_function_type (V2SI_type_node,
13093 tree_cons (NULL_TREE, V2SI_type_node,
13094 tree_cons (NULL_TREE, integer_type_node,
13096 tree v2si_ftype_di_di
13097 = build_function_type (V2SI_type_node,
13098 tree_cons (NULL_TREE, long_long_integer_type_node,
13099 tree_cons (NULL_TREE, long_long_integer_type_node,
13101 tree di_ftype_di_int
13102 = build_function_type (long_long_integer_type_node,
13103 tree_cons (NULL_TREE, long_long_integer_type_node,
13104 tree_cons (NULL_TREE, integer_type_node,
13106 tree di_ftype_di_int_int
13107 = build_function_type (long_long_integer_type_node,
13108 tree_cons (NULL_TREE, long_long_integer_type_node,
13109 tree_cons (NULL_TREE, integer_type_node,
13110 tree_cons (NULL_TREE,
13113 tree int_ftype_v8qi
13114 = build_function_type (integer_type_node,
13115 tree_cons (NULL_TREE, V8QI_type_node,
13117 tree int_ftype_v4hi
13118 = build_function_type (integer_type_node,
13119 tree_cons (NULL_TREE, V4HI_type_node,
13121 tree int_ftype_v2si
13122 = build_function_type (integer_type_node,
13123 tree_cons (NULL_TREE, V2SI_type_node,
13125 tree int_ftype_v8qi_int
13126 = build_function_type (integer_type_node,
13127 tree_cons (NULL_TREE, V8QI_type_node,
13128 tree_cons (NULL_TREE, integer_type_node,
13130 tree int_ftype_v4hi_int
13131 = build_function_type (integer_type_node,
13132 tree_cons (NULL_TREE, V4HI_type_node,
13133 tree_cons (NULL_TREE, integer_type_node,
13135 tree int_ftype_v2si_int
13136 = build_function_type (integer_type_node,
13137 tree_cons (NULL_TREE, V2SI_type_node,
13138 tree_cons (NULL_TREE, integer_type_node,
13140 tree v8qi_ftype_v8qi_int_int
13141 = build_function_type (V8QI_type_node,
13142 tree_cons (NULL_TREE, V8QI_type_node,
13143 tree_cons (NULL_TREE, integer_type_node,
13144 tree_cons (NULL_TREE,
13147 tree v4hi_ftype_v4hi_int_int
13148 = build_function_type (V4HI_type_node,
13149 tree_cons (NULL_TREE, V4HI_type_node,
13150 tree_cons (NULL_TREE, integer_type_node,
13151 tree_cons (NULL_TREE,
13154 tree v2si_ftype_v2si_int_int
13155 = build_function_type (V2SI_type_node,
13156 tree_cons (NULL_TREE, V2SI_type_node,
13157 tree_cons (NULL_TREE, integer_type_node,
13158 tree_cons (NULL_TREE,
13161 /* Miscellaneous. */
13162 tree v8qi_ftype_v4hi_v4hi
13163 = build_function_type (V8QI_type_node,
13164 tree_cons (NULL_TREE, V4HI_type_node,
13165 tree_cons (NULL_TREE, V4HI_type_node,
13167 tree v4hi_ftype_v2si_v2si
13168 = build_function_type (V4HI_type_node,
13169 tree_cons (NULL_TREE, V2SI_type_node,
13170 tree_cons (NULL_TREE, V2SI_type_node,
13172 tree v2si_ftype_v4hi_v4hi
13173 = build_function_type (V2SI_type_node,
13174 tree_cons (NULL_TREE, V4HI_type_node,
13175 tree_cons (NULL_TREE, V4HI_type_node,
13177 tree v2si_ftype_v8qi_v8qi
13178 = build_function_type (V2SI_type_node,
13179 tree_cons (NULL_TREE, V8QI_type_node,
13180 tree_cons (NULL_TREE, V8QI_type_node,
13182 tree v4hi_ftype_v4hi_di
13183 = build_function_type (V4HI_type_node,
13184 tree_cons (NULL_TREE, V4HI_type_node,
13185 tree_cons (NULL_TREE,
13186 long_long_integer_type_node,
13188 tree v2si_ftype_v2si_di
13189 = build_function_type (V2SI_type_node,
13190 tree_cons (NULL_TREE, V2SI_type_node,
13191 tree_cons (NULL_TREE,
13192 long_long_integer_type_node,
13194 tree void_ftype_int_int
13195 = build_function_type (void_type_node,
13196 tree_cons (NULL_TREE, integer_type_node,
13197 tree_cons (NULL_TREE, integer_type_node,
13200 = build_function_type (long_long_unsigned_type_node, endlink);
13202 = build_function_type (long_long_integer_type_node,
13203 tree_cons (NULL_TREE, V8QI_type_node,
13206 = build_function_type (long_long_integer_type_node,
13207 tree_cons (NULL_TREE, V4HI_type_node,
13210 = build_function_type (long_long_integer_type_node,
13211 tree_cons (NULL_TREE, V2SI_type_node,
13213 tree v2si_ftype_v4hi
13214 = build_function_type (V2SI_type_node,
13215 tree_cons (NULL_TREE, V4HI_type_node,
13217 tree v4hi_ftype_v8qi
13218 = build_function_type (V4HI_type_node,
13219 tree_cons (NULL_TREE, V8QI_type_node,
13222 tree di_ftype_di_v4hi_v4hi
13223 = build_function_type (long_long_unsigned_type_node,
13224 tree_cons (NULL_TREE,
13225 long_long_unsigned_type_node,
13226 tree_cons (NULL_TREE, V4HI_type_node,
13227 tree_cons (NULL_TREE,
13231 tree di_ftype_v4hi_v4hi
13232 = build_function_type (long_long_unsigned_type_node,
13233 tree_cons (NULL_TREE, V4HI_type_node,
13234 tree_cons (NULL_TREE, V4HI_type_node,
13237 /* Normal vector binops. */
13238 tree v8qi_ftype_v8qi_v8qi
13239 = build_function_type (V8QI_type_node,
13240 tree_cons (NULL_TREE, V8QI_type_node,
13241 tree_cons (NULL_TREE, V8QI_type_node,
13243 tree v4hi_ftype_v4hi_v4hi
13244 = build_function_type (V4HI_type_node,
13245 tree_cons (NULL_TREE, V4HI_type_node,
13246 tree_cons (NULL_TREE, V4HI_type_node,
13248 tree v2si_ftype_v2si_v2si
13249 = build_function_type (V2SI_type_node,
13250 tree_cons (NULL_TREE, V2SI_type_node,
13251 tree_cons (NULL_TREE, V2SI_type_node,
13253 tree di_ftype_di_di
13254 = build_function_type (long_long_unsigned_type_node,
13255 tree_cons (NULL_TREE, long_long_unsigned_type_node,
13256 tree_cons (NULL_TREE,
13257 long_long_unsigned_type_node,
13260 /* Add all builtins that are more or less simple operations on two
13262 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13264 /* Use one of the operands; the target can have a different mode for
13265 mask-generating compares. */
13266 enum machine_mode mode;
13272 mode = insn_data[d->icode].operand[1].mode;
13277 type = v8qi_ftype_v8qi_v8qi;
13280 type = v4hi_ftype_v4hi_v4hi;
13283 type = v2si_ftype_v2si_v2si;
13286 type = di_ftype_di_di;
13290 gcc_unreachable ();
13293 def_mbuiltin (d->mask, d->name, type, d->code);
13296 /* Add the remaining MMX insns with somewhat more complicated types. */
13297 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
13298 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
13299 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
13301 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
13302 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
13303 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
13304 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
13305 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
13306 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
13308 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
13309 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
13310 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
13311 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
13312 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
13313 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
13315 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
13316 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
13317 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
13318 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
13319 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
13320 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
13322 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
13323 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
13324 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
13325 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
13326 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
13327 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
13329 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
13331 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
13332 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
13333 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
13334 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
13336 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
13337 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
13338 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
13339 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
13340 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
13341 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
13342 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
13343 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
13344 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
13346 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
13347 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
13348 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
13350 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
13351 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
13352 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
13354 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
13355 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
13356 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
13357 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
13358 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
13359 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
13361 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
13362 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
13363 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
13364 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
13365 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
13366 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
13367 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
13368 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
13369 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
13370 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
13371 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
13372 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
13374 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
13375 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
13376 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
13377 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
13379 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
13380 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
13381 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
13382 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
13383 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
13384 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
13385 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
13389 arm_init_tls_builtins (void)
13392 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
13393 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
13395 ftype = build_function_type (ptr_type_node, void_list_node);
13396 add_builtin_function ("__builtin_thread_pointer", ftype,
13397 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
13398 NULL, const_nothrow);
13402 arm_init_builtins (void)
13404 arm_init_tls_builtins ();
13406 if (TARGET_REALLY_IWMMXT)
13407 arm_init_iwmmxt_builtins ();
13410 /* Errors in the source file can cause expand_expr to return const0_rtx
13411 where we expect a vector. To avoid crashing, use one of the vector
13412 clear instructions. */
13415 safe_vector_operand (rtx x, enum machine_mode mode)
13417 if (x != const0_rtx)
13419 x = gen_reg_rtx (mode);
13421 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
13422 : gen_rtx_SUBREG (DImode, x, 0)));
13426 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13429 arm_expand_binop_builtin (enum insn_code icode,
13430 tree exp, rtx target)
13433 tree arg0 = CALL_EXPR_ARG (exp, 0);
13434 tree arg1 = CALL_EXPR_ARG (exp, 1);
13435 rtx op0 = expand_normal (arg0);
13436 rtx op1 = expand_normal (arg1);
13437 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13438 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13439 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
13441 if (VECTOR_MODE_P (mode0))
13442 op0 = safe_vector_operand (op0, mode0);
13443 if (VECTOR_MODE_P (mode1))
13444 op1 = safe_vector_operand (op1, mode1);
13447 || GET_MODE (target) != tmode
13448 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13449 target = gen_reg_rtx (tmode);
13451 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
13453 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13454 op0 = copy_to_mode_reg (mode0, op0);
13455 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13456 op1 = copy_to_mode_reg (mode1, op1);
13458 pat = GEN_FCN (icode) (target, op0, op1);
13465 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13468 arm_expand_unop_builtin (enum insn_code icode,
13469 tree exp, rtx target, int do_load)
13472 tree arg0 = CALL_EXPR_ARG (exp, 0);
13473 rtx op0 = expand_normal (arg0);
13474 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13475 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13478 || GET_MODE (target) != tmode
13479 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13480 target = gen_reg_rtx (tmode);
13482 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
13485 if (VECTOR_MODE_P (mode0))
13486 op0 = safe_vector_operand (op0, mode0);
13488 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13489 op0 = copy_to_mode_reg (mode0, op0);
13492 pat = GEN_FCN (icode) (target, op0);
13499 /* Expand an expression EXP that calls a built-in function,
13500 with result going to TARGET if that's convenient
13501 (and in mode MODE if that's convenient).
13502 SUBTARGET may be used as the target for computing one of EXP's operands.
13503 IGNORE is nonzero if the value is to be ignored. */
13506 arm_expand_builtin (tree exp,
13508 rtx subtarget ATTRIBUTE_UNUSED,
13509 enum machine_mode mode ATTRIBUTE_UNUSED,
13510 int ignore ATTRIBUTE_UNUSED)
13512 const struct builtin_description * d;
13513 enum insn_code icode;
13514 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13522 int fcode = DECL_FUNCTION_CODE (fndecl);
13524 enum machine_mode tmode;
13525 enum machine_mode mode0;
13526 enum machine_mode mode1;
13527 enum machine_mode mode2;
13531 case ARM_BUILTIN_TEXTRMSB:
13532 case ARM_BUILTIN_TEXTRMUB:
13533 case ARM_BUILTIN_TEXTRMSH:
13534 case ARM_BUILTIN_TEXTRMUH:
13535 case ARM_BUILTIN_TEXTRMSW:
13536 case ARM_BUILTIN_TEXTRMUW:
13537 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
13538 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
13539 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
13540 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
13541 : CODE_FOR_iwmmxt_textrmw);
13543 arg0 = CALL_EXPR_ARG (exp, 0);
13544 arg1 = CALL_EXPR_ARG (exp, 1);
13545 op0 = expand_normal (arg0);
13546 op1 = expand_normal (arg1);
13547 tmode = insn_data[icode].operand[0].mode;
13548 mode0 = insn_data[icode].operand[1].mode;
13549 mode1 = insn_data[icode].operand[2].mode;
13551 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13552 op0 = copy_to_mode_reg (mode0, op0);
13553 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13555 /* @@@ better error message */
13556 error ("selector must be an immediate");
13557 return gen_reg_rtx (tmode);
13560 || GET_MODE (target) != tmode
13561 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13562 target = gen_reg_rtx (tmode);
13563 pat = GEN_FCN (icode) (target, op0, op1);
13569 case ARM_BUILTIN_TINSRB:
13570 case ARM_BUILTIN_TINSRH:
13571 case ARM_BUILTIN_TINSRW:
13572 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
13573 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
13574 : CODE_FOR_iwmmxt_tinsrw);
13575 arg0 = CALL_EXPR_ARG (exp, 0);
13576 arg1 = CALL_EXPR_ARG (exp, 1);
13577 arg2 = CALL_EXPR_ARG (exp, 2);
13578 op0 = expand_normal (arg0);
13579 op1 = expand_normal (arg1);
13580 op2 = expand_normal (arg2);
13581 tmode = insn_data[icode].operand[0].mode;
13582 mode0 = insn_data[icode].operand[1].mode;
13583 mode1 = insn_data[icode].operand[2].mode;
13584 mode2 = insn_data[icode].operand[3].mode;
13586 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13587 op0 = copy_to_mode_reg (mode0, op0);
13588 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13589 op1 = copy_to_mode_reg (mode1, op1);
13590 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13592 /* @@@ better error message */
13593 error ("selector must be an immediate");
13597 || GET_MODE (target) != tmode
13598 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13599 target = gen_reg_rtx (tmode);
13600 pat = GEN_FCN (icode) (target, op0, op1, op2);
13606 case ARM_BUILTIN_SETWCX:
13607 arg0 = CALL_EXPR_ARG (exp, 0);
13608 arg1 = CALL_EXPR_ARG (exp, 1);
13609 op0 = force_reg (SImode, expand_normal (arg0));
13610 op1 = expand_normal (arg1);
13611 emit_insn (gen_iwmmxt_tmcr (op1, op0));
13614 case ARM_BUILTIN_GETWCX:
13615 arg0 = CALL_EXPR_ARG (exp, 0);
13616 op0 = expand_normal (arg0);
13617 target = gen_reg_rtx (SImode);
13618 emit_insn (gen_iwmmxt_tmrc (target, op0));
13621 case ARM_BUILTIN_WSHUFH:
13622 icode = CODE_FOR_iwmmxt_wshufh;
13623 arg0 = CALL_EXPR_ARG (exp, 0);
13624 arg1 = CALL_EXPR_ARG (exp, 1);
13625 op0 = expand_normal (arg0);
13626 op1 = expand_normal (arg1);
13627 tmode = insn_data[icode].operand[0].mode;
13628 mode1 = insn_data[icode].operand[1].mode;
13629 mode2 = insn_data[icode].operand[2].mode;
13631 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
13632 op0 = copy_to_mode_reg (mode1, op0);
13633 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
13635 /* @@@ better error message */
13636 error ("mask must be an immediate");
13640 || GET_MODE (target) != tmode
13641 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13642 target = gen_reg_rtx (tmode);
13643 pat = GEN_FCN (icode) (target, op0, op1);
13649 case ARM_BUILTIN_WSADB:
13650 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
13651 case ARM_BUILTIN_WSADH:
13652 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
13653 case ARM_BUILTIN_WSADBZ:
13654 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
13655 case ARM_BUILTIN_WSADHZ:
13656 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
13658 /* Several three-argument builtins. */
13659 case ARM_BUILTIN_WMACS:
13660 case ARM_BUILTIN_WMACU:
13661 case ARM_BUILTIN_WALIGN:
13662 case ARM_BUILTIN_TMIA:
13663 case ARM_BUILTIN_TMIAPH:
13664 case ARM_BUILTIN_TMIATT:
13665 case ARM_BUILTIN_TMIATB:
13666 case ARM_BUILTIN_TMIABT:
13667 case ARM_BUILTIN_TMIABB:
13668 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
13669 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
13670 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
13671 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
13672 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
13673 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
13674 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
13675 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
13676 : CODE_FOR_iwmmxt_walign);
13677 arg0 = CALL_EXPR_ARG (exp, 0);
13678 arg1 = CALL_EXPR_ARG (exp, 1);
13679 arg2 = CALL_EXPR_ARG (exp, 2);
13680 op0 = expand_normal (arg0);
13681 op1 = expand_normal (arg1);
13682 op2 = expand_normal (arg2);
13683 tmode = insn_data[icode].operand[0].mode;
13684 mode0 = insn_data[icode].operand[1].mode;
13685 mode1 = insn_data[icode].operand[2].mode;
13686 mode2 = insn_data[icode].operand[3].mode;
13688 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13689 op0 = copy_to_mode_reg (mode0, op0);
13690 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13691 op1 = copy_to_mode_reg (mode1, op1);
13692 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13693 op2 = copy_to_mode_reg (mode2, op2);
13695 || GET_MODE (target) != tmode
13696 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13697 target = gen_reg_rtx (tmode);
13698 pat = GEN_FCN (icode) (target, op0, op1, op2);
13704 case ARM_BUILTIN_WZERO:
13705 target = gen_reg_rtx (DImode);
13706 emit_insn (gen_iwmmxt_clrdi (target));
13709 case ARM_BUILTIN_THREAD_POINTER:
13710 return arm_load_tp (target);
13716 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13717 if (d->code == (const enum arm_builtins) fcode)
13718 return arm_expand_binop_builtin (d->icode, exp, target);
13720 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13721 if (d->code == (const enum arm_builtins) fcode)
13722 return arm_expand_unop_builtin (d->icode, exp, target, 0);
13724 /* @@@ Should really do something sensible here. */
13728 /* Return the number (counting from 0) of
13729 the least significant set bit in MASK. */
13732 number_of_first_bit_set (unsigned mask)
13737 (mask & (1 << bit)) == 0;
13744 /* Emit code to push or pop registers to or from the stack. F is the
13745 assembly file. MASK is the registers to push or pop. PUSH is
13746 nonzero if we should push, and zero if we should pop. For debugging
13747 output, if pushing, adjust CFA_OFFSET by the amount of space added
13748 to the stack. REAL_REGS should have the same number of bits set as
13749 MASK, and will be used instead (in the same order) to describe which
13750 registers were saved - this is used to mark the save slots when we
13751 push high registers after moving them to low registers. */
13753 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
13754 unsigned long real_regs)
13757 int lo_mask = mask & 0xFF;
13758 int pushed_words = 0;
13762 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
13764 /* Special case. Do not generate a POP PC statement here, do it in
13766 thumb_exit (f, -1);
13770 if (ARM_EABI_UNWIND_TABLES && push)
13772 fprintf (f, "\t.save\t{");
13773 for (regno = 0; regno < 15; regno++)
13775 if (real_regs & (1 << regno))
13777 if (real_regs & ((1 << regno) -1))
13779 asm_fprintf (f, "%r", regno);
13782 fprintf (f, "}\n");
13785 fprintf (f, "\t%s\t{", push ? "push" : "pop");
13787 /* Look at the low registers first. */
13788 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
13792 asm_fprintf (f, "%r", regno);
13794 if ((lo_mask & ~1) != 0)
13801 if (push && (mask & (1 << LR_REGNUM)))
13803 /* Catch pushing the LR. */
13807 asm_fprintf (f, "%r", LR_REGNUM);
13811 else if (!push && (mask & (1 << PC_REGNUM)))
13813 /* Catch popping the PC. */
13814 if (TARGET_INTERWORK || TARGET_BACKTRACE
13815 || current_function_calls_eh_return)
13817 /* The PC is never poped directly, instead
13818 it is popped into r3 and then BX is used. */
13819 fprintf (f, "}\n");
13821 thumb_exit (f, -1);
13830 asm_fprintf (f, "%r", PC_REGNUM);
13834 fprintf (f, "}\n");
13836 if (push && pushed_words && dwarf2out_do_frame ())
13838 char *l = dwarf2out_cfi_label ();
13839 int pushed_mask = real_regs;
13841 *cfa_offset += pushed_words * 4;
13842 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13845 pushed_mask = real_regs;
13846 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13848 if (pushed_mask & 1)
13849 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13854 /* Generate code to return from a thumb function.
13855 If 'reg_containing_return_addr' is -1, then the return address is
13856 actually on the stack, at the stack pointer. */
13858 thumb_exit (FILE *f, int reg_containing_return_addr)
13860 unsigned regs_available_for_popping;
13861 unsigned regs_to_pop;
13863 unsigned available;
13867 int restore_a4 = FALSE;
13869 /* Compute the registers we need to pop. */
13873 if (reg_containing_return_addr == -1)
13875 regs_to_pop |= 1 << LR_REGNUM;
13879 if (TARGET_BACKTRACE)
13881 /* Restore the (ARM) frame pointer and stack pointer. */
13882 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
13886 /* If there is nothing to pop then just emit the BX instruction and
13888 if (pops_needed == 0)
13890 if (current_function_calls_eh_return)
13891 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13893 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13896 /* Otherwise if we are not supporting interworking and we have not created
13897 a backtrace structure and the function was not entered in ARM mode then
13898 just pop the return address straight into the PC. */
13899 else if (!TARGET_INTERWORK
13900 && !TARGET_BACKTRACE
13901 && !is_called_in_ARM_mode (current_function_decl)
13902 && !current_function_calls_eh_return)
13904 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
13908 /* Find out how many of the (return) argument registers we can corrupt. */
13909 regs_available_for_popping = 0;
13911 /* If returning via __builtin_eh_return, the bottom three registers
13912 all contain information needed for the return. */
13913 if (current_function_calls_eh_return)
13917 /* If we can deduce the registers used from the function's
13918 return value. This is more reliable that examining
13919 regs_ever_live[] because that will be set if the register is
13920 ever used in the function, not just if the register is used
13921 to hold a return value. */
13923 if (current_function_return_rtx != 0)
13924 mode = GET_MODE (current_function_return_rtx);
13926 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13928 size = GET_MODE_SIZE (mode);
13932 /* In a void function we can use any argument register.
13933 In a function that returns a structure on the stack
13934 we can use the second and third argument registers. */
13935 if (mode == VOIDmode)
13936 regs_available_for_popping =
13937 (1 << ARG_REGISTER (1))
13938 | (1 << ARG_REGISTER (2))
13939 | (1 << ARG_REGISTER (3));
13941 regs_available_for_popping =
13942 (1 << ARG_REGISTER (2))
13943 | (1 << ARG_REGISTER (3));
13945 else if (size <= 4)
13946 regs_available_for_popping =
13947 (1 << ARG_REGISTER (2))
13948 | (1 << ARG_REGISTER (3));
13949 else if (size <= 8)
13950 regs_available_for_popping =
13951 (1 << ARG_REGISTER (3));
13954 /* Match registers to be popped with registers into which we pop them. */
13955 for (available = regs_available_for_popping,
13956 required = regs_to_pop;
13957 required != 0 && available != 0;
13958 available &= ~(available & - available),
13959 required &= ~(required & - required))
13962 /* If we have any popping registers left over, remove them. */
13964 regs_available_for_popping &= ~available;
13966 /* Otherwise if we need another popping register we can use
13967 the fourth argument register. */
13968 else if (pops_needed)
13970 /* If we have not found any free argument registers and
13971 reg a4 contains the return address, we must move it. */
13972 if (regs_available_for_popping == 0
13973 && reg_containing_return_addr == LAST_ARG_REGNUM)
13975 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13976 reg_containing_return_addr = LR_REGNUM;
13978 else if (size > 12)
13980 /* Register a4 is being used to hold part of the return value,
13981 but we have dire need of a free, low register. */
13984 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
13987 if (reg_containing_return_addr != LAST_ARG_REGNUM)
13989 /* The fourth argument register is available. */
13990 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
13996 /* Pop as many registers as we can. */
13997 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13998 regs_available_for_popping);
14000 /* Process the registers we popped. */
14001 if (reg_containing_return_addr == -1)
14003 /* The return address was popped into the lowest numbered register. */
14004 regs_to_pop &= ~(1 << LR_REGNUM);
14006 reg_containing_return_addr =
14007 number_of_first_bit_set (regs_available_for_popping);
14009 /* Remove this register for the mask of available registers, so that
14010 the return address will not be corrupted by further pops. */
14011 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
14014 /* If we popped other registers then handle them here. */
14015 if (regs_available_for_popping)
14019 /* Work out which register currently contains the frame pointer. */
14020 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
14022 /* Move it into the correct place. */
14023 asm_fprintf (f, "\tmov\t%r, %r\n",
14024 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
14026 /* (Temporarily) remove it from the mask of popped registers. */
14027 regs_available_for_popping &= ~(1 << frame_pointer);
14028 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
14030 if (regs_available_for_popping)
14034 /* We popped the stack pointer as well,
14035 find the register that contains it. */
14036 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
14038 /* Move it into the stack register. */
14039 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
14041 /* At this point we have popped all necessary registers, so
14042 do not worry about restoring regs_available_for_popping
14043 to its correct value:
14045 assert (pops_needed == 0)
14046 assert (regs_available_for_popping == (1 << frame_pointer))
14047 assert (regs_to_pop == (1 << STACK_POINTER)) */
14051 /* Since we have just move the popped value into the frame
14052 pointer, the popping register is available for reuse, and
14053 we know that we still have the stack pointer left to pop. */
14054 regs_available_for_popping |= (1 << frame_pointer);
14058 /* If we still have registers left on the stack, but we no longer have
14059 any registers into which we can pop them, then we must move the return
14060 address into the link register and make available the register that
14062 if (regs_available_for_popping == 0 && pops_needed > 0)
14064 regs_available_for_popping |= 1 << reg_containing_return_addr;
14066 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
14067 reg_containing_return_addr);
14069 reg_containing_return_addr = LR_REGNUM;
14072 /* If we have registers left on the stack then pop some more.
14073 We know that at most we will want to pop FP and SP. */
14074 if (pops_needed > 0)
14079 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14080 regs_available_for_popping);
14082 /* We have popped either FP or SP.
14083 Move whichever one it is into the correct register. */
14084 popped_into = number_of_first_bit_set (regs_available_for_popping);
14085 move_to = number_of_first_bit_set (regs_to_pop);
14087 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
14089 regs_to_pop &= ~(1 << move_to);
14094 /* If we still have not popped everything then we must have only
14095 had one register available to us and we are now popping the SP. */
14096 if (pops_needed > 0)
14100 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14101 regs_available_for_popping);
14103 popped_into = number_of_first_bit_set (regs_available_for_popping);
14105 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
14107 assert (regs_to_pop == (1 << STACK_POINTER))
14108 assert (pops_needed == 1)
14112 /* If necessary restore the a4 register. */
14115 if (reg_containing_return_addr != LR_REGNUM)
14117 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14118 reg_containing_return_addr = LR_REGNUM;
14121 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
14124 if (current_function_calls_eh_return)
14125 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14127 /* Return to caller. */
14128 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14133 thumb1_final_prescan_insn (rtx insn)
14135 if (flag_print_asm_name)
14136 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
14137 INSN_ADDRESSES (INSN_UID (insn)));
14141 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
14143 unsigned HOST_WIDE_INT mask = 0xff;
14146 if (val == 0) /* XXX */
14149 for (i = 0; i < 25; i++)
14150 if ((val & (mask << i)) == val)
14156 /* Returns nonzero if the current function contains,
14157 or might contain a far jump. */
14159 thumb_far_jump_used_p (void)
14163 /* This test is only important for leaf functions. */
14164 /* assert (!leaf_function_p ()); */
14166 /* If we have already decided that far jumps may be used,
14167 do not bother checking again, and always return true even if
14168 it turns out that they are not being used. Once we have made
14169 the decision that far jumps are present (and that hence the link
14170 register will be pushed onto the stack) we cannot go back on it. */
14171 if (cfun->machine->far_jump_used)
14174 /* If this function is not being called from the prologue/epilogue
14175 generation code then it must be being called from the
14176 INITIAL_ELIMINATION_OFFSET macro. */
14177 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
14179 /* In this case we know that we are being asked about the elimination
14180 of the arg pointer register. If that register is not being used,
14181 then there are no arguments on the stack, and we do not have to
14182 worry that a far jump might force the prologue to push the link
14183 register, changing the stack offsets. In this case we can just
14184 return false, since the presence of far jumps in the function will
14185 not affect stack offsets.
14187 If the arg pointer is live (or if it was live, but has now been
14188 eliminated and so set to dead) then we do have to test to see if
14189 the function might contain a far jump. This test can lead to some
14190 false negatives, since before reload is completed, then length of
14191 branch instructions is not known, so gcc defaults to returning their
14192 longest length, which in turn sets the far jump attribute to true.
14194 A false negative will not result in bad code being generated, but it
14195 will result in a needless push and pop of the link register. We
14196 hope that this does not occur too often.
14198 If we need doubleword stack alignment this could affect the other
14199 elimination offsets so we can't risk getting it wrong. */
14200 if (regs_ever_live [ARG_POINTER_REGNUM])
14201 cfun->machine->arg_pointer_live = 1;
14202 else if (!cfun->machine->arg_pointer_live)
14206 /* Check to see if the function contains a branch
14207 insn with the far jump attribute set. */
14208 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14210 if (GET_CODE (insn) == JUMP_INSN
14211 /* Ignore tablejump patterns. */
14212 && GET_CODE (PATTERN (insn)) != ADDR_VEC
14213 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
14214 && get_attr_far_jump (insn) == FAR_JUMP_YES
14217 /* Record the fact that we have decided that
14218 the function does use far jumps. */
14219 cfun->machine->far_jump_used = 1;
14227 /* Return nonzero if FUNC must be entered in ARM mode. */
14229 is_called_in_ARM_mode (tree func)
14231 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
14233 /* Ignore the problem about functions whose address is taken. */
14234 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
14238 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
14244 /* The bits which aren't usefully expanded as rtl. */
14246 thumb_unexpanded_epilogue (void)
14249 unsigned long live_regs_mask = 0;
14250 int high_regs_pushed = 0;
14251 int had_to_push_lr;
14254 if (return_used_this_function)
14257 if (IS_NAKED (arm_current_func_type ()))
14260 live_regs_mask = thumb1_compute_save_reg_mask ();
14261 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14263 /* If we can deduce the registers used from the function's return value.
14264 This is more reliable that examining regs_ever_live[] because that
14265 will be set if the register is ever used in the function, not just if
14266 the register is used to hold a return value. */
14267 size = arm_size_return_regs ();
14269 /* The prolog may have pushed some high registers to use as
14270 work registers. e.g. the testsuite file:
14271 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14272 compiles to produce:
14273 push {r4, r5, r6, r7, lr}
14277 as part of the prolog. We have to undo that pushing here. */
14279 if (high_regs_pushed)
14281 unsigned long mask = live_regs_mask & 0xff;
14284 /* The available low registers depend on the size of the value we are
14292 /* Oh dear! We have no low registers into which we can pop
14295 ("no low registers available for popping high registers");
14297 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
14298 if (live_regs_mask & (1 << next_hi_reg))
14301 while (high_regs_pushed)
14303 /* Find lo register(s) into which the high register(s) can
14305 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14307 if (mask & (1 << regno))
14308 high_regs_pushed--;
14309 if (high_regs_pushed == 0)
14313 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
14315 /* Pop the values into the low register(s). */
14316 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
14318 /* Move the value(s) into the high registers. */
14319 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14321 if (mask & (1 << regno))
14323 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
14326 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
14327 if (live_regs_mask & (1 << next_hi_reg))
14332 live_regs_mask &= ~0x0f00;
14335 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
14336 live_regs_mask &= 0xff;
14338 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
14340 /* Pop the return address into the PC. */
14341 if (had_to_push_lr)
14342 live_regs_mask |= 1 << PC_REGNUM;
14344 /* Either no argument registers were pushed or a backtrace
14345 structure was created which includes an adjusted stack
14346 pointer, so just pop everything. */
14347 if (live_regs_mask)
14348 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14351 /* We have either just popped the return address into the
14352 PC or it is was kept in LR for the entire function. */
14353 if (!had_to_push_lr)
14354 thumb_exit (asm_out_file, LR_REGNUM);
14358 /* Pop everything but the return address. */
14359 if (live_regs_mask)
14360 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14363 if (had_to_push_lr)
14367 /* We have no free low regs, so save one. */
14368 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
14372 /* Get the return address into a temporary register. */
14373 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
14374 1 << LAST_ARG_REGNUM);
14378 /* Move the return address to lr. */
14379 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
14381 /* Restore the low register. */
14382 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
14387 regno = LAST_ARG_REGNUM;
14392 /* Remove the argument registers that were pushed onto the stack. */
14393 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
14394 SP_REGNUM, SP_REGNUM,
14395 current_function_pretend_args_size);
14397 thumb_exit (asm_out_file, regno);
14403 /* Functions to save and restore machine-specific function data. */
14404 static struct machine_function *
14405 arm_init_machine_status (void)
14407 struct machine_function *machine;
14408 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
14410 #if ARM_FT_UNKNOWN != 0
14411 machine->func_type = ARM_FT_UNKNOWN;
14416 /* Return an RTX indicating where the return address to the
14417 calling function can be found. */
14419 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
14424 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
14427 /* Do anything needed before RTL is emitted for each function. */
14429 arm_init_expanders (void)
14431 /* Arrange to initialize and mark the machine per-function status. */
14432 init_machine_status = arm_init_machine_status;
14434 /* This is to stop the combine pass optimizing away the alignment
14435 adjustment of va_arg. */
14436 /* ??? It is claimed that this should not be necessary. */
14438 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
14442 /* Like arm_compute_initial_elimination offset. Simpler because there
14443 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14444 to point at the base of the local variables after static stack
14445 space for a function has been allocated. */
14448 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
14450 arm_stack_offsets *offsets;
14452 offsets = arm_get_frame_offsets ();
14456 case ARG_POINTER_REGNUM:
14459 case STACK_POINTER_REGNUM:
14460 return offsets->outgoing_args - offsets->saved_args;
14462 case FRAME_POINTER_REGNUM:
14463 return offsets->soft_frame - offsets->saved_args;
14465 case ARM_HARD_FRAME_POINTER_REGNUM:
14466 return offsets->saved_regs - offsets->saved_args;
14468 case THUMB_HARD_FRAME_POINTER_REGNUM:
14469 return offsets->locals_base - offsets->saved_args;
14472 gcc_unreachable ();
14476 case FRAME_POINTER_REGNUM:
14479 case STACK_POINTER_REGNUM:
14480 return offsets->outgoing_args - offsets->soft_frame;
14482 case ARM_HARD_FRAME_POINTER_REGNUM:
14483 return offsets->saved_regs - offsets->soft_frame;
14485 case THUMB_HARD_FRAME_POINTER_REGNUM:
14486 return offsets->locals_base - offsets->soft_frame;
14489 gcc_unreachable ();
14494 gcc_unreachable ();
14498 /* Generate the rest of a function's prologue. */
14500 thumb1_expand_prologue (void)
14504 HOST_WIDE_INT amount;
14505 arm_stack_offsets *offsets;
14506 unsigned long func_type;
14508 unsigned long live_regs_mask;
14510 func_type = arm_current_func_type ();
14512 /* Naked functions don't have prologues. */
14513 if (IS_NAKED (func_type))
14516 if (IS_INTERRUPT (func_type))
14518 error ("interrupt Service Routines cannot be coded in Thumb mode");
14522 live_regs_mask = thumb1_compute_save_reg_mask ();
14523 /* Load the pic register before setting the frame pointer,
14524 so we can use r7 as a temporary work register. */
14525 if (flag_pic && arm_pic_register != INVALID_REGNUM)
14526 arm_load_pic_register (live_regs_mask);
14528 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
14529 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
14530 stack_pointer_rtx);
14532 offsets = arm_get_frame_offsets ();
14533 amount = offsets->outgoing_args - offsets->saved_regs;
14538 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14539 GEN_INT (- amount)));
14540 RTX_FRAME_RELATED_P (insn) = 1;
14546 /* The stack decrement is too big for an immediate value in a single
14547 insn. In theory we could issue multiple subtracts, but after
14548 three of them it becomes more space efficient to place the full
14549 value in the constant pool and load into a register. (Also the
14550 ARM debugger really likes to see only one stack decrement per
14551 function). So instead we look for a scratch register into which
14552 we can load the decrement, and then we subtract this from the
14553 stack pointer. Unfortunately on the thumb the only available
14554 scratch registers are the argument registers, and we cannot use
14555 these as they may hold arguments to the function. Instead we
14556 attempt to locate a call preserved register which is used by this
14557 function. If we can find one, then we know that it will have
14558 been pushed at the start of the prologue and so we can corrupt
14560 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
14561 if (live_regs_mask & (1 << regno)
14562 && !(frame_pointer_needed
14563 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
14566 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
14568 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
14570 /* Choose an arbitrary, non-argument low register. */
14571 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
14573 /* Save it by copying it into a high, scratch register. */
14574 emit_insn (gen_movsi (spare, reg));
14575 /* Add a USE to stop propagate_one_insn() from barfing. */
14576 emit_insn (gen_prologue_use (spare));
14578 /* Decrement the stack. */
14579 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14580 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14581 stack_pointer_rtx, reg));
14582 RTX_FRAME_RELATED_P (insn) = 1;
14583 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14584 plus_constant (stack_pointer_rtx,
14586 RTX_FRAME_RELATED_P (dwarf) = 1;
14588 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14591 /* Restore the low register's original value. */
14592 emit_insn (gen_movsi (reg, spare));
14594 /* Emit a USE of the restored scratch register, so that flow
14595 analysis will not consider the restore redundant. The
14596 register won't be used again in this function and isn't
14597 restored by the epilogue. */
14598 emit_insn (gen_prologue_use (reg));
14602 reg = gen_rtx_REG (SImode, regno);
14604 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14606 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14607 stack_pointer_rtx, reg));
14608 RTX_FRAME_RELATED_P (insn) = 1;
14609 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14610 plus_constant (stack_pointer_rtx,
14612 RTX_FRAME_RELATED_P (dwarf) = 1;
14614 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14620 if (frame_pointer_needed)
14621 thumb_set_frame_pointer (offsets);
14623 /* If we are profiling, make sure no instructions are scheduled before
14624 the call to mcount. Similarly if the user has requested no
14625 scheduling in the prolog. Similarly if we want non-call exceptions
14626 using the EABI unwinder, to prevent faulting instructions from being
14627 swapped with a stack adjustment. */
14628 if (current_function_profile || !TARGET_SCHED_PROLOG
14629 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
14630 emit_insn (gen_blockage ());
14632 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
14633 if (live_regs_mask & 0xff)
14634 cfun->machine->lr_save_eliminated = 0;
14636 /* If the link register is being kept alive, with the return address in it,
14637 then make sure that it does not get reused by the ce2 pass. */
14638 if (cfun->machine->lr_save_eliminated)
14639 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
14644 thumb1_expand_epilogue (void)
14646 HOST_WIDE_INT amount;
14647 arm_stack_offsets *offsets;
14650 /* Naked functions don't have prologues. */
14651 if (IS_NAKED (arm_current_func_type ()))
14654 offsets = arm_get_frame_offsets ();
14655 amount = offsets->outgoing_args - offsets->saved_regs;
14657 if (frame_pointer_needed)
14659 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
14660 amount = offsets->locals_base - offsets->saved_regs;
14666 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14667 GEN_INT (amount)));
14670 /* r3 is always free in the epilogue. */
14671 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
14673 emit_insn (gen_movsi (reg, GEN_INT (amount)));
14674 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
14678 /* Emit a USE (stack_pointer_rtx), so that
14679 the stack adjustment will not be deleted. */
14680 emit_insn (gen_prologue_use (stack_pointer_rtx));
14682 if (current_function_profile || !TARGET_SCHED_PROLOG)
14683 emit_insn (gen_blockage ());
14685 /* Emit a clobber for each insn that will be restored in the epilogue,
14686 so that flow2 will get register lifetimes correct. */
14687 for (regno = 0; regno < 13; regno++)
14688 if (regs_ever_live[regno] && !call_used_regs[regno])
14689 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
14691 if (! regs_ever_live[LR_REGNUM])
14692 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
14696 thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14698 unsigned long live_regs_mask = 0;
14699 unsigned long l_mask;
14700 unsigned high_regs_pushed = 0;
14701 int cfa_offset = 0;
14704 if (IS_NAKED (arm_current_func_type ()))
14707 if (is_called_in_ARM_mode (current_function_decl))
14711 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
14712 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
14714 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14716 /* Generate code sequence to switch us into Thumb mode. */
14717 /* The .code 32 directive has already been emitted by
14718 ASM_DECLARE_FUNCTION_NAME. */
14719 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
14720 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
14722 /* Generate a label, so that the debugger will notice the
14723 change in instruction sets. This label is also used by
14724 the assembler to bypass the ARM code when this function
14725 is called from a Thumb encoded function elsewhere in the
14726 same file. Hence the definition of STUB_NAME here must
14727 agree with the definition in gas/config/tc-arm.c. */
14729 #define STUB_NAME ".real_start_of"
14731 fprintf (f, "\t.code\t16\n");
14733 if (arm_dllexport_name_p (name))
14734 name = arm_strip_name_encoding (name);
14736 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
14737 fprintf (f, "\t.thumb_func\n");
14738 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
14741 if (current_function_pretend_args_size)
14743 /* Output unwind directive for the stack adjustment. */
14744 if (ARM_EABI_UNWIND_TABLES)
14745 fprintf (f, "\t.pad #%d\n",
14746 current_function_pretend_args_size);
14748 if (cfun->machine->uses_anonymous_args)
14752 fprintf (f, "\tpush\t{");
14754 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
14756 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
14757 regno <= LAST_ARG_REGNUM;
14759 asm_fprintf (f, "%r%s", regno,
14760 regno == LAST_ARG_REGNUM ? "" : ", ");
14762 fprintf (f, "}\n");
14765 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
14766 SP_REGNUM, SP_REGNUM,
14767 current_function_pretend_args_size);
14769 /* We don't need to record the stores for unwinding (would it
14770 help the debugger any if we did?), but record the change in
14771 the stack pointer. */
14772 if (dwarf2out_do_frame ())
14774 char *l = dwarf2out_cfi_label ();
14776 cfa_offset = cfa_offset + current_function_pretend_args_size;
14777 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14781 /* Get the registers we are going to push. */
14782 live_regs_mask = thumb1_compute_save_reg_mask ();
14783 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14784 l_mask = live_regs_mask & 0x40ff;
14785 /* Then count how many other high registers will need to be pushed. */
14786 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14788 if (TARGET_BACKTRACE)
14791 unsigned work_register;
14793 /* We have been asked to create a stack backtrace structure.
14794 The code looks like this:
14798 0 sub SP, #16 Reserve space for 4 registers.
14799 2 push {R7} Push low registers.
14800 4 add R7, SP, #20 Get the stack pointer before the push.
14801 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14802 8 mov R7, PC Get hold of the start of this code plus 12.
14803 10 str R7, [SP, #16] Store it.
14804 12 mov R7, FP Get hold of the current frame pointer.
14805 14 str R7, [SP, #4] Store it.
14806 16 mov R7, LR Get hold of the current return address.
14807 18 str R7, [SP, #12] Store it.
14808 20 add R7, SP, #16 Point at the start of the backtrace structure.
14809 22 mov FP, R7 Put this value into the frame pointer. */
14811 work_register = thumb_find_work_register (live_regs_mask);
14813 if (ARM_EABI_UNWIND_TABLES)
14814 asm_fprintf (f, "\t.pad #16\n");
14817 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14818 SP_REGNUM, SP_REGNUM);
14820 if (dwarf2out_do_frame ())
14822 char *l = dwarf2out_cfi_label ();
14824 cfa_offset = cfa_offset + 16;
14825 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14830 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14831 offset = bit_count (l_mask) * UNITS_PER_WORD;
14836 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14837 offset + 16 + current_function_pretend_args_size);
14839 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14842 /* Make sure that the instruction fetching the PC is in the right place
14843 to calculate "start of backtrace creation code + 12". */
14846 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14847 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14849 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14850 ARM_HARD_FRAME_POINTER_REGNUM);
14851 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14856 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14857 ARM_HARD_FRAME_POINTER_REGNUM);
14858 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14860 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14861 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14865 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
14866 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14868 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14870 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14871 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
14873 /* Optimization: If we are not pushing any low registers but we are going
14874 to push some high registers then delay our first push. This will just
14875 be a push of LR and we can combine it with the push of the first high
14877 else if ((l_mask & 0xff) != 0
14878 || (high_regs_pushed == 0 && l_mask))
14879 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14881 if (high_regs_pushed)
14883 unsigned pushable_regs;
14884 unsigned next_hi_reg;
14886 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
14887 if (live_regs_mask & (1 << next_hi_reg))
14890 pushable_regs = l_mask & 0xff;
14892 if (pushable_regs == 0)
14893 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
14895 while (high_regs_pushed > 0)
14897 unsigned long real_regs_mask = 0;
14899 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
14901 if (pushable_regs & (1 << regno))
14903 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
14905 high_regs_pushed --;
14906 real_regs_mask |= (1 << next_hi_reg);
14908 if (high_regs_pushed)
14910 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
14912 if (live_regs_mask & (1 << next_hi_reg))
14917 pushable_regs &= ~((1 << regno) - 1);
14923 /* If we had to find a work register and we have not yet
14924 saved the LR then add it to the list of regs to push. */
14925 if (l_mask == (1 << LR_REGNUM))
14927 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
14929 real_regs_mask | (1 << LR_REGNUM));
14933 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
14938 /* Handle the case of a double word load into a low register from
14939 a computed memory address. The computed address may involve a
14940 register which is overwritten by the load. */
14942 thumb_load_double_from_address (rtx *operands)
14950 gcc_assert (GET_CODE (operands[0]) == REG);
14951 gcc_assert (GET_CODE (operands[1]) == MEM);
14953 /* Get the memory address. */
14954 addr = XEXP (operands[1], 0);
14956 /* Work out how the memory address is computed. */
14957 switch (GET_CODE (addr))
14960 operands[2] = adjust_address (operands[1], SImode, 4);
14962 if (REGNO (operands[0]) == REGNO (addr))
14964 output_asm_insn ("ldr\t%H0, %2", operands);
14965 output_asm_insn ("ldr\t%0, %1", operands);
14969 output_asm_insn ("ldr\t%0, %1", operands);
14970 output_asm_insn ("ldr\t%H0, %2", operands);
14975 /* Compute <address> + 4 for the high order load. */
14976 operands[2] = adjust_address (operands[1], SImode, 4);
14978 output_asm_insn ("ldr\t%0, %1", operands);
14979 output_asm_insn ("ldr\t%H0, %2", operands);
14983 arg1 = XEXP (addr, 0);
14984 arg2 = XEXP (addr, 1);
14986 if (CONSTANT_P (arg1))
14987 base = arg2, offset = arg1;
14989 base = arg1, offset = arg2;
14991 gcc_assert (GET_CODE (base) == REG);
14993 /* Catch the case of <address> = <reg> + <reg> */
14994 if (GET_CODE (offset) == REG)
14996 int reg_offset = REGNO (offset);
14997 int reg_base = REGNO (base);
14998 int reg_dest = REGNO (operands[0]);
15000 /* Add the base and offset registers together into the
15001 higher destination register. */
15002 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
15003 reg_dest + 1, reg_base, reg_offset);
15005 /* Load the lower destination register from the address in
15006 the higher destination register. */
15007 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
15008 reg_dest, reg_dest + 1);
15010 /* Load the higher destination register from its own address
15012 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
15013 reg_dest + 1, reg_dest + 1);
15017 /* Compute <address> + 4 for the high order load. */
15018 operands[2] = adjust_address (operands[1], SImode, 4);
15020 /* If the computed address is held in the low order register
15021 then load the high order register first, otherwise always
15022 load the low order register first. */
15023 if (REGNO (operands[0]) == REGNO (base))
15025 output_asm_insn ("ldr\t%H0, %2", operands);
15026 output_asm_insn ("ldr\t%0, %1", operands);
15030 output_asm_insn ("ldr\t%0, %1", operands);
15031 output_asm_insn ("ldr\t%H0, %2", operands);
15037 /* With no registers to worry about we can just load the value
15039 operands[2] = adjust_address (operands[1], SImode, 4);
15041 output_asm_insn ("ldr\t%H0, %2", operands);
15042 output_asm_insn ("ldr\t%0, %1", operands);
15046 gcc_unreachable ();
15053 thumb_output_move_mem_multiple (int n, rtx *operands)
15060 if (REGNO (operands[4]) > REGNO (operands[5]))
15063 operands[4] = operands[5];
15066 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
15067 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
15071 if (REGNO (operands[4]) > REGNO (operands[5]))
15074 operands[4] = operands[5];
15077 if (REGNO (operands[5]) > REGNO (operands[6]))
15080 operands[5] = operands[6];
15083 if (REGNO (operands[4]) > REGNO (operands[5]))
15086 operands[4] = operands[5];
15090 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
15091 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
15095 gcc_unreachable ();
15101 /* Output a call-via instruction for thumb state. */
15103 thumb_call_via_reg (rtx reg)
15105 int regno = REGNO (reg);
15108 gcc_assert (regno < LR_REGNUM);
15110 /* If we are in the normal text section we can use a single instance
15111 per compilation unit. If we are doing function sections, then we need
15112 an entry per section, since we can't rely on reachability. */
15113 if (in_section == text_section)
15115 thumb_call_reg_needed = 1;
15117 if (thumb_call_via_label[regno] == NULL)
15118 thumb_call_via_label[regno] = gen_label_rtx ();
15119 labelp = thumb_call_via_label + regno;
15123 if (cfun->machine->call_via[regno] == NULL)
15124 cfun->machine->call_via[regno] = gen_label_rtx ();
15125 labelp = cfun->machine->call_via + regno;
15128 output_asm_insn ("bl\t%a0", labelp);
15132 /* Routines for generating rtl. */
15134 thumb_expand_movmemqi (rtx *operands)
15136 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
15137 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
15138 HOST_WIDE_INT len = INTVAL (operands[2]);
15139 HOST_WIDE_INT offset = 0;
15143 emit_insn (gen_movmem12b (out, in, out, in));
15149 emit_insn (gen_movmem8b (out, in, out, in));
15155 rtx reg = gen_reg_rtx (SImode);
15156 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
15157 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
15164 rtx reg = gen_reg_rtx (HImode);
15165 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
15166 plus_constant (in, offset))));
15167 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
15175 rtx reg = gen_reg_rtx (QImode);
15176 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
15177 plus_constant (in, offset))));
15178 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
15184 thumb_reload_out_hi (rtx *operands)
15186 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
15189 /* Handle reading a half-word from memory during reload. */
15191 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
15193 gcc_unreachable ();
15196 /* Return the length of a function name prefix
15197 that starts with the character 'c'. */
15199 arm_get_strip_length (int c)
15203 ARM_NAME_ENCODING_LENGTHS
15208 /* Return a pointer to a function's name with any
15209 and all prefix encodings stripped from it. */
15211 arm_strip_name_encoding (const char *name)
15215 while ((skip = arm_get_strip_length (* name)))
15221 /* If there is a '*' anywhere in the name's prefix, then
15222 emit the stripped name verbatim, otherwise prepend an
15223 underscore if leading underscores are being used. */
15225 arm_asm_output_labelref (FILE *stream, const char *name)
15230 while ((skip = arm_get_strip_length (* name)))
15232 verbatim |= (*name == '*');
15237 fputs (name, stream);
15239 asm_fprintf (stream, "%U%s", name);
15243 arm_file_start (void)
15247 if (TARGET_UNIFIED_ASM)
15248 asm_fprintf (asm_out_file, "\t.syntax unified\n");
15252 const char *fpu_name;
15253 if (arm_select[0].string)
15254 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
15255 else if (arm_select[1].string)
15256 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
15258 asm_fprintf (asm_out_file, "\t.cpu %s\n",
15259 all_cores[arm_default_cpu].name);
15261 if (TARGET_SOFT_FLOAT)
15264 fpu_name = "softvfp";
15266 fpu_name = "softfpa";
15270 switch (arm_fpu_arch)
15275 case FPUTYPE_FPA_EMU2:
15278 case FPUTYPE_FPA_EMU3:
15281 case FPUTYPE_MAVERICK:
15282 fpu_name = "maverick";
15285 if (TARGET_HARD_FLOAT)
15286 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
15287 if (TARGET_HARD_FLOAT_ABI)
15288 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
15295 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
15297 /* Some of these attributes only apply when the corresponding features
15298 are used. However we don't have any easy way of figuring this out.
15299 Conservatively record the setting that would have been used. */
15301 /* Tag_ABI_PCS_wchar_t. */
15302 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
15303 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
15305 /* Tag_ABI_FP_rounding. */
15306 if (flag_rounding_math)
15307 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
15308 if (!flag_unsafe_math_optimizations)
15310 /* Tag_ABI_FP_denomal. */
15311 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
15312 /* Tag_ABI_FP_exceptions. */
15313 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
15315 /* Tag_ABI_FP_user_exceptions. */
15316 if (flag_signaling_nans)
15317 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
15318 /* Tag_ABI_FP_number_model. */
15319 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
15320 flag_finite_math_only ? 1 : 3);
15322 /* Tag_ABI_align8_needed. */
15323 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
15324 /* Tag_ABI_align8_preserved. */
15325 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
15326 /* Tag_ABI_enum_size. */
15327 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
15328 flag_short_enums ? 1 : 2);
15330 /* Tag_ABI_optimization_goals. */
15333 else if (optimize >= 2)
15339 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
15341 default_file_start();
15345 arm_file_end (void)
15349 if (NEED_INDICATE_EXEC_STACK)
15350 /* Add .note.GNU-stack. */
15351 file_end_indicate_exec_stack ();
15353 if (! thumb_call_reg_needed)
15356 switch_to_section (text_section);
15357 asm_fprintf (asm_out_file, "\t.code 16\n");
15358 ASM_OUTPUT_ALIGN (asm_out_file, 1);
15360 for (regno = 0; regno < LR_REGNUM; regno++)
15362 rtx label = thumb_call_via_label[regno];
15366 targetm.asm_out.internal_label (asm_out_file, "L",
15367 CODE_LABEL_NUMBER (label));
15368 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
15375 #ifdef AOF_ASSEMBLER
15376 /* Special functions only needed when producing AOF syntax assembler. */
15380 struct pic_chain * next;
15381 const char * symname;
15384 static struct pic_chain * aof_pic_chain = NULL;
15387 aof_pic_entry (rtx x)
15389 struct pic_chain ** chainp;
15392 if (aof_pic_label == NULL_RTX)
15394 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
15397 for (offset = 0, chainp = &aof_pic_chain; *chainp;
15398 offset += 4, chainp = &(*chainp)->next)
15399 if ((*chainp)->symname == XSTR (x, 0))
15400 return plus_constant (aof_pic_label, offset);
15402 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
15403 (*chainp)->next = NULL;
15404 (*chainp)->symname = XSTR (x, 0);
15405 return plus_constant (aof_pic_label, offset);
15409 aof_dump_pic_table (FILE *f)
15411 struct pic_chain * chain;
15413 if (aof_pic_chain == NULL)
15416 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
15417 PIC_OFFSET_TABLE_REGNUM,
15418 PIC_OFFSET_TABLE_REGNUM);
15419 fputs ("|x$adcons|\n", f);
15421 for (chain = aof_pic_chain; chain; chain = chain->next)
15423 fputs ("\tDCD\t", f);
15424 assemble_name (f, chain->symname);
15429 int arm_text_section_count = 1;
15431 /* A get_unnamed_section callback for switching to the text section. */
15434 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15436 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
15437 arm_text_section_count++);
15439 fprintf (asm_out_file, ", PIC, REENTRANT");
15440 fprintf (asm_out_file, "\n");
15443 static int arm_data_section_count = 1;
15445 /* A get_unnamed_section callback for switching to the data section. */
15448 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15450 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
15451 arm_data_section_count++);
15454 /* Implement TARGET_ASM_INIT_SECTIONS.
15456 AOF Assembler syntax is a nightmare when it comes to areas, since once
15457 we change from one area to another, we can't go back again. Instead,
15458 we must create a new area with the same attributes and add the new output
15459 to that. Unfortunately, there is nothing we can do here to guarantee that
15460 two areas with the same attributes will be linked adjacently in the
15461 resulting executable, so we have to be careful not to do pc-relative
15462 addressing across such boundaries. */
15465 aof_asm_init_sections (void)
15467 text_section = get_unnamed_section (SECTION_CODE,
15468 aof_output_text_section_asm_op, NULL);
15469 data_section = get_unnamed_section (SECTION_WRITE,
15470 aof_output_data_section_asm_op, NULL);
15471 readonly_data_section = text_section;
15475 zero_init_section (void)
15477 static int zero_init_count = 1;
15479 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
15483 /* The AOF assembler is religiously strict about declarations of
15484 imported and exported symbols, so that it is impossible to declare
15485 a function as imported near the beginning of the file, and then to
15486 export it later on. It is, however, possible to delay the decision
15487 until all the functions in the file have been compiled. To get
15488 around this, we maintain a list of the imports and exports, and
15489 delete from it any that are subsequently defined. At the end of
15490 compilation we spit the remainder of the list out before the END
15495 struct import * next;
15499 static struct import * imports_list = NULL;
15502 aof_add_import (const char *name)
15504 struct import * new;
15506 for (new = imports_list; new; new = new->next)
15507 if (new->name == name)
15510 new = (struct import *) xmalloc (sizeof (struct import));
15511 new->next = imports_list;
15512 imports_list = new;
15517 aof_delete_import (const char *name)
15519 struct import ** old;
15521 for (old = &imports_list; *old; old = & (*old)->next)
15523 if ((*old)->name == name)
15525 *old = (*old)->next;
15531 int arm_main_function = 0;
15534 aof_dump_imports (FILE *f)
15536 /* The AOF assembler needs this to cause the startup code to be extracted
15537 from the library. Brining in __main causes the whole thing to work
15539 if (arm_main_function)
15541 switch_to_section (text_section);
15542 fputs ("\tIMPORT __main\n", f);
15543 fputs ("\tDCD __main\n", f);
15546 /* Now dump the remaining imports. */
15547 while (imports_list)
15549 fprintf (f, "\tIMPORT\t");
15550 assemble_name (f, imports_list->name);
15552 imports_list = imports_list->next;
15557 aof_globalize_label (FILE *stream, const char *name)
15559 default_globalize_label (stream, name);
15560 if (! strcmp (name, "main"))
15561 arm_main_function = 1;
15565 aof_file_start (void)
15567 fputs ("__r0\tRN\t0\n", asm_out_file);
15568 fputs ("__a1\tRN\t0\n", asm_out_file);
15569 fputs ("__a2\tRN\t1\n", asm_out_file);
15570 fputs ("__a3\tRN\t2\n", asm_out_file);
15571 fputs ("__a4\tRN\t3\n", asm_out_file);
15572 fputs ("__v1\tRN\t4\n", asm_out_file);
15573 fputs ("__v2\tRN\t5\n", asm_out_file);
15574 fputs ("__v3\tRN\t6\n", asm_out_file);
15575 fputs ("__v4\tRN\t7\n", asm_out_file);
15576 fputs ("__v5\tRN\t8\n", asm_out_file);
15577 fputs ("__v6\tRN\t9\n", asm_out_file);
15578 fputs ("__sl\tRN\t10\n", asm_out_file);
15579 fputs ("__fp\tRN\t11\n", asm_out_file);
15580 fputs ("__ip\tRN\t12\n", asm_out_file);
15581 fputs ("__sp\tRN\t13\n", asm_out_file);
15582 fputs ("__lr\tRN\t14\n", asm_out_file);
15583 fputs ("__pc\tRN\t15\n", asm_out_file);
15584 fputs ("__f0\tFN\t0\n", asm_out_file);
15585 fputs ("__f1\tFN\t1\n", asm_out_file);
15586 fputs ("__f2\tFN\t2\n", asm_out_file);
15587 fputs ("__f3\tFN\t3\n", asm_out_file);
15588 fputs ("__f4\tFN\t4\n", asm_out_file);
15589 fputs ("__f5\tFN\t5\n", asm_out_file);
15590 fputs ("__f6\tFN\t6\n", asm_out_file);
15591 fputs ("__f7\tFN\t7\n", asm_out_file);
15592 switch_to_section (text_section);
15596 aof_file_end (void)
15599 aof_dump_pic_table (asm_out_file);
15601 aof_dump_imports (asm_out_file);
15602 fputs ("\tEND\n", asm_out_file);
15604 #endif /* AOF_ASSEMBLER */
15607 /* Symbols in the text segment can be accessed without indirecting via the
15608 constant pool; it may take an extra binary operation, but this is still
15609 faster than indirecting via memory. Don't do this when not optimizing,
15610 since we won't be calculating al of the offsets necessary to do this
15614 arm_encode_section_info (tree decl, rtx rtl, int first)
15616 /* This doesn't work with AOF syntax, since the string table may be in
15617 a different AREA. */
15618 #ifndef AOF_ASSEMBLER
15619 if (optimize > 0 && TREE_CONSTANT (decl))
15620 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
15623 default_encode_section_info (decl, rtl, first);
15625 #endif /* !ARM_PE */
15628 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
15630 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
15631 && !strcmp (prefix, "L"))
15633 arm_ccfsm_state = 0;
15634 arm_target_insn = NULL;
15636 default_internal_label (stream, prefix, labelno);
15639 /* Output code to add DELTA to the first argument, and then jump
15640 to FUNCTION. Used for C++ multiple inheritance. */
15642 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
15643 HOST_WIDE_INT delta,
15644 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
15647 static int thunk_label = 0;
15650 int mi_delta = delta;
15651 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
15653 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
15656 mi_delta = - mi_delta;
15657 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15660 int labelno = thunk_label++;
15661 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
15662 fputs ("\tldr\tr12, ", file);
15663 assemble_name (file, label);
15664 fputc ('\n', file);
15667 /* If we are generating PIC, the ldr instruction below loads
15668 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15669 the address of the add + 8, so we have:
15671 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15674 Note that we have "+ 1" because some versions of GNU ld
15675 don't set the low bit of the result for R_ARM_REL32
15676 relocations against thumb function symbols. */
15677 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
15678 assemble_name (file, labelpc);
15679 fputs (":\n", file);
15680 fputs ("\tadd\tr12, pc, r12\n", file);
15683 /* TODO: Use movw/movt for large constants when available. */
15684 while (mi_delta != 0)
15686 if ((mi_delta & (3 << shift)) == 0)
15690 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
15691 mi_op, this_regno, this_regno,
15692 mi_delta & (0xff << shift));
15693 mi_delta &= ~(0xff << shift);
15699 fprintf (file, "\tbx\tr12\n");
15700 ASM_OUTPUT_ALIGN (file, 2);
15701 assemble_name (file, label);
15702 fputs (":\n", file);
15705 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15706 rtx tem = XEXP (DECL_RTL (function), 0);
15707 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
15708 tem = gen_rtx_MINUS (GET_MODE (tem),
15710 gen_rtx_SYMBOL_REF (Pmode,
15711 ggc_strdup (labelpc)));
15712 assemble_integer (tem, 4, BITS_PER_WORD, 1);
15715 /* Output ".word .LTHUNKn". */
15716 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
15720 fputs ("\tb\t", file);
15721 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
15722 if (NEED_PLT_RELOC)
15723 fputs ("(PLT)", file);
15724 fputc ('\n', file);
15729 arm_emit_vector_const (FILE *file, rtx x)
15732 const char * pattern;
15734 gcc_assert (GET_CODE (x) == CONST_VECTOR);
15736 switch (GET_MODE (x))
15738 case V2SImode: pattern = "%08x"; break;
15739 case V4HImode: pattern = "%04x"; break;
15740 case V8QImode: pattern = "%02x"; break;
15741 default: gcc_unreachable ();
15744 fprintf (file, "0x");
15745 for (i = CONST_VECTOR_NUNITS (x); i--;)
15749 element = CONST_VECTOR_ELT (x, i);
15750 fprintf (file, pattern, INTVAL (element));
15757 arm_output_load_gr (rtx *operands)
15764 if (GET_CODE (operands [1]) != MEM
15765 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
15766 || GET_CODE (reg = XEXP (sum, 0)) != REG
15767 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
15768 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
15769 return "wldrw%?\t%0, %1";
15771 /* Fix up an out-of-range load of a GR register. */
15772 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
15773 wcgr = operands[0];
15775 output_asm_insn ("ldr%?\t%0, %1", operands);
15777 operands[0] = wcgr;
15779 output_asm_insn ("tmcr%?\t%0, %1", operands);
15780 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
15785 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
15787 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
15788 named arg and all anonymous args onto the stack.
15789 XXX I know the prologue shouldn't be pushing registers, but it is faster
15793 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
15794 enum machine_mode mode ATTRIBUTE_UNUSED,
15795 tree type ATTRIBUTE_UNUSED,
15797 int second_time ATTRIBUTE_UNUSED)
15799 cfun->machine->uses_anonymous_args = 1;
15800 if (cum->nregs < NUM_ARG_REGS)
15801 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
15804 /* Return nonzero if the CONSUMER instruction (a store) does not need
15805 PRODUCER's value to calculate the address. */
15808 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
15810 rtx value = PATTERN (producer);
15811 rtx addr = PATTERN (consumer);
15813 if (GET_CODE (value) == COND_EXEC)
15814 value = COND_EXEC_CODE (value);
15815 if (GET_CODE (value) == PARALLEL)
15816 value = XVECEXP (value, 0, 0);
15817 value = XEXP (value, 0);
15818 if (GET_CODE (addr) == COND_EXEC)
15819 addr = COND_EXEC_CODE (addr);
15820 if (GET_CODE (addr) == PARALLEL)
15821 addr = XVECEXP (addr, 0, 0);
15822 addr = XEXP (addr, 0);
15824 return !reg_overlap_mentioned_p (value, addr);
15827 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15828 have an early register shift value or amount dependency on the
15829 result of PRODUCER. */
15832 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
15834 rtx value = PATTERN (producer);
15835 rtx op = PATTERN (consumer);
15838 if (GET_CODE (value) == COND_EXEC)
15839 value = COND_EXEC_CODE (value);
15840 if (GET_CODE (value) == PARALLEL)
15841 value = XVECEXP (value, 0, 0);
15842 value = XEXP (value, 0);
15843 if (GET_CODE (op) == COND_EXEC)
15844 op = COND_EXEC_CODE (op);
15845 if (GET_CODE (op) == PARALLEL)
15846 op = XVECEXP (op, 0, 0);
15849 early_op = XEXP (op, 0);
15850 /* This is either an actual independent shift, or a shift applied to
15851 the first operand of another operation. We want the whole shift
15853 if (GET_CODE (early_op) == REG)
15856 return !reg_overlap_mentioned_p (value, early_op);
15859 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15860 have an early register shift value dependency on the result of
15864 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
15866 rtx value = PATTERN (producer);
15867 rtx op = PATTERN (consumer);
15870 if (GET_CODE (value) == COND_EXEC)
15871 value = COND_EXEC_CODE (value);
15872 if (GET_CODE (value) == PARALLEL)
15873 value = XVECEXP (value, 0, 0);
15874 value = XEXP (value, 0);
15875 if (GET_CODE (op) == COND_EXEC)
15876 op = COND_EXEC_CODE (op);
15877 if (GET_CODE (op) == PARALLEL)
15878 op = XVECEXP (op, 0, 0);
15881 early_op = XEXP (op, 0);
15883 /* This is either an actual independent shift, or a shift applied to
15884 the first operand of another operation. We want the value being
15885 shifted, in either case. */
15886 if (GET_CODE (early_op) != REG)
15887 early_op = XEXP (early_op, 0);
15889 return !reg_overlap_mentioned_p (value, early_op);
15892 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15893 have an early register mult dependency on the result of
15897 arm_no_early_mul_dep (rtx producer, rtx consumer)
15899 rtx value = PATTERN (producer);
15900 rtx op = PATTERN (consumer);
15902 if (GET_CODE (value) == COND_EXEC)
15903 value = COND_EXEC_CODE (value);
15904 if (GET_CODE (value) == PARALLEL)
15905 value = XVECEXP (value, 0, 0);
15906 value = XEXP (value, 0);
15907 if (GET_CODE (op) == COND_EXEC)
15908 op = COND_EXEC_CODE (op);
15909 if (GET_CODE (op) == PARALLEL)
15910 op = XVECEXP (op, 0, 0);
15913 return (GET_CODE (op) == PLUS
15914 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
15918 /* We can't rely on the caller doing the proper promotion when
15919 using APCS or ATPCS. */
15922 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
15924 return !TARGET_AAPCS_BASED;
15928 /* AAPCS based ABIs use short enums by default. */
15931 arm_default_short_enums (void)
15933 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
15937 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15940 arm_align_anon_bitfield (void)
15942 return TARGET_AAPCS_BASED;
15946 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15949 arm_cxx_guard_type (void)
15951 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
15955 /* The EABI says test the least significant bit of a guard variable. */
15958 arm_cxx_guard_mask_bit (void)
15960 return TARGET_AAPCS_BASED;
15964 /* The EABI specifies that all array cookies are 8 bytes long. */
15967 arm_get_cookie_size (tree type)
15971 if (!TARGET_AAPCS_BASED)
15972 return default_cxx_get_cookie_size (type);
15974 size = build_int_cst (sizetype, 8);
15979 /* The EABI says that array cookies should also contain the element size. */
15982 arm_cookie_has_size (void)
15984 return TARGET_AAPCS_BASED;
15988 /* The EABI says constructors and destructors should return a pointer to
15989 the object constructed/destroyed. */
15992 arm_cxx_cdtor_returns_this (void)
15994 return TARGET_AAPCS_BASED;
15997 /* The EABI says that an inline function may never be the key
16001 arm_cxx_key_method_may_be_inline (void)
16003 return !TARGET_AAPCS_BASED;
16007 arm_cxx_determine_class_data_visibility (tree decl)
16009 if (!TARGET_AAPCS_BASED)
16012 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
16013 is exported. However, on systems without dynamic vague linkage,
16014 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
16015 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
16016 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
16018 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
16019 DECL_VISIBILITY_SPECIFIED (decl) = 1;
16023 arm_cxx_class_data_always_comdat (void)
16025 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
16026 vague linkage if the class has no key function. */
16027 return !TARGET_AAPCS_BASED;
16031 /* The EABI says __aeabi_atexit should be used to register static
16035 arm_cxx_use_aeabi_atexit (void)
16037 return TARGET_AAPCS_BASED;
16042 arm_set_return_address (rtx source, rtx scratch)
16044 arm_stack_offsets *offsets;
16045 HOST_WIDE_INT delta;
16047 unsigned long saved_regs;
16049 saved_regs = arm_compute_save_reg_mask ();
16051 if ((saved_regs & (1 << LR_REGNUM)) == 0)
16052 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16055 if (frame_pointer_needed)
16056 addr = plus_constant(hard_frame_pointer_rtx, -4);
16059 /* LR will be the first saved register. */
16060 offsets = arm_get_frame_offsets ();
16061 delta = offsets->outgoing_args - (offsets->frame + 4);
16066 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
16067 GEN_INT (delta & ~4095)));
16072 addr = stack_pointer_rtx;
16074 addr = plus_constant (addr, delta);
16076 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16082 thumb_set_return_address (rtx source, rtx scratch)
16084 arm_stack_offsets *offsets;
16085 HOST_WIDE_INT delta;
16086 HOST_WIDE_INT limit;
16089 unsigned long mask;
16091 emit_insn (gen_rtx_USE (VOIDmode, source));
16093 mask = thumb1_compute_save_reg_mask ();
16094 if (mask & (1 << LR_REGNUM))
16096 offsets = arm_get_frame_offsets ();
16099 /* Find the saved regs. */
16100 if (frame_pointer_needed)
16102 delta = offsets->soft_frame - offsets->saved_args;
16103 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
16109 delta = offsets->outgoing_args - offsets->saved_args;
16112 /* Allow for the stack frame. */
16113 if (TARGET_THUMB1 && TARGET_BACKTRACE)
16115 /* The link register is always the first saved register. */
16118 /* Construct the address. */
16119 addr = gen_rtx_REG (SImode, reg);
16122 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
16123 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
16127 addr = plus_constant (addr, delta);
16129 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16132 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16135 /* Implements target hook vector_mode_supported_p. */
16137 arm_vector_mode_supported_p (enum machine_mode mode)
16139 if ((mode == V2SImode)
16140 || (mode == V4HImode)
16141 || (mode == V8QImode))
16147 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16148 ARM insns and therefore guarantee that the shift count is modulo 256.
16149 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16150 guarantee no particular behavior for out-of-range counts. */
16152 static unsigned HOST_WIDE_INT
16153 arm_shift_truncation_mask (enum machine_mode mode)
16155 return mode == SImode ? 255 : 0;
16159 /* Map internal gcc register numbers to DWARF2 register numbers. */
16162 arm_dbx_register_number (unsigned int regno)
16167 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16168 compatibility. The EABI defines them as registers 96-103. */
16169 if (IS_FPA_REGNUM (regno))
16170 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
16172 if (IS_VFP_REGNUM (regno))
16173 return 64 + regno - FIRST_VFP_REGNUM;
16175 if (IS_IWMMXT_GR_REGNUM (regno))
16176 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
16178 if (IS_IWMMXT_REGNUM (regno))
16179 return 112 + regno - FIRST_IWMMXT_REGNUM;
16181 gcc_unreachable ();
16185 #ifdef TARGET_UNWIND_INFO
16186 /* Emit unwind directives for a store-multiple instruction or stack pointer
16187 push during alignment.
16188 These should only ever be generated by the function prologue code, so
16189 expect them to have a particular form. */
16192 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
16195 HOST_WIDE_INT offset;
16196 HOST_WIDE_INT nregs;
16202 e = XVECEXP (p, 0, 0);
16203 if (GET_CODE (e) != SET)
16206 /* First insn will adjust the stack pointer. */
16207 if (GET_CODE (e) != SET
16208 || GET_CODE (XEXP (e, 0)) != REG
16209 || REGNO (XEXP (e, 0)) != SP_REGNUM
16210 || GET_CODE (XEXP (e, 1)) != PLUS)
16213 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
16214 nregs = XVECLEN (p, 0) - 1;
16216 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
16219 /* The function prologue may also push pc, but not annotate it as it is
16220 never restored. We turn this into a stack pointer adjustment. */
16221 if (nregs * 4 == offset - 4)
16223 fprintf (asm_out_file, "\t.pad #4\n");
16227 fprintf (asm_out_file, "\t.save {");
16229 else if (IS_VFP_REGNUM (reg))
16232 fprintf (asm_out_file, "\t.vsave {");
16234 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
16236 /* FPA registers are done differently. */
16237 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
16241 /* Unknown register type. */
16244 /* If the stack increment doesn't match the size of the saved registers,
16245 something has gone horribly wrong. */
16246 if (offset != nregs * reg_size)
16251 /* The remaining insns will describe the stores. */
16252 for (i = 1; i <= nregs; i++)
16254 /* Expect (set (mem <addr>) (reg)).
16255 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16256 e = XVECEXP (p, 0, i);
16257 if (GET_CODE (e) != SET
16258 || GET_CODE (XEXP (e, 0)) != MEM
16259 || GET_CODE (XEXP (e, 1)) != REG)
16262 reg = REGNO (XEXP (e, 1));
16267 fprintf (asm_out_file, ", ");
16268 /* We can't use %r for vfp because we need to use the
16269 double precision register names. */
16270 if (IS_VFP_REGNUM (reg))
16271 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
16273 asm_fprintf (asm_out_file, "%r", reg);
16275 #ifdef ENABLE_CHECKING
16276 /* Check that the addresses are consecutive. */
16277 e = XEXP (XEXP (e, 0), 0);
16278 if (GET_CODE (e) == PLUS)
16280 offset += reg_size;
16281 if (GET_CODE (XEXP (e, 0)) != REG
16282 || REGNO (XEXP (e, 0)) != SP_REGNUM
16283 || GET_CODE (XEXP (e, 1)) != CONST_INT
16284 || offset != INTVAL (XEXP (e, 1)))
16288 || GET_CODE (e) != REG
16289 || REGNO (e) != SP_REGNUM)
16293 fprintf (asm_out_file, "}\n");
16296 /* Emit unwind directives for a SET. */
16299 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
16307 switch (GET_CODE (e0))
16310 /* Pushing a single register. */
16311 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
16312 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
16313 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
16316 asm_fprintf (asm_out_file, "\t.save ");
16317 if (IS_VFP_REGNUM (REGNO (e1)))
16318 asm_fprintf(asm_out_file, "{d%d}\n",
16319 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
16321 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
16325 if (REGNO (e0) == SP_REGNUM)
16327 /* A stack increment. */
16328 if (GET_CODE (e1) != PLUS
16329 || GET_CODE (XEXP (e1, 0)) != REG
16330 || REGNO (XEXP (e1, 0)) != SP_REGNUM
16331 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16334 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
16335 -INTVAL (XEXP (e1, 1)));
16337 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
16339 HOST_WIDE_INT offset;
16341 if (GET_CODE (e1) == PLUS)
16343 if (GET_CODE (XEXP (e1, 0)) != REG
16344 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16346 reg = REGNO (XEXP (e1, 0));
16347 offset = INTVAL (XEXP (e1, 1));
16348 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
16349 HARD_FRAME_POINTER_REGNUM, reg,
16350 INTVAL (XEXP (e1, 1)));
16352 else if (GET_CODE (e1) == REG)
16355 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
16356 HARD_FRAME_POINTER_REGNUM, reg);
16361 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
16363 /* Move from sp to reg. */
16364 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
16366 else if (GET_CODE (e1) == PLUS
16367 && GET_CODE (XEXP (e1, 0)) == REG
16368 && REGNO (XEXP (e1, 0)) == SP_REGNUM
16369 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
16371 /* Set reg to offset from sp. */
16372 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
16373 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
16375 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
16377 /* Stack pointer save before alignment. */
16379 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16392 /* Emit unwind directives for the given insn. */
16395 arm_unwind_emit (FILE * asm_out_file, rtx insn)
16399 if (!ARM_EABI_UNWIND_TABLES)
16402 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
16405 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
16407 pat = XEXP (pat, 0);
16409 pat = PATTERN (insn);
16411 switch (GET_CODE (pat))
16414 arm_unwind_emit_set (asm_out_file, pat);
16418 /* Store multiple. */
16419 arm_unwind_emit_sequence (asm_out_file, pat);
16428 /* Output a reference from a function exception table to the type_info
16429 object X. The EABI specifies that the symbol should be relocated by
16430 an R_ARM_TARGET2 relocation. */
16433 arm_output_ttype (rtx x)
16435 fputs ("\t.word\t", asm_out_file);
16436 output_addr_const (asm_out_file, x);
16437 /* Use special relocations for symbol references. */
16438 if (GET_CODE (x) != CONST_INT)
16439 fputs ("(TARGET2)", asm_out_file);
16440 fputc ('\n', asm_out_file);
16444 #endif /* TARGET_UNWIND_INFO */
16447 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16448 stack alignment. */
16451 arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
16453 rtx unspec = SET_SRC (pattern);
16454 gcc_assert (GET_CODE (unspec) == UNSPEC);
16458 case UNSPEC_STACK_ALIGN:
16459 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16460 put anything on the stack, so hopefully it won't matter.
16461 CFA = SP will be correct after alignment. */
16462 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
16463 SET_DEST (pattern));
16466 gcc_unreachable ();
16471 /* Output unwind directives for the start/end of a function. */
16474 arm_output_fn_unwind (FILE * f, bool prologue)
16476 if (!ARM_EABI_UNWIND_TABLES)
16480 fputs ("\t.fnstart\n", f);
16482 fputs ("\t.fnend\n", f);
16486 arm_emit_tls_decoration (FILE *fp, rtx x)
16488 enum tls_reloc reloc;
16491 val = XVECEXP (x, 0, 0);
16492 reloc = INTVAL (XVECEXP (x, 0, 1));
16494 output_addr_const (fp, val);
16499 fputs ("(tlsgd)", fp);
16502 fputs ("(tlsldm)", fp);
16505 fputs ("(tlsldo)", fp);
16508 fputs ("(gottpoff)", fp);
16511 fputs ("(tpoff)", fp);
16514 gcc_unreachable ();
16522 fputs (" + (. - ", fp);
16523 output_addr_const (fp, XVECEXP (x, 0, 2));
16525 output_addr_const (fp, XVECEXP (x, 0, 3));
16536 arm_output_addr_const_extra (FILE *fp, rtx x)
16538 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
16539 return arm_emit_tls_decoration (fp, x);
16540 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
16543 int labelno = INTVAL (XVECEXP (x, 0, 0));
16545 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
16546 assemble_name_raw (fp, label);
16550 else if (GET_CODE (x) == CONST_VECTOR)
16551 return arm_emit_vector_const (fp, x);
16556 /* Output assembly for a shift instruction.
16557 SET_FLAGS determines how the instruction modifies the condition codes.
16558 0 - Do not set condition codes.
16559 1 - Set condition codes.
16560 2 - Use smallest instruction. */
16562 arm_output_shift(rtx * operands, int set_flags)
16565 static const char flag_chars[3] = {'?', '.', '!'};
16570 c = flag_chars[set_flags];
16571 if (TARGET_UNIFIED_ASM)
16573 shift = shift_op(operands[3], &val);
16577 operands[2] = GEN_INT(val);
16578 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
16581 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
16584 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
16585 output_asm_insn (pattern, operands);
16589 /* Output a Thumb-2 casesi instruction. */
16591 thumb2_output_casesi (rtx *operands)
16593 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
16595 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
16597 output_asm_insn ("cmp\t%0, %1", operands);
16598 output_asm_insn ("bhi\t%l3", operands);
16599 switch (GET_MODE(diff_vec))
16602 return "tbb\t[%|pc, %0]";
16604 return "tbh\t[%|pc, %0, lsl #1]";
16608 output_asm_insn ("adr\t%4, %l2", operands);
16609 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
16610 output_asm_insn ("add\t%4, %4, %5", operands);
16615 output_asm_insn ("adr\t%4, %l2", operands);
16616 return "ldr\t%|pc, [%4, %0, lsl #2]";
16619 gcc_unreachable ();
16623 #include "gt-arm.h"