1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int count_insns_for_constant (HOST_WIDE_INT, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree, tree);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
126 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
127 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
128 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
130 static bool arm_9e_rtx_costs (rtx, int, int, int *);
131 static int arm_address_cost (rtx);
132 static bool arm_memory_load_p (rtx);
133 static bool arm_cirrus_insn_p (rtx);
134 static void cirrus_reorg (rtx);
135 static void arm_init_builtins (void);
136 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
137 static void arm_init_iwmmxt_builtins (void);
138 static rtx safe_vector_operand (rtx, enum machine_mode);
139 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
140 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
141 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
142 static void emit_constant_insn (rtx cond, rtx pattern);
144 #ifdef OBJECT_FORMAT_ELF
145 static void arm_elf_asm_named_section (const char *, unsigned int);
148 static void arm_encode_section_info (tree, rtx, int);
151 static void aof_globalize_label (FILE *, const char *);
152 static void aof_dump_imports (FILE *);
153 static void aof_dump_pic_table (FILE *);
154 static void aof_file_start (void);
155 static void aof_file_end (void);
157 static rtx arm_struct_value_rtx (tree, int);
158 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
160 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
161 enum machine_mode, tree, bool);
162 static bool arm_promote_prototypes (tree);
163 static bool arm_default_short_enums (void);
164 static bool arm_align_anon_bitfield (void);
166 static tree arm_cxx_guard_type (void);
167 static bool arm_cxx_guard_mask_bit (void);
168 static tree arm_get_cookie_size (tree);
169 static bool arm_cookie_has_size (void);
172 /* Initialize the GCC target structure. */
173 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
174 #undef TARGET_MERGE_DECL_ATTRIBUTES
175 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
178 #undef TARGET_ATTRIBUTE_TABLE
179 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
182 #undef TARGET_ASM_BYTE_OP
183 #define TARGET_ASM_BYTE_OP "\tDCB\t"
184 #undef TARGET_ASM_ALIGNED_HI_OP
185 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
186 #undef TARGET_ASM_ALIGNED_SI_OP
187 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
188 #undef TARGET_ASM_GLOBALIZE_LABEL
189 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
190 #undef TARGET_ASM_FILE_START
191 #define TARGET_ASM_FILE_START aof_file_start
192 #undef TARGET_ASM_FILE_END
193 #define TARGET_ASM_FILE_END aof_file_end
195 #undef TARGET_ASM_ALIGNED_SI_OP
196 #define TARGET_ASM_ALIGNED_SI_OP NULL
197 #undef TARGET_ASM_INTEGER
198 #define TARGET_ASM_INTEGER arm_assemble_integer
201 #undef TARGET_ASM_FUNCTION_PROLOGUE
202 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
204 #undef TARGET_ASM_FUNCTION_EPILOGUE
205 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
207 #undef TARGET_COMP_TYPE_ATTRIBUTES
208 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
210 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
211 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
213 #undef TARGET_SCHED_ADJUST_COST
214 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
216 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
217 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
219 #undef TARGET_ENCODE_SECTION_INFO
221 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
223 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
229 #undef TARGET_ASM_INTERNAL_LABEL
230 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 /* This will be overridden in arm_override_options. */
241 #undef TARGET_RTX_COSTS
242 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
243 #undef TARGET_ADDRESS_COST
244 #define TARGET_ADDRESS_COST arm_address_cost
246 #undef TARGET_MACHINE_DEPENDENT_REORG
247 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
249 #undef TARGET_INIT_BUILTINS
250 #define TARGET_INIT_BUILTINS arm_init_builtins
251 #undef TARGET_EXPAND_BUILTIN
252 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
254 #undef TARGET_PROMOTE_FUNCTION_ARGS
255 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
256 #undef TARGET_PROMOTE_FUNCTION_RETURN
257 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
258 #undef TARGET_PROMOTE_PROTOTYPES
259 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
260 #undef TARGET_PASS_BY_REFERENCE
261 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
263 #undef TARGET_STRUCT_VALUE_RTX
264 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
266 #undef TARGET_SETUP_INCOMING_VARARGS
267 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
269 #undef TARGET_DEFAULT_SHORT_ENUMS
270 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
272 #undef TARGET_ALIGN_ANON_BITFIELD
273 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
275 #undef TARGET_CXX_GUARD_TYPE
276 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
278 #undef TARGET_CXX_GUARD_MASK_BIT
279 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
281 #undef TARGET_CXX_GET_COOKIE_SIZE
282 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
284 #undef TARGET_CXX_COOKIE_HAS_SIZE
285 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
287 struct gcc_target targetm = TARGET_INITIALIZER;
289 /* Obstack for minipool constant handling. */
290 static struct obstack minipool_obstack;
291 static char * minipool_startobj;
293 /* The maximum number of insns skipped which
294 will be conditionalised if possible. */
295 static int max_insns_skipped = 5;
297 extern FILE * asm_out_file;
299 /* True if we are currently building a constant table. */
300 int making_const_table;
302 /* Define the information needed to generate branch insns. This is
303 stored from the compare operation. */
304 rtx arm_compare_op0, arm_compare_op1;
306 /* The processor for which instructions should be scheduled. */
307 enum processor_type arm_tune = arm_none;
309 /* Which floating point model to use. */
310 enum arm_fp_model arm_fp_model;
312 /* Which floating point hardware is available. */
313 enum fputype arm_fpu_arch;
315 /* Which floating point hardware to schedule for. */
316 enum fputype arm_fpu_tune;
318 /* Whether to use floating point hardware. */
319 enum float_abi_type arm_float_abi;
321 /* Which ABI to use. */
322 enum arm_abi_type arm_abi;
324 /* Set by the -mfpu=... option. */
325 const char * target_fpu_name = NULL;
327 /* Set by the -mfpe=... option. */
328 const char * target_fpe_name = NULL;
330 /* Set by the -mfloat-abi=... option. */
331 const char * target_float_abi_name = NULL;
333 /* Set by the -mabi=... option. */
334 const char * target_abi_name = NULL;
336 /* Used to parse -mstructure_size_boundary command line option. */
337 const char * structure_size_string = NULL;
338 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
340 /* Bit values used to identify processor capabilities. */
341 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
342 #define FL_ARCH3M (1 << 1) /* Extended multiply */
343 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
344 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
345 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
346 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
347 #define FL_THUMB (1 << 6) /* Thumb aware */
348 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
349 #define FL_STRONG (1 << 8) /* StrongARM */
350 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
351 #define FL_XSCALE (1 << 10) /* XScale */
352 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
353 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
354 media instructions. */
355 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
357 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
359 #define FL_FOR_ARCH2 0
360 #define FL_FOR_ARCH3 FL_MODE32
361 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
362 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
363 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
364 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
365 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
366 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
367 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
368 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
369 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
370 #define FL_FOR_ARCH6J FL_FOR_ARCH6
372 /* The bits in this mask specify which
373 instructions we are allowed to generate. */
374 static unsigned long insn_flags = 0;
376 /* The bits in this mask specify which instruction scheduling options should
378 static unsigned long tune_flags = 0;
380 /* The following are used in the arm.md file as equivalents to bits
381 in the above two flag variables. */
383 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
386 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
389 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
392 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
395 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
398 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
401 /* Nonzero if this chip can benefit from load scheduling. */
402 int arm_ld_sched = 0;
404 /* Nonzero if this chip is a StrongARM. */
405 int arm_is_strong = 0;
407 /* Nonzero if this chip is a Cirrus variant. */
408 int arm_arch_cirrus = 0;
410 /* Nonzero if this chip supports Intel Wireless MMX technology. */
411 int arm_arch_iwmmxt = 0;
413 /* Nonzero if this chip is an XScale. */
414 int arm_arch_xscale = 0;
416 /* Nonzero if tuning for XScale */
417 int arm_tune_xscale = 0;
419 /* Nonzero if this chip is an ARM6 or an ARM7. */
420 int arm_is_6_or_7 = 0;
422 /* Nonzero if generating Thumb instructions. */
425 /* Nonzero if we should define __THUMB_INTERWORK__ in the
427 XXX This is a bit of a hack, it's intended to help work around
428 problems in GLD which doesn't understand that armv5t code is
429 interworking clean. */
430 int arm_cpp_interwork = 0;
432 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
433 must report the mode of the memory reference from PRINT_OPERAND to
434 PRINT_OPERAND_ADDRESS. */
435 enum machine_mode output_memory_reference_mode;
437 /* The register number to be used for the PIC offset register. */
438 const char * arm_pic_register_string = NULL;
439 int arm_pic_register = INVALID_REGNUM;
441 /* Set to 1 when a return insn is output, this means that the epilogue
443 int return_used_this_function;
445 /* Set to 1 after arm_reorg has started. Reset to start at the start of
446 the next function. */
447 static int after_arm_reorg = 0;
449 /* The maximum number of insns to be used when loading a constant. */
450 static int arm_constant_limit = 3;
452 /* For an explanation of these variables, see final_prescan_insn below. */
454 enum arm_cond_code arm_current_cc;
456 int arm_target_label;
458 /* The condition codes of the ARM, and the inverse function. */
459 static const char * const arm_condition_codes[] =
461 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
462 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
465 #define streq(string1, string2) (strcmp (string1, string2) == 0)
467 /* Initialization code. */
471 const char *const name;
472 enum processor_type core;
474 const unsigned long flags;
475 bool (* rtx_costs) (rtx, int, int, int *);
478 /* Not all of these give usefully different compilation alternatives,
479 but there is no simple way of generalizing them. */
480 static const struct processors all_cores[] =
483 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
484 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
485 #include "arm-cores.def"
487 {NULL, arm_none, NULL, 0, NULL}
490 static const struct processors all_architectures[] =
492 /* ARM Architectures */
493 /* We don't specify rtx_costs here as it will be figured out
496 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
497 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
498 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
499 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
500 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
501 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
502 implementations that support it, so we will leave it out for now. */
503 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
504 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
505 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
506 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
507 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
508 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
509 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
510 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
511 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
512 {NULL, arm_none, NULL, 0 , NULL}
515 /* This is a magic structure. The 'string' field is magically filled in
516 with a pointer to the value specified by the user on the command line
517 assuming that the user has specified such a value. */
519 struct arm_cpu_select arm_select[] =
521 /* string name processors */
522 { NULL, "-mcpu=", all_cores },
523 { NULL, "-march=", all_architectures },
524 { NULL, "-mtune=", all_cores }
528 /* The name of the proprocessor macro to define for this architecture. */
530 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
539 /* Available values for for -mfpu=. */
541 static const struct fpu_desc all_fpus[] =
543 {"fpa", FPUTYPE_FPA},
544 {"fpe2", FPUTYPE_FPA_EMU2},
545 {"fpe3", FPUTYPE_FPA_EMU2},
546 {"maverick", FPUTYPE_MAVERICK},
551 /* Floating point models used by the different hardware.
552 See fputype in arm.h. */
554 static const enum fputype fp_model_for_fpu[] =
556 /* No FP hardware. */
557 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
558 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
559 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
560 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
561 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
562 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
569 enum float_abi_type abi_type;
573 /* Available values for -mfloat-abi=. */
575 static const struct float_abi all_float_abis[] =
577 {"soft", ARM_FLOAT_ABI_SOFT},
578 {"softfp", ARM_FLOAT_ABI_SOFTFP},
579 {"hard", ARM_FLOAT_ABI_HARD}
586 enum arm_abi_type abi_type;
590 /* Available values for -mabi=. */
592 static const struct abi_name arm_all_abis[] =
594 {"apcs-gnu", ARM_ABI_APCS},
595 {"atpcs", ARM_ABI_ATPCS},
596 {"aapcs", ARM_ABI_AAPCS},
597 {"iwmmxt", ARM_ABI_IWMMXT}
600 /* Return the number of bits set in VALUE. */
602 bit_count (unsigned long value)
604 unsigned long count = 0;
609 value &= value - 1; /* Clear the least-significant set bit. */
615 /* Fix up any incompatible options that the user has specified.
616 This has now turned into a maze. */
618 arm_override_options (void)
622 /* Set up the flags based on the cpu/architecture selected by the user. */
623 for (i = ARRAY_SIZE (arm_select); i--;)
625 struct arm_cpu_select * ptr = arm_select + i;
627 if (ptr->string != NULL && ptr->string[0] != '\0')
629 const struct processors * sel;
631 for (sel = ptr->processors; sel->name != NULL; sel++)
632 if (streq (ptr->string, sel->name))
634 /* Set the architecture define. */
636 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
638 /* Determine the processor core for which we should
639 tune code-generation. */
640 if (/* -mcpu= is a sensible default. */
642 /* If -march= is used, and -mcpu= has not been used,
643 assume that we should tune for a representative
644 CPU from that architecture. */
646 /* -mtune= overrides -mcpu= and -march=. */
648 arm_tune = (enum processor_type) (sel - ptr->processors);
652 /* If we have been given an architecture and a processor
653 make sure that they are compatible. We only generate
654 a warning though, and we prefer the CPU over the
656 if (insn_flags != 0 && (insn_flags ^ sel->flags))
657 warning ("switch -mcpu=%s conflicts with -march= switch",
660 insn_flags = sel->flags;
666 if (sel->name == NULL)
667 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
671 /* If the user did not specify a processor, choose one for them. */
674 const struct processors * sel;
676 enum processor_type cpu;
678 cpu = TARGET_CPU_DEFAULT;
681 #ifdef SUBTARGET_CPU_DEFAULT
682 /* Use the subtarget default CPU if none was specified by
684 cpu = SUBTARGET_CPU_DEFAULT;
686 /* Default to ARM6. */
690 sel = &all_cores[cpu];
692 insn_flags = sel->flags;
694 /* Now check to see if the user has specified some command line
695 switch that require certain abilities from the cpu. */
698 if (TARGET_INTERWORK || TARGET_THUMB)
700 sought |= (FL_THUMB | FL_MODE32);
702 /* There are no ARM processors that support both APCS-26 and
703 interworking. Therefore we force FL_MODE26 to be removed
704 from insn_flags here (if it was set), so that the search
705 below will always be able to find a compatible processor. */
706 insn_flags &= ~FL_MODE26;
709 if (sought != 0 && ((sought & insn_flags) != sought))
711 /* Try to locate a CPU type that supports all of the abilities
712 of the default CPU, plus the extra abilities requested by
714 for (sel = all_cores; sel->name != NULL; sel++)
715 if ((sel->flags & sought) == (sought | insn_flags))
718 if (sel->name == NULL)
720 unsigned current_bit_count = 0;
721 const struct processors * best_fit = NULL;
723 /* Ideally we would like to issue an error message here
724 saying that it was not possible to find a CPU compatible
725 with the default CPU, but which also supports the command
726 line options specified by the programmer, and so they
727 ought to use the -mcpu=<name> command line option to
728 override the default CPU type.
730 If we cannot find a cpu that has both the
731 characteristics of the default cpu and the given
732 command line options we scan the array again looking
734 for (sel = all_cores; sel->name != NULL; sel++)
735 if ((sel->flags & sought) == sought)
739 count = bit_count (sel->flags & insn_flags);
741 if (count >= current_bit_count)
744 current_bit_count = count;
748 if (best_fit == NULL)
754 insn_flags = sel->flags;
756 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
757 if (arm_tune == arm_none)
758 arm_tune = (enum processor_type) (sel - all_cores);
761 /* The processor for which we should tune should now have been
763 if (arm_tune == arm_none)
766 tune_flags = all_cores[(int)arm_tune].flags;
767 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
769 /* Make sure that the processor choice does not conflict with any of the
770 other command line choices. */
771 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
773 warning ("target CPU does not support interworking" );
774 target_flags &= ~ARM_FLAG_INTERWORK;
777 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
779 warning ("target CPU does not support THUMB instructions");
780 target_flags &= ~ARM_FLAG_THUMB;
783 if (TARGET_APCS_FRAME && TARGET_THUMB)
785 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
786 target_flags &= ~ARM_FLAG_APCS_FRAME;
789 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
790 from here where no function is being compiled currently. */
791 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
793 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
795 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
796 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
798 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
799 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
801 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
803 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
804 target_flags |= ARM_FLAG_APCS_FRAME;
807 if (TARGET_POKE_FUNCTION_NAME)
808 target_flags |= ARM_FLAG_APCS_FRAME;
810 if (TARGET_APCS_REENT && flag_pic)
811 error ("-fpic and -mapcs-reent are incompatible");
813 if (TARGET_APCS_REENT)
814 warning ("APCS reentrant code not supported. Ignored");
816 /* If this target is normally configured to use APCS frames, warn if they
817 are turned off and debugging is turned on. */
819 && write_symbols != NO_DEBUG
820 && !TARGET_APCS_FRAME
821 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
822 warning ("-g with -mno-apcs-frame may not give sensible debugging");
824 /* If stack checking is disabled, we can use r10 as the PIC register,
825 which keeps r9 available. */
827 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
829 if (TARGET_APCS_FLOAT)
830 warning ("passing floating point arguments in fp regs not yet supported");
832 /* Initialize boolean versions of the flags, for use in the arm.md file. */
833 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
834 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
835 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
836 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
837 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
838 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
839 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
840 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
842 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
843 arm_is_strong = (tune_flags & FL_STRONG) != 0;
844 thumb_code = (TARGET_ARM == 0);
845 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
846 && !(tune_flags & FL_ARCH4))) != 0;
847 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
848 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
850 /* V5 code we generate is completely interworking capable, so we turn off
851 TARGET_INTERWORK here to avoid many tests later on. */
853 /* XXX However, we must pass the right pre-processor defines to CPP
854 or GLD can get confused. This is a hack. */
855 if (TARGET_INTERWORK)
856 arm_cpp_interwork = 1;
859 target_flags &= ~ARM_FLAG_INTERWORK;
863 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
865 if (streq (arm_all_abis[i].name, target_abi_name))
867 arm_abi = arm_all_abis[i].abi_type;
871 if (i == ARRAY_SIZE (arm_all_abis))
872 error ("invalid ABI option: -mabi=%s", target_abi_name);
875 arm_abi = ARM_DEFAULT_ABI;
877 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
878 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
880 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
881 error ("iwmmxt abi requires an iwmmxt capable cpu");
883 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
884 if (target_fpu_name == NULL && target_fpe_name != NULL)
886 if (streq (target_fpe_name, "2"))
887 target_fpu_name = "fpe2";
888 else if (streq (target_fpe_name, "3"))
889 target_fpu_name = "fpe3";
891 error ("invalid floating point emulation option: -mfpe=%s",
894 if (target_fpu_name != NULL)
896 /* The user specified a FPU. */
897 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
899 if (streq (all_fpus[i].name, target_fpu_name))
901 arm_fpu_arch = all_fpus[i].fpu;
902 arm_fpu_tune = arm_fpu_arch;
903 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
907 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
908 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
912 #ifdef FPUTYPE_DEFAULT
913 /* Use the default if it is specified for this platform. */
914 arm_fpu_arch = FPUTYPE_DEFAULT;
915 arm_fpu_tune = FPUTYPE_DEFAULT;
917 /* Pick one based on CPU type. */
918 /* ??? Some targets assume FPA is the default.
919 if ((insn_flags & FL_VFP) != 0)
920 arm_fpu_arch = FPUTYPE_VFP;
924 arm_fpu_arch = FPUTYPE_MAVERICK;
926 arm_fpu_arch = FPUTYPE_FPA_EMU2;
928 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
929 arm_fpu_tune = FPUTYPE_FPA;
931 arm_fpu_tune = arm_fpu_arch;
932 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
933 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
937 if (target_float_abi_name != NULL)
939 /* The user specified a FP ABI. */
940 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
942 if (streq (all_float_abis[i].name, target_float_abi_name))
944 arm_float_abi = all_float_abis[i].abi_type;
948 if (i == ARRAY_SIZE (all_float_abis))
949 error ("invalid floating point abi: -mfloat-abi=%s",
950 target_float_abi_name);
954 /* Use soft-float target flag. */
955 if (target_flags & ARM_FLAG_SOFT_FLOAT)
956 arm_float_abi = ARM_FLOAT_ABI_SOFT;
958 arm_float_abi = ARM_FLOAT_ABI_HARD;
961 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
962 sorry ("-mfloat-abi=softfp");
963 /* If soft-float is specified then don't use FPU. */
964 if (TARGET_SOFT_FLOAT)
965 arm_fpu_arch = FPUTYPE_NONE;
967 /* For arm2/3 there is no need to do any scheduling if there is only
968 a floating point emulator, or we are doing software floating-point. */
969 if ((TARGET_SOFT_FLOAT
970 || arm_fpu_tune == FPUTYPE_FPA_EMU2
971 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
972 && (tune_flags & FL_MODE32) == 0)
973 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
975 /* Override the default structure alignment for AAPCS ABI. */
976 if (arm_abi == ARM_ABI_AAPCS)
977 arm_structure_size_boundary = 8;
979 if (structure_size_string != NULL)
981 int size = strtol (structure_size_string, NULL, 0);
983 if (size == 8 || size == 32
984 || (ARM_DOUBLEWORD_ALIGN && size == 64))
985 arm_structure_size_boundary = size;
987 warning ("structure size boundary can only be set to %s",
988 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
991 if (arm_pic_register_string != NULL)
993 int pic_register = decode_reg_name (arm_pic_register_string);
996 warning ("-mpic-register= is useless without -fpic");
998 /* Prevent the user from choosing an obviously stupid PIC register. */
999 else if (pic_register < 0 || call_used_regs[pic_register]
1000 || pic_register == HARD_FRAME_POINTER_REGNUM
1001 || pic_register == STACK_POINTER_REGNUM
1002 || pic_register >= PC_REGNUM)
1003 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1005 arm_pic_register = pic_register;
1008 if (TARGET_THUMB && flag_schedule_insns)
1010 /* Don't warn since it's on by default in -O2. */
1011 flag_schedule_insns = 0;
1016 /* There's some dispute as to whether this should be 1 or 2. However,
1017 experiments seem to show that in pathological cases a setting of
1018 1 degrades less severely than a setting of 2. This could change if
1019 other parts of the compiler change their behavior. */
1020 arm_constant_limit = 1;
1022 /* If optimizing for size, bump the number of instructions that we
1023 are prepared to conditionally execute (even on a StrongARM). */
1024 max_insns_skipped = 6;
1028 /* For processors with load scheduling, it never costs more than
1029 2 cycles to load a constant, and the load scheduler may well
1030 reduce that to 1. */
1031 if (tune_flags & FL_LDSCHED)
1032 arm_constant_limit = 1;
1034 /* On XScale the longer latency of a load makes it more difficult
1035 to achieve a good schedule, so it's faster to synthesize
1036 constants that can be done in two insns. */
1037 if (arm_tune_xscale)
1038 arm_constant_limit = 2;
1040 /* StrongARM has early execution of branches, so a sequence
1041 that is worth skipping is shorter. */
1043 max_insns_skipped = 3;
1046 /* Register global variables with the garbage collector. */
1047 arm_add_gc_roots ();
1051 arm_add_gc_roots (void)
1053 gcc_obstack_init(&minipool_obstack);
1054 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1057 /* A table of known ARM exception types.
1058 For use with the interrupt function attribute. */
1062 const char *const arg;
1063 const unsigned long return_value;
1067 static const isr_attribute_arg isr_attribute_args [] =
1069 { "IRQ", ARM_FT_ISR },
1070 { "irq", ARM_FT_ISR },
1071 { "FIQ", ARM_FT_FIQ },
1072 { "fiq", ARM_FT_FIQ },
1073 { "ABORT", ARM_FT_ISR },
1074 { "abort", ARM_FT_ISR },
1075 { "ABORT", ARM_FT_ISR },
1076 { "abort", ARM_FT_ISR },
1077 { "UNDEF", ARM_FT_EXCEPTION },
1078 { "undef", ARM_FT_EXCEPTION },
1079 { "SWI", ARM_FT_EXCEPTION },
1080 { "swi", ARM_FT_EXCEPTION },
1081 { NULL, ARM_FT_NORMAL }
1084 /* Returns the (interrupt) function type of the current
1085 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1087 static unsigned long
1088 arm_isr_value (tree argument)
1090 const isr_attribute_arg * ptr;
1093 /* No argument - default to IRQ. */
1094 if (argument == NULL_TREE)
1097 /* Get the value of the argument. */
1098 if (TREE_VALUE (argument) == NULL_TREE
1099 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1100 return ARM_FT_UNKNOWN;
1102 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1104 /* Check it against the list of known arguments. */
1105 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1106 if (streq (arg, ptr->arg))
1107 return ptr->return_value;
1109 /* An unrecognized interrupt type. */
1110 return ARM_FT_UNKNOWN;
1113 /* Computes the type of the current function. */
1115 static unsigned long
1116 arm_compute_func_type (void)
1118 unsigned long type = ARM_FT_UNKNOWN;
1122 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1125 /* Decide if the current function is volatile. Such functions
1126 never return, and many memory cycles can be saved by not storing
1127 register values that will never be needed again. This optimization
1128 was added to speed up context switching in a kernel application. */
1130 && TREE_NOTHROW (current_function_decl)
1131 && TREE_THIS_VOLATILE (current_function_decl))
1132 type |= ARM_FT_VOLATILE;
1134 if (cfun->static_chain_decl != NULL)
1135 type |= ARM_FT_NESTED;
1137 attr = DECL_ATTRIBUTES (current_function_decl);
1139 a = lookup_attribute ("naked", attr);
1141 type |= ARM_FT_NAKED;
1143 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1144 type |= ARM_FT_EXCEPTION_HANDLER;
1147 a = lookup_attribute ("isr", attr);
1149 a = lookup_attribute ("interrupt", attr);
1152 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1154 type |= arm_isr_value (TREE_VALUE (a));
1160 /* Returns the type of the current function. */
1163 arm_current_func_type (void)
1165 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1166 cfun->machine->func_type = arm_compute_func_type ();
1168 return cfun->machine->func_type;
1171 /* Return 1 if it is possible to return using a single instruction.
1172 If SIBLING is non-null, this is a test for a return before a sibling
1173 call. SIBLING is the call insn, so we can examine its register usage. */
1176 use_return_insn (int iscond, rtx sibling)
1179 unsigned int func_type;
1180 unsigned long saved_int_regs;
1181 unsigned HOST_WIDE_INT stack_adjust;
1182 arm_stack_offsets *offsets;
1184 /* Never use a return instruction before reload has run. */
1185 if (!reload_completed)
1188 func_type = arm_current_func_type ();
1190 /* Naked functions and volatile functions need special
1192 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1195 /* So do interrupt functions that use the frame pointer. */
1196 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1199 offsets = arm_get_frame_offsets ();
1200 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1202 /* As do variadic functions. */
1203 if (current_function_pretend_args_size
1204 || cfun->machine->uses_anonymous_args
1205 /* Or if the function calls __builtin_eh_return () */
1206 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1207 /* Or if the function calls alloca */
1208 || current_function_calls_alloca
1209 /* Or if there is a stack adjustment. However, if the stack pointer
1210 is saved on the stack, we can use a pre-incrementing stack load. */
1211 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1214 saved_int_regs = arm_compute_save_reg_mask ();
1216 /* Unfortunately, the insn
1218 ldmib sp, {..., sp, ...}
1220 triggers a bug on most SA-110 based devices, such that the stack
1221 pointer won't be correctly restored if the instruction takes a
1222 page fault. We work around this problem by popping r3 along with
1223 the other registers, since that is never slower than executing
1224 another instruction.
1226 We test for !arm_arch5 here, because code for any architecture
1227 less than this could potentially be run on one of the buggy
1229 if (stack_adjust == 4 && !arm_arch5)
1231 /* Validate that r3 is a call-clobbered register (always true in
1232 the default abi) ... */
1233 if (!call_used_regs[3])
1236 /* ... that it isn't being used for a return value (always true
1237 until we implement return-in-regs), or for a tail-call
1241 if (GET_CODE (sibling) != CALL_INSN)
1244 if (find_regno_fusage (sibling, USE, 3))
1248 /* ... and that there are no call-saved registers in r0-r2
1249 (always true in the default ABI). */
1250 if (saved_int_regs & 0x7)
1254 /* Can't be done if interworking with Thumb, and any registers have been
1256 if (TARGET_INTERWORK && saved_int_regs != 0)
1259 /* On StrongARM, conditional returns are expensive if they aren't
1260 taken and multiple registers have been stacked. */
1261 if (iscond && arm_is_strong)
1263 /* Conditional return when just the LR is stored is a simple
1264 conditional-load instruction, that's not expensive. */
1265 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1268 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1272 /* If there are saved registers but the LR isn't saved, then we need
1273 two instructions for the return. */
1274 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1277 /* Can't be done if any of the FPA regs are pushed,
1278 since this also requires an insn. */
1279 if (TARGET_HARD_FLOAT && TARGET_FPA)
1280 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1281 if (regs_ever_live[regno] && !call_used_regs[regno])
1284 /* Likewise VFP regs. */
1285 if (TARGET_HARD_FLOAT && TARGET_VFP)
1286 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1287 if (regs_ever_live[regno] && !call_used_regs[regno])
1290 if (TARGET_REALLY_IWMMXT)
1291 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1292 if (regs_ever_live[regno] && ! call_used_regs [regno])
1298 /* Return TRUE if int I is a valid immediate ARM constant. */
1301 const_ok_for_arm (HOST_WIDE_INT i)
1303 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1305 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1306 be all zero, or all one. */
1307 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1308 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1309 != ((~(unsigned HOST_WIDE_INT) 0)
1310 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1313 /* Fast return for 0 and powers of 2 */
1314 if ((i & (i - 1)) == 0)
1319 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1322 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1323 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1325 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1330 /* Return true if I is a valid constant for the operation CODE. */
1332 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1334 if (const_ok_for_arm (i))
1340 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1342 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1348 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1355 /* Emit a sequence of insns to handle a large constant.
1356 CODE is the code of the operation required, it can be any of SET, PLUS,
1357 IOR, AND, XOR, MINUS;
1358 MODE is the mode in which the operation is being performed;
1359 VAL is the integer to operate on;
1360 SOURCE is the other operand (a register, or a null-pointer for SET);
1361 SUBTARGETS means it is safe to create scratch registers if that will
1362 either produce a simpler sequence, or we will want to cse the values.
1363 Return value is the number of insns emitted. */
1366 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1367 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1371 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1372 cond = COND_EXEC_TEST (PATTERN (insn));
1376 if (subtargets || code == SET
1377 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1378 && REGNO (target) != REGNO (source)))
1380 /* After arm_reorg has been called, we can't fix up expensive
1381 constants by pushing them into memory so we must synthesize
1382 them in-line, regardless of the cost. This is only likely to
1383 be more costly on chips that have load delay slots and we are
1384 compiling without running the scheduler (so no splitting
1385 occurred before the final instruction emission).
1387 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1389 if (!after_arm_reorg
1391 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1393 > arm_constant_limit + (code != SET)))
1397 /* Currently SET is the only monadic value for CODE, all
1398 the rest are diadic. */
1399 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1404 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1406 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1407 /* For MINUS, the value is subtracted from, since we never
1408 have subtraction of a constant. */
1410 emit_insn (gen_rtx_SET (VOIDmode, target,
1411 gen_rtx_MINUS (mode, temp, source)));
1413 emit_insn (gen_rtx_SET (VOIDmode, target,
1414 gen_rtx_fmt_ee (code, mode, source, temp)));
1420 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1425 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1427 HOST_WIDE_INT temp1;
1435 if (remainder & (3 << (i - 2)))
1440 temp1 = remainder & ((0x0ff << end)
1441 | ((i < end) ? (0xff >> (32 - end)) : 0));
1442 remainder &= ~temp1;
1447 } while (remainder);
1451 /* Emit an instruction with the indicated PATTERN. If COND is
1452 non-NULL, conditionalize the execution of the instruction on COND
1456 emit_constant_insn (rtx cond, rtx pattern)
1459 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1460 emit_insn (pattern);
1463 /* As above, but extra parameter GENERATE which, if clear, suppresses
1467 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1468 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1473 int can_negate_initial = 0;
1476 int num_bits_set = 0;
1477 int set_sign_bit_copies = 0;
1478 int clear_sign_bit_copies = 0;
1479 int clear_zero_bit_copies = 0;
1480 int set_zero_bit_copies = 0;
1482 unsigned HOST_WIDE_INT temp1, temp2;
1483 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1485 /* Find out which operations are safe for a given CODE. Also do a quick
1486 check for degenerate cases; these can occur when DImode operations
1498 can_negate_initial = 1;
1502 if (remainder == 0xffffffff)
1505 emit_constant_insn (cond,
1506 gen_rtx_SET (VOIDmode, target,
1507 GEN_INT (ARM_SIGN_EXTEND (val))));
1512 if (reload_completed && rtx_equal_p (target, source))
1515 emit_constant_insn (cond,
1516 gen_rtx_SET (VOIDmode, target, source));
1525 emit_constant_insn (cond,
1526 gen_rtx_SET (VOIDmode, target, const0_rtx));
1529 if (remainder == 0xffffffff)
1531 if (reload_completed && rtx_equal_p (target, source))
1534 emit_constant_insn (cond,
1535 gen_rtx_SET (VOIDmode, target, source));
1544 if (reload_completed && rtx_equal_p (target, source))
1547 emit_constant_insn (cond,
1548 gen_rtx_SET (VOIDmode, target, source));
1551 if (remainder == 0xffffffff)
1554 emit_constant_insn (cond,
1555 gen_rtx_SET (VOIDmode, target,
1556 gen_rtx_NOT (mode, source)));
1560 /* We don't know how to handle this yet below. */
1564 /* We treat MINUS as (val - source), since (source - val) is always
1565 passed as (source + (-val)). */
1569 emit_constant_insn (cond,
1570 gen_rtx_SET (VOIDmode, target,
1571 gen_rtx_NEG (mode, source)));
1574 if (const_ok_for_arm (val))
1577 emit_constant_insn (cond,
1578 gen_rtx_SET (VOIDmode, target,
1579 gen_rtx_MINUS (mode, GEN_INT (val),
1591 /* If we can do it in one insn get out quickly. */
1592 if (const_ok_for_arm (val)
1593 || (can_negate_initial && const_ok_for_arm (-val))
1594 || (can_invert && const_ok_for_arm (~val)))
1597 emit_constant_insn (cond,
1598 gen_rtx_SET (VOIDmode, target,
1600 ? gen_rtx_fmt_ee (code, mode, source,
1606 /* Calculate a few attributes that may be useful for specific
1608 for (i = 31; i >= 0; i--)
1610 if ((remainder & (1 << i)) == 0)
1611 clear_sign_bit_copies++;
1616 for (i = 31; i >= 0; i--)
1618 if ((remainder & (1 << i)) != 0)
1619 set_sign_bit_copies++;
1624 for (i = 0; i <= 31; i++)
1626 if ((remainder & (1 << i)) == 0)
1627 clear_zero_bit_copies++;
1632 for (i = 0; i <= 31; i++)
1634 if ((remainder & (1 << i)) != 0)
1635 set_zero_bit_copies++;
1643 /* See if we can do this by sign_extending a constant that is known
1644 to be negative. This is a good, way of doing it, since the shift
1645 may well merge into a subsequent insn. */
1646 if (set_sign_bit_copies > 1)
1648 if (const_ok_for_arm
1649 (temp1 = ARM_SIGN_EXTEND (remainder
1650 << (set_sign_bit_copies - 1))))
1654 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1655 emit_constant_insn (cond,
1656 gen_rtx_SET (VOIDmode, new_src,
1658 emit_constant_insn (cond,
1659 gen_ashrsi3 (target, new_src,
1660 GEN_INT (set_sign_bit_copies - 1)));
1664 /* For an inverted constant, we will need to set the low bits,
1665 these will be shifted out of harm's way. */
1666 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1667 if (const_ok_for_arm (~temp1))
1671 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1672 emit_constant_insn (cond,
1673 gen_rtx_SET (VOIDmode, new_src,
1675 emit_constant_insn (cond,
1676 gen_ashrsi3 (target, new_src,
1677 GEN_INT (set_sign_bit_copies - 1)));
1683 /* See if we can generate this by setting the bottom (or the top)
1684 16 bits, and then shifting these into the other half of the
1685 word. We only look for the simplest cases, to do more would cost
1686 too much. Be careful, however, not to generate this when the
1687 alternative would take fewer insns. */
1688 if (val & 0xffff0000)
1690 temp1 = remainder & 0xffff0000;
1691 temp2 = remainder & 0x0000ffff;
1693 /* Overlaps outside this range are best done using other methods. */
1694 for (i = 9; i < 24; i++)
1696 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1697 && !const_ok_for_arm (temp2))
1699 rtx new_src = (subtargets
1700 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1702 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1703 source, subtargets, generate);
1711 gen_rtx_ASHIFT (mode, source,
1718 /* Don't duplicate cases already considered. */
1719 for (i = 17; i < 24; i++)
1721 if (((temp1 | (temp1 >> i)) == remainder)
1722 && !const_ok_for_arm (temp1))
1724 rtx new_src = (subtargets
1725 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1727 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1728 source, subtargets, generate);
1733 gen_rtx_SET (VOIDmode, target,
1736 gen_rtx_LSHIFTRT (mode, source,
1747 /* If we have IOR or XOR, and the constant can be loaded in a
1748 single instruction, and we can find a temporary to put it in,
1749 then this can be done in two instructions instead of 3-4. */
1751 /* TARGET can't be NULL if SUBTARGETS is 0 */
1752 || (reload_completed && !reg_mentioned_p (target, source)))
1754 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1758 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1760 emit_constant_insn (cond,
1761 gen_rtx_SET (VOIDmode, sub,
1763 emit_constant_insn (cond,
1764 gen_rtx_SET (VOIDmode, target,
1765 gen_rtx_fmt_ee (code, mode,
1775 if (set_sign_bit_copies > 8
1776 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1780 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1781 rtx shift = GEN_INT (set_sign_bit_copies);
1785 gen_rtx_SET (VOIDmode, sub,
1787 gen_rtx_ASHIFT (mode,
1792 gen_rtx_SET (VOIDmode, target,
1794 gen_rtx_LSHIFTRT (mode, sub,
1800 if (set_zero_bit_copies > 8
1801 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1805 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1806 rtx shift = GEN_INT (set_zero_bit_copies);
1810 gen_rtx_SET (VOIDmode, sub,
1812 gen_rtx_LSHIFTRT (mode,
1817 gen_rtx_SET (VOIDmode, target,
1819 gen_rtx_ASHIFT (mode, sub,
1825 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1829 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1830 emit_constant_insn (cond,
1831 gen_rtx_SET (VOIDmode, sub,
1832 gen_rtx_NOT (mode, source)));
1835 sub = gen_reg_rtx (mode);
1836 emit_constant_insn (cond,
1837 gen_rtx_SET (VOIDmode, sub,
1838 gen_rtx_AND (mode, source,
1840 emit_constant_insn (cond,
1841 gen_rtx_SET (VOIDmode, target,
1842 gen_rtx_NOT (mode, sub)));
1849 /* See if two shifts will do 2 or more insn's worth of work. */
1850 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1852 HOST_WIDE_INT shift_mask = ((0xffffffff
1853 << (32 - clear_sign_bit_copies))
1856 if ((remainder | shift_mask) != 0xffffffff)
1860 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1861 insns = arm_gen_constant (AND, mode, cond,
1862 remainder | shift_mask,
1863 new_src, source, subtargets, 1);
1868 rtx targ = subtargets ? NULL_RTX : target;
1869 insns = arm_gen_constant (AND, mode, cond,
1870 remainder | shift_mask,
1871 targ, source, subtargets, 0);
1877 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1878 rtx shift = GEN_INT (clear_sign_bit_copies);
1880 emit_insn (gen_ashlsi3 (new_src, source, shift));
1881 emit_insn (gen_lshrsi3 (target, new_src, shift));
1887 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1889 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1891 if ((remainder | shift_mask) != 0xffffffff)
1895 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1897 insns = arm_gen_constant (AND, mode, cond,
1898 remainder | shift_mask,
1899 new_src, source, subtargets, 1);
1904 rtx targ = subtargets ? NULL_RTX : target;
1906 insns = arm_gen_constant (AND, mode, cond,
1907 remainder | shift_mask,
1908 targ, source, subtargets, 0);
1914 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1915 rtx shift = GEN_INT (clear_zero_bit_copies);
1917 emit_insn (gen_lshrsi3 (new_src, source, shift));
1918 emit_insn (gen_ashlsi3 (target, new_src, shift));
1930 for (i = 0; i < 32; i++)
1931 if (remainder & (1 << i))
1934 if (code == AND || (can_invert && num_bits_set > 16))
1935 remainder = (~remainder) & 0xffffffff;
1936 else if (code == PLUS && num_bits_set > 16)
1937 remainder = (-remainder) & 0xffffffff;
1944 /* Now try and find a way of doing the job in either two or three
1946 We start by looking for the largest block of zeros that are aligned on
1947 a 2-bit boundary, we then fill up the temps, wrapping around to the
1948 top of the word when we drop off the bottom.
1949 In the worst case this code should produce no more than four insns. */
1952 int best_consecutive_zeros = 0;
1954 for (i = 0; i < 32; i += 2)
1956 int consecutive_zeros = 0;
1958 if (!(remainder & (3 << i)))
1960 while ((i < 32) && !(remainder & (3 << i)))
1962 consecutive_zeros += 2;
1965 if (consecutive_zeros > best_consecutive_zeros)
1967 best_consecutive_zeros = consecutive_zeros;
1968 best_start = i - consecutive_zeros;
1974 /* So long as it won't require any more insns to do so, it's
1975 desirable to emit a small constant (in bits 0...9) in the last
1976 insn. This way there is more chance that it can be combined with
1977 a later addressing insn to form a pre-indexed load or store
1978 operation. Consider:
1980 *((volatile int *)0xe0000100) = 1;
1981 *((volatile int *)0xe0000110) = 2;
1983 We want this to wind up as:
1987 str rB, [rA, #0x100]
1989 str rB, [rA, #0x110]
1991 rather than having to synthesize both large constants from scratch.
1993 Therefore, we calculate how many insns would be required to emit
1994 the constant starting from `best_start', and also starting from
1995 zero (ie with bit 31 first to be output). If `best_start' doesn't
1996 yield a shorter sequence, we may as well use zero. */
1998 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1999 && (count_insns_for_constant (remainder, 0) <=
2000 count_insns_for_constant (remainder, best_start)))
2003 /* Now start emitting the insns. */
2011 if (remainder & (3 << (i - 2)))
2016 temp1 = remainder & ((0x0ff << end)
2017 | ((i < end) ? (0xff >> (32 - end)) : 0));
2018 remainder &= ~temp1;
2022 rtx new_src, temp1_rtx;
2024 if (code == SET || code == MINUS)
2026 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2027 if (can_invert && code != MINUS)
2032 if (remainder && subtargets)
2033 new_src = gen_reg_rtx (mode);
2038 else if (can_negate)
2042 temp1 = trunc_int_for_mode (temp1, mode);
2043 temp1_rtx = GEN_INT (temp1);
2047 else if (code == MINUS)
2048 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2050 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2052 emit_constant_insn (cond,
2053 gen_rtx_SET (VOIDmode, new_src,
2063 else if (code == MINUS)
2077 /* Canonicalize a comparison so that we are more likely to recognize it.
2078 This can be done for a few constant compares, where we can make the
2079 immediate value easier to load. */
2082 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2084 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2094 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2095 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2097 *op1 = GEN_INT (i + 1);
2098 return code == GT ? GE : LT;
2104 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2105 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2107 *op1 = GEN_INT (i - 1);
2108 return code == GE ? GT : LE;
2114 if (i != ~((unsigned HOST_WIDE_INT) 0)
2115 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2117 *op1 = GEN_INT (i + 1);
2118 return code == GTU ? GEU : LTU;
2125 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2127 *op1 = GEN_INT (i - 1);
2128 return code == GEU ? GTU : LEU;
2140 /* Define how to find the value returned by a function. */
2142 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2144 enum machine_mode mode;
2145 int unsignedp ATTRIBUTE_UNUSED;
2146 rtx r ATTRIBUTE_UNUSED;
2149 mode = TYPE_MODE (type);
2150 /* Promote integer types. */
2151 if (INTEGRAL_TYPE_P (type))
2152 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2153 return LIBCALL_VALUE(mode);
2157 /* Decide whether a type should be returned in memory (true)
2158 or in a register (false). This is called by the macro
2159 RETURN_IN_MEMORY. */
2161 arm_return_in_memory (tree type)
2165 if (!AGGREGATE_TYPE_P (type))
2166 /* All simple types are returned in registers. */
2169 size = int_size_in_bytes (type);
2171 if (arm_abi != ARM_ABI_APCS)
2173 /* ATPCS and later return aggregate types in memory only if they are
2174 larger than a word (or are variable size). */
2175 return (size < 0 || size > UNITS_PER_WORD);
2178 /* For the arm-wince targets we choose to be compatible with Microsoft's
2179 ARM and Thumb compilers, which always return aggregates in memory. */
2181 /* All structures/unions bigger than one word are returned in memory.
2182 Also catch the case where int_size_in_bytes returns -1. In this case
2183 the aggregate is either huge or of variable size, and in either case
2184 we will want to return it via memory and not in a register. */
2185 if (size < 0 || size > UNITS_PER_WORD)
2188 if (TREE_CODE (type) == RECORD_TYPE)
2192 /* For a struct the APCS says that we only return in a register
2193 if the type is 'integer like' and every addressable element
2194 has an offset of zero. For practical purposes this means
2195 that the structure can have at most one non bit-field element
2196 and that this element must be the first one in the structure. */
2198 /* Find the first field, ignoring non FIELD_DECL things which will
2199 have been created by C++. */
2200 for (field = TYPE_FIELDS (type);
2201 field && TREE_CODE (field) != FIELD_DECL;
2202 field = TREE_CHAIN (field))
2206 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2208 /* Check that the first field is valid for returning in a register. */
2210 /* ... Floats are not allowed */
2211 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2214 /* ... Aggregates that are not themselves valid for returning in
2215 a register are not allowed. */
2216 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2219 /* Now check the remaining fields, if any. Only bitfields are allowed,
2220 since they are not addressable. */
2221 for (field = TREE_CHAIN (field);
2223 field = TREE_CHAIN (field))
2225 if (TREE_CODE (field) != FIELD_DECL)
2228 if (!DECL_BIT_FIELD_TYPE (field))
2235 if (TREE_CODE (type) == UNION_TYPE)
2239 /* Unions can be returned in registers if every element is
2240 integral, or can be returned in an integer register. */
2241 for (field = TYPE_FIELDS (type);
2243 field = TREE_CHAIN (field))
2245 if (TREE_CODE (field) != FIELD_DECL)
2248 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2251 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2257 #endif /* not ARM_WINCE */
2259 /* Return all other types in memory. */
2263 /* Indicate whether or not words of a double are in big-endian order. */
2266 arm_float_words_big_endian (void)
2268 if (TARGET_MAVERICK)
2271 /* For FPA, float words are always big-endian. For VFP, floats words
2272 follow the memory system mode. */
2280 return (TARGET_BIG_END ? 1 : 0);
2285 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2286 for a call to a function whose data type is FNTYPE.
2287 For a library call, FNTYPE is NULL. */
2289 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2290 rtx libname ATTRIBUTE_UNUSED,
2291 tree fndecl ATTRIBUTE_UNUSED)
2293 /* On the ARM, the offset starts at 0. */
2294 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2295 pcum->iwmmxt_nregs = 0;
2296 pcum->can_split = true;
2298 pcum->call_cookie = CALL_NORMAL;
2300 if (TARGET_LONG_CALLS)
2301 pcum->call_cookie = CALL_LONG;
2303 /* Check for long call/short call attributes. The attributes
2304 override any command line option. */
2307 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2308 pcum->call_cookie = CALL_SHORT;
2309 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2310 pcum->call_cookie = CALL_LONG;
2313 /* Varargs vectors are treated the same as long long.
2314 named_count avoids having to change the way arm handles 'named' */
2315 pcum->named_count = 0;
2318 if (TARGET_REALLY_IWMMXT && fntype)
2322 for (fn_arg = TYPE_ARG_TYPES (fntype);
2324 fn_arg = TREE_CHAIN (fn_arg))
2325 pcum->named_count += 1;
2327 if (! pcum->named_count)
2328 pcum->named_count = INT_MAX;
2333 /* Return true if mode/type need doubleword alignment. */
2335 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2337 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2338 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2342 /* Determine where to put an argument to a function.
2343 Value is zero to push the argument on the stack,
2344 or a hard register in which to store the argument.
2346 MODE is the argument's machine mode.
2347 TYPE is the data type of the argument (as a tree).
2348 This is null for libcalls where that information may
2350 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2351 the preceding args and about the function being called.
2352 NAMED is nonzero if this argument is a named parameter
2353 (otherwise it is an extra parameter matching an ellipsis). */
2356 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2357 tree type, int named)
2361 /* Varargs vectors are treated the same as long long.
2362 named_count avoids having to change the way arm handles 'named' */
2363 if (TARGET_IWMMXT_ABI
2364 && VECTOR_MODE_SUPPORTED_P (mode)
2365 && pcum->named_count > pcum->nargs + 1)
2367 if (pcum->iwmmxt_nregs <= 9)
2368 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2371 pcum->can_split = false;
2376 /* Put doubleword aligned quantities in even register pairs. */
2378 && ARM_DOUBLEWORD_ALIGN
2379 && arm_needs_doubleword_align (mode, type))
2382 if (mode == VOIDmode)
2383 /* Compute operand 2 of the call insn. */
2384 return GEN_INT (pcum->call_cookie);
2386 /* Only allow splitting an arg between regs and memory if all preceding
2387 args were allocated to regs. For args passed by reference we only count
2388 the reference pointer. */
2389 if (pcum->can_split)
2392 nregs = ARM_NUM_REGS2 (mode, type);
2394 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2397 return gen_rtx_REG (mode, pcum->nregs);
2400 /* Variable sized types are passed by reference. This is a GCC
2401 extension to the ARM ABI. */
2404 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2405 enum machine_mode mode ATTRIBUTE_UNUSED,
2406 tree type, bool named ATTRIBUTE_UNUSED)
2408 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2411 /* Implement va_arg. */
2414 arm_va_arg (tree valist, tree type)
2418 /* Variable sized types are passed by reference. */
2419 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2421 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2422 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2425 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2426 if (align > PARM_BOUNDARY)
2431 /* Maintain 64-bit alignment of the valist pointer by
2432 constructing: valist = ((valist + (8 - 1)) & -8). */
2433 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2434 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2435 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2436 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2437 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2438 TREE_SIDE_EFFECTS (t) = 1;
2439 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2441 /* This is to stop the combine pass optimizing
2442 away the alignment adjustment. */
2443 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2446 return std_expand_builtin_va_arg (valist, type);
2449 /* Encode the current state of the #pragma [no_]long_calls. */
2452 OFF, /* No #pramgma [no_]long_calls is in effect. */
2453 LONG, /* #pragma long_calls is in effect. */
2454 SHORT /* #pragma no_long_calls is in effect. */
2457 static arm_pragma_enum arm_pragma_long_calls = OFF;
2460 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2462 arm_pragma_long_calls = LONG;
2466 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2468 arm_pragma_long_calls = SHORT;
2472 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2474 arm_pragma_long_calls = OFF;
2477 /* Table of machine attributes. */
2478 const struct attribute_spec arm_attribute_table[] =
2480 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2481 /* Function calls made to this symbol must be done indirectly, because
2482 it may lie outside of the 26 bit addressing range of a normal function
2484 { "long_call", 0, 0, false, true, true, NULL },
2485 /* Whereas these functions are always known to reside within the 26 bit
2486 addressing range. */
2487 { "short_call", 0, 0, false, true, true, NULL },
2488 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2489 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2490 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2491 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2493 /* ARM/PE has three new attributes:
2495 dllexport - for exporting a function/variable that will live in a dll
2496 dllimport - for importing a function/variable from a dll
2498 Microsoft allows multiple declspecs in one __declspec, separating
2499 them with spaces. We do NOT support this. Instead, use __declspec
2502 { "dllimport", 0, 0, true, false, false, NULL },
2503 { "dllexport", 0, 0, true, false, false, NULL },
2504 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2506 { NULL, 0, 0, false, false, false, NULL }
2509 /* Handle an attribute requiring a FUNCTION_DECL;
2510 arguments as in struct attribute_spec.handler. */
2512 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2513 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2515 if (TREE_CODE (*node) != FUNCTION_DECL)
2517 warning ("`%s' attribute only applies to functions",
2518 IDENTIFIER_POINTER (name));
2519 *no_add_attrs = true;
2525 /* Handle an "interrupt" or "isr" attribute;
2526 arguments as in struct attribute_spec.handler. */
2528 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2533 if (TREE_CODE (*node) != FUNCTION_DECL)
2535 warning ("`%s' attribute only applies to functions",
2536 IDENTIFIER_POINTER (name));
2537 *no_add_attrs = true;
2539 /* FIXME: the argument if any is checked for type attributes;
2540 should it be checked for decl ones? */
2544 if (TREE_CODE (*node) == FUNCTION_TYPE
2545 || TREE_CODE (*node) == METHOD_TYPE)
2547 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2549 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2550 *no_add_attrs = true;
2553 else if (TREE_CODE (*node) == POINTER_TYPE
2554 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2555 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2556 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2558 *node = build_type_copy (*node);
2559 TREE_TYPE (*node) = build_type_attribute_variant
2561 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2562 *no_add_attrs = true;
2566 /* Possibly pass this attribute on from the type to a decl. */
2567 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2568 | (int) ATTR_FLAG_FUNCTION_NEXT
2569 | (int) ATTR_FLAG_ARRAY_NEXT))
2571 *no_add_attrs = true;
2572 return tree_cons (name, args, NULL_TREE);
2576 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2584 /* Return 0 if the attributes for two types are incompatible, 1 if they
2585 are compatible, and 2 if they are nearly compatible (which causes a
2586 warning to be generated). */
2588 arm_comp_type_attributes (tree type1, tree type2)
2592 /* Check for mismatch of non-default calling convention. */
2593 if (TREE_CODE (type1) != FUNCTION_TYPE)
2596 /* Check for mismatched call attributes. */
2597 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2598 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2599 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2600 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2602 /* Only bother to check if an attribute is defined. */
2603 if (l1 | l2 | s1 | s2)
2605 /* If one type has an attribute, the other must have the same attribute. */
2606 if ((l1 != l2) || (s1 != s2))
2609 /* Disallow mixed attributes. */
2610 if ((l1 & s2) || (l2 & s1))
2614 /* Check for mismatched ISR attribute. */
2615 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2617 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2618 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2620 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2627 /* Encode long_call or short_call attribute by prefixing
2628 symbol name in DECL with a special character FLAG. */
2630 arm_encode_call_attribute (tree decl, int flag)
2632 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2633 int len = strlen (str);
2636 /* Do not allow weak functions to be treated as short call. */
2637 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2640 newstr = alloca (len + 2);
2642 strcpy (newstr + 1, str);
2644 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2645 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2648 /* Assigns default attributes to newly defined type. This is used to
2649 set short_call/long_call attributes for function types of
2650 functions defined inside corresponding #pragma scopes. */
2652 arm_set_default_type_attributes (tree type)
2654 /* Add __attribute__ ((long_call)) to all functions, when
2655 inside #pragma long_calls or __attribute__ ((short_call)),
2656 when inside #pragma no_long_calls. */
2657 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2659 tree type_attr_list, attr_name;
2660 type_attr_list = TYPE_ATTRIBUTES (type);
2662 if (arm_pragma_long_calls == LONG)
2663 attr_name = get_identifier ("long_call");
2664 else if (arm_pragma_long_calls == SHORT)
2665 attr_name = get_identifier ("short_call");
2669 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2670 TYPE_ATTRIBUTES (type) = type_attr_list;
2674 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2675 defined within the current compilation unit. If this cannot be
2676 determined, then 0 is returned. */
2678 current_file_function_operand (rtx sym_ref)
2680 /* This is a bit of a fib. A function will have a short call flag
2681 applied to its name if it has the short call attribute, or it has
2682 already been defined within the current compilation unit. */
2683 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2686 /* The current function is always defined within the current compilation
2687 unit. if it s a weak definition however, then this may not be the real
2688 definition of the function, and so we have to say no. */
2689 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2690 && !DECL_WEAK (current_function_decl))
2693 /* We cannot make the determination - default to returning 0. */
2697 /* Return nonzero if a 32 bit "long_call" should be generated for
2698 this call. We generate a long_call if the function:
2700 a. has an __attribute__((long call))
2701 or b. is within the scope of a #pragma long_calls
2702 or c. the -mlong-calls command line switch has been specified
2704 However we do not generate a long call if the function:
2706 d. has an __attribute__ ((short_call))
2707 or e. is inside the scope of a #pragma no_long_calls
2708 or f. has an __attribute__ ((section))
2709 or g. is defined within the current compilation unit.
2711 This function will be called by C fragments contained in the machine
2712 description file. CALL_REF and CALL_COOKIE correspond to the matched
2713 rtl operands. CALL_SYMBOL is used to distinguish between
2714 two different callers of the function. It is set to 1 in the
2715 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2716 and "call_value" patterns. This is because of the difference in the
2717 SYM_REFs passed by these patterns. */
2719 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2723 if (GET_CODE (sym_ref) != MEM)
2726 sym_ref = XEXP (sym_ref, 0);
2729 if (GET_CODE (sym_ref) != SYMBOL_REF)
2732 if (call_cookie & CALL_SHORT)
2735 if (TARGET_LONG_CALLS && flag_function_sections)
2738 if (current_file_function_operand (sym_ref))
2741 return (call_cookie & CALL_LONG)
2742 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2743 || TARGET_LONG_CALLS;
2746 /* Return nonzero if it is ok to make a tail-call to DECL. */
2748 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2750 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2752 if (cfun->machine->sibcall_blocked)
2755 /* Never tailcall something for which we have no decl, or if we
2756 are in Thumb mode. */
2757 if (decl == NULL || TARGET_THUMB)
2760 /* Get the calling method. */
2761 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2762 call_type = CALL_SHORT;
2763 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2764 call_type = CALL_LONG;
2766 /* Cannot tail-call to long calls, since these are out of range of
2767 a branch instruction. However, if not compiling PIC, we know
2768 we can reach the symbol if it is in this compilation unit. */
2769 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2772 /* If we are interworking and the function is not declared static
2773 then we can't tail-call it unless we know that it exists in this
2774 compilation unit (since it might be a Thumb routine). */
2775 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2778 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2779 if (IS_INTERRUPT (arm_current_func_type ()))
2782 /* Everything else is ok. */
2787 /* Addressing mode support functions. */
2789 /* Return nonzero if X is a legitimate immediate operand when compiling
2792 legitimate_pic_operand_p (rtx x)
2796 && (GET_CODE (x) == SYMBOL_REF
2797 || (GET_CODE (x) == CONST
2798 && GET_CODE (XEXP (x, 0)) == PLUS
2799 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2806 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2808 if (GET_CODE (orig) == SYMBOL_REF
2809 || GET_CODE (orig) == LABEL_REF)
2811 #ifndef AOF_ASSEMBLER
2812 rtx pic_ref, address;
2822 reg = gen_reg_rtx (Pmode);
2827 #ifdef AOF_ASSEMBLER
2828 /* The AOF assembler can generate relocations for these directly, and
2829 understands that the PIC register has to be added into the offset. */
2830 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2833 address = gen_reg_rtx (Pmode);
2838 emit_insn (gen_pic_load_addr_arm (address, orig));
2840 emit_insn (gen_pic_load_addr_thumb (address, orig));
2842 if ((GET_CODE (orig) == LABEL_REF
2843 || (GET_CODE (orig) == SYMBOL_REF &&
2844 SYMBOL_REF_LOCAL_P (orig)))
2846 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2849 pic_ref = gen_rtx_MEM (Pmode,
2850 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2852 RTX_UNCHANGING_P (pic_ref) = 1;
2855 insn = emit_move_insn (reg, pic_ref);
2857 current_function_uses_pic_offset_table = 1;
2858 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2860 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2864 else if (GET_CODE (orig) == CONST)
2868 if (GET_CODE (XEXP (orig, 0)) == PLUS
2869 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2877 reg = gen_reg_rtx (Pmode);
2880 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2882 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2883 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2884 base == reg ? 0 : reg);
2889 if (GET_CODE (offset) == CONST_INT)
2891 /* The base register doesn't really matter, we only want to
2892 test the index for the appropriate mode. */
2893 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2895 if (!no_new_pseudos)
2896 offset = force_reg (Pmode, offset);
2901 if (GET_CODE (offset) == CONST_INT)
2902 return plus_constant (base, INTVAL (offset));
2905 if (GET_MODE_SIZE (mode) > 4
2906 && (GET_MODE_CLASS (mode) == MODE_INT
2907 || TARGET_SOFT_FLOAT))
2909 emit_insn (gen_addsi3 (reg, base, offset));
2913 return gen_rtx_PLUS (Pmode, base, offset);
2919 /* Generate code to load the PIC register. PROLOGUE is true if
2920 called from arm_expand_prologue (in which case we want the
2921 generated insns at the start of the function); false if called
2922 by an exception receiver that needs the PIC register reloaded
2923 (in which case the insns are just dumped at the current location). */
2925 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2927 #ifndef AOF_ASSEMBLER
2928 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2929 rtx global_offset_table;
2931 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2938 l1 = gen_label_rtx ();
2940 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2941 /* On the ARM the PC register contains 'dot + 8' at the time of the
2942 addition, on the Thumb it is 'dot + 4'. */
2943 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2945 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2946 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2948 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2950 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2954 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2955 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2959 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2960 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2966 emit_insn_after (seq, get_insns ());
2970 /* Need to emit this whether or not we obey regdecls,
2971 since setjmp/longjmp can cause life info to screw up. */
2972 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2973 #endif /* AOF_ASSEMBLER */
2976 /* Return nonzero if X is valid as an ARM state addressing register. */
2978 arm_address_register_rtx_p (rtx x, int strict_p)
2982 if (GET_CODE (x) != REG)
2988 return ARM_REGNO_OK_FOR_BASE_P (regno);
2990 return (regno <= LAST_ARM_REGNUM
2991 || regno >= FIRST_PSEUDO_REGISTER
2992 || regno == FRAME_POINTER_REGNUM
2993 || regno == ARG_POINTER_REGNUM);
2996 /* Return nonzero if X is a valid ARM state address operand. */
2998 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3002 enum rtx_code code = GET_CODE (x);
3004 if (arm_address_register_rtx_p (x, strict_p))
3007 use_ldrd = (TARGET_LDRD
3009 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3011 if (code == POST_INC || code == PRE_DEC
3012 || ((code == PRE_INC || code == POST_DEC)
3013 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3014 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3016 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3017 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3018 && GET_CODE (XEXP (x, 1)) == PLUS
3019 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3021 rtx addend = XEXP (XEXP (x, 1), 1);
3023 /* Don't allow ldrd post increment by register becuase it's hard
3024 to fixup invalid register choices. */
3026 && GET_CODE (x) == POST_MODIFY
3027 && GET_CODE (addend) == REG)
3030 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3031 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3034 /* After reload constants split into minipools will have addresses
3035 from a LABEL_REF. */
3036 else if (reload_completed
3037 && (code == LABEL_REF
3039 && GET_CODE (XEXP (x, 0)) == PLUS
3040 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3041 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3044 else if (mode == TImode)
3047 else if (code == PLUS)
3049 rtx xop0 = XEXP (x, 0);
3050 rtx xop1 = XEXP (x, 1);
3052 return ((arm_address_register_rtx_p (xop0, strict_p)
3053 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3054 || (arm_address_register_rtx_p (xop1, strict_p)
3055 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3059 /* Reload currently can't handle MINUS, so disable this for now */
3060 else if (GET_CODE (x) == MINUS)
3062 rtx xop0 = XEXP (x, 0);
3063 rtx xop1 = XEXP (x, 1);
3065 return (arm_address_register_rtx_p (xop0, strict_p)
3066 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3070 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3071 && code == SYMBOL_REF
3072 && CONSTANT_POOL_ADDRESS_P (x)
3074 && symbol_mentioned_p (get_pool_constant (x))))
3080 /* Return nonzero if INDEX is valid for an address index operand in
3083 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3086 HOST_WIDE_INT range;
3087 enum rtx_code code = GET_CODE (index);
3089 /* Standard coprocessor addressing modes. */
3090 if (TARGET_HARD_FLOAT
3091 && (TARGET_FPA || TARGET_MAVERICK)
3092 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3093 || (TARGET_MAVERICK && mode == DImode)))
3094 return (code == CONST_INT && INTVAL (index) < 1024
3095 && INTVAL (index) > -1024
3096 && (INTVAL (index) & 3) == 0);
3098 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3099 return (code == CONST_INT
3100 && INTVAL (index) < 1024
3101 && INTVAL (index) > -1024
3102 && (INTVAL (index) & 3) == 0);
3104 if (arm_address_register_rtx_p (index, strict_p)
3105 && (GET_MODE_SIZE (mode) <= 4))
3108 if (mode == DImode || mode == DFmode)
3110 if (code == CONST_INT)
3112 HOST_WIDE_INT val = INTVAL (index);
3115 return val > -256 && val < 256;
3117 return val > -4096 && val < 4092;
3120 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3123 if (GET_MODE_SIZE (mode) <= 4
3126 || (mode == QImode && outer == SIGN_EXTEND))))
3130 rtx xiop0 = XEXP (index, 0);
3131 rtx xiop1 = XEXP (index, 1);
3133 return ((arm_address_register_rtx_p (xiop0, strict_p)
3134 && power_of_two_operand (xiop1, SImode))
3135 || (arm_address_register_rtx_p (xiop1, strict_p)
3136 && power_of_two_operand (xiop0, SImode)));
3138 else if (code == LSHIFTRT || code == ASHIFTRT
3139 || code == ASHIFT || code == ROTATERT)
3141 rtx op = XEXP (index, 1);
3143 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3144 && GET_CODE (op) == CONST_INT
3146 && INTVAL (op) <= 31);
3150 /* For ARM v4 we may be doing a sign-extend operation during the
3154 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3160 range = (mode == HImode) ? 4095 : 4096;
3162 return (code == CONST_INT
3163 && INTVAL (index) < range
3164 && INTVAL (index) > -range);
3167 /* Return nonzero if X is valid as a Thumb state base register. */
3169 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3173 if (GET_CODE (x) != REG)
3179 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3181 return (regno <= LAST_LO_REGNUM
3182 || regno > LAST_VIRTUAL_REGISTER
3183 || regno == FRAME_POINTER_REGNUM
3184 || (GET_MODE_SIZE (mode) >= 4
3185 && (regno == STACK_POINTER_REGNUM
3186 || regno >= FIRST_PSEUDO_REGISTER
3187 || x == hard_frame_pointer_rtx
3188 || x == arg_pointer_rtx)));
3191 /* Return nonzero if x is a legitimate index register. This is the case
3192 for any base register that can access a QImode object. */
3194 thumb_index_register_rtx_p (rtx x, int strict_p)
3196 return thumb_base_register_rtx_p (x, QImode, strict_p);
3199 /* Return nonzero if x is a legitimate Thumb-state address.
3201 The AP may be eliminated to either the SP or the FP, so we use the
3202 least common denominator, e.g. SImode, and offsets from 0 to 64.
3204 ??? Verify whether the above is the right approach.
3206 ??? Also, the FP may be eliminated to the SP, so perhaps that
3207 needs special handling also.
3209 ??? Look at how the mips16 port solves this problem. It probably uses
3210 better ways to solve some of these problems.
3212 Although it is not incorrect, we don't accept QImode and HImode
3213 addresses based on the frame pointer or arg pointer until the
3214 reload pass starts. This is so that eliminating such addresses
3215 into stack based ones won't produce impossible code. */
3217 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3219 /* ??? Not clear if this is right. Experiment. */
3220 if (GET_MODE_SIZE (mode) < 4
3221 && !(reload_in_progress || reload_completed)
3222 && (reg_mentioned_p (frame_pointer_rtx, x)
3223 || reg_mentioned_p (arg_pointer_rtx, x)
3224 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3225 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3226 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3227 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3230 /* Accept any base register. SP only in SImode or larger. */
3231 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3234 /* This is PC relative data before arm_reorg runs. */
3235 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3236 && GET_CODE (x) == SYMBOL_REF
3237 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3240 /* This is PC relative data after arm_reorg runs. */
3241 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3242 && (GET_CODE (x) == LABEL_REF
3243 || (GET_CODE (x) == CONST
3244 && GET_CODE (XEXP (x, 0)) == PLUS
3245 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3246 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3249 /* Post-inc indexing only supported for SImode and larger. */
3250 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3251 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3254 else if (GET_CODE (x) == PLUS)
3256 /* REG+REG address can be any two index registers. */
3257 /* We disallow FRAME+REG addressing since we know that FRAME
3258 will be replaced with STACK, and SP relative addressing only
3259 permits SP+OFFSET. */
3260 if (GET_MODE_SIZE (mode) <= 4
3261 && XEXP (x, 0) != frame_pointer_rtx
3262 && XEXP (x, 1) != frame_pointer_rtx
3263 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3264 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3267 /* REG+const has 5-7 bit offset for non-SP registers. */
3268 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3269 || XEXP (x, 0) == arg_pointer_rtx)
3270 && GET_CODE (XEXP (x, 1)) == CONST_INT
3271 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3274 /* REG+const has 10 bit offset for SP, but only SImode and
3275 larger is supported. */
3276 /* ??? Should probably check for DI/DFmode overflow here
3277 just like GO_IF_LEGITIMATE_OFFSET does. */
3278 else if (GET_CODE (XEXP (x, 0)) == REG
3279 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3280 && GET_MODE_SIZE (mode) >= 4
3281 && GET_CODE (XEXP (x, 1)) == CONST_INT
3282 && INTVAL (XEXP (x, 1)) >= 0
3283 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3284 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3287 else if (GET_CODE (XEXP (x, 0)) == REG
3288 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3289 && GET_MODE_SIZE (mode) >= 4
3290 && GET_CODE (XEXP (x, 1)) == CONST_INT
3291 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3295 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3296 && GET_MODE_SIZE (mode) == 4
3297 && GET_CODE (x) == SYMBOL_REF
3298 && CONSTANT_POOL_ADDRESS_P (x)
3300 && symbol_mentioned_p (get_pool_constant (x))))
3306 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3307 instruction of mode MODE. */
3309 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3311 switch (GET_MODE_SIZE (mode))
3314 return val >= 0 && val < 32;
3317 return val >= 0 && val < 64 && (val & 1) == 0;
3321 && (val + GET_MODE_SIZE (mode)) <= 128
3326 /* Try machine-dependent ways of modifying an illegitimate address
3327 to be legitimate. If we find one, return the new, valid address. */
3329 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3331 if (GET_CODE (x) == PLUS)
3333 rtx xop0 = XEXP (x, 0);
3334 rtx xop1 = XEXP (x, 1);
3336 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3337 xop0 = force_reg (SImode, xop0);
3339 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3340 xop1 = force_reg (SImode, xop1);
3342 if (ARM_BASE_REGISTER_RTX_P (xop0)
3343 && GET_CODE (xop1) == CONST_INT)
3345 HOST_WIDE_INT n, low_n;
3349 /* VFP addressing modes actually allow greater offsets, but for
3350 now we just stick with the lowest common denominator. */
3352 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3364 low_n = ((mode) == TImode ? 0
3365 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3369 base_reg = gen_reg_rtx (SImode);
3370 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3371 GEN_INT (n)), NULL_RTX);
3372 emit_move_insn (base_reg, val);
3373 x = (low_n == 0 ? base_reg
3374 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3376 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3377 x = gen_rtx_PLUS (SImode, xop0, xop1);
3380 /* XXX We don't allow MINUS any more -- see comment in
3381 arm_legitimate_address_p (). */
3382 else if (GET_CODE (x) == MINUS)
3384 rtx xop0 = XEXP (x, 0);
3385 rtx xop1 = XEXP (x, 1);
3387 if (CONSTANT_P (xop0))
3388 xop0 = force_reg (SImode, xop0);
3390 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3391 xop1 = force_reg (SImode, xop1);
3393 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3394 x = gen_rtx_MINUS (SImode, xop0, xop1);
3399 /* We need to find and carefully transform any SYMBOL and LABEL
3400 references; so go back to the original address expression. */
3401 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3403 if (new_x != orig_x)
3411 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3412 to be legitimate. If we find one, return the new, valid address. */
3414 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3416 if (GET_CODE (x) == PLUS
3417 && GET_CODE (XEXP (x, 1)) == CONST_INT
3418 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3419 || INTVAL (XEXP (x, 1)) < 0))
3421 rtx xop0 = XEXP (x, 0);
3422 rtx xop1 = XEXP (x, 1);
3423 HOST_WIDE_INT offset = INTVAL (xop1);
3425 /* Try and fold the offset into a biasing of the base register and
3426 then offsetting that. Don't do this when optimizing for space
3427 since it can cause too many CSEs. */
3428 if (optimize_size && offset >= 0
3429 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3431 HOST_WIDE_INT delta;
3434 delta = offset - (256 - GET_MODE_SIZE (mode));
3435 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3436 delta = 31 * GET_MODE_SIZE (mode);
3438 delta = offset & (~31 * GET_MODE_SIZE (mode));
3440 xop0 = force_operand (plus_constant (xop0, offset - delta),
3442 x = plus_constant (xop0, delta);
3444 else if (offset < 0 && offset > -256)
3445 /* Small negative offsets are best done with a subtract before the
3446 dereference, forcing these into a register normally takes two
3448 x = force_operand (x, NULL_RTX);
3451 /* For the remaining cases, force the constant into a register. */
3452 xop1 = force_reg (SImode, xop1);
3453 x = gen_rtx_PLUS (SImode, xop0, xop1);
3456 else if (GET_CODE (x) == PLUS
3457 && s_register_operand (XEXP (x, 1), SImode)
3458 && !s_register_operand (XEXP (x, 0), SImode))
3460 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3462 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3467 /* We need to find and carefully transform any SYMBOL and LABEL
3468 references; so go back to the original address expression. */
3469 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3471 if (new_x != orig_x)
3480 #define REG_OR_SUBREG_REG(X) \
3481 (GET_CODE (X) == REG \
3482 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3484 #define REG_OR_SUBREG_RTX(X) \
3485 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3487 #ifndef COSTS_N_INSNS
3488 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3491 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3493 enum machine_mode mode = GET_MODE (x);
3506 return COSTS_N_INSNS (1);
3509 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3512 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3519 return COSTS_N_INSNS (2) + cycles;
3521 return COSTS_N_INSNS (1) + 16;
3524 return (COSTS_N_INSNS (1)
3525 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3526 + GET_CODE (SET_DEST (x)) == MEM));
3531 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3533 if (thumb_shiftable_const (INTVAL (x)))
3534 return COSTS_N_INSNS (2);
3535 return COSTS_N_INSNS (3);
3537 else if ((outer == PLUS || outer == COMPARE)
3538 && INTVAL (x) < 256 && INTVAL (x) > -256)
3540 else if (outer == AND
3541 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3542 return COSTS_N_INSNS (1);
3543 else if (outer == ASHIFT || outer == ASHIFTRT
3544 || outer == LSHIFTRT)
3546 return COSTS_N_INSNS (2);
3552 return COSTS_N_INSNS (3);
3570 /* XXX another guess. */
3571 /* Memory costs quite a lot for the first word, but subsequent words
3572 load at the equivalent of a single insn each. */
3573 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3574 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3579 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3584 /* XXX still guessing. */
3585 switch (GET_MODE (XEXP (x, 0)))
3588 return (1 + (mode == DImode ? 4 : 0)
3589 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3592 return (4 + (mode == DImode ? 4 : 0)
3593 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3596 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3608 /* Worker routine for arm_rtx_costs. */
3610 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3612 enum machine_mode mode = GET_MODE (x);
3613 enum rtx_code subcode;
3619 /* Memory costs quite a lot for the first word, but subsequent words
3620 load at the equivalent of a single insn each. */
3621 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3622 + (GET_CODE (x) == SYMBOL_REF
3623 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3629 return optimize_size ? COSTS_N_INSNS (2) : 100;
3632 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3639 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3641 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3642 + ((GET_CODE (XEXP (x, 0)) == REG
3643 || (GET_CODE (XEXP (x, 0)) == SUBREG
3644 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3646 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3647 || (GET_CODE (XEXP (x, 0)) == SUBREG
3648 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3650 + ((GET_CODE (XEXP (x, 1)) == REG
3651 || (GET_CODE (XEXP (x, 1)) == SUBREG
3652 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3653 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3658 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3659 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3660 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3661 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3664 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3665 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3666 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3667 && arm_const_double_rtx (XEXP (x, 1))))
3669 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3670 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3671 && arm_const_double_rtx (XEXP (x, 0))))
3674 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3675 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3676 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3677 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3678 || subcode == ASHIFTRT || subcode == LSHIFTRT
3679 || subcode == ROTATE || subcode == ROTATERT
3681 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3682 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3683 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3684 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3685 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3686 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3687 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3692 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3693 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3694 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3695 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3696 && arm_const_double_rtx (XEXP (x, 1))))
3700 case AND: case XOR: case IOR:
3703 /* Normally the frame registers will be spilt into reg+const during
3704 reload, so it is a bad idea to combine them with other instructions,
3705 since then they might not be moved outside of loops. As a compromise
3706 we allow integration with ops that have a constant as their second
3708 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3709 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3710 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3711 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3712 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3716 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3717 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3718 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3719 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3722 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3723 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3724 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3725 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3726 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3729 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3730 return (1 + extra_cost
3731 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3732 || subcode == LSHIFTRT || subcode == ASHIFTRT
3733 || subcode == ROTATE || subcode == ROTATERT
3735 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3736 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3737 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3738 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3739 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3740 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3746 /* This should have been handled by the CPU specific routines. */
3750 if (arm_arch3m && mode == SImode
3751 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3752 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3753 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3754 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3755 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3756 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3761 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3762 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3766 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3768 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3771 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3779 return 4 + (mode == DImode ? 4 : 0);
3782 if (GET_MODE (XEXP (x, 0)) == QImode)
3783 return (4 + (mode == DImode ? 4 : 0)
3784 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3787 switch (GET_MODE (XEXP (x, 0)))
3790 return (1 + (mode == DImode ? 4 : 0)
3791 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3794 return (4 + (mode == DImode ? 4 : 0)
3795 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3798 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3813 if (const_ok_for_arm (INTVAL (x)))
3814 return outer == SET ? 2 : -1;
3815 else if (outer == AND
3816 && const_ok_for_arm (~INTVAL (x)))
3818 else if ((outer == COMPARE
3819 || outer == PLUS || outer == MINUS)
3820 && const_ok_for_arm (-INTVAL (x)))
3831 if (arm_const_double_rtx (x))
3832 return outer == SET ? 2 : -1;
3833 else if ((outer == COMPARE || outer == PLUS)
3834 && neg_const_double_rtx_ok_for_fpa (x))
3843 /* RTX costs for cores with a slow MUL implementation. */
3846 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3848 enum machine_mode mode = GET_MODE (x);
3852 *total = thumb_rtx_costs (x, code, outer_code);
3859 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3866 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3868 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3869 & (unsigned HOST_WIDE_INT) 0xffffffff);
3870 int cost, const_ok = const_ok_for_arm (i);
3871 int j, booth_unit_size;
3873 /* Tune as appropriate. */
3874 cost = const_ok ? 4 : 8;
3875 booth_unit_size = 2;
3876 for (j = 0; i && j < 32; j += booth_unit_size)
3878 i >>= booth_unit_size;
3886 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3887 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3891 *total = arm_rtx_costs_1 (x, code, outer_code);
3897 /* RTX cost for cores with a fast multiply unit (M variants). */
3900 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3902 enum machine_mode mode = GET_MODE (x);
3906 *total = thumb_rtx_costs (x, code, outer_code);
3913 /* There is no point basing this on the tuning, since it is always the
3914 fast variant if it exists at all. */
3916 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3917 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3918 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3925 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3932 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3934 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3935 & (unsigned HOST_WIDE_INT) 0xffffffff);
3936 int cost, const_ok = const_ok_for_arm (i);
3937 int j, booth_unit_size;
3939 /* Tune as appropriate. */
3940 cost = const_ok ? 4 : 8;
3941 booth_unit_size = 8;
3942 for (j = 0; i && j < 32; j += booth_unit_size)
3944 i >>= booth_unit_size;
3952 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3953 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3957 *total = arm_rtx_costs_1 (x, code, outer_code);
3963 /* RTX cost for XScale CPUs. */
3966 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3968 enum machine_mode mode = GET_MODE (x);
3972 *total = thumb_rtx_costs (x, code, outer_code);
3979 /* There is no point basing this on the tuning, since it is always the
3980 fast variant if it exists at all. */
3982 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3983 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3984 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3991 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3998 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4000 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4001 & (unsigned HOST_WIDE_INT) 0xffffffff);
4002 int cost, const_ok = const_ok_for_arm (i);
4003 unsigned HOST_WIDE_INT masked_const;
4005 /* The cost will be related to two insns.
4006 First a load of the constant (MOV or LDR), then a multiply. */
4009 cost += 1; /* LDR is probably more expensive because
4010 of longer result latency. */
4011 masked_const = i & 0xffff8000;
4012 if (masked_const != 0 && masked_const != 0xffff8000)
4014 masked_const = i & 0xf8000000;
4015 if (masked_const == 0 || masked_const == 0xf8000000)
4024 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4025 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4029 *total = arm_rtx_costs_1 (x, code, outer_code);
4035 /* RTX costs for 9e (and later) cores. */
4038 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4040 enum machine_mode mode = GET_MODE (x);
4049 *total = COSTS_N_INSNS (3);
4053 *total = thumb_rtx_costs (x, code, outer_code);
4061 /* There is no point basing this on the tuning, since it is always the
4062 fast variant if it exists at all. */
4064 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4065 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4066 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4073 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4090 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4091 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4095 *total = arm_rtx_costs_1 (x, code, outer_code);
4099 /* All address computations that can be done are free, but rtx cost returns
4100 the same for practically all of them. So we weight the different types
4101 of address here in the order (most pref first):
4102 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4104 arm_arm_address_cost (rtx x)
4106 enum rtx_code c = GET_CODE (x);
4108 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4110 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4113 if (c == PLUS || c == MINUS)
4115 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4118 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4128 arm_thumb_address_cost (rtx x)
4130 enum rtx_code c = GET_CODE (x);
4135 && GET_CODE (XEXP (x, 0)) == REG
4136 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4143 arm_address_cost (rtx x)
4145 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4149 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4153 /* Some true dependencies can have a higher cost depending
4154 on precisely how certain input operands are used. */
4156 && REG_NOTE_KIND (link) == 0
4157 && recog_memoized (insn) >= 0
4158 && recog_memoized (dep) >= 0)
4160 int shift_opnum = get_attr_shift (insn);
4161 enum attr_type attr_type = get_attr_type (dep);
4163 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4164 operand for INSN. If we have a shifted input operand and the
4165 instruction we depend on is another ALU instruction, then we may
4166 have to account for an additional stall. */
4167 if (shift_opnum != 0
4168 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4170 rtx shifted_operand;
4173 /* Get the shifted operand. */
4174 extract_insn (insn);
4175 shifted_operand = recog_data.operand[shift_opnum];
4177 /* Iterate over all the operands in DEP. If we write an operand
4178 that overlaps with SHIFTED_OPERAND, then we have increase the
4179 cost of this dependency. */
4181 preprocess_constraints ();
4182 for (opno = 0; opno < recog_data.n_operands; opno++)
4184 /* We can ignore strict inputs. */
4185 if (recog_data.operand_type[opno] == OP_IN)
4188 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4195 /* XXX This is not strictly true for the FPA. */
4196 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4197 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4200 /* Call insns don't incur a stall, even if they follow a load. */
4201 if (REG_NOTE_KIND (link) == 0
4202 && GET_CODE (insn) == CALL_INSN)
4205 if ((i_pat = single_set (insn)) != NULL
4206 && GET_CODE (SET_SRC (i_pat)) == MEM
4207 && (d_pat = single_set (dep)) != NULL
4208 && GET_CODE (SET_DEST (d_pat)) == MEM)
4210 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4211 /* This is a load after a store, there is no conflict if the load reads
4212 from a cached area. Assume that loads from the stack, and from the
4213 constant pool are cached, and that others will miss. This is a
4216 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4217 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4218 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4219 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4226 static int fp_consts_inited = 0;
4228 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4229 static const char * const strings_fp[8] =
4232 "4", "5", "0.5", "10"
4235 static REAL_VALUE_TYPE values_fp[8];
4238 init_fp_table (void)
4244 fp_consts_inited = 1;
4246 fp_consts_inited = 8;
4248 for (i = 0; i < fp_consts_inited; i++)
4250 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4255 /* Return TRUE if rtx X is a valid immediate FP constant. */
4257 arm_const_double_rtx (rtx x)
4262 if (!fp_consts_inited)
4265 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4266 if (REAL_VALUE_MINUS_ZERO (r))
4269 for (i = 0; i < fp_consts_inited; i++)
4270 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4276 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4278 neg_const_double_rtx_ok_for_fpa (rtx x)
4283 if (!fp_consts_inited)
4286 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4287 r = REAL_VALUE_NEGATE (r);
4288 if (REAL_VALUE_MINUS_ZERO (r))
4291 for (i = 0; i < 8; i++)
4292 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4298 /* Predicates for `match_operand' and `match_operator'. */
4300 /* s_register_operand is the same as register_operand, but it doesn't accept
4303 This function exists because at the time it was put in it led to better
4304 code. SUBREG(MEM) always needs a reload in the places where
4305 s_register_operand is used, and this seemed to lead to excessive
4308 s_register_operand (rtx op, enum machine_mode mode)
4310 if (GET_MODE (op) != mode && mode != VOIDmode)
4313 if (GET_CODE (op) == SUBREG)
4314 op = SUBREG_REG (op);
4316 /* We don't consider registers whose class is NO_REGS
4317 to be a register operand. */
4318 /* XXX might have to check for lo regs only for thumb ??? */
4319 return (GET_CODE (op) == REG
4320 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4321 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4324 /* A hard register operand (even before reload. */
4326 arm_hard_register_operand (rtx op, enum machine_mode mode)
4328 if (GET_MODE (op) != mode && mode != VOIDmode)
4331 return (GET_CODE (op) == REG
4332 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4335 /* An arm register operand. */
4337 arm_general_register_operand (rtx op, enum machine_mode mode)
4339 if (GET_MODE (op) != mode && mode != VOIDmode)
4342 if (GET_CODE (op) == SUBREG)
4343 op = SUBREG_REG (op);
4345 return (GET_CODE (op) == REG
4346 && (REGNO (op) <= LAST_ARM_REGNUM
4347 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4350 /* Only accept reg, subreg(reg), const_int. */
4352 reg_or_int_operand (rtx op, enum machine_mode mode)
4354 if (GET_CODE (op) == CONST_INT)
4357 if (GET_MODE (op) != mode && mode != VOIDmode)
4360 if (GET_CODE (op) == SUBREG)
4361 op = SUBREG_REG (op);
4363 /* We don't consider registers whose class is NO_REGS
4364 to be a register operand. */
4365 return (GET_CODE (op) == REG
4366 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4367 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4370 /* Return 1 if OP is an item in memory, given that we are in reload. */
4372 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4374 int regno = true_regnum (op);
4376 return (!CONSTANT_P (op)
4378 || (GET_CODE (op) == REG
4379 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4382 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4384 arm_rhs_operand (rtx op, enum machine_mode mode)
4386 return (s_register_operand (op, mode)
4387 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4390 /* Return TRUE for valid operands for the
4391 rhs of an ARM instruction, or a load. */
4393 arm_rhsm_operand (rtx op, enum machine_mode mode)
4395 return (s_register_operand (op, mode)
4396 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4397 || memory_operand (op, mode));
4400 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4401 constant that is valid when negated. */
4403 arm_add_operand (rtx op, enum machine_mode mode)
4406 return thumb_cmp_operand (op, mode);
4408 return (s_register_operand (op, mode)
4409 || (GET_CODE (op) == CONST_INT
4410 && (const_ok_for_arm (INTVAL (op))
4411 || const_ok_for_arm (-INTVAL (op)))));
4414 /* Return TRUE for valid ARM constants (or when valid if negated). */
4416 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4418 return (GET_CODE (op) == CONST_INT
4419 && (const_ok_for_arm (INTVAL (op))
4420 || const_ok_for_arm (-INTVAL (op))));
4424 arm_not_operand (rtx op, enum machine_mode mode)
4426 return (s_register_operand (op, mode)
4427 || (GET_CODE (op) == CONST_INT
4428 && (const_ok_for_arm (INTVAL (op))
4429 || const_ok_for_arm (~INTVAL (op)))));
4432 /* Return TRUE if the operand is a memory reference which contains an
4433 offsettable address. */
4435 offsettable_memory_operand (rtx op, enum machine_mode mode)
4437 if (mode == VOIDmode)
4438 mode = GET_MODE (op);
4440 return (mode == GET_MODE (op)
4441 && GET_CODE (op) == MEM
4442 && offsettable_address_p (reload_completed | reload_in_progress,
4443 mode, XEXP (op, 0)));
4446 /* Return TRUE if the operand is a memory reference which is, or can be
4447 made word aligned by adjusting the offset. */
4449 alignable_memory_operand (rtx op, enum machine_mode mode)
4453 if (mode == VOIDmode)
4454 mode = GET_MODE (op);
4456 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4461 return ((GET_CODE (reg = op) == REG
4462 || (GET_CODE (op) == SUBREG
4463 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4464 || (GET_CODE (op) == PLUS
4465 && GET_CODE (XEXP (op, 1)) == CONST_INT
4466 && (GET_CODE (reg = XEXP (op, 0)) == REG
4467 || (GET_CODE (XEXP (op, 0)) == SUBREG
4468 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4469 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4472 /* Similar to s_register_operand, but does not allow hard integer
4475 f_register_operand (rtx op, enum machine_mode mode)
4477 if (GET_MODE (op) != mode && mode != VOIDmode)
4480 if (GET_CODE (op) == SUBREG)
4481 op = SUBREG_REG (op);
4483 /* We don't consider registers whose class is NO_REGS
4484 to be a register operand. */
4485 return (GET_CODE (op) == REG
4486 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4487 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4490 /* Return TRUE for valid operands for the rhs of an floating point insns.
4491 Allows regs or certain consts on FPA, just regs for everything else. */
4493 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4495 if (s_register_operand (op, mode))
4498 if (GET_MODE (op) != mode && mode != VOIDmode)
4501 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4502 return arm_const_double_rtx (op);
4508 arm_float_add_operand (rtx op, enum machine_mode mode)
4510 if (s_register_operand (op, mode))
4513 if (GET_MODE (op) != mode && mode != VOIDmode)
4516 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4517 return (arm_const_double_rtx (op)
4518 || neg_const_double_rtx_ok_for_fpa (op));
4524 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4525 Depends which fpu we are targeting. */
4528 arm_float_compare_operand (rtx op, enum machine_mode mode)
4531 return vfp_compare_operand (op, mode);
4533 return arm_float_rhs_operand (op, mode);
4537 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4539 cirrus_memory_offset (rtx op)
4541 /* Reject eliminable registers. */
4542 if (! (reload_in_progress || reload_completed)
4543 && ( reg_mentioned_p (frame_pointer_rtx, op)
4544 || reg_mentioned_p (arg_pointer_rtx, op)
4545 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4546 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4547 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4548 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4551 if (GET_CODE (op) == MEM)
4557 /* Match: (mem (reg)). */
4558 if (GET_CODE (ind) == REG)
4564 if (GET_CODE (ind) == PLUS
4565 && GET_CODE (XEXP (ind, 0)) == REG
4566 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4567 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4575 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4577 if (!memory_operand (op, mode))
4580 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4583 /* Return nonzero if OP is a Cirrus or general register. */
4585 cirrus_register_operand (rtx op, enum machine_mode mode)
4587 if (GET_MODE (op) != mode && mode != VOIDmode)
4590 if (GET_CODE (op) == SUBREG)
4591 op = SUBREG_REG (op);
4593 return (GET_CODE (op) == REG
4594 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4595 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4598 /* Return nonzero if OP is a cirrus FP register. */
4600 cirrus_fp_register (rtx op, enum machine_mode mode)
4602 if (GET_MODE (op) != mode && mode != VOIDmode)
4605 if (GET_CODE (op) == SUBREG)
4606 op = SUBREG_REG (op);
4608 return (GET_CODE (op) == REG
4609 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4610 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4613 /* Return nonzero if OP is a 6bit constant (0..63). */
4615 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4617 return (GET_CODE (op) == CONST_INT
4619 && INTVAL (op) < 64);
4623 /* Return TRUE if OP is a valid VFP memory address pattern.
4624 WB if true if writeback address modes are allowed. */
4627 arm_coproc_mem_operand (rtx op, bool wb)
4631 /* Reject eliminable registers. */
4632 if (! (reload_in_progress || reload_completed)
4633 && ( reg_mentioned_p (frame_pointer_rtx, op)
4634 || reg_mentioned_p (arg_pointer_rtx, op)
4635 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4636 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4637 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4638 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4641 /* Constants are converted into offsets from labels. */
4642 if (GET_CODE (op) != MEM)
4647 if (reload_completed
4648 && (GET_CODE (ind) == LABEL_REF
4649 || (GET_CODE (ind) == CONST
4650 && GET_CODE (XEXP (ind, 0)) == PLUS
4651 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4652 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4655 /* Match: (mem (reg)). */
4656 if (GET_CODE (ind) == REG)
4657 return arm_address_register_rtx_p (ind, 0);
4659 /* Autoincremment addressing modes. */
4661 && (GET_CODE (ind) == PRE_INC
4662 || GET_CODE (ind) == POST_INC
4663 || GET_CODE (ind) == PRE_DEC
4664 || GET_CODE (ind) == POST_DEC))
4665 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4668 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4669 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4670 && GET_CODE (XEXP (ind, 1)) == PLUS
4671 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4672 ind = XEXP (ind, 1);
4677 if (GET_CODE (ind) == PLUS
4678 && GET_CODE (XEXP (ind, 0)) == REG
4679 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4680 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4681 && INTVAL (XEXP (ind, 1)) > -1024
4682 && INTVAL (XEXP (ind, 1)) < 1024
4683 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4690 /* Return TRUE if OP is a REG or constant zero. */
4692 vfp_compare_operand (rtx op, enum machine_mode mode)
4694 if (s_register_operand (op, mode))
4697 return (GET_CODE (op) == CONST_DOUBLE
4698 && arm_const_double_rtx (op));
4702 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4703 VFP registers. Otherwise return NO_REGS. */
4706 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4708 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4711 return GENERAL_REGS;
4715 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4716 Use by the Cirrus Maverick code which has to workaround
4717 a hardware bug triggered by such instructions. */
4719 arm_memory_load_p (rtx insn)
4721 rtx body, lhs, rhs;;
4723 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4726 body = PATTERN (insn);
4728 if (GET_CODE (body) != SET)
4731 lhs = XEXP (body, 0);
4732 rhs = XEXP (body, 1);
4734 lhs = REG_OR_SUBREG_RTX (lhs);
4736 /* If the destination is not a general purpose
4737 register we do not have to worry. */
4738 if (GET_CODE (lhs) != REG
4739 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4742 /* As well as loads from memory we also have to react
4743 to loads of invalid constants which will be turned
4744 into loads from the minipool. */
4745 return (GET_CODE (rhs) == MEM
4746 || GET_CODE (rhs) == SYMBOL_REF
4747 || note_invalid_constants (insn, -1, false));
4750 /* Return TRUE if INSN is a Cirrus instruction. */
4752 arm_cirrus_insn_p (rtx insn)
4754 enum attr_cirrus attr;
4756 /* get_attr aborts on USE and CLOBBER. */
4758 || GET_CODE (insn) != INSN
4759 || GET_CODE (PATTERN (insn)) == USE
4760 || GET_CODE (PATTERN (insn)) == CLOBBER)
4763 attr = get_attr_cirrus (insn);
4765 return attr != CIRRUS_NOT;
4768 /* Cirrus reorg for invalid instruction combinations. */
4770 cirrus_reorg (rtx first)
4772 enum attr_cirrus attr;
4773 rtx body = PATTERN (first);
4777 /* Any branch must be followed by 2 non Cirrus instructions. */
4778 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4781 t = next_nonnote_insn (first);
4783 if (arm_cirrus_insn_p (t))
4786 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4790 emit_insn_after (gen_nop (), first);
4795 /* (float (blah)) is in parallel with a clobber. */
4796 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4797 body = XVECEXP (body, 0, 0);
4799 if (GET_CODE (body) == SET)
4801 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4803 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4804 be followed by a non Cirrus insn. */
4805 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4807 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4808 emit_insn_after (gen_nop (), first);
4812 else if (arm_memory_load_p (first))
4814 unsigned int arm_regno;
4816 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4817 ldr/cfmv64hr combination where the Rd field is the same
4818 in both instructions must be split with a non Cirrus
4825 /* Get Arm register number for ldr insn. */
4826 if (GET_CODE (lhs) == REG)
4827 arm_regno = REGNO (lhs);
4828 else if (GET_CODE (rhs) == REG)
4829 arm_regno = REGNO (rhs);
4834 first = next_nonnote_insn (first);
4836 if (! arm_cirrus_insn_p (first))
4839 body = PATTERN (first);
4841 /* (float (blah)) is in parallel with a clobber. */
4842 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4843 body = XVECEXP (body, 0, 0);
4845 if (GET_CODE (body) == FLOAT)
4846 body = XEXP (body, 0);
4848 if (get_attr_cirrus (first) == CIRRUS_MOVE
4849 && GET_CODE (XEXP (body, 1)) == REG
4850 && arm_regno == REGNO (XEXP (body, 1)))
4851 emit_insn_after (gen_nop (), first);
4857 /* get_attr aborts on USE and CLOBBER. */
4859 || GET_CODE (first) != INSN
4860 || GET_CODE (PATTERN (first)) == USE
4861 || GET_CODE (PATTERN (first)) == CLOBBER)
4864 attr = get_attr_cirrus (first);
4866 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4867 must be followed by a non-coprocessor instruction. */
4868 if (attr == CIRRUS_COMPARE)
4872 t = next_nonnote_insn (first);
4874 if (arm_cirrus_insn_p (t))
4877 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4881 emit_insn_after (gen_nop (), first);
4887 /* Return nonzero if OP is a constant power of two. */
4889 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4891 if (GET_CODE (op) == CONST_INT)
4893 HOST_WIDE_INT value = INTVAL (op);
4895 return value != 0 && (value & (value - 1)) == 0;
4901 /* Return TRUE for a valid operand of a DImode operation.
4902 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4903 Note that this disallows MEM(REG+REG), but allows
4904 MEM(PRE/POST_INC/DEC(REG)). */
4906 di_operand (rtx op, enum machine_mode mode)
4908 if (s_register_operand (op, mode))
4911 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4914 if (GET_CODE (op) == SUBREG)
4915 op = SUBREG_REG (op);
4917 switch (GET_CODE (op))
4924 return memory_address_p (DImode, XEXP (op, 0));
4931 /* Like di_operand, but don't accept constants. */
4933 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4935 if (s_register_operand (op, mode))
4938 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4941 if (GET_CODE (op) == SUBREG)
4942 op = SUBREG_REG (op);
4944 if (GET_CODE (op) == MEM)
4945 return memory_address_p (DImode, XEXP (op, 0));
4950 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4951 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4952 Note that this disallows MEM(REG+REG), but allows
4953 MEM(PRE/POST_INC/DEC(REG)). */
4955 soft_df_operand (rtx op, enum machine_mode mode)
4957 if (s_register_operand (op, mode))
4960 if (mode != VOIDmode && GET_MODE (op) != mode)
4963 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4966 if (GET_CODE (op) == SUBREG)
4967 op = SUBREG_REG (op);
4969 switch (GET_CODE (op))
4975 return memory_address_p (DFmode, XEXP (op, 0));
4982 /* Like soft_df_operand, but don't accept constants. */
4984 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4986 if (s_register_operand (op, mode))
4989 if (mode != VOIDmode && GET_MODE (op) != mode)
4992 if (GET_CODE (op) == SUBREG)
4993 op = SUBREG_REG (op);
4995 if (GET_CODE (op) == MEM)
4996 return memory_address_p (DFmode, XEXP (op, 0));
5000 /* Return TRUE for valid index operands. */
5002 index_operand (rtx op, enum machine_mode mode)
5004 return (s_register_operand (op, mode)
5005 || (immediate_operand (op, mode)
5006 && (GET_CODE (op) != CONST_INT
5007 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
5010 /* Return TRUE for valid shifts by a constant. This also accepts any
5011 power of two on the (somewhat overly relaxed) assumption that the
5012 shift operator in this case was a mult. */
5014 const_shift_operand (rtx op, enum machine_mode mode)
5016 return (power_of_two_operand (op, mode)
5017 || (immediate_operand (op, mode)
5018 && (GET_CODE (op) != CONST_INT
5019 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5022 /* Return TRUE for arithmetic operators which can be combined with a multiply
5025 shiftable_operator (rtx x, enum machine_mode mode)
5029 if (GET_MODE (x) != mode)
5032 code = GET_CODE (x);
5034 return (code == PLUS || code == MINUS
5035 || code == IOR || code == XOR || code == AND);
5038 /* Return TRUE for binary logical operators. */
5040 logical_binary_operator (rtx x, enum machine_mode mode)
5044 if (GET_MODE (x) != mode)
5047 code = GET_CODE (x);
5049 return (code == IOR || code == XOR || code == AND);
5052 /* Return TRUE for shift operators. */
5054 shift_operator (rtx x,enum machine_mode mode)
5058 if (GET_MODE (x) != mode)
5061 code = GET_CODE (x);
5064 return power_of_two_operand (XEXP (x, 1), mode);
5066 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5067 || code == ROTATERT);
5070 /* Return TRUE if x is EQ or NE. */
5072 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5074 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5077 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5079 arm_comparison_operator (rtx x, enum machine_mode mode)
5081 return (comparison_operator (x, mode)
5082 && GET_CODE (x) != LTGT
5083 && GET_CODE (x) != UNEQ);
5086 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5088 minmax_operator (rtx x, enum machine_mode mode)
5090 enum rtx_code code = GET_CODE (x);
5092 if (GET_MODE (x) != mode)
5095 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5098 /* Return TRUE if this is the condition code register, if we aren't given
5099 a mode, accept any class CCmode register. */
5101 cc_register (rtx x, enum machine_mode mode)
5103 if (mode == VOIDmode)
5105 mode = GET_MODE (x);
5107 if (GET_MODE_CLASS (mode) != MODE_CC)
5111 if ( GET_MODE (x) == mode
5112 && GET_CODE (x) == REG
5113 && REGNO (x) == CC_REGNUM)
5119 /* Return TRUE if this is the condition code register, if we aren't given
5120 a mode, accept any class CCmode register which indicates a dominance
5123 dominant_cc_register (rtx x, enum machine_mode mode)
5125 if (mode == VOIDmode)
5127 mode = GET_MODE (x);
5129 if (GET_MODE_CLASS (mode) != MODE_CC)
5133 if (mode != CC_DNEmode && mode != CC_DEQmode
5134 && mode != CC_DLEmode && mode != CC_DLTmode
5135 && mode != CC_DGEmode && mode != CC_DGTmode
5136 && mode != CC_DLEUmode && mode != CC_DLTUmode
5137 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5140 return cc_register (x, mode);
5143 /* Return TRUE if X references a SYMBOL_REF. */
5145 symbol_mentioned_p (rtx x)
5150 if (GET_CODE (x) == SYMBOL_REF)
5153 fmt = GET_RTX_FORMAT (GET_CODE (x));
5155 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5161 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5162 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5165 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5172 /* Return TRUE if X references a LABEL_REF. */
5174 label_mentioned_p (rtx x)
5179 if (GET_CODE (x) == LABEL_REF)
5182 fmt = GET_RTX_FORMAT (GET_CODE (x));
5183 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5189 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5190 if (label_mentioned_p (XVECEXP (x, i, j)))
5193 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5203 enum rtx_code code = GET_CODE (x);
5207 else if (code == SMIN)
5209 else if (code == UMIN)
5211 else if (code == UMAX)
5217 /* Return 1 if memory locations are adjacent. */
5219 adjacent_mem_locations (rtx a, rtx b)
5221 if ((GET_CODE (XEXP (a, 0)) == REG
5222 || (GET_CODE (XEXP (a, 0)) == PLUS
5223 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5224 && (GET_CODE (XEXP (b, 0)) == REG
5225 || (GET_CODE (XEXP (b, 0)) == PLUS
5226 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5228 int val0 = 0, val1 = 0;
5231 if (GET_CODE (XEXP (a, 0)) == PLUS)
5233 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5234 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5237 reg0 = REGNO (XEXP (a, 0));
5239 if (GET_CODE (XEXP (b, 0)) == PLUS)
5241 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5242 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5245 reg1 = REGNO (XEXP (b, 0));
5247 /* Don't accept any offset that will require multiple
5248 instructions to handle, since this would cause the
5249 arith_adjacentmem pattern to output an overlong sequence. */
5250 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5253 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5258 /* Return 1 if OP is a load multiple operation. It is known to be
5259 parallel and the first section will be tested. */
5261 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5263 HOST_WIDE_INT count = XVECLEN (op, 0);
5266 HOST_WIDE_INT i = 1, base = 0;
5270 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5273 /* Check to see if this might be a write-back. */
5274 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5279 /* Now check it more carefully. */
5280 if (GET_CODE (SET_DEST (elt)) != REG
5281 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5282 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5283 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5287 /* Perform a quick check so we don't blow up below. */
5289 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5290 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5291 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5294 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5295 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5297 for (; i < count; i++)
5299 elt = XVECEXP (op, 0, i);
5301 if (GET_CODE (elt) != SET
5302 || GET_CODE (SET_DEST (elt)) != REG
5303 || GET_MODE (SET_DEST (elt)) != SImode
5304 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5305 || GET_CODE (SET_SRC (elt)) != MEM
5306 || GET_MODE (SET_SRC (elt)) != SImode
5307 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5308 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5309 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5310 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5317 /* Return 1 if OP is a store multiple operation. It is known to be
5318 parallel and the first section will be tested. */
5320 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5322 HOST_WIDE_INT count = XVECLEN (op, 0);
5325 HOST_WIDE_INT i = 1, base = 0;
5329 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5332 /* Check to see if this might be a write-back. */
5333 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5338 /* Now check it more carefully. */
5339 if (GET_CODE (SET_DEST (elt)) != REG
5340 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5341 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5342 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5346 /* Perform a quick check so we don't blow up below. */
5348 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5349 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5350 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5353 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5354 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5356 for (; i < count; i++)
5358 elt = XVECEXP (op, 0, i);
5360 if (GET_CODE (elt) != SET
5361 || GET_CODE (SET_SRC (elt)) != REG
5362 || GET_MODE (SET_SRC (elt)) != SImode
5363 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5364 || GET_CODE (SET_DEST (elt)) != MEM
5365 || GET_MODE (SET_DEST (elt)) != SImode
5366 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5367 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5368 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5369 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5377 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5378 HOST_WIDE_INT *load_offset)
5380 int unsorted_regs[4];
5381 HOST_WIDE_INT unsorted_offsets[4];
5386 /* Can only handle 2, 3, or 4 insns at present,
5387 though could be easily extended if required. */
5388 if (nops < 2 || nops > 4)
5391 /* Loop over the operands and check that the memory references are
5392 suitable (ie immediate offsets from the same base register). At
5393 the same time, extract the target register, and the memory
5395 for (i = 0; i < nops; i++)
5400 /* Convert a subreg of a mem into the mem itself. */
5401 if (GET_CODE (operands[nops + i]) == SUBREG)
5402 operands[nops + i] = alter_subreg (operands + (nops + i));
5404 if (GET_CODE (operands[nops + i]) != MEM)
5407 /* Don't reorder volatile memory references; it doesn't seem worth
5408 looking for the case where the order is ok anyway. */
5409 if (MEM_VOLATILE_P (operands[nops + i]))
5412 offset = const0_rtx;
5414 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5415 || (GET_CODE (reg) == SUBREG
5416 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5417 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5418 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5420 || (GET_CODE (reg) == SUBREG
5421 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5422 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5427 base_reg = REGNO (reg);
5428 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5429 ? REGNO (operands[i])
5430 : REGNO (SUBREG_REG (operands[i])));
5435 if (base_reg != (int) REGNO (reg))
5436 /* Not addressed from the same base register. */
5439 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5440 ? REGNO (operands[i])
5441 : REGNO (SUBREG_REG (operands[i])));
5442 if (unsorted_regs[i] < unsorted_regs[order[0]])
5446 /* If it isn't an integer register, or if it overwrites the
5447 base register but isn't the last insn in the list, then
5448 we can't do this. */
5449 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5450 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5453 unsorted_offsets[i] = INTVAL (offset);
5456 /* Not a suitable memory address. */
5460 /* All the useful information has now been extracted from the
5461 operands into unsorted_regs and unsorted_offsets; additionally,
5462 order[0] has been set to the lowest numbered register in the
5463 list. Sort the registers into order, and check that the memory
5464 offsets are ascending and adjacent. */
5466 for (i = 1; i < nops; i++)
5470 order[i] = order[i - 1];
5471 for (j = 0; j < nops; j++)
5472 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5473 && (order[i] == order[i - 1]
5474 || unsorted_regs[j] < unsorted_regs[order[i]]))
5477 /* Have we found a suitable register? if not, one must be used more
5479 if (order[i] == order[i - 1])
5482 /* Is the memory address adjacent and ascending? */
5483 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5491 for (i = 0; i < nops; i++)
5492 regs[i] = unsorted_regs[order[i]];
5494 *load_offset = unsorted_offsets[order[0]];
5497 if (unsorted_offsets[order[0]] == 0)
5498 return 1; /* ldmia */
5500 if (unsorted_offsets[order[0]] == 4)
5501 return 2; /* ldmib */
5503 if (unsorted_offsets[order[nops - 1]] == 0)
5504 return 3; /* ldmda */
5506 if (unsorted_offsets[order[nops - 1]] == -4)
5507 return 4; /* ldmdb */
5509 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5510 if the offset isn't small enough. The reason 2 ldrs are faster
5511 is because these ARMs are able to do more than one cache access
5512 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5513 whilst the ARM8 has a double bandwidth cache. This means that
5514 these cores can do both an instruction fetch and a data fetch in
5515 a single cycle, so the trick of calculating the address into a
5516 scratch register (one of the result regs) and then doing a load
5517 multiple actually becomes slower (and no smaller in code size).
5518 That is the transformation
5520 ldr rd1, [rbase + offset]
5521 ldr rd2, [rbase + offset + 4]
5525 add rd1, rbase, offset
5526 ldmia rd1, {rd1, rd2}
5528 produces worse code -- '3 cycles + any stalls on rd2' instead of
5529 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5530 access per cycle, the first sequence could never complete in less
5531 than 6 cycles, whereas the ldm sequence would only take 5 and
5532 would make better use of sequential accesses if not hitting the
5535 We cheat here and test 'arm_ld_sched' which we currently know to
5536 only be true for the ARM8, ARM9 and StrongARM. If this ever
5537 changes, then the test below needs to be reworked. */
5538 if (nops == 2 && arm_ld_sched)
5541 /* Can't do it without setting up the offset, only do this if it takes
5542 no more than one insn. */
5543 return (const_ok_for_arm (unsorted_offsets[order[0]])
5544 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5548 emit_ldm_seq (rtx *operands, int nops)
5552 HOST_WIDE_INT offset;
5556 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5559 strcpy (buf, "ldm%?ia\t");
5563 strcpy (buf, "ldm%?ib\t");
5567 strcpy (buf, "ldm%?da\t");
5571 strcpy (buf, "ldm%?db\t");
5576 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5577 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5580 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5581 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5583 output_asm_insn (buf, operands);
5585 strcpy (buf, "ldm%?ia\t");
5592 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5593 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5595 for (i = 1; i < nops; i++)
5596 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5597 reg_names[regs[i]]);
5599 strcat (buf, "}\t%@ phole ldm");
5601 output_asm_insn (buf, operands);
5606 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5607 HOST_WIDE_INT * load_offset)
5609 int unsorted_regs[4];
5610 HOST_WIDE_INT unsorted_offsets[4];
5615 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5616 extended if required. */
5617 if (nops < 2 || nops > 4)
5620 /* Loop over the operands and check that the memory references are
5621 suitable (ie immediate offsets from the same base register). At
5622 the same time, extract the target register, and the memory
5624 for (i = 0; i < nops; i++)
5629 /* Convert a subreg of a mem into the mem itself. */
5630 if (GET_CODE (operands[nops + i]) == SUBREG)
5631 operands[nops + i] = alter_subreg (operands + (nops + i));
5633 if (GET_CODE (operands[nops + i]) != MEM)
5636 /* Don't reorder volatile memory references; it doesn't seem worth
5637 looking for the case where the order is ok anyway. */
5638 if (MEM_VOLATILE_P (operands[nops + i]))
5641 offset = const0_rtx;
5643 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5644 || (GET_CODE (reg) == SUBREG
5645 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5646 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5647 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5649 || (GET_CODE (reg) == SUBREG
5650 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5651 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5656 base_reg = REGNO (reg);
5657 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5658 ? REGNO (operands[i])
5659 : REGNO (SUBREG_REG (operands[i])));
5664 if (base_reg != (int) REGNO (reg))
5665 /* Not addressed from the same base register. */
5668 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5669 ? REGNO (operands[i])
5670 : REGNO (SUBREG_REG (operands[i])));
5671 if (unsorted_regs[i] < unsorted_regs[order[0]])
5675 /* If it isn't an integer register, then we can't do this. */
5676 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5679 unsorted_offsets[i] = INTVAL (offset);
5682 /* Not a suitable memory address. */
5686 /* All the useful information has now been extracted from the
5687 operands into unsorted_regs and unsorted_offsets; additionally,
5688 order[0] has been set to the lowest numbered register in the
5689 list. Sort the registers into order, and check that the memory
5690 offsets are ascending and adjacent. */
5692 for (i = 1; i < nops; i++)
5696 order[i] = order[i - 1];
5697 for (j = 0; j < nops; j++)
5698 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5699 && (order[i] == order[i - 1]
5700 || unsorted_regs[j] < unsorted_regs[order[i]]))
5703 /* Have we found a suitable register? if not, one must be used more
5705 if (order[i] == order[i - 1])
5708 /* Is the memory address adjacent and ascending? */
5709 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5717 for (i = 0; i < nops; i++)
5718 regs[i] = unsorted_regs[order[i]];
5720 *load_offset = unsorted_offsets[order[0]];
5723 if (unsorted_offsets[order[0]] == 0)
5724 return 1; /* stmia */
5726 if (unsorted_offsets[order[0]] == 4)
5727 return 2; /* stmib */
5729 if (unsorted_offsets[order[nops - 1]] == 0)
5730 return 3; /* stmda */
5732 if (unsorted_offsets[order[nops - 1]] == -4)
5733 return 4; /* stmdb */
5739 emit_stm_seq (rtx *operands, int nops)
5743 HOST_WIDE_INT offset;
5747 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5750 strcpy (buf, "stm%?ia\t");
5754 strcpy (buf, "stm%?ib\t");
5758 strcpy (buf, "stm%?da\t");
5762 strcpy (buf, "stm%?db\t");
5769 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5770 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5772 for (i = 1; i < nops; i++)
5773 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5774 reg_names[regs[i]]);
5776 strcat (buf, "}\t%@ phole stm");
5778 output_asm_insn (buf, operands);
5783 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5785 if (GET_CODE (op) != PARALLEL
5786 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5787 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5788 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5794 /* Routines for use in generating RTL. */
5797 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5798 int write_back, int unchanging_p, int in_struct_p,
5803 int sign = up ? 1 : -1;
5806 /* XScale has load-store double instructions, but they have stricter
5807 alignment requirements than load-store multiple, so we can not
5810 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5811 the pipeline until completion.
5819 An ldr instruction takes 1-3 cycles, but does not block the
5828 Best case ldr will always win. However, the more ldr instructions
5829 we issue, the less likely we are to be able to schedule them well.
5830 Using ldr instructions also increases code size.
5832 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5833 for counts of 3 or 4 regs. */
5834 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5840 for (i = 0; i < count; i++)
5842 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5843 RTX_UNCHANGING_P (mem) = unchanging_p;
5844 MEM_IN_STRUCT_P (mem) = in_struct_p;
5845 MEM_SCALAR_P (mem) = scalar_p;
5846 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5850 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5858 result = gen_rtx_PARALLEL (VOIDmode,
5859 rtvec_alloc (count + (write_back ? 1 : 0)));
5862 XVECEXP (result, 0, 0)
5863 = gen_rtx_SET (GET_MODE (from), from,
5864 plus_constant (from, count * 4 * sign));
5869 for (j = 0; i < count; i++, j++)
5871 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5872 RTX_UNCHANGING_P (mem) = unchanging_p;
5873 MEM_IN_STRUCT_P (mem) = in_struct_p;
5874 MEM_SCALAR_P (mem) = scalar_p;
5875 XVECEXP (result, 0, i)
5876 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5883 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5884 int write_back, int unchanging_p, int in_struct_p,
5889 int sign = up ? 1 : -1;
5892 /* See arm_gen_load_multiple for discussion of
5893 the pros/cons of ldm/stm usage for XScale. */
5894 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5900 for (i = 0; i < count; i++)
5902 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5903 RTX_UNCHANGING_P (mem) = unchanging_p;
5904 MEM_IN_STRUCT_P (mem) = in_struct_p;
5905 MEM_SCALAR_P (mem) = scalar_p;
5906 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5910 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5918 result = gen_rtx_PARALLEL (VOIDmode,
5919 rtvec_alloc (count + (write_back ? 1 : 0)));
5922 XVECEXP (result, 0, 0)
5923 = gen_rtx_SET (GET_MODE (to), to,
5924 plus_constant (to, count * 4 * sign));
5929 for (j = 0; i < count; i++, j++)
5931 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5932 RTX_UNCHANGING_P (mem) = unchanging_p;
5933 MEM_IN_STRUCT_P (mem) = in_struct_p;
5934 MEM_SCALAR_P (mem) = scalar_p;
5936 XVECEXP (result, 0, i)
5937 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5944 arm_gen_movmemqi (rtx *operands)
5946 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5949 rtx st_src, st_dst, fin_src, fin_dst;
5950 rtx part_bytes_reg = NULL;
5952 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5953 int dst_scalar_p, src_scalar_p;
5955 if (GET_CODE (operands[2]) != CONST_INT
5956 || GET_CODE (operands[3]) != CONST_INT
5957 || INTVAL (operands[2]) > 64
5958 || INTVAL (operands[3]) & 3)
5961 st_dst = XEXP (operands[0], 0);
5962 st_src = XEXP (operands[1], 0);
5964 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5965 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5966 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5967 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5968 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5969 src_scalar_p = MEM_SCALAR_P (operands[1]);
5971 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5972 fin_src = src = copy_to_mode_reg (SImode, st_src);
5974 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5975 out_words_to_go = INTVAL (operands[2]) / 4;
5976 last_bytes = INTVAL (operands[2]) & 3;
5978 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5979 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5981 for (i = 0; in_words_to_go >= 2; i+=4)
5983 if (in_words_to_go > 4)
5984 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5989 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5990 FALSE, src_unchanging_p,
5991 src_in_struct_p, src_scalar_p));
5993 if (out_words_to_go)
5995 if (out_words_to_go > 4)
5996 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6000 else if (out_words_to_go != 1)
6001 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6010 mem = gen_rtx_MEM (SImode, dst);
6011 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6012 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6013 MEM_SCALAR_P (mem) = dst_scalar_p;
6014 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6015 if (last_bytes != 0)
6016 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6020 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6021 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6024 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6025 if (out_words_to_go)
6029 mem = gen_rtx_MEM (SImode, src);
6030 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6031 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6032 MEM_SCALAR_P (mem) = src_scalar_p;
6033 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
6034 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6036 mem = gen_rtx_MEM (SImode, dst);
6037 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6038 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6039 MEM_SCALAR_P (mem) = dst_scalar_p;
6040 emit_move_insn (mem, sreg);
6041 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6044 if (in_words_to_go) /* Sanity check */
6050 if (in_words_to_go < 0)
6053 mem = gen_rtx_MEM (SImode, src);
6054 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6055 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6056 MEM_SCALAR_P (mem) = src_scalar_p;
6057 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6060 if (last_bytes && part_bytes_reg == NULL)
6063 if (BYTES_BIG_ENDIAN && last_bytes)
6065 rtx tmp = gen_reg_rtx (SImode);
6067 /* The bytes we want are in the top end of the word. */
6068 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6069 GEN_INT (8 * (4 - last_bytes))));
6070 part_bytes_reg = tmp;
6074 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6075 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6076 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6077 MEM_SCALAR_P (mem) = dst_scalar_p;
6078 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6082 tmp = gen_reg_rtx (SImode);
6083 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6084 part_bytes_reg = tmp;
6093 mem = gen_rtx_MEM (HImode, dst);
6094 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6095 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6096 MEM_SCALAR_P (mem) = dst_scalar_p;
6097 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6101 rtx tmp = gen_reg_rtx (SImode);
6103 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6104 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6105 part_bytes_reg = tmp;
6111 mem = gen_rtx_MEM (QImode, dst);
6112 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6113 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6114 MEM_SCALAR_P (mem) = dst_scalar_p;
6115 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6122 /* Generate a memory reference for a half word, such that it will be loaded
6123 into the top 16 bits of the word. We can assume that the address is
6124 known to be alignable and of the form reg, or plus (reg, const). */
6127 arm_gen_rotated_half_load (rtx memref)
6129 HOST_WIDE_INT offset = 0;
6130 rtx base = XEXP (memref, 0);
6132 if (GET_CODE (base) == PLUS)
6134 offset = INTVAL (XEXP (base, 1));
6135 base = XEXP (base, 0);
6138 /* If we aren't allowed to generate unaligned addresses, then fail. */
6139 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6142 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6144 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6147 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6150 /* Select a dominance comparison mode if possible for a test of the general
6151 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6152 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6153 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6154 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6155 In all cases OP will be either EQ or NE, but we don't need to know which
6156 here. If we are unable to support a dominance comparison we return
6157 CC mode. This will then fail to match for the RTL expressions that
6158 generate this call. */
6160 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6162 enum rtx_code cond1, cond2;
6165 /* Currently we will probably get the wrong result if the individual
6166 comparisons are not simple. This also ensures that it is safe to
6167 reverse a comparison if necessary. */
6168 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6170 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6174 /* The if_then_else variant of this tests the second condition if the
6175 first passes, but is true if the first fails. Reverse the first
6176 condition to get a true "inclusive-or" expression. */
6177 if (cond_or == DOM_CC_NX_OR_Y)
6178 cond1 = reverse_condition (cond1);
6180 /* If the comparisons are not equal, and one doesn't dominate the other,
6181 then we can't do this. */
6183 && !comparison_dominates_p (cond1, cond2)
6184 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6189 enum rtx_code temp = cond1;
6197 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6202 case LE: return CC_DLEmode;
6203 case LEU: return CC_DLEUmode;
6204 case GE: return CC_DGEmode;
6205 case GEU: return CC_DGEUmode;
6212 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6221 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6230 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6239 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6247 /* The remaining cases only occur when both comparisons are the
6272 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6274 /* All floating point compares return CCFP if it is an equality
6275 comparison, and CCFPE otherwise. */
6276 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6296 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6305 /* A compare with a shifted operand. Because of canonicalization, the
6306 comparison will have to be swapped when we emit the assembler. */
6307 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6308 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6309 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6310 || GET_CODE (x) == ROTATERT))
6313 /* This is a special case that is used by combine to allow a
6314 comparison of a shifted byte load to be split into a zero-extend
6315 followed by a comparison of the shifted integer (only valid for
6316 equalities and unsigned inequalities). */
6317 if (GET_MODE (x) == SImode
6318 && GET_CODE (x) == ASHIFT
6319 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6320 && GET_CODE (XEXP (x, 0)) == SUBREG
6321 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6322 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6323 && (op == EQ || op == NE
6324 || op == GEU || op == GTU || op == LTU || op == LEU)
6325 && GET_CODE (y) == CONST_INT)
6328 /* A construct for a conditional compare, if the false arm contains
6329 0, then both conditions must be true, otherwise either condition
6330 must be true. Not all conditions are possible, so CCmode is
6331 returned if it can't be done. */
6332 if (GET_CODE (x) == IF_THEN_ELSE
6333 && (XEXP (x, 2) == const0_rtx
6334 || XEXP (x, 2) == const1_rtx)
6335 && COMPARISON_P (XEXP (x, 0))
6336 && COMPARISON_P (XEXP (x, 1)))
6337 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6338 INTVAL (XEXP (x, 2)));
6340 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6341 if (GET_CODE (x) == AND
6342 && COMPARISON_P (XEXP (x, 0))
6343 && COMPARISON_P (XEXP (x, 1)))
6344 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6347 if (GET_CODE (x) == IOR
6348 && COMPARISON_P (XEXP (x, 0))
6349 && COMPARISON_P (XEXP (x, 1)))
6350 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6353 /* An operation (on Thumb) where we want to test for a single bit.
6354 This is done by shifting that bit up into the top bit of a
6355 scratch register; we can then branch on the sign bit. */
6357 && GET_MODE (x) == SImode
6358 && (op == EQ || op == NE)
6359 && (GET_CODE (x) == ZERO_EXTRACT))
6362 /* An operation that sets the condition codes as a side-effect, the
6363 V flag is not set correctly, so we can only use comparisons where
6364 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6366 if (GET_MODE (x) == SImode
6368 && (op == EQ || op == NE || op == LT || op == GE)
6369 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6370 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6371 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6372 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6373 || GET_CODE (x) == LSHIFTRT
6374 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6375 || GET_CODE (x) == ROTATERT
6376 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6379 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6382 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6383 && GET_CODE (x) == PLUS
6384 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6390 /* X and Y are two things to compare using CODE. Emit the compare insn and
6391 return the rtx for register 0 in the proper mode. FP means this is a
6392 floating point compare: I don't think that it is needed on the arm. */
6394 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6396 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6397 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6399 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6400 gen_rtx_COMPARE (mode, x, y)));
6405 /* Generate a sequence of insns that will generate the correct return
6406 address mask depending on the physical architecture that the program
6409 arm_gen_return_addr_mask (void)
6411 rtx reg = gen_reg_rtx (Pmode);
6413 emit_insn (gen_return_addr_mask (reg));
6418 arm_reload_in_hi (rtx *operands)
6420 rtx ref = operands[1];
6422 HOST_WIDE_INT offset = 0;
6424 if (GET_CODE (ref) == SUBREG)
6426 offset = SUBREG_BYTE (ref);
6427 ref = SUBREG_REG (ref);
6430 if (GET_CODE (ref) == REG)
6432 /* We have a pseudo which has been spilt onto the stack; there
6433 are two cases here: the first where there is a simple
6434 stack-slot replacement and a second where the stack-slot is
6435 out of range, or is used as a subreg. */
6436 if (reg_equiv_mem[REGNO (ref)])
6438 ref = reg_equiv_mem[REGNO (ref)];
6439 base = find_replacement (&XEXP (ref, 0));
6442 /* The slot is out of range, or was dressed up in a SUBREG. */
6443 base = reg_equiv_address[REGNO (ref)];
6446 base = find_replacement (&XEXP (ref, 0));
6448 /* Handle the case where the address is too complex to be offset by 1. */
6449 if (GET_CODE (base) == MINUS
6450 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6452 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6454 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6457 else if (GET_CODE (base) == PLUS)
6459 /* The addend must be CONST_INT, or we would have dealt with it above. */
6460 HOST_WIDE_INT hi, lo;
6462 offset += INTVAL (XEXP (base, 1));
6463 base = XEXP (base, 0);
6465 /* Rework the address into a legal sequence of insns. */
6466 /* Valid range for lo is -4095 -> 4095 */
6469 : -((-offset) & 0xfff));
6471 /* Corner case, if lo is the max offset then we would be out of range
6472 once we have added the additional 1 below, so bump the msb into the
6473 pre-loading insn(s). */
6477 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6478 ^ (HOST_WIDE_INT) 0x80000000)
6479 - (HOST_WIDE_INT) 0x80000000);
6481 if (hi + lo != offset)
6486 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6488 /* Get the base address; addsi3 knows how to handle constants
6489 that require more than one insn. */
6490 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6496 /* Operands[2] may overlap operands[0] (though it won't overlap
6497 operands[1]), that's why we asked for a DImode reg -- so we can
6498 use the bit that does not overlap. */
6499 if (REGNO (operands[2]) == REGNO (operands[0]))
6500 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6502 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6504 emit_insn (gen_zero_extendqisi2 (scratch,
6505 gen_rtx_MEM (QImode,
6506 plus_constant (base,
6508 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6509 gen_rtx_MEM (QImode,
6510 plus_constant (base,
6512 if (!BYTES_BIG_ENDIAN)
6513 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6514 gen_rtx_IOR (SImode,
6517 gen_rtx_SUBREG (SImode, operands[0], 0),
6521 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6522 gen_rtx_IOR (SImode,
6523 gen_rtx_ASHIFT (SImode, scratch,
6525 gen_rtx_SUBREG (SImode, operands[0],
6529 /* Handle storing a half-word to memory during reload by synthesizing as two
6530 byte stores. Take care not to clobber the input values until after we
6531 have moved them somewhere safe. This code assumes that if the DImode
6532 scratch in operands[2] overlaps either the input value or output address
6533 in some way, then that value must die in this insn (we absolutely need
6534 two scratch registers for some corner cases). */
6536 arm_reload_out_hi (rtx *operands)
6538 rtx ref = operands[0];
6539 rtx outval = operands[1];
6541 HOST_WIDE_INT offset = 0;
6543 if (GET_CODE (ref) == SUBREG)
6545 offset = SUBREG_BYTE (ref);
6546 ref = SUBREG_REG (ref);
6549 if (GET_CODE (ref) == REG)
6551 /* We have a pseudo which has been spilt onto the stack; there
6552 are two cases here: the first where there is a simple
6553 stack-slot replacement and a second where the stack-slot is
6554 out of range, or is used as a subreg. */
6555 if (reg_equiv_mem[REGNO (ref)])
6557 ref = reg_equiv_mem[REGNO (ref)];
6558 base = find_replacement (&XEXP (ref, 0));
6561 /* The slot is out of range, or was dressed up in a SUBREG. */
6562 base = reg_equiv_address[REGNO (ref)];
6565 base = find_replacement (&XEXP (ref, 0));
6567 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6569 /* Handle the case where the address is too complex to be offset by 1. */
6570 if (GET_CODE (base) == MINUS
6571 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6573 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6575 /* Be careful not to destroy OUTVAL. */
6576 if (reg_overlap_mentioned_p (base_plus, outval))
6578 /* Updating base_plus might destroy outval, see if we can
6579 swap the scratch and base_plus. */
6580 if (!reg_overlap_mentioned_p (scratch, outval))
6583 scratch = base_plus;
6588 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6590 /* Be conservative and copy OUTVAL into the scratch now,
6591 this should only be necessary if outval is a subreg
6592 of something larger than a word. */
6593 /* XXX Might this clobber base? I can't see how it can,
6594 since scratch is known to overlap with OUTVAL, and
6595 must be wider than a word. */
6596 emit_insn (gen_movhi (scratch_hi, outval));
6597 outval = scratch_hi;
6601 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6604 else if (GET_CODE (base) == PLUS)
6606 /* The addend must be CONST_INT, or we would have dealt with it above. */
6607 HOST_WIDE_INT hi, lo;
6609 offset += INTVAL (XEXP (base, 1));
6610 base = XEXP (base, 0);
6612 /* Rework the address into a legal sequence of insns. */
6613 /* Valid range for lo is -4095 -> 4095 */
6616 : -((-offset) & 0xfff));
6618 /* Corner case, if lo is the max offset then we would be out of range
6619 once we have added the additional 1 below, so bump the msb into the
6620 pre-loading insn(s). */
6624 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6625 ^ (HOST_WIDE_INT) 0x80000000)
6626 - (HOST_WIDE_INT) 0x80000000);
6628 if (hi + lo != offset)
6633 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6635 /* Be careful not to destroy OUTVAL. */
6636 if (reg_overlap_mentioned_p (base_plus, outval))
6638 /* Updating base_plus might destroy outval, see if we
6639 can swap the scratch and base_plus. */
6640 if (!reg_overlap_mentioned_p (scratch, outval))
6643 scratch = base_plus;
6648 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6650 /* Be conservative and copy outval into scratch now,
6651 this should only be necessary if outval is a
6652 subreg of something larger than a word. */
6653 /* XXX Might this clobber base? I can't see how it
6654 can, since scratch is known to overlap with
6656 emit_insn (gen_movhi (scratch_hi, outval));
6657 outval = scratch_hi;
6661 /* Get the base address; addsi3 knows how to handle constants
6662 that require more than one insn. */
6663 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6669 if (BYTES_BIG_ENDIAN)
6671 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6672 plus_constant (base, offset + 1)),
6673 gen_lowpart (QImode, outval)));
6674 emit_insn (gen_lshrsi3 (scratch,
6675 gen_rtx_SUBREG (SImode, outval, 0),
6677 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6678 gen_lowpart (QImode, scratch)));
6682 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6683 gen_lowpart (QImode, outval)));
6684 emit_insn (gen_lshrsi3 (scratch,
6685 gen_rtx_SUBREG (SImode, outval, 0),
6687 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6688 plus_constant (base, offset + 1)),
6689 gen_lowpart (QImode, scratch)));
6693 /* Print a symbolic form of X to the debug file, F. */
6695 arm_print_value (FILE *f, rtx x)
6697 switch (GET_CODE (x))
6700 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6704 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6712 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6714 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6715 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6723 fprintf (f, "\"%s\"", XSTR (x, 0));
6727 fprintf (f, "`%s'", XSTR (x, 0));
6731 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6735 arm_print_value (f, XEXP (x, 0));
6739 arm_print_value (f, XEXP (x, 0));
6741 arm_print_value (f, XEXP (x, 1));
6749 fprintf (f, "????");
6754 /* Routines for manipulation of the constant pool. */
6756 /* Arm instructions cannot load a large constant directly into a
6757 register; they have to come from a pc relative load. The constant
6758 must therefore be placed in the addressable range of the pc
6759 relative load. Depending on the precise pc relative load
6760 instruction the range is somewhere between 256 bytes and 4k. This
6761 means that we often have to dump a constant inside a function, and
6762 generate code to branch around it.
6764 It is important to minimize this, since the branches will slow
6765 things down and make the code larger.
6767 Normally we can hide the table after an existing unconditional
6768 branch so that there is no interruption of the flow, but in the
6769 worst case the code looks like this:
6787 We fix this by performing a scan after scheduling, which notices
6788 which instructions need to have their operands fetched from the
6789 constant table and builds the table.
6791 The algorithm starts by building a table of all the constants that
6792 need fixing up and all the natural barriers in the function (places
6793 where a constant table can be dropped without breaking the flow).
6794 For each fixup we note how far the pc-relative replacement will be
6795 able to reach and the offset of the instruction into the function.
6797 Having built the table we then group the fixes together to form
6798 tables that are as large as possible (subject to addressing
6799 constraints) and emit each table of constants after the last
6800 barrier that is within range of all the instructions in the group.
6801 If a group does not contain a barrier, then we forcibly create one
6802 by inserting a jump instruction into the flow. Once the table has
6803 been inserted, the insns are then modified to reference the
6804 relevant entry in the pool.
6806 Possible enhancements to the algorithm (not implemented) are:
6808 1) For some processors and object formats, there may be benefit in
6809 aligning the pools to the start of cache lines; this alignment
6810 would need to be taken into account when calculating addressability
6813 /* These typedefs are located at the start of this file, so that
6814 they can be used in the prototypes there. This comment is to
6815 remind readers of that fact so that the following structures
6816 can be understood more easily.
6818 typedef struct minipool_node Mnode;
6819 typedef struct minipool_fixup Mfix; */
6821 struct minipool_node
6823 /* Doubly linked chain of entries. */
6826 /* The maximum offset into the code that this entry can be placed. While
6827 pushing fixes for forward references, all entries are sorted in order
6828 of increasing max_address. */
6829 HOST_WIDE_INT max_address;
6830 /* Similarly for an entry inserted for a backwards ref. */
6831 HOST_WIDE_INT min_address;
6832 /* The number of fixes referencing this entry. This can become zero
6833 if we "unpush" an entry. In this case we ignore the entry when we
6834 come to emit the code. */
6836 /* The offset from the start of the minipool. */
6837 HOST_WIDE_INT offset;
6838 /* The value in table. */
6840 /* The mode of value. */
6841 enum machine_mode mode;
6842 /* The size of the value. With iWMMXt enabled
6843 sizes > 4 also imply an alignment of 8-bytes. */
6847 struct minipool_fixup
6851 HOST_WIDE_INT address;
6853 enum machine_mode mode;
6857 HOST_WIDE_INT forwards;
6858 HOST_WIDE_INT backwards;
6861 /* Fixes less than a word need padding out to a word boundary. */
6862 #define MINIPOOL_FIX_SIZE(mode) \
6863 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6865 static Mnode * minipool_vector_head;
6866 static Mnode * minipool_vector_tail;
6867 static rtx minipool_vector_label;
6869 /* The linked list of all minipool fixes required for this function. */
6870 Mfix * minipool_fix_head;
6871 Mfix * minipool_fix_tail;
6872 /* The fix entry for the current minipool, once it has been placed. */
6873 Mfix * minipool_barrier;
6875 /* Determines if INSN is the start of a jump table. Returns the end
6876 of the TABLE or NULL_RTX. */
6878 is_jump_table (rtx insn)
6882 if (GET_CODE (insn) == JUMP_INSN
6883 && JUMP_LABEL (insn) != NULL
6884 && ((table = next_real_insn (JUMP_LABEL (insn)))
6885 == next_real_insn (insn))
6887 && GET_CODE (table) == JUMP_INSN
6888 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6889 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6895 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6896 #define JUMP_TABLES_IN_TEXT_SECTION 0
6899 static HOST_WIDE_INT
6900 get_jump_table_size (rtx insn)
6902 /* ADDR_VECs only take room if read-only data does into the text
6904 if (JUMP_TABLES_IN_TEXT_SECTION
6905 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6910 rtx body = PATTERN (insn);
6911 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6913 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6919 /* Move a minipool fix MP from its current location to before MAX_MP.
6920 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6921 constraints may need updating. */
6923 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6924 HOST_WIDE_INT max_address)
6926 /* This should never be true and the code below assumes these are
6933 if (max_address < mp->max_address)
6934 mp->max_address = max_address;
6938 if (max_address > max_mp->max_address - mp->fix_size)
6939 mp->max_address = max_mp->max_address - mp->fix_size;
6941 mp->max_address = max_address;
6943 /* Unlink MP from its current position. Since max_mp is non-null,
6944 mp->prev must be non-null. */
6945 mp->prev->next = mp->next;
6946 if (mp->next != NULL)
6947 mp->next->prev = mp->prev;
6949 minipool_vector_tail = mp->prev;
6951 /* Re-insert it before MAX_MP. */
6953 mp->prev = max_mp->prev;
6956 if (mp->prev != NULL)
6957 mp->prev->next = mp;
6959 minipool_vector_head = mp;
6962 /* Save the new entry. */
6965 /* Scan over the preceding entries and adjust their addresses as
6967 while (mp->prev != NULL
6968 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6970 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6977 /* Add a constant to the minipool for a forward reference. Returns the
6978 node added or NULL if the constant will not fit in this pool. */
6980 add_minipool_forward_ref (Mfix *fix)
6982 /* If set, max_mp is the first pool_entry that has a lower
6983 constraint than the one we are trying to add. */
6984 Mnode * max_mp = NULL;
6985 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6988 /* If this fix's address is greater than the address of the first
6989 entry, then we can't put the fix in this pool. We subtract the
6990 size of the current fix to ensure that if the table is fully
6991 packed we still have enough room to insert this value by suffling
6992 the other fixes forwards. */
6993 if (minipool_vector_head &&
6994 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6997 /* Scan the pool to see if a constant with the same value has
6998 already been added. While we are doing this, also note the
6999 location where we must insert the constant if it doesn't already
7001 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7003 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7004 && fix->mode == mp->mode
7005 && (GET_CODE (fix->value) != CODE_LABEL
7006 || (CODE_LABEL_NUMBER (fix->value)
7007 == CODE_LABEL_NUMBER (mp->value)))
7008 && rtx_equal_p (fix->value, mp->value))
7010 /* More than one fix references this entry. */
7012 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7015 /* Note the insertion point if necessary. */
7017 && mp->max_address > max_address)
7020 /* If we are inserting an 8-bytes aligned quantity and
7021 we have not already found an insertion point, then
7022 make sure that all such 8-byte aligned quantities are
7023 placed at the start of the pool. */
7024 if (ARM_DOUBLEWORD_ALIGN
7026 && fix->fix_size == 8
7027 && mp->fix_size != 8)
7030 max_address = mp->max_address;
7034 /* The value is not currently in the minipool, so we need to create
7035 a new entry for it. If MAX_MP is NULL, the entry will be put on
7036 the end of the list since the placement is less constrained than
7037 any existing entry. Otherwise, we insert the new fix before
7038 MAX_MP and, if necessary, adjust the constraints on the other
7040 mp = xmalloc (sizeof (* mp));
7041 mp->fix_size = fix->fix_size;
7042 mp->mode = fix->mode;
7043 mp->value = fix->value;
7045 /* Not yet required for a backwards ref. */
7046 mp->min_address = -65536;
7050 mp->max_address = max_address;
7052 mp->prev = minipool_vector_tail;
7054 if (mp->prev == NULL)
7056 minipool_vector_head = mp;
7057 minipool_vector_label = gen_label_rtx ();
7060 mp->prev->next = mp;
7062 minipool_vector_tail = mp;
7066 if (max_address > max_mp->max_address - mp->fix_size)
7067 mp->max_address = max_mp->max_address - mp->fix_size;
7069 mp->max_address = max_address;
7072 mp->prev = max_mp->prev;
7074 if (mp->prev != NULL)
7075 mp->prev->next = mp;
7077 minipool_vector_head = mp;
7080 /* Save the new entry. */
7083 /* Scan over the preceding entries and adjust their addresses as
7085 while (mp->prev != NULL
7086 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7088 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7096 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7097 HOST_WIDE_INT min_address)
7099 HOST_WIDE_INT offset;
7101 /* This should never be true, and the code below assumes these are
7108 if (min_address > mp->min_address)
7109 mp->min_address = min_address;
7113 /* We will adjust this below if it is too loose. */
7114 mp->min_address = min_address;
7116 /* Unlink MP from its current position. Since min_mp is non-null,
7117 mp->next must be non-null. */
7118 mp->next->prev = mp->prev;
7119 if (mp->prev != NULL)
7120 mp->prev->next = mp->next;
7122 minipool_vector_head = mp->next;
7124 /* Reinsert it after MIN_MP. */
7126 mp->next = min_mp->next;
7128 if (mp->next != NULL)
7129 mp->next->prev = mp;
7131 minipool_vector_tail = mp;
7137 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7139 mp->offset = offset;
7140 if (mp->refcount > 0)
7141 offset += mp->fix_size;
7143 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7144 mp->next->min_address = mp->min_address + mp->fix_size;
7150 /* Add a constant to the minipool for a backward reference. Returns the
7151 node added or NULL if the constant will not fit in this pool.
7153 Note that the code for insertion for a backwards reference can be
7154 somewhat confusing because the calculated offsets for each fix do
7155 not take into account the size of the pool (which is still under
7158 add_minipool_backward_ref (Mfix *fix)
7160 /* If set, min_mp is the last pool_entry that has a lower constraint
7161 than the one we are trying to add. */
7162 Mnode *min_mp = NULL;
7163 /* This can be negative, since it is only a constraint. */
7164 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7167 /* If we can't reach the current pool from this insn, or if we can't
7168 insert this entry at the end of the pool without pushing other
7169 fixes out of range, then we don't try. This ensures that we
7170 can't fail later on. */
7171 if (min_address >= minipool_barrier->address
7172 || (minipool_vector_tail->min_address + fix->fix_size
7173 >= minipool_barrier->address))
7176 /* Scan the pool to see if a constant with the same value has
7177 already been added. While we are doing this, also note the
7178 location where we must insert the constant if it doesn't already
7180 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7182 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7183 && fix->mode == mp->mode
7184 && (GET_CODE (fix->value) != CODE_LABEL
7185 || (CODE_LABEL_NUMBER (fix->value)
7186 == CODE_LABEL_NUMBER (mp->value)))
7187 && rtx_equal_p (fix->value, mp->value)
7188 /* Check that there is enough slack to move this entry to the
7189 end of the table (this is conservative). */
7191 > (minipool_barrier->address
7192 + minipool_vector_tail->offset
7193 + minipool_vector_tail->fix_size)))
7196 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7200 mp->min_address += fix->fix_size;
7203 /* Note the insertion point if necessary. */
7204 if (mp->min_address < min_address)
7206 /* For now, we do not allow the insertion of 8-byte alignment
7207 requiring nodes anywhere but at the start of the pool. */
7208 if (ARM_DOUBLEWORD_ALIGN
7209 && fix->fix_size == 8 && mp->fix_size != 8)
7214 else if (mp->max_address
7215 < minipool_barrier->address + mp->offset + fix->fix_size)
7217 /* Inserting before this entry would push the fix beyond
7218 its maximum address (which can happen if we have
7219 re-located a forwards fix); force the new fix to come
7222 min_address = mp->min_address + fix->fix_size;
7224 /* If we are inserting an 8-bytes aligned quantity and
7225 we have not already found an insertion point, then
7226 make sure that all such 8-byte aligned quantities are
7227 placed at the start of the pool. */
7228 else if (ARM_DOUBLEWORD_ALIGN
7230 && fix->fix_size == 8
7231 && mp->fix_size < 8)
7234 min_address = mp->min_address + fix->fix_size;
7239 /* We need to create a new entry. */
7240 mp = xmalloc (sizeof (* mp));
7241 mp->fix_size = fix->fix_size;
7242 mp->mode = fix->mode;
7243 mp->value = fix->value;
7245 mp->max_address = minipool_barrier->address + 65536;
7247 mp->min_address = min_address;
7252 mp->next = minipool_vector_head;
7254 if (mp->next == NULL)
7256 minipool_vector_tail = mp;
7257 minipool_vector_label = gen_label_rtx ();
7260 mp->next->prev = mp;
7262 minipool_vector_head = mp;
7266 mp->next = min_mp->next;
7270 if (mp->next != NULL)
7271 mp->next->prev = mp;
7273 minipool_vector_tail = mp;
7276 /* Save the new entry. */
7284 /* Scan over the following entries and adjust their offsets. */
7285 while (mp->next != NULL)
7287 if (mp->next->min_address < mp->min_address + mp->fix_size)
7288 mp->next->min_address = mp->min_address + mp->fix_size;
7291 mp->next->offset = mp->offset + mp->fix_size;
7293 mp->next->offset = mp->offset;
7302 assign_minipool_offsets (Mfix *barrier)
7304 HOST_WIDE_INT offset = 0;
7307 minipool_barrier = barrier;
7309 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7311 mp->offset = offset;
7313 if (mp->refcount > 0)
7314 offset += mp->fix_size;
7318 /* Output the literal table */
7320 dump_minipool (rtx scan)
7326 if (ARM_DOUBLEWORD_ALIGN)
7327 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7328 if (mp->refcount > 0 && mp->fix_size == 8)
7336 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7337 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7339 scan = emit_label_after (gen_label_rtx (), scan);
7340 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7341 scan = emit_label_after (minipool_vector_label, scan);
7343 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7345 if (mp->refcount > 0)
7350 ";; Offset %u, min %ld, max %ld ",
7351 (unsigned) mp->offset, (unsigned long) mp->min_address,
7352 (unsigned long) mp->max_address);
7353 arm_print_value (dump_file, mp->value);
7354 fputc ('\n', dump_file);
7357 switch (mp->fix_size)
7359 #ifdef HAVE_consttable_1
7361 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7365 #ifdef HAVE_consttable_2
7367 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7371 #ifdef HAVE_consttable_4
7373 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7377 #ifdef HAVE_consttable_8
7379 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7393 minipool_vector_head = minipool_vector_tail = NULL;
7394 scan = emit_insn_after (gen_consttable_end (), scan);
7395 scan = emit_barrier_after (scan);
7398 /* Return the cost of forcibly inserting a barrier after INSN. */
7400 arm_barrier_cost (rtx insn)
7402 /* Basing the location of the pool on the loop depth is preferable,
7403 but at the moment, the basic block information seems to be
7404 corrupt by this stage of the compilation. */
7406 rtx next = next_nonnote_insn (insn);
7408 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7411 switch (GET_CODE (insn))
7414 /* It will always be better to place the table before the label, rather
7423 return base_cost - 10;
7426 return base_cost + 10;
7430 /* Find the best place in the insn stream in the range
7431 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7432 Create the barrier by inserting a jump and add a new fix entry for
7435 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7437 HOST_WIDE_INT count = 0;
7439 rtx from = fix->insn;
7440 rtx selected = from;
7442 HOST_WIDE_INT selected_address;
7444 HOST_WIDE_INT max_count = max_address - fix->address;
7445 rtx label = gen_label_rtx ();
7447 selected_cost = arm_barrier_cost (from);
7448 selected_address = fix->address;
7450 while (from && count < max_count)
7455 /* This code shouldn't have been called if there was a natural barrier
7457 if (GET_CODE (from) == BARRIER)
7460 /* Count the length of this insn. */
7461 count += get_attr_length (from);
7463 /* If there is a jump table, add its length. */
7464 tmp = is_jump_table (from);
7467 count += get_jump_table_size (tmp);
7469 /* Jump tables aren't in a basic block, so base the cost on
7470 the dispatch insn. If we select this location, we will
7471 still put the pool after the table. */
7472 new_cost = arm_barrier_cost (from);
7474 if (count < max_count && new_cost <= selected_cost)
7477 selected_cost = new_cost;
7478 selected_address = fix->address + count;
7481 /* Continue after the dispatch table. */
7482 from = NEXT_INSN (tmp);
7486 new_cost = arm_barrier_cost (from);
7488 if (count < max_count && new_cost <= selected_cost)
7491 selected_cost = new_cost;
7492 selected_address = fix->address + count;
7495 from = NEXT_INSN (from);
7498 /* Create a new JUMP_INSN that branches around a barrier. */
7499 from = emit_jump_insn_after (gen_jump (label), selected);
7500 JUMP_LABEL (from) = label;
7501 barrier = emit_barrier_after (from);
7502 emit_label_after (label, barrier);
7504 /* Create a minipool barrier entry for the new barrier. */
7505 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7506 new_fix->insn = barrier;
7507 new_fix->address = selected_address;
7508 new_fix->next = fix->next;
7509 fix->next = new_fix;
7514 /* Record that there is a natural barrier in the insn stream at
7517 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7519 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7522 fix->address = address;
7525 if (minipool_fix_head != NULL)
7526 minipool_fix_tail->next = fix;
7528 minipool_fix_head = fix;
7530 minipool_fix_tail = fix;
7533 /* Record INSN, which will need fixing up to load a value from the
7534 minipool. ADDRESS is the offset of the insn since the start of the
7535 function; LOC is a pointer to the part of the insn which requires
7536 fixing; VALUE is the constant that must be loaded, which is of type
7539 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7540 enum machine_mode mode, rtx value)
7542 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7544 #ifdef AOF_ASSEMBLER
7545 /* PIC symbol references need to be converted into offsets into the
7547 /* XXX This shouldn't be done here. */
7548 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7549 value = aof_pic_entry (value);
7550 #endif /* AOF_ASSEMBLER */
7553 fix->address = address;
7556 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7558 fix->forwards = get_attr_pool_range (insn);
7559 fix->backwards = get_attr_neg_pool_range (insn);
7560 fix->minipool = NULL;
7562 /* If an insn doesn't have a range defined for it, then it isn't
7563 expecting to be reworked by this code. Better to abort now than
7564 to generate duff assembly code. */
7565 if (fix->forwards == 0 && fix->backwards == 0)
7568 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7569 So there might be an empty word before the start of the pool.
7570 Hence we reduce the forward range by 4 to allow for this
7572 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7578 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7579 GET_MODE_NAME (mode),
7580 INSN_UID (insn), (unsigned long) address,
7581 -1 * (long)fix->backwards, (long)fix->forwards);
7582 arm_print_value (dump_file, fix->value);
7583 fprintf (dump_file, "\n");
7586 /* Add it to the chain of fixes. */
7589 if (minipool_fix_head != NULL)
7590 minipool_fix_tail->next = fix;
7592 minipool_fix_head = fix;
7594 minipool_fix_tail = fix;
7597 /* Scan INSN and note any of its operands that need fixing.
7598 If DO_PUSHES is false we do not actually push any of the fixups
7599 needed. The function returns TRUE is any fixups were needed/pushed.
7600 This is used by arm_memory_load_p() which needs to know about loads
7601 of constants that will be converted into minipool loads. */
7603 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7605 bool result = false;
7608 extract_insn (insn);
7610 if (!constrain_operands (1))
7611 fatal_insn_not_found (insn);
7613 if (recog_data.n_alternatives == 0)
7616 /* Fill in recog_op_alt with information about the constraints of this insn. */
7617 preprocess_constraints ();
7619 for (opno = 0; opno < recog_data.n_operands; opno++)
7621 /* Things we need to fix can only occur in inputs. */
7622 if (recog_data.operand_type[opno] != OP_IN)
7625 /* If this alternative is a memory reference, then any mention
7626 of constants in this alternative is really to fool reload
7627 into allowing us to accept one there. We need to fix them up
7628 now so that we output the right code. */
7629 if (recog_op_alt[opno][which_alternative].memory_ok)
7631 rtx op = recog_data.operand[opno];
7633 if (CONSTANT_P (op))
7636 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7637 recog_data.operand_mode[opno], op);
7640 else if (GET_CODE (op) == MEM
7641 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7642 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7646 rtx cop = avoid_constant_pool_reference (op);
7648 /* Casting the address of something to a mode narrower
7649 than a word can cause avoid_constant_pool_reference()
7650 to return the pool reference itself. That's no good to
7651 us here. Lets just hope that we can use the
7652 constant pool value directly. */
7654 cop = get_pool_constant (XEXP (op, 0));
7656 push_minipool_fix (insn, address,
7657 recog_data.operand_loc[opno],
7658 recog_data.operand_mode[opno], cop);
7669 /* Gcc puts the pool in the wrong place for ARM, since we can only
7670 load addresses a limited distance around the pc. We do some
7671 special munging to move the constant pool values to the correct
7672 point in the code. */
7677 HOST_WIDE_INT address = 0;
7680 minipool_fix_head = minipool_fix_tail = NULL;
7682 /* The first insn must always be a note, or the code below won't
7683 scan it properly. */
7684 insn = get_insns ();
7685 if (GET_CODE (insn) != NOTE)
7688 /* Scan all the insns and record the operands that will need fixing. */
7689 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7691 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7692 && (arm_cirrus_insn_p (insn)
7693 || GET_CODE (insn) == JUMP_INSN
7694 || arm_memory_load_p (insn)))
7695 cirrus_reorg (insn);
7697 if (GET_CODE (insn) == BARRIER)
7698 push_minipool_barrier (insn, address);
7699 else if (INSN_P (insn))
7703 note_invalid_constants (insn, address, true);
7704 address += get_attr_length (insn);
7706 /* If the insn is a vector jump, add the size of the table
7707 and skip the table. */
7708 if ((table = is_jump_table (insn)) != NULL)
7710 address += get_jump_table_size (table);
7716 fix = minipool_fix_head;
7718 /* Now scan the fixups and perform the required changes. */
7723 Mfix * last_added_fix;
7724 Mfix * last_barrier = NULL;
7727 /* Skip any further barriers before the next fix. */
7728 while (fix && GET_CODE (fix->insn) == BARRIER)
7731 /* No more fixes. */
7735 last_added_fix = NULL;
7737 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7739 if (GET_CODE (ftmp->insn) == BARRIER)
7741 if (ftmp->address >= minipool_vector_head->max_address)
7744 last_barrier = ftmp;
7746 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7749 last_added_fix = ftmp; /* Keep track of the last fix added. */
7752 /* If we found a barrier, drop back to that; any fixes that we
7753 could have reached but come after the barrier will now go in
7754 the next mini-pool. */
7755 if (last_barrier != NULL)
7757 /* Reduce the refcount for those fixes that won't go into this
7759 for (fdel = last_barrier->next;
7760 fdel && fdel != ftmp;
7763 fdel->minipool->refcount--;
7764 fdel->minipool = NULL;
7767 ftmp = last_barrier;
7771 /* ftmp is first fix that we can't fit into this pool and
7772 there no natural barriers that we could use. Insert a
7773 new barrier in the code somewhere between the previous
7774 fix and this one, and arrange to jump around it. */
7775 HOST_WIDE_INT max_address;
7777 /* The last item on the list of fixes must be a barrier, so
7778 we can never run off the end of the list of fixes without
7779 last_barrier being set. */
7783 max_address = minipool_vector_head->max_address;
7784 /* Check that there isn't another fix that is in range that
7785 we couldn't fit into this pool because the pool was
7786 already too large: we need to put the pool before such an
7788 if (ftmp->address < max_address)
7789 max_address = ftmp->address;
7791 last_barrier = create_fix_barrier (last_added_fix, max_address);
7794 assign_minipool_offsets (last_barrier);
7798 if (GET_CODE (ftmp->insn) != BARRIER
7799 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7806 /* Scan over the fixes we have identified for this pool, fixing them
7807 up and adding the constants to the pool itself. */
7808 for (this_fix = fix; this_fix && ftmp != this_fix;
7809 this_fix = this_fix->next)
7810 if (GET_CODE (this_fix->insn) != BARRIER)
7813 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7814 minipool_vector_label),
7815 this_fix->minipool->offset);
7816 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7819 dump_minipool (last_barrier->insn);
7823 /* From now on we must synthesize any constants that we can't handle
7824 directly. This can happen if the RTL gets split during final
7825 instruction generation. */
7826 after_arm_reorg = 1;
7828 /* Free the minipool memory. */
7829 obstack_free (&minipool_obstack, minipool_startobj);
7832 /* Routines to output assembly language. */
7834 /* If the rtx is the correct value then return the string of the number.
7835 In this way we can ensure that valid double constants are generated even
7836 when cross compiling. */
7838 fp_immediate_constant (rtx x)
7843 if (!fp_consts_inited)
7846 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7847 for (i = 0; i < 8; i++)
7848 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7849 return strings_fp[i];
7854 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7856 fp_const_from_val (REAL_VALUE_TYPE *r)
7860 if (!fp_consts_inited)
7863 for (i = 0; i < 8; i++)
7864 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7865 return strings_fp[i];
7870 /* Output the operands of a LDM/STM instruction to STREAM.
7871 MASK is the ARM register set mask of which only bits 0-15 are important.
7872 REG is the base register, either the frame pointer or the stack pointer,
7873 INSTR is the possibly suffixed load or store instruction. */
7875 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7878 int not_first = FALSE;
7880 fputc ('\t', stream);
7881 asm_fprintf (stream, instr, reg);
7882 fputs (", {", stream);
7884 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7885 if (mask & (1 << i))
7888 fprintf (stream, ", ");
7890 asm_fprintf (stream, "%r", i);
7894 fprintf (stream, "}\n");
7898 /* Output a FLDMX instruction to STREAM.
7899 BASE if the register containing the address.
7900 REG and COUNT specify the register range.
7901 Extra registers may be added to avoid hardware bugs. */
7904 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7908 /* Workaround ARM10 VFPr1 bug. */
7909 if (count == 2 && !arm_arch6)
7916 fputc ('\t', stream);
7917 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7919 for (i = reg; i < reg + count; i++)
7922 fputs (", ", stream);
7923 asm_fprintf (stream, "d%d", i);
7925 fputs ("}\n", stream);
7930 /* Output the assembly for a store multiple. */
7933 vfp_output_fstmx (rtx * operands)
7940 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7941 p = strlen (pattern);
7943 if (GET_CODE (operands[1]) != REG)
7946 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7947 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7949 p += sprintf (&pattern[p], ", d%d", base + i);
7951 strcpy (&pattern[p], "}");
7953 output_asm_insn (pattern, operands);
7958 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7959 number of bytes pushed. */
7962 vfp_emit_fstmx (int base_reg, int count)
7969 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7970 register pairs are stored by a store multiple insn. We avoid this
7971 by pushing an extra pair. */
7972 if (count == 2 && !arm_arch6)
7974 if (base_reg == LAST_VFP_REGNUM - 3)
7979 /* ??? The frame layout is implementation defined. We describe
7980 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7981 We really need some way of representing the whole block so that the
7982 unwinder can figure it out at runtime. */
7983 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7984 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7986 reg = gen_rtx_REG (DFmode, base_reg);
7990 = gen_rtx_SET (VOIDmode,
7991 gen_rtx_MEM (BLKmode,
7992 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7993 gen_rtx_UNSPEC (BLKmode,
7997 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7998 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7999 GEN_INT (-(count * 8 + 4))));
8000 RTX_FRAME_RELATED_P (tmp) = 1;
8001 XVECEXP (dwarf, 0, 0) = tmp;
8003 tmp = gen_rtx_SET (VOIDmode,
8004 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8006 RTX_FRAME_RELATED_P (tmp) = 1;
8007 XVECEXP (dwarf, 0, 1) = tmp;
8009 for (i = 1; i < count; i++)
8011 reg = gen_rtx_REG (DFmode, base_reg);
8013 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8015 tmp = gen_rtx_SET (VOIDmode,
8016 gen_rtx_MEM (DFmode,
8017 gen_rtx_PLUS (SImode,
8021 RTX_FRAME_RELATED_P (tmp) = 1;
8022 XVECEXP (dwarf, 0, i + 1) = tmp;
8025 par = emit_insn (par);
8026 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8028 RTX_FRAME_RELATED_P (par) = 1;
8030 return count * 8 + 4;
8034 /* Output a 'call' insn. */
8036 output_call (rtx *operands)
8039 abort (); /* Patterns should call blx <reg> directly. */
8041 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8042 if (REGNO (operands[0]) == LR_REGNUM)
8044 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8045 output_asm_insn ("mov%?\t%0, %|lr", operands);
8048 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8050 if (TARGET_INTERWORK || arm_arch4t)
8051 output_asm_insn ("bx%?\t%0", operands);
8053 output_asm_insn ("mov%?\t%|pc, %0", operands);
8058 /* Output a 'call' insn that is a reference in memory. */
8060 output_call_mem (rtx *operands)
8062 if (TARGET_INTERWORK && !arm_arch5)
8064 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8065 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8066 output_asm_insn ("bx%?\t%|ip", operands);
8068 else if (regno_use_in (LR_REGNUM, operands[0]))
8070 /* LR is used in the memory address. We load the address in the
8071 first instruction. It's safe to use IP as the target of the
8072 load since the call will kill it anyway. */
8073 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8075 output_asm_insn ("blx%?%|ip", operands);
8078 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8080 output_asm_insn ("bx%?\t%|ip", operands);
8082 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8087 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8088 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8095 /* Output a move from arm registers to an fpa registers.
8096 OPERANDS[0] is an fpa register.
8097 OPERANDS[1] is the first registers of an arm register pair. */
8099 output_mov_long_double_fpa_from_arm (rtx *operands)
8101 int arm_reg0 = REGNO (operands[1]);
8104 if (arm_reg0 == IP_REGNUM)
8107 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8108 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8109 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8111 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8112 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8117 /* Output a move from an fpa register to arm registers.
8118 OPERANDS[0] is the first registers of an arm register pair.
8119 OPERANDS[1] is an fpa register. */
8121 output_mov_long_double_arm_from_fpa (rtx *operands)
8123 int arm_reg0 = REGNO (operands[0]);
8126 if (arm_reg0 == IP_REGNUM)
8129 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8130 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8131 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8133 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8134 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8138 /* Output a move from arm registers to arm registers of a long double
8139 OPERANDS[0] is the destination.
8140 OPERANDS[1] is the source. */
8142 output_mov_long_double_arm_from_arm (rtx *operands)
8144 /* We have to be careful here because the two might overlap. */
8145 int dest_start = REGNO (operands[0]);
8146 int src_start = REGNO (operands[1]);
8150 if (dest_start < src_start)
8152 for (i = 0; i < 3; i++)
8154 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8155 ops[1] = gen_rtx_REG (SImode, src_start + i);
8156 output_asm_insn ("mov%?\t%0, %1", ops);
8161 for (i = 2; i >= 0; i--)
8163 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8164 ops[1] = gen_rtx_REG (SImode, src_start + i);
8165 output_asm_insn ("mov%?\t%0, %1", ops);
8173 /* Output a move from arm registers to an fpa registers.
8174 OPERANDS[0] is an fpa register.
8175 OPERANDS[1] is the first registers of an arm register pair. */
8177 output_mov_double_fpa_from_arm (rtx *operands)
8179 int arm_reg0 = REGNO (operands[1]);
8182 if (arm_reg0 == IP_REGNUM)
8185 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8186 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8187 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8188 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8192 /* Output a move from an fpa register to arm registers.
8193 OPERANDS[0] is the first registers of an arm register pair.
8194 OPERANDS[1] is an fpa register. */
8196 output_mov_double_arm_from_fpa (rtx *operands)
8198 int arm_reg0 = REGNO (operands[0]);
8201 if (arm_reg0 == IP_REGNUM)
8204 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8205 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8206 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8207 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8211 /* Output a move between double words.
8212 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8213 or MEM<-REG and all MEMs must be offsettable addresses. */
8215 output_move_double (rtx *operands)
8217 enum rtx_code code0 = GET_CODE (operands[0]);
8218 enum rtx_code code1 = GET_CODE (operands[1]);
8223 int reg0 = REGNO (operands[0]);
8225 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8229 int reg1 = REGNO (operands[1]);
8230 if (reg1 == IP_REGNUM)
8233 /* Ensure the second source is not overwritten. */
8234 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8235 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8237 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8239 else if (code1 == CONST_VECTOR)
8241 HOST_WIDE_INT hint = 0;
8243 switch (GET_MODE (operands[1]))
8246 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8247 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8251 if (BYTES_BIG_ENDIAN)
8253 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8255 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8259 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8261 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8264 otherops[1] = GEN_INT (hint);
8267 if (BYTES_BIG_ENDIAN)
8269 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8271 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8275 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8277 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8280 operands[1] = GEN_INT (hint);
8284 if (BYTES_BIG_ENDIAN)
8286 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8288 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8290 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8292 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8296 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8298 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8300 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8302 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8305 otherops[1] = GEN_INT (hint);
8308 if (BYTES_BIG_ENDIAN)
8310 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8312 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8314 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8316 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8320 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8322 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8324 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8326 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8329 operands[1] = GEN_INT (hint);
8335 output_mov_immediate (operands);
8336 output_mov_immediate (otherops);
8338 else if (code1 == CONST_DOUBLE)
8340 if (GET_MODE (operands[1]) == DFmode)
8345 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8346 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8347 otherops[1] = GEN_INT (l[1]);
8348 operands[1] = GEN_INT (l[0]);
8350 else if (GET_MODE (operands[1]) != VOIDmode)
8352 else if (WORDS_BIG_ENDIAN)
8354 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8355 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8359 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8360 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8363 output_mov_immediate (operands);
8364 output_mov_immediate (otherops);
8366 else if (code1 == CONST_INT)
8368 #if HOST_BITS_PER_WIDE_INT > 32
8369 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8370 what the upper word is. */
8371 if (WORDS_BIG_ENDIAN)
8373 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8374 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8378 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8379 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8382 /* Sign extend the intval into the high-order word. */
8383 if (WORDS_BIG_ENDIAN)
8385 otherops[1] = operands[1];
8386 operands[1] = (INTVAL (operands[1]) < 0
8387 ? constm1_rtx : const0_rtx);
8390 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8392 output_mov_immediate (otherops);
8393 output_mov_immediate (operands);
8395 else if (code1 == MEM)
8397 switch (GET_CODE (XEXP (operands[1], 0)))
8400 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8405 abort (); /* Should never happen now. */
8406 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8410 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8414 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8419 abort (); /* Should never happen now. */
8420 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8425 otherops[0] = operands[0];
8426 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8427 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8429 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8431 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8433 /* Registers overlap so split out the increment. */
8434 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8435 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8438 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8442 /* We only allow constant increments, so this is safe. */
8443 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8449 output_asm_insn ("adr%?\t%0, %1", operands);
8450 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8454 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8455 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8457 otherops[0] = operands[0];
8458 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8459 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8461 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8463 if (GET_CODE (otherops[2]) == CONST_INT)
8465 switch ((int) INTVAL (otherops[2]))
8468 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8471 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8474 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8479 && (GET_CODE (otherops[2]) == REG
8480 || (GET_CODE (otherops[2]) == CONST_INT
8481 && INTVAL (otherops[2]) > -256
8482 && INTVAL (otherops[2]) < 256)))
8484 if (reg_overlap_mentioned_p (otherops[0],
8487 /* Swap base and index registers over to
8488 avoid a conflict. */
8489 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8490 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8493 /* If both registers conflict, it will usually
8494 have been fixed by a splitter. */
8495 if (reg_overlap_mentioned_p (otherops[0],
8498 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8499 output_asm_insn ("ldr%?d\t%0, [%1]",
8505 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8510 if (GET_CODE (otherops[2]) == CONST_INT)
8512 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8513 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8515 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8518 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8521 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8523 return "ldm%?ia\t%0, %M0";
8527 otherops[1] = adjust_address (operands[1], SImode, 4);
8528 /* Take care of overlapping base/data reg. */
8529 if (reg_mentioned_p (operands[0], operands[1]))
8531 output_asm_insn ("ldr%?\t%0, %1", otherops);
8532 output_asm_insn ("ldr%?\t%0, %1", operands);
8536 output_asm_insn ("ldr%?\t%0, %1", operands);
8537 output_asm_insn ("ldr%?\t%0, %1", otherops);
8543 abort (); /* Constraints should prevent this. */
8545 else if (code0 == MEM && code1 == REG)
8547 if (REGNO (operands[1]) == IP_REGNUM)
8550 switch (GET_CODE (XEXP (operands[0], 0)))
8553 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8558 abort (); /* Should never happen now. */
8559 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8563 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8567 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8572 abort (); /* Should never happen now. */
8573 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8578 otherops[0] = operands[1];
8579 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8580 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8582 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8583 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8585 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8589 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8590 if (GET_CODE (otherops[2]) == CONST_INT)
8592 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8595 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8599 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8603 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8608 && (GET_CODE (otherops[2]) == REG
8609 || (GET_CODE (otherops[2]) == CONST_INT
8610 && INTVAL (otherops[2]) > -256
8611 && INTVAL (otherops[2]) < 256)))
8613 otherops[0] = operands[1];
8614 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8615 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8621 otherops[0] = adjust_address (operands[0], SImode, 4);
8622 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8623 output_asm_insn ("str%?\t%1, %0", operands);
8624 output_asm_insn ("str%?\t%1, %0", otherops);
8628 /* Constraints should prevent this. */
8635 /* Output an arbitrary MOV reg, #n.
8636 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8638 output_mov_immediate (rtx *operands)
8640 HOST_WIDE_INT n = INTVAL (operands[1]);
8642 /* Try to use one MOV. */
8643 if (const_ok_for_arm (n))
8644 output_asm_insn ("mov%?\t%0, %1", operands);
8646 /* Try to use one MVN. */
8647 else if (const_ok_for_arm (~n))
8649 operands[1] = GEN_INT (~n);
8650 output_asm_insn ("mvn%?\t%0, %1", operands);
8657 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8658 for (i = 0; i < 32; i++)
8662 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8663 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8665 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8671 /* Output an ADD r, s, #n where n may be too big for one instruction.
8672 If adding zero to one register, output nothing. */
8674 output_add_immediate (rtx *operands)
8676 HOST_WIDE_INT n = INTVAL (operands[2]);
8678 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8681 output_multi_immediate (operands,
8682 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8685 output_multi_immediate (operands,
8686 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8693 /* Output a multiple immediate operation.
8694 OPERANDS is the vector of operands referred to in the output patterns.
8695 INSTR1 is the output pattern to use for the first constant.
8696 INSTR2 is the output pattern to use for subsequent constants.
8697 IMMED_OP is the index of the constant slot in OPERANDS.
8698 N is the constant value. */
8700 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8701 int immed_op, HOST_WIDE_INT n)
8703 #if HOST_BITS_PER_WIDE_INT > 32
8709 /* Quick and easy output. */
8710 operands[immed_op] = const0_rtx;
8711 output_asm_insn (instr1, operands);
8716 const char * instr = instr1;
8718 /* Note that n is never zero here (which would give no output). */
8719 for (i = 0; i < 32; i += 2)
8723 operands[immed_op] = GEN_INT (n & (255 << i));
8724 output_asm_insn (instr, operands);
8734 /* Return the appropriate ARM instruction for the operation code.
8735 The returned result should not be overwritten. OP is the rtx of the
8736 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8739 arithmetic_instr (rtx op, int shift_first_arg)
8741 switch (GET_CODE (op))
8747 return shift_first_arg ? "rsb" : "sub";
8763 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8764 for the operation code. The returned result should not be overwritten.
8765 OP is the rtx code of the shift.
8766 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8769 shift_op (rtx op, HOST_WIDE_INT *amountp)
8772 enum rtx_code code = GET_CODE (op);
8774 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8776 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8777 *amountp = INTVAL (XEXP (op, 1));
8800 /* We never have to worry about the amount being other than a
8801 power of 2, since this case can never be reloaded from a reg. */
8803 *amountp = int_log2 (*amountp);
8814 /* This is not 100% correct, but follows from the desire to merge
8815 multiplication by a power of 2 with the recognizer for a
8816 shift. >=32 is not a valid shift for "asl", so we must try and
8817 output a shift that produces the correct arithmetical result.
8818 Using lsr #32 is identical except for the fact that the carry bit
8819 is not set correctly if we set the flags; but we never use the
8820 carry bit from such an operation, so we can ignore that. */
8821 if (code == ROTATERT)
8822 /* Rotate is just modulo 32. */
8824 else if (*amountp != (*amountp & 31))
8831 /* Shifts of 0 are no-ops. */
8839 /* Obtain the shift from the POWER of two. */
8841 static HOST_WIDE_INT
8842 int_log2 (HOST_WIDE_INT power)
8844 HOST_WIDE_INT shift = 0;
8846 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8856 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8857 /bin/as is horribly restrictive. */
8858 #define MAX_ASCII_LEN 51
8861 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8866 fputs ("\t.ascii\t\"", stream);
8868 for (i = 0; i < len; i++)
8872 if (len_so_far >= MAX_ASCII_LEN)
8874 fputs ("\"\n\t.ascii\t\"", stream);
8881 fputs ("\\t", stream);
8886 fputs ("\\f", stream);
8891 fputs ("\\b", stream);
8896 fputs ("\\r", stream);
8900 case TARGET_NEWLINE:
8901 fputs ("\\n", stream);
8903 if ((c >= ' ' && c <= '~')
8905 /* This is a good place for a line break. */
8906 len_so_far = MAX_ASCII_LEN;
8913 putc ('\\', stream);
8918 if (c >= ' ' && c <= '~')
8925 fprintf (stream, "\\%03o", c);
8932 fputs ("\"\n", stream);
8935 /* Compute the register sabe mask for registers 0 through 12
8936 inclusive. This code is used by arm_compute_save_reg_mask. */
8937 static unsigned long
8938 arm_compute_save_reg0_reg12_mask (void)
8940 unsigned long func_type = arm_current_func_type ();
8941 unsigned int save_reg_mask = 0;
8944 if (IS_INTERRUPT (func_type))
8946 unsigned int max_reg;
8947 /* Interrupt functions must not corrupt any registers,
8948 even call clobbered ones. If this is a leaf function
8949 we can just examine the registers used by the RTL, but
8950 otherwise we have to assume that whatever function is
8951 called might clobber anything, and so we have to save
8952 all the call-clobbered registers as well. */
8953 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8954 /* FIQ handlers have registers r8 - r12 banked, so
8955 we only need to check r0 - r7, Normal ISRs only
8956 bank r14 and r15, so we must check up to r12.
8957 r13 is the stack pointer which is always preserved,
8958 so we do not need to consider it here. */
8963 for (reg = 0; reg <= max_reg; reg++)
8964 if (regs_ever_live[reg]
8965 || (! current_function_is_leaf && call_used_regs [reg]))
8966 save_reg_mask |= (1 << reg);
8970 /* In the normal case we only need to save those registers
8971 which are call saved and which are used by this function. */
8972 for (reg = 0; reg <= 10; reg++)
8973 if (regs_ever_live[reg] && ! call_used_regs [reg])
8974 save_reg_mask |= (1 << reg);
8976 /* Handle the frame pointer as a special case. */
8977 if (! TARGET_APCS_FRAME
8978 && ! frame_pointer_needed
8979 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8980 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8981 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8983 /* If we aren't loading the PIC register,
8984 don't stack it even though it may be live. */
8986 && ! TARGET_SINGLE_PIC_BASE
8987 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8988 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8991 return save_reg_mask;
8994 /* Compute a bit mask of which registers need to be
8995 saved on the stack for the current function. */
8997 static unsigned long
8998 arm_compute_save_reg_mask (void)
9000 unsigned int save_reg_mask = 0;
9001 unsigned long func_type = arm_current_func_type ();
9003 if (IS_NAKED (func_type))
9004 /* This should never really happen. */
9007 /* If we are creating a stack frame, then we must save the frame pointer,
9008 IP (which will hold the old stack pointer), LR and the PC. */
9009 if (frame_pointer_needed)
9011 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9016 /* Volatile functions do not return, so there
9017 is no need to save any other registers. */
9018 if (IS_VOLATILE (func_type))
9019 return save_reg_mask;
9021 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9023 /* Decide if we need to save the link register.
9024 Interrupt routines have their own banked link register,
9025 so they never need to save it.
9026 Otherwise if we do not use the link register we do not need to save
9027 it. If we are pushing other registers onto the stack however, we
9028 can save an instruction in the epilogue by pushing the link register
9029 now and then popping it back into the PC. This incurs extra memory
9030 accesses though, so we only do it when optimizing for size, and only
9031 if we know that we will not need a fancy return sequence. */
9032 if (regs_ever_live [LR_REGNUM]
9035 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
9036 save_reg_mask |= 1 << LR_REGNUM;
9038 if (cfun->machine->lr_save_eliminated)
9039 save_reg_mask &= ~ (1 << LR_REGNUM);
9041 if (TARGET_REALLY_IWMMXT
9042 && ((bit_count (save_reg_mask)
9043 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9047 /* The total number of registers that are going to be pushed
9048 onto the stack is odd. We need to ensure that the stack
9049 is 64-bit aligned before we start to save iWMMXt registers,
9050 and also before we start to create locals. (A local variable
9051 might be a double or long long which we will load/store using
9052 an iWMMXt instruction). Therefore we need to push another
9053 ARM register, so that the stack will be 64-bit aligned. We
9054 try to avoid using the arg registers (r0 -r3) as they might be
9055 used to pass values in a tail call. */
9056 for (reg = 4; reg <= 12; reg++)
9057 if ((save_reg_mask & (1 << reg)) == 0)
9061 save_reg_mask |= (1 << reg);
9064 cfun->machine->sibcall_blocked = 1;
9065 save_reg_mask |= (1 << 3);
9069 return save_reg_mask;
9073 /* Return the number of bytes required to save VFP registers. */
9075 arm_get_vfp_saved_size (void)
9082 /* Space for saved VFP registers. */
9083 if (TARGET_HARD_FLOAT && TARGET_VFP)
9086 for (regno = FIRST_VFP_REGNUM;
9087 regno < LAST_VFP_REGNUM;
9090 if ((!regs_ever_live[regno] || call_used_regs[regno])
9091 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9095 /* Workaround ARM10 VFPr1 bug. */
9096 if (count == 2 && !arm_arch6)
9098 saved += count * 8 + 4;
9107 if (count == 2 && !arm_arch6)
9109 saved += count * 8 + 4;
9116 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9117 everything bar the final return instruction. */
9119 output_return_instruction (rtx operand, int really_return, int reverse)
9121 char conditional[10];
9124 unsigned long live_regs_mask;
9125 unsigned long func_type;
9126 arm_stack_offsets *offsets;
9128 func_type = arm_current_func_type ();
9130 if (IS_NAKED (func_type))
9133 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9135 /* If this function was declared non-returning, and we have
9136 found a tail call, then we have to trust that the called
9137 function won't return. */
9142 /* Otherwise, trap an attempted return by aborting. */
9144 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9146 assemble_external_libcall (ops[1]);
9147 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9153 if (current_function_calls_alloca && !really_return)
9156 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9158 return_used_this_function = 1;
9160 live_regs_mask = arm_compute_save_reg_mask ();
9164 const char * return_reg;
9166 /* If we do not have any special requirements for function exit
9167 (eg interworking, or ISR) then we can load the return address
9168 directly into the PC. Otherwise we must load it into LR. */
9170 && ! TARGET_INTERWORK)
9171 return_reg = reg_names[PC_REGNUM];
9173 return_reg = reg_names[LR_REGNUM];
9175 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9177 /* There are three possible reasons for the IP register
9178 being saved. 1) a stack frame was created, in which case
9179 IP contains the old stack pointer, or 2) an ISR routine
9180 corrupted it, or 3) it was saved to align the stack on
9181 iWMMXt. In case 1, restore IP into SP, otherwise just
9183 if (frame_pointer_needed)
9185 live_regs_mask &= ~ (1 << IP_REGNUM);
9186 live_regs_mask |= (1 << SP_REGNUM);
9190 if (! IS_INTERRUPT (func_type)
9191 && ! TARGET_REALLY_IWMMXT)
9196 /* On some ARM architectures it is faster to use LDR rather than
9197 LDM to load a single register. On other architectures, the
9198 cost is the same. In 26 bit mode, or for exception handlers,
9199 we have to use LDM to load the PC so that the CPSR is also
9201 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9203 if (live_regs_mask == (unsigned int)(1 << reg))
9206 if (reg <= LAST_ARM_REGNUM
9207 && (reg != LR_REGNUM
9209 || ! IS_INTERRUPT (func_type)))
9211 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9212 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9219 /* Generate the load multiple instruction to restore the
9220 registers. Note we can get here, even if
9221 frame_pointer_needed is true, but only if sp already
9222 points to the base of the saved core registers. */
9223 if (live_regs_mask & (1 << SP_REGNUM))
9225 unsigned HOST_WIDE_INT stack_adjust;
9227 offsets = arm_get_frame_offsets ();
9228 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9229 if (stack_adjust != 0 && stack_adjust != 4)
9232 if (stack_adjust && arm_arch5)
9233 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9236 /* If we can't use ldmib (SA110 bug), then try to pop r3
9239 live_regs_mask |= 1 << 3;
9240 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9244 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9246 p = instr + strlen (instr);
9248 for (reg = 0; reg <= SP_REGNUM; reg++)
9249 if (live_regs_mask & (1 << reg))
9251 int l = strlen (reg_names[reg]);
9257 memcpy (p, ", ", 2);
9261 memcpy (p, "%|", 2);
9262 memcpy (p + 2, reg_names[reg], l);
9266 if (live_regs_mask & (1 << LR_REGNUM))
9268 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9269 /* If returning from an interrupt, restore the CPSR. */
9270 if (IS_INTERRUPT (func_type))
9277 output_asm_insn (instr, & operand);
9279 /* See if we need to generate an extra instruction to
9280 perform the actual function return. */
9282 && func_type != ARM_FT_INTERWORKED
9283 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9285 /* The return has already been handled
9286 by loading the LR into the PC. */
9293 switch ((int) ARM_FUNC_TYPE (func_type))
9297 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9300 case ARM_FT_INTERWORKED:
9301 sprintf (instr, "bx%s\t%%|lr", conditional);
9304 case ARM_FT_EXCEPTION:
9305 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9309 /* Use bx if it's available. */
9310 if (arm_arch5 || arm_arch4t)
9311 sprintf (instr, "bx%s\t%%|lr", conditional);
9313 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9317 output_asm_insn (instr, & operand);
9323 /* Write the function name into the code section, directly preceding
9324 the function prologue.
9326 Code will be output similar to this:
9328 .ascii "arm_poke_function_name", 0
9331 .word 0xff000000 + (t1 - t0)
9332 arm_poke_function_name
9334 stmfd sp!, {fp, ip, lr, pc}
9337 When performing a stack backtrace, code can inspect the value
9338 of 'pc' stored at 'fp' + 0. If the trace function then looks
9339 at location pc - 12 and the top 8 bits are set, then we know
9340 that there is a function name embedded immediately preceding this
9341 location and has length ((pc[-3]) & 0xff000000).
9343 We assume that pc is declared as a pointer to an unsigned long.
9345 It is of no benefit to output the function name if we are assembling
9346 a leaf function. These function types will not contain a stack
9347 backtrace structure, therefore it is not possible to determine the
9350 arm_poke_function_name (FILE *stream, const char *name)
9352 unsigned long alignlength;
9353 unsigned long length;
9356 length = strlen (name) + 1;
9357 alignlength = ROUND_UP_WORD (length);
9359 ASM_OUTPUT_ASCII (stream, name, length);
9360 ASM_OUTPUT_ALIGN (stream, 2);
9361 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9362 assemble_aligned_integer (UNITS_PER_WORD, x);
9365 /* Place some comments into the assembler stream
9366 describing the current function. */
9368 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9370 unsigned long func_type;
9374 thumb_output_function_prologue (f, frame_size);
9379 if (arm_ccfsm_state || arm_target_insn)
9382 func_type = arm_current_func_type ();
9384 switch ((int) ARM_FUNC_TYPE (func_type))
9389 case ARM_FT_INTERWORKED:
9390 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9392 case ARM_FT_EXCEPTION_HANDLER:
9393 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9396 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9399 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9401 case ARM_FT_EXCEPTION:
9402 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9406 if (IS_NAKED (func_type))
9407 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9409 if (IS_VOLATILE (func_type))
9410 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9412 if (IS_NESTED (func_type))
9413 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9415 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9416 current_function_args_size,
9417 current_function_pretend_args_size, frame_size);
9419 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9420 frame_pointer_needed,
9421 cfun->machine->uses_anonymous_args);
9423 if (cfun->machine->lr_save_eliminated)
9424 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9426 #ifdef AOF_ASSEMBLER
9428 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9431 return_used_this_function = 0;
9435 arm_output_epilogue (rtx sibling)
9438 unsigned long saved_regs_mask;
9439 unsigned long func_type;
9440 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9441 frame that is $fp + 4 for a non-variadic function. */
9442 int floats_offset = 0;
9444 FILE * f = asm_out_file;
9445 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9446 unsigned int lrm_count = 0;
9447 int really_return = (sibling == NULL);
9449 arm_stack_offsets *offsets;
9451 /* If we have already generated the return instruction
9452 then it is futile to generate anything else. */
9453 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9456 func_type = arm_current_func_type ();
9458 if (IS_NAKED (func_type))
9459 /* Naked functions don't have epilogues. */
9462 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9466 /* A volatile function should never return. Call abort. */
9467 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9468 assemble_external_libcall (op);
9469 output_asm_insn ("bl\t%a0", &op);
9474 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9476 /* If we are throwing an exception, then we really must
9477 be doing a return, so we can't tail-call. */
9480 offsets = arm_get_frame_offsets ();
9481 saved_regs_mask = arm_compute_save_reg_mask ();
9484 lrm_count = bit_count (saved_regs_mask);
9486 floats_offset = offsets->saved_args;
9487 /* Compute how far away the floats will be. */
9488 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9489 if (saved_regs_mask & (1 << reg))
9492 if (frame_pointer_needed)
9494 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9495 int vfp_offset = offsets->frame;
9497 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9499 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9500 if (regs_ever_live[reg] && !call_used_regs[reg])
9502 floats_offset += 12;
9503 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9504 reg, FP_REGNUM, floats_offset - vfp_offset);
9509 start_reg = LAST_FPA_REGNUM;
9511 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9513 if (regs_ever_live[reg] && !call_used_regs[reg])
9515 floats_offset += 12;
9517 /* We can't unstack more than four registers at once. */
9518 if (start_reg - reg == 3)
9520 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9521 reg, FP_REGNUM, floats_offset - vfp_offset);
9522 start_reg = reg - 1;
9527 if (reg != start_reg)
9528 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9529 reg + 1, start_reg - reg,
9530 FP_REGNUM, floats_offset - vfp_offset);
9531 start_reg = reg - 1;
9535 /* Just in case the last register checked also needs unstacking. */
9536 if (reg != start_reg)
9537 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9538 reg + 1, start_reg - reg,
9539 FP_REGNUM, floats_offset - vfp_offset);
9542 if (TARGET_HARD_FLOAT && TARGET_VFP)
9546 /* The fldmx insn does not have base+offset addressing modes,
9547 so we use IP to hold the address. */
9548 saved_size = arm_get_vfp_saved_size ();
9552 floats_offset += saved_size;
9553 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9554 FP_REGNUM, floats_offset - vfp_offset);
9556 start_reg = FIRST_VFP_REGNUM;
9557 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9559 if ((!regs_ever_live[reg] || call_used_regs[reg])
9560 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9562 if (start_reg != reg)
9563 arm_output_fldmx (f, IP_REGNUM,
9564 (start_reg - FIRST_VFP_REGNUM) / 2,
9565 (reg - start_reg) / 2);
9566 start_reg = reg + 2;
9569 if (start_reg != reg)
9570 arm_output_fldmx (f, IP_REGNUM,
9571 (start_reg - FIRST_VFP_REGNUM) / 2,
9572 (reg - start_reg) / 2);
9577 /* The frame pointer is guaranteed to be non-double-word aligned.
9578 This is because it is set to (old_stack_pointer - 4) and the
9579 old_stack_pointer was double word aligned. Thus the offset to
9580 the iWMMXt registers to be loaded must also be non-double-word
9581 sized, so that the resultant address *is* double-word aligned.
9582 We can ignore floats_offset since that was already included in
9583 the live_regs_mask. */
9584 lrm_count += (lrm_count % 2 ? 2 : 1);
9586 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9587 if (regs_ever_live[reg] && !call_used_regs[reg])
9589 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9590 reg, FP_REGNUM, lrm_count * 4);
9595 /* saved_regs_mask should contain the IP, which at the time of stack
9596 frame generation actually contains the old stack pointer. So a
9597 quick way to unwind the stack is just pop the IP register directly
9598 into the stack pointer. */
9599 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9601 saved_regs_mask &= ~ (1 << IP_REGNUM);
9602 saved_regs_mask |= (1 << SP_REGNUM);
9604 /* There are two registers left in saved_regs_mask - LR and PC. We
9605 only need to restore the LR register (the return address), but to
9606 save time we can load it directly into the PC, unless we need a
9607 special function exit sequence, or we are not really returning. */
9608 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9609 /* Delete the LR from the register mask, so that the LR on
9610 the stack is loaded into the PC in the register mask. */
9611 saved_regs_mask &= ~ (1 << LR_REGNUM);
9613 saved_regs_mask &= ~ (1 << PC_REGNUM);
9615 /* We must use SP as the base register, because SP is one of the
9616 registers being restored. If an interrupt or page fault
9617 happens in the ldm instruction, the SP might or might not
9618 have been restored. That would be bad, as then SP will no
9619 longer indicate the safe area of stack, and we can get stack
9620 corruption. Using SP as the base register means that it will
9621 be reset correctly to the original value, should an interrupt
9622 occur. If the stack pointer already points at the right
9623 place, then omit the subtraction. */
9624 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9625 || current_function_calls_alloca)
9626 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9627 4 * bit_count (saved_regs_mask));
9628 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9630 if (IS_INTERRUPT (func_type))
9631 /* Interrupt handlers will have pushed the
9632 IP onto the stack, so restore it now. */
9633 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9637 /* Restore stack pointer if necessary. */
9638 if (offsets->outgoing_args != offsets->saved_regs)
9640 operands[0] = operands[1] = stack_pointer_rtx;
9641 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9642 output_add_immediate (operands);
9645 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9647 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9648 if (regs_ever_live[reg] && !call_used_regs[reg])
9649 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9654 start_reg = FIRST_FPA_REGNUM;
9656 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9658 if (regs_ever_live[reg] && !call_used_regs[reg])
9660 if (reg - start_reg == 3)
9662 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9663 start_reg, SP_REGNUM);
9664 start_reg = reg + 1;
9669 if (reg != start_reg)
9670 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9671 start_reg, reg - start_reg,
9674 start_reg = reg + 1;
9678 /* Just in case the last register checked also needs unstacking. */
9679 if (reg != start_reg)
9680 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9681 start_reg, reg - start_reg, SP_REGNUM);
9684 if (TARGET_HARD_FLOAT && TARGET_VFP)
9686 start_reg = FIRST_VFP_REGNUM;
9687 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9689 if ((!regs_ever_live[reg] || call_used_regs[reg])
9690 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9692 if (start_reg != reg)
9693 arm_output_fldmx (f, SP_REGNUM,
9694 (start_reg - FIRST_VFP_REGNUM) / 2,
9695 (reg - start_reg) / 2);
9696 start_reg = reg + 2;
9699 if (start_reg != reg)
9700 arm_output_fldmx (f, SP_REGNUM,
9701 (start_reg - FIRST_VFP_REGNUM) / 2,
9702 (reg - start_reg) / 2);
9705 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9706 if (regs_ever_live[reg] && !call_used_regs[reg])
9707 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9709 /* If we can, restore the LR into the PC. */
9710 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9712 && current_function_pretend_args_size == 0
9713 && saved_regs_mask & (1 << LR_REGNUM))
9715 saved_regs_mask &= ~ (1 << LR_REGNUM);
9716 saved_regs_mask |= (1 << PC_REGNUM);
9719 /* Load the registers off the stack. If we only have one register
9720 to load use the LDR instruction - it is faster. */
9721 if (saved_regs_mask == (1 << LR_REGNUM))
9723 /* The exception handler ignores the LR, so we do
9724 not really need to load it off the stack. */
9726 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9728 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9730 else if (saved_regs_mask)
9732 if (saved_regs_mask & (1 << SP_REGNUM))
9733 /* Note - write back to the stack register is not enabled
9734 (ie "ldmfd sp!..."). We know that the stack pointer is
9735 in the list of registers and if we add writeback the
9736 instruction becomes UNPREDICTABLE. */
9737 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9739 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9742 if (current_function_pretend_args_size)
9744 /* Unwind the pre-pushed regs. */
9745 operands[0] = operands[1] = stack_pointer_rtx;
9746 operands[2] = GEN_INT (current_function_pretend_args_size);
9747 output_add_immediate (operands);
9751 /* We may have already restored PC directly from the stack. */
9752 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9755 /* Generate the return instruction. */
9756 switch ((int) ARM_FUNC_TYPE (func_type))
9758 case ARM_FT_EXCEPTION_HANDLER:
9759 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9764 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9767 case ARM_FT_EXCEPTION:
9768 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9771 case ARM_FT_INTERWORKED:
9772 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9776 if (arm_arch5 || arm_arch4t)
9777 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9779 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9787 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9788 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9790 arm_stack_offsets *offsets;
9794 /* ??? Probably not safe to set this here, since it assumes that a
9795 function will be emitted as assembly immediately after we generate
9796 RTL for it. This does not happen for inline functions. */
9797 return_used_this_function = 0;
9801 /* We need to take into account any stack-frame rounding. */
9802 offsets = arm_get_frame_offsets ();
9804 if (use_return_insn (FALSE, NULL)
9805 && return_used_this_function
9806 && offsets->saved_regs != offsets->outgoing_args
9807 && !frame_pointer_needed)
9810 /* Reset the ARM-specific per-function variables. */
9811 after_arm_reorg = 0;
9815 /* Generate and emit an insn that we will recognize as a push_multi.
9816 Unfortunately, since this insn does not reflect very well the actual
9817 semantics of the operation, we need to annotate the insn for the benefit
9818 of DWARF2 frame unwind information. */
9820 emit_multi_reg_push (int mask)
9827 int dwarf_par_index;
9830 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9831 if (mask & (1 << i))
9834 if (num_regs == 0 || num_regs > 16)
9837 /* We don't record the PC in the dwarf frame information. */
9838 num_dwarf_regs = num_regs;
9839 if (mask & (1 << PC_REGNUM))
9842 /* For the body of the insn we are going to generate an UNSPEC in
9843 parallel with several USEs. This allows the insn to be recognized
9844 by the push_multi pattern in the arm.md file. The insn looks
9845 something like this:
9848 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9849 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9850 (use (reg:SI 11 fp))
9851 (use (reg:SI 12 ip))
9852 (use (reg:SI 14 lr))
9853 (use (reg:SI 15 pc))
9856 For the frame note however, we try to be more explicit and actually
9857 show each register being stored into the stack frame, plus a (single)
9858 decrement of the stack pointer. We do it this way in order to be
9859 friendly to the stack unwinding code, which only wants to see a single
9860 stack decrement per instruction. The RTL we generate for the note looks
9861 something like this:
9864 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9865 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9866 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9867 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9868 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9871 This sequence is used both by the code to support stack unwinding for
9872 exceptions handlers and the code to generate dwarf2 frame debugging. */
9874 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9875 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9876 dwarf_par_index = 1;
9878 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9880 if (mask & (1 << i))
9882 reg = gen_rtx_REG (SImode, i);
9885 = gen_rtx_SET (VOIDmode,
9886 gen_rtx_MEM (BLKmode,
9887 gen_rtx_PRE_DEC (BLKmode,
9888 stack_pointer_rtx)),
9889 gen_rtx_UNSPEC (BLKmode,
9895 tmp = gen_rtx_SET (VOIDmode,
9896 gen_rtx_MEM (SImode, stack_pointer_rtx),
9898 RTX_FRAME_RELATED_P (tmp) = 1;
9899 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9907 for (j = 1, i++; j < num_regs; i++)
9909 if (mask & (1 << i))
9911 reg = gen_rtx_REG (SImode, i);
9913 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9917 tmp = gen_rtx_SET (VOIDmode,
9918 gen_rtx_MEM (SImode,
9919 plus_constant (stack_pointer_rtx,
9922 RTX_FRAME_RELATED_P (tmp) = 1;
9923 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9930 par = emit_insn (par);
9932 tmp = gen_rtx_SET (SImode,
9934 gen_rtx_PLUS (SImode,
9936 GEN_INT (-4 * num_regs)));
9937 RTX_FRAME_RELATED_P (tmp) = 1;
9938 XVECEXP (dwarf, 0, 0) = tmp;
9940 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9946 emit_sfm (int base_reg, int count)
9953 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9954 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9956 reg = gen_rtx_REG (XFmode, base_reg++);
9959 = gen_rtx_SET (VOIDmode,
9960 gen_rtx_MEM (BLKmode,
9961 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9962 gen_rtx_UNSPEC (BLKmode,
9966 = gen_rtx_SET (VOIDmode,
9967 gen_rtx_MEM (XFmode,
9968 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9970 RTX_FRAME_RELATED_P (tmp) = 1;
9971 XVECEXP (dwarf, 0, count - 1) = tmp;
9973 for (i = 1; i < count; i++)
9975 reg = gen_rtx_REG (XFmode, base_reg++);
9976 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9978 tmp = gen_rtx_SET (VOIDmode,
9979 gen_rtx_MEM (XFmode,
9980 gen_rtx_PRE_DEC (BLKmode,
9981 stack_pointer_rtx)),
9983 RTX_FRAME_RELATED_P (tmp) = 1;
9984 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9987 par = emit_insn (par);
9988 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9994 /* Return true if the current function needs to save/restore LR. */
9997 thumb_force_lr_save (void)
9999 return !cfun->machine->lr_save_eliminated
10000 && (!leaf_function_p ()
10001 || thumb_far_jump_used_p ()
10002 || regs_ever_live [LR_REGNUM]);
10006 /* Compute the distance from register FROM to register TO.
10007 These can be the arg pointer (26), the soft frame pointer (25),
10008 the stack pointer (13) or the hard frame pointer (11).
10009 Typical stack layout looks like this:
10011 old stack pointer -> | |
10014 | | saved arguments for
10015 | | vararg functions
10018 hard FP & arg pointer -> | | \
10026 soft frame pointer -> | | /
10036 current stack pointer -> | | /
10039 For a given function some or all of these stack components
10040 may not be needed, giving rise to the possibility of
10041 eliminating some of the registers.
10043 The values returned by this function must reflect the behavior
10044 of arm_expand_prologue() and arm_compute_save_reg_mask().
10046 The sign of the number returned reflects the direction of stack
10047 growth, so the values are positive for all eliminations except
10048 from the soft frame pointer to the hard frame pointer.
10050 SFP may point just inside the local variables block to ensure correct
10054 /* Calculate stack offsets. These are used to calculate register elimination
10055 offsets and in prologue/epilogue code. */
10057 static arm_stack_offsets *
10058 arm_get_frame_offsets (void)
10060 struct arm_stack_offsets *offsets;
10061 unsigned long func_type;
10064 HOST_WIDE_INT frame_size;
10066 offsets = &cfun->machine->stack_offsets;
10068 /* We need to know if we are a leaf function. Unfortunately, it
10069 is possible to be called after start_sequence has been called,
10070 which causes get_insns to return the insns for the sequence,
10071 not the function, which will cause leaf_function_p to return
10072 the incorrect result.
10074 to know about leaf functions once reload has completed, and the
10075 frame size cannot be changed after that time, so we can safely
10076 use the cached value. */
10078 if (reload_completed)
10081 /* Initially this is the size of the local variables. It will translated
10082 into an offset once we have determined the size of preceding data. */
10083 frame_size = ROUND_UP_WORD (get_frame_size ());
10085 leaf = leaf_function_p ();
10087 /* Space for variadic functions. */
10088 offsets->saved_args = current_function_pretend_args_size;
10090 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10094 unsigned int regno;
10096 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10098 /* We know that SP will be doubleword aligned on entry, and we must
10099 preserve that condition at any subroutine call. We also require the
10100 soft frame pointer to be doubleword aligned. */
10102 if (TARGET_REALLY_IWMMXT)
10104 /* Check for the call-saved iWMMXt registers. */
10105 for (regno = FIRST_IWMMXT_REGNUM;
10106 regno <= LAST_IWMMXT_REGNUM;
10108 if (regs_ever_live [regno] && ! call_used_regs [regno])
10112 func_type = arm_current_func_type ();
10113 if (! IS_VOLATILE (func_type))
10115 /* Space for saved FPA registers. */
10116 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10117 if (regs_ever_live[regno] && ! call_used_regs[regno])
10120 /* Space for saved VFP registers. */
10121 if (TARGET_HARD_FLOAT && TARGET_VFP)
10122 saved += arm_get_vfp_saved_size ();
10125 else /* TARGET_THUMB */
10132 for (reg = 8; reg < 13; reg ++)
10133 if (THUMB_REG_PUSHED_P (reg))
10136 saved += 4 * count_regs;
10138 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10139 if (THUMB_REG_PUSHED_P (reg))
10141 if (count_regs || thumb_force_lr_save ())
10142 saved += 4 * (count_regs + 1);
10143 if (TARGET_BACKTRACE)
10145 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10152 /* Saved registers include the stack frame. */
10153 offsets->saved_regs = offsets->saved_args + saved;
10154 offsets->soft_frame = offsets->saved_regs;
10155 /* A leaf function does not need any stack alignment if it has nothing
10157 if (leaf && frame_size == 0)
10159 offsets->outgoing_args = offsets->soft_frame;
10163 /* Ensure SFP has the correct alignment. */
10164 if (ARM_DOUBLEWORD_ALIGN
10165 && (offsets->soft_frame & 7))
10166 offsets->soft_frame += 4;
10168 offsets->outgoing_args = offsets->soft_frame + frame_size
10169 + current_function_outgoing_args_size;
10171 if (ARM_DOUBLEWORD_ALIGN)
10173 /* Ensure SP remains doubleword aligned. */
10174 if (offsets->outgoing_args & 7)
10175 offsets->outgoing_args += 4;
10176 if (offsets->outgoing_args & 7)
10184 /* Calculate the relative offsets for the different stack pointers. Positive
10185 offsets are in the direction of stack growth. */
10188 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10190 arm_stack_offsets *offsets;
10192 offsets = arm_get_frame_offsets ();
10194 /* OK, now we have enough information to compute the distances.
10195 There must be an entry in these switch tables for each pair
10196 of registers in ELIMINABLE_REGS, even if some of the entries
10197 seem to be redundant or useless. */
10200 case ARG_POINTER_REGNUM:
10203 case THUMB_HARD_FRAME_POINTER_REGNUM:
10206 case FRAME_POINTER_REGNUM:
10207 /* This is the reverse of the soft frame pointer
10208 to hard frame pointer elimination below. */
10209 return offsets->soft_frame - offsets->saved_args;
10211 case ARM_HARD_FRAME_POINTER_REGNUM:
10212 /* If there is no stack frame then the hard
10213 frame pointer and the arg pointer coincide. */
10214 if (offsets->frame == offsets->saved_regs)
10216 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10217 return (frame_pointer_needed
10218 && cfun->static_chain_decl != NULL
10219 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10221 case STACK_POINTER_REGNUM:
10222 /* If nothing has been pushed on the stack at all
10223 then this will return -4. This *is* correct! */
10224 return offsets->outgoing_args - (offsets->saved_args + 4);
10231 case FRAME_POINTER_REGNUM:
10234 case THUMB_HARD_FRAME_POINTER_REGNUM:
10237 case ARM_HARD_FRAME_POINTER_REGNUM:
10238 /* The hard frame pointer points to the top entry in the
10239 stack frame. The soft frame pointer to the bottom entry
10240 in the stack frame. If there is no stack frame at all,
10241 then they are identical. */
10243 return offsets->frame - offsets->soft_frame;
10245 case STACK_POINTER_REGNUM:
10246 return offsets->outgoing_args - offsets->soft_frame;
10254 /* You cannot eliminate from the stack pointer.
10255 In theory you could eliminate from the hard frame
10256 pointer to the stack pointer, but this will never
10257 happen, since if a stack frame is not needed the
10258 hard frame pointer will never be used. */
10264 /* Generate the prologue instructions for entry into an ARM function. */
10266 arm_expand_prologue (void)
10272 unsigned long live_regs_mask;
10273 unsigned long func_type;
10275 int saved_pretend_args = 0;
10276 int saved_regs = 0;
10277 unsigned int args_to_push;
10278 arm_stack_offsets *offsets;
10280 func_type = arm_current_func_type ();
10282 /* Naked functions don't have prologues. */
10283 if (IS_NAKED (func_type))
10286 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10287 args_to_push = current_function_pretend_args_size;
10289 /* Compute which register we will have to save onto the stack. */
10290 live_regs_mask = arm_compute_save_reg_mask ();
10292 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10294 if (frame_pointer_needed)
10296 if (IS_INTERRUPT (func_type))
10298 /* Interrupt functions must not corrupt any registers.
10299 Creating a frame pointer however, corrupts the IP
10300 register, so we must push it first. */
10301 insn = emit_multi_reg_push (1 << IP_REGNUM);
10303 /* Do not set RTX_FRAME_RELATED_P on this insn.
10304 The dwarf stack unwinding code only wants to see one
10305 stack decrement per function, and this is not it. If
10306 this instruction is labeled as being part of the frame
10307 creation sequence then dwarf2out_frame_debug_expr will
10308 abort when it encounters the assignment of IP to FP
10309 later on, since the use of SP here establishes SP as
10310 the CFA register and not IP.
10312 Anyway this instruction is not really part of the stack
10313 frame creation although it is part of the prologue. */
10315 else if (IS_NESTED (func_type))
10317 /* The Static chain register is the same as the IP register
10318 used as a scratch register during stack frame creation.
10319 To get around this need to find somewhere to store IP
10320 whilst the frame is being created. We try the following
10323 1. The last argument register.
10324 2. A slot on the stack above the frame. (This only
10325 works if the function is not a varargs function).
10326 3. Register r3, after pushing the argument registers
10329 Note - we only need to tell the dwarf2 backend about the SP
10330 adjustment in the second variant; the static chain register
10331 doesn't need to be unwound, as it doesn't contain a value
10332 inherited from the caller. */
10334 if (regs_ever_live[3] == 0)
10336 insn = gen_rtx_REG (SImode, 3);
10337 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10338 insn = emit_insn (insn);
10340 else if (args_to_push == 0)
10343 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10344 insn = gen_rtx_MEM (SImode, insn);
10345 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10346 insn = emit_insn (insn);
10350 /* Just tell the dwarf backend that we adjusted SP. */
10351 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10352 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10353 GEN_INT (-fp_offset)));
10354 RTX_FRAME_RELATED_P (insn) = 1;
10355 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10356 dwarf, REG_NOTES (insn));
10360 /* Store the args on the stack. */
10361 if (cfun->machine->uses_anonymous_args)
10362 insn = emit_multi_reg_push
10363 ((0xf0 >> (args_to_push / 4)) & 0xf);
10366 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10367 GEN_INT (- args_to_push)));
10369 RTX_FRAME_RELATED_P (insn) = 1;
10371 saved_pretend_args = 1;
10372 fp_offset = args_to_push;
10375 /* Now reuse r3 to preserve IP. */
10376 insn = gen_rtx_REG (SImode, 3);
10377 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10378 (void) emit_insn (insn);
10384 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10385 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10388 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10390 insn = emit_insn (insn);
10391 RTX_FRAME_RELATED_P (insn) = 1;
10396 /* Push the argument registers, or reserve space for them. */
10397 if (cfun->machine->uses_anonymous_args)
10398 insn = emit_multi_reg_push
10399 ((0xf0 >> (args_to_push / 4)) & 0xf);
10402 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10403 GEN_INT (- args_to_push)));
10404 RTX_FRAME_RELATED_P (insn) = 1;
10407 /* If this is an interrupt service routine, and the link register
10408 is going to be pushed, and we are not creating a stack frame,
10409 (which would involve an extra push of IP and a pop in the epilogue)
10410 subtracting four from LR now will mean that the function return
10411 can be done with a single instruction. */
10412 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10413 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10414 && ! frame_pointer_needed)
10415 emit_insn (gen_rtx_SET (SImode,
10416 gen_rtx_REG (SImode, LR_REGNUM),
10417 gen_rtx_PLUS (SImode,
10418 gen_rtx_REG (SImode, LR_REGNUM),
10421 if (live_regs_mask)
10423 insn = emit_multi_reg_push (live_regs_mask);
10424 saved_regs += bit_count (live_regs_mask) * 4;
10425 RTX_FRAME_RELATED_P (insn) = 1;
10429 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10430 if (regs_ever_live[reg] && ! call_used_regs [reg])
10432 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10433 insn = gen_rtx_MEM (V2SImode, insn);
10434 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10435 gen_rtx_REG (V2SImode, reg)));
10436 RTX_FRAME_RELATED_P (insn) = 1;
10440 if (! IS_VOLATILE (func_type))
10444 /* Save any floating point call-saved registers used by this
10446 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10448 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10449 if (regs_ever_live[reg] && !call_used_regs[reg])
10451 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10452 insn = gen_rtx_MEM (XFmode, insn);
10453 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10454 gen_rtx_REG (XFmode, reg)));
10455 RTX_FRAME_RELATED_P (insn) = 1;
10461 start_reg = LAST_FPA_REGNUM;
10463 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10465 if (regs_ever_live[reg] && !call_used_regs[reg])
10467 if (start_reg - reg == 3)
10469 insn = emit_sfm (reg, 4);
10470 RTX_FRAME_RELATED_P (insn) = 1;
10472 start_reg = reg - 1;
10477 if (start_reg != reg)
10479 insn = emit_sfm (reg + 1, start_reg - reg);
10480 RTX_FRAME_RELATED_P (insn) = 1;
10481 saved_regs += (start_reg - reg) * 12;
10483 start_reg = reg - 1;
10487 if (start_reg != reg)
10489 insn = emit_sfm (reg + 1, start_reg - reg);
10490 saved_regs += (start_reg - reg) * 12;
10491 RTX_FRAME_RELATED_P (insn) = 1;
10494 if (TARGET_HARD_FLOAT && TARGET_VFP)
10496 start_reg = FIRST_VFP_REGNUM;
10498 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10500 if ((!regs_ever_live[reg] || call_used_regs[reg])
10501 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10503 if (start_reg != reg)
10504 saved_regs += vfp_emit_fstmx (start_reg,
10505 (reg - start_reg) / 2);
10506 start_reg = reg + 2;
10509 if (start_reg != reg)
10510 saved_regs += vfp_emit_fstmx (start_reg,
10511 (reg - start_reg) / 2);
10515 if (frame_pointer_needed)
10517 /* Create the new frame pointer. */
10518 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10519 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10520 RTX_FRAME_RELATED_P (insn) = 1;
10522 if (IS_NESTED (func_type))
10524 /* Recover the static chain register. */
10525 if (regs_ever_live [3] == 0
10526 || saved_pretend_args)
10527 insn = gen_rtx_REG (SImode, 3);
10528 else /* if (current_function_pretend_args_size == 0) */
10530 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10532 insn = gen_rtx_MEM (SImode, insn);
10535 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10536 /* Add a USE to stop propagate_one_insn() from barfing. */
10537 emit_insn (gen_prologue_use (ip_rtx));
10541 offsets = arm_get_frame_offsets ();
10542 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10544 /* This add can produce multiple insns for a large constant, so we
10545 need to get tricky. */
10546 rtx last = get_last_insn ();
10548 amount = GEN_INT (offsets->saved_args + saved_regs
10549 - offsets->outgoing_args);
10551 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10555 last = last ? NEXT_INSN (last) : get_insns ();
10556 RTX_FRAME_RELATED_P (last) = 1;
10558 while (last != insn);
10560 /* If the frame pointer is needed, emit a special barrier that
10561 will prevent the scheduler from moving stores to the frame
10562 before the stack adjustment. */
10563 if (frame_pointer_needed)
10564 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10565 hard_frame_pointer_rtx));
10568 /* If we are profiling, make sure no instructions are scheduled before
10569 the call to mcount. Similarly if the user has requested no
10570 scheduling in the prolog. */
10571 if (current_function_profile || TARGET_NO_SCHED_PRO)
10572 emit_insn (gen_blockage ());
10574 /* If the link register is being kept alive, with the return address in it,
10575 then make sure that it does not get reused by the ce2 pass. */
10576 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10578 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10579 cfun->machine->lr_save_eliminated = 1;
10583 /* If CODE is 'd', then the X is a condition operand and the instruction
10584 should only be executed if the condition is true.
10585 if CODE is 'D', then the X is a condition operand and the instruction
10586 should only be executed if the condition is false: however, if the mode
10587 of the comparison is CCFPEmode, then always execute the instruction -- we
10588 do this because in these circumstances !GE does not necessarily imply LT;
10589 in these cases the instruction pattern will take care to make sure that
10590 an instruction containing %d will follow, thereby undoing the effects of
10591 doing this instruction unconditionally.
10592 If CODE is 'N' then X is a floating point operand that must be negated
10594 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10595 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10597 arm_print_operand (FILE *stream, rtx x, int code)
10602 fputs (ASM_COMMENT_START, stream);
10606 fputs (user_label_prefix, stream);
10610 fputs (REGISTER_PREFIX, stream);
10614 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10616 if (TARGET_THUMB || current_insn_predicate != NULL)
10619 fputs (arm_condition_codes[arm_current_cc], stream);
10621 else if (current_insn_predicate)
10623 enum arm_cond_code code;
10628 code = get_arm_condition_code (current_insn_predicate);
10629 fputs (arm_condition_codes[code], stream);
10636 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10637 r = REAL_VALUE_NEGATE (r);
10638 fprintf (stream, "%s", fp_const_from_val (&r));
10643 if (GET_CODE (x) == CONST_INT)
10646 val = ARM_SIGN_EXTEND (~INTVAL (x));
10647 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10651 putc ('~', stream);
10652 output_addr_const (stream, x);
10657 fprintf (stream, "%s", arithmetic_instr (x, 1));
10660 /* Truncate Cirrus shift counts. */
10662 if (GET_CODE (x) == CONST_INT)
10664 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10667 arm_print_operand (stream, x, 0);
10671 fprintf (stream, "%s", arithmetic_instr (x, 0));
10677 const char * shift = shift_op (x, &val);
10681 fprintf (stream, ", %s ", shift_op (x, &val));
10683 arm_print_operand (stream, XEXP (x, 1), 0);
10685 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10690 /* An explanation of the 'Q', 'R' and 'H' register operands:
10692 In a pair of registers containing a DI or DF value the 'Q'
10693 operand returns the register number of the register containing
10694 the least significant part of the value. The 'R' operand returns
10695 the register number of the register containing the most
10696 significant part of the value.
10698 The 'H' operand returns the higher of the two register numbers.
10699 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10700 same as the 'Q' operand, since the most significant part of the
10701 value is held in the lower number register. The reverse is true
10702 on systems where WORDS_BIG_ENDIAN is false.
10704 The purpose of these operands is to distinguish between cases
10705 where the endian-ness of the values is important (for example
10706 when they are added together), and cases where the endian-ness
10707 is irrelevant, but the order of register operations is important.
10708 For example when loading a value from memory into a register
10709 pair, the endian-ness does not matter. Provided that the value
10710 from the lower memory address is put into the lower numbered
10711 register, and the value from the higher address is put into the
10712 higher numbered register, the load will work regardless of whether
10713 the value being loaded is big-wordian or little-wordian. The
10714 order of the two register loads can matter however, if the address
10715 of the memory location is actually held in one of the registers
10716 being overwritten by the load. */
10718 if (REGNO (x) > LAST_ARM_REGNUM)
10720 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10724 if (REGNO (x) > LAST_ARM_REGNUM)
10726 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10730 if (REGNO (x) > LAST_ARM_REGNUM)
10732 asm_fprintf (stream, "%r", REGNO (x) + 1);
10736 asm_fprintf (stream, "%r",
10737 GET_CODE (XEXP (x, 0)) == REG
10738 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10742 asm_fprintf (stream, "{%r-%r}",
10744 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10748 /* CONST_TRUE_RTX means always -- that's the default. */
10749 if (x == const_true_rtx)
10752 fputs (arm_condition_codes[get_arm_condition_code (x)],
10757 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10758 want to do that. */
10759 if (x == const_true_rtx)
10762 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10763 (get_arm_condition_code (x))],
10767 /* Cirrus registers can be accessed in a variety of ways:
10768 single floating point (f)
10769 double floating point (d)
10771 64bit integer (dx). */
10772 case 'W': /* Cirrus register in F mode. */
10773 case 'X': /* Cirrus register in D mode. */
10774 case 'Y': /* Cirrus register in FX mode. */
10775 case 'Z': /* Cirrus register in DX mode. */
10776 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10779 fprintf (stream, "mv%s%s",
10781 : code == 'X' ? "d"
10782 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10786 /* Print cirrus register in the mode specified by the register's mode. */
10789 int mode = GET_MODE (x);
10791 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10794 fprintf (stream, "mv%s%s",
10795 mode == DFmode ? "d"
10796 : mode == SImode ? "fx"
10797 : mode == DImode ? "dx"
10798 : "f", reg_names[REGNO (x)] + 2);
10804 if (GET_CODE (x) != REG
10805 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10806 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10807 /* Bad value for wCG register number. */
10810 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10813 /* Print an iWMMXt control register name. */
10815 if (GET_CODE (x) != CONST_INT
10817 || INTVAL (x) >= 16)
10818 /* Bad value for wC register number. */
10822 static const char * wc_reg_names [16] =
10824 "wCID", "wCon", "wCSSF", "wCASF",
10825 "wC4", "wC5", "wC6", "wC7",
10826 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10827 "wC12", "wC13", "wC14", "wC15"
10830 fprintf (stream, wc_reg_names [INTVAL (x)]);
10834 /* Print a VFP double precision register name. */
10837 int mode = GET_MODE (x);
10840 if (mode != DImode && mode != DFmode)
10843 if (GET_CODE (x) != REG
10844 || !IS_VFP_REGNUM (REGNO (x)))
10847 num = REGNO(x) - FIRST_VFP_REGNUM;
10851 fprintf (stream, "d%d", num >> 1);
10859 if (GET_CODE (x) == REG)
10860 asm_fprintf (stream, "%r", REGNO (x));
10861 else if (GET_CODE (x) == MEM)
10863 output_memory_reference_mode = GET_MODE (x);
10864 output_address (XEXP (x, 0));
10866 else if (GET_CODE (x) == CONST_DOUBLE)
10867 fprintf (stream, "#%s", fp_immediate_constant (x));
10868 else if (GET_CODE (x) == NEG)
10869 abort (); /* This should never happen now. */
10872 fputc ('#', stream);
10873 output_addr_const (stream, x);
10878 #ifndef AOF_ASSEMBLER
10879 /* Target hook for assembling integer objects. The ARM version needs to
10880 handle word-sized values specially. */
10882 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10884 if (size == UNITS_PER_WORD && aligned_p)
10886 fputs ("\t.word\t", asm_out_file);
10887 output_addr_const (asm_out_file, x);
10889 /* Mark symbols as position independent. We only do this in the
10890 .text segment, not in the .data segment. */
10891 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10892 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10894 if (GET_CODE (x) == SYMBOL_REF
10895 && (CONSTANT_POOL_ADDRESS_P (x)
10896 || SYMBOL_REF_LOCAL_P (x)))
10897 fputs ("(GOTOFF)", asm_out_file);
10898 else if (GET_CODE (x) == LABEL_REF)
10899 fputs ("(GOTOFF)", asm_out_file);
10901 fputs ("(GOT)", asm_out_file);
10903 fputc ('\n', asm_out_file);
10907 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10911 if (GET_CODE (x) != CONST_VECTOR)
10914 units = CONST_VECTOR_NUNITS (x);
10916 switch (GET_MODE (x))
10918 case V2SImode: size = 4; break;
10919 case V4HImode: size = 2; break;
10920 case V8QImode: size = 1; break;
10925 for (i = 0; i < units; i++)
10929 elt = CONST_VECTOR_ELT (x, i);
10931 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10937 return default_assemble_integer (x, size, aligned_p);
10941 /* A finite state machine takes care of noticing whether or not instructions
10942 can be conditionally executed, and thus decrease execution time and code
10943 size by deleting branch instructions. The fsm is controlled by
10944 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10946 /* The state of the fsm controlling condition codes are:
10947 0: normal, do nothing special
10948 1: make ASM_OUTPUT_OPCODE not output this instruction
10949 2: make ASM_OUTPUT_OPCODE not output this instruction
10950 3: make instructions conditional
10951 4: make instructions conditional
10953 State transitions (state->state by whom under condition):
10954 0 -> 1 final_prescan_insn if the `target' is a label
10955 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10956 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10957 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10958 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10959 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10960 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10961 (the target insn is arm_target_insn).
10963 If the jump clobbers the conditions then we use states 2 and 4.
10965 A similar thing can be done with conditional return insns.
10967 XXX In case the `target' is an unconditional branch, this conditionalising
10968 of the instructions always reduces code size, but not always execution
10969 time. But then, I want to reduce the code size to somewhere near what
10970 /bin/cc produces. */
10972 /* Returns the index of the ARM condition code string in
10973 `arm_condition_codes'. COMPARISON should be an rtx like
10974 `(eq (...) (...))'. */
10975 static enum arm_cond_code
10976 get_arm_condition_code (rtx comparison)
10978 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10980 enum rtx_code comp_code = GET_CODE (comparison);
10982 if (GET_MODE_CLASS (mode) != MODE_CC)
10983 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10984 XEXP (comparison, 1));
10988 case CC_DNEmode: code = ARM_NE; goto dominance;
10989 case CC_DEQmode: code = ARM_EQ; goto dominance;
10990 case CC_DGEmode: code = ARM_GE; goto dominance;
10991 case CC_DGTmode: code = ARM_GT; goto dominance;
10992 case CC_DLEmode: code = ARM_LE; goto dominance;
10993 case CC_DLTmode: code = ARM_LT; goto dominance;
10994 case CC_DGEUmode: code = ARM_CS; goto dominance;
10995 case CC_DGTUmode: code = ARM_HI; goto dominance;
10996 case CC_DLEUmode: code = ARM_LS; goto dominance;
10997 case CC_DLTUmode: code = ARM_CC;
11000 if (comp_code != EQ && comp_code != NE)
11003 if (comp_code == EQ)
11004 return ARM_INVERSE_CONDITION_CODE (code);
11010 case NE: return ARM_NE;
11011 case EQ: return ARM_EQ;
11012 case GE: return ARM_PL;
11013 case LT: return ARM_MI;
11020 case NE: return ARM_NE;
11021 case EQ: return ARM_EQ;
11028 case NE: return ARM_MI;
11029 case EQ: return ARM_PL;
11035 /* These encodings assume that AC=1 in the FPA system control
11036 byte. This allows us to handle all cases except UNEQ and
11040 case GE: return ARM_GE;
11041 case GT: return ARM_GT;
11042 case LE: return ARM_LS;
11043 case LT: return ARM_MI;
11044 case NE: return ARM_NE;
11045 case EQ: return ARM_EQ;
11046 case ORDERED: return ARM_VC;
11047 case UNORDERED: return ARM_VS;
11048 case UNLT: return ARM_LT;
11049 case UNLE: return ARM_LE;
11050 case UNGT: return ARM_HI;
11051 case UNGE: return ARM_PL;
11052 /* UNEQ and LTGT do not have a representation. */
11053 case UNEQ: /* Fall through. */
11054 case LTGT: /* Fall through. */
11061 case NE: return ARM_NE;
11062 case EQ: return ARM_EQ;
11063 case GE: return ARM_LE;
11064 case GT: return ARM_LT;
11065 case LE: return ARM_GE;
11066 case LT: return ARM_GT;
11067 case GEU: return ARM_LS;
11068 case GTU: return ARM_CC;
11069 case LEU: return ARM_CS;
11070 case LTU: return ARM_HI;
11077 case LTU: return ARM_CS;
11078 case GEU: return ARM_CC;
11085 case NE: return ARM_NE;
11086 case EQ: return ARM_EQ;
11087 case GE: return ARM_GE;
11088 case GT: return ARM_GT;
11089 case LE: return ARM_LE;
11090 case LT: return ARM_LT;
11091 case GEU: return ARM_CS;
11092 case GTU: return ARM_HI;
11093 case LEU: return ARM_LS;
11094 case LTU: return ARM_CC;
11105 arm_final_prescan_insn (rtx insn)
11107 /* BODY will hold the body of INSN. */
11108 rtx body = PATTERN (insn);
11110 /* This will be 1 if trying to repeat the trick, and things need to be
11111 reversed if it appears to fail. */
11114 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11115 taken are clobbered, even if the rtl suggests otherwise. It also
11116 means that we have to grub around within the jump expression to find
11117 out what the conditions are when the jump isn't taken. */
11118 int jump_clobbers = 0;
11120 /* If we start with a return insn, we only succeed if we find another one. */
11121 int seeking_return = 0;
11123 /* START_INSN will hold the insn from where we start looking. This is the
11124 first insn after the following code_label if REVERSE is true. */
11125 rtx start_insn = insn;
11127 /* If in state 4, check if the target branch is reached, in order to
11128 change back to state 0. */
11129 if (arm_ccfsm_state == 4)
11131 if (insn == arm_target_insn)
11133 arm_target_insn = NULL;
11134 arm_ccfsm_state = 0;
11139 /* If in state 3, it is possible to repeat the trick, if this insn is an
11140 unconditional branch to a label, and immediately following this branch
11141 is the previous target label which is only used once, and the label this
11142 branch jumps to is not too far off. */
11143 if (arm_ccfsm_state == 3)
11145 if (simplejump_p (insn))
11147 start_insn = next_nonnote_insn (start_insn);
11148 if (GET_CODE (start_insn) == BARRIER)
11150 /* XXX Isn't this always a barrier? */
11151 start_insn = next_nonnote_insn (start_insn);
11153 if (GET_CODE (start_insn) == CODE_LABEL
11154 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11155 && LABEL_NUSES (start_insn) == 1)
11160 else if (GET_CODE (body) == RETURN)
11162 start_insn = next_nonnote_insn (start_insn);
11163 if (GET_CODE (start_insn) == BARRIER)
11164 start_insn = next_nonnote_insn (start_insn);
11165 if (GET_CODE (start_insn) == CODE_LABEL
11166 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11167 && LABEL_NUSES (start_insn) == 1)
11170 seeking_return = 1;
11179 if (arm_ccfsm_state != 0 && !reverse)
11181 if (GET_CODE (insn) != JUMP_INSN)
11184 /* This jump might be paralleled with a clobber of the condition codes
11185 the jump should always come first */
11186 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11187 body = XVECEXP (body, 0, 0);
11190 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11191 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11194 int fail = FALSE, succeed = FALSE;
11195 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11196 int then_not_else = TRUE;
11197 rtx this_insn = start_insn, label = 0;
11199 /* If the jump cannot be done with one instruction, we cannot
11200 conditionally execute the instruction in the inverse case. */
11201 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11207 /* Register the insn jumped to. */
11210 if (!seeking_return)
11211 label = XEXP (SET_SRC (body), 0);
11213 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11214 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11215 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11217 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11218 then_not_else = FALSE;
11220 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11221 seeking_return = 1;
11222 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11224 seeking_return = 1;
11225 then_not_else = FALSE;
11230 /* See how many insns this branch skips, and what kind of insns. If all
11231 insns are okay, and the label or unconditional branch to the same
11232 label is not too far away, succeed. */
11233 for (insns_skipped = 0;
11234 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11238 this_insn = next_nonnote_insn (this_insn);
11242 switch (GET_CODE (this_insn))
11245 /* Succeed if it is the target label, otherwise fail since
11246 control falls in from somewhere else. */
11247 if (this_insn == label)
11251 arm_ccfsm_state = 2;
11252 this_insn = next_nonnote_insn (this_insn);
11255 arm_ccfsm_state = 1;
11263 /* Succeed if the following insn is the target label.
11265 If return insns are used then the last insn in a function
11266 will be a barrier. */
11267 this_insn = next_nonnote_insn (this_insn);
11268 if (this_insn && this_insn == label)
11272 arm_ccfsm_state = 2;
11273 this_insn = next_nonnote_insn (this_insn);
11276 arm_ccfsm_state = 1;
11284 /* The AAPCS says that conditional calls should not be
11285 used since they make interworking inefficient (the
11286 linker can't transform BL<cond> into BLX). That's
11287 only a problem if the machine has BLX. */
11294 /* Succeed if the following insn is the target label, or
11295 if the following two insns are a barrier and the
11297 this_insn = next_nonnote_insn (this_insn);
11298 if (this_insn && GET_CODE (this_insn) == BARRIER)
11299 this_insn = next_nonnote_insn (this_insn);
11301 if (this_insn && this_insn == label
11302 && insns_skipped < max_insns_skipped)
11306 arm_ccfsm_state = 2;
11307 this_insn = next_nonnote_insn (this_insn);
11310 arm_ccfsm_state = 1;
11318 /* If this is an unconditional branch to the same label, succeed.
11319 If it is to another label, do nothing. If it is conditional,
11321 /* XXX Probably, the tests for SET and the PC are
11324 scanbody = PATTERN (this_insn);
11325 if (GET_CODE (scanbody) == SET
11326 && GET_CODE (SET_DEST (scanbody)) == PC)
11328 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11329 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11331 arm_ccfsm_state = 2;
11334 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11337 /* Fail if a conditional return is undesirable (eg on a
11338 StrongARM), but still allow this if optimizing for size. */
11339 else if (GET_CODE (scanbody) == RETURN
11340 && !use_return_insn (TRUE, NULL)
11343 else if (GET_CODE (scanbody) == RETURN
11346 arm_ccfsm_state = 2;
11349 else if (GET_CODE (scanbody) == PARALLEL)
11351 switch (get_attr_conds (this_insn))
11361 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11366 /* Instructions using or affecting the condition codes make it
11368 scanbody = PATTERN (this_insn);
11369 if (!(GET_CODE (scanbody) == SET
11370 || GET_CODE (scanbody) == PARALLEL)
11371 || get_attr_conds (this_insn) != CONDS_NOCOND)
11374 /* A conditional cirrus instruction must be followed by
11375 a non Cirrus instruction. However, since we
11376 conditionalize instructions in this function and by
11377 the time we get here we can't add instructions
11378 (nops), because shorten_branches() has already been
11379 called, we will disable conditionalizing Cirrus
11380 instructions to be safe. */
11381 if (GET_CODE (scanbody) != USE
11382 && GET_CODE (scanbody) != CLOBBER
11383 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11393 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11394 arm_target_label = CODE_LABEL_NUMBER (label);
11395 else if (seeking_return || arm_ccfsm_state == 2)
11397 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11399 this_insn = next_nonnote_insn (this_insn);
11400 if (this_insn && (GET_CODE (this_insn) == BARRIER
11401 || GET_CODE (this_insn) == CODE_LABEL))
11406 /* Oh, dear! we ran off the end.. give up. */
11407 recog (PATTERN (insn), insn, NULL);
11408 arm_ccfsm_state = 0;
11409 arm_target_insn = NULL;
11412 arm_target_insn = this_insn;
11421 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11423 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11424 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11425 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11426 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11430 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11433 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11437 if (reverse || then_not_else)
11438 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11441 /* Restore recog_data (getting the attributes of other insns can
11442 destroy this array, but final.c assumes that it remains intact
11443 across this call; since the insn has been recognized already we
11444 call recog direct). */
11445 recog (PATTERN (insn), insn, NULL);
11449 /* Returns true if REGNO is a valid register
11450 for holding a quantity of tyoe MODE. */
11452 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11454 if (GET_MODE_CLASS (mode) == MODE_CC)
11455 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11458 /* For the Thumb we only allow values bigger than SImode in
11459 registers 0 - 6, so that there is always a second low
11460 register available to hold the upper part of the value.
11461 We probably we ought to ensure that the register is the
11462 start of an even numbered register pair. */
11463 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11465 if (IS_CIRRUS_REGNUM (regno))
11466 /* We have outlawed SI values in Cirrus registers because they
11467 reside in the lower 32 bits, but SF values reside in the
11468 upper 32 bits. This causes gcc all sorts of grief. We can't
11469 even split the registers into pairs because Cirrus SI values
11470 get sign extended to 64bits-- aldyh. */
11471 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11473 if (IS_VFP_REGNUM (regno))
11475 if (mode == SFmode || mode == SImode)
11478 /* DFmode values are only valid in even register pairs. */
11479 if (mode == DFmode)
11480 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11484 if (IS_IWMMXT_GR_REGNUM (regno))
11485 return mode == SImode;
11487 if (IS_IWMMXT_REGNUM (regno))
11488 return VALID_IWMMXT_REG_MODE (mode);
11490 /* We allow any value to be stored in the general registers.
11491 Restrict doubleword quantities to even register pairs so that we can
11493 if (regno <= LAST_ARM_REGNUM)
11494 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11496 if ( regno == FRAME_POINTER_REGNUM
11497 || regno == ARG_POINTER_REGNUM)
11498 /* We only allow integers in the fake hard registers. */
11499 return GET_MODE_CLASS (mode) == MODE_INT;
11501 /* The only registers left are the FPA registers
11502 which we only allow to hold FP values. */
11503 return GET_MODE_CLASS (mode) == MODE_FLOAT
11504 && regno >= FIRST_FPA_REGNUM
11505 && regno <= LAST_FPA_REGNUM;
11509 arm_regno_class (int regno)
11513 if (regno == STACK_POINTER_REGNUM)
11515 if (regno == CC_REGNUM)
11522 if ( regno <= LAST_ARM_REGNUM
11523 || regno == FRAME_POINTER_REGNUM
11524 || regno == ARG_POINTER_REGNUM)
11525 return GENERAL_REGS;
11527 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11530 if (IS_CIRRUS_REGNUM (regno))
11531 return CIRRUS_REGS;
11533 if (IS_VFP_REGNUM (regno))
11536 if (IS_IWMMXT_REGNUM (regno))
11537 return IWMMXT_REGS;
11539 if (IS_IWMMXT_GR_REGNUM (regno))
11540 return IWMMXT_GR_REGS;
11545 /* Handle a special case when computing the offset
11546 of an argument from the frame pointer. */
11548 arm_debugger_arg_offset (int value, rtx addr)
11552 /* We are only interested if dbxout_parms() failed to compute the offset. */
11556 /* We can only cope with the case where the address is held in a register. */
11557 if (GET_CODE (addr) != REG)
11560 /* If we are using the frame pointer to point at the argument, then
11561 an offset of 0 is correct. */
11562 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11565 /* If we are using the stack pointer to point at the
11566 argument, then an offset of 0 is correct. */
11567 if ((TARGET_THUMB || !frame_pointer_needed)
11568 && REGNO (addr) == SP_REGNUM)
11571 /* Oh dear. The argument is pointed to by a register rather
11572 than being held in a register, or being stored at a known
11573 offset from the frame pointer. Since GDB only understands
11574 those two kinds of argument we must translate the address
11575 held in the register into an offset from the frame pointer.
11576 We do this by searching through the insns for the function
11577 looking to see where this register gets its value. If the
11578 register is initialized from the frame pointer plus an offset
11579 then we are in luck and we can continue, otherwise we give up.
11581 This code is exercised by producing debugging information
11582 for a function with arguments like this:
11584 double func (double a, double b, int c, double d) {return d;}
11586 Without this code the stab for parameter 'd' will be set to
11587 an offset of 0 from the frame pointer, rather than 8. */
11589 /* The if() statement says:
11591 If the insn is a normal instruction
11592 and if the insn is setting the value in a register
11593 and if the register being set is the register holding the address of the argument
11594 and if the address is computing by an addition
11595 that involves adding to a register
11596 which is the frame pointer
11601 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11603 if ( GET_CODE (insn) == INSN
11604 && GET_CODE (PATTERN (insn)) == SET
11605 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11606 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11607 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11608 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11609 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11612 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11621 warning ("unable to compute real location of stacked parameter");
11622 value = 8; /* XXX magic hack */
11628 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11631 if ((MASK) & insn_flags) \
11632 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11636 struct builtin_description
11638 const unsigned int mask;
11639 const enum insn_code icode;
11640 const char * const name;
11641 const enum arm_builtins code;
11642 const enum rtx_code comparison;
11643 const unsigned int flag;
11646 static const struct builtin_description bdesc_2arg[] =
11648 #define IWMMXT_BUILTIN(code, string, builtin) \
11649 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11650 ARM_BUILTIN_##builtin, 0, 0 },
11652 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11653 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11654 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11655 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11656 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11657 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11658 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11659 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11660 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11661 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11662 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11663 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11664 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11665 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11666 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11667 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11668 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11669 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11670 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11671 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11672 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11673 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11674 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11675 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11676 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11677 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11678 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11679 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11680 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11681 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11682 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11683 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11684 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11685 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11686 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11687 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11688 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11689 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11690 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11691 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11692 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11693 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11694 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11695 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11696 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11697 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11698 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11699 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11700 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11701 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11702 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11703 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11704 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11705 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11706 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11707 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11708 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11709 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11711 #define IWMMXT_BUILTIN2(code, builtin) \
11712 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11714 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11715 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11716 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11717 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11718 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11719 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11720 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11721 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11722 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11723 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11724 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11725 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11726 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11727 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11728 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11729 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11730 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11731 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11732 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11733 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11734 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11735 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11736 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11737 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11738 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11739 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11740 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11741 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11742 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11743 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11744 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11745 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11748 static const struct builtin_description bdesc_1arg[] =
11750 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11751 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11752 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11753 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11754 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11755 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11756 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11757 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11758 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11759 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11760 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11761 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11762 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11763 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11764 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11765 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11766 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11767 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11770 /* Set up all the iWMMXt builtins. This is
11771 not called if TARGET_IWMMXT is zero. */
11774 arm_init_iwmmxt_builtins (void)
11776 const struct builtin_description * d;
11778 tree endlink = void_list_node;
11780 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11781 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11782 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11785 = build_function_type (integer_type_node,
11786 tree_cons (NULL_TREE, integer_type_node, endlink));
11787 tree v8qi_ftype_v8qi_v8qi_int
11788 = build_function_type (V8QI_type_node,
11789 tree_cons (NULL_TREE, V8QI_type_node,
11790 tree_cons (NULL_TREE, V8QI_type_node,
11791 tree_cons (NULL_TREE,
11794 tree v4hi_ftype_v4hi_int
11795 = build_function_type (V4HI_type_node,
11796 tree_cons (NULL_TREE, V4HI_type_node,
11797 tree_cons (NULL_TREE, integer_type_node,
11799 tree v2si_ftype_v2si_int
11800 = build_function_type (V2SI_type_node,
11801 tree_cons (NULL_TREE, V2SI_type_node,
11802 tree_cons (NULL_TREE, integer_type_node,
11804 tree v2si_ftype_di_di
11805 = build_function_type (V2SI_type_node,
11806 tree_cons (NULL_TREE, long_long_integer_type_node,
11807 tree_cons (NULL_TREE, long_long_integer_type_node,
11809 tree di_ftype_di_int
11810 = build_function_type (long_long_integer_type_node,
11811 tree_cons (NULL_TREE, long_long_integer_type_node,
11812 tree_cons (NULL_TREE, integer_type_node,
11814 tree di_ftype_di_int_int
11815 = build_function_type (long_long_integer_type_node,
11816 tree_cons (NULL_TREE, long_long_integer_type_node,
11817 tree_cons (NULL_TREE, integer_type_node,
11818 tree_cons (NULL_TREE,
11821 tree int_ftype_v8qi
11822 = build_function_type (integer_type_node,
11823 tree_cons (NULL_TREE, V8QI_type_node,
11825 tree int_ftype_v4hi
11826 = build_function_type (integer_type_node,
11827 tree_cons (NULL_TREE, V4HI_type_node,
11829 tree int_ftype_v2si
11830 = build_function_type (integer_type_node,
11831 tree_cons (NULL_TREE, V2SI_type_node,
11833 tree int_ftype_v8qi_int
11834 = build_function_type (integer_type_node,
11835 tree_cons (NULL_TREE, V8QI_type_node,
11836 tree_cons (NULL_TREE, integer_type_node,
11838 tree int_ftype_v4hi_int
11839 = build_function_type (integer_type_node,
11840 tree_cons (NULL_TREE, V4HI_type_node,
11841 tree_cons (NULL_TREE, integer_type_node,
11843 tree int_ftype_v2si_int
11844 = build_function_type (integer_type_node,
11845 tree_cons (NULL_TREE, V2SI_type_node,
11846 tree_cons (NULL_TREE, integer_type_node,
11848 tree v8qi_ftype_v8qi_int_int
11849 = build_function_type (V8QI_type_node,
11850 tree_cons (NULL_TREE, V8QI_type_node,
11851 tree_cons (NULL_TREE, integer_type_node,
11852 tree_cons (NULL_TREE,
11855 tree v4hi_ftype_v4hi_int_int
11856 = build_function_type (V4HI_type_node,
11857 tree_cons (NULL_TREE, V4HI_type_node,
11858 tree_cons (NULL_TREE, integer_type_node,
11859 tree_cons (NULL_TREE,
11862 tree v2si_ftype_v2si_int_int
11863 = build_function_type (V2SI_type_node,
11864 tree_cons (NULL_TREE, V2SI_type_node,
11865 tree_cons (NULL_TREE, integer_type_node,
11866 tree_cons (NULL_TREE,
11869 /* Miscellaneous. */
11870 tree v8qi_ftype_v4hi_v4hi
11871 = build_function_type (V8QI_type_node,
11872 tree_cons (NULL_TREE, V4HI_type_node,
11873 tree_cons (NULL_TREE, V4HI_type_node,
11875 tree v4hi_ftype_v2si_v2si
11876 = build_function_type (V4HI_type_node,
11877 tree_cons (NULL_TREE, V2SI_type_node,
11878 tree_cons (NULL_TREE, V2SI_type_node,
11880 tree v2si_ftype_v4hi_v4hi
11881 = build_function_type (V2SI_type_node,
11882 tree_cons (NULL_TREE, V4HI_type_node,
11883 tree_cons (NULL_TREE, V4HI_type_node,
11885 tree v2si_ftype_v8qi_v8qi
11886 = build_function_type (V2SI_type_node,
11887 tree_cons (NULL_TREE, V8QI_type_node,
11888 tree_cons (NULL_TREE, V8QI_type_node,
11890 tree v4hi_ftype_v4hi_di
11891 = build_function_type (V4HI_type_node,
11892 tree_cons (NULL_TREE, V4HI_type_node,
11893 tree_cons (NULL_TREE,
11894 long_long_integer_type_node,
11896 tree v2si_ftype_v2si_di
11897 = build_function_type (V2SI_type_node,
11898 tree_cons (NULL_TREE, V2SI_type_node,
11899 tree_cons (NULL_TREE,
11900 long_long_integer_type_node,
11902 tree void_ftype_int_int
11903 = build_function_type (void_type_node,
11904 tree_cons (NULL_TREE, integer_type_node,
11905 tree_cons (NULL_TREE, integer_type_node,
11908 = build_function_type (long_long_unsigned_type_node, endlink);
11910 = build_function_type (long_long_integer_type_node,
11911 tree_cons (NULL_TREE, V8QI_type_node,
11914 = build_function_type (long_long_integer_type_node,
11915 tree_cons (NULL_TREE, V4HI_type_node,
11918 = build_function_type (long_long_integer_type_node,
11919 tree_cons (NULL_TREE, V2SI_type_node,
11921 tree v2si_ftype_v4hi
11922 = build_function_type (V2SI_type_node,
11923 tree_cons (NULL_TREE, V4HI_type_node,
11925 tree v4hi_ftype_v8qi
11926 = build_function_type (V4HI_type_node,
11927 tree_cons (NULL_TREE, V8QI_type_node,
11930 tree di_ftype_di_v4hi_v4hi
11931 = build_function_type (long_long_unsigned_type_node,
11932 tree_cons (NULL_TREE,
11933 long_long_unsigned_type_node,
11934 tree_cons (NULL_TREE, V4HI_type_node,
11935 tree_cons (NULL_TREE,
11939 tree di_ftype_v4hi_v4hi
11940 = build_function_type (long_long_unsigned_type_node,
11941 tree_cons (NULL_TREE, V4HI_type_node,
11942 tree_cons (NULL_TREE, V4HI_type_node,
11945 /* Normal vector binops. */
11946 tree v8qi_ftype_v8qi_v8qi
11947 = build_function_type (V8QI_type_node,
11948 tree_cons (NULL_TREE, V8QI_type_node,
11949 tree_cons (NULL_TREE, V8QI_type_node,
11951 tree v4hi_ftype_v4hi_v4hi
11952 = build_function_type (V4HI_type_node,
11953 tree_cons (NULL_TREE, V4HI_type_node,
11954 tree_cons (NULL_TREE, V4HI_type_node,
11956 tree v2si_ftype_v2si_v2si
11957 = build_function_type (V2SI_type_node,
11958 tree_cons (NULL_TREE, V2SI_type_node,
11959 tree_cons (NULL_TREE, V2SI_type_node,
11961 tree di_ftype_di_di
11962 = build_function_type (long_long_unsigned_type_node,
11963 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11964 tree_cons (NULL_TREE,
11965 long_long_unsigned_type_node,
11968 /* Add all builtins that are more or less simple operations on two
11970 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11972 /* Use one of the operands; the target can have a different mode for
11973 mask-generating compares. */
11974 enum machine_mode mode;
11980 mode = insn_data[d->icode].operand[1].mode;
11985 type = v8qi_ftype_v8qi_v8qi;
11988 type = v4hi_ftype_v4hi_v4hi;
11991 type = v2si_ftype_v2si_v2si;
11994 type = di_ftype_di_di;
12001 def_mbuiltin (d->mask, d->name, type, d->code);
12004 /* Add the remaining MMX insns with somewhat more complicated types. */
12005 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12006 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12012 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12013 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12019 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12020 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12026 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12027 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12040 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12056 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12063 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12064 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12065 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12066 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12067 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12069 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12070 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12071 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12072 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12073 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12074 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12075 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12076 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12077 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12078 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12079 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12080 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12082 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12083 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12084 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12085 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12087 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12088 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12089 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12090 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12091 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12092 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12093 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12097 arm_init_builtins (void)
12099 if (TARGET_REALLY_IWMMXT)
12100 arm_init_iwmmxt_builtins ();
12103 /* Errors in the source file can cause expand_expr to return const0_rtx
12104 where we expect a vector. To avoid crashing, use one of the vector
12105 clear instructions. */
12108 safe_vector_operand (rtx x, enum machine_mode mode)
12110 if (x != const0_rtx)
12112 x = gen_reg_rtx (mode);
12114 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12115 : gen_rtx_SUBREG (DImode, x, 0)));
12119 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12122 arm_expand_binop_builtin (enum insn_code icode,
12123 tree arglist, rtx target)
12126 tree arg0 = TREE_VALUE (arglist);
12127 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12128 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12129 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12130 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12131 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12132 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12134 if (VECTOR_MODE_P (mode0))
12135 op0 = safe_vector_operand (op0, mode0);
12136 if (VECTOR_MODE_P (mode1))
12137 op1 = safe_vector_operand (op1, mode1);
12140 || GET_MODE (target) != tmode
12141 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12142 target = gen_reg_rtx (tmode);
12144 /* In case the insn wants input operands in modes different from
12145 the result, abort. */
12146 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12149 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12150 op0 = copy_to_mode_reg (mode0, op0);
12151 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12152 op1 = copy_to_mode_reg (mode1, op1);
12154 pat = GEN_FCN (icode) (target, op0, op1);
12161 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12164 arm_expand_unop_builtin (enum insn_code icode,
12165 tree arglist, rtx target, int do_load)
12168 tree arg0 = TREE_VALUE (arglist);
12169 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12170 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12171 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12174 || GET_MODE (target) != tmode
12175 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12176 target = gen_reg_rtx (tmode);
12178 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12181 if (VECTOR_MODE_P (mode0))
12182 op0 = safe_vector_operand (op0, mode0);
12184 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12185 op0 = copy_to_mode_reg (mode0, op0);
12188 pat = GEN_FCN (icode) (target, op0);
12195 /* Expand an expression EXP that calls a built-in function,
12196 with result going to TARGET if that's convenient
12197 (and in mode MODE if that's convenient).
12198 SUBTARGET may be used as the target for computing one of EXP's operands.
12199 IGNORE is nonzero if the value is to be ignored. */
12202 arm_expand_builtin (tree exp,
12204 rtx subtarget ATTRIBUTE_UNUSED,
12205 enum machine_mode mode ATTRIBUTE_UNUSED,
12206 int ignore ATTRIBUTE_UNUSED)
12208 const struct builtin_description * d;
12209 enum insn_code icode;
12210 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12211 tree arglist = TREE_OPERAND (exp, 1);
12219 int fcode = DECL_FUNCTION_CODE (fndecl);
12221 enum machine_mode tmode;
12222 enum machine_mode mode0;
12223 enum machine_mode mode1;
12224 enum machine_mode mode2;
12228 case ARM_BUILTIN_TEXTRMSB:
12229 case ARM_BUILTIN_TEXTRMUB:
12230 case ARM_BUILTIN_TEXTRMSH:
12231 case ARM_BUILTIN_TEXTRMUH:
12232 case ARM_BUILTIN_TEXTRMSW:
12233 case ARM_BUILTIN_TEXTRMUW:
12234 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12235 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12236 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12237 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12238 : CODE_FOR_iwmmxt_textrmw);
12240 arg0 = TREE_VALUE (arglist);
12241 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12242 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12243 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12244 tmode = insn_data[icode].operand[0].mode;
12245 mode0 = insn_data[icode].operand[1].mode;
12246 mode1 = insn_data[icode].operand[2].mode;
12248 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12249 op0 = copy_to_mode_reg (mode0, op0);
12250 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12252 /* @@@ better error message */
12253 error ("selector must be an immediate");
12254 return gen_reg_rtx (tmode);
12257 || GET_MODE (target) != tmode
12258 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12259 target = gen_reg_rtx (tmode);
12260 pat = GEN_FCN (icode) (target, op0, op1);
12266 case ARM_BUILTIN_TINSRB:
12267 case ARM_BUILTIN_TINSRH:
12268 case ARM_BUILTIN_TINSRW:
12269 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12270 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12271 : CODE_FOR_iwmmxt_tinsrw);
12272 arg0 = TREE_VALUE (arglist);
12273 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12274 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12275 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12276 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12277 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12278 tmode = insn_data[icode].operand[0].mode;
12279 mode0 = insn_data[icode].operand[1].mode;
12280 mode1 = insn_data[icode].operand[2].mode;
12281 mode2 = insn_data[icode].operand[3].mode;
12283 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12284 op0 = copy_to_mode_reg (mode0, op0);
12285 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12286 op1 = copy_to_mode_reg (mode1, op1);
12287 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12289 /* @@@ better error message */
12290 error ("selector must be an immediate");
12294 || GET_MODE (target) != tmode
12295 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12296 target = gen_reg_rtx (tmode);
12297 pat = GEN_FCN (icode) (target, op0, op1, op2);
12303 case ARM_BUILTIN_SETWCX:
12304 arg0 = TREE_VALUE (arglist);
12305 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12306 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12307 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12308 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12311 case ARM_BUILTIN_GETWCX:
12312 arg0 = TREE_VALUE (arglist);
12313 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12314 target = gen_reg_rtx (SImode);
12315 emit_insn (gen_iwmmxt_tmrc (target, op0));
12318 case ARM_BUILTIN_WSHUFH:
12319 icode = CODE_FOR_iwmmxt_wshufh;
12320 arg0 = TREE_VALUE (arglist);
12321 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12322 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12323 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12324 tmode = insn_data[icode].operand[0].mode;
12325 mode1 = insn_data[icode].operand[1].mode;
12326 mode2 = insn_data[icode].operand[2].mode;
12328 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12329 op0 = copy_to_mode_reg (mode1, op0);
12330 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12332 /* @@@ better error message */
12333 error ("mask must be an immediate");
12337 || GET_MODE (target) != tmode
12338 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12339 target = gen_reg_rtx (tmode);
12340 pat = GEN_FCN (icode) (target, op0, op1);
12346 case ARM_BUILTIN_WSADB:
12347 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12348 case ARM_BUILTIN_WSADH:
12349 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12350 case ARM_BUILTIN_WSADBZ:
12351 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12352 case ARM_BUILTIN_WSADHZ:
12353 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12355 /* Several three-argument builtins. */
12356 case ARM_BUILTIN_WMACS:
12357 case ARM_BUILTIN_WMACU:
12358 case ARM_BUILTIN_WALIGN:
12359 case ARM_BUILTIN_TMIA:
12360 case ARM_BUILTIN_TMIAPH:
12361 case ARM_BUILTIN_TMIATT:
12362 case ARM_BUILTIN_TMIATB:
12363 case ARM_BUILTIN_TMIABT:
12364 case ARM_BUILTIN_TMIABB:
12365 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12366 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12367 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12368 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12369 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12370 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12371 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12372 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12373 : CODE_FOR_iwmmxt_walign);
12374 arg0 = TREE_VALUE (arglist);
12375 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12376 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12377 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12378 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12379 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12380 tmode = insn_data[icode].operand[0].mode;
12381 mode0 = insn_data[icode].operand[1].mode;
12382 mode1 = insn_data[icode].operand[2].mode;
12383 mode2 = insn_data[icode].operand[3].mode;
12385 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12386 op0 = copy_to_mode_reg (mode0, op0);
12387 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12388 op1 = copy_to_mode_reg (mode1, op1);
12389 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12390 op2 = copy_to_mode_reg (mode2, op2);
12392 || GET_MODE (target) != tmode
12393 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12394 target = gen_reg_rtx (tmode);
12395 pat = GEN_FCN (icode) (target, op0, op1, op2);
12401 case ARM_BUILTIN_WZERO:
12402 target = gen_reg_rtx (DImode);
12403 emit_insn (gen_iwmmxt_clrdi (target));
12410 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12411 if (d->code == (const enum arm_builtins) fcode)
12412 return arm_expand_binop_builtin (d->icode, arglist, target);
12414 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12415 if (d->code == (const enum arm_builtins) fcode)
12416 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12418 /* @@@ Should really do something sensible here. */
12422 /* Recursively search through all of the blocks in a function
12423 checking to see if any of the variables created in that
12424 function match the RTX called 'orig'. If they do then
12425 replace them with the RTX called 'new'. */
12427 replace_symbols_in_block (tree block, rtx orig, rtx new)
12429 for (; block; block = BLOCK_CHAIN (block))
12433 if (!TREE_USED (block))
12436 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12438 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12439 || DECL_IGNORED_P (sym)
12440 || TREE_CODE (sym) != VAR_DECL
12441 || DECL_EXTERNAL (sym)
12442 || !rtx_equal_p (DECL_RTL (sym), orig)
12446 SET_DECL_RTL (sym, new);
12449 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12453 /* Return the number (counting from 0) of
12454 the least significant set bit in MASK. */
12457 number_of_first_bit_set (int mask)
12462 (mask & (1 << bit)) == 0;
12469 /* Generate code to return from a thumb function.
12470 If 'reg_containing_return_addr' is -1, then the return address is
12471 actually on the stack, at the stack pointer. */
12473 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12475 unsigned regs_available_for_popping;
12476 unsigned regs_to_pop;
12478 unsigned available;
12482 int restore_a4 = FALSE;
12484 /* Compute the registers we need to pop. */
12488 /* There is an assumption here, that if eh_ofs is not NULL, the
12489 normal return address will have been pushed. */
12490 if (reg_containing_return_addr == -1 || eh_ofs)
12492 /* When we are generating a return for __builtin_eh_return,
12493 reg_containing_return_addr must specify the return regno. */
12494 if (eh_ofs && reg_containing_return_addr == -1)
12497 regs_to_pop |= 1 << LR_REGNUM;
12501 if (TARGET_BACKTRACE)
12503 /* Restore the (ARM) frame pointer and stack pointer. */
12504 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12508 /* If there is nothing to pop then just emit the BX instruction and
12510 if (pops_needed == 0)
12513 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12515 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12518 /* Otherwise if we are not supporting interworking and we have not created
12519 a backtrace structure and the function was not entered in ARM mode then
12520 just pop the return address straight into the PC. */
12521 else if (!TARGET_INTERWORK
12522 && !TARGET_BACKTRACE
12523 && !is_called_in_ARM_mode (current_function_decl))
12527 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12528 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12529 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12532 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12537 /* Find out how many of the (return) argument registers we can corrupt. */
12538 regs_available_for_popping = 0;
12540 /* If returning via __builtin_eh_return, the bottom three registers
12541 all contain information needed for the return. */
12546 /* If we can deduce the registers used from the function's
12547 return value. This is more reliable that examining
12548 regs_ever_live[] because that will be set if the register is
12549 ever used in the function, not just if the register is used
12550 to hold a return value. */
12552 if (current_function_return_rtx != 0)
12553 mode = GET_MODE (current_function_return_rtx);
12555 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12557 size = GET_MODE_SIZE (mode);
12561 /* In a void function we can use any argument register.
12562 In a function that returns a structure on the stack
12563 we can use the second and third argument registers. */
12564 if (mode == VOIDmode)
12565 regs_available_for_popping =
12566 (1 << ARG_REGISTER (1))
12567 | (1 << ARG_REGISTER (2))
12568 | (1 << ARG_REGISTER (3));
12570 regs_available_for_popping =
12571 (1 << ARG_REGISTER (2))
12572 | (1 << ARG_REGISTER (3));
12574 else if (size <= 4)
12575 regs_available_for_popping =
12576 (1 << ARG_REGISTER (2))
12577 | (1 << ARG_REGISTER (3));
12578 else if (size <= 8)
12579 regs_available_for_popping =
12580 (1 << ARG_REGISTER (3));
12583 /* Match registers to be popped with registers into which we pop them. */
12584 for (available = regs_available_for_popping,
12585 required = regs_to_pop;
12586 required != 0 && available != 0;
12587 available &= ~(available & - available),
12588 required &= ~(required & - required))
12591 /* If we have any popping registers left over, remove them. */
12593 regs_available_for_popping &= ~available;
12595 /* Otherwise if we need another popping register we can use
12596 the fourth argument register. */
12597 else if (pops_needed)
12599 /* If we have not found any free argument registers and
12600 reg a4 contains the return address, we must move it. */
12601 if (regs_available_for_popping == 0
12602 && reg_containing_return_addr == LAST_ARG_REGNUM)
12604 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12605 reg_containing_return_addr = LR_REGNUM;
12607 else if (size > 12)
12609 /* Register a4 is being used to hold part of the return value,
12610 but we have dire need of a free, low register. */
12613 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12616 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12618 /* The fourth argument register is available. */
12619 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12625 /* Pop as many registers as we can. */
12626 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12627 regs_available_for_popping);
12629 /* Process the registers we popped. */
12630 if (reg_containing_return_addr == -1)
12632 /* The return address was popped into the lowest numbered register. */
12633 regs_to_pop &= ~(1 << LR_REGNUM);
12635 reg_containing_return_addr =
12636 number_of_first_bit_set (regs_available_for_popping);
12638 /* Remove this register for the mask of available registers, so that
12639 the return address will not be corrupted by further pops. */
12640 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12643 /* If we popped other registers then handle them here. */
12644 if (regs_available_for_popping)
12648 /* Work out which register currently contains the frame pointer. */
12649 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12651 /* Move it into the correct place. */
12652 asm_fprintf (f, "\tmov\t%r, %r\n",
12653 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12655 /* (Temporarily) remove it from the mask of popped registers. */
12656 regs_available_for_popping &= ~(1 << frame_pointer);
12657 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12659 if (regs_available_for_popping)
12663 /* We popped the stack pointer as well,
12664 find the register that contains it. */
12665 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12667 /* Move it into the stack register. */
12668 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12670 /* At this point we have popped all necessary registers, so
12671 do not worry about restoring regs_available_for_popping
12672 to its correct value:
12674 assert (pops_needed == 0)
12675 assert (regs_available_for_popping == (1 << frame_pointer))
12676 assert (regs_to_pop == (1 << STACK_POINTER)) */
12680 /* Since we have just move the popped value into the frame
12681 pointer, the popping register is available for reuse, and
12682 we know that we still have the stack pointer left to pop. */
12683 regs_available_for_popping |= (1 << frame_pointer);
12687 /* If we still have registers left on the stack, but we no longer have
12688 any registers into which we can pop them, then we must move the return
12689 address into the link register and make available the register that
12691 if (regs_available_for_popping == 0 && pops_needed > 0)
12693 regs_available_for_popping |= 1 << reg_containing_return_addr;
12695 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12696 reg_containing_return_addr);
12698 reg_containing_return_addr = LR_REGNUM;
12701 /* If we have registers left on the stack then pop some more.
12702 We know that at most we will want to pop FP and SP. */
12703 if (pops_needed > 0)
12708 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12709 regs_available_for_popping);
12711 /* We have popped either FP or SP.
12712 Move whichever one it is into the correct register. */
12713 popped_into = number_of_first_bit_set (regs_available_for_popping);
12714 move_to = number_of_first_bit_set (regs_to_pop);
12716 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12718 regs_to_pop &= ~(1 << move_to);
12723 /* If we still have not popped everything then we must have only
12724 had one register available to us and we are now popping the SP. */
12725 if (pops_needed > 0)
12729 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12730 regs_available_for_popping);
12732 popped_into = number_of_first_bit_set (regs_available_for_popping);
12734 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12736 assert (regs_to_pop == (1 << STACK_POINTER))
12737 assert (pops_needed == 1)
12741 /* If necessary restore the a4 register. */
12744 if (reg_containing_return_addr != LR_REGNUM)
12746 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12747 reg_containing_return_addr = LR_REGNUM;
12750 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12754 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12756 /* Return to caller. */
12757 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12760 /* Emit code to push or pop registers to or from the stack. F is the
12761 assembly file. MASK is the registers to push or pop. PUSH is
12762 nonzero if we should push, and zero if we should pop. For debugging
12763 output, if pushing, adjust CFA_OFFSET by the amount of space added
12764 to the stack. REAL_REGS should have the same number of bits set as
12765 MASK, and will be used instead (in the same order) to describe which
12766 registers were saved - this is used to mark the save slots when we
12767 push high registers after moving them to low registers. */
12769 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12772 int lo_mask = mask & 0xFF;
12773 int pushed_words = 0;
12775 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12777 /* Special case. Do not generate a POP PC statement here, do it in
12779 thumb_exit (f, -1, NULL_RTX);
12783 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12785 /* Look at the low registers first. */
12786 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12790 asm_fprintf (f, "%r", regno);
12792 if ((lo_mask & ~1) != 0)
12799 if (push && (mask & (1 << LR_REGNUM)))
12801 /* Catch pushing the LR. */
12805 asm_fprintf (f, "%r", LR_REGNUM);
12809 else if (!push && (mask & (1 << PC_REGNUM)))
12811 /* Catch popping the PC. */
12812 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12814 /* The PC is never poped directly, instead
12815 it is popped into r3 and then BX is used. */
12816 fprintf (f, "}\n");
12818 thumb_exit (f, -1, NULL_RTX);
12827 asm_fprintf (f, "%r", PC_REGNUM);
12831 fprintf (f, "}\n");
12833 if (push && pushed_words && dwarf2out_do_frame ())
12835 char *l = dwarf2out_cfi_label ();
12836 int pushed_mask = real_regs;
12838 *cfa_offset += pushed_words * 4;
12839 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12842 pushed_mask = real_regs;
12843 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12845 if (pushed_mask & 1)
12846 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12852 thumb_final_prescan_insn (rtx insn)
12854 if (flag_print_asm_name)
12855 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12856 INSN_ADDRESSES (INSN_UID (insn)));
12860 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12862 unsigned HOST_WIDE_INT mask = 0xff;
12865 if (val == 0) /* XXX */
12868 for (i = 0; i < 25; i++)
12869 if ((val & (mask << i)) == val)
12875 /* Returns nonzero if the current function contains,
12876 or might contain a far jump. */
12878 thumb_far_jump_used_p (void)
12882 /* This test is only important for leaf functions. */
12883 /* assert (!leaf_function_p ()); */
12885 /* If we have already decided that far jumps may be used,
12886 do not bother checking again, and always return true even if
12887 it turns out that they are not being used. Once we have made
12888 the decision that far jumps are present (and that hence the link
12889 register will be pushed onto the stack) we cannot go back on it. */
12890 if (cfun->machine->far_jump_used)
12893 /* If this function is not being called from the prologue/epilogue
12894 generation code then it must be being called from the
12895 INITIAL_ELIMINATION_OFFSET macro. */
12896 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12898 /* In this case we know that we are being asked about the elimination
12899 of the arg pointer register. If that register is not being used,
12900 then there are no arguments on the stack, and we do not have to
12901 worry that a far jump might force the prologue to push the link
12902 register, changing the stack offsets. In this case we can just
12903 return false, since the presence of far jumps in the function will
12904 not affect stack offsets.
12906 If the arg pointer is live (or if it was live, but has now been
12907 eliminated and so set to dead) then we do have to test to see if
12908 the function might contain a far jump. This test can lead to some
12909 false negatives, since before reload is completed, then length of
12910 branch instructions is not known, so gcc defaults to returning their
12911 longest length, which in turn sets the far jump attribute to true.
12913 A false negative will not result in bad code being generated, but it
12914 will result in a needless push and pop of the link register. We
12915 hope that this does not occur too often.
12917 If we need doubleword stack alignment this could affect the other
12918 elimination offsets so we can't risk getting it wrong. */
12919 if (regs_ever_live [ARG_POINTER_REGNUM])
12920 cfun->machine->arg_pointer_live = 1;
12921 else if (!cfun->machine->arg_pointer_live)
12925 /* Check to see if the function contains a branch
12926 insn with the far jump attribute set. */
12927 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12929 if (GET_CODE (insn) == JUMP_INSN
12930 /* Ignore tablejump patterns. */
12931 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12932 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12933 && get_attr_far_jump (insn) == FAR_JUMP_YES
12936 /* Record the fact that we have decided that
12937 the function does use far jumps. */
12938 cfun->machine->far_jump_used = 1;
12946 /* Return nonzero if FUNC must be entered in ARM mode. */
12948 is_called_in_ARM_mode (tree func)
12950 if (TREE_CODE (func) != FUNCTION_DECL)
12953 /* Ignore the problem about functions whoes address is taken. */
12954 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12958 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12964 /* The bits which aren't usefully expanded as rtl. */
12966 thumb_unexpanded_epilogue (void)
12969 int live_regs_mask = 0;
12970 int high_regs_pushed = 0;
12971 int had_to_push_lr;
12972 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12974 if (return_used_this_function)
12977 if (IS_NAKED (arm_current_func_type ()))
12980 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12981 if (THUMB_REG_PUSHED_P (regno))
12982 live_regs_mask |= 1 << regno;
12984 for (regno = 8; regno < 13; regno++)
12985 if (THUMB_REG_PUSHED_P (regno))
12986 high_regs_pushed++;
12988 /* The prolog may have pushed some high registers to use as
12989 work registers. eg the testsuite file:
12990 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12991 compiles to produce:
12992 push {r4, r5, r6, r7, lr}
12996 as part of the prolog. We have to undo that pushing here. */
12998 if (high_regs_pushed)
13000 int mask = live_regs_mask;
13005 /* If we can deduce the registers used from the function's return value.
13006 This is more reliable that examining regs_ever_live[] because that
13007 will be set if the register is ever used in the function, not just if
13008 the register is used to hold a return value. */
13010 if (current_function_return_rtx != 0)
13011 mode = GET_MODE (current_function_return_rtx);
13013 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13015 size = GET_MODE_SIZE (mode);
13017 /* Unless we are returning a type of size > 12 register r3 is
13023 /* Oh dear! We have no low registers into which we can pop
13026 ("no low registers available for popping high registers");
13028 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13029 if (THUMB_REG_PUSHED_P (next_hi_reg))
13032 while (high_regs_pushed)
13034 /* Find lo register(s) into which the high register(s) can
13036 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13038 if (mask & (1 << regno))
13039 high_regs_pushed--;
13040 if (high_regs_pushed == 0)
13044 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13046 /* Pop the values into the low register(s). */
13047 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13049 /* Move the value(s) into the high registers. */
13050 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13052 if (mask & (1 << regno))
13054 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13057 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13058 if (THUMB_REG_PUSHED_P (next_hi_reg))
13065 had_to_push_lr = (live_regs_mask || thumb_force_lr_save ());
13067 if (TARGET_BACKTRACE
13068 && ((live_regs_mask & 0xFF) == 0)
13069 && regs_ever_live [LAST_ARG_REGNUM] != 0)
13071 /* The stack backtrace structure creation code had to
13072 push R7 in order to get a work register, so we pop
13074 live_regs_mask |= (1 << LAST_LO_REGNUM);
13077 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13080 && !is_called_in_ARM_mode (current_function_decl)
13082 live_regs_mask |= 1 << PC_REGNUM;
13084 /* Either no argument registers were pushed or a backtrace
13085 structure was created which includes an adjusted stack
13086 pointer, so just pop everything. */
13087 if (live_regs_mask)
13088 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13092 thumb_exit (asm_out_file, 2, eh_ofs);
13093 /* We have either just popped the return address into the
13094 PC or it is was kept in LR for the entire function or
13095 it is still on the stack because we do not want to
13096 return by doing a pop {pc}. */
13097 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13098 thumb_exit (asm_out_file,
13100 && is_called_in_ARM_mode (current_function_decl)) ?
13101 -1 : LR_REGNUM, NULL_RTX);
13105 /* Pop everything but the return address. */
13106 live_regs_mask &= ~(1 << PC_REGNUM);
13108 if (live_regs_mask)
13109 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13112 if (had_to_push_lr)
13113 /* Get the return address into a temporary register. */
13114 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13115 1 << LAST_ARG_REGNUM);
13117 /* Remove the argument registers that were pushed onto the stack. */
13118 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13119 SP_REGNUM, SP_REGNUM,
13120 current_function_pretend_args_size);
13123 thumb_exit (asm_out_file, 2, eh_ofs);
13125 thumb_exit (asm_out_file,
13126 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13132 /* Functions to save and restore machine-specific function data. */
13133 static struct machine_function *
13134 arm_init_machine_status (void)
13136 struct machine_function *machine;
13137 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13139 #if ARM_FT_UNKNOWN != 0
13140 machine->func_type = ARM_FT_UNKNOWN;
13145 /* Return an RTX indicating where the return address to the
13146 calling function can be found. */
13148 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13153 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13156 /* Do anything needed before RTL is emitted for each function. */
13158 arm_init_expanders (void)
13160 /* Arrange to initialize and mark the machine per-function status. */
13161 init_machine_status = arm_init_machine_status;
13165 /* Like arm_compute_initial_elimination offset. Simpler because
13166 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13169 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13171 arm_stack_offsets *offsets;
13173 offsets = arm_get_frame_offsets ();
13177 case ARG_POINTER_REGNUM:
13180 case STACK_POINTER_REGNUM:
13181 return offsets->outgoing_args - offsets->saved_args;
13183 case FRAME_POINTER_REGNUM:
13184 return offsets->soft_frame - offsets->saved_args;
13186 case THUMB_HARD_FRAME_POINTER_REGNUM:
13187 case ARM_HARD_FRAME_POINTER_REGNUM:
13188 return offsets->saved_regs - offsets->saved_args;
13195 case FRAME_POINTER_REGNUM:
13198 case STACK_POINTER_REGNUM:
13199 return offsets->outgoing_args - offsets->soft_frame;
13201 case THUMB_HARD_FRAME_POINTER_REGNUM:
13202 case ARM_HARD_FRAME_POINTER_REGNUM:
13203 return offsets->saved_regs - offsets->soft_frame;
13216 /* Generate the rest of a function's prologue. */
13218 thumb_expand_prologue (void)
13222 HOST_WIDE_INT amount;
13223 arm_stack_offsets *offsets;
13224 unsigned long func_type;
13227 func_type = arm_current_func_type ();
13229 /* Naked functions don't have prologues. */
13230 if (IS_NAKED (func_type))
13233 if (IS_INTERRUPT (func_type))
13235 error ("interrupt Service Routines cannot be coded in Thumb mode");
13239 offsets = arm_get_frame_offsets ();
13241 if (frame_pointer_needed)
13243 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13244 stack_pointer_rtx));
13245 RTX_FRAME_RELATED_P (insn) = 1;
13248 amount = offsets->outgoing_args - offsets->saved_regs;
13253 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13254 GEN_INT (- amount)));
13255 RTX_FRAME_RELATED_P (insn) = 1;
13261 /* The stack decrement is too big for an immediate value in a single
13262 insn. In theory we could issue multiple subtracts, but after
13263 three of them it becomes more space efficient to place the full
13264 value in the constant pool and load into a register. (Also the
13265 ARM debugger really likes to see only one stack decrement per
13266 function). So instead we look for a scratch register into which
13267 we can load the decrement, and then we subtract this from the
13268 stack pointer. Unfortunately on the thumb the only available
13269 scratch registers are the argument registers, and we cannot use
13270 these as they may hold arguments to the function. Instead we
13271 attempt to locate a call preserved register which is used by this
13272 function. If we can find one, then we know that it will have
13273 been pushed at the start of the prologue and so we can corrupt
13275 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13276 if (THUMB_REG_PUSHED_P (regno)
13277 && !(frame_pointer_needed
13278 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13281 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13283 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13285 /* Choose an arbitrary, non-argument low register. */
13286 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13288 /* Save it by copying it into a high, scratch register. */
13289 emit_insn (gen_movsi (spare, reg));
13290 /* Add a USE to stop propagate_one_insn() from barfing. */
13291 emit_insn (gen_prologue_use (spare));
13293 /* Decrement the stack. */
13294 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13295 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13296 stack_pointer_rtx, reg));
13297 RTX_FRAME_RELATED_P (insn) = 1;
13298 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13299 plus_constant (stack_pointer_rtx,
13300 GEN_INT (- amount)));
13301 RTX_FRAME_RELATED_P (dwarf) = 1;
13303 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13306 /* Restore the low register's original value. */
13307 emit_insn (gen_movsi (reg, spare));
13309 /* Emit a USE of the restored scratch register, so that flow
13310 analysis will not consider the restore redundant. The
13311 register won't be used again in this function and isn't
13312 restored by the epilogue. */
13313 emit_insn (gen_prologue_use (reg));
13317 reg = gen_rtx_REG (SImode, regno);
13319 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13321 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13322 stack_pointer_rtx, reg));
13323 RTX_FRAME_RELATED_P (insn) = 1;
13324 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13325 plus_constant (stack_pointer_rtx,
13326 GEN_INT (- amount)));
13327 RTX_FRAME_RELATED_P (dwarf) = 1;
13329 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13333 /* If the frame pointer is needed, emit a special barrier that
13334 will prevent the scheduler from moving stores to the frame
13335 before the stack adjustment. */
13336 if (frame_pointer_needed)
13337 emit_insn (gen_stack_tie (stack_pointer_rtx,
13338 hard_frame_pointer_rtx));
13341 if (current_function_profile || TARGET_NO_SCHED_PRO)
13342 emit_insn (gen_blockage ());
13344 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13345 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13347 if (THUMB_REG_PUSHED_P (regno))
13349 cfun->machine->lr_save_eliminated = 0;
13354 /* If the link register is being kept alive, with the return address in it,
13355 then make sure that it does not get reused by the ce2 pass. */
13356 if (cfun->machine->lr_save_eliminated)
13357 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13361 thumb_expand_epilogue (void)
13363 HOST_WIDE_INT amount;
13364 arm_stack_offsets *offsets;
13367 /* Naked functions don't have prologues. */
13368 if (IS_NAKED (arm_current_func_type ()))
13371 offsets = arm_get_frame_offsets ();
13372 amount = offsets->outgoing_args - offsets->saved_regs;
13374 if (frame_pointer_needed)
13375 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13379 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13380 GEN_INT (amount)));
13383 /* r3 is always free in the epilogue. */
13384 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13386 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13387 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13391 /* Emit a USE (stack_pointer_rtx), so that
13392 the stack adjustment will not be deleted. */
13393 emit_insn (gen_prologue_use (stack_pointer_rtx));
13395 if (current_function_profile || TARGET_NO_SCHED_PRO)
13396 emit_insn (gen_blockage ());
13398 /* Emit a clobber for each insn that will be restored in the epilogue,
13399 so that flow2 will get register lifetimes correct. */
13400 for (regno = 0; regno < 13; regno++)
13401 if (regs_ever_live[regno] && !call_used_regs[regno])
13402 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13404 if (! regs_ever_live[LR_REGNUM])
13405 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13409 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13411 int live_regs_mask = 0;
13412 int high_regs_pushed = 0;
13413 int cfa_offset = 0;
13416 if (IS_NAKED (arm_current_func_type ()))
13419 if (is_called_in_ARM_mode (current_function_decl))
13423 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13425 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13427 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13429 /* Generate code sequence to switch us into Thumb mode. */
13430 /* The .code 32 directive has already been emitted by
13431 ASM_DECLARE_FUNCTION_NAME. */
13432 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13433 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13435 /* Generate a label, so that the debugger will notice the
13436 change in instruction sets. This label is also used by
13437 the assembler to bypass the ARM code when this function
13438 is called from a Thumb encoded function elsewhere in the
13439 same file. Hence the definition of STUB_NAME here must
13440 agree with the definition in gas/config/tc-arm.c. */
13442 #define STUB_NAME ".real_start_of"
13444 fprintf (f, "\t.code\t16\n");
13446 if (arm_dllexport_name_p (name))
13447 name = arm_strip_name_encoding (name);
13449 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13450 fprintf (f, "\t.thumb_func\n");
13451 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13454 if (current_function_pretend_args_size)
13456 if (cfun->machine->uses_anonymous_args)
13460 fprintf (f, "\tpush\t{");
13462 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13464 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13465 regno <= LAST_ARG_REGNUM;
13467 asm_fprintf (f, "%r%s", regno,
13468 regno == LAST_ARG_REGNUM ? "" : ", ");
13470 fprintf (f, "}\n");
13473 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13474 SP_REGNUM, SP_REGNUM,
13475 current_function_pretend_args_size);
13477 /* We don't need to record the stores for unwinding (would it
13478 help the debugger any if we did?), but record the change in
13479 the stack pointer. */
13480 if (dwarf2out_do_frame ())
13482 char *l = dwarf2out_cfi_label ();
13483 cfa_offset = cfa_offset + current_function_pretend_args_size;
13484 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13488 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13489 if (THUMB_REG_PUSHED_P (regno))
13490 live_regs_mask |= 1 << regno;
13492 if (live_regs_mask || thumb_force_lr_save ())
13493 live_regs_mask |= 1 << LR_REGNUM;
13495 if (TARGET_BACKTRACE)
13498 int work_register = 0;
13501 /* We have been asked to create a stack backtrace structure.
13502 The code looks like this:
13506 0 sub SP, #16 Reserve space for 4 registers.
13507 2 push {R7} Get a work register.
13508 4 add R7, SP, #20 Get the stack pointer before the push.
13509 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13510 8 mov R7, PC Get hold of the start of this code plus 12.
13511 10 str R7, [SP, #16] Store it.
13512 12 mov R7, FP Get hold of the current frame pointer.
13513 14 str R7, [SP, #4] Store it.
13514 16 mov R7, LR Get hold of the current return address.
13515 18 str R7, [SP, #12] Store it.
13516 20 add R7, SP, #16 Point at the start of the backtrace structure.
13517 22 mov FP, R7 Put this value into the frame pointer. */
13519 if ((live_regs_mask & 0xFF) == 0)
13521 /* See if the a4 register is free. */
13523 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13524 work_register = LAST_ARG_REGNUM;
13525 else /* We must push a register of our own. */
13526 live_regs_mask |= (1 << LAST_LO_REGNUM);
13529 if (work_register == 0)
13531 /* Select a register from the list that will be pushed to
13532 use as our work register. */
13533 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13534 if ((1 << work_register) & live_regs_mask)
13539 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13540 SP_REGNUM, SP_REGNUM);
13542 if (dwarf2out_do_frame ())
13544 char *l = dwarf2out_cfi_label ();
13545 cfa_offset = cfa_offset + 16;
13546 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13549 if (live_regs_mask)
13550 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13552 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13553 if (wr & live_regs_mask)
13556 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13557 offset + 16 + current_function_pretend_args_size);
13559 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13562 /* Make sure that the instruction fetching the PC is in the right place
13563 to calculate "start of backtrace creation code + 12". */
13564 if (live_regs_mask)
13566 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13567 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13569 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13570 ARM_HARD_FRAME_POINTER_REGNUM);
13571 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13576 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13577 ARM_HARD_FRAME_POINTER_REGNUM);
13578 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13580 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13581 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13585 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13586 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13588 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13590 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13591 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13593 else if (live_regs_mask)
13594 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13596 for (regno = 8; regno < 13; regno++)
13597 if (THUMB_REG_PUSHED_P (regno))
13598 high_regs_pushed++;
13600 if (high_regs_pushed)
13602 int pushable_regs = 0;
13603 int mask = live_regs_mask & 0xff;
13606 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13607 if (THUMB_REG_PUSHED_P (next_hi_reg))
13610 pushable_regs = mask;
13612 if (pushable_regs == 0)
13614 /* Desperation time -- this probably will never happen. */
13615 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13616 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13617 mask = 1 << LAST_ARG_REGNUM;
13620 while (high_regs_pushed > 0)
13622 int real_regs_mask = 0;
13624 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13626 if (mask & (1 << regno))
13628 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13630 high_regs_pushed--;
13631 real_regs_mask |= (1 << next_hi_reg);
13633 if (high_regs_pushed)
13635 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13637 if (THUMB_REG_PUSHED_P (next_hi_reg))
13642 mask &= ~((1 << regno) - 1);
13648 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13651 if (pushable_regs == 0
13652 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13653 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13657 /* Handle the case of a double word load into a low register from
13658 a computed memory address. The computed address may involve a
13659 register which is overwritten by the load. */
13661 thumb_load_double_from_address (rtx *operands)
13669 if (GET_CODE (operands[0]) != REG)
13672 if (GET_CODE (operands[1]) != MEM)
13675 /* Get the memory address. */
13676 addr = XEXP (operands[1], 0);
13678 /* Work out how the memory address is computed. */
13679 switch (GET_CODE (addr))
13682 operands[2] = gen_rtx_MEM (SImode,
13683 plus_constant (XEXP (operands[1], 0), 4));
13685 if (REGNO (operands[0]) == REGNO (addr))
13687 output_asm_insn ("ldr\t%H0, %2", operands);
13688 output_asm_insn ("ldr\t%0, %1", operands);
13692 output_asm_insn ("ldr\t%0, %1", operands);
13693 output_asm_insn ("ldr\t%H0, %2", operands);
13698 /* Compute <address> + 4 for the high order load. */
13699 operands[2] = gen_rtx_MEM (SImode,
13700 plus_constant (XEXP (operands[1], 0), 4));
13702 output_asm_insn ("ldr\t%0, %1", operands);
13703 output_asm_insn ("ldr\t%H0, %2", operands);
13707 arg1 = XEXP (addr, 0);
13708 arg2 = XEXP (addr, 1);
13710 if (CONSTANT_P (arg1))
13711 base = arg2, offset = arg1;
13713 base = arg1, offset = arg2;
13715 if (GET_CODE (base) != REG)
13718 /* Catch the case of <address> = <reg> + <reg> */
13719 if (GET_CODE (offset) == REG)
13721 int reg_offset = REGNO (offset);
13722 int reg_base = REGNO (base);
13723 int reg_dest = REGNO (operands[0]);
13725 /* Add the base and offset registers together into the
13726 higher destination register. */
13727 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13728 reg_dest + 1, reg_base, reg_offset);
13730 /* Load the lower destination register from the address in
13731 the higher destination register. */
13732 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13733 reg_dest, reg_dest + 1);
13735 /* Load the higher destination register from its own address
13737 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13738 reg_dest + 1, reg_dest + 1);
13742 /* Compute <address> + 4 for the high order load. */
13743 operands[2] = gen_rtx_MEM (SImode,
13744 plus_constant (XEXP (operands[1], 0), 4));
13746 /* If the computed address is held in the low order register
13747 then load the high order register first, otherwise always
13748 load the low order register first. */
13749 if (REGNO (operands[0]) == REGNO (base))
13751 output_asm_insn ("ldr\t%H0, %2", operands);
13752 output_asm_insn ("ldr\t%0, %1", operands);
13756 output_asm_insn ("ldr\t%0, %1", operands);
13757 output_asm_insn ("ldr\t%H0, %2", operands);
13763 /* With no registers to worry about we can just load the value
13765 operands[2] = gen_rtx_MEM (SImode,
13766 plus_constant (XEXP (operands[1], 0), 4));
13768 output_asm_insn ("ldr\t%H0, %2", operands);
13769 output_asm_insn ("ldr\t%0, %1", operands);
13781 thumb_output_move_mem_multiple (int n, rtx *operands)
13788 if (REGNO (operands[4]) > REGNO (operands[5]))
13791 operands[4] = operands[5];
13794 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13795 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13799 if (REGNO (operands[4]) > REGNO (operands[5]))
13802 operands[4] = operands[5];
13805 if (REGNO (operands[5]) > REGNO (operands[6]))
13808 operands[5] = operands[6];
13811 if (REGNO (operands[4]) > REGNO (operands[5]))
13814 operands[4] = operands[5];
13818 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13819 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13829 /* Routines for generating rtl. */
13831 thumb_expand_movmemqi (rtx *operands)
13833 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13834 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13835 HOST_WIDE_INT len = INTVAL (operands[2]);
13836 HOST_WIDE_INT offset = 0;
13840 emit_insn (gen_movmem12b (out, in, out, in));
13846 emit_insn (gen_movmem8b (out, in, out, in));
13852 rtx reg = gen_reg_rtx (SImode);
13853 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13854 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13861 rtx reg = gen_reg_rtx (HImode);
13862 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13863 plus_constant (in, offset))));
13864 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13872 rtx reg = gen_reg_rtx (QImode);
13873 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13874 plus_constant (in, offset))));
13875 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13881 thumb_cmp_operand (rtx op, enum machine_mode mode)
13883 return ((GET_CODE (op) == CONST_INT
13884 && INTVAL (op) < 256
13885 && INTVAL (op) >= 0)
13886 || s_register_operand (op, mode));
13890 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13892 return (GET_CODE (op) == CONST_INT
13894 && INTVAL (op) > -256);
13897 /* Return TRUE if a result can be stored in OP without clobbering the
13898 condition code register. Prior to reload we only accept a
13899 register. After reload we have to be able to handle memory as
13900 well, since a pseudo may not get a hard reg and reload cannot
13901 handle output-reloads on jump insns.
13903 We could possibly handle mem before reload as well, but that might
13904 complicate things with the need to handle increment
13908 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13910 return (s_register_operand (op, mode)
13911 || ((reload_in_progress || reload_completed)
13912 && memory_operand (op, mode)));
13915 /* Handle storing a half-word to memory during reload. */
13917 thumb_reload_out_hi (rtx *operands)
13919 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13922 /* Handle reading a half-word from memory during reload. */
13924 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13929 /* Return the length of a function name prefix
13930 that starts with the character 'c'. */
13932 arm_get_strip_length (int c)
13936 ARM_NAME_ENCODING_LENGTHS
13941 /* Return a pointer to a function's name with any
13942 and all prefix encodings stripped from it. */
13944 arm_strip_name_encoding (const char *name)
13948 while ((skip = arm_get_strip_length (* name)))
13954 /* If there is a '*' anywhere in the name's prefix, then
13955 emit the stripped name verbatim, otherwise prepend an
13956 underscore if leading underscores are being used. */
13958 arm_asm_output_labelref (FILE *stream, const char *name)
13963 while ((skip = arm_get_strip_length (* name)))
13965 verbatim |= (*name == '*');
13970 fputs (name, stream);
13972 asm_fprintf (stream, "%U%s", name);
13977 #ifdef AOF_ASSEMBLER
13978 /* Special functions only needed when producing AOF syntax assembler. */
13982 struct pic_chain * next;
13983 const char * symname;
13986 static struct pic_chain * aof_pic_chain = NULL;
13989 aof_pic_entry (rtx x)
13991 struct pic_chain ** chainp;
13994 if (aof_pic_label == NULL_RTX)
13996 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13999 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14000 offset += 4, chainp = &(*chainp)->next)
14001 if ((*chainp)->symname == XSTR (x, 0))
14002 return plus_constant (aof_pic_label, offset);
14004 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14005 (*chainp)->next = NULL;
14006 (*chainp)->symname = XSTR (x, 0);
14007 return plus_constant (aof_pic_label, offset);
14011 aof_dump_pic_table (FILE *f)
14013 struct pic_chain * chain;
14015 if (aof_pic_chain == NULL)
14018 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14019 PIC_OFFSET_TABLE_REGNUM,
14020 PIC_OFFSET_TABLE_REGNUM);
14021 fputs ("|x$adcons|\n", f);
14023 for (chain = aof_pic_chain; chain; chain = chain->next)
14025 fputs ("\tDCD\t", f);
14026 assemble_name (f, chain->symname);
14031 int arm_text_section_count = 1;
14034 aof_text_section (void )
14036 static char buf[100];
14037 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14038 arm_text_section_count++);
14040 strcat (buf, ", PIC, REENTRANT");
14044 static int arm_data_section_count = 1;
14047 aof_data_section (void)
14049 static char buf[100];
14050 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14054 /* The AOF assembler is religiously strict about declarations of
14055 imported and exported symbols, so that it is impossible to declare
14056 a function as imported near the beginning of the file, and then to
14057 export it later on. It is, however, possible to delay the decision
14058 until all the functions in the file have been compiled. To get
14059 around this, we maintain a list of the imports and exports, and
14060 delete from it any that are subsequently defined. At the end of
14061 compilation we spit the remainder of the list out before the END
14066 struct import * next;
14070 static struct import * imports_list = NULL;
14073 aof_add_import (const char *name)
14075 struct import * new;
14077 for (new = imports_list; new; new = new->next)
14078 if (new->name == name)
14081 new = (struct import *) xmalloc (sizeof (struct import));
14082 new->next = imports_list;
14083 imports_list = new;
14088 aof_delete_import (const char *name)
14090 struct import ** old;
14092 for (old = &imports_list; *old; old = & (*old)->next)
14094 if ((*old)->name == name)
14096 *old = (*old)->next;
14102 int arm_main_function = 0;
14105 aof_dump_imports (FILE *f)
14107 /* The AOF assembler needs this to cause the startup code to be extracted
14108 from the library. Brining in __main causes the whole thing to work
14110 if (arm_main_function)
14113 fputs ("\tIMPORT __main\n", f);
14114 fputs ("\tDCD __main\n", f);
14117 /* Now dump the remaining imports. */
14118 while (imports_list)
14120 fprintf (f, "\tIMPORT\t");
14121 assemble_name (f, imports_list->name);
14123 imports_list = imports_list->next;
14128 aof_globalize_label (FILE *stream, const char *name)
14130 default_globalize_label (stream, name);
14131 if (! strcmp (name, "main"))
14132 arm_main_function = 1;
14136 aof_file_start (void)
14138 fputs ("__r0\tRN\t0\n", asm_out_file);
14139 fputs ("__a1\tRN\t0\n", asm_out_file);
14140 fputs ("__a2\tRN\t1\n", asm_out_file);
14141 fputs ("__a3\tRN\t2\n", asm_out_file);
14142 fputs ("__a4\tRN\t3\n", asm_out_file);
14143 fputs ("__v1\tRN\t4\n", asm_out_file);
14144 fputs ("__v2\tRN\t5\n", asm_out_file);
14145 fputs ("__v3\tRN\t6\n", asm_out_file);
14146 fputs ("__v4\tRN\t7\n", asm_out_file);
14147 fputs ("__v5\tRN\t8\n", asm_out_file);
14148 fputs ("__v6\tRN\t9\n", asm_out_file);
14149 fputs ("__sl\tRN\t10\n", asm_out_file);
14150 fputs ("__fp\tRN\t11\n", asm_out_file);
14151 fputs ("__ip\tRN\t12\n", asm_out_file);
14152 fputs ("__sp\tRN\t13\n", asm_out_file);
14153 fputs ("__lr\tRN\t14\n", asm_out_file);
14154 fputs ("__pc\tRN\t15\n", asm_out_file);
14155 fputs ("__f0\tFN\t0\n", asm_out_file);
14156 fputs ("__f1\tFN\t1\n", asm_out_file);
14157 fputs ("__f2\tFN\t2\n", asm_out_file);
14158 fputs ("__f3\tFN\t3\n", asm_out_file);
14159 fputs ("__f4\tFN\t4\n", asm_out_file);
14160 fputs ("__f5\tFN\t5\n", asm_out_file);
14161 fputs ("__f6\tFN\t6\n", asm_out_file);
14162 fputs ("__f7\tFN\t7\n", asm_out_file);
14167 aof_file_end (void)
14170 aof_dump_pic_table (asm_out_file);
14171 aof_dump_imports (asm_out_file);
14172 fputs ("\tEND\n", asm_out_file);
14174 #endif /* AOF_ASSEMBLER */
14176 #ifdef OBJECT_FORMAT_ELF
14177 /* Switch to an arbitrary section NAME with attributes as specified
14178 by FLAGS. ALIGN specifies any known alignment requirements for
14179 the section; 0 if the default should be used.
14181 Differs from the default elf version only in the prefix character
14182 used before the section type. */
14185 arm_elf_asm_named_section (const char *name, unsigned int flags)
14187 char flagchars[10], *f = flagchars;
14189 if (! named_section_first_declaration (name))
14191 fprintf (asm_out_file, "\t.section\t%s\n", name);
14195 if (!(flags & SECTION_DEBUG))
14197 if (flags & SECTION_WRITE)
14199 if (flags & SECTION_CODE)
14201 if (flags & SECTION_SMALL)
14203 if (flags & SECTION_MERGE)
14205 if (flags & SECTION_STRINGS)
14207 if (flags & SECTION_TLS)
14211 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14213 if (!(flags & SECTION_NOTYPE))
14217 if (flags & SECTION_BSS)
14222 fprintf (asm_out_file, ",%%%s", type);
14224 if (flags & SECTION_ENTSIZE)
14225 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14228 putc ('\n', asm_out_file);
14233 /* Symbols in the text segment can be accessed without indirecting via the
14234 constant pool; it may take an extra binary operation, but this is still
14235 faster than indirecting via memory. Don't do this when not optimizing,
14236 since we won't be calculating al of the offsets necessary to do this
14240 arm_encode_section_info (tree decl, rtx rtl, int first)
14242 /* This doesn't work with AOF syntax, since the string table may be in
14243 a different AREA. */
14244 #ifndef AOF_ASSEMBLER
14245 if (optimize > 0 && TREE_CONSTANT (decl))
14246 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14249 /* If we are referencing a function that is weak then encode a long call
14250 flag in the function name, otherwise if the function is static or
14251 or known to be defined in this file then encode a short call flag. */
14252 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14254 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14255 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14256 else if (! TREE_PUBLIC (decl))
14257 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14260 #endif /* !ARM_PE */
14263 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14265 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14266 && !strcmp (prefix, "L"))
14268 arm_ccfsm_state = 0;
14269 arm_target_insn = NULL;
14271 default_internal_label (stream, prefix, labelno);
14274 /* Output code to add DELTA to the first argument, and then jump
14275 to FUNCTION. Used for C++ multiple inheritance. */
14277 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14278 HOST_WIDE_INT delta,
14279 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14282 static int thunk_label = 0;
14284 int mi_delta = delta;
14285 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14287 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14290 mi_delta = - mi_delta;
14293 int labelno = thunk_label++;
14294 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14295 fputs ("\tldr\tr12, ", file);
14296 assemble_name (file, label);
14297 fputc ('\n', file);
14299 while (mi_delta != 0)
14301 if ((mi_delta & (3 << shift)) == 0)
14305 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14306 mi_op, this_regno, this_regno,
14307 mi_delta & (0xff << shift));
14308 mi_delta &= ~(0xff << shift);
14314 fprintf (file, "\tbx\tr12\n");
14315 ASM_OUTPUT_ALIGN (file, 2);
14316 assemble_name (file, label);
14317 fputs (":\n", file);
14318 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14322 fputs ("\tb\t", file);
14323 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14324 if (NEED_PLT_RELOC)
14325 fputs ("(PLT)", file);
14326 fputc ('\n', file);
14331 arm_emit_vector_const (FILE *file, rtx x)
14334 const char * pattern;
14336 if (GET_CODE (x) != CONST_VECTOR)
14339 switch (GET_MODE (x))
14341 case V2SImode: pattern = "%08x"; break;
14342 case V4HImode: pattern = "%04x"; break;
14343 case V8QImode: pattern = "%02x"; break;
14347 fprintf (file, "0x");
14348 for (i = CONST_VECTOR_NUNITS (x); i--;)
14352 element = CONST_VECTOR_ELT (x, i);
14353 fprintf (file, pattern, INTVAL (element));
14360 arm_output_load_gr (rtx *operands)
14367 if (GET_CODE (operands [1]) != MEM
14368 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14369 || GET_CODE (reg = XEXP (sum, 0)) != REG
14370 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14371 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14372 return "wldrw%?\t%0, %1";
14374 /* Fix up an out-of-range load of a GR register. */
14375 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14376 wcgr = operands[0];
14378 output_asm_insn ("ldr%?\t%0, %1", operands);
14380 operands[0] = wcgr;
14382 output_asm_insn ("tmcr%?\t%0, %1", operands);
14383 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14389 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14390 int incoming ATTRIBUTE_UNUSED)
14393 /* FIXME: The ARM backend has special code to handle structure
14394 returns, and will reserve its own hidden first argument. So
14395 if this macro is enabled a *second* hidden argument will be
14396 reserved, which will break binary compatibility with old
14397 toolchains and also thunk handling. One day this should be
14401 /* Register in which address to store a structure value
14402 is passed to a function. */
14403 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14407 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14409 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14410 named arg and all anonymous args onto the stack.
14411 XXX I know the prologue shouldn't be pushing registers, but it is faster
14415 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14416 enum machine_mode mode ATTRIBUTE_UNUSED,
14417 tree type ATTRIBUTE_UNUSED,
14419 int second_time ATTRIBUTE_UNUSED)
14421 cfun->machine->uses_anonymous_args = 1;
14422 if (cum->nregs < NUM_ARG_REGS)
14423 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14426 /* Return nonzero if the CONSUMER instruction (a store) does not need
14427 PRODUCER's value to calculate the address. */
14430 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14432 rtx value = PATTERN (producer);
14433 rtx addr = PATTERN (consumer);
14435 if (GET_CODE (value) == COND_EXEC)
14436 value = COND_EXEC_CODE (value);
14437 if (GET_CODE (value) == PARALLEL)
14438 value = XVECEXP (value, 0, 0);
14439 value = XEXP (value, 0);
14440 if (GET_CODE (addr) == COND_EXEC)
14441 addr = COND_EXEC_CODE (addr);
14442 if (GET_CODE (addr) == PARALLEL)
14443 addr = XVECEXP (addr, 0, 0);
14444 addr = XEXP (addr, 0);
14446 return !reg_overlap_mentioned_p (value, addr);
14449 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14450 have an early register shift value or amount dependency on the
14451 result of PRODUCER. */
14454 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14456 rtx value = PATTERN (producer);
14457 rtx op = PATTERN (consumer);
14460 if (GET_CODE (value) == COND_EXEC)
14461 value = COND_EXEC_CODE (value);
14462 if (GET_CODE (value) == PARALLEL)
14463 value = XVECEXP (value, 0, 0);
14464 value = XEXP (value, 0);
14465 if (GET_CODE (op) == COND_EXEC)
14466 op = COND_EXEC_CODE (op);
14467 if (GET_CODE (op) == PARALLEL)
14468 op = XVECEXP (op, 0, 0);
14471 early_op = XEXP (op, 0);
14472 /* This is either an actual independent shift, or a shift applied to
14473 the first operand of another operation. We want the whole shift
14475 if (GET_CODE (early_op) == REG)
14478 return !reg_overlap_mentioned_p (value, early_op);
14481 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14482 have an early register shift value dependency on the result of
14486 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14488 rtx value = PATTERN (producer);
14489 rtx op = PATTERN (consumer);
14492 if (GET_CODE (value) == COND_EXEC)
14493 value = COND_EXEC_CODE (value);
14494 if (GET_CODE (value) == PARALLEL)
14495 value = XVECEXP (value, 0, 0);
14496 value = XEXP (value, 0);
14497 if (GET_CODE (op) == COND_EXEC)
14498 op = COND_EXEC_CODE (op);
14499 if (GET_CODE (op) == PARALLEL)
14500 op = XVECEXP (op, 0, 0);
14503 early_op = XEXP (op, 0);
14505 /* This is either an actual independent shift, or a shift applied to
14506 the first operand of another operation. We want the value being
14507 shifted, in either case. */
14508 if (GET_CODE (early_op) != REG)
14509 early_op = XEXP (early_op, 0);
14511 return !reg_overlap_mentioned_p (value, early_op);
14514 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14515 have an early register mult dependency on the result of
14519 arm_no_early_mul_dep (rtx producer, rtx consumer)
14521 rtx value = PATTERN (producer);
14522 rtx op = PATTERN (consumer);
14524 if (GET_CODE (value) == COND_EXEC)
14525 value = COND_EXEC_CODE (value);
14526 if (GET_CODE (value) == PARALLEL)
14527 value = XVECEXP (value, 0, 0);
14528 value = XEXP (value, 0);
14529 if (GET_CODE (op) == COND_EXEC)
14530 op = COND_EXEC_CODE (op);
14531 if (GET_CODE (op) == PARALLEL)
14532 op = XVECEXP (op, 0, 0);
14535 return (GET_CODE (op) == PLUS
14536 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14540 /* We can't rely on the caller doing the proper promotion when
14541 using APCS or ATPCS. */
14544 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14546 return !TARGET_AAPCS_BASED;
14550 /* AAPCS based ABIs use short enums by default. */
14553 arm_default_short_enums (void)
14555 return TARGET_AAPCS_BASED;
14559 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14562 arm_align_anon_bitfield (void)
14564 return TARGET_AAPCS_BASED;
14568 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14571 arm_cxx_guard_type (void)
14573 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14577 /* The EABI says test the least significan bit of a guard variable. */
14580 arm_cxx_guard_mask_bit (void)
14582 return TARGET_AAPCS_BASED;
14586 /* The EABI specifies that all array cookies are 8 bytes long. */
14589 arm_get_cookie_size (tree type)
14593 if (!TARGET_AAPCS_BASED)
14594 return default_cxx_get_cookie_size (type);
14596 size = build_int_2 (8, 0);
14597 TREE_TYPE (size) = sizetype;
14602 /* The EABI says that array cookies should also contain the element size. */
14605 arm_cookie_has_size (void)
14607 return TARGET_AAPCS_BASED;