1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
46 #define Mmode enum machine_mode
49 /* Some function declarations. */
50 static HOST_WIDE_INT int_log2 PARAMS ((HOST_WIDE_INT));
51 static char * output_multi_immediate PARAMS ((rtx *, char *, char *, int, HOST_WIDE_INT));
52 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, HOST_WIDE_INT, rtx, rtx, int, int));
53 static int arm_naked_function_p PARAMS ((tree));
54 static void init_fpa_table PARAMS ((void));
55 static enum machine_mode select_dominance_cc_mode PARAMS ((rtx, rtx, HOST_WIDE_INT));
56 static HOST_WIDE_INT add_minipool_constant PARAMS ((rtx, Mmode));
57 static void dump_minipool PARAMS ((rtx));
58 static rtx find_barrier PARAMS ((rtx, int));
59 static void push_minipool_fix PARAMS ((rtx, int, rtx *, Mmode, rtx));
60 static void push_minipool_barrier PARAMS ((rtx, int));
61 static void note_invalid_constants PARAMS ((rtx, int));
62 static char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
63 static int eliminate_lr2ip PARAMS ((rtx *));
64 static char * shift_op PARAMS ((rtx, HOST_WIDE_INT *));
65 static int pattern_really_clobbers_lr PARAMS ((rtx));
66 static int function_really_clobbers_lr PARAMS ((rtx));
67 static rtx emit_multi_reg_push PARAMS ((int));
68 static rtx emit_sfm PARAMS ((int, int));
69 static enum arm_cond_code get_arm_condition_code PARAMS ((rtx));
70 static int const_ok_for_op PARAMS ((HOST_WIDE_INT, enum rtx_code));
71 static void arm_add_gc_roots PARAMS ((void));
73 /* The maximum number of insns skipped which will be conditionalised if
75 static int max_insns_skipped = 5;
77 extern FILE * asm_out_file;
79 /* True if we are currently building a constant table. */
80 int making_const_table;
82 /* Define the information needed to generate branch insns. This is
83 stored from the compare operation. */
84 rtx arm_compare_op0, arm_compare_op1;
86 /* What type of floating point are we tuning for? */
87 enum floating_point_type arm_fpu;
89 /* What type of floating point instructions are available? */
90 enum floating_point_type arm_fpu_arch;
92 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
93 enum prog_mode_type arm_prgmode;
95 /* Set by the -mfp=... option. */
96 const char * target_fp_name = NULL;
98 /* Used to parse -mstructure_size_boundary command line option. */
99 const char * structure_size_string = NULL;
100 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
102 /* Bit values used to identify processor capabilities. */
103 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
104 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
105 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
106 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
107 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
108 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
109 #define FL_THUMB (1 << 6) /* Thumb aware */
110 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
111 #define FL_STRONG (1 << 8) /* StrongARM */
113 /* The bits in this mask specify which instructions we are allowed to
115 static int insn_flags = 0;
116 /* The bits in this mask specify which instruction scheduling options should
117 be used. Note - there is an overlap with the FL_FAST_MULT. For some
118 hardware we want to be able to generate the multiply instructions, but to
119 tune as if they were not present in the architecture. */
120 static int tune_flags = 0;
122 /* The following are used in the arm.md file as equivalents to bits
123 in the above two flag variables. */
125 /* Nonzero if this is an "M" variant of the processor. */
126 int arm_fast_multiply = 0;
128 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
131 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
134 /* Nonzero if this chip can benefit from load scheduling. */
135 int arm_ld_sched = 0;
137 /* Nonzero if this chip is a StrongARM. */
138 int arm_is_strong = 0;
140 /* Nonzero if this chip is a an ARM6 or an ARM7. */
141 int arm_is_6_or_7 = 0;
143 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
144 must report the mode of the memory reference from PRINT_OPERAND to
145 PRINT_OPERAND_ADDRESS. */
146 enum machine_mode output_memory_reference_mode;
148 /* Nonzero if the prologue must setup `fp'. */
149 int current_function_anonymous_args;
151 /* The register number to be used for the PIC offset register. */
152 const char * arm_pic_register_string = NULL;
153 int arm_pic_register = 9;
155 /* Set to one if we think that lr is only saved because of subroutine calls,
156 but all of these can be `put after' return insns. */
157 int lr_save_eliminated;
159 /* Set to 1 when a return insn is output, this means that the epilogue
161 static int return_used_this_function;
163 /* Set to 1 after arm_reorg has started. Reset to start at the start of
164 the next function. */
165 static int after_arm_reorg = 0;
167 /* The maximum number of insns to be used when loading a constant. */
168 static int arm_constant_limit = 3;
170 /* For an explanation of these variables, see final_prescan_insn below. */
172 enum arm_cond_code arm_current_cc;
174 int arm_target_label;
176 /* The condition codes of the ARM, and the inverse function. */
177 char * arm_condition_codes[] =
179 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
180 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
183 static enum arm_cond_code get_arm_condition_code ();
185 #define streq(string1, string2) (strcmp (string1, string2) == 0)
187 /* Initialization code. */
195 /* Not all of these give usefully different compilation alternatives,
196 but there is no simple way of generalizing them. */
197 static struct processors all_cores[] =
201 {"arm2", FL_CO_PROC | FL_MODE26 },
202 {"arm250", FL_CO_PROC | FL_MODE26 },
203 {"arm3", FL_CO_PROC | FL_MODE26 },
204 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
205 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
206 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm610", FL_MODE26 | FL_MODE32 },
208 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
210 /* arm7m doesn't exist on its own, but only with D, (and I), but
211 those don't alter the code, so arm7m is sometimes used. */
212 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
213 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
214 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
215 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
216 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
217 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
218 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
219 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
220 {"arm710", FL_MODE26 | FL_MODE32 },
221 {"arm720", FL_MODE26 | FL_MODE32 },
222 {"arm710c", FL_MODE26 | FL_MODE32 },
223 {"arm7100", FL_MODE26 | FL_MODE32 },
224 {"arm7500", FL_MODE26 | FL_MODE32 },
225 /* Doesn't have an external co-proc, but does have embedded fpu. */
226 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
227 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
228 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
229 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
230 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
231 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
232 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
233 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
234 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
235 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
236 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
241 static struct processors all_architectures[] =
243 /* ARM Architectures */
245 { "armv2", FL_CO_PROC | FL_MODE26 },
246 { "armv2a", FL_CO_PROC | FL_MODE26 },
247 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
248 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
249 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
250 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
251 implementations that support it, so we will leave it out for now. */
252 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
253 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
257 /* This is a magic stucture. The 'string' field is magically filled in
258 with a pointer to the value specified by the user on the command line
259 assuming that the user has specified such a value. */
261 struct arm_cpu_select arm_select[] =
263 /* string name processors */
264 { NULL, "-mcpu=", all_cores },
265 { NULL, "-march=", all_architectures },
266 { NULL, "-mtune=", all_cores }
269 /* Return the number of bits set in value' */
274 unsigned int count = 0;
278 value &= ~(value & - value);
285 /* Fix up any incompatible options that the user has specified.
286 This has now turned into a maze. */
288 arm_override_options ()
292 /* Set up the flags based on the cpu/architecture selected by the user. */
293 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
295 struct arm_cpu_select * ptr = arm_select + i;
297 if (ptr->string != NULL && ptr->string[0] != '\0')
299 const struct processors * sel;
301 for (sel = ptr->processors; sel->name != NULL; sel ++)
302 if (streq (ptr->string, sel->name))
305 tune_flags = sel->flags;
308 /* If we have been given an architecture and a processor
309 make sure that they are compatible. We only generate
310 a warning though, and we prefer the CPU over the
312 if (insn_flags != 0 && (insn_flags ^ sel->flags))
313 warning ("switch -mcpu=%s conflicts with -march= switch",
316 insn_flags = sel->flags;
322 if (sel->name == NULL)
323 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
327 /* If the user did not specify a processor, choose one for them. */
330 struct processors * sel;
332 static struct cpu_default
339 { TARGET_CPU_arm2, "arm2" },
340 { TARGET_CPU_arm6, "arm6" },
341 { TARGET_CPU_arm610, "arm610" },
342 { TARGET_CPU_arm710, "arm710" },
343 { TARGET_CPU_arm7m, "arm7m" },
344 { TARGET_CPU_arm7500fe, "arm7500fe" },
345 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
346 { TARGET_CPU_arm8, "arm8" },
347 { TARGET_CPU_arm810, "arm810" },
348 { TARGET_CPU_arm9, "arm9" },
349 { TARGET_CPU_strongarm, "strongarm" },
350 { TARGET_CPU_generic, "arm" },
353 struct cpu_default * def;
355 /* Find the default. */
356 for (def = cpu_defaults; def->name; def ++)
357 if (def->cpu == TARGET_CPU_DEFAULT)
360 /* Make sure we found the default CPU. */
361 if (def->name == NULL)
364 /* Find the default CPU's flags. */
365 for (sel = all_cores; sel->name != NULL; sel ++)
366 if (streq (def->name, sel->name))
369 if (sel->name == NULL)
372 insn_flags = sel->flags;
374 /* Now check to see if the user has specified some command line
375 switch that require certain abilities from the cpu. */
378 if (TARGET_INTERWORK)
380 sought |= (FL_THUMB | FL_MODE32);
382 /* Force apcs-32 to be used for interworking. */
383 target_flags |= ARM_FLAG_APCS_32;
385 /* There are no ARM processor that supports both APCS-26 and
386 interworking. Therefore we force FL_MODE26 to be removed
387 from insn_flags here (if it was set), so that the search
388 below will always be able to find a compatible processor. */
389 insn_flags &= ~ FL_MODE26;
392 if (! TARGET_APCS_32)
395 if (sought != 0 && ((sought & insn_flags) != sought))
397 /* Try to locate a CPU type that supports all of the abilities
398 of the default CPU, plus the extra abilities requested by
400 for (sel = all_cores; sel->name != NULL; sel ++)
401 if ((sel->flags & sought) == (sought | insn_flags))
404 if (sel->name == NULL)
406 unsigned int current_bit_count = 0;
407 struct processors * best_fit = NULL;
409 /* Ideally we would like to issue an error message here
410 saying that it was not possible to find a CPU compatible
411 with the default CPU, but which also supports the command
412 line options specified by the programmer, and so they
413 ought to use the -mcpu=<name> command line option to
414 override the default CPU type.
416 Unfortunately this does not work with multilibing. We
417 need to be able to support multilibs for -mapcs-26 and for
418 -mthumb-interwork and there is no CPU that can support both
419 options. Instead if we cannot find a cpu that has both the
420 characteristics of the default cpu and the given command line
421 options we scan the array again looking for a best match. */
422 for (sel = all_cores; sel->name != NULL; sel ++)
423 if ((sel->flags & sought) == sought)
427 count = bit_count (sel->flags & insn_flags);
429 if (count >= current_bit_count)
432 current_bit_count = count;
436 if (best_fit == NULL)
442 insn_flags = sel->flags;
446 /* If tuning has not been specified, tune for whichever processor or
447 architecture has been selected. */
449 tune_flags = insn_flags;
451 /* Make sure that the processor choice does not conflict with any of the
452 other command line choices. */
453 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
455 /* If APCS-32 was not the default then it must have been set by the
456 user, so issue a warning message. If the user has specified
457 "-mapcs-32 -mcpu=arm2" then we loose here. */
458 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
459 warning ("target CPU does not support APCS-32" );
460 target_flags &= ~ ARM_FLAG_APCS_32;
462 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
464 warning ("target CPU does not support APCS-26" );
465 target_flags |= ARM_FLAG_APCS_32;
468 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
470 warning ("target CPU does not support interworking" );
471 target_flags &= ~ARM_FLAG_INTERWORK;
474 /* If interworking is enabled then APCS-32 must be selected as well. */
475 if (TARGET_INTERWORK)
477 if (! TARGET_APCS_32)
478 warning ("interworking forces APCS-32 to be used" );
479 target_flags |= ARM_FLAG_APCS_32;
482 if (TARGET_APCS_STACK && ! TARGET_APCS)
484 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
485 target_flags |= ARM_FLAG_APCS_FRAME;
488 if (TARGET_POKE_FUNCTION_NAME)
489 target_flags |= ARM_FLAG_APCS_FRAME;
491 if (TARGET_APCS_REENT && flag_pic)
492 fatal ("-fpic and -mapcs-reent are incompatible");
494 if (TARGET_APCS_REENT)
495 warning ("APCS reentrant code not supported. Ignored");
497 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
498 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
500 /* If stack checking is disabled, we can use r10 as the PIC register,
501 which keeps r9 available. */
502 if (flag_pic && ! TARGET_APCS_STACK)
503 arm_pic_register = 10;
505 if (TARGET_APCS_FLOAT)
506 warning ("Passing floating point arguments in fp regs not yet supported");
508 /* Initialise boolean versions of the flags, for use in the arm.md file. */
509 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
510 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
511 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
513 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
514 arm_is_strong = (tune_flags & FL_STRONG) != 0;
515 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
516 && !(tune_flags & FL_ARCH4)) != 0;
518 /* Default value for floating point code... if no co-processor
519 bus, then schedule for emulated floating point. Otherwise,
520 assume the user has an FPA.
521 Note: this does not prevent use of floating point instructions,
522 -msoft-float does that. */
523 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
527 if (streq (target_fp_name, "2"))
528 arm_fpu_arch = FP_SOFT2;
529 else if (streq (target_fp_name, "3"))
530 arm_fpu_arch = FP_SOFT3;
532 fatal ("Invalid floating point emulation option: -mfpe-%s",
536 arm_fpu_arch = FP_DEFAULT;
538 if (TARGET_FPE && arm_fpu != FP_HARD)
541 /* For arm2/3 there is no need to do any scheduling if there is only
542 a floating point emulator, or we are doing software floating-point. */
543 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
544 && (tune_flags & FL_MODE32) == 0)
545 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
547 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
549 if (structure_size_string != NULL)
551 int size = strtol (structure_size_string, NULL, 0);
553 if (size == 8 || size == 32)
554 arm_structure_size_boundary = size;
556 warning ("Structure size boundary can only be set to 8 or 32");
559 if (arm_pic_register_string != NULL)
564 warning ("-mpic-register= is useless without -fpic");
566 pic_register = decode_reg_name (arm_pic_register_string);
568 /* Prevent the user from choosing an obviously stupid PIC register. */
569 if (pic_register < 0 || call_used_regs[pic_register]
570 || pic_register == HARD_FRAME_POINTER_REGNUM
571 || pic_register == STACK_POINTER_REGNUM
572 || pic_register >= PC_REGNUM)
573 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
575 arm_pic_register = pic_register;
578 /* If optimizing for space, don't synthesize constants.
579 For processors with load scheduling, it never costs more than 2 cycles
580 to load a constant, and the load scheduler may well reduce that to 1. */
581 if (optimize_size || (tune_flags & FL_LDSCHED))
582 arm_constant_limit = 1;
584 /* If optimizing for size, bump the number of instructions that we
585 are prepared to conditionally execute (even on a StrongARM).
586 Otherwise for the StrongARM, which has early execution of branches,
587 a sequence that is worth skipping is shorter. */
589 max_insns_skipped = 6;
590 else if (arm_is_strong)
591 max_insns_skipped = 3;
593 /* Register global variables with the garbage collector. */
600 ggc_add_rtx_root (&arm_compare_op0, 1);
601 ggc_add_rtx_root (&arm_compare_op1, 1);
602 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
603 /* XXX: What about the minipool tables? */
607 /* Return 1 if it is possible to return using a single instruction. */
609 use_return_insn (iscond)
614 if (!reload_completed
615 || current_function_pretend_args_size
616 || current_function_anonymous_args
617 || ((get_frame_size () + current_function_outgoing_args_size != 0)
618 && !(TARGET_APCS && frame_pointer_needed)))
621 /* Can't be done if interworking with Thumb, and any registers have been
622 stacked. Similarly, on StrongARM, conditional returns are expensive
623 if they aren't taken and registers have been stacked. */
624 if (iscond && arm_is_strong && frame_pointer_needed)
626 if ((iscond && arm_is_strong)
629 for (regno = 0; regno < 16; regno++)
630 if (regs_ever_live[regno] && ! call_used_regs[regno])
633 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
637 /* Can't be done if any of the FPU regs are pushed, since this also
639 for (regno = 16; regno < 24; regno++)
640 if (regs_ever_live[regno] && ! call_used_regs[regno])
643 /* If a function is naked, don't use the "return" insn. */
644 if (arm_naked_function_p (current_function_decl))
650 /* Return TRUE if int I is a valid immediate ARM constant. */
656 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
658 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
659 be all zero, or all one. */
660 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
661 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
662 != ((~(unsigned HOST_WIDE_INT) 0)
663 & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
666 /* Fast return for 0 and powers of 2 */
667 if ((i & (i - 1)) == 0)
672 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
675 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
676 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
677 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
682 /* Return true if I is a valid constant for the operation CODE. */
684 const_ok_for_op (i, code)
688 if (const_ok_for_arm (i))
694 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
696 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
702 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
709 /* Emit a sequence of insns to handle a large constant.
710 CODE is the code of the operation required, it can be any of SET, PLUS,
711 IOR, AND, XOR, MINUS;
712 MODE is the mode in which the operation is being performed;
713 VAL is the integer to operate on;
714 SOURCE is the other operand (a register, or a null-pointer for SET);
715 SUBTARGETS means it is safe to create scratch registers if that will
716 either produce a simpler sequence, or we will want to cse the values.
717 Return value is the number of insns emitted. */
720 arm_split_constant (code, mode, val, target, source, subtargets)
722 enum machine_mode mode;
728 if (subtargets || code == SET
729 || (GET_CODE (target) == REG && GET_CODE (source) == REG
730 && REGNO (target) != REGNO (source)))
732 /* After arm_reorg has been called, we can't fix up expensive
733 constants by pushing them into memory so we must synthesise
734 them in-line, regardless of the cost. This is only likely to
735 be more costly on chips that have load delay slots and we are
736 compiling without running the scheduler (so no splitting
737 occurred before the final instruction emission).
739 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
741 if (! after_arm_reorg
742 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
743 > arm_constant_limit + (code != SET)))
747 /* Currently SET is the only monadic value for CODE, all
748 the rest are diadic. */
749 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
754 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
756 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
757 /* For MINUS, the value is subtracted from, since we never
758 have subtraction of a constant. */
760 emit_insn (gen_rtx_SET (VOIDmode, target,
761 gen_rtx (code, mode, temp, source)));
763 emit_insn (gen_rtx_SET (VOIDmode, target,
764 gen_rtx (code, mode, source, temp)));
770 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
773 /* As above, but extra parameter GENERATE which, if clear, suppresses
776 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
778 enum machine_mode mode;
787 int can_negate_initial = 0;
790 int num_bits_set = 0;
791 int set_sign_bit_copies = 0;
792 int clear_sign_bit_copies = 0;
793 int clear_zero_bit_copies = 0;
794 int set_zero_bit_copies = 0;
796 unsigned HOST_WIDE_INT temp1, temp2;
797 unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
799 /* find out which operations are safe for a given CODE. Also do a quick
800 check for degenerate cases; these can occur when DImode operations
812 can_negate_initial = 1;
816 if (remainder == 0xffffffffUL)
819 emit_insn (gen_rtx_SET (VOIDmode, target,
820 GEN_INT (ARM_SIGN_EXTEND (val))));
825 if (reload_completed && rtx_equal_p (target, source))
828 emit_insn (gen_rtx_SET (VOIDmode, target, source));
837 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
840 if (remainder == 0xffffffffUL)
842 if (reload_completed && rtx_equal_p (target, source))
845 emit_insn (gen_rtx_SET (VOIDmode, target, source));
854 if (reload_completed && rtx_equal_p (target, source))
857 emit_insn (gen_rtx_SET (VOIDmode, target, source));
860 if (remainder == 0xffffffffUL)
863 emit_insn (gen_rtx_SET (VOIDmode, target,
864 gen_rtx_NOT (mode, source)));
868 /* We don't know how to handle this yet below. */
872 /* We treat MINUS as (val - source), since (source - val) is always
873 passed as (source + (-val)). */
877 emit_insn (gen_rtx_SET (VOIDmode, target,
878 gen_rtx_NEG (mode, source)));
881 if (const_ok_for_arm (val))
884 emit_insn (gen_rtx_SET (VOIDmode, target,
885 gen_rtx_MINUS (mode, GEN_INT (val),
897 /* If we can do it in one insn get out quickly. */
898 if (const_ok_for_arm (val)
899 || (can_negate_initial && const_ok_for_arm (-val))
900 || (can_invert && const_ok_for_arm (~val)))
903 emit_insn (gen_rtx_SET (VOIDmode, target,
904 (source ? gen_rtx (code, mode, source,
910 /* Calculate a few attributes that may be useful for specific
912 for (i = 31; i >= 0; i--)
914 if ((remainder & (1 << i)) == 0)
915 clear_sign_bit_copies++;
920 for (i = 31; i >= 0; i--)
922 if ((remainder & (1 << i)) != 0)
923 set_sign_bit_copies++;
928 for (i = 0; i <= 31; i++)
930 if ((remainder & (1 << i)) == 0)
931 clear_zero_bit_copies++;
936 for (i = 0; i <= 31; i++)
938 if ((remainder & (1 << i)) != 0)
939 set_zero_bit_copies++;
947 /* See if we can do this by sign_extending a constant that is known
948 to be negative. This is a good, way of doing it, since the shift
949 may well merge into a subsequent insn. */
950 if (set_sign_bit_copies > 1)
953 (temp1 = ARM_SIGN_EXTEND (remainder
954 << (set_sign_bit_copies - 1))))
958 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
959 emit_insn (gen_rtx_SET (VOIDmode, new_src,
961 emit_insn (gen_ashrsi3 (target, new_src,
962 GEN_INT (set_sign_bit_copies - 1)));
966 /* For an inverted constant, we will need to set the low bits,
967 these will be shifted out of harm's way. */
968 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
969 if (const_ok_for_arm (~temp1))
973 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
974 emit_insn (gen_rtx_SET (VOIDmode, new_src,
976 emit_insn (gen_ashrsi3 (target, new_src,
977 GEN_INT (set_sign_bit_copies - 1)));
983 /* See if we can generate this by setting the bottom (or the top)
984 16 bits, and then shifting these into the other half of the
985 word. We only look for the simplest cases, to do more would cost
986 too much. Be careful, however, not to generate this when the
987 alternative would take fewer insns. */
988 if (val & 0xffff0000UL)
990 temp1 = remainder & 0xffff0000UL;
991 temp2 = remainder & 0x0000ffff;
993 /* Overlaps outside this range are best done using other methods. */
994 for (i = 9; i < 24; i++)
996 if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
997 && ! const_ok_for_arm (temp2))
999 rtx new_src = (subtargets
1000 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1002 insns = arm_gen_constant (code, mode, temp2, new_src,
1003 source, subtargets, generate);
1006 emit_insn (gen_rtx_SET
1009 gen_rtx_ASHIFT (mode, source,
1016 /* Don't duplicate cases already considered. */
1017 for (i = 17; i < 24; i++)
1019 if (((temp1 | (temp1 >> i)) == remainder)
1020 && ! const_ok_for_arm (temp1))
1022 rtx new_src = (subtargets
1023 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1025 insns = arm_gen_constant (code, mode, temp1, new_src,
1026 source, subtargets, generate);
1030 (gen_rtx_SET (VOIDmode, target,
1033 gen_rtx_LSHIFTRT (mode, source,
1044 /* If we have IOR or XOR, and the constant can be loaded in a
1045 single instruction, and we can find a temporary to put it in,
1046 then this can be done in two instructions instead of 3-4. */
1048 /* TARGET can't be NULL if SUBTARGETS is 0 */
1049 || (reload_completed && ! reg_mentioned_p (target, source)))
1051 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1055 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1057 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1058 emit_insn (gen_rtx_SET (VOIDmode, target,
1059 gen_rtx (code, mode, source, sub)));
1068 if (set_sign_bit_copies > 8
1069 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1073 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1074 rtx shift = GEN_INT (set_sign_bit_copies);
1076 emit_insn (gen_rtx_SET (VOIDmode, sub,
1078 gen_rtx_ASHIFT (mode,
1081 emit_insn (gen_rtx_SET (VOIDmode, target,
1083 gen_rtx_LSHIFTRT (mode, sub,
1089 if (set_zero_bit_copies > 8
1090 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1094 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1095 rtx shift = GEN_INT (set_zero_bit_copies);
1097 emit_insn (gen_rtx_SET (VOIDmode, sub,
1099 gen_rtx_LSHIFTRT (mode,
1102 emit_insn (gen_rtx_SET (VOIDmode, target,
1104 gen_rtx_ASHIFT (mode, sub,
1110 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1114 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1115 emit_insn (gen_rtx_SET (VOIDmode, sub,
1116 gen_rtx_NOT (mode, source)));
1119 sub = gen_reg_rtx (mode);
1120 emit_insn (gen_rtx_SET (VOIDmode, sub,
1121 gen_rtx_AND (mode, source,
1123 emit_insn (gen_rtx_SET (VOIDmode, target,
1124 gen_rtx_NOT (mode, sub)));
1131 /* See if two shifts will do 2 or more insn's worth of work. */
1132 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1134 HOST_WIDE_INT shift_mask = ((0xffffffffUL
1135 << (32 - clear_sign_bit_copies))
1138 if ((remainder | shift_mask) != 0xffffffffUL)
1142 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1143 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1144 new_src, source, subtargets, 1);
1149 rtx targ = subtargets ? NULL_RTX : target;
1150 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1151 targ, source, subtargets, 0);
1157 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1158 rtx shift = GEN_INT (clear_sign_bit_copies);
1160 emit_insn (gen_ashlsi3 (new_src, source, shift));
1161 emit_insn (gen_lshrsi3 (target, new_src, shift));
1167 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1169 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1171 if ((remainder | shift_mask) != 0xffffffffUL)
1175 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1177 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1178 new_src, source, subtargets, 1);
1183 rtx targ = subtargets ? NULL_RTX : target;
1185 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1186 targ, source, subtargets, 0);
1192 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1193 rtx shift = GEN_INT (clear_zero_bit_copies);
1195 emit_insn (gen_lshrsi3 (new_src, source, shift));
1196 emit_insn (gen_ashlsi3 (target, new_src, shift));
1208 for (i = 0; i < 32; i++)
1209 if (remainder & (1 << i))
1212 if (code == AND || (can_invert && num_bits_set > 16))
1213 remainder = (~remainder) & 0xffffffffUL;
1214 else if (code == PLUS && num_bits_set > 16)
1215 remainder = (-remainder) & 0xffffffffUL;
1222 /* Now try and find a way of doing the job in either two or three
1224 We start by looking for the largest block of zeros that are aligned on
1225 a 2-bit boundary, we then fill up the temps, wrapping around to the
1226 top of the word when we drop off the bottom.
1227 In the worst case this code should produce no more than four insns. */
1230 int best_consecutive_zeros = 0;
1232 for (i = 0; i < 32; i += 2)
1234 int consecutive_zeros = 0;
1236 if (! (remainder & (3 << i)))
1238 while ((i < 32) && ! (remainder & (3 << i)))
1240 consecutive_zeros += 2;
1243 if (consecutive_zeros > best_consecutive_zeros)
1245 best_consecutive_zeros = consecutive_zeros;
1246 best_start = i - consecutive_zeros;
1252 /* Now start emitting the insns, starting with the one with the highest
1253 bit set: we do this so that the smallest number will be emitted last;
1254 this is more likely to be combinable with addressing insns. */
1262 if (remainder & (3 << (i - 2)))
1267 temp1 = remainder & ((0x0ff << end)
1268 | ((i < end) ? (0xff >> (32 - end)) : 0));
1269 remainder &= ~temp1;
1276 emit_insn (gen_rtx_SET (VOIDmode,
1277 new_src = (subtargets
1278 ? gen_reg_rtx (mode)
1281 ? ~temp1 : temp1)));
1282 else if (code == MINUS)
1283 emit_insn (gen_rtx_SET (VOIDmode,
1284 new_src = (subtargets
1285 ? gen_reg_rtx (mode)
1287 gen_rtx (code, mode, GEN_INT (temp1),
1290 emit_insn (gen_rtx_SET (VOIDmode,
1291 new_src = (remainder
1293 ? gen_reg_rtx (mode)
1296 gen_rtx (code, mode, source,
1297 GEN_INT (can_invert ? ~temp1
1309 else if (code == MINUS)
1316 } while (remainder);
1321 /* Canonicalize a comparison so that we are more likely to recognize it.
1322 This can be done for a few constant compares, where we can make the
1323 immediate value easier to load. */
1325 arm_canonicalize_comparison (code, op1)
1329 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1339 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1341 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1343 *op1 = GEN_INT (i+1);
1344 return code == GT ? GE : LT;
1350 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1351 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1353 *op1 = GEN_INT (i-1);
1354 return code == GE ? GT : LE;
1360 if (i != ~((unsigned HOST_WIDE_INT) 0)
1361 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1363 *op1 = GEN_INT (i + 1);
1364 return code == GTU ? GEU : LTU;
1371 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1373 *op1 = GEN_INT (i - 1);
1374 return code == GEU ? GTU : LEU;
1385 /* Decide whether a type should be returned in memory (true)
1386 or in a register (false). This is called by the macro
1387 RETURN_IN_MEMORY. */
1389 arm_return_in_memory (type)
1392 if (! AGGREGATE_TYPE_P (type))
1393 /* All simple types are returned in registers. */
1396 if (int_size_in_bytes (type) > 4)
1397 /* All structures/unions bigger than one word are returned in memory. */
1400 if (TREE_CODE (type) == RECORD_TYPE)
1404 /* For a struct the APCS says that we only return in a register
1405 if the type is 'integer like' and every addressable element
1406 has an offset of zero. For practical purposes this means
1407 that the structure can have at most one non bit-field element
1408 and that this element must be the first one in the structure. */
1410 /* Find the first field, ignoring non FIELD_DECL things which will
1411 have been created by C++. */
1412 for (field = TYPE_FIELDS (type);
1413 field && TREE_CODE (field) != FIELD_DECL;
1414 field = TREE_CHAIN (field))
1418 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1420 /* Check that the first field is valid for returning in a register... */
1421 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1424 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1427 /* Now check the remaining fields, if any. Only bitfields are allowed,
1428 since they are not addressable. */
1429 for (field = TREE_CHAIN (field);
1431 field = TREE_CHAIN (field))
1433 if (TREE_CODE (field) != FIELD_DECL)
1436 if (! DECL_BIT_FIELD_TYPE (field))
1443 if (TREE_CODE (type) == UNION_TYPE)
1447 /* Unions can be returned in registers if every element is
1448 integral, or can be returned in an integer register. */
1449 for (field = TYPE_FIELDS (type);
1451 field = TREE_CHAIN (field))
1453 if (TREE_CODE (field) != FIELD_DECL)
1456 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1459 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1466 /* Put other aggregates in memory. */
1470 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1471 for a call to a function whose data type is FNTYPE.
1472 For a library call, FNTYPE is NULL. */
1474 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1475 CUMULATIVE_ARGS * pcum;
1477 rtx libname ATTRIBUTE_UNUSED;
1478 int indirect ATTRIBUTE_UNUSED;
1480 /* On the ARM, the offset starts at 0. */
1481 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1483 pcum->call_cookie = CALL_NORMAL;
1485 if (TARGET_LONG_CALLS)
1486 pcum->call_cookie = CALL_LONG;
1488 /* Check for long call/short call attributes. The attributes
1489 override any command line option. */
1492 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1493 pcum->call_cookie = CALL_SHORT;
1494 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1495 pcum->call_cookie = CALL_LONG;
1499 /* Determine where to put an argument to a function.
1500 Value is zero to push the argument on the stack,
1501 or a hard register in which to store the argument.
1503 MODE is the argument's machine mode.
1504 TYPE is the data type of the argument (as a tree).
1505 This is null for libcalls where that information may
1507 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1508 the preceding args and about the function being called.
1509 NAMED is nonzero if this argument is a named parameter
1510 (otherwise it is an extra parameter matching an ellipsis). */
1512 arm_function_arg (pcum, mode, type, named)
1513 CUMULATIVE_ARGS * pcum;
1514 enum machine_mode mode;
1515 tree type ATTRIBUTE_UNUSED;
1518 if (mode == VOIDmode)
1519 /* Compute operand 2 of the call insn. */
1520 return GEN_INT (pcum->call_cookie);
1522 if (! named || pcum->nregs >= NUM_ARG_REGS)
1525 return gen_rtx_REG (mode, pcum->nregs);
1528 /* Encode the current state of the #pragma [no_]long_calls. */
1531 OFF, /* No #pramgma [no_]long_calls is in effect. */
1532 LONG, /* #pragma long_calls is in effect. */
1533 SHORT /* #pragma no_long_calls is in effect. */
1536 static arm_pragma_enum arm_pragma_long_calls = OFF;
1538 /* Handle pragmas for compatibility with Intel's compilers.
1539 FIXME: This is incomplete, since it does not handle all
1540 the pragmas that the Intel compilers understand. */
1542 arm_process_pragma (p_getc, p_ungetc, pname)
1543 int (* p_getc) PARAMS ((void)) ATTRIBUTE_UNUSED;
1544 void (* p_ungetc) PARAMS ((int)) ATTRIBUTE_UNUSED;
1547 /* Should be pragma 'far' or equivalent for callx/balx here. */
1548 if (strcmp (pname, "long_calls") == 0)
1549 arm_pragma_long_calls = LONG;
1550 else if (strcmp (pname, "no_long_calls") == 0)
1551 arm_pragma_long_calls = SHORT;
1552 else if (strcmp (pname, "long_calls_off") == 0)
1553 arm_pragma_long_calls = OFF;
1560 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1561 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1562 assigned to TYPE. */
1564 arm_valid_type_attribute_p (type, attributes, identifier, args)
1566 tree attributes ATTRIBUTE_UNUSED;
1570 if ( TREE_CODE (type) != FUNCTION_TYPE
1571 && TREE_CODE (type) != METHOD_TYPE
1572 && TREE_CODE (type) != FIELD_DECL
1573 && TREE_CODE (type) != TYPE_DECL)
1576 /* Function calls made to this symbol must be done indirectly, because
1577 it may lie outside of the 26 bit addressing range of a normal function
1579 if (is_attribute_p ("long_call", identifier))
1580 return (args == NULL_TREE);
1582 /* Whereas these functions are always known to reside within the 26 bit
1583 addressing range. */
1584 if (is_attribute_p ("short_call", identifier))
1585 return (args == NULL_TREE);
1590 /* Return 0 if the attributes for two types are incompatible, 1 if they
1591 are compatible, and 2 if they are nearly compatible (which causes a
1592 warning to be generated). */
1594 arm_comp_type_attributes (type1, type2)
1600 /* Check for mismatch of non-default calling convention. */
1601 if (TREE_CODE (type1) != FUNCTION_TYPE)
1604 /* Check for mismatched call attributes. */
1605 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1606 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1607 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1608 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1610 /* Only bother to check if an attribute is defined. */
1611 if (l1 | l2 | s1 | s2)
1613 /* If one type has an attribute, the other must have the same attribute. */
1614 if ((l1 != l2) || (s1 != s2))
1617 /* Disallow mixed attributes. */
1618 if ((l1 & s2) || (l2 & s1))
1625 /* Check the ARM specific attributes on the given function decl.
1626 If any of them would prevent the function from being inlined,
1627 return a tesxtual description of why not. Otherwise return NULL. */
1629 arm_function_attribute_inlineable_p (fndecl)
1632 if (lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (fndecl)))
1633 return "naked functions cannot be inlined";
1635 /* Allow functions with short_call and long_call attributes to be inlined. */
1639 /* Encode long_call or short_call attribute by prefixing
1640 symbol name in DECL with a special character FLAG. */
1642 arm_encode_call_attribute (decl, flag)
1646 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1647 int len = strlen (str);
1650 if (TREE_CODE (decl) != FUNCTION_DECL)
1653 /* Do not allow weak functions to be treated as short call. */
1654 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1658 newstr = ggc_alloc_string (NULL, len + 2);
1660 newstr = permalloc (len + 2);
1662 sprintf (newstr, "%c%s", flag, str);
1664 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1667 /* Assigns default attributes to newly defined type. This is used to
1668 set short_call/long_call attributes for function types of
1669 functions defined inside corresponding #pragma scopes. */
1671 arm_set_default_type_attributes (type)
1674 /* Add __attribute__ ((long_call)) to all functions, when
1675 inside #pragma long_calls or __attribute__ ((short_call)),
1676 when inside #pragma no_long_calls. */
1677 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
1679 tree type_attr_list, attr_name;
1680 type_attr_list = TYPE_ATTRIBUTES (type);
1682 if (arm_pragma_long_calls == LONG)
1683 attr_name = get_identifier ("long_call");
1684 else if (arm_pragma_long_calls == SHORT)
1685 attr_name = get_identifier ("short_call");
1689 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
1690 TYPE_ATTRIBUTES (type) = type_attr_list;
1694 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1695 defined within the current compilation unit. If this caanot be
1696 determined, then 0 is returned. */
1698 current_file_function_operand (sym_ref)
1701 /* This is a bit of a fib. A function will have a short call flag
1702 applied to its name if it has the short call attribute, or it has
1703 already been defined within the current compilation unit. */
1704 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
1707 /* The current funciton is always defined within the current compilation
1708 unit. if it s a weak defintion however, then this may not be the real
1709 defintion of the function, and so we have to say no. */
1710 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
1711 && ! DECL_WEAK (current_function_decl))
1714 /* We cannot make the determination - default to returning 0. */
1718 /* Return non-zero if a 32 bit "long_call" should be generated for
1719 this call. We generate a long_call if the function:
1721 a. has an __attribute__((long call))
1722 or b. is within the scope of a #pragma long_calls
1723 or c. the -mlong-calls command line switch has been specified
1725 However we do not generate a long call if the function:
1727 d. has an __attribute__ ((short_call))
1728 or e. is inside the scope of a #pragma no_long_calls
1729 or f. has an __attribute__ ((section))
1730 or g. is defined within the current compilation unit.
1732 This function will be called by C fragments contained in the machine
1733 description file. CALL_REF and CALL_COOKIE correspond to the matched
1734 rtl operands. CALL_SYMBOL is used to distinguish between
1735 two different callers of the function. It is set to 1 in the
1736 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1737 and "call_value" patterns. This is because of the difference in the
1738 SYM_REFs passed by these patterns. */
1740 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
1747 if (GET_CODE (sym_ref) != MEM)
1750 sym_ref = XEXP (sym_ref, 0);
1753 if (GET_CODE (sym_ref) != SYMBOL_REF)
1756 if (call_cookie & CALL_SHORT)
1759 if (TARGET_LONG_CALLS && flag_function_sections)
1762 if (current_file_function_operand (sym_ref, VOIDmode))
1765 return (call_cookie & CALL_LONG)
1766 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
1767 || TARGET_LONG_CALLS;
1771 legitimate_pic_operand_p (x)
1774 if (CONSTANT_P (x) && flag_pic
1775 && (GET_CODE (x) == SYMBOL_REF
1776 || (GET_CODE (x) == CONST
1777 && GET_CODE (XEXP (x, 0)) == PLUS
1778 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1785 legitimize_pic_address (orig, mode, reg)
1787 enum machine_mode mode;
1790 if (GET_CODE (orig) == SYMBOL_REF)
1792 rtx pic_ref, address;
1798 if (reload_in_progress || reload_completed)
1801 reg = gen_reg_rtx (Pmode);
1806 #ifdef AOF_ASSEMBLER
1807 /* The AOF assembler can generate relocations for these directly, and
1808 understands that the PIC register has to be added into the offset. */
1809 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1812 address = gen_reg_rtx (Pmode);
1816 emit_insn (gen_pic_load_addr (address, orig));
1818 pic_ref = gen_rtx_MEM (Pmode,
1819 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1821 RTX_UNCHANGING_P (pic_ref) = 1;
1822 insn = emit_move_insn (reg, pic_ref);
1824 current_function_uses_pic_offset_table = 1;
1825 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1827 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1831 else if (GET_CODE (orig) == CONST)
1835 if (GET_CODE (XEXP (orig, 0)) == PLUS
1836 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1841 if (reload_in_progress || reload_completed)
1844 reg = gen_reg_rtx (Pmode);
1847 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1849 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1850 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1851 base == reg ? 0 : reg);
1856 if (GET_CODE (offset) == CONST_INT)
1858 /* The base register doesn't really matter, we only want to
1859 test the index for the appropriate mode. */
1860 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1862 if (! reload_in_progress && ! reload_completed)
1863 offset = force_reg (Pmode, offset);
1868 if (GET_CODE (offset) == CONST_INT)
1869 return plus_constant_for_output (base, INTVAL (offset));
1872 if (GET_MODE_SIZE (mode) > 4
1873 && (GET_MODE_CLASS (mode) == MODE_INT
1874 || TARGET_SOFT_FLOAT))
1876 emit_insn (gen_addsi3 (reg, base, offset));
1880 return gen_rtx_PLUS (Pmode, base, offset);
1882 else if (GET_CODE (orig) == LABEL_REF)
1884 current_function_uses_pic_offset_table = 1;
1888 rtx pic_ref, address = gen_reg_rtx (Pmode);
1890 emit_insn (gen_pic_load_addr (address, orig));
1891 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
1893 emit_move_insn (address, pic_ref);
1915 #ifndef AOF_ASSEMBLER
1916 rtx l1, pic_tmp, pic_tmp2, seq;
1917 rtx global_offset_table;
1919 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
1926 l1 = gen_label_rtx ();
1928 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1929 /* On the ARM the PC register contains 'dot + 8' at the time of the
1931 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1933 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1934 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1936 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1938 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1940 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1941 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1943 seq = gen_sequence ();
1945 emit_insn_after (seq, get_insns ());
1947 /* Need to emit this whether or not we obey regdecls,
1948 since setjmp/longjmp can cause life info to screw up. */
1949 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1950 #endif /* AOF_ASSEMBLER */
1953 #define REG_OR_SUBREG_REG(X) \
1954 (GET_CODE (X) == REG \
1955 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1957 #define REG_OR_SUBREG_RTX(X) \
1958 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1960 #define ARM_FRAME_RTX(X) \
1961 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1962 || (X) == arg_pointer_rtx)
1965 arm_rtx_costs (x, code)
1969 enum machine_mode mode = GET_MODE (x);
1970 enum rtx_code subcode;
1976 /* Memory costs quite a lot for the first word, but subsequent words
1977 load at the equivalent of a single insn each. */
1978 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1979 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1986 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1993 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1995 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1996 + ((GET_CODE (XEXP (x, 0)) == REG
1997 || (GET_CODE (XEXP (x, 0)) == SUBREG
1998 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2000 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2001 || (GET_CODE (XEXP (x, 0)) == SUBREG
2002 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2004 + ((GET_CODE (XEXP (x, 1)) == REG
2005 || (GET_CODE (XEXP (x, 1)) == SUBREG
2006 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2007 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2012 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2013 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2014 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2015 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2018 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2019 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2020 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2021 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2023 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2024 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2025 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2028 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2029 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2030 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2031 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2032 || subcode == ASHIFTRT || subcode == LSHIFTRT
2033 || subcode == ROTATE || subcode == ROTATERT
2035 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2036 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2037 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2038 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2039 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2040 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2041 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2046 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2047 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2048 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2049 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2050 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2054 case AND: case XOR: case IOR:
2057 /* Normally the frame registers will be spilt into reg+const during
2058 reload, so it is a bad idea to combine them with other instructions,
2059 since then they might not be moved outside of loops. As a compromise
2060 we allow integration with ops that have a constant as their second
2062 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2063 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2064 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2065 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2066 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2070 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2071 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2072 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2073 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2076 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2077 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2078 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2079 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2080 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2083 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2084 return (1 + extra_cost
2085 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2086 || subcode == LSHIFTRT || subcode == ASHIFTRT
2087 || subcode == ROTATE || subcode == ROTATERT
2089 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2090 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2091 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2092 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2093 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2094 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2100 /* There is no point basing this on the tuning, since it is always the
2101 fast variant if it exists at all. */
2102 if (arm_fast_multiply && mode == DImode
2103 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2104 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2105 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2108 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2112 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2114 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2115 & (unsigned HOST_WIDE_INT) 0xffffffffUL);
2116 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2119 /* Tune as appropriate. */
2120 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2122 for (j = 0; i && j < 32; j += booth_unit_size)
2124 i >>= booth_unit_size;
2131 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2132 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2133 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2136 if (arm_fast_multiply && mode == SImode
2137 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2138 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2139 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2140 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2141 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2142 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2147 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2148 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2152 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2154 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2157 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2165 return 4 + (mode == DImode ? 4 : 0);
2168 if (GET_MODE (XEXP (x, 0)) == QImode)
2169 return (4 + (mode == DImode ? 4 : 0)
2170 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2173 switch (GET_MODE (XEXP (x, 0)))
2176 return (1 + (mode == DImode ? 4 : 0)
2177 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2180 return (4 + (mode == DImode ? 4 : 0)
2181 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2184 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2197 arm_adjust_cost (insn, link, dep, cost)
2205 /* XXX This is not strictly true for the FPA. */
2206 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
2207 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
2210 if ((i_pat = single_set (insn)) != NULL
2211 && GET_CODE (SET_SRC (i_pat)) == MEM
2212 && (d_pat = single_set (dep)) != NULL
2213 && GET_CODE (SET_DEST (d_pat)) == MEM)
2215 /* This is a load after a store, there is no conflict if the load reads
2216 from a cached area. Assume that loads from the stack, and from the
2217 constant pool are cached, and that others will miss. This is a
2220 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2221 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2222 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2223 || reg_mentioned_p (hard_frame_pointer_rtx,
2224 XEXP (SET_SRC (i_pat), 0)))
2231 /* This code has been fixed for cross compilation. */
2233 static int fpa_consts_inited = 0;
2235 char * strings_fpa[8] =
2238 "4", "5", "0.5", "10"
2241 static REAL_VALUE_TYPE values_fpa[8];
2249 for (i = 0; i < 8; i++)
2251 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2255 fpa_consts_inited = 1;
2258 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2261 const_double_rtx_ok_for_fpu (x)
2267 if (!fpa_consts_inited)
2270 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2271 if (REAL_VALUE_MINUS_ZERO (r))
2274 for (i = 0; i < 8; i++)
2275 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2281 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2284 neg_const_double_rtx_ok_for_fpu (x)
2290 if (!fpa_consts_inited)
2293 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2294 r = REAL_VALUE_NEGATE (r);
2295 if (REAL_VALUE_MINUS_ZERO (r))
2298 for (i = 0; i < 8; i++)
2299 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2305 /* Predicates for `match_operand' and `match_operator'. */
2307 /* s_register_operand is the same as register_operand, but it doesn't accept
2310 This function exists because at the time it was put in it led to better
2311 code. SUBREG(MEM) always needs a reload in the places where
2312 s_register_operand is used, and this seemed to lead to excessive
2316 s_register_operand (op, mode)
2318 enum machine_mode mode;
2320 if (GET_MODE (op) != mode && mode != VOIDmode)
2323 if (GET_CODE (op) == SUBREG)
2324 op = SUBREG_REG (op);
2326 /* We don't consider registers whose class is NO_REGS
2327 to be a register operand. */
2328 return (GET_CODE (op) == REG
2329 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2330 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2333 /* Only accept reg, subreg(reg), const_int. */
2336 reg_or_int_operand (op, mode)
2338 enum machine_mode mode;
2340 if (GET_CODE (op) == CONST_INT)
2343 if (GET_MODE (op) != mode && mode != VOIDmode)
2346 if (GET_CODE (op) == SUBREG)
2347 op = SUBREG_REG (op);
2349 /* We don't consider registers whose class is NO_REGS
2350 to be a register operand. */
2351 return (GET_CODE (op) == REG
2352 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2353 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2356 /* Return 1 if OP is an item in memory, given that we are in reload. */
2359 reload_memory_operand (op, mode)
2361 enum machine_mode mode ATTRIBUTE_UNUSED;
2363 int regno = true_regnum (op);
2365 return (! CONSTANT_P (op)
2367 || (GET_CODE (op) == REG
2368 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2371 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2372 memory access (architecture V4) */
2374 bad_signed_byte_operand (op, mode)
2376 enum machine_mode mode;
2378 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2383 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2384 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2385 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2386 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2387 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2390 /* Big constants are also bad. */
2391 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2392 && (INTVAL (XEXP (op, 1)) > 0xff
2393 || -INTVAL (XEXP (op, 1)) > 0xff))
2396 /* Everything else is good, or can will automatically be made so. */
2400 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2403 arm_rhs_operand (op, mode)
2405 enum machine_mode mode;
2407 return (s_register_operand (op, mode)
2408 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2411 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2415 arm_rhsm_operand (op, mode)
2417 enum machine_mode mode;
2419 return (s_register_operand (op, mode)
2420 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2421 || memory_operand (op, mode));
2424 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2425 constant that is valid when negated. */
2428 arm_add_operand (op, mode)
2430 enum machine_mode mode;
2432 return (s_register_operand (op, mode)
2433 || (GET_CODE (op) == CONST_INT
2434 && (const_ok_for_arm (INTVAL (op))
2435 || const_ok_for_arm (-INTVAL (op)))));
2439 arm_not_operand (op, mode)
2441 enum machine_mode mode;
2443 return (s_register_operand (op, mode)
2444 || (GET_CODE (op) == CONST_INT
2445 && (const_ok_for_arm (INTVAL (op))
2446 || const_ok_for_arm (~INTVAL (op)))));
2449 /* Return TRUE if the operand is a memory reference which contains an
2450 offsettable address. */
2452 offsettable_memory_operand (op, mode)
2454 enum machine_mode mode;
2456 if (mode == VOIDmode)
2457 mode = GET_MODE (op);
2459 return (mode == GET_MODE (op)
2460 && GET_CODE (op) == MEM
2461 && offsettable_address_p (reload_completed | reload_in_progress,
2462 mode, XEXP (op, 0)));
2465 /* Return TRUE if the operand is a memory reference which is, or can be
2466 made word aligned by adjusting the offset. */
2468 alignable_memory_operand (op, mode)
2470 enum machine_mode mode;
2474 if (mode == VOIDmode)
2475 mode = GET_MODE (op);
2477 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2482 return ((GET_CODE (reg = op) == REG
2483 || (GET_CODE (op) == SUBREG
2484 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2485 || (GET_CODE (op) == PLUS
2486 && GET_CODE (XEXP (op, 1)) == CONST_INT
2487 && (GET_CODE (reg = XEXP (op, 0)) == REG
2488 || (GET_CODE (XEXP (op, 0)) == SUBREG
2489 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2490 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
2493 /* Similar to s_register_operand, but does not allow hard integer
2496 f_register_operand (op, mode)
2498 enum machine_mode mode;
2500 if (GET_MODE (op) != mode && mode != VOIDmode)
2503 if (GET_CODE (op) == SUBREG)
2504 op = SUBREG_REG (op);
2506 /* We don't consider registers whose class is NO_REGS
2507 to be a register operand. */
2508 return (GET_CODE (op) == REG
2509 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2510 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2513 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2516 fpu_rhs_operand (op, mode)
2518 enum machine_mode mode;
2520 if (s_register_operand (op, mode))
2523 if (GET_MODE (op) != mode && mode != VOIDmode)
2526 if (GET_CODE (op) == CONST_DOUBLE)
2527 return const_double_rtx_ok_for_fpu (op);
2533 fpu_add_operand (op, mode)
2535 enum machine_mode mode;
2537 if (s_register_operand (op, mode))
2540 if (GET_MODE (op) != mode && mode != VOIDmode)
2543 if (GET_CODE (op) == CONST_DOUBLE)
2544 return (const_double_rtx_ok_for_fpu (op)
2545 || neg_const_double_rtx_ok_for_fpu (op));
2550 /* Return nonzero if OP is a constant power of two. */
2553 power_of_two_operand (op, mode)
2555 enum machine_mode mode ATTRIBUTE_UNUSED;
2557 if (GET_CODE (op) == CONST_INT)
2559 HOST_WIDE_INT value = INTVAL(op);
2560 return value != 0 && (value & (value - 1)) == 0;
2565 /* Return TRUE for a valid operand of a DImode operation.
2566 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2567 Note that this disallows MEM(REG+REG), but allows
2568 MEM(PRE/POST_INC/DEC(REG)). */
2571 di_operand (op, mode)
2573 enum machine_mode mode;
2575 if (s_register_operand (op, mode))
2578 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2581 if (GET_CODE (op) == SUBREG)
2582 op = SUBREG_REG (op);
2584 switch (GET_CODE (op))
2591 return memory_address_p (DImode, XEXP (op, 0));
2598 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2599 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2600 Note that this disallows MEM(REG+REG), but allows
2601 MEM(PRE/POST_INC/DEC(REG)). */
2604 soft_df_operand (op, mode)
2606 enum machine_mode mode;
2608 if (s_register_operand (op, mode))
2611 if (mode != VOIDmode && GET_MODE (op) != mode)
2614 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
2617 if (GET_CODE (op) == SUBREG)
2618 op = SUBREG_REG (op);
2620 switch (GET_CODE (op))
2626 return memory_address_p (DFmode, XEXP (op, 0));
2633 /* Return TRUE for valid index operands. */
2636 index_operand (op, mode)
2638 enum machine_mode mode;
2640 return (s_register_operand(op, mode)
2641 || (immediate_operand (op, mode)
2642 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2645 /* Return TRUE for valid shifts by a constant. This also accepts any
2646 power of two on the (somewhat overly relaxed) assumption that the
2647 shift operator in this case was a mult. */
2650 const_shift_operand (op, mode)
2652 enum machine_mode mode;
2654 return (power_of_two_operand (op, mode)
2655 || (immediate_operand (op, mode)
2656 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2659 /* Return TRUE for arithmetic operators which can be combined with a multiply
2663 shiftable_operator (x, mode)
2665 enum machine_mode mode;
2667 if (GET_MODE (x) != mode)
2671 enum rtx_code code = GET_CODE (x);
2673 return (code == PLUS || code == MINUS
2674 || code == IOR || code == XOR || code == AND);
2678 /* Return TRUE for binary logical operators. */
2681 logical_binary_operator (x, mode)
2683 enum machine_mode mode;
2685 if (GET_MODE (x) != mode)
2689 enum rtx_code code = GET_CODE (x);
2691 return (code == IOR || code == XOR || code == AND);
2695 /* Return TRUE for shift operators. */
2698 shift_operator (x, mode)
2700 enum machine_mode mode;
2702 if (GET_MODE (x) != mode)
2706 enum rtx_code code = GET_CODE (x);
2709 return power_of_two_operand (XEXP (x, 1), mode);
2711 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2712 || code == ROTATERT);
2716 /* Return TRUE if x is EQ or NE. */
2718 equality_operator (x, mode)
2720 enum machine_mode mode ATTRIBUTE_UNUSED;
2722 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2725 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2727 minmax_operator (x, mode)
2729 enum machine_mode mode;
2731 enum rtx_code code = GET_CODE (x);
2733 if (GET_MODE (x) != mode)
2736 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2739 /* Return TRUE if this is the condition code register, if we aren't given
2740 a mode, accept any class CCmode register. */
2742 cc_register (x, mode)
2744 enum machine_mode mode;
2746 if (mode == VOIDmode)
2748 mode = GET_MODE (x);
2749 if (GET_MODE_CLASS (mode) != MODE_CC)
2753 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2759 /* Return TRUE if this is the condition code register, if we aren't given
2760 a mode, accept any class CCmode register which indicates a dominance
2763 dominant_cc_register (x, mode)
2765 enum machine_mode mode;
2767 if (mode == VOIDmode)
2769 mode = GET_MODE (x);
2770 if (GET_MODE_CLASS (mode) != MODE_CC)
2774 if (mode != CC_DNEmode && mode != CC_DEQmode
2775 && mode != CC_DLEmode && mode != CC_DLTmode
2776 && mode != CC_DGEmode && mode != CC_DGTmode
2777 && mode != CC_DLEUmode && mode != CC_DLTUmode
2778 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2781 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2787 /* Return TRUE if X references a SYMBOL_REF. */
2789 symbol_mentioned_p (x)
2792 register const char * fmt;
2795 if (GET_CODE (x) == SYMBOL_REF)
2798 fmt = GET_RTX_FORMAT (GET_CODE (x));
2799 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2805 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2806 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2809 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2816 /* Return TRUE if X references a LABEL_REF. */
2818 label_mentioned_p (x)
2821 register const char * fmt;
2824 if (GET_CODE (x) == LABEL_REF)
2827 fmt = GET_RTX_FORMAT (GET_CODE (x));
2828 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2834 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2835 if (label_mentioned_p (XVECEXP (x, i, j)))
2838 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2849 enum rtx_code code = GET_CODE (x);
2853 else if (code == SMIN)
2855 else if (code == UMIN)
2857 else if (code == UMAX)
2863 /* Return 1 if memory locations are adjacent. */
2865 adjacent_mem_locations (a, b)
2868 int val0 = 0, val1 = 0;
2871 if ((GET_CODE (XEXP (a, 0)) == REG
2872 || (GET_CODE (XEXP (a, 0)) == PLUS
2873 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2874 && (GET_CODE (XEXP (b, 0)) == REG
2875 || (GET_CODE (XEXP (b, 0)) == PLUS
2876 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2878 if (GET_CODE (XEXP (a, 0)) == PLUS)
2880 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2881 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2884 reg0 = REGNO (XEXP (a, 0));
2885 if (GET_CODE (XEXP (b, 0)) == PLUS)
2887 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2888 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2891 reg1 = REGNO (XEXP (b, 0));
2892 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2897 /* Return 1 if OP is a load multiple operation. It is known to be
2898 parallel and the first section will be tested. */
2901 load_multiple_operation (op, mode)
2903 enum machine_mode mode ATTRIBUTE_UNUSED;
2905 HOST_WIDE_INT count = XVECLEN (op, 0);
2908 HOST_WIDE_INT i = 1, base = 0;
2912 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2915 /* Check to see if this might be a write-back. */
2916 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2921 /* Now check it more carefully. */
2922 if (GET_CODE (SET_DEST (elt)) != REG
2923 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2924 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2925 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2926 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2927 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2928 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2929 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2930 != REGNO (SET_DEST (elt)))
2936 /* Perform a quick check so we don't blow up below. */
2938 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2939 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2940 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2943 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2944 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2946 for (; i < count; i++)
2948 elt = XVECEXP (op, 0, i);
2950 if (GET_CODE (elt) != SET
2951 || GET_CODE (SET_DEST (elt)) != REG
2952 || GET_MODE (SET_DEST (elt)) != SImode
2953 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
2954 || GET_CODE (SET_SRC (elt)) != MEM
2955 || GET_MODE (SET_SRC (elt)) != SImode
2956 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2957 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2958 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2959 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2966 /* Return 1 if OP is a store multiple operation. It is known to be
2967 parallel and the first section will be tested. */
2969 store_multiple_operation (op, mode)
2971 enum machine_mode mode ATTRIBUTE_UNUSED;
2973 HOST_WIDE_INT count = XVECLEN (op, 0);
2976 HOST_WIDE_INT i = 1, base = 0;
2980 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2983 /* Check to see if this might be a write-back. */
2984 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2989 /* Now check it more carefully. */
2990 if (GET_CODE (SET_DEST (elt)) != REG
2991 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2992 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2993 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2994 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2995 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2996 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2997 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2998 != REGNO (SET_DEST (elt)))
3004 /* Perform a quick check so we don't blow up below. */
3006 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3007 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3008 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3011 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3012 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3014 for (; i < count; i++)
3016 elt = XVECEXP (op, 0, i);
3018 if (GET_CODE (elt) != SET
3019 || GET_CODE (SET_SRC (elt)) != REG
3020 || GET_MODE (SET_SRC (elt)) != SImode
3021 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3022 || GET_CODE (SET_DEST (elt)) != MEM
3023 || GET_MODE (SET_DEST (elt)) != SImode
3024 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3025 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3026 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3027 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3035 load_multiple_sequence (operands, nops, regs, base, load_offset)
3040 HOST_WIDE_INT * load_offset;
3042 int unsorted_regs[4];
3043 HOST_WIDE_INT unsorted_offsets[4];
3048 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3049 extended if required. */
3050 if (nops < 2 || nops > 4)
3053 /* Loop over the operands and check that the memory references are
3054 suitable (ie immediate offsets from the same base register). At
3055 the same time, extract the target register, and the memory
3057 for (i = 0; i < nops; i++)
3062 /* Convert a subreg of a mem into the mem itself. */
3063 if (GET_CODE (operands[nops + i]) == SUBREG)
3064 operands[nops + i] = alter_subreg(operands[nops + i]);
3066 if (GET_CODE (operands[nops + i]) != MEM)
3069 /* Don't reorder volatile memory references; it doesn't seem worth
3070 looking for the case where the order is ok anyway. */
3071 if (MEM_VOLATILE_P (operands[nops + i]))
3074 offset = const0_rtx;
3076 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3077 || (GET_CODE (reg) == SUBREG
3078 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3079 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3080 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3082 || (GET_CODE (reg) == SUBREG
3083 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3084 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3089 base_reg = REGNO(reg);
3090 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3091 ? REGNO (operands[i])
3092 : REGNO (SUBREG_REG (operands[i])));
3097 if (base_reg != (int) REGNO (reg))
3098 /* Not addressed from the same base register. */
3101 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3102 ? REGNO (operands[i])
3103 : REGNO (SUBREG_REG (operands[i])));
3104 if (unsorted_regs[i] < unsorted_regs[order[0]])
3108 /* If it isn't an integer register, or if it overwrites the
3109 base register but isn't the last insn in the list, then
3110 we can't do this. */
3111 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3112 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3115 unsorted_offsets[i] = INTVAL (offset);
3118 /* Not a suitable memory address. */
3122 /* All the useful information has now been extracted from the
3123 operands into unsorted_regs and unsorted_offsets; additionally,
3124 order[0] has been set to the lowest numbered register in the
3125 list. Sort the registers into order, and check that the memory
3126 offsets are ascending and adjacent. */
3128 for (i = 1; i < nops; i++)
3132 order[i] = order[i - 1];
3133 for (j = 0; j < nops; j++)
3134 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3135 && (order[i] == order[i - 1]
3136 || unsorted_regs[j] < unsorted_regs[order[i]]))
3139 /* Have we found a suitable register? if not, one must be used more
3141 if (order[i] == order[i - 1])
3144 /* Is the memory address adjacent and ascending? */
3145 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3153 for (i = 0; i < nops; i++)
3154 regs[i] = unsorted_regs[order[i]];
3156 *load_offset = unsorted_offsets[order[0]];
3159 if (unsorted_offsets[order[0]] == 0)
3160 return 1; /* ldmia */
3162 if (unsorted_offsets[order[0]] == 4)
3163 return 2; /* ldmib */
3165 if (unsorted_offsets[order[nops - 1]] == 0)
3166 return 3; /* ldmda */
3168 if (unsorted_offsets[order[nops - 1]] == -4)
3169 return 4; /* ldmdb */
3171 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3172 if the offset isn't small enough. The reason 2 ldrs are faster
3173 is because these ARMs are able to do more than one cache access
3174 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3175 whilst the ARM8 has a double bandwidth cache. This means that
3176 these cores can do both an instruction fetch and a data fetch in
3177 a single cycle, so the trick of calculating the address into a
3178 scratch register (one of the result regs) and then doing a load
3179 multiple actually becomes slower (and no smaller in code size).
3180 That is the transformation
3182 ldr rd1, [rbase + offset]
3183 ldr rd2, [rbase + offset + 4]
3187 add rd1, rbase, offset
3188 ldmia rd1, {rd1, rd2}
3190 produces worse code -- '3 cycles + any stalls on rd2' instead of
3191 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3192 access per cycle, the first sequence could never complete in less
3193 than 6 cycles, whereas the ldm sequence would only take 5 and
3194 would make better use of sequential accesses if not hitting the
3197 We cheat here and test 'arm_ld_sched' which we currently know to
3198 only be true for the ARM8, ARM9 and StrongARM. If this ever
3199 changes, then the test below needs to be reworked. */
3200 if (nops == 2 && arm_ld_sched)
3203 /* Can't do it without setting up the offset, only do this if it takes
3204 no more than one insn. */
3205 return (const_ok_for_arm (unsorted_offsets[order[0]])
3206 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3210 emit_ldm_seq (operands, nops)
3216 HOST_WIDE_INT offset;
3220 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3223 strcpy (buf, "ldm%?ia\t");
3227 strcpy (buf, "ldm%?ib\t");
3231 strcpy (buf, "ldm%?da\t");
3235 strcpy (buf, "ldm%?db\t");
3240 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3241 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3244 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3245 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3247 output_asm_insn (buf, operands);
3249 strcpy (buf, "ldm%?ia\t");
3256 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3257 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3259 for (i = 1; i < nops; i++)
3260 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3261 reg_names[regs[i]]);
3263 strcat (buf, "}\t%@ phole ldm");
3265 output_asm_insn (buf, operands);
3270 store_multiple_sequence (operands, nops, regs, base, load_offset)
3275 HOST_WIDE_INT * load_offset;
3277 int unsorted_regs[4];
3278 HOST_WIDE_INT unsorted_offsets[4];
3283 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3284 extended if required. */
3285 if (nops < 2 || nops > 4)
3288 /* Loop over the operands and check that the memory references are
3289 suitable (ie immediate offsets from the same base register). At
3290 the same time, extract the target register, and the memory
3292 for (i = 0; i < nops; i++)
3297 /* Convert a subreg of a mem into the mem itself. */
3298 if (GET_CODE (operands[nops + i]) == SUBREG)
3299 operands[nops + i] = alter_subreg(operands[nops + i]);
3301 if (GET_CODE (operands[nops + i]) != MEM)
3304 /* Don't reorder volatile memory references; it doesn't seem worth
3305 looking for the case where the order is ok anyway. */
3306 if (MEM_VOLATILE_P (operands[nops + i]))
3309 offset = const0_rtx;
3311 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3312 || (GET_CODE (reg) == SUBREG
3313 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3314 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3315 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3317 || (GET_CODE (reg) == SUBREG
3318 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3319 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3324 base_reg = REGNO (reg);
3325 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3326 ? REGNO (operands[i])
3327 : REGNO (SUBREG_REG (operands[i])));
3332 if (base_reg != (int) REGNO (reg))
3333 /* Not addressed from the same base register. */
3336 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3337 ? REGNO (operands[i])
3338 : REGNO (SUBREG_REG (operands[i])));
3339 if (unsorted_regs[i] < unsorted_regs[order[0]])
3343 /* If it isn't an integer register, then we can't do this. */
3344 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3347 unsorted_offsets[i] = INTVAL (offset);
3350 /* Not a suitable memory address. */
3354 /* All the useful information has now been extracted from the
3355 operands into unsorted_regs and unsorted_offsets; additionally,
3356 order[0] has been set to the lowest numbered register in the
3357 list. Sort the registers into order, and check that the memory
3358 offsets are ascending and adjacent. */
3360 for (i = 1; i < nops; i++)
3364 order[i] = order[i - 1];
3365 for (j = 0; j < nops; j++)
3366 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3367 && (order[i] == order[i - 1]
3368 || unsorted_regs[j] < unsorted_regs[order[i]]))
3371 /* Have we found a suitable register? if not, one must be used more
3373 if (order[i] == order[i - 1])
3376 /* Is the memory address adjacent and ascending? */
3377 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3385 for (i = 0; i < nops; i++)
3386 regs[i] = unsorted_regs[order[i]];
3388 *load_offset = unsorted_offsets[order[0]];
3391 if (unsorted_offsets[order[0]] == 0)
3392 return 1; /* stmia */
3394 if (unsorted_offsets[order[0]] == 4)
3395 return 2; /* stmib */
3397 if (unsorted_offsets[order[nops - 1]] == 0)
3398 return 3; /* stmda */
3400 if (unsorted_offsets[order[nops - 1]] == -4)
3401 return 4; /* stmdb */
3407 emit_stm_seq (operands, nops)
3413 HOST_WIDE_INT offset;
3417 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3420 strcpy (buf, "stm%?ia\t");
3424 strcpy (buf, "stm%?ib\t");
3428 strcpy (buf, "stm%?da\t");
3432 strcpy (buf, "stm%?db\t");
3439 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3440 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3442 for (i = 1; i < nops; i++)
3443 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3444 reg_names[regs[i]]);
3446 strcat (buf, "}\t%@ phole stm");
3448 output_asm_insn (buf, operands);
3453 multi_register_push (op, mode)
3455 enum machine_mode mode ATTRIBUTE_UNUSED;
3457 if (GET_CODE (op) != PARALLEL
3458 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3459 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3460 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3467 /* Routines for use with attributes. */
3469 /* Return nonzero if ATTR is a valid attribute for DECL.
3470 ATTRIBUTES are any existing attributes and ARGS are
3471 the arguments supplied with ATTR.
3473 Supported attributes:
3475 naked: don't output any prologue or epilogue code,
3476 the user is assumed to do the right thing.
3479 arm_valid_machine_decl_attribute (decl, attr, args)
3484 if (args != NULL_TREE)
3487 if (is_attribute_p ("naked", attr))
3488 return TREE_CODE (decl) == FUNCTION_DECL;
3492 /* Return non-zero if FUNC is a naked function. */
3495 arm_naked_function_p (func)
3500 if (TREE_CODE (func) != FUNCTION_DECL)
3503 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3504 return a != NULL_TREE;
3507 /* Routines for use in generating RTL. */
3509 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3510 in_struct_p, scalar_p)
3522 int sign = up ? 1 : -1;
3525 result = gen_rtx_PARALLEL (VOIDmode,
3526 rtvec_alloc (count + (write_back ? 2 : 0)));
3529 XVECEXP (result, 0, 0)
3530 = gen_rtx_SET (GET_MODE (from), from,
3531 plus_constant (from, count * 4 * sign));
3536 for (j = 0; i < count; i++, j++)
3538 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3539 RTX_UNCHANGING_P (mem) = unchanging_p;
3540 MEM_IN_STRUCT_P (mem) = in_struct_p;
3541 MEM_SCALAR_P (mem) = scalar_p;
3542 XVECEXP (result, 0, i)
3543 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3547 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3553 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3554 in_struct_p, scalar_p)
3566 int sign = up ? 1 : -1;
3569 result = gen_rtx_PARALLEL (VOIDmode,
3570 rtvec_alloc (count + (write_back ? 2 : 0)));
3573 XVECEXP (result, 0, 0)
3574 = gen_rtx_SET (GET_MODE (to), to,
3575 plus_constant (to, count * 4 * sign));
3580 for (j = 0; i < count; i++, j++)
3582 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3583 RTX_UNCHANGING_P (mem) = unchanging_p;
3584 MEM_IN_STRUCT_P (mem) = in_struct_p;
3585 MEM_SCALAR_P (mem) = scalar_p;
3587 XVECEXP (result, 0, i)
3588 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3592 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3598 arm_gen_movstrqi (operands)
3601 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3604 rtx st_src, st_dst, fin_src, fin_dst;
3605 rtx part_bytes_reg = NULL;
3607 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3608 int dst_scalar_p, src_scalar_p;
3610 if (GET_CODE (operands[2]) != CONST_INT
3611 || GET_CODE (operands[3]) != CONST_INT
3612 || INTVAL (operands[2]) > 64
3613 || INTVAL (operands[3]) & 3)
3616 st_dst = XEXP (operands[0], 0);
3617 st_src = XEXP (operands[1], 0);
3619 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3620 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3621 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3622 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3623 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3624 src_scalar_p = MEM_SCALAR_P (operands[1]);
3626 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3627 fin_src = src = copy_to_mode_reg (SImode, st_src);
3629 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3630 out_words_to_go = INTVAL (operands[2]) / 4;
3631 last_bytes = INTVAL (operands[2]) & 3;
3633 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3634 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3636 for (i = 0; in_words_to_go >= 2; i+=4)
3638 if (in_words_to_go > 4)
3639 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3644 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3645 FALSE, src_unchanging_p,
3646 src_in_struct_p, src_scalar_p));
3648 if (out_words_to_go)
3650 if (out_words_to_go > 4)
3651 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3655 else if (out_words_to_go != 1)
3656 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3665 mem = gen_rtx_MEM (SImode, dst);
3666 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3667 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3668 MEM_SCALAR_P (mem) = dst_scalar_p;
3669 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3670 if (last_bytes != 0)
3671 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3675 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3676 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3679 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3680 if (out_words_to_go)
3684 mem = gen_rtx_MEM (SImode, src);
3685 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3686 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3687 MEM_SCALAR_P (mem) = src_scalar_p;
3688 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3689 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3691 mem = gen_rtx_MEM (SImode, dst);
3692 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3693 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3694 MEM_SCALAR_P (mem) = dst_scalar_p;
3695 emit_move_insn (mem, sreg);
3696 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3699 if (in_words_to_go) /* Sanity check */
3705 if (in_words_to_go < 0)
3708 mem = gen_rtx_MEM (SImode, src);
3709 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3710 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3711 MEM_SCALAR_P (mem) = src_scalar_p;
3712 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3715 if (BYTES_BIG_ENDIAN && last_bytes)
3717 rtx tmp = gen_reg_rtx (SImode);
3719 if (part_bytes_reg == NULL)
3722 /* The bytes we want are in the top end of the word. */
3723 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3724 GEN_INT (8 * (4 - last_bytes))));
3725 part_bytes_reg = tmp;
3729 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3730 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3731 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3732 MEM_SCALAR_P (mem) = dst_scalar_p;
3733 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3737 tmp = gen_reg_rtx (SImode);
3738 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3739 part_bytes_reg = tmp;
3748 if (part_bytes_reg == NULL)
3751 mem = gen_rtx_MEM (QImode, dst);
3752 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3753 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3754 MEM_SCALAR_P (mem) = dst_scalar_p;
3755 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3759 rtx tmp = gen_reg_rtx (SImode);
3761 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3762 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3763 part_bytes_reg = tmp;
3771 /* Generate a memory reference for a half word, such that it will be loaded
3772 into the top 16 bits of the word. We can assume that the address is
3773 known to be alignable and of the form reg, or plus (reg, const). */
3775 gen_rotated_half_load (memref)
3778 HOST_WIDE_INT offset = 0;
3779 rtx base = XEXP (memref, 0);
3781 if (GET_CODE (base) == PLUS)
3783 offset = INTVAL (XEXP (base, 1));
3784 base = XEXP (base, 0);
3787 /* If we aren't allowed to generate unaligned addresses, then fail. */
3788 if (TARGET_MMU_TRAPS
3789 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3792 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3794 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3797 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3800 static enum machine_mode
3801 select_dominance_cc_mode (x, y, cond_or)
3804 HOST_WIDE_INT cond_or;
3806 enum rtx_code cond1, cond2;
3809 /* Currently we will probably get the wrong result if the individual
3810 comparisons are not simple. This also ensures that it is safe to
3811 reverse a comparison if necessary. */
3812 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3814 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3819 cond1 = reverse_condition (cond1);
3821 /* If the comparisons are not equal, and one doesn't dominate the other,
3822 then we can't do this. */
3824 && ! comparison_dominates_p (cond1, cond2)
3825 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3830 enum rtx_code temp = cond1;
3838 if (cond2 == EQ || ! cond_or)
3843 case LE: return CC_DLEmode;
3844 case LEU: return CC_DLEUmode;
3845 case GE: return CC_DGEmode;
3846 case GEU: return CC_DGEUmode;
3853 if (cond2 == LT || ! cond_or)
3862 if (cond2 == GT || ! cond_or)
3871 if (cond2 == LTU || ! cond_or)
3880 if (cond2 == GTU || ! cond_or)
3888 /* The remaining cases only occur when both comparisons are the
3913 arm_select_cc_mode (op, x, y)
3918 /* All floating point compares return CCFP if it is an equality
3919 comparison, and CCFPE otherwise. */
3920 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3921 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3923 /* A compare with a shifted operand. Because of canonicalization, the
3924 comparison will have to be swapped when we emit the assembler. */
3925 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3926 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3927 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3928 || GET_CODE (x) == ROTATERT))
3931 /* This is a special case that is used by combine to allow a
3932 comparison of a shifted byte load to be split into a zero-extend
3933 followed by a comparison of the shifted integer (only valid for
3934 equalities and unsigned inequalities). */
3935 if (GET_MODE (x) == SImode
3936 && GET_CODE (x) == ASHIFT
3937 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3938 && GET_CODE (XEXP (x, 0)) == SUBREG
3939 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3940 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3941 && (op == EQ || op == NE
3942 || op == GEU || op == GTU || op == LTU || op == LEU)
3943 && GET_CODE (y) == CONST_INT)
3946 /* An operation that sets the condition codes as a side-effect, the
3947 V flag is not set correctly, so we can only use comparisons where
3948 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3950 if (GET_MODE (x) == SImode
3952 && (op == EQ || op == NE || op == LT || op == GE)
3953 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3954 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3955 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3956 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3957 || GET_CODE (x) == LSHIFTRT
3958 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3959 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3962 /* A construct for a conditional compare, if the false arm contains
3963 0, then both conditions must be true, otherwise either condition
3964 must be true. Not all conditions are possible, so CCmode is
3965 returned if it can't be done. */
3966 if (GET_CODE (x) == IF_THEN_ELSE
3967 && (XEXP (x, 2) == const0_rtx
3968 || XEXP (x, 2) == const1_rtx)
3969 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3970 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3971 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3972 INTVAL (XEXP (x, 2)));
3974 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3977 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3978 && GET_CODE (x) == PLUS
3979 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3985 /* X and Y are two things to compare using CODE. Emit the compare insn and
3986 return the rtx for register 0 in the proper mode. FP means this is a
3987 floating point compare: I don't think that it is needed on the arm. */
3990 gen_compare_reg (code, x, y)
3994 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3995 rtx cc_reg = gen_rtx_REG (mode, 24);
3997 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
3998 gen_rtx_COMPARE (mode, x, y)));
4004 arm_reload_in_hi (operands)
4007 rtx ref = operands[1];
4009 HOST_WIDE_INT offset = 0;
4011 if (GET_CODE (ref) == SUBREG)
4013 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4014 if (BYTES_BIG_ENDIAN)
4015 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4016 - MIN (UNITS_PER_WORD,
4017 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4018 ref = SUBREG_REG (ref);
4021 if (GET_CODE (ref) == REG)
4023 /* We have a pseudo which has been spilt onto the stack; there
4024 are two cases here: the first where there is a simple
4025 stack-slot replacement and a second where the stack-slot is
4026 out of range, or is used as a subreg. */
4027 if (reg_equiv_mem[REGNO (ref)])
4029 ref = reg_equiv_mem[REGNO (ref)];
4030 base = find_replacement (&XEXP (ref, 0));
4033 /* The slot is out of range, or was dressed up in a SUBREG. */
4034 base = reg_equiv_address[REGNO (ref)];
4037 base = find_replacement (&XEXP (ref, 0));
4039 /* Handle the case where the address is too complex to be offset by 1. */
4040 if (GET_CODE (base) == MINUS
4041 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4043 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4045 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4048 else if (GET_CODE (base) == PLUS)
4050 /* The addend must be CONST_INT, or we would have dealt with it above. */
4051 HOST_WIDE_INT hi, lo;
4053 offset += INTVAL (XEXP (base, 1));
4054 base = XEXP (base, 0);
4056 /* Rework the address into a legal sequence of insns. */
4057 /* Valid range for lo is -4095 -> 4095 */
4060 : -((-offset) & 0xfff));
4062 /* Corner case, if lo is the max offset then we would be out of range
4063 once we have added the additional 1 below, so bump the msb into the
4064 pre-loading insn(s). */
4068 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4069 ^ (HOST_WIDE_INT) 0x80000000UL)
4070 - (HOST_WIDE_INT) 0x80000000UL);
4072 if (hi + lo != offset)
4077 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4079 /* Get the base address; addsi3 knows how to handle constants
4080 that require more than one insn. */
4081 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4087 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4088 emit_insn (gen_zero_extendqisi2 (scratch,
4089 gen_rtx_MEM (QImode,
4090 plus_constant (base,
4092 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4093 gen_rtx_MEM (QImode,
4094 plus_constant (base,
4096 if (! BYTES_BIG_ENDIAN)
4097 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4098 gen_rtx_IOR (SImode,
4101 gen_rtx_SUBREG (SImode, operands[0], 0),
4105 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4106 gen_rtx_IOR (SImode,
4107 gen_rtx_ASHIFT (SImode, scratch,
4109 gen_rtx_SUBREG (SImode, operands[0],
4113 /* Handle storing a half-word to memory during reload by synthesising as two
4114 byte stores. Take care not to clobber the input values until after we
4115 have moved them somewhere safe. This code assumes that if the DImode
4116 scratch in operands[2] overlaps either the input value or output address
4117 in some way, then that value must die in this insn (we absolutely need
4118 two scratch registers for some corner cases). */
4120 arm_reload_out_hi (operands)
4123 rtx ref = operands[0];
4124 rtx outval = operands[1];
4126 HOST_WIDE_INT offset = 0;
4128 if (GET_CODE (ref) == SUBREG)
4130 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4131 if (BYTES_BIG_ENDIAN)
4132 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4133 - MIN (UNITS_PER_WORD,
4134 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4135 ref = SUBREG_REG (ref);
4139 if (GET_CODE (ref) == REG)
4141 /* We have a pseudo which has been spilt onto the stack; there
4142 are two cases here: the first where there is a simple
4143 stack-slot replacement and a second where the stack-slot is
4144 out of range, or is used as a subreg. */
4145 if (reg_equiv_mem[REGNO (ref)])
4147 ref = reg_equiv_mem[REGNO (ref)];
4148 base = find_replacement (&XEXP (ref, 0));
4151 /* The slot is out of range, or was dressed up in a SUBREG. */
4152 base = reg_equiv_address[REGNO (ref)];
4155 base = find_replacement (&XEXP (ref, 0));
4157 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4159 /* Handle the case where the address is too complex to be offset by 1. */
4160 if (GET_CODE (base) == MINUS
4161 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4163 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4165 /* Be careful not to destroy OUTVAL. */
4166 if (reg_overlap_mentioned_p (base_plus, outval))
4168 /* Updating base_plus might destroy outval, see if we can
4169 swap the scratch and base_plus. */
4170 if (! reg_overlap_mentioned_p (scratch, outval))
4173 scratch = base_plus;
4178 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4180 /* Be conservative and copy OUTVAL into the scratch now,
4181 this should only be necessary if outval is a subreg
4182 of something larger than a word. */
4183 /* XXX Might this clobber base? I can't see how it can,
4184 since scratch is known to overlap with OUTVAL, and
4185 must be wider than a word. */
4186 emit_insn (gen_movhi (scratch_hi, outval));
4187 outval = scratch_hi;
4191 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4194 else if (GET_CODE (base) == PLUS)
4196 /* The addend must be CONST_INT, or we would have dealt with it above. */
4197 HOST_WIDE_INT hi, lo;
4199 offset += INTVAL (XEXP (base, 1));
4200 base = XEXP (base, 0);
4202 /* Rework the address into a legal sequence of insns. */
4203 /* Valid range for lo is -4095 -> 4095 */
4206 : -((-offset) & 0xfff));
4208 /* Corner case, if lo is the max offset then we would be out of range
4209 once we have added the additional 1 below, so bump the msb into the
4210 pre-loading insn(s). */
4214 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4215 ^ (HOST_WIDE_INT) 0x80000000UL)
4216 - (HOST_WIDE_INT) 0x80000000UL);
4218 if (hi + lo != offset)
4223 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4225 /* Be careful not to destroy OUTVAL. */
4226 if (reg_overlap_mentioned_p (base_plus, outval))
4228 /* Updating base_plus might destroy outval, see if we
4229 can swap the scratch and base_plus. */
4230 if (! reg_overlap_mentioned_p (scratch, outval))
4233 scratch = base_plus;
4238 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4240 /* Be conservative and copy outval into scratch now,
4241 this should only be necessary if outval is a
4242 subreg of something larger than a word. */
4243 /* XXX Might this clobber base? I can't see how it
4244 can, since scratch is known to overlap with
4246 emit_insn (gen_movhi (scratch_hi, outval));
4247 outval = scratch_hi;
4251 /* Get the base address; addsi3 knows how to handle constants
4252 that require more than one insn. */
4253 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4259 if (BYTES_BIG_ENDIAN)
4261 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4262 plus_constant (base, offset + 1)),
4263 gen_rtx_SUBREG (QImode, outval, 0)));
4264 emit_insn (gen_lshrsi3 (scratch,
4265 gen_rtx_SUBREG (SImode, outval, 0),
4267 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4268 gen_rtx_SUBREG (QImode, scratch, 0)));
4272 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4273 gen_rtx_SUBREG (QImode, outval, 0)));
4274 emit_insn (gen_lshrsi3 (scratch,
4275 gen_rtx_SUBREG (SImode, outval, 0),
4277 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4278 plus_constant (base, offset + 1)),
4279 gen_rtx_SUBREG (QImode, scratch, 0)));
4283 /* Routines for manipulation of the constant pool. */
4285 /* Arm instructions cannot load a large constant directly into a
4286 register; they have to come from a pc relative load. The constant
4287 must therefore be placed in the addressable range of the pc
4288 relative load. Depending on the precise pc relative load
4289 instruction the range is somewhere between 256 bytes and 4k. This
4290 means that we often have to dump a constant inside a function, and
4291 generate code to branch around it.
4293 It is important to minimize this, since the branches will slow
4294 things down and make the code larger.
4296 Normally we can hide the table after an existing unconditional
4297 branch so that there is no interruption of the flow, but in the
4298 worst case the code looks like this:
4316 We fix this by performing a scan after scheduling, which notices
4317 which instructions need to have their operands fetched from the
4318 constant table and builds the table.
4320 The algorithm starts by building a table of all the constants that
4321 need fixing up and all the natural barriers in the function (places
4322 where a constant table can be dropped without breaking the flow).
4323 For each fixup we note how far the pc-relative replacement will be
4324 able to reach and the offset of the instruction into the function.
4326 Having built the table we then group the fixes together to form
4327 tables that are as large as possible (subject to addressing
4328 constraints) and emit each table of constants after the last
4329 barrier that is within range of all the instructions in the group.
4330 If a group does not contain a barrier, then we forcibly create one
4331 by inserting a jump instruction into the flow. Once the table has
4332 been inserted, the insns are then modified to reference the
4333 relevant entry in the pool.
4335 Possible enhancements to the algorithm (not implemented) are:
4337 1) ARM instructions (but not Thumb) can use negative offsets, so we
4338 could reference back to a previous pool rather than forwards to a
4339 new one. For large functions this may reduce the number of pools
4342 2) For some processors and object formats, there may be benefit in
4343 aligning the pools to the start of cache lines; this alignment
4344 would need to be taken into account when calculating addressability
4349 rtx value; /* Value in table */
4350 HOST_WIDE_INT next_offset;
4351 enum machine_mode mode; /* Mode of value */
4354 /* The maximum number of constants that can fit into one pool, since
4355 the pc relative range is 0...4092 bytes and constants are at least 4
4357 #define MAX_MINIPOOL_SIZE (4092/4)
4358 static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
4359 static int minipool_size;
4360 static rtx minipool_vector_label;
4362 /* Add a constant to the pool and return its offset within the current
4365 X is the rtx we want to replace. MODE is its mode. On return,
4366 ADDRESS_ONLY will be non-zero if we really want the address of such
4367 a constant, not the constant itself. */
4368 static HOST_WIDE_INT
4369 add_minipool_constant (x, mode)
4371 enum machine_mode mode;
4374 HOST_WIDE_INT offset;
4376 /* First, see if we've already got it. */
4377 for (i = 0; i < minipool_size; i++)
4379 if (GET_CODE (x) == minipool_vector[i].value->code
4380 && mode == minipool_vector[i].mode)
4382 if (GET_CODE (x) == CODE_LABEL)
4384 if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
4387 if (rtx_equal_p (x, minipool_vector[i].value))
4388 return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
4392 /* Need a new one. */
4393 minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
4395 if (minipool_size == 0)
4396 minipool_vector_label = gen_label_rtx ();
4398 minipool_vector[minipool_size].next_offset
4399 += (offset = minipool_vector[minipool_size - 1].next_offset);
4401 minipool_vector[minipool_size].value = x;
4402 minipool_vector[minipool_size].mode = mode;
4407 /* Output the literal table. */
4409 dump_minipool (scan)
4414 scan = emit_label_after (gen_label_rtx (), scan);
4415 scan = emit_insn_after (gen_align_4 (), scan);
4416 scan = emit_label_after (minipool_vector_label, scan);
4418 for (i = 0; i < minipool_size; i++)
4420 minipool_node *p = minipool_vector + i;
4422 switch (GET_MODE_SIZE (p->mode))
4425 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4429 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4438 scan = emit_insn_after (gen_consttable_end (), scan);
4439 scan = emit_barrier_after (scan);
4443 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4446 find_barrier (from, max_count)
4451 rtx found_barrier = 0;
4454 while (from && count < max_count)
4458 if (GET_CODE (from) == BARRIER)
4459 found_barrier = from;
4461 /* Count the length of this insn. */
4462 if (GET_CODE (from) == JUMP_INSN
4463 && JUMP_LABEL (from) != 0
4464 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4465 == next_real_insn (from))
4467 && GET_CODE (tmp) == JUMP_INSN
4468 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4469 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4471 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4472 count += (get_attr_length (from)
4473 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4474 /* Continue after the dispatch table. */
4476 from = NEXT_INSN (tmp);
4480 count += get_attr_length (from);
4483 from = NEXT_INSN (from);
4486 if (! found_barrier)
4488 /* We didn't find a barrier in time to
4489 dump our stuff, so we'll make one. */
4490 rtx label = gen_label_rtx ();
4493 from = PREV_INSN (last);
4495 from = get_last_insn ();
4497 /* Walk back to be just before any jump. */
4498 while (GET_CODE (from) == JUMP_INSN
4499 || GET_CODE (from) == NOTE
4500 || GET_CODE (from) == CODE_LABEL)
4501 from = PREV_INSN (from);
4503 from = emit_jump_insn_after (gen_jump (label), from);
4504 JUMP_LABEL (from) = label;
4505 found_barrier = emit_barrier_after (from);
4506 emit_label_after (label, found_barrier);
4509 return found_barrier;
4512 struct minipool_fixup
4514 struct minipool_fixup *next;
4518 enum machine_mode mode;
4523 struct minipool_fixup *minipool_fix_head;
4524 struct minipool_fixup *minipool_fix_tail;
4527 push_minipool_barrier (insn, address)
4531 struct minipool_fixup *fix
4532 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4535 fix->address = address;
4538 if (minipool_fix_head != NULL)
4539 minipool_fix_tail->next = fix;
4541 minipool_fix_head = fix;
4543 minipool_fix_tail = fix;
4547 push_minipool_fix (insn, address, loc, mode, value)
4551 enum machine_mode mode;
4554 struct minipool_fixup *fix
4555 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4557 #ifdef AOF_ASSEMBLER
4558 /* PIC symbol refereneces need to be converted into offsets into the
4560 if (flag_pic && GET_MODE == SYMBOL_REF)
4561 value = aof_pic_entry (value);
4562 #endif /* AOF_ASSEMBLER */
4565 fix->address = address;
4569 fix->range = get_attr_pool_range (insn);
4571 /* If an insn doesn't have a range defined for it, then it isn't
4572 expecting to be reworked by this code. Better to abort now than
4573 to generate duff assembly code. */
4574 if (fix->range == 0)
4577 /* Add it to the chain of fixes. */
4579 if (minipool_fix_head != NULL)
4580 minipool_fix_tail->next = fix;
4582 minipool_fix_head = fix;
4584 minipool_fix_tail = fix;
4588 note_invalid_constants (insn, address)
4594 /* Extract the operands of the insn. */
4597 /* Find the alternative selected. */
4598 if (! constrain_operands (1))
4599 fatal_insn_not_found (insn);
4601 /* Preprocess the constraints, to extract some useful information. */
4602 preprocess_constraints ();
4604 for (opno = 0; opno < recog_data.n_operands; opno++)
4606 /* Things we need to fix can only occur in inputs. */
4607 if (recog_data.operand_type[opno] != OP_IN)
4610 /* If this alternative is a memory reference, then any mention
4611 of constants in this alternative is really to fool reload
4612 into allowing us to accept one there. We need to fix them up
4613 now so that we output the right code. */
4614 if (recog_op_alt[opno][which_alternative].memory_ok)
4616 rtx op = recog_data.operand[opno];
4618 if (CONSTANT_P (op))
4619 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4620 recog_data.operand_mode[opno], op);
4621 #ifndef AOF_ASSEMBLER
4622 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
4623 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4624 recog_data.operand_mode[opno],
4625 XVECEXP (op, 0, 0));
4627 else if (recog_data.operand_mode[opno] == SImode
4628 && GET_CODE (op) == MEM
4629 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
4630 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4631 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4632 recog_data.operand_mode[opno],
4633 get_pool_constant (XEXP (op, 0)));
4644 struct minipool_fixup *fix;
4646 minipool_fix_head = minipool_fix_tail = NULL;
4648 /* The first insn must always be a note, or the code below won't
4649 scan it properly. */
4650 if (GET_CODE (first) != NOTE)
4653 /* Scan all the insns and record the operands that will need fixing. */
4654 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
4657 if (GET_CODE (insn) == BARRIER)
4658 push_minipool_barrier(insn, address);
4659 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
4660 || GET_CODE (insn) == JUMP_INSN)
4664 note_invalid_constants (insn, address);
4665 address += get_attr_length (insn);
4666 /* If the insn is a vector jump, add the size of the table
4667 and skip the table. */
4668 if (GET_CODE (insn) == JUMP_INSN
4669 && JUMP_LABEL (insn) != NULL
4670 && ((table = next_real_insn (JUMP_LABEL (insn)))
4671 == next_real_insn (insn))
4673 && GET_CODE (table) == JUMP_INSN
4674 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4675 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4677 int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
4679 address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
4686 /* Now scan the fixups and perform the required changes. */
4687 for (fix = minipool_fix_head; fix; fix = fix->next)
4689 struct minipool_fixup *ftmp;
4690 struct minipool_fixup *last_barrier = NULL;
4693 struct minipool_fixup *this_fix;
4694 int new_minipool_size = 0;
4696 /* Skip any further barriers before the next fix. */
4697 while (fix && GET_CODE (fix->insn) == BARRIER)
4704 max_range = fix->address + fix->range;
4706 /* Find all the other fixes that can live in the same pool. */
4707 while (ftmp->next && ftmp->next->address < max_range
4708 && (GET_CODE (ftmp->next->insn) == BARRIER
4709 /* Ensure we can reach the constant inside the pool. */
4710 || ftmp->next->range > new_minipool_size))
4713 if (GET_CODE (ftmp->insn) == BARRIER)
4714 last_barrier = ftmp;
4717 /* Does this fix constrain the range we can search? */
4718 if (ftmp->address + ftmp->range - new_minipool_size < max_range)
4719 max_range = ftmp->address + ftmp->range - new_minipool_size;
4721 new_minipool_size += GET_MODE_SIZE (ftmp->mode);
4725 /* If we found a barrier, drop back to that; any fixes that we could
4726 have reached but come after the barrier will now go in the next
4728 if (last_barrier != NULL)
4730 barrier = last_barrier->insn;
4731 ftmp = last_barrier;
4733 /* ftmp is last fix that we can fit into this pool and we
4734 failed to find a barrier that we could use. Insert a new
4735 barrier in the code and arrange to jump around it. */
4738 /* Check that there isn't another fix that is in range that
4739 we couldn't fit into this pool because the pool was
4740 already too large: we need to put the pool before such an
4742 if (ftmp->next && ftmp->next->address < max_range)
4743 max_range = ftmp->address;
4745 barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
4748 /* Scan over the fixes we have identified for this pool, fixing them
4749 up and adding the constants to the pool itself. */
4750 for (this_fix = fix; this_fix && ftmp->next != this_fix;
4751 this_fix = this_fix->next)
4752 if (GET_CODE (this_fix->insn) != BARRIER)
4754 int offset = add_minipool_constant (this_fix->value,
4757 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4758 minipool_vector_label),
4760 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
4763 dump_minipool (barrier);
4767 /* From now on we must synthesize any constants that we can't handle
4768 directly. This can happen if the RTL gets split during final
4769 instruction generation. */
4770 after_arm_reorg = 1;
4774 /* Routines to output assembly language. */
4776 /* If the rtx is the correct value then return the string of the number.
4777 In this way we can ensure that valid double constants are generated even
4778 when cross compiling. */
4780 fp_immediate_constant (x)
4786 if (!fpa_consts_inited)
4789 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4790 for (i = 0; i < 8; i++)
4791 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4792 return strings_fpa[i];
4797 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4799 fp_const_from_val (r)
4800 REAL_VALUE_TYPE * r;
4804 if (! fpa_consts_inited)
4807 for (i = 0; i < 8; i++)
4808 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4809 return strings_fpa[i];
4814 /* Output the operands of a LDM/STM instruction to STREAM.
4815 MASK is the ARM register set mask of which only bits 0-15 are important.
4816 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4817 must follow the register list. */
4820 print_multi_reg (stream, instr, reg, mask, hat)
4828 int not_first = FALSE;
4830 fputc ('\t', stream);
4831 asm_fprintf (stream, instr, reg);
4832 fputs (", {", stream);
4834 for (i = 0; i < 16; i++)
4835 if (mask & (1 << i))
4838 fprintf (stream, ", ");
4840 asm_fprintf (stream, "%r", i);
4844 fprintf (stream, "}%s\n", hat ? "^" : "");
4847 /* Output a 'call' insn. */
4850 output_call (operands)
4853 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4855 if (REGNO (operands[0]) == LR_REGNUM)
4857 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
4858 output_asm_insn ("mov%?\t%0, %|lr", operands);
4861 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4863 if (TARGET_INTERWORK)
4864 output_asm_insn ("bx%?\t%0", operands);
4866 output_asm_insn ("mov%?\t%|pc, %0", operands);
4875 int something_changed = 0;
4877 int code = GET_CODE (x0);
4879 register const char * fmt;
4884 if (REGNO (x0) == LR_REGNUM)
4886 *x = gen_rtx_REG (SImode, IP_REGNUM);
4891 /* Scan through the sub-elements and change any references there. */
4892 fmt = GET_RTX_FORMAT (code);
4894 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4896 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4897 else if (fmt[i] == 'E')
4898 for (j = 0; j < XVECLEN (x0, i); j++)
4899 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4901 return something_changed;
4905 /* Output a 'call' insn that is a reference in memory. */
4908 output_call_mem (operands)
4911 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
4912 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
4913 if (eliminate_lr2ip (&operands[0]))
4914 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4916 if (TARGET_INTERWORK)
4918 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4919 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4920 output_asm_insn ("bx%?\t%|ip", operands);
4924 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4925 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4932 /* Output a move from arm registers to an fpu registers.
4933 OPERANDS[0] is an fpu register.
4934 OPERANDS[1] is the first registers of an arm register pair. */
4937 output_mov_long_double_fpu_from_arm (operands)
4940 int arm_reg0 = REGNO (operands[1]);
4943 if (arm_reg0 == IP_REGNUM)
4946 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4947 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4948 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4950 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4951 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4956 /* Output a move from an fpu register to arm registers.
4957 OPERANDS[0] is the first registers of an arm register pair.
4958 OPERANDS[1] is an fpu register. */
4961 output_mov_long_double_arm_from_fpu (operands)
4964 int arm_reg0 = REGNO (operands[0]);
4967 if (arm_reg0 == IP_REGNUM)
4970 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4971 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4972 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4974 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4975 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4979 /* Output a move from arm registers to arm registers of a long double
4980 OPERANDS[0] is the destination.
4981 OPERANDS[1] is the source. */
4983 output_mov_long_double_arm_from_arm (operands)
4986 /* We have to be careful here because the two might overlap. */
4987 int dest_start = REGNO (operands[0]);
4988 int src_start = REGNO (operands[1]);
4992 if (dest_start < src_start)
4994 for (i = 0; i < 3; i++)
4996 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4997 ops[1] = gen_rtx_REG (SImode, src_start + i);
4998 output_asm_insn ("mov%?\t%0, %1", ops);
5003 for (i = 2; i >= 0; i--)
5005 ops[0] = gen_rtx_REG (SImode, dest_start + i);
5006 ops[1] = gen_rtx_REG (SImode, src_start + i);
5007 output_asm_insn ("mov%?\t%0, %1", ops);
5015 /* Output a move from arm registers to an fpu registers.
5016 OPERANDS[0] is an fpu register.
5017 OPERANDS[1] is the first registers of an arm register pair. */
5020 output_mov_double_fpu_from_arm (operands)
5023 int arm_reg0 = REGNO (operands[1]);
5026 if (arm_reg0 == IP_REGNUM)
5029 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5030 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5031 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
5032 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
5036 /* Output a move from an fpu register to arm registers.
5037 OPERANDS[0] is the first registers of an arm register pair.
5038 OPERANDS[1] is an fpu register. */
5041 output_mov_double_arm_from_fpu (operands)
5044 int arm_reg0 = REGNO (operands[0]);
5047 if (arm_reg0 == IP_REGNUM)
5050 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5051 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5052 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
5053 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
5057 /* Output a move between double words.
5058 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
5059 or MEM<-REG and all MEMs must be offsettable addresses. */
5062 output_move_double (operands)
5065 enum rtx_code code0 = GET_CODE (operands[0]);
5066 enum rtx_code code1 = GET_CODE (operands[1]);
5071 int reg0 = REGNO (operands[0]);
5073 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
5077 int reg1 = REGNO (operands[1]);
5078 if (reg1 == IP_REGNUM)
5081 /* Ensure the second source is not overwritten. */
5082 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
5083 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
5085 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
5087 else if (code1 == CONST_DOUBLE)
5089 if (GET_MODE (operands[1]) == DFmode)
5092 union real_extract u;
5094 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
5096 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
5097 otherops[1] = GEN_INT(l[1]);
5098 operands[1] = GEN_INT(l[0]);
5100 else if (GET_MODE (operands[1]) != VOIDmode)
5102 else if (WORDS_BIG_ENDIAN)
5105 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5106 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5111 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5112 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5115 output_mov_immediate (operands);
5116 output_mov_immediate (otherops);
5118 else if (code1 == CONST_INT)
5120 #if HOST_BITS_PER_WIDE_INT > 32
5121 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5122 what the upper word is. */
5123 if (WORDS_BIG_ENDIAN)
5125 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5126 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5130 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5131 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5134 /* Sign extend the intval into the high-order word. */
5135 if (WORDS_BIG_ENDIAN)
5137 otherops[1] = operands[1];
5138 operands[1] = (INTVAL (operands[1]) < 0
5139 ? constm1_rtx : const0_rtx);
5142 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
5144 output_mov_immediate (otherops);
5145 output_mov_immediate (operands);
5147 else if (code1 == MEM)
5149 switch (GET_CODE (XEXP (operands[1], 0)))
5152 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
5156 abort (); /* Should never happen now. */
5160 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
5164 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
5168 abort (); /* Should never happen now. */
5173 output_asm_insn ("adr%?\t%0, %1", operands);
5174 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
5178 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
5179 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
5181 otherops[0] = operands[0];
5182 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
5183 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
5184 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
5186 if (GET_CODE (otherops[2]) == CONST_INT)
5188 switch (INTVAL (otherops[2]))
5191 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
5194 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
5197 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
5200 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
5201 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
5203 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5206 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5209 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
5211 return "ldm%?ia\t%0, %M0";
5215 otherops[1] = adj_offsettable_operand (operands[1], 4);
5216 /* Take care of overlapping base/data reg. */
5217 if (reg_mentioned_p (operands[0], operands[1]))
5219 output_asm_insn ("ldr%?\t%0, %1", otherops);
5220 output_asm_insn ("ldr%?\t%0, %1", operands);
5224 output_asm_insn ("ldr%?\t%0, %1", operands);
5225 output_asm_insn ("ldr%?\t%0, %1", otherops);
5231 abort (); /* Constraints should prevent this. */
5233 else if (code0 == MEM && code1 == REG)
5235 if (REGNO (operands[1]) == IP_REGNUM)
5238 switch (GET_CODE (XEXP (operands[0], 0)))
5241 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
5245 abort (); /* Should never happen now. */
5249 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
5253 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
5257 abort (); /* Should never happen now. */
5261 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
5263 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
5266 output_asm_insn ("stm%?db\t%m0, %M1", operands);
5270 output_asm_insn ("stm%?da\t%m0, %M1", operands);
5274 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
5281 otherops[0] = adj_offsettable_operand (operands[0], 4);
5282 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
5283 output_asm_insn ("str%?\t%1, %0", operands);
5284 output_asm_insn ("str%?\t%1, %0", otherops);
5288 abort (); /* Constraints should prevent this */
5294 /* Output an arbitrary MOV reg, #n.
5295 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
5298 output_mov_immediate (operands)
5301 HOST_WIDE_INT n = INTVAL (operands[1]);
5305 /* Try to use one MOV */
5306 if (const_ok_for_arm (n))
5308 output_asm_insn ("mov%?\t%0, %1", operands);
5312 /* Try to use one MVN */
5313 if (const_ok_for_arm (~n))
5315 operands[1] = GEN_INT (~n);
5316 output_asm_insn ("mvn%?\t%0, %1", operands);
5320 /* If all else fails, make it out of ORRs or BICs as appropriate. */
5322 for (i=0; i < 32; i++)
5326 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
5327 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5330 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5337 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5338 adding zero to one register, output nothing. */
5341 output_add_immediate (operands)
5344 HOST_WIDE_INT n = INTVAL (operands[2]);
5346 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
5349 output_multi_immediate (operands,
5350 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5353 output_multi_immediate (operands,
5354 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5361 /* Output a multiple immediate operation.
5362 OPERANDS is the vector of operands referred to in the output patterns.
5363 INSTR1 is the output pattern to use for the first constant.
5364 INSTR2 is the output pattern to use for subsequent constants.
5365 IMMED_OP is the index of the constant slot in OPERANDS.
5366 N is the constant value. */
5369 output_multi_immediate (operands, instr1, instr2, immed_op, n)
5371 char * instr1, * instr2;
5375 #if HOST_BITS_PER_WIDE_INT > 32
5381 operands[immed_op] = const0_rtx;
5382 output_asm_insn (instr1, operands); /* Quick and easy output. */
5387 char *instr = instr1;
5389 /* Note that n is never zero here (which would give no output). */
5390 for (i = 0; i < 32; i += 2)
5394 operands[immed_op] = GEN_INT (n & (255 << i));
5395 output_asm_insn (instr, operands);
5405 /* Return the appropriate ARM instruction for the operation code.
5406 The returned result should not be overwritten. OP is the rtx of the
5407 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5411 arithmetic_instr (op, shift_first_arg)
5413 int shift_first_arg;
5415 switch (GET_CODE (op))
5421 return shift_first_arg ? "rsb" : "sub";
5438 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5439 for the operation code. The returned result should not be overwritten.
5440 OP is the rtx code of the shift.
5441 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5445 shift_op (op, amountp)
5447 HOST_WIDE_INT *amountp;
5450 enum rtx_code code = GET_CODE (op);
5452 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5454 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5455 *amountp = INTVAL (XEXP (op, 1));
5478 /* We never have to worry about the amount being other than a
5479 power of 2, since this case can never be reloaded from a reg. */
5481 *amountp = int_log2 (*amountp);
5492 /* This is not 100% correct, but follows from the desire to merge
5493 multiplication by a power of 2 with the recognizer for a
5494 shift. >=32 is not a valid shift for "asl", so we must try and
5495 output a shift that produces the correct arithmetical result.
5496 Using lsr #32 is identical except for the fact that the carry bit
5497 is not set correctly if we set the flags; but we never use the
5498 carry bit from such an operation, so we can ignore that. */
5499 if (code == ROTATERT)
5500 *amountp &= 31; /* Rotate is just modulo 32 */
5501 else if (*amountp != (*amountp & 31))
5508 /* Shifts of 0 are no-ops. */
5517 /* Obtain the shift from the POWER of two. */
5518 static HOST_WIDE_INT
5520 HOST_WIDE_INT power;
5522 HOST_WIDE_INT shift = 0;
5524 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5534 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5535 /bin/as is horribly restrictive. */
5536 #define MAX_ASCII_LEN 51
5539 output_ascii_pseudo_op (stream, p, len)
5541 const unsigned char * p;
5547 fputs ("\t.ascii\t\"", stream);
5549 for (i = 0; i < len; i++)
5551 register int c = p[i];
5553 if (len_so_far >= MAX_ASCII_LEN)
5555 fputs ("\"\n\t.ascii\t\"", stream);
5562 fputs ("\\t", stream);
5567 fputs ("\\f", stream);
5572 fputs ("\\b", stream);
5577 fputs ("\\r", stream);
5581 case TARGET_NEWLINE:
5582 fputs ("\\n", stream);
5584 if ((c >= ' ' && c <= '~')
5586 /* This is a good place for a line break. */
5587 len_so_far = MAX_ASCII_LEN;
5594 putc ('\\', stream);
5599 if (c >= ' ' && c <= '~')
5606 fprintf (stream, "\\%03o", c);
5613 fputs ("\"\n", stream);
5617 /* Try to determine whether a pattern really clobbers the link register.
5618 This information is useful when peepholing, so that lr need not be pushed
5619 if we combine a call followed by a return.
5620 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5621 such a check should not be needed because these only update an existing
5622 value within a register; the register must still be set elsewhere within
5625 pattern_really_clobbers_lr (x)
5630 switch (GET_CODE (x))
5633 switch (GET_CODE (SET_DEST (x)))
5636 return REGNO (SET_DEST (x)) == LR_REGNUM;
5639 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5640 return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
5642 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5651 for (i = 0; i < XVECLEN (x, 0); i++)
5652 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5657 switch (GET_CODE (XEXP (x, 0)))
5660 return REGNO (XEXP (x, 0)) == LR_REGNUM;
5663 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5664 return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
5680 function_really_clobbers_lr (first)
5685 for (insn = first; insn; insn = next_nonnote_insn (insn))
5687 switch (GET_CODE (insn))
5692 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5696 if (pattern_really_clobbers_lr (PATTERN (insn)))
5701 /* Don't yet know how to handle those calls that are not to a
5703 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5706 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5709 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5715 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5721 default: /* Don't recognize it, be safe. */
5725 /* A call can be made (by peepholing) not to clobber lr iff it is
5726 followed by a return. There may, however, be a use insn iff
5727 we are returning the result of the call.
5728 If we run off the end of the insn chain, then that means the
5729 call was at the end of the function. Unfortunately we don't
5730 have a return insn for the peephole to recognize, so we
5731 must reject this. (Can this be fixed by adding our own insn?) */
5732 if ((next = next_nonnote_insn (insn)) == NULL)
5735 /* No need to worry about lr if the call never returns. */
5736 if (GET_CODE (next) == BARRIER)
5739 if (GET_CODE (next) == INSN
5740 && GET_CODE (PATTERN (next)) == USE
5741 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5742 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5743 == REGNO (XEXP (PATTERN (next), 0))))
5744 if ((next = next_nonnote_insn (next)) == NULL)
5747 if (GET_CODE (next) == JUMP_INSN
5748 && GET_CODE (PATTERN (next)) == RETURN)
5757 /* We have reached the end of the chain so lr was _not_ clobbered. */
5762 output_return_instruction (operand, really_return, reverse)
5768 int reg, live_regs = 0;
5769 int volatile_func = arm_volatile_func ();
5771 return_used_this_function = 1;
5773 if (TARGET_ABORT_NORETURN && volatile_func)
5775 /* If this function was declared non-returning, and we have found a tail
5776 call, then we have to trust that the called function won't return. */
5781 /* Otherwise, trap an attempted return by aborting. */
5783 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
5785 assemble_external_libcall (ops[1]);
5786 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5792 if (current_function_calls_alloca && ! really_return)
5795 for (reg = 0; reg <= 10; reg++)
5796 if (regs_ever_live[reg] && ! call_used_regs[reg])
5799 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5800 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5803 if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
5806 if (frame_pointer_needed)
5809 /* On some ARM architectures it is faster to use LDR rather than LDM to
5810 load a single register. On other architectures, the cost is the same. */
5812 && regs_ever_live[LR_REGNUM]
5813 && ! lr_save_eliminated
5814 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
5815 really_return is true, and only the PC needs restoring. */
5818 output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
5819 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
5823 if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
5826 if (frame_pointer_needed)
5828 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5831 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5833 for (reg = 0; reg <= 10; reg++)
5834 if (regs_ever_live[reg]
5835 && (! call_used_regs[reg]
5836 || (flag_pic && ! TARGET_SINGLE_PIC_BASE
5837 && reg == PIC_OFFSET_TABLE_REGNUM)))
5839 strcat (instr, "%|");
5840 strcat (instr, reg_names[reg]);
5842 strcat (instr, ", ");
5845 if (frame_pointer_needed)
5847 strcat (instr, "%|");
5848 strcat (instr, reg_names[11]);
5849 strcat (instr, ", ");
5850 strcat (instr, "%|");
5851 strcat (instr, reg_names[13]);
5852 strcat (instr, ", ");
5853 strcat (instr, "%|");
5854 strcat (instr, TARGET_INTERWORK || (! really_return)
5855 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
5859 strcat (instr, "%|");
5860 if (TARGET_INTERWORK && really_return)
5861 strcat (instr, reg_names[IP_REGNUM]);
5863 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
5865 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5866 output_asm_insn (instr, &operand);
5868 if (TARGET_INTERWORK && really_return)
5870 strcpy (instr, "bx%?");
5871 strcat (instr, reverse ? "%D0" : "%d0");
5872 strcat (instr, "\t%|");
5873 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5875 output_asm_insn (instr, & operand);
5878 else if (really_return)
5880 if (TARGET_INTERWORK)
5881 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5883 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5884 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5886 output_asm_insn (instr, & operand);
5892 /* Return nonzero if optimizing and the current function is volatile.
5893 Such functions never return, and many memory cycles can be saved
5894 by not storing register values that will never be needed again.
5895 This optimization was added to speed up context switching in a
5896 kernel application. */
5898 arm_volatile_func ()
5900 return (optimize > 0
5901 && current_function_nothrow
5902 && TREE_THIS_VOLATILE (current_function_decl));
5905 /* Write the function name into the code section, directly preceding
5906 the function prologue.
5908 Code will be output similar to this:
5910 .ascii "arm_poke_function_name", 0
5913 .word 0xff000000 + (t1 - t0)
5914 arm_poke_function_name
5916 stmfd sp!, {fp, ip, lr, pc}
5919 When performing a stack backtrace, code can inspect the value
5920 of 'pc' stored at 'fp' + 0. If the trace function then looks
5921 at location pc - 12 and the top 8 bits are set, then we know
5922 that there is a function name embedded immediately preceding this
5923 location and has length ((pc[-3]) & 0xff000000).
5925 We assume that pc is declared as a pointer to an unsigned long.
5927 It is of no benefit to output the function name if we are assembling
5928 a leaf function. These function types will not contain a stack
5929 backtrace structure, therefore it is not possible to determine the
5933 arm_poke_function_name (stream, name)
5937 unsigned long alignlength;
5938 unsigned long length;
5941 length = strlen (name) + 1;
5942 alignlength = (length + 3) & ~3;
5944 ASM_OUTPUT_ASCII (stream, name, length);
5945 ASM_OUTPUT_ALIGN (stream, 2);
5946 x = GEN_INT (0xff000000UL + alignlength);
5947 ASM_OUTPUT_INT (stream, x);
5950 /* The amount of stack adjustment that happens here, in output_return and in
5951 output_epilogue must be exactly the same as was calculated during reload,
5952 or things will point to the wrong place. The only time we can safely
5953 ignore this constraint is when a function has no arguments on the stack,
5954 no stack frame requirement and no live registers execpt for `lr'. If we
5955 can guarantee that by making all function calls into tail calls and that
5956 lr is not clobbered in any other way, then there is no need to push lr
5959 output_func_prologue (f, frame_size)
5963 int reg, live_regs_mask = 0;
5964 int volatile_func = arm_volatile_func ();
5966 /* Nonzero if we must stuff some register arguments onto the stack as if
5967 they were passed there. */
5968 int store_arg_regs = 0;
5970 if (arm_ccfsm_state || arm_target_insn)
5971 abort (); /* Sanity check. */
5973 if (arm_naked_function_p (current_function_decl))
5976 return_used_this_function = 0;
5977 lr_save_eliminated = 0;
5979 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
5980 current_function_args_size,
5981 current_function_pretend_args_size, frame_size);
5982 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
5983 frame_pointer_needed,
5984 current_function_anonymous_args);
5987 asm_fprintf (f, "\t%@ Volatile function.\n");
5989 if (current_function_anonymous_args && current_function_pretend_args_size)
5992 for (reg = 0; reg <= 10; reg++)
5993 if (regs_ever_live[reg] && ! call_used_regs[reg])
5994 live_regs_mask |= (1 << reg);
5996 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5997 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5998 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6000 if (frame_pointer_needed)
6001 live_regs_mask |= 0xD800;
6002 else if (regs_ever_live[LR_REGNUM])
6004 if (! current_function_args_size
6005 && ! function_really_clobbers_lr (get_insns ()))
6006 lr_save_eliminated = 1;
6008 live_regs_mask |= 1 << LR_REGNUM;
6013 /* If a di mode load/store multiple is used, and the base register
6014 is r3, then r4 can become an ever live register without lr
6015 doing so, in this case we need to push lr as well, or we
6016 will fail to get a proper return. */
6017 live_regs_mask |= 1 << LR_REGNUM;
6018 lr_save_eliminated = 0;
6022 if (lr_save_eliminated)
6023 asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
6025 #ifdef AOF_ASSEMBLER
6027 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
6032 arm_output_epilogue ()
6035 int live_regs_mask = 0;
6036 /* If we need this, then it will always be at least this much. */
6037 int floats_offset = 12;
6039 int frame_size = get_frame_size ();
6040 FILE *f = asm_out_file;
6041 int volatile_func = arm_volatile_func ();
6043 if (use_return_insn (FALSE) && return_used_this_function)
6046 /* Naked functions don't have epilogues. */
6047 if (arm_naked_function_p (current_function_decl))
6050 /* A volatile function should never return. Call abort. */
6051 if (TARGET_ABORT_NORETURN && volatile_func)
6054 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
6055 assemble_external_libcall (op);
6056 output_asm_insn ("bl\t%a0", &op);
6060 for (reg = 0; reg <= 10; reg++)
6061 if (regs_ever_live[reg] && ! call_used_regs[reg])
6063 live_regs_mask |= (1 << reg);
6067 /* If we aren't loading the PIC register, don't stack it even though it may
6069 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
6070 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6072 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6076 if (frame_pointer_needed)
6078 if (arm_fpu_arch == FP_SOFT2)
6080 for (reg = 23; reg > 15; reg--)
6081 if (regs_ever_live[reg] && ! call_used_regs[reg])
6083 floats_offset += 12;
6084 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
6085 reg, FP_REGNUM, floats_offset);
6092 for (reg = 23; reg > 15; reg--)
6094 if (regs_ever_live[reg] && ! call_used_regs[reg])
6096 floats_offset += 12;
6098 /* We can't unstack more than four registers at once. */
6099 if (start_reg - reg == 3)
6101 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
6102 reg, FP_REGNUM, floats_offset);
6103 start_reg = reg - 1;
6108 if (reg != start_reg)
6109 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6110 reg + 1, start_reg - reg,
6111 FP_REGNUM, floats_offset);
6112 start_reg = reg - 1;
6116 /* Just in case the last register checked also needs unstacking. */
6117 if (reg != start_reg)
6118 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6119 reg + 1, start_reg - reg,
6120 FP_REGNUM, floats_offset);
6123 if (TARGET_INTERWORK)
6125 live_regs_mask |= 0x6800;
6126 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
6127 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6131 live_regs_mask |= 0xA800;
6132 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
6133 TARGET_APCS_32 ? FALSE : TRUE);
6138 /* Restore stack pointer if necessary. */
6139 if (frame_size + current_function_outgoing_args_size != 0)
6141 operands[0] = operands[1] = stack_pointer_rtx;
6142 operands[2] = GEN_INT (frame_size
6143 + current_function_outgoing_args_size);
6144 output_add_immediate (operands);
6147 if (arm_fpu_arch == FP_SOFT2)
6149 for (reg = 16; reg < 24; reg++)
6150 if (regs_ever_live[reg] && ! call_used_regs[reg])
6151 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
6158 for (reg = 16; reg < 24; reg++)
6160 if (regs_ever_live[reg] && ! call_used_regs[reg])
6162 if (reg - start_reg == 3)
6164 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
6165 start_reg, SP_REGNUM);
6166 start_reg = reg + 1;
6171 if (reg != start_reg)
6172 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6173 start_reg, reg - start_reg,
6176 start_reg = reg + 1;
6180 /* Just in case the last register checked also needs unstacking. */
6181 if (reg != start_reg)
6182 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6183 start_reg, reg - start_reg, SP_REGNUM);
6186 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
6188 if (TARGET_INTERWORK)
6190 if (! lr_save_eliminated)
6191 live_regs_mask |= 1 << LR_REGNUM;
6193 if (live_regs_mask != 0)
6194 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6196 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6198 else if (lr_save_eliminated)
6200 TARGET_APCS_32 ? "\tmov\t%r, %r\n" : "\tmovs\t%r, %r\n",
6201 PC_REGNUM, LR_REGNUM);
6203 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
6204 TARGET_APCS_32 ? FALSE : TRUE);
6208 if (live_regs_mask || regs_ever_live[LR_REGNUM])
6210 /* Restore the integer regs, and the return address into lr. */
6211 if (! lr_save_eliminated)
6212 live_regs_mask |= 1 << LR_REGNUM;
6214 if (live_regs_mask != 0)
6215 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6218 if (current_function_pretend_args_size)
6220 /* Unwind the pre-pushed regs. */
6221 operands[0] = operands[1] = stack_pointer_rtx;
6222 operands[2] = GEN_INT (current_function_pretend_args_size);
6223 output_add_immediate (operands);
6225 /* And finally, go home. */
6226 if (TARGET_INTERWORK)
6227 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6228 else if (TARGET_APCS_32)
6229 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6231 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6239 output_func_epilogue (frame_size)
6242 if (use_return_insn (FALSE) && return_used_this_function
6243 && (frame_size + current_function_outgoing_args_size) != 0
6244 && ! (frame_pointer_needed && TARGET_APCS))
6247 /* Reset the ARM-specific per-function variables. */
6248 current_function_anonymous_args = 0;
6249 after_arm_reorg = 0;
6252 /* Generate and emit an insn that we will recognize as a push_multi.
6253 Unfortunately, since this insn does not reflect very well the actual
6254 semantics of the operation, we need to annotate the insn for the benefit
6255 of DWARF2 frame unwind information. */
6257 emit_multi_reg_push (mask)
6266 for (i = 0; i < 16; i++)
6267 if (mask & (1 << i))
6270 if (num_regs == 0 || num_regs > 16)
6273 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
6274 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
6275 RTX_FRAME_RELATED_P (dwarf) = 1;
6277 for (i = 0; i < 16; i++)
6279 if (mask & (1 << i))
6281 reg = gen_rtx_REG (SImode, i);
6284 = gen_rtx_SET (VOIDmode,
6285 gen_rtx_MEM (BLKmode,
6286 gen_rtx_PRE_DEC (BLKmode,
6287 stack_pointer_rtx)),
6288 gen_rtx_UNSPEC (BLKmode,
6292 tmp = gen_rtx_SET (VOIDmode,
6293 gen_rtx_MEM (SImode,
6294 gen_rtx_PRE_DEC (BLKmode,
6295 stack_pointer_rtx)),
6297 RTX_FRAME_RELATED_P (tmp) = 1;
6298 XVECEXP (dwarf, 0, num_regs - 1) = tmp;
6304 for (j = 1, i++; j < num_regs; i++)
6306 if (mask & (1 << i))
6308 reg = gen_rtx_REG (SImode, i);
6310 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
6312 tmp = gen_rtx_SET (VOIDmode,
6313 gen_rtx_MEM (SImode,
6314 gen_rtx_PRE_DEC (BLKmode,
6315 stack_pointer_rtx)),
6317 RTX_FRAME_RELATED_P (tmp) = 1;
6318 XVECEXP (dwarf, 0, num_regs - j - 1) = tmp;
6324 par = emit_insn (par);
6325 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
6331 emit_sfm (base_reg, count)
6340 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6341 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6342 RTX_FRAME_RELATED_P (dwarf) = 1;
6344 reg = gen_rtx_REG (XFmode, base_reg++);
6347 = gen_rtx_SET (VOIDmode,
6348 gen_rtx_MEM (BLKmode,
6349 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
6350 gen_rtx_UNSPEC (BLKmode,
6354 = gen_rtx_SET (VOIDmode,
6355 gen_rtx_MEM (XFmode,
6356 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
6358 RTX_FRAME_RELATED_P (tmp) = 1;
6359 XVECEXP (dwarf, 0, count - 1) = tmp;
6361 for (i = 1; i < count; i++)
6363 reg = gen_rtx_REG (XFmode, base_reg++);
6364 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
6366 tmp = gen_rtx_SET (VOIDmode,
6367 gen_rtx_MEM (XFmode,
6368 gen_rtx_PRE_DEC (BLKmode,
6369 stack_pointer_rtx)),
6371 RTX_FRAME_RELATED_P (tmp) = 1;
6372 XVECEXP (dwarf, 0, count - i - 1) = tmp;
6375 par = emit_insn (par);
6376 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
6382 arm_expand_prologue ()
6385 rtx amount = GEN_INT (-(get_frame_size ()
6386 + current_function_outgoing_args_size));
6387 int live_regs_mask = 0;
6388 int store_arg_regs = 0;
6389 /* If this function doesn't return, then there is no need to push
6390 the call-saved regs. */
6391 int volatile_func = arm_volatile_func ();
6394 /* Naked functions don't have prologues. */
6395 if (arm_naked_function_p (current_function_decl))
6398 if (current_function_anonymous_args && current_function_pretend_args_size)
6401 if (! volatile_func)
6403 for (reg = 0; reg <= 10; reg++)
6404 if (regs_ever_live[reg] && ! call_used_regs[reg])
6405 live_regs_mask |= 1 << reg;
6407 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6408 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6410 if (regs_ever_live[LR_REGNUM])
6411 live_regs_mask |= 1 << LR_REGNUM;
6414 if (frame_pointer_needed)
6416 live_regs_mask |= 0xD800;
6417 insn = emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
6418 stack_pointer_rtx));
6419 RTX_FRAME_RELATED_P (insn) = 1;
6422 if (current_function_pretend_args_size)
6425 insn = emit_multi_reg_push
6426 ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
6429 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6430 GEN_INT (-current_function_pretend_args_size)));
6431 RTX_FRAME_RELATED_P (insn) = 1;
6436 /* If we have to push any regs, then we must push lr as well, or
6437 we won't get a proper return. */
6438 live_regs_mask |= 1 << LR_REGNUM;
6439 insn = emit_multi_reg_push (live_regs_mask);
6440 RTX_FRAME_RELATED_P (insn) = 1;
6443 /* And now the floating point regs. */
6444 if (! volatile_func)
6446 if (arm_fpu_arch == FP_SOFT2)
6448 for (reg = 23; reg > 15; reg--)
6449 if (regs_ever_live[reg] && ! call_used_regs[reg])
6451 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
6452 insn = gen_rtx_MEM (XFmode, insn);
6453 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
6454 gen_rtx_REG (XFmode, reg)));
6455 RTX_FRAME_RELATED_P (insn) = 1;
6462 for (reg = 23; reg > 15; reg--)
6464 if (regs_ever_live[reg] && ! call_used_regs[reg])
6466 if (start_reg - reg == 3)
6468 insn = emit_sfm (reg, 4);
6469 RTX_FRAME_RELATED_P (insn) = 1;
6470 start_reg = reg - 1;
6475 if (start_reg != reg)
6477 insn = emit_sfm (reg + 1, start_reg - reg);
6478 RTX_FRAME_RELATED_P (insn) = 1;
6480 start_reg = reg - 1;
6484 if (start_reg != reg)
6486 insn = emit_sfm (reg + 1, start_reg - reg);
6487 RTX_FRAME_RELATED_P (insn) = 1;
6492 if (frame_pointer_needed)
6494 insn = GEN_INT (-(4 + current_function_pretend_args_size));
6495 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6496 gen_rtx_REG (SImode, IP_REGNUM),
6498 RTX_FRAME_RELATED_P (insn) = 1;
6501 if (amount != const0_rtx)
6503 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6505 RTX_FRAME_RELATED_P (insn) = 1;
6506 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6507 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
6510 /* If we are profiling, make sure no instructions are scheduled before
6511 the call to mcount. Similarly if the user has requested no
6512 scheduling in the prolog. */
6513 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
6514 emit_insn (gen_blockage ());
6518 /* If CODE is 'd', then the X is a condition operand and the instruction
6519 should only be executed if the condition is true.
6520 if CODE is 'D', then the X is a condition operand and the instruction
6521 should only be executed if the condition is false: however, if the mode
6522 of the comparison is CCFPEmode, then always execute the instruction -- we
6523 do this because in these circumstances !GE does not necessarily imply LT;
6524 in these cases the instruction pattern will take care to make sure that
6525 an instruction containing %d will follow, thereby undoing the effects of
6526 doing this instruction unconditionally.
6527 If CODE is 'N' then X is a floating point operand that must be negated
6529 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6530 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6533 arm_print_operand (stream, x, code)
6541 fputs (ASM_COMMENT_START, stream);
6545 fputs (REGISTER_PREFIX, stream);
6549 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
6550 fputs (arm_condition_codes[arm_current_cc], stream);
6556 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6557 r = REAL_VALUE_NEGATE (r);
6558 fprintf (stream, "%s", fp_const_from_val (&r));
6563 if (GET_CODE (x) == CONST_INT)
6566 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6567 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6572 output_addr_const (stream, x);
6577 fprintf (stream, "%s", arithmetic_instr (x, 1));
6581 fprintf (stream, "%s", arithmetic_instr (x, 0));
6587 char * shift = shift_op (x, & val);
6591 fprintf (stream, ", %s ", shift_op (x, & val));
6593 arm_print_operand (stream, XEXP (x, 1), 0);
6596 fputc ('#', stream);
6597 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6606 fputs (REGISTER_PREFIX, stream);
6607 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6613 fputs (REGISTER_PREFIX, stream);
6614 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6618 fputs (REGISTER_PREFIX, stream);
6619 if (GET_CODE (XEXP (x, 0)) == REG)
6620 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6622 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6626 asm_fprintf (stream, "{%r-%r}",
6627 REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
6632 fputs (arm_condition_codes[get_arm_condition_code (x)],
6638 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6639 (get_arm_condition_code (x))],
6647 if (GET_CODE (x) == REG)
6649 fputs (REGISTER_PREFIX, stream);
6650 fputs (reg_names[REGNO (x)], stream);
6652 else if (GET_CODE (x) == MEM)
6654 output_memory_reference_mode = GET_MODE (x);
6655 output_address (XEXP (x, 0));
6657 else if (GET_CODE (x) == CONST_DOUBLE)
6658 fprintf (stream, "#%s", fp_immediate_constant (x));
6659 else if (GET_CODE (x) == NEG)
6660 abort (); /* This should never happen now. */
6663 fputc ('#', stream);
6664 output_addr_const (stream, x);
6669 /* A finite state machine takes care of noticing whether or not instructions
6670 can be conditionally executed, and thus decrease execution time and code
6671 size by deleting branch instructions. The fsm is controlled by
6672 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6674 /* The state of the fsm controlling condition codes are:
6675 0: normal, do nothing special
6676 1: make ASM_OUTPUT_OPCODE not output this instruction
6677 2: make ASM_OUTPUT_OPCODE not output this instruction
6678 3: make instructions conditional
6679 4: make instructions conditional
6681 State transitions (state->state by whom under condition):
6682 0 -> 1 final_prescan_insn if the `target' is a label
6683 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6684 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6685 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6686 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6687 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6688 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6689 (the target insn is arm_target_insn).
6691 If the jump clobbers the conditions then we use states 2 and 4.
6693 A similar thing can be done with conditional return insns.
6695 XXX In case the `target' is an unconditional branch, this conditionalising
6696 of the instructions always reduces code size, but not always execution
6697 time. But then, I want to reduce the code size to somewhere near what
6698 /bin/cc produces. */
6700 /* Returns the index of the ARM condition code string in
6701 `arm_condition_codes'. COMPARISON should be an rtx like
6702 `(eq (...) (...))'. */
6704 static enum arm_cond_code
6705 get_arm_condition_code (comparison)
6708 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6710 register enum rtx_code comp_code = GET_CODE (comparison);
6712 if (GET_MODE_CLASS (mode) != MODE_CC)
6713 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6714 XEXP (comparison, 1));
6718 case CC_DNEmode: code = ARM_NE; goto dominance;
6719 case CC_DEQmode: code = ARM_EQ; goto dominance;
6720 case CC_DGEmode: code = ARM_GE; goto dominance;
6721 case CC_DGTmode: code = ARM_GT; goto dominance;
6722 case CC_DLEmode: code = ARM_LE; goto dominance;
6723 case CC_DLTmode: code = ARM_LT; goto dominance;
6724 case CC_DGEUmode: code = ARM_CS; goto dominance;
6725 case CC_DGTUmode: code = ARM_HI; goto dominance;
6726 case CC_DLEUmode: code = ARM_LS; goto dominance;
6727 case CC_DLTUmode: code = ARM_CC;
6730 if (comp_code != EQ && comp_code != NE)
6733 if (comp_code == EQ)
6734 return ARM_INVERSE_CONDITION_CODE (code);
6740 case NE: return ARM_NE;
6741 case EQ: return ARM_EQ;
6742 case GE: return ARM_PL;
6743 case LT: return ARM_MI;
6751 case NE: return ARM_NE;
6752 case EQ: return ARM_EQ;
6759 case GE: return ARM_GE;
6760 case GT: return ARM_GT;
6761 case LE: return ARM_LS;
6762 case LT: return ARM_MI;
6769 case NE: return ARM_NE;
6770 case EQ: return ARM_EQ;
6771 case GE: return ARM_LE;
6772 case GT: return ARM_LT;
6773 case LE: return ARM_GE;
6774 case LT: return ARM_GT;
6775 case GEU: return ARM_LS;
6776 case GTU: return ARM_CC;
6777 case LEU: return ARM_CS;
6778 case LTU: return ARM_HI;
6785 case LTU: return ARM_CS;
6786 case GEU: return ARM_CC;
6793 case NE: return ARM_NE;
6794 case EQ: return ARM_EQ;
6795 case GE: return ARM_GE;
6796 case GT: return ARM_GT;
6797 case LE: return ARM_LE;
6798 case LT: return ARM_LT;
6799 case GEU: return ARM_CS;
6800 case GTU: return ARM_HI;
6801 case LEU: return ARM_LS;
6802 case LTU: return ARM_CC;
6814 arm_final_prescan_insn (insn)
6817 /* BODY will hold the body of INSN. */
6818 register rtx body = PATTERN (insn);
6820 /* This will be 1 if trying to repeat the trick, and things need to be
6821 reversed if it appears to fail. */
6824 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6825 taken are clobbered, even if the rtl suggests otherwise. It also
6826 means that we have to grub around within the jump expression to find
6827 out what the conditions are when the jump isn't taken. */
6828 int jump_clobbers = 0;
6830 /* If we start with a return insn, we only succeed if we find another one. */
6831 int seeking_return = 0;
6833 /* START_INSN will hold the insn from where we start looking. This is the
6834 first insn after the following code_label if REVERSE is true. */
6835 rtx start_insn = insn;
6837 /* If in state 4, check if the target branch is reached, in order to
6838 change back to state 0. */
6839 if (arm_ccfsm_state == 4)
6841 if (insn == arm_target_insn)
6843 arm_target_insn = NULL;
6844 arm_ccfsm_state = 0;
6849 /* If in state 3, it is possible to repeat the trick, if this insn is an
6850 unconditional branch to a label, and immediately following this branch
6851 is the previous target label which is only used once, and the label this
6852 branch jumps to is not too far off. */
6853 if (arm_ccfsm_state == 3)
6855 if (simplejump_p (insn))
6857 start_insn = next_nonnote_insn (start_insn);
6858 if (GET_CODE (start_insn) == BARRIER)
6860 /* XXX Isn't this always a barrier? */
6861 start_insn = next_nonnote_insn (start_insn);
6863 if (GET_CODE (start_insn) == CODE_LABEL
6864 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6865 && LABEL_NUSES (start_insn) == 1)
6870 else if (GET_CODE (body) == RETURN)
6872 start_insn = next_nonnote_insn (start_insn);
6873 if (GET_CODE (start_insn) == BARRIER)
6874 start_insn = next_nonnote_insn (start_insn);
6875 if (GET_CODE (start_insn) == CODE_LABEL
6876 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6877 && LABEL_NUSES (start_insn) == 1)
6889 if (arm_ccfsm_state != 0 && !reverse)
6891 if (GET_CODE (insn) != JUMP_INSN)
6894 /* This jump might be paralleled with a clobber of the condition codes
6895 the jump should always come first */
6896 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6897 body = XVECEXP (body, 0, 0);
6900 /* If this is a conditional return then we don't want to know */
6901 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6902 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6903 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6904 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6909 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6910 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6913 int fail = FALSE, succeed = FALSE;
6914 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6915 int then_not_else = TRUE;
6916 rtx this_insn = start_insn, label = 0;
6918 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6920 /* The code below is wrong for these, and I haven't time to
6921 fix it now. So we just do the safe thing and return. This
6922 whole function needs re-writing anyway. */
6927 /* Register the insn jumped to. */
6930 if (!seeking_return)
6931 label = XEXP (SET_SRC (body), 0);
6933 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6934 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6935 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6937 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6938 then_not_else = FALSE;
6940 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6942 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6945 then_not_else = FALSE;
6950 /* See how many insns this branch skips, and what kind of insns. If all
6951 insns are okay, and the label or unconditional branch to the same
6952 label is not too far away, succeed. */
6953 for (insns_skipped = 0;
6954 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6958 this_insn = next_nonnote_insn (this_insn);
6962 switch (GET_CODE (this_insn))
6965 /* Succeed if it is the target label, otherwise fail since
6966 control falls in from somewhere else. */
6967 if (this_insn == label)
6971 arm_ccfsm_state = 2;
6972 this_insn = next_nonnote_insn (this_insn);
6975 arm_ccfsm_state = 1;
6983 /* Succeed if the following insn is the target label.
6985 If return insns are used then the last insn in a function
6986 will be a barrier. */
6987 this_insn = next_nonnote_insn (this_insn);
6988 if (this_insn && this_insn == label)
6992 arm_ccfsm_state = 2;
6993 this_insn = next_nonnote_insn (this_insn);
6996 arm_ccfsm_state = 1;
7004 /* If using 32-bit addresses the cc is not preserved over
7008 /* Succeed if the following insn is the target label,
7009 or if the following two insns are a barrier and
7010 the target label. */
7011 this_insn = next_nonnote_insn (this_insn);
7012 if (this_insn && GET_CODE (this_insn) == BARRIER)
7013 this_insn = next_nonnote_insn (this_insn);
7015 if (this_insn && this_insn == label
7016 && insns_skipped < max_insns_skipped)
7020 arm_ccfsm_state = 2;
7021 this_insn = next_nonnote_insn (this_insn);
7024 arm_ccfsm_state = 1;
7033 /* If this is an unconditional branch to the same label, succeed.
7034 If it is to another label, do nothing. If it is conditional,
7036 /* XXX Probably, the tests for SET and the PC are unnecessary. */
7038 scanbody = PATTERN (this_insn);
7039 if (GET_CODE (scanbody) == SET
7040 && GET_CODE (SET_DEST (scanbody)) == PC)
7042 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
7043 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
7045 arm_ccfsm_state = 2;
7048 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
7051 /* Fail if a conditional return is undesirable (eg on a
7052 StrongARM), but still allow this if optimizing for size. */
7053 else if (GET_CODE (scanbody) == RETURN
7054 && ! use_return_insn (TRUE)
7057 else if (GET_CODE (scanbody) == RETURN
7060 arm_ccfsm_state = 2;
7063 else if (GET_CODE (scanbody) == PARALLEL)
7065 switch (get_attr_conds (this_insn))
7077 /* Instructions using or affecting the condition codes make it
7079 scanbody = PATTERN (this_insn);
7080 if (! (GET_CODE (scanbody) == SET
7081 || GET_CODE (scanbody) == PARALLEL)
7082 || get_attr_conds (this_insn) != CONDS_NOCOND)
7092 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
7093 arm_target_label = CODE_LABEL_NUMBER (label);
7094 else if (seeking_return || arm_ccfsm_state == 2)
7096 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
7098 this_insn = next_nonnote_insn (this_insn);
7099 if (this_insn && (GET_CODE (this_insn) == BARRIER
7100 || GET_CODE (this_insn) == CODE_LABEL))
7105 /* Oh, dear! we ran off the end.. give up */
7106 recog (PATTERN (insn), insn, NULL_PTR);
7107 arm_ccfsm_state = 0;
7108 arm_target_insn = NULL;
7111 arm_target_insn = this_insn;
7120 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
7122 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
7123 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7124 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
7125 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7129 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
7132 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
7136 if (reverse || then_not_else)
7137 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7140 /* Restore recog_data (getting the attributes of other insns can
7141 destroy this array, but final.c assumes that it remains intact
7142 across this call; since the insn has been recognized already we
7143 call recog direct). */
7144 recog (PATTERN (insn), insn, NULL_PTR);
7148 /* Return the length of a function name prefix
7149 that starts with the character 'c'. */
7151 arm_get_strip_length (char c)
7155 ARM_NAME_ENCODING_LENGTHS
7160 /* Return a pointer to a function's name with any
7161 and all prefix encodings stripped from it. */
7163 arm_strip_name_encoding (const char * name)
7167 while ((skip = arm_get_strip_length (* name)))
7173 #ifdef AOF_ASSEMBLER
7174 /* Special functions only needed when producing AOF syntax assembler. */
7176 rtx aof_pic_label = NULL_RTX;
7179 struct pic_chain * next;
7183 static struct pic_chain * aof_pic_chain = NULL;
7189 struct pic_chain ** chainp;
7192 if (aof_pic_label == NULL_RTX)
7194 /* We mark this here and not in arm_add_gc_roots() to avoid
7195 polluting even more code with ifdefs, and because it never
7196 contains anything useful until we assign to it here. */
7197 ggc_add_rtx_root (&aof_pic_label, 1);
7198 /* This needs to persist throughout the compilation. */
7199 end_temporary_allocation ();
7200 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
7201 resume_temporary_allocation ();
7204 for (offset = 0, chainp = &aof_pic_chain; *chainp;
7205 offset += 4, chainp = &(*chainp)->next)
7206 if ((*chainp)->symname == XSTR (x, 0))
7207 return plus_constant (aof_pic_label, offset);
7209 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
7210 (*chainp)->next = NULL;
7211 (*chainp)->symname = XSTR (x, 0);
7212 return plus_constant (aof_pic_label, offset);
7216 aof_dump_pic_table (f)
7219 struct pic_chain * chain;
7221 if (aof_pic_chain == NULL)
7224 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
7225 PIC_OFFSET_TABLE_REGNUM,
7226 PIC_OFFSET_TABLE_REGNUM);
7227 fputs ("|x$adcons|\n", f);
7229 for (chain = aof_pic_chain; chain; chain = chain->next)
7231 fputs ("\tDCD\t", f);
7232 assemble_name (f, chain->symname);
7237 int arm_text_section_count = 1;
7242 static char buf[100];
7243 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
7244 arm_text_section_count++);
7246 strcat (buf, ", PIC, REENTRANT");
7250 static int arm_data_section_count = 1;
7255 static char buf[100];
7256 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
7260 /* The AOF assembler is religiously strict about declarations of
7261 imported and exported symbols, so that it is impossible to declare
7262 a function as imported near the beginning of the file, and then to
7263 export it later on. It is, however, possible to delay the decision
7264 until all the functions in the file have been compiled. To get
7265 around this, we maintain a list of the imports and exports, and
7266 delete from it any that are subsequently defined. At the end of
7267 compilation we spit the remainder of the list out before the END
7272 struct import * next;
7276 static struct import * imports_list = NULL;
7279 aof_add_import (name)
7282 struct import * new;
7284 for (new = imports_list; new; new = new->next)
7285 if (new->name == name)
7288 new = (struct import *) xmalloc (sizeof (struct import));
7289 new->next = imports_list;
7295 aof_delete_import (name)
7298 struct import ** old;
7300 for (old = &imports_list; *old; old = & (*old)->next)
7302 if ((*old)->name == name)
7304 *old = (*old)->next;
7310 int arm_main_function = 0;
7313 aof_dump_imports (f)
7316 /* The AOF assembler needs this to cause the startup code to be extracted
7317 from the library. Brining in __main causes the whole thing to work
7319 if (arm_main_function)
7322 fputs ("\tIMPORT __main\n", f);
7323 fputs ("\tDCD __main\n", f);
7326 /* Now dump the remaining imports. */
7327 while (imports_list)
7329 fprintf (f, "\tIMPORT\t");
7330 assemble_name (f, imports_list->name);
7332 imports_list = imports_list->next;
7335 #endif /* AOF_ASSEMBLER */