1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode;
56 typedef struct minipool_fixup Mfix;
58 /* In order to improve the layout of the prototypes below
59 some short type abbreviations are defined here. */
60 #define Hint HOST_WIDE_INT
61 #define Mmode enum machine_mode
62 #define Ulong unsigned long
63 #define Ccstar const char *
65 const char extra_reg_names1[][16] =
66 { "mv0", "mv1", "mv2", "mv3", "mv4", "mv5", "mv6", "mv7",
67 "mv8", "mv9", "mv10", "mv11", "mv12", "mv13", "mv14", "mv15"
69 #define extra_reg_names1 bogus1_regnames
71 const struct attribute_spec arm_attribute_table[];
73 /* Forward function declarations. */
74 static void arm_add_gc_roots PARAMS ((void));
75 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
76 static unsigned bit_count PARAMS ((Ulong));
77 static int arm_address_register_rtx_p PARAMS ((rtx, int));
78 static int arm_legitimate_index_p PARAMS ((enum machine_mode,
80 static int thumb_base_register_rtx_p PARAMS ((rtx,
83 inline static int thumb_index_register_rtx_p PARAMS ((rtx, int));
84 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
85 static int eliminate_lr2ip PARAMS ((rtx *));
86 static rtx emit_multi_reg_push PARAMS ((int));
87 static rtx emit_sfm PARAMS ((int, int));
89 static bool arm_assemble_integer PARAMS ((rtx, unsigned int, int));
91 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
92 static arm_cc get_arm_condition_code PARAMS ((rtx));
93 static void init_fpa_table PARAMS ((void));
94 static Hint int_log2 PARAMS ((Hint));
95 static rtx is_jump_table PARAMS ((rtx));
96 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
97 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
98 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
99 static Ccstar shift_op PARAMS ((rtx, Hint *));
100 static struct machine_function * arm_init_machine_status PARAMS ((void));
101 static int number_of_first_bit_set PARAMS ((int));
102 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
103 static void thumb_exit PARAMS ((FILE *, int, rtx));
104 static void thumb_pushpop PARAMS ((FILE *, int, int));
105 static Ccstar thumb_condition_code PARAMS ((rtx, int));
106 static rtx is_jump_table PARAMS ((rtx));
107 static Hint get_jump_table_size PARAMS ((rtx));
108 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
109 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
110 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
111 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
112 static void assign_minipool_offsets PARAMS ((Mfix *));
113 static void arm_print_value PARAMS ((FILE *, rtx));
114 static void dump_minipool PARAMS ((rtx));
115 static int arm_barrier_cost PARAMS ((rtx));
116 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
117 static void push_minipool_barrier PARAMS ((rtx, Hint));
118 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
119 static void note_invalid_constants PARAMS ((rtx, Hint));
120 static int current_file_function_operand PARAMS ((rtx));
121 static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void));
122 static Ulong arm_compute_save_reg_mask PARAMS ((void));
123 static Ulong arm_isr_value PARAMS ((tree));
124 static Ulong arm_compute_func_type PARAMS ((void));
125 static tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
126 static tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *));
127 static void arm_output_function_epilogue PARAMS ((FILE *, Hint));
128 static void arm_output_function_prologue PARAMS ((FILE *, Hint));
129 static void thumb_output_function_prologue PARAMS ((FILE *, Hint));
130 static int arm_comp_type_attributes PARAMS ((tree, tree));
131 static void arm_set_default_type_attributes PARAMS ((tree));
132 static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
133 static int count_insns_for_constant PARAMS ((HOST_WIDE_INT, int));
134 static int arm_get_strip_length PARAMS ((int));
135 static bool arm_function_ok_for_sibcall PARAMS ((tree, tree));
136 #ifdef OBJECT_FORMAT_ELF
137 static void arm_elf_asm_named_section PARAMS ((const char *, unsigned int));
140 static void arm_encode_section_info PARAMS ((tree, int));
143 static void aof_globalize_label PARAMS ((FILE *, const char *));
145 static void arm_internal_label PARAMS ((FILE *, const char *, unsigned long));
146 static void arm_output_mi_thunk PARAMS ((FILE *, tree,
148 HOST_WIDE_INT, tree));
149 static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code,
151 static bool arm_rtx_costs PARAMS ((rtx, int, int, int*));
152 static int arm_address_cost PARAMS ((rtx));
153 static int is_load_address PARAMS ((rtx));
154 static int is_cirrus_insn PARAMS ((rtx));
155 static void cirrus_reorg PARAMS ((rtx));
162 /* Initialize the GCC target structure. */
163 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
164 #undef TARGET_MERGE_DECL_ATTRIBUTES
165 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
168 #undef TARGET_ATTRIBUTE_TABLE
169 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
172 #undef TARGET_ASM_BYTE_OP
173 #define TARGET_ASM_BYTE_OP "\tDCB\t"
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
178 #undef TARGET_ASM_GLOBALIZE_LABEL
179 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
181 #undef TARGET_ASM_ALIGNED_SI_OP
182 #define TARGET_ASM_ALIGNED_SI_OP NULL
183 #undef TARGET_ASM_INTEGER
184 #define TARGET_ASM_INTEGER arm_assemble_integer
187 #undef TARGET_ASM_FUNCTION_PROLOGUE
188 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
190 #undef TARGET_ASM_FUNCTION_EPILOGUE
191 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
193 #undef TARGET_COMP_TYPE_ATTRIBUTES
194 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
196 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
197 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
199 #undef TARGET_SCHED_ADJUST_COST
200 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
202 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
206 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
209 #undef TARGET_STRIP_NAME_ENCODING
210 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
212 #undef TARGET_ASM_INTERNAL_LABEL
213 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
215 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
216 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
218 #undef TARGET_ASM_OUTPUT_MI_THUNK
219 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS arm_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST arm_address_cost
228 struct gcc_target targetm = TARGET_INITIALIZER;
230 /* Obstack for minipool constant handling. */
231 static struct obstack minipool_obstack;
232 static char * minipool_startobj;
234 /* The maximum number of insns skipped which
235 will be conditionalised if possible. */
236 static int max_insns_skipped = 5;
238 extern FILE * asm_out_file;
240 /* True if we are currently building a constant table. */
241 int making_const_table;
243 /* Define the information needed to generate branch insns. This is
244 stored from the compare operation. */
245 rtx arm_compare_op0, arm_compare_op1;
247 /* What type of floating point are we tuning for? */
248 enum floating_point_type arm_fpu;
250 /* What type of floating point instructions are available? */
251 enum floating_point_type arm_fpu_arch;
253 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
254 enum prog_mode_type arm_prgmode;
256 /* Set by the -mfp=... option. */
257 const char * target_fp_name = NULL;
259 /* Used to parse -mstructure_size_boundary command line option. */
260 const char * structure_size_string = NULL;
261 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
263 /* Bit values used to identify processor capabilities. */
264 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
265 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
266 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
267 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
268 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
269 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
270 #define FL_THUMB (1 << 6) /* Thumb aware */
271 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
272 #define FL_STRONG (1 << 8) /* StrongARM */
273 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
274 #define FL_XSCALE (1 << 10) /* XScale */
275 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
277 /* The bits in this mask specify which
278 instructions we are allowed to generate. */
279 static unsigned long insn_flags = 0;
281 /* The bits in this mask specify which instruction scheduling options should
282 be used. Note - there is an overlap with the FL_FAST_MULT. For some
283 hardware we want to be able to generate the multiply instructions, but to
284 tune as if they were not present in the architecture. */
285 static unsigned long tune_flags = 0;
287 /* The following are used in the arm.md file as equivalents to bits
288 in the above two flag variables. */
290 /* Nonzero if this is an "M" variant of the processor. */
291 int arm_fast_multiply = 0;
293 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
296 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
299 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
302 /* Nonzero if this chip can benefit from load scheduling. */
303 int arm_ld_sched = 0;
305 /* Nonzero if this chip is a StrongARM. */
306 int arm_is_strong = 0;
308 /* Nonzero if this chip is an XScale. */
309 int arm_is_xscale = 0;
311 /* Nonzero if this chip is an ARM6 or an ARM7. */
312 int arm_is_6_or_7 = 0;
314 /* Nonzero if this chip is a Cirrus/DSP. */
315 int arm_is_cirrus = 0;
317 /* Nonzero if generating Thumb instructions. */
320 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
321 must report the mode of the memory reference from PRINT_OPERAND to
322 PRINT_OPERAND_ADDRESS. */
323 enum machine_mode output_memory_reference_mode;
325 /* The register number to be used for the PIC offset register. */
326 const char * arm_pic_register_string = NULL;
327 int arm_pic_register = INVALID_REGNUM;
329 /* Set to 1 when a return insn is output, this means that the epilogue
331 int return_used_this_function;
333 /* Set to 1 after arm_reorg has started. Reset to start at the start of
334 the next function. */
335 static int after_arm_reorg = 0;
337 /* The maximum number of insns to be used when loading a constant. */
338 static int arm_constant_limit = 3;
340 /* For an explanation of these variables, see final_prescan_insn below. */
342 enum arm_cond_code arm_current_cc;
344 int arm_target_label;
346 /* The condition codes of the ARM, and the inverse function. */
347 static const char * const arm_condition_codes[] =
349 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
350 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
353 #define streq(string1, string2) (strcmp (string1, string2) == 0)
355 /* Initialization code. */
359 const char *const name;
360 const unsigned long flags;
363 /* Not all of these give usefully different compilation alternatives,
364 but there is no simple way of generalizing them. */
365 static const struct processors all_cores[] =
369 {"arm2", FL_CO_PROC | FL_MODE26 },
370 {"arm250", FL_CO_PROC | FL_MODE26 },
371 {"arm3", FL_CO_PROC | FL_MODE26 },
372 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
373 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
374 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
375 {"arm610", FL_MODE26 | FL_MODE32 },
376 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
377 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
378 /* arm7m doesn't exist on its own, but only with D, (and I), but
379 those don't alter the code, so arm7m is sometimes used. */
380 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
381 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
382 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
383 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
384 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
385 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
386 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
387 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
388 {"arm710", FL_MODE26 | FL_MODE32 },
389 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
390 {"arm720", FL_MODE26 | FL_MODE32 },
391 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
392 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
393 {"arm710c", FL_MODE26 | FL_MODE32 },
394 {"arm7100", FL_MODE26 | FL_MODE32 },
395 {"arm7500", FL_MODE26 | FL_MODE32 },
396 /* Doesn't have an external co-proc, but does have embedded fpu. */
397 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
398 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
399 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
400 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
401 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
402 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
403 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
404 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
405 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
406 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
407 {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
408 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
409 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
410 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
411 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
412 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
413 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
414 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
419 static const struct processors all_architectures[] =
421 /* ARM Architectures */
423 { "armv2", FL_CO_PROC | FL_MODE26 },
424 { "armv2a", FL_CO_PROC | FL_MODE26 },
425 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
426 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
427 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
428 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
429 implementations that support it, so we will leave it out for now. */
430 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
431 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
432 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
433 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
434 { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
438 /* This is a magic stucture. The 'string' field is magically filled in
439 with a pointer to the value specified by the user on the command line
440 assuming that the user has specified such a value. */
442 struct arm_cpu_select arm_select[] =
444 /* string name processors */
445 { NULL, "-mcpu=", all_cores },
446 { NULL, "-march=", all_architectures },
447 { NULL, "-mtune=", all_cores }
450 /* Return the number of bits set in VALUE. */
455 unsigned long count = 0;
460 value &= value - 1; /* Clear the least-significant set bit. */
466 /* Fix up any incompatible options that the user has specified.
467 This has now turned into a maze. */
469 arm_override_options ()
473 /* Set up the flags based on the cpu/architecture selected by the user. */
474 for (i = ARRAY_SIZE (arm_select); i--;)
476 struct arm_cpu_select * ptr = arm_select + i;
478 if (ptr->string != NULL && ptr->string[0] != '\0')
480 const struct processors * sel;
482 for (sel = ptr->processors; sel->name != NULL; sel++)
483 if (streq (ptr->string, sel->name))
486 tune_flags = sel->flags;
489 /* If we have been given an architecture and a processor
490 make sure that they are compatible. We only generate
491 a warning though, and we prefer the CPU over the
493 if (insn_flags != 0 && (insn_flags ^ sel->flags))
494 warning ("switch -mcpu=%s conflicts with -march= switch",
497 insn_flags = sel->flags;
503 if (sel->name == NULL)
504 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
508 /* If the user did not specify a processor, choose one for them. */
511 const struct processors * sel;
513 static const struct cpu_default
516 const char *const name;
520 { TARGET_CPU_arm2, "arm2" },
521 { TARGET_CPU_arm6, "arm6" },
522 { TARGET_CPU_arm610, "arm610" },
523 { TARGET_CPU_arm710, "arm710" },
524 { TARGET_CPU_arm7m, "arm7m" },
525 { TARGET_CPU_arm7500fe, "arm7500fe" },
526 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
527 { TARGET_CPU_arm8, "arm8" },
528 { TARGET_CPU_arm810, "arm810" },
529 { TARGET_CPU_arm9, "arm9" },
530 { TARGET_CPU_strongarm, "strongarm" },
531 { TARGET_CPU_xscale, "xscale" },
532 { TARGET_CPU_ep9312, "ep9312" },
533 { TARGET_CPU_generic, "arm" },
536 const struct cpu_default * def;
538 /* Find the default. */
539 for (def = cpu_defaults; def->name; def++)
540 if (def->cpu == TARGET_CPU_DEFAULT)
543 /* Make sure we found the default CPU. */
544 if (def->name == NULL)
547 /* Find the default CPU's flags. */
548 for (sel = all_cores; sel->name != NULL; sel++)
549 if (streq (def->name, sel->name))
552 if (sel->name == NULL)
555 insn_flags = sel->flags;
557 /* Now check to see if the user has specified some command line
558 switch that require certain abilities from the cpu. */
561 if (TARGET_INTERWORK || TARGET_THUMB)
563 sought |= (FL_THUMB | FL_MODE32);
565 /* Force apcs-32 to be used for interworking. */
566 target_flags |= ARM_FLAG_APCS_32;
568 /* There are no ARM processors that support both APCS-26 and
569 interworking. Therefore we force FL_MODE26 to be removed
570 from insn_flags here (if it was set), so that the search
571 below will always be able to find a compatible processor. */
572 insn_flags &= ~FL_MODE26;
574 else if (!TARGET_APCS_32)
577 if (sought != 0 && ((sought & insn_flags) != sought))
579 /* Try to locate a CPU type that supports all of the abilities
580 of the default CPU, plus the extra abilities requested by
582 for (sel = all_cores; sel->name != NULL; sel++)
583 if ((sel->flags & sought) == (sought | insn_flags))
586 if (sel->name == NULL)
588 unsigned current_bit_count = 0;
589 const struct processors * best_fit = NULL;
591 /* Ideally we would like to issue an error message here
592 saying that it was not possible to find a CPU compatible
593 with the default CPU, but which also supports the command
594 line options specified by the programmer, and so they
595 ought to use the -mcpu=<name> command line option to
596 override the default CPU type.
598 Unfortunately this does not work with multilibing. We
599 need to be able to support multilibs for -mapcs-26 and for
600 -mthumb-interwork and there is no CPU that can support both
601 options. Instead if we cannot find a cpu that has both the
602 characteristics of the default cpu and the given command line
603 options we scan the array again looking for a best match. */
604 for (sel = all_cores; sel->name != NULL; sel++)
605 if ((sel->flags & sought) == sought)
609 count = bit_count (sel->flags & insn_flags);
611 if (count >= current_bit_count)
614 current_bit_count = count;
618 if (best_fit == NULL)
624 insn_flags = sel->flags;
628 /* If tuning has not been specified, tune for whichever processor or
629 architecture has been selected. */
631 tune_flags = insn_flags;
633 /* Make sure that the processor choice does not conflict with any of the
634 other command line choices. */
635 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
637 /* If APCS-32 was not the default then it must have been set by the
638 user, so issue a warning message. If the user has specified
639 "-mapcs-32 -mcpu=arm2" then we loose here. */
640 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
641 warning ("target CPU does not support APCS-32" );
642 target_flags &= ~ARM_FLAG_APCS_32;
644 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
646 warning ("target CPU does not support APCS-26" );
647 target_flags |= ARM_FLAG_APCS_32;
650 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
652 warning ("target CPU does not support interworking" );
653 target_flags &= ~ARM_FLAG_INTERWORK;
656 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
658 warning ("target CPU does not support THUMB instructions");
659 target_flags &= ~ARM_FLAG_THUMB;
662 if (TARGET_APCS_FRAME && TARGET_THUMB)
664 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
665 target_flags &= ~ARM_FLAG_APCS_FRAME;
668 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
669 from here where no function is being compiled currently. */
670 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
672 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
674 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
675 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
677 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
678 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
680 /* If interworking is enabled then APCS-32 must be selected as well. */
681 if (TARGET_INTERWORK)
684 warning ("interworking forces APCS-32 to be used" );
685 target_flags |= ARM_FLAG_APCS_32;
688 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
690 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
691 target_flags |= ARM_FLAG_APCS_FRAME;
694 if (TARGET_POKE_FUNCTION_NAME)
695 target_flags |= ARM_FLAG_APCS_FRAME;
697 if (TARGET_APCS_REENT && flag_pic)
698 error ("-fpic and -mapcs-reent are incompatible");
700 if (TARGET_APCS_REENT)
701 warning ("APCS reentrant code not supported. Ignored");
703 /* If this target is normally configured to use APCS frames, warn if they
704 are turned off and debugging is turned on. */
706 && write_symbols != NO_DEBUG
707 && !TARGET_APCS_FRAME
708 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
709 warning ("-g with -mno-apcs-frame may not give sensible debugging");
711 /* If stack checking is disabled, we can use r10 as the PIC register,
712 which keeps r9 available. */
714 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
716 if (TARGET_APCS_FLOAT)
717 warning ("passing floating point arguments in fp regs not yet supported");
719 /* Initialize boolean versions of the flags, for use in the arm.md file. */
720 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
721 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
722 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
723 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
724 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
726 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
727 arm_is_strong = (tune_flags & FL_STRONG) != 0;
728 thumb_code = (TARGET_ARM == 0);
729 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
730 && !(tune_flags & FL_ARCH4))) != 0;
731 arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
737 /* Ignore -mhard-float if -mcpu=ep9312. */
738 if (TARGET_HARD_FLOAT)
739 target_flags ^= ARM_FLAG_SOFT_FLOAT;
742 /* Default value for floating point code... if no co-processor
743 bus, then schedule for emulated floating point. Otherwise,
744 assume the user has an FPA.
745 Note: this does not prevent use of floating point instructions,
746 -msoft-float does that. */
747 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
751 if (streq (target_fp_name, "2"))
752 arm_fpu_arch = FP_SOFT2;
753 else if (streq (target_fp_name, "3"))
754 arm_fpu_arch = FP_SOFT3;
756 error ("invalid floating point emulation option: -mfpe-%s",
760 arm_fpu_arch = FP_DEFAULT;
764 if (arm_fpu == FP_SOFT3)
766 else if (arm_fpu == FP_CIRRUS)
767 warning ("-mpfpe switch not supported by ep9312 target cpu - ignored.");
768 else if (arm_fpu != FP_HARD)
772 /* For arm2/3 there is no need to do any scheduling if there is only
773 a floating point emulator, or we are doing software floating-point. */
774 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
775 && (tune_flags & FL_MODE32) == 0)
776 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
778 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
780 if (structure_size_string != NULL)
782 int size = strtol (structure_size_string, NULL, 0);
784 if (size == 8 || size == 32)
785 arm_structure_size_boundary = size;
787 warning ("structure size boundary can only be set to 8 or 32");
790 if (arm_pic_register_string != NULL)
792 int pic_register = decode_reg_name (arm_pic_register_string);
795 warning ("-mpic-register= is useless without -fpic");
797 /* Prevent the user from choosing an obviously stupid PIC register. */
798 else if (pic_register < 0 || call_used_regs[pic_register]
799 || pic_register == HARD_FRAME_POINTER_REGNUM
800 || pic_register == STACK_POINTER_REGNUM
801 || pic_register >= PC_REGNUM)
802 error ("unable to use '%s' for PIC register", arm_pic_register_string);
804 arm_pic_register = pic_register;
807 if (TARGET_THUMB && flag_schedule_insns)
809 /* Don't warn since it's on by default in -O2. */
810 flag_schedule_insns = 0;
813 /* If optimizing for space, don't synthesize constants.
814 For processors with load scheduling, it never costs more than 2 cycles
815 to load a constant, and the load scheduler may well reduce that to 1. */
816 if (optimize_size || (tune_flags & FL_LDSCHED))
817 arm_constant_limit = 1;
820 arm_constant_limit = 2;
822 /* If optimizing for size, bump the number of instructions that we
823 are prepared to conditionally execute (even on a StrongARM).
824 Otherwise for the StrongARM, which has early execution of branches,
825 a sequence that is worth skipping is shorter. */
827 max_insns_skipped = 6;
828 else if (arm_is_strong)
829 max_insns_skipped = 3;
831 /* Register global variables with the garbage collector. */
838 gcc_obstack_init(&minipool_obstack);
839 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
842 /* A table of known ARM exception types.
843 For use with the interrupt function attribute. */
847 const char *const arg;
848 const unsigned long return_value;
852 static const isr_attribute_arg isr_attribute_args [] =
854 { "IRQ", ARM_FT_ISR },
855 { "irq", ARM_FT_ISR },
856 { "FIQ", ARM_FT_FIQ },
857 { "fiq", ARM_FT_FIQ },
858 { "ABORT", ARM_FT_ISR },
859 { "abort", ARM_FT_ISR },
860 { "ABORT", ARM_FT_ISR },
861 { "abort", ARM_FT_ISR },
862 { "UNDEF", ARM_FT_EXCEPTION },
863 { "undef", ARM_FT_EXCEPTION },
864 { "SWI", ARM_FT_EXCEPTION },
865 { "swi", ARM_FT_EXCEPTION },
866 { NULL, ARM_FT_NORMAL }
869 /* Returns the (interrupt) function type of the current
870 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
873 arm_isr_value (argument)
876 const isr_attribute_arg * ptr;
879 /* No argument - default to IRQ. */
880 if (argument == NULL_TREE)
883 /* Get the value of the argument. */
884 if (TREE_VALUE (argument) == NULL_TREE
885 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
886 return ARM_FT_UNKNOWN;
888 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
890 /* Check it against the list of known arguments. */
891 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
892 if (streq (arg, ptr->arg))
893 return ptr->return_value;
895 /* An unrecognized interrupt type. */
896 return ARM_FT_UNKNOWN;
899 /* Computes the type of the current function. */
902 arm_compute_func_type ()
904 unsigned long type = ARM_FT_UNKNOWN;
908 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
911 /* Decide if the current function is volatile. Such functions
912 never return, and many memory cycles can be saved by not storing
913 register values that will never be needed again. This optimization
914 was added to speed up context switching in a kernel application. */
916 && current_function_nothrow
917 && TREE_THIS_VOLATILE (current_function_decl))
918 type |= ARM_FT_VOLATILE;
920 if (current_function_needs_context)
921 type |= ARM_FT_NESTED;
923 attr = DECL_ATTRIBUTES (current_function_decl);
925 a = lookup_attribute ("naked", attr);
927 type |= ARM_FT_NAKED;
929 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
930 type |= ARM_FT_EXCEPTION_HANDLER;
933 a = lookup_attribute ("isr", attr);
935 a = lookup_attribute ("interrupt", attr);
938 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
940 type |= arm_isr_value (TREE_VALUE (a));
946 /* Returns the type of the current function. */
949 arm_current_func_type ()
951 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
952 cfun->machine->func_type = arm_compute_func_type ();
954 return cfun->machine->func_type;
957 /* Return 1 if it is possible to return using a single instruction. */
960 use_return_insn (iscond)
964 unsigned int func_type;
965 unsigned long saved_int_regs;
967 /* Never use a return instruction before reload has run. */
968 if (!reload_completed)
971 func_type = arm_current_func_type ();
973 /* Naked functions and volatile functions need special
975 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
978 /* So do interrupt functions that use the frame pointer. */
979 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
982 /* As do variadic functions. */
983 if (current_function_pretend_args_size
984 || cfun->machine->uses_anonymous_args
985 /* Of if the function calls __builtin_eh_return () */
986 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
987 /* Or if there is no frame pointer and there is a stack adjustment. */
988 || ((arm_get_frame_size () + current_function_outgoing_args_size != 0)
989 && !frame_pointer_needed))
992 saved_int_regs = arm_compute_save_reg_mask ();
994 /* Can't be done if interworking with Thumb, and any registers have been
996 if (TARGET_INTERWORK && saved_int_regs != 0)
999 /* On StrongARM, conditional returns are expensive if they aren't
1000 taken and multiple registers have been stacked. */
1001 if (iscond && arm_is_strong)
1003 /* Conditional return when just the LR is stored is a simple
1004 conditional-load instruction, that's not expensive. */
1005 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1008 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1012 /* If there are saved registers but the LR isn't saved, then we need
1013 two instructions for the return. */
1014 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1017 /* Can't be done if any of the FPU regs are pushed,
1018 since this also requires an insn. */
1019 if (TARGET_HARD_FLOAT)
1020 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
1021 if (regs_ever_live[regno] && !call_used_regs[regno])
1027 /* Return TRUE if int I is a valid immediate ARM constant. */
1030 const_ok_for_arm (i)
1033 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1035 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1036 be all zero, or all one. */
1037 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1038 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1039 != ((~(unsigned HOST_WIDE_INT) 0)
1040 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1043 /* Fast return for 0 and powers of 2 */
1044 if ((i & (i - 1)) == 0)
1049 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1052 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1053 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1055 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1060 /* Return true if I is a valid constant for the operation CODE. */
1062 const_ok_for_op (i, code)
1066 if (const_ok_for_arm (i))
1072 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1074 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1080 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1087 /* Emit a sequence of insns to handle a large constant.
1088 CODE is the code of the operation required, it can be any of SET, PLUS,
1089 IOR, AND, XOR, MINUS;
1090 MODE is the mode in which the operation is being performed;
1091 VAL is the integer to operate on;
1092 SOURCE is the other operand (a register, or a null-pointer for SET);
1093 SUBTARGETS means it is safe to create scratch registers if that will
1094 either produce a simpler sequence, or we will want to cse the values.
1095 Return value is the number of insns emitted. */
1098 arm_split_constant (code, mode, val, target, source, subtargets)
1100 enum machine_mode mode;
1106 if (subtargets || code == SET
1107 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1108 && REGNO (target) != REGNO (source)))
1110 /* After arm_reorg has been called, we can't fix up expensive
1111 constants by pushing them into memory so we must synthesize
1112 them in-line, regardless of the cost. This is only likely to
1113 be more costly on chips that have load delay slots and we are
1114 compiling without running the scheduler (so no splitting
1115 occurred before the final instruction emission).
1117 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1119 if (!after_arm_reorg
1120 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1121 > arm_constant_limit + (code != SET)))
1125 /* Currently SET is the only monadic value for CODE, all
1126 the rest are diadic. */
1127 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1132 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1134 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1135 /* For MINUS, the value is subtracted from, since we never
1136 have subtraction of a constant. */
1138 emit_insn (gen_rtx_SET (VOIDmode, target,
1139 gen_rtx_MINUS (mode, temp, source)));
1141 emit_insn (gen_rtx_SET (VOIDmode, target,
1142 gen_rtx (code, mode, source, temp)));
1148 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1152 count_insns_for_constant (remainder, i)
1153 HOST_WIDE_INT remainder;
1156 HOST_WIDE_INT temp1;
1164 if (remainder & (3 << (i - 2)))
1169 temp1 = remainder & ((0x0ff << end)
1170 | ((i < end) ? (0xff >> (32 - end)) : 0));
1171 remainder &= ~temp1;
1176 } while (remainder);
1180 /* As above, but extra parameter GENERATE which, if clear, suppresses
1184 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1186 enum machine_mode mode;
1195 int can_negate_initial = 0;
1198 int num_bits_set = 0;
1199 int set_sign_bit_copies = 0;
1200 int clear_sign_bit_copies = 0;
1201 int clear_zero_bit_copies = 0;
1202 int set_zero_bit_copies = 0;
1204 unsigned HOST_WIDE_INT temp1, temp2;
1205 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1207 /* Find out which operations are safe for a given CODE. Also do a quick
1208 check for degenerate cases; these can occur when DImode operations
1220 can_negate_initial = 1;
1224 if (remainder == 0xffffffff)
1227 emit_insn (gen_rtx_SET (VOIDmode, target,
1228 GEN_INT (ARM_SIGN_EXTEND (val))));
1233 if (reload_completed && rtx_equal_p (target, source))
1236 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1245 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1248 if (remainder == 0xffffffff)
1250 if (reload_completed && rtx_equal_p (target, source))
1253 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1262 if (reload_completed && rtx_equal_p (target, source))
1265 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1268 if (remainder == 0xffffffff)
1271 emit_insn (gen_rtx_SET (VOIDmode, target,
1272 gen_rtx_NOT (mode, source)));
1276 /* We don't know how to handle this yet below. */
1280 /* We treat MINUS as (val - source), since (source - val) is always
1281 passed as (source + (-val)). */
1285 emit_insn (gen_rtx_SET (VOIDmode, target,
1286 gen_rtx_NEG (mode, source)));
1289 if (const_ok_for_arm (val))
1292 emit_insn (gen_rtx_SET (VOIDmode, target,
1293 gen_rtx_MINUS (mode, GEN_INT (val),
1305 /* If we can do it in one insn get out quickly. */
1306 if (const_ok_for_arm (val)
1307 || (can_negate_initial && const_ok_for_arm (-val))
1308 || (can_invert && const_ok_for_arm (~val)))
1311 emit_insn (gen_rtx_SET (VOIDmode, target,
1312 (source ? gen_rtx (code, mode, source,
1318 /* Calculate a few attributes that may be useful for specific
1320 for (i = 31; i >= 0; i--)
1322 if ((remainder & (1 << i)) == 0)
1323 clear_sign_bit_copies++;
1328 for (i = 31; i >= 0; i--)
1330 if ((remainder & (1 << i)) != 0)
1331 set_sign_bit_copies++;
1336 for (i = 0; i <= 31; i++)
1338 if ((remainder & (1 << i)) == 0)
1339 clear_zero_bit_copies++;
1344 for (i = 0; i <= 31; i++)
1346 if ((remainder & (1 << i)) != 0)
1347 set_zero_bit_copies++;
1355 /* See if we can do this by sign_extending a constant that is known
1356 to be negative. This is a good, way of doing it, since the shift
1357 may well merge into a subsequent insn. */
1358 if (set_sign_bit_copies > 1)
1360 if (const_ok_for_arm
1361 (temp1 = ARM_SIGN_EXTEND (remainder
1362 << (set_sign_bit_copies - 1))))
1366 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1367 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1369 emit_insn (gen_ashrsi3 (target, new_src,
1370 GEN_INT (set_sign_bit_copies - 1)));
1374 /* For an inverted constant, we will need to set the low bits,
1375 these will be shifted out of harm's way. */
1376 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1377 if (const_ok_for_arm (~temp1))
1381 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1382 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1384 emit_insn (gen_ashrsi3 (target, new_src,
1385 GEN_INT (set_sign_bit_copies - 1)));
1391 /* See if we can generate this by setting the bottom (or the top)
1392 16 bits, and then shifting these into the other half of the
1393 word. We only look for the simplest cases, to do more would cost
1394 too much. Be careful, however, not to generate this when the
1395 alternative would take fewer insns. */
1396 if (val & 0xffff0000)
1398 temp1 = remainder & 0xffff0000;
1399 temp2 = remainder & 0x0000ffff;
1401 /* Overlaps outside this range are best done using other methods. */
1402 for (i = 9; i < 24; i++)
1404 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1405 && !const_ok_for_arm (temp2))
1407 rtx new_src = (subtargets
1408 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1410 insns = arm_gen_constant (code, mode, temp2, new_src,
1411 source, subtargets, generate);
1414 emit_insn (gen_rtx_SET
1417 gen_rtx_ASHIFT (mode, source,
1424 /* Don't duplicate cases already considered. */
1425 for (i = 17; i < 24; i++)
1427 if (((temp1 | (temp1 >> i)) == remainder)
1428 && !const_ok_for_arm (temp1))
1430 rtx new_src = (subtargets
1431 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1433 insns = arm_gen_constant (code, mode, temp1, new_src,
1434 source, subtargets, generate);
1438 (gen_rtx_SET (VOIDmode, target,
1441 gen_rtx_LSHIFTRT (mode, source,
1452 /* If we have IOR or XOR, and the constant can be loaded in a
1453 single instruction, and we can find a temporary to put it in,
1454 then this can be done in two instructions instead of 3-4. */
1456 /* TARGET can't be NULL if SUBTARGETS is 0 */
1457 || (reload_completed && !reg_mentioned_p (target, source)))
1459 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1463 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1465 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1466 emit_insn (gen_rtx_SET (VOIDmode, target,
1467 gen_rtx (code, mode, source, sub)));
1476 if (set_sign_bit_copies > 8
1477 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1481 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1482 rtx shift = GEN_INT (set_sign_bit_copies);
1484 emit_insn (gen_rtx_SET (VOIDmode, sub,
1486 gen_rtx_ASHIFT (mode,
1489 emit_insn (gen_rtx_SET (VOIDmode, target,
1491 gen_rtx_LSHIFTRT (mode, sub,
1497 if (set_zero_bit_copies > 8
1498 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1502 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1503 rtx shift = GEN_INT (set_zero_bit_copies);
1505 emit_insn (gen_rtx_SET (VOIDmode, sub,
1507 gen_rtx_LSHIFTRT (mode,
1510 emit_insn (gen_rtx_SET (VOIDmode, target,
1512 gen_rtx_ASHIFT (mode, sub,
1518 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1522 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1523 emit_insn (gen_rtx_SET (VOIDmode, sub,
1524 gen_rtx_NOT (mode, source)));
1527 sub = gen_reg_rtx (mode);
1528 emit_insn (gen_rtx_SET (VOIDmode, sub,
1529 gen_rtx_AND (mode, source,
1531 emit_insn (gen_rtx_SET (VOIDmode, target,
1532 gen_rtx_NOT (mode, sub)));
1539 /* See if two shifts will do 2 or more insn's worth of work. */
1540 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1542 HOST_WIDE_INT shift_mask = ((0xffffffff
1543 << (32 - clear_sign_bit_copies))
1546 if ((remainder | shift_mask) != 0xffffffff)
1550 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1551 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1552 new_src, source, subtargets, 1);
1557 rtx targ = subtargets ? NULL_RTX : target;
1558 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1559 targ, source, subtargets, 0);
1565 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1566 rtx shift = GEN_INT (clear_sign_bit_copies);
1568 emit_insn (gen_ashlsi3 (new_src, source, shift));
1569 emit_insn (gen_lshrsi3 (target, new_src, shift));
1575 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1577 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1579 if ((remainder | shift_mask) != 0xffffffff)
1583 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1585 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1586 new_src, source, subtargets, 1);
1591 rtx targ = subtargets ? NULL_RTX : target;
1593 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1594 targ, source, subtargets, 0);
1600 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1601 rtx shift = GEN_INT (clear_zero_bit_copies);
1603 emit_insn (gen_lshrsi3 (new_src, source, shift));
1604 emit_insn (gen_ashlsi3 (target, new_src, shift));
1616 for (i = 0; i < 32; i++)
1617 if (remainder & (1 << i))
1620 if (code == AND || (can_invert && num_bits_set > 16))
1621 remainder = (~remainder) & 0xffffffff;
1622 else if (code == PLUS && num_bits_set > 16)
1623 remainder = (-remainder) & 0xffffffff;
1630 /* Now try and find a way of doing the job in either two or three
1632 We start by looking for the largest block of zeros that are aligned on
1633 a 2-bit boundary, we then fill up the temps, wrapping around to the
1634 top of the word when we drop off the bottom.
1635 In the worst case this code should produce no more than four insns. */
1638 int best_consecutive_zeros = 0;
1640 for (i = 0; i < 32; i += 2)
1642 int consecutive_zeros = 0;
1644 if (!(remainder & (3 << i)))
1646 while ((i < 32) && !(remainder & (3 << i)))
1648 consecutive_zeros += 2;
1651 if (consecutive_zeros > best_consecutive_zeros)
1653 best_consecutive_zeros = consecutive_zeros;
1654 best_start = i - consecutive_zeros;
1660 /* So long as it won't require any more insns to do so, it's
1661 desirable to emit a small constant (in bits 0...9) in the last
1662 insn. This way there is more chance that it can be combined with
1663 a later addressing insn to form a pre-indexed load or store
1664 operation. Consider:
1666 *((volatile int *)0xe0000100) = 1;
1667 *((volatile int *)0xe0000110) = 2;
1669 We want this to wind up as:
1673 str rB, [rA, #0x100]
1675 str rB, [rA, #0x110]
1677 rather than having to synthesize both large constants from scratch.
1679 Therefore, we calculate how many insns would be required to emit
1680 the constant starting from `best_start', and also starting from
1681 zero (ie with bit 31 first to be output). If `best_start' doesn't
1682 yield a shorter sequence, we may as well use zero. */
1684 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1685 && (count_insns_for_constant (remainder, 0) <=
1686 count_insns_for_constant (remainder, best_start)))
1689 /* Now start emitting the insns. */
1697 if (remainder & (3 << (i - 2)))
1702 temp1 = remainder & ((0x0ff << end)
1703 | ((i < end) ? (0xff >> (32 - end)) : 0));
1704 remainder &= ~temp1;
1708 rtx new_src, temp1_rtx;
1710 if (code == SET || code == MINUS)
1712 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1713 if (can_invert && code != MINUS)
1718 if (remainder && subtargets)
1719 new_src = gen_reg_rtx (mode);
1724 else if (can_negate)
1728 temp1 = trunc_int_for_mode (temp1, mode);
1729 temp1_rtx = GEN_INT (temp1);
1733 else if (code == MINUS)
1734 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1736 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1738 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1747 else if (code == MINUS)
1761 /* Canonicalize a comparison so that we are more likely to recognize it.
1762 This can be done for a few constant compares, where we can make the
1763 immediate value easier to load. */
1766 arm_canonicalize_comparison (code, op1)
1770 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1780 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1781 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1783 *op1 = GEN_INT (i + 1);
1784 return code == GT ? GE : LT;
1790 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1791 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1793 *op1 = GEN_INT (i - 1);
1794 return code == GE ? GT : LE;
1800 if (i != ~((unsigned HOST_WIDE_INT) 0)
1801 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1803 *op1 = GEN_INT (i + 1);
1804 return code == GTU ? GEU : LTU;
1811 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1813 *op1 = GEN_INT (i - 1);
1814 return code == GEU ? GTU : LEU;
1825 /* Decide whether a type should be returned in memory (true)
1826 or in a register (false). This is called by the macro
1827 RETURN_IN_MEMORY. */
1830 arm_return_in_memory (type)
1835 if (!AGGREGATE_TYPE_P (type))
1836 /* All simple types are returned in registers. */
1839 size = int_size_in_bytes (type);
1843 /* ATPCS returns aggregate types in memory only if they are
1844 larger than a word (or are variable size). */
1845 return (size < 0 || size > UNITS_PER_WORD);
1848 /* For the arm-wince targets we choose to be compatible with Microsoft's
1849 ARM and Thumb compilers, which always return aggregates in memory. */
1851 /* All structures/unions bigger than one word are returned in memory.
1852 Also catch the case where int_size_in_bytes returns -1. In this case
1853 the aggregate is either huge or of variable size, and in either case
1854 we will want to return it via memory and not in a register. */
1855 if (size < 0 || size > UNITS_PER_WORD)
1858 if (TREE_CODE (type) == RECORD_TYPE)
1862 /* For a struct the APCS says that we only return in a register
1863 if the type is 'integer like' and every addressable element
1864 has an offset of zero. For practical purposes this means
1865 that the structure can have at most one non bit-field element
1866 and that this element must be the first one in the structure. */
1868 /* Find the first field, ignoring non FIELD_DECL things which will
1869 have been created by C++. */
1870 for (field = TYPE_FIELDS (type);
1871 field && TREE_CODE (field) != FIELD_DECL;
1872 field = TREE_CHAIN (field))
1876 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1878 /* Check that the first field is valid for returning in a register. */
1880 /* ... Floats are not allowed */
1881 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1884 /* ... Aggregates that are not themselves valid for returning in
1885 a register are not allowed. */
1886 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1889 /* Now check the remaining fields, if any. Only bitfields are allowed,
1890 since they are not addressable. */
1891 for (field = TREE_CHAIN (field);
1893 field = TREE_CHAIN (field))
1895 if (TREE_CODE (field) != FIELD_DECL)
1898 if (!DECL_BIT_FIELD_TYPE (field))
1905 if (TREE_CODE (type) == UNION_TYPE)
1909 /* Unions can be returned in registers if every element is
1910 integral, or can be returned in an integer register. */
1911 for (field = TYPE_FIELDS (type);
1913 field = TREE_CHAIN (field))
1915 if (TREE_CODE (field) != FIELD_DECL)
1918 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1921 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1927 #endif /* not ARM_WINCE */
1929 /* Return all other types in memory. */
1933 /* Indicate whether or not words of a double are in big-endian order. */
1936 arm_float_words_big_endian ()
1941 /* For FPA, float words are always big-endian. For VFP, floats words
1942 follow the memory system mode. */
1944 if (TARGET_HARD_FLOAT)
1946 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1951 return (TARGET_BIG_END ? 1 : 0);
1956 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1957 for a call to a function whose data type is FNTYPE.
1958 For a library call, FNTYPE is NULL. */
1960 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1961 CUMULATIVE_ARGS * pcum;
1963 rtx libname ATTRIBUTE_UNUSED;
1964 int indirect ATTRIBUTE_UNUSED;
1966 /* On the ARM, the offset starts at 0. */
1967 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1969 pcum->call_cookie = CALL_NORMAL;
1971 if (TARGET_LONG_CALLS)
1972 pcum->call_cookie = CALL_LONG;
1974 /* Check for long call/short call attributes. The attributes
1975 override any command line option. */
1978 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1979 pcum->call_cookie = CALL_SHORT;
1980 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1981 pcum->call_cookie = CALL_LONG;
1985 /* Determine where to put an argument to a function.
1986 Value is zero to push the argument on the stack,
1987 or a hard register in which to store the argument.
1989 MODE is the argument's machine mode.
1990 TYPE is the data type of the argument (as a tree).
1991 This is null for libcalls where that information may
1993 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1994 the preceding args and about the function being called.
1995 NAMED is nonzero if this argument is a named parameter
1996 (otherwise it is an extra parameter matching an ellipsis). */
1999 arm_function_arg (pcum, mode, type, named)
2000 CUMULATIVE_ARGS * pcum;
2001 enum machine_mode mode;
2002 tree type ATTRIBUTE_UNUSED;
2005 if (mode == VOIDmode)
2006 /* Compute operand 2 of the call insn. */
2007 return GEN_INT (pcum->call_cookie);
2009 if (!named || pcum->nregs >= NUM_ARG_REGS)
2012 return gen_rtx_REG (mode, pcum->nregs);
2015 /* Variable sized types are passed by reference. This is a GCC
2016 extension to the ARM ABI. */
2019 arm_function_arg_pass_by_reference (cum, mode, type, named)
2020 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
2021 enum machine_mode mode ATTRIBUTE_UNUSED;
2023 int named ATTRIBUTE_UNUSED;
2025 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2028 /* Implement va_arg. */
2031 arm_va_arg (valist, type)
2034 /* Variable sized types are passed by reference. */
2035 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2037 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2038 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2041 return std_expand_builtin_va_arg (valist, type);
2044 /* Encode the current state of the #pragma [no_]long_calls. */
2047 OFF, /* No #pramgma [no_]long_calls is in effect. */
2048 LONG, /* #pragma long_calls is in effect. */
2049 SHORT /* #pragma no_long_calls is in effect. */
2052 static arm_pragma_enum arm_pragma_long_calls = OFF;
2055 arm_pr_long_calls (pfile)
2056 struct cpp_reader * pfile ATTRIBUTE_UNUSED;
2058 arm_pragma_long_calls = LONG;
2062 arm_pr_no_long_calls (pfile)
2063 struct cpp_reader * pfile ATTRIBUTE_UNUSED;
2065 arm_pragma_long_calls = SHORT;
2069 arm_pr_long_calls_off (pfile)
2070 struct cpp_reader * pfile ATTRIBUTE_UNUSED;
2072 arm_pragma_long_calls = OFF;
2075 /* Table of machine attributes. */
2076 const struct attribute_spec arm_attribute_table[] =
2078 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2079 /* Function calls made to this symbol must be done indirectly, because
2080 it may lie outside of the 26 bit addressing range of a normal function
2082 { "long_call", 0, 0, false, true, true, NULL },
2083 /* Whereas these functions are always known to reside within the 26 bit
2084 addressing range. */
2085 { "short_call", 0, 0, false, true, true, NULL },
2086 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2087 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2088 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2089 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2091 /* ARM/PE has three new attributes:
2093 dllexport - for exporting a function/variable that will live in a dll
2094 dllimport - for importing a function/variable from a dll
2096 Microsoft allows multiple declspecs in one __declspec, separating
2097 them with spaces. We do NOT support this. Instead, use __declspec
2100 { "dllimport", 0, 0, true, false, false, NULL },
2101 { "dllexport", 0, 0, true, false, false, NULL },
2102 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2104 { NULL, 0, 0, false, false, false, NULL }
2107 /* Handle an attribute requiring a FUNCTION_DECL;
2108 arguments as in struct attribute_spec.handler. */
2111 arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
2114 tree args ATTRIBUTE_UNUSED;
2115 int flags ATTRIBUTE_UNUSED;
2116 bool * no_add_attrs;
2118 if (TREE_CODE (*node) != FUNCTION_DECL)
2120 warning ("`%s' attribute only applies to functions",
2121 IDENTIFIER_POINTER (name));
2122 *no_add_attrs = true;
2128 /* Handle an "interrupt" or "isr" attribute;
2129 arguments as in struct attribute_spec.handler. */
2132 arm_handle_isr_attribute (node, name, args, flags, no_add_attrs)
2137 bool * no_add_attrs;
2141 if (TREE_CODE (*node) != FUNCTION_DECL)
2143 warning ("`%s' attribute only applies to functions",
2144 IDENTIFIER_POINTER (name));
2145 *no_add_attrs = true;
2147 /* FIXME: the argument if any is checked for type attributes;
2148 should it be checked for decl ones? */
2152 if (TREE_CODE (*node) == FUNCTION_TYPE
2153 || TREE_CODE (*node) == METHOD_TYPE)
2155 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2157 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2158 *no_add_attrs = true;
2161 else if (TREE_CODE (*node) == POINTER_TYPE
2162 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2163 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2164 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2166 *node = build_type_copy (*node);
2167 TREE_TYPE (*node) = build_type_attribute_variant
2169 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2170 *no_add_attrs = true;
2174 /* Possibly pass this attribute on from the type to a decl. */
2175 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2176 | (int) ATTR_FLAG_FUNCTION_NEXT
2177 | (int) ATTR_FLAG_ARRAY_NEXT))
2179 *no_add_attrs = true;
2180 return tree_cons (name, args, NULL_TREE);
2184 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2192 /* Return 0 if the attributes for two types are incompatible, 1 if they
2193 are compatible, and 2 if they are nearly compatible (which causes a
2194 warning to be generated). */
2197 arm_comp_type_attributes (type1, type2)
2203 /* Check for mismatch of non-default calling convention. */
2204 if (TREE_CODE (type1) != FUNCTION_TYPE)
2207 /* Check for mismatched call attributes. */
2208 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2209 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2210 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2211 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2213 /* Only bother to check if an attribute is defined. */
2214 if (l1 | l2 | s1 | s2)
2216 /* If one type has an attribute, the other must have the same attribute. */
2217 if ((l1 != l2) || (s1 != s2))
2220 /* Disallow mixed attributes. */
2221 if ((l1 & s2) || (l2 & s1))
2225 /* Check for mismatched ISR attribute. */
2226 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2228 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2229 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2231 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2238 /* Encode long_call or short_call attribute by prefixing
2239 symbol name in DECL with a special character FLAG. */
2242 arm_encode_call_attribute (decl, flag)
2246 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2247 int len = strlen (str);
2250 /* Do not allow weak functions to be treated as short call. */
2251 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2254 newstr = alloca (len + 2);
2256 strcpy (newstr + 1, str);
2258 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2259 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2262 /* Assigns default attributes to newly defined type. This is used to
2263 set short_call/long_call attributes for function types of
2264 functions defined inside corresponding #pragma scopes. */
2267 arm_set_default_type_attributes (type)
2270 /* Add __attribute__ ((long_call)) to all functions, when
2271 inside #pragma long_calls or __attribute__ ((short_call)),
2272 when inside #pragma no_long_calls. */
2273 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2275 tree type_attr_list, attr_name;
2276 type_attr_list = TYPE_ATTRIBUTES (type);
2278 if (arm_pragma_long_calls == LONG)
2279 attr_name = get_identifier ("long_call");
2280 else if (arm_pragma_long_calls == SHORT)
2281 attr_name = get_identifier ("short_call");
2285 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2286 TYPE_ATTRIBUTES (type) = type_attr_list;
2290 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2291 defined within the current compilation unit. If this cannot be
2292 determined, then 0 is returned. */
2295 current_file_function_operand (sym_ref)
2298 /* This is a bit of a fib. A function will have a short call flag
2299 applied to its name if it has the short call attribute, or it has
2300 already been defined within the current compilation unit. */
2301 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2304 /* The current function is always defined within the current compilation
2305 unit. if it s a weak definition however, then this may not be the real
2306 definition of the function, and so we have to say no. */
2307 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2308 && !DECL_WEAK (current_function_decl))
2311 /* We cannot make the determination - default to returning 0. */
2315 /* Return nonzero if a 32 bit "long_call" should be generated for
2316 this call. We generate a long_call if the function:
2318 a. has an __attribute__((long call))
2319 or b. is within the scope of a #pragma long_calls
2320 or c. the -mlong-calls command line switch has been specified
2322 However we do not generate a long call if the function:
2324 d. has an __attribute__ ((short_call))
2325 or e. is inside the scope of a #pragma no_long_calls
2326 or f. has an __attribute__ ((section))
2327 or g. is defined within the current compilation unit.
2329 This function will be called by C fragments contained in the machine
2330 description file. CALL_REF and CALL_COOKIE correspond to the matched
2331 rtl operands. CALL_SYMBOL is used to distinguish between
2332 two different callers of the function. It is set to 1 in the
2333 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2334 and "call_value" patterns. This is because of the difference in the
2335 SYM_REFs passed by these patterns. */
2338 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2345 if (GET_CODE (sym_ref) != MEM)
2348 sym_ref = XEXP (sym_ref, 0);
2351 if (GET_CODE (sym_ref) != SYMBOL_REF)
2354 if (call_cookie & CALL_SHORT)
2357 if (TARGET_LONG_CALLS && flag_function_sections)
2360 if (current_file_function_operand (sym_ref))
2363 return (call_cookie & CALL_LONG)
2364 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2365 || TARGET_LONG_CALLS;
2368 /* Return nonzero if it is ok to make a tail-call to DECL. */
2371 arm_function_ok_for_sibcall (decl, exp)
2373 tree exp ATTRIBUTE_UNUSED;
2375 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2377 /* Never tailcall something for which we have no decl, or if we
2378 are in Thumb mode. */
2379 if (decl == NULL || TARGET_THUMB)
2382 /* Get the calling method. */
2383 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2384 call_type = CALL_SHORT;
2385 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2386 call_type = CALL_LONG;
2388 /* Cannot tail-call to long calls, since these are out of range of
2389 a branch instruction. However, if not compiling PIC, we know
2390 we can reach the symbol if it is in this compilation unit. */
2391 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2394 /* If we are interworking and the function is not declared static
2395 then we can't tail-call it unless we know that it exists in this
2396 compilation unit (since it might be a Thumb routine). */
2397 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2400 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2401 if (IS_INTERRUPT (arm_current_func_type ()))
2404 /* Everything else is ok. */
2409 /* Addressing mode support functions. */
2411 /* Return non-zero if X is a legitimate immediate operand when compiling
2414 legitimate_pic_operand_p (x)
2419 && (GET_CODE (x) == SYMBOL_REF
2420 || (GET_CODE (x) == CONST
2421 && GET_CODE (XEXP (x, 0)) == PLUS
2422 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2429 legitimize_pic_address (orig, mode, reg)
2431 enum machine_mode mode;
2434 if (GET_CODE (orig) == SYMBOL_REF
2435 || GET_CODE (orig) == LABEL_REF)
2437 #ifndef AOF_ASSEMBLER
2438 rtx pic_ref, address;
2448 reg = gen_reg_rtx (Pmode);
2453 #ifdef AOF_ASSEMBLER
2454 /* The AOF assembler can generate relocations for these directly, and
2455 understands that the PIC register has to be added into the offset. */
2456 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2459 address = gen_reg_rtx (Pmode);
2464 emit_insn (gen_pic_load_addr_arm (address, orig));
2466 emit_insn (gen_pic_load_addr_thumb (address, orig));
2468 if ((GET_CODE (orig) == LABEL_REF
2469 || (GET_CODE (orig) == SYMBOL_REF &&
2470 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0))))
2472 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2475 pic_ref = gen_rtx_MEM (Pmode,
2476 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2478 RTX_UNCHANGING_P (pic_ref) = 1;
2481 insn = emit_move_insn (reg, pic_ref);
2483 current_function_uses_pic_offset_table = 1;
2484 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2486 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2490 else if (GET_CODE (orig) == CONST)
2494 if (GET_CODE (XEXP (orig, 0)) == PLUS
2495 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2503 reg = gen_reg_rtx (Pmode);
2506 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2508 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2509 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2510 base == reg ? 0 : reg);
2515 if (GET_CODE (offset) == CONST_INT)
2517 /* The base register doesn't really matter, we only want to
2518 test the index for the appropriate mode. */
2519 if (!arm_legitimate_index_p (mode, offset, 0))
2521 if (!no_new_pseudos)
2522 offset = force_reg (Pmode, offset);
2527 if (GET_CODE (offset) == CONST_INT)
2528 return plus_constant (base, INTVAL (offset));
2531 if (GET_MODE_SIZE (mode) > 4
2532 && (GET_MODE_CLASS (mode) == MODE_INT
2533 || TARGET_SOFT_FLOAT))
2535 emit_insn (gen_addsi3 (reg, base, offset));
2539 return gen_rtx_PLUS (Pmode, base, offset);
2545 /* Generate code to load the PIC register. PROLOGUE is true if
2546 called from arm_expand_prologue (in which case we want the
2547 generated insns at the start of the function); false if called
2548 by an exception receiver that needs the PIC register reloaded
2549 (in which case the insns are just dumped at the current location). */
2552 arm_finalize_pic (prologue)
2553 int prologue ATTRIBUTE_UNUSED;
2555 #ifndef AOF_ASSEMBLER
2556 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2557 rtx global_offset_table;
2559 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2566 l1 = gen_label_rtx ();
2568 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2569 /* On the ARM the PC register contains 'dot + 8' at the time of the
2570 addition, on the Thumb it is 'dot + 4'. */
2571 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2573 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2574 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2576 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2578 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2582 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2583 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2587 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2588 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2594 emit_insn_after (seq, get_insns ());
2598 /* Need to emit this whether or not we obey regdecls,
2599 since setjmp/longjmp can cause life info to screw up. */
2600 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2601 #endif /* AOF_ASSEMBLER */
2604 /* Return nonzero if X is valid as an ARM state addressing register. */
2606 arm_address_register_rtx_p (x, strict_p)
2612 if (GET_CODE (x) != REG)
2618 return ARM_REGNO_OK_FOR_BASE_P (regno);
2620 return (regno <= LAST_ARM_REGNUM
2621 || regno >= FIRST_PSEUDO_REGISTER
2622 || regno == FRAME_POINTER_REGNUM
2623 || regno == ARG_POINTER_REGNUM);
2626 /* Return nonzero if X is a valid ARM state address operand. */
2628 arm_legitimate_address_p (mode, x, strict_p)
2629 enum machine_mode mode;
2633 if (arm_address_register_rtx_p (x, strict_p))
2636 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2637 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2639 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2640 && GET_MODE_SIZE (mode) <= 4
2641 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2642 && GET_CODE (XEXP (x, 1)) == PLUS
2643 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2644 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2646 /* After reload constants split into minipools will have addresses
2647 from a LABEL_REF. */
2648 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2649 && (GET_CODE (x) == LABEL_REF
2650 || (GET_CODE (x) == CONST
2651 && GET_CODE (XEXP (x, 0)) == PLUS
2652 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2653 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2656 else if (mode == TImode)
2659 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2661 if (GET_CODE (x) == PLUS
2662 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2663 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2665 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2667 if (val == 4 || val == -4 || val == -8)
2672 else if (GET_CODE (x) == PLUS)
2674 rtx xop0 = XEXP (x, 0);
2675 rtx xop1 = XEXP (x, 1);
2677 return ((arm_address_register_rtx_p (xop0, strict_p)
2678 && arm_legitimate_index_p (mode, xop1, strict_p))
2679 || (arm_address_register_rtx_p (xop1, strict_p)
2680 && arm_legitimate_index_p (mode, xop0, strict_p)));
2684 /* Reload currently can't handle MINUS, so disable this for now */
2685 else if (GET_CODE (x) == MINUS)
2687 rtx xop0 = XEXP (x, 0);
2688 rtx xop1 = XEXP (x, 1);
2690 return (arm_address_register_rtx_p (xop0, strict_p)
2691 && arm_legitimate_index_p (mode, xop1, strict_p));
2695 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2696 && GET_CODE (x) == SYMBOL_REF
2697 && CONSTANT_POOL_ADDRESS_P (x)
2699 && symbol_mentioned_p (get_pool_constant (x))))
2702 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2703 && (GET_MODE_SIZE (mode) <= 4)
2704 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2710 /* Return nonzero if INDEX is valid for an address index operand in
2713 arm_legitimate_index_p (mode, index, strict_p)
2714 enum machine_mode mode;
2718 HOST_WIDE_INT range;
2719 enum rtx_code code = GET_CODE (index);
2721 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
2722 return (code == CONST_INT && INTVAL (index) < 1024
2723 && INTVAL (index) > -1024
2724 && (INTVAL (index) & 3) == 0);
2727 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2728 return (code == CONST_INT
2729 && INTVAL (index) < 255
2730 && INTVAL (index) > -255);
2732 if (arm_address_register_rtx_p (index, strict_p)
2733 && GET_MODE_SIZE (mode) <= 4)
2736 /* XXX What about ldrsb? */
2737 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2738 && (!arm_arch4 || (mode) != HImode))
2740 rtx xiop0 = XEXP (index, 0);
2741 rtx xiop1 = XEXP (index, 1);
2743 return ((arm_address_register_rtx_p (xiop0, strict_p)
2744 && power_of_two_operand (xiop1, SImode))
2745 || (arm_address_register_rtx_p (xiop1, strict_p)
2746 && power_of_two_operand (xiop0, SImode)));
2749 if (GET_MODE_SIZE (mode) <= 4
2750 && (code == LSHIFTRT || code == ASHIFTRT
2751 || code == ASHIFT || code == ROTATERT)
2752 && (!arm_arch4 || (mode) != HImode))
2754 rtx op = XEXP (index, 1);
2756 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2757 && GET_CODE (op) == CONST_INT
2759 && INTVAL (op) <= 31);
2762 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2763 load, but that has a restricted addressing range and we are unable
2764 to tell here whether that is the case. To be safe we restrict all
2765 loads to that range. */
2766 range = ((mode) == HImode || (mode) == QImode)
2767 ? (arm_arch4 ? 256 : 4095) : 4096;
2769 return (code == CONST_INT
2770 && INTVAL (index) < range
2771 && INTVAL (index) > -range);
2774 /* Return nonzero if X is valid as an ARM state addressing register. */
2776 thumb_base_register_rtx_p (x, mode, strict_p)
2778 enum machine_mode mode;
2783 if (GET_CODE (x) != REG)
2789 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
2791 return (regno <= LAST_LO_REGNUM
2792 || regno >= FIRST_PSEUDO_REGISTER
2793 || regno == FRAME_POINTER_REGNUM
2794 || (GET_MODE_SIZE (mode) >= 4
2795 && (regno == STACK_POINTER_REGNUM
2796 || x == hard_frame_pointer_rtx
2797 || x == arg_pointer_rtx)));
2800 /* Return nonzero if x is a legitimate index register. This is the case
2801 for any base register that can access a QImode object. */
2803 thumb_index_register_rtx_p (x, strict_p)
2807 return thumb_base_register_rtx_p (x, QImode, strict_p);
2810 /* Return nonzero if x is a legitimate Thumb-state address.
2812 The AP may be eliminated to either the SP or the FP, so we use the
2813 least common denominator, e.g. SImode, and offsets from 0 to 64.
2815 ??? Verify whether the above is the right approach.
2817 ??? Also, the FP may be eliminated to the SP, so perhaps that
2818 needs special handling also.
2820 ??? Look at how the mips16 port solves this problem. It probably uses
2821 better ways to solve some of these problems.
2823 Although it is not incorrect, we don't accept QImode and HImode
2824 addresses based on the frame pointer or arg pointer until the
2825 reload pass starts. This is so that eliminating such addresses
2826 into stack based ones won't produce impossible code. */
2828 thumb_legitimate_address_p (mode, x, strict_p)
2829 enum machine_mode mode;
2833 /* ??? Not clear if this is right. Experiment. */
2834 if (GET_MODE_SIZE (mode) < 4
2835 && !(reload_in_progress || reload_completed)
2836 && (reg_mentioned_p (frame_pointer_rtx, x)
2837 || reg_mentioned_p (arg_pointer_rtx, x)
2838 || reg_mentioned_p (virtual_incoming_args_rtx, x)
2839 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
2840 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
2841 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
2844 /* Accept any base register. SP only in SImode or larger. */
2845 else if (thumb_base_register_rtx_p (x, mode, strict_p))
2848 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */
2849 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
2850 && GET_CODE (x) == SYMBOL_REF
2851 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
2854 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */
2855 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2856 && (GET_CODE (x) == LABEL_REF
2857 || (GET_CODE (x) == CONST
2858 && GET_CODE (XEXP (x, 0)) == PLUS
2859 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2860 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2863 /* Post-inc indexing only supported for SImode and larger. */
2864 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
2865 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
2868 else if (GET_CODE (x) == PLUS)
2870 /* REG+REG address can be any two index registers. */
2871 /* We disallow FRAME+REG addressing since we know that FRAME
2872 will be replaced with STACK, and SP relative addressing only
2873 permits SP+OFFSET. */
2874 if (GET_MODE_SIZE (mode) <= 4
2875 && XEXP (x, 0) != frame_pointer_rtx
2876 && XEXP (x, 1) != frame_pointer_rtx
2877 && XEXP (x, 0) != virtual_stack_vars_rtx
2878 && XEXP (x, 1) != virtual_stack_vars_rtx
2879 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2880 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
2883 /* REG+const has 5-7 bit offset for non-SP registers. */
2884 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2885 || XEXP (x, 0) == arg_pointer_rtx)
2886 && GET_CODE (XEXP (x, 1)) == CONST_INT
2887 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
2890 /* REG+const has 10 bit offset for SP, but only SImode and
2891 larger is supported. */
2892 /* ??? Should probably check for DI/DFmode overflow here
2893 just like GO_IF_LEGITIMATE_OFFSET does. */
2894 else if (GET_CODE (XEXP (x, 0)) == REG
2895 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
2896 && GET_MODE_SIZE (mode) >= 4
2897 && GET_CODE (XEXP (x, 1)) == CONST_INT
2898 && INTVAL (XEXP (x, 1)) >= 0
2899 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
2900 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2903 else if (GET_CODE (XEXP (x, 0)) == REG
2904 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
2905 && GET_MODE_SIZE (mode) >= 4
2906 && GET_CODE (XEXP (x, 1)) == CONST_INT
2907 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2911 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2912 && GET_CODE (x) == SYMBOL_REF
2913 && CONSTANT_POOL_ADDRESS_P (x)
2915 && symbol_mentioned_p (get_pool_constant (x))))
2921 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2922 instruction of mode MODE. */
2924 thumb_legitimate_offset_p (mode, val)
2925 enum machine_mode mode;
2928 switch (GET_MODE_SIZE (mode))
2931 return val >= 0 && val < 32;
2934 return val >= 0 && val < 64 && (val & 1) == 0;
2938 && (val + GET_MODE_SIZE (mode)) <= 128
2943 /* Try machine-dependent ways of modifying an illegitimate address
2944 to be legitimate. If we find one, return the new, valid address. */
2947 arm_legitimize_address (x, orig_x, mode)
2950 enum machine_mode mode;
2952 if (GET_CODE (x) == PLUS)
2954 rtx xop0 = XEXP (x, 0);
2955 rtx xop1 = XEXP (x, 1);
2957 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
2958 xop0 = force_reg (SImode, xop0);
2960 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
2961 xop1 = force_reg (SImode, xop1);
2963 if (ARM_BASE_REGISTER_RTX_P (xop0)
2964 && GET_CODE (xop1) == CONST_INT)
2966 HOST_WIDE_INT n, low_n;
2970 if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2982 low_n = ((mode) == TImode ? 0
2983 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
2987 base_reg = gen_reg_rtx (SImode);
2988 val = force_operand (gen_rtx_PLUS (SImode, xop0,
2989 GEN_INT (n)), NULL_RTX);
2990 emit_move_insn (base_reg, val);
2991 x = (low_n == 0 ? base_reg
2992 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
2994 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
2995 x = gen_rtx_PLUS (SImode, xop0, xop1);
2998 /* XXX We don't allow MINUS any more -- see comment in
2999 arm_legitimate_address_p (). */
3000 else if (GET_CODE (x) == MINUS)
3002 rtx xop0 = XEXP (x, 0);
3003 rtx xop1 = XEXP (x, 1);
3005 if (CONSTANT_P (xop0))
3006 xop0 = force_reg (SImode, xop0);
3008 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3009 xop1 = force_reg (SImode, xop1);
3011 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3012 x = gen_rtx_MINUS (SImode, xop0, xop1);
3017 /* We need to find and carefully transform any SYMBOL and LABEL
3018 references; so go back to the original address expression. */
3019 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3021 if (new_x != orig_x)
3030 #define REG_OR_SUBREG_REG(X) \
3031 (GET_CODE (X) == REG \
3032 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3034 #define REG_OR_SUBREG_RTX(X) \
3035 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3037 #ifndef COSTS_N_INSNS
3038 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3042 arm_rtx_costs_1 (x, code, outer)
3045 enum rtx_code outer;
3047 enum machine_mode mode = GET_MODE (x);
3048 enum rtx_code subcode;
3064 return COSTS_N_INSNS (1);
3067 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3070 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3077 return COSTS_N_INSNS (2) + cycles;
3079 return COSTS_N_INSNS (1) + 16;
3082 return (COSTS_N_INSNS (1)
3083 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3084 + GET_CODE (SET_DEST (x)) == MEM));
3089 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3091 if (thumb_shiftable_const (INTVAL (x)))
3092 return COSTS_N_INSNS (2);
3093 return COSTS_N_INSNS (3);
3095 else if (outer == PLUS
3096 && INTVAL (x) < 256 && INTVAL (x) > -256)
3098 else if (outer == COMPARE
3099 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3101 else if (outer == ASHIFT || outer == ASHIFTRT
3102 || outer == LSHIFTRT)
3104 return COSTS_N_INSNS (2);
3110 return COSTS_N_INSNS (3);
3129 /* XXX another guess. */
3130 /* Memory costs quite a lot for the first word, but subsequent words
3131 load at the equivalent of a single insn each. */
3132 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3133 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3138 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3143 /* XXX still guessing. */
3144 switch (GET_MODE (XEXP (x, 0)))
3147 return (1 + (mode == DImode ? 4 : 0)
3148 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3151 return (4 + (mode == DImode ? 4 : 0)
3152 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3155 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3169 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
3179 /* Memory costs quite a lot for the first word, but subsequent words
3180 load at the equivalent of a single insn each. */
3181 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3182 + (GET_CODE (x) == SYMBOL_REF
3183 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3190 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3197 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3199 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3200 + ((GET_CODE (XEXP (x, 0)) == REG
3201 || (GET_CODE (XEXP (x, 0)) == SUBREG
3202 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3204 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3205 || (GET_CODE (XEXP (x, 0)) == SUBREG
3206 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3208 + ((GET_CODE (XEXP (x, 1)) == REG
3209 || (GET_CODE (XEXP (x, 1)) == SUBREG
3210 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3211 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3216 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3217 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3218 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3219 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3222 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3223 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3224 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3225 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
3227 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3228 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3229 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
3232 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3233 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3234 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3235 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3236 || subcode == ASHIFTRT || subcode == LSHIFTRT
3237 || subcode == ROTATE || subcode == ROTATERT
3239 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3240 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3241 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3242 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3243 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3244 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3245 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3250 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3251 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3252 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3253 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3254 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
3258 case AND: case XOR: case IOR:
3261 /* Normally the frame registers will be spilt into reg+const during
3262 reload, so it is a bad idea to combine them with other instructions,
3263 since then they might not be moved outside of loops. As a compromise
3264 we allow integration with ops that have a constant as their second
3266 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3267 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3268 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3269 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3270 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3274 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3275 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3276 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3277 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3280 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3281 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3282 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3283 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3284 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3287 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3288 return (1 + extra_cost
3289 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3290 || subcode == LSHIFTRT || subcode == ASHIFTRT
3291 || subcode == ROTATE || subcode == ROTATERT
3293 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3294 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3295 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3296 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3297 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3298 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3304 /* There is no point basing this on the tuning, since it is always the
3305 fast variant if it exists at all. */
3306 if (arm_fast_multiply && mode == DImode
3307 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3308 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3309 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3312 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3316 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3318 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3319 & (unsigned HOST_WIDE_INT) 0xffffffff);
3320 int add_cost = const_ok_for_arm (i) ? 4 : 8;
3323 /* Tune as appropriate. */
3324 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
3326 for (j = 0; i && j < 32; j += booth_unit_size)
3328 i >>= booth_unit_size;
3335 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
3336 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3337 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
3340 if (arm_fast_multiply && mode == SImode
3341 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3342 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3343 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3344 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3345 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3346 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3351 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3352 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3356 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3358 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3361 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3369 return 4 + (mode == DImode ? 4 : 0);
3372 if (GET_MODE (XEXP (x, 0)) == QImode)
3373 return (4 + (mode == DImode ? 4 : 0)
3374 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3377 switch (GET_MODE (XEXP (x, 0)))
3380 return (1 + (mode == DImode ? 4 : 0)
3381 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3384 return (4 + (mode == DImode ? 4 : 0)
3385 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3388 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3396 if (const_ok_for_arm (INTVAL (x)))
3397 return outer == SET ? 2 : -1;
3398 else if (outer == AND
3399 && const_ok_for_arm (~INTVAL (x)))
3401 else if ((outer == COMPARE
3402 || outer == PLUS || outer == MINUS)
3403 && const_ok_for_arm (-INTVAL (x)))
3414 if (const_double_rtx_ok_for_fpu (x))
3415 return outer == SET ? 2 : -1;
3416 else if ((outer == COMPARE || outer == PLUS)
3417 && neg_const_double_rtx_ok_for_fpu (x))
3427 arm_rtx_costs (x, code, outer_code, total)
3429 int code, outer_code;
3432 *total = arm_rtx_costs_1 (x, code, outer_code);
3436 /* All address computations that can be done are free, but rtx cost returns
3437 the same for practically all of them. So we weight the different types
3438 of address here in the order (most pref first):
3439 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3442 arm_address_cost (X)
3445 #define ARM_ADDRESS_COST(X) \
3446 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3447 || GET_CODE (X) == SYMBOL_REF) \
3449 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3450 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3452 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3453 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3454 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3455 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3456 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3457 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3461 #define THUMB_ADDRESS_COST(X) \
3462 ((GET_CODE (X) == REG \
3463 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3464 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3467 return (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X));
3471 arm_adjust_cost (insn, link, dep, cost)
3479 /* Some true dependencies can have a higher cost depending
3480 on precisely how certain input operands are used. */
3482 && REG_NOTE_KIND (link) == 0
3483 && recog_memoized (insn) < 0
3484 && recog_memoized (dep) < 0)
3486 int shift_opnum = get_attr_shift (insn);
3487 enum attr_type attr_type = get_attr_type (dep);
3489 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3490 operand for INSN. If we have a shifted input operand and the
3491 instruction we depend on is another ALU instruction, then we may
3492 have to account for an additional stall. */
3493 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
3495 rtx shifted_operand;
3498 /* Get the shifted operand. */
3499 extract_insn (insn);
3500 shifted_operand = recog_data.operand[shift_opnum];
3502 /* Iterate over all the operands in DEP. If we write an operand
3503 that overlaps with SHIFTED_OPERAND, then we have increase the
3504 cost of this dependency. */
3506 preprocess_constraints ();
3507 for (opno = 0; opno < recog_data.n_operands; opno++)
3509 /* We can ignore strict inputs. */
3510 if (recog_data.operand_type[opno] == OP_IN)
3513 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3520 /* XXX This is not strictly true for the FPA. */
3521 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3522 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3525 /* Call insns don't incur a stall, even if they follow a load. */
3526 if (REG_NOTE_KIND (link) == 0
3527 && GET_CODE (insn) == CALL_INSN)
3530 if ((i_pat = single_set (insn)) != NULL
3531 && GET_CODE (SET_SRC (i_pat)) == MEM
3532 && (d_pat = single_set (dep)) != NULL
3533 && GET_CODE (SET_DEST (d_pat)) == MEM)
3535 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3536 /* This is a load after a store, there is no conflict if the load reads
3537 from a cached area. Assume that loads from the stack, and from the
3538 constant pool are cached, and that others will miss. This is a
3541 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3542 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3543 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3544 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3551 /* This code has been fixed for cross compilation. */
3553 static int fpa_consts_inited = 0;
3555 static const char * const strings_fpa[8] =
3558 "4", "5", "0.5", "10"
3561 static REAL_VALUE_TYPE values_fpa[8];
3569 for (i = 0; i < 8; i++)
3571 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3575 fpa_consts_inited = 1;
3578 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3581 const_double_rtx_ok_for_fpu (x)
3587 if (!fpa_consts_inited)
3590 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3591 if (REAL_VALUE_MINUS_ZERO (r))
3594 for (i = 0; i < 8; i++)
3595 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3601 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3604 neg_const_double_rtx_ok_for_fpu (x)
3610 if (!fpa_consts_inited)
3613 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3614 r = REAL_VALUE_NEGATE (r);
3615 if (REAL_VALUE_MINUS_ZERO (r))
3618 for (i = 0; i < 8; i++)
3619 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3625 /* Predicates for `match_operand' and `match_operator'. */
3627 /* s_register_operand is the same as register_operand, but it doesn't accept
3630 This function exists because at the time it was put in it led to better
3631 code. SUBREG(MEM) always needs a reload in the places where
3632 s_register_operand is used, and this seemed to lead to excessive
3636 s_register_operand (op, mode)
3638 enum machine_mode mode;
3640 if (GET_MODE (op) != mode && mode != VOIDmode)
3643 if (GET_CODE (op) == SUBREG)
3644 op = SUBREG_REG (op);
3646 /* We don't consider registers whose class is NO_REGS
3647 to be a register operand. */
3648 /* XXX might have to check for lo regs only for thumb ??? */
3649 return (GET_CODE (op) == REG
3650 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3651 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3654 /* A hard register operand (even before reload. */
3657 arm_hard_register_operand (op, mode)
3659 enum machine_mode mode;
3661 if (GET_MODE (op) != mode && mode != VOIDmode)
3664 return (GET_CODE (op) == REG
3665 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3668 /* Only accept reg, subreg(reg), const_int. */
3671 reg_or_int_operand (op, mode)
3673 enum machine_mode mode;
3675 if (GET_CODE (op) == CONST_INT)
3678 if (GET_MODE (op) != mode && mode != VOIDmode)
3681 if (GET_CODE (op) == SUBREG)
3682 op = SUBREG_REG (op);
3684 /* We don't consider registers whose class is NO_REGS
3685 to be a register operand. */
3686 return (GET_CODE (op) == REG
3687 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3688 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3691 /* Return 1 if OP is an item in memory, given that we are in reload. */
3694 arm_reload_memory_operand (op, mode)
3696 enum machine_mode mode ATTRIBUTE_UNUSED;
3698 int regno = true_regnum (op);
3700 return (!CONSTANT_P (op)
3702 || (GET_CODE (op) == REG
3703 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3706 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3707 memory access (architecture V4).
3708 MODE is QImode if called when computing constraints, or VOIDmode when
3709 emitting patterns. In this latter case we cannot use memory_operand()
3710 because it will fail on badly formed MEMs, which is precisely what we are
3714 bad_signed_byte_operand (op, mode)
3716 enum machine_mode mode ATTRIBUTE_UNUSED;
3719 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
3722 if (GET_CODE (op) != MEM)
3727 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3728 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3729 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3730 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3731 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3734 /* Big constants are also bad. */
3735 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3736 && (INTVAL (XEXP (op, 1)) > 0xff
3737 || -INTVAL (XEXP (op, 1)) > 0xff))
3740 /* Everything else is good, or can will automatically be made so. */
3744 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3747 arm_rhs_operand (op, mode)
3749 enum machine_mode mode;
3751 return (s_register_operand (op, mode)
3752 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3755 /* Return TRUE for valid operands for the
3756 rhs of an ARM instruction, or a load. */
3759 arm_rhsm_operand (op, mode)
3761 enum machine_mode mode;
3763 return (s_register_operand (op, mode)
3764 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3765 || memory_operand (op, mode));
3768 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3769 constant that is valid when negated. */
3772 arm_add_operand (op, mode)
3774 enum machine_mode mode;
3777 return thumb_cmp_operand (op, mode);
3779 return (s_register_operand (op, mode)
3780 || (GET_CODE (op) == CONST_INT
3781 && (const_ok_for_arm (INTVAL (op))
3782 || const_ok_for_arm (-INTVAL (op)))));
3786 arm_not_operand (op, mode)
3788 enum machine_mode mode;
3790 return (s_register_operand (op, mode)
3791 || (GET_CODE (op) == CONST_INT
3792 && (const_ok_for_arm (INTVAL (op))
3793 || const_ok_for_arm (~INTVAL (op)))));
3796 /* Return TRUE if the operand is a memory reference which contains an
3797 offsettable address. */
3800 offsettable_memory_operand (op, mode)
3802 enum machine_mode mode;
3804 if (mode == VOIDmode)
3805 mode = GET_MODE (op);
3807 return (mode == GET_MODE (op)
3808 && GET_CODE (op) == MEM
3809 && offsettable_address_p (reload_completed | reload_in_progress,
3810 mode, XEXP (op, 0)));
3813 /* Return TRUE if the operand is a memory reference which is, or can be
3814 made word aligned by adjusting the offset. */
3817 alignable_memory_operand (op, mode)
3819 enum machine_mode mode;
3823 if (mode == VOIDmode)
3824 mode = GET_MODE (op);
3826 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3831 return ((GET_CODE (reg = op) == REG
3832 || (GET_CODE (op) == SUBREG
3833 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3834 || (GET_CODE (op) == PLUS
3835 && GET_CODE (XEXP (op, 1)) == CONST_INT
3836 && (GET_CODE (reg = XEXP (op, 0)) == REG
3837 || (GET_CODE (XEXP (op, 0)) == SUBREG
3838 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3839 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3842 /* Similar to s_register_operand, but does not allow hard integer
3846 f_register_operand (op, mode)
3848 enum machine_mode mode;
3850 if (GET_MODE (op) != mode && mode != VOIDmode)
3853 if (GET_CODE (op) == SUBREG)
3854 op = SUBREG_REG (op);
3856 /* We don't consider registers whose class is NO_REGS
3857 to be a register operand. */
3858 return (GET_CODE (op) == REG
3859 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3860 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3863 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3866 fpu_rhs_operand (op, mode)
3868 enum machine_mode mode;
3870 if (s_register_operand (op, mode))
3873 if (GET_MODE (op) != mode && mode != VOIDmode)
3876 if (GET_CODE (op) == CONST_DOUBLE)
3877 return const_double_rtx_ok_for_fpu (op);
3883 fpu_add_operand (op, mode)
3885 enum machine_mode mode;
3887 if (s_register_operand (op, mode))
3890 if (GET_MODE (op) != mode && mode != VOIDmode)
3893 if (GET_CODE (op) == CONST_DOUBLE)
3894 return (const_double_rtx_ok_for_fpu (op)
3895 || neg_const_double_rtx_ok_for_fpu (op));
3900 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3903 cirrus_memory_offset (op)
3906 /* Reject eliminable registers. */
3907 if (! (reload_in_progress || reload_completed)
3908 && ( reg_mentioned_p (frame_pointer_rtx, op)
3909 || reg_mentioned_p (arg_pointer_rtx, op)
3910 || reg_mentioned_p (virtual_incoming_args_rtx, op)
3911 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
3912 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
3913 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
3916 if (GET_CODE (op) == MEM)
3922 /* Match: (mem (reg)). */
3923 if (GET_CODE (ind) == REG)
3929 if (GET_CODE (ind) == PLUS
3930 && GET_CODE (XEXP (ind, 0)) == REG
3931 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
3932 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
3939 /* Return nonzero if OP is a Cirrus or general register. */
3942 cirrus_register_operand (op, mode)
3944 enum machine_mode mode;
3946 if (GET_MODE (op) != mode && mode != VOIDmode)
3949 if (GET_CODE (op) == SUBREG)
3950 op = SUBREG_REG (op);
3952 return (GET_CODE (op) == REG
3953 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
3954 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
3957 /* Return nonzero if OP is a cirrus FP register. */
3960 cirrus_fp_register (op, mode)
3962 enum machine_mode mode;
3964 if (GET_MODE (op) != mode && mode != VOIDmode)
3967 if (GET_CODE (op) == SUBREG)
3968 op = SUBREG_REG (op);
3970 return (GET_CODE (op) == REG
3971 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3972 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
3975 /* Return nonzero if OP is a 6bit constant (0..63). */
3978 cirrus_shift_const (op, mode)
3980 enum machine_mode mode ATTRIBUTE_UNUSED;
3982 return (GET_CODE (op) == CONST_INT
3984 && INTVAL (op) < 64);
3987 /* Return nonzero if INSN is an LDR R0,ADDR instruction. */
3990 is_load_address (insn)
3993 rtx body, lhs, rhs;;
3998 if (GET_CODE (insn) != INSN)
4001 body = PATTERN (insn);
4003 if (GET_CODE (body) != SET)
4006 lhs = XEXP (body, 0);
4007 rhs = XEXP (body, 1);
4009 return (GET_CODE (lhs) == REG
4010 && REGNO_REG_CLASS (REGNO (lhs)) == GENERAL_REGS
4011 && (GET_CODE (rhs) == MEM
4012 || GET_CODE (rhs) == SYMBOL_REF));
4015 /* Return nonzero if INSN is a Cirrus instruction. */
4018 is_cirrus_insn (insn)
4021 enum attr_cirrus attr;
4023 /* get_attr aborts on USE and CLOBBER. */
4025 || GET_CODE (insn) != INSN
4026 || GET_CODE (PATTERN (insn)) == USE
4027 || GET_CODE (PATTERN (insn)) == CLOBBER)
4030 attr = get_attr_cirrus (insn);
4032 return attr != CIRRUS_NO;
4035 /* Cirrus reorg for invalid instruction combinations. */
4038 cirrus_reorg (first)
4041 enum attr_cirrus attr;
4042 rtx body = PATTERN (first);
4046 /* Any branch must be followed by 2 non Cirrus instructions. */
4047 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4050 t = next_nonnote_insn (first);
4052 if (is_cirrus_insn (t))
4055 if (is_cirrus_insn (next_nonnote_insn (t)))
4059 emit_insn_after (gen_nop (), first);
4064 /* (float (blah)) is in parallel with a clobber. */
4065 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4066 body = XVECEXP (body, 0, 0);
4068 if (GET_CODE (body) == SET)
4070 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4072 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4073 be followed by a non Cirrus insn. */
4074 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4076 if (is_cirrus_insn (next_nonnote_insn (first)))
4077 emit_insn_after (gen_nop (), first);
4081 else if (is_load_address (first))
4083 unsigned int arm_regno;
4085 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4086 ldr/cfmv64hr combination where the Rd field is the same
4087 in both instructions must be split with a non Cirrus
4094 /* Get Arm register number for ldr insn. */
4095 if (GET_CODE (lhs) == REG)
4096 arm_regno = REGNO (lhs);
4097 else if (GET_CODE (rhs) == REG)
4098 arm_regno = REGNO (rhs);
4103 first = next_nonnote_insn (first);
4105 if (!is_cirrus_insn (first))
4108 body = PATTERN (first);
4110 /* (float (blah)) is in parallel with a clobber. */
4111 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4112 body = XVECEXP (body, 0, 0);
4114 if (GET_CODE (body) == FLOAT)
4115 body = XEXP (body, 0);
4117 if (get_attr_cirrus (first) == CIRRUS_MOVE
4118 && GET_CODE (XEXP (body, 1)) == REG
4119 && arm_regno == REGNO (XEXP (body, 1)))
4120 emit_insn_after (gen_nop (), first);
4126 /* get_attr aborts on USE and CLOBBER. */
4128 || GET_CODE (first) != INSN
4129 || GET_CODE (PATTERN (first)) == USE
4130 || GET_CODE (PATTERN (first)) == CLOBBER)
4133 attr = get_attr_cirrus (first);
4135 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4136 must be followed by a non-coprocessor instruction. */
4137 if (attr == CIRRUS_COMPARE)
4141 t = next_nonnote_insn (first);
4143 if (is_cirrus_insn (t))
4146 if (is_cirrus_insn (next_nonnote_insn (t)))
4150 emit_insn_after (gen_nop (), first);
4156 /* Return nonzero if OP is a constant power of two. */
4159 power_of_two_operand (op, mode)
4161 enum machine_mode mode ATTRIBUTE_UNUSED;
4163 if (GET_CODE (op) == CONST_INT)
4165 HOST_WIDE_INT value = INTVAL (op);
4167 return value != 0 && (value & (value - 1)) == 0;
4173 /* Return TRUE for a valid operand of a DImode operation.
4174 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4175 Note that this disallows MEM(REG+REG), but allows
4176 MEM(PRE/POST_INC/DEC(REG)). */
4179 di_operand (op, mode)
4181 enum machine_mode mode;
4183 if (s_register_operand (op, mode))
4186 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4189 if (GET_CODE (op) == SUBREG)
4190 op = SUBREG_REG (op);
4192 switch (GET_CODE (op))
4199 return memory_address_p (DImode, XEXP (op, 0));
4206 /* Like di_operand, but don't accept constants. */
4209 nonimmediate_di_operand (op, mode)
4211 enum machine_mode mode;
4213 if (s_register_operand (op, mode))
4216 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4219 if (GET_CODE (op) == SUBREG)
4220 op = SUBREG_REG (op);
4222 if (GET_CODE (op) == MEM)
4223 return memory_address_p (DImode, XEXP (op, 0));
4228 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4229 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4230 Note that this disallows MEM(REG+REG), but allows
4231 MEM(PRE/POST_INC/DEC(REG)). */
4234 soft_df_operand (op, mode)
4236 enum machine_mode mode;
4238 if (s_register_operand (op, mode))
4241 if (mode != VOIDmode && GET_MODE (op) != mode)
4244 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4247 if (GET_CODE (op) == SUBREG)
4248 op = SUBREG_REG (op);
4250 switch (GET_CODE (op))
4256 return memory_address_p (DFmode, XEXP (op, 0));
4263 /* Like soft_df_operand, but don't accept constants. */
4266 nonimmediate_soft_df_operand (op, mode)
4268 enum machine_mode mode;
4270 if (s_register_operand (op, mode))
4273 if (mode != VOIDmode && GET_MODE (op) != mode)
4276 if (GET_CODE (op) == SUBREG)
4277 op = SUBREG_REG (op);
4279 if (GET_CODE (op) == MEM)
4280 return memory_address_p (DFmode, XEXP (op, 0));
4284 /* Return TRUE for valid index operands. */
4287 index_operand (op, mode)
4289 enum machine_mode mode;
4291 return (s_register_operand (op, mode)
4292 || (immediate_operand (op, mode)
4293 && (GET_CODE (op) != CONST_INT
4294 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4297 /* Return TRUE for valid shifts by a constant. This also accepts any
4298 power of two on the (somewhat overly relaxed) assumption that the
4299 shift operator in this case was a mult. */
4302 const_shift_operand (op, mode)
4304 enum machine_mode mode;
4306 return (power_of_two_operand (op, mode)
4307 || (immediate_operand (op, mode)
4308 && (GET_CODE (op) != CONST_INT
4309 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4312 /* Return TRUE for arithmetic operators which can be combined with a multiply
4316 shiftable_operator (x, mode)
4318 enum machine_mode mode;
4322 if (GET_MODE (x) != mode)
4325 code = GET_CODE (x);
4327 return (code == PLUS || code == MINUS
4328 || code == IOR || code == XOR || code == AND);
4331 /* Return TRUE for binary logical operators. */
4334 logical_binary_operator (x, mode)
4336 enum machine_mode mode;
4340 if (GET_MODE (x) != mode)
4343 code = GET_CODE (x);
4345 return (code == IOR || code == XOR || code == AND);
4348 /* Return TRUE for shift operators. */
4351 shift_operator (x, mode)
4353 enum machine_mode mode;
4357 if (GET_MODE (x) != mode)
4360 code = GET_CODE (x);
4363 return power_of_two_operand (XEXP (x, 1), mode);
4365 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4366 || code == ROTATERT);
4369 /* Return TRUE if x is EQ or NE. */
4372 equality_operator (x, mode)
4374 enum machine_mode mode ATTRIBUTE_UNUSED;
4376 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4379 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4382 arm_comparison_operator (x, mode)
4384 enum machine_mode mode;
4386 return (comparison_operator (x, mode)
4387 && GET_CODE (x) != LTGT
4388 && GET_CODE (x) != UNEQ);
4391 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4394 minmax_operator (x, mode)
4396 enum machine_mode mode;
4398 enum rtx_code code = GET_CODE (x);
4400 if (GET_MODE (x) != mode)
4403 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4406 /* Return TRUE if this is the condition code register, if we aren't given
4407 a mode, accept any class CCmode register. */
4410 cc_register (x, mode)
4412 enum machine_mode mode;
4414 if (mode == VOIDmode)
4416 mode = GET_MODE (x);
4418 if (GET_MODE_CLASS (mode) != MODE_CC)
4422 if ( GET_MODE (x) == mode
4423 && GET_CODE (x) == REG
4424 && REGNO (x) == CC_REGNUM)
4430 /* Return TRUE if this is the condition code register, if we aren't given
4431 a mode, accept any class CCmode register which indicates a dominance
4435 dominant_cc_register (x, mode)
4437 enum machine_mode mode;
4439 if (mode == VOIDmode)
4441 mode = GET_MODE (x);
4443 if (GET_MODE_CLASS (mode) != MODE_CC)
4447 if ( mode != CC_DNEmode && mode != CC_DEQmode
4448 && mode != CC_DLEmode && mode != CC_DLTmode
4449 && mode != CC_DGEmode && mode != CC_DGTmode
4450 && mode != CC_DLEUmode && mode != CC_DLTUmode
4451 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4454 return cc_register (x, mode);
4457 /* Return TRUE if X references a SYMBOL_REF. */
4460 symbol_mentioned_p (x)
4466 if (GET_CODE (x) == SYMBOL_REF)
4469 fmt = GET_RTX_FORMAT (GET_CODE (x));
4471 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4477 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4478 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4481 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4488 /* Return TRUE if X references a LABEL_REF. */
4491 label_mentioned_p (x)
4497 if (GET_CODE (x) == LABEL_REF)
4500 fmt = GET_RTX_FORMAT (GET_CODE (x));
4501 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4507 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4508 if (label_mentioned_p (XVECEXP (x, i, j)))
4511 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4522 enum rtx_code code = GET_CODE (x);
4526 else if (code == SMIN)
4528 else if (code == UMIN)
4530 else if (code == UMAX)
4536 /* Return 1 if memory locations are adjacent. */
4539 adjacent_mem_locations (a, b)
4542 if ((GET_CODE (XEXP (a, 0)) == REG
4543 || (GET_CODE (XEXP (a, 0)) == PLUS
4544 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4545 && (GET_CODE (XEXP (b, 0)) == REG
4546 || (GET_CODE (XEXP (b, 0)) == PLUS
4547 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
4549 int val0 = 0, val1 = 0;
4552 if (GET_CODE (XEXP (a, 0)) == PLUS)
4554 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
4555 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
4558 reg0 = REGNO (XEXP (a, 0));
4560 if (GET_CODE (XEXP (b, 0)) == PLUS)
4562 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
4563 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
4566 reg1 = REGNO (XEXP (b, 0));
4568 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
4573 /* Return 1 if OP is a load multiple operation. It is known to be
4574 parallel and the first section will be tested. */
4577 load_multiple_operation (op, mode)
4579 enum machine_mode mode ATTRIBUTE_UNUSED;
4581 HOST_WIDE_INT count = XVECLEN (op, 0);
4584 HOST_WIDE_INT i = 1, base = 0;
4588 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4591 /* Check to see if this might be a write-back. */
4592 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4597 /* Now check it more carefully. */
4598 if (GET_CODE (SET_DEST (elt)) != REG
4599 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4600 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4601 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4602 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4606 /* Perform a quick check so we don't blow up below. */
4608 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4609 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
4610 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
4613 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
4614 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
4616 for (; i < count; i++)
4618 elt = XVECEXP (op, 0, i);
4620 if (GET_CODE (elt) != SET
4621 || GET_CODE (SET_DEST (elt)) != REG
4622 || GET_MODE (SET_DEST (elt)) != SImode
4623 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
4624 || GET_CODE (SET_SRC (elt)) != MEM
4625 || GET_MODE (SET_SRC (elt)) != SImode
4626 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
4627 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
4628 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
4629 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
4636 /* Return 1 if OP is a store multiple operation. It is known to be
4637 parallel and the first section will be tested. */
4640 store_multiple_operation (op, mode)
4642 enum machine_mode mode ATTRIBUTE_UNUSED;
4644 HOST_WIDE_INT count = XVECLEN (op, 0);
4647 HOST_WIDE_INT i = 1, base = 0;
4651 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4654 /* Check to see if this might be a write-back. */
4655 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4660 /* Now check it more carefully. */
4661 if (GET_CODE (SET_DEST (elt)) != REG
4662 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4663 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4664 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4665 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4669 /* Perform a quick check so we don't blow up below. */
4671 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4672 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
4673 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
4676 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
4677 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
4679 for (; i < count; i++)
4681 elt = XVECEXP (op, 0, i);
4683 if (GET_CODE (elt) != SET
4684 || GET_CODE (SET_SRC (elt)) != REG
4685 || GET_MODE (SET_SRC (elt)) != SImode
4686 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
4687 || GET_CODE (SET_DEST (elt)) != MEM
4688 || GET_MODE (SET_DEST (elt)) != SImode
4689 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
4690 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
4691 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
4692 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
4700 load_multiple_sequence (operands, nops, regs, base, load_offset)
4705 HOST_WIDE_INT * load_offset;
4707 int unsorted_regs[4];
4708 HOST_WIDE_INT unsorted_offsets[4];
4713 /* Can only handle 2, 3, or 4 insns at present,
4714 though could be easily extended if required. */
4715 if (nops < 2 || nops > 4)
4718 /* Loop over the operands and check that the memory references are
4719 suitable (ie immediate offsets from the same base register). At
4720 the same time, extract the target register, and the memory
4722 for (i = 0; i < nops; i++)
4727 /* Convert a subreg of a mem into the mem itself. */
4728 if (GET_CODE (operands[nops + i]) == SUBREG)
4729 operands[nops + i] = alter_subreg (operands + (nops + i));
4731 if (GET_CODE (operands[nops + i]) != MEM)
4734 /* Don't reorder volatile memory references; it doesn't seem worth
4735 looking for the case where the order is ok anyway. */
4736 if (MEM_VOLATILE_P (operands[nops + i]))
4739 offset = const0_rtx;
4741 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4742 || (GET_CODE (reg) == SUBREG
4743 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4744 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4745 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4747 || (GET_CODE (reg) == SUBREG
4748 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4749 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4754 base_reg = REGNO (reg);
4755 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4756 ? REGNO (operands[i])
4757 : REGNO (SUBREG_REG (operands[i])));
4762 if (base_reg != (int) REGNO (reg))
4763 /* Not addressed from the same base register. */
4766 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4767 ? REGNO (operands[i])
4768 : REGNO (SUBREG_REG (operands[i])));
4769 if (unsorted_regs[i] < unsorted_regs[order[0]])
4773 /* If it isn't an integer register, or if it overwrites the
4774 base register but isn't the last insn in the list, then
4775 we can't do this. */
4776 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4777 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4780 unsorted_offsets[i] = INTVAL (offset);
4783 /* Not a suitable memory address. */
4787 /* All the useful information has now been extracted from the
4788 operands into unsorted_regs and unsorted_offsets; additionally,
4789 order[0] has been set to the lowest numbered register in the
4790 list. Sort the registers into order, and check that the memory
4791 offsets are ascending and adjacent. */
4793 for (i = 1; i < nops; i++)
4797 order[i] = order[i - 1];
4798 for (j = 0; j < nops; j++)
4799 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4800 && (order[i] == order[i - 1]
4801 || unsorted_regs[j] < unsorted_regs[order[i]]))
4804 /* Have we found a suitable register? if not, one must be used more
4806 if (order[i] == order[i - 1])
4809 /* Is the memory address adjacent and ascending? */
4810 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4818 for (i = 0; i < nops; i++)
4819 regs[i] = unsorted_regs[order[i]];
4821 *load_offset = unsorted_offsets[order[0]];
4824 if (unsorted_offsets[order[0]] == 0)
4825 return 1; /* ldmia */
4827 if (unsorted_offsets[order[0]] == 4)
4828 return 2; /* ldmib */
4830 if (unsorted_offsets[order[nops - 1]] == 0)
4831 return 3; /* ldmda */
4833 if (unsorted_offsets[order[nops - 1]] == -4)
4834 return 4; /* ldmdb */
4836 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4837 if the offset isn't small enough. The reason 2 ldrs are faster
4838 is because these ARMs are able to do more than one cache access
4839 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4840 whilst the ARM8 has a double bandwidth cache. This means that
4841 these cores can do both an instruction fetch and a data fetch in
4842 a single cycle, so the trick of calculating the address into a
4843 scratch register (one of the result regs) and then doing a load
4844 multiple actually becomes slower (and no smaller in code size).
4845 That is the transformation
4847 ldr rd1, [rbase + offset]
4848 ldr rd2, [rbase + offset + 4]
4852 add rd1, rbase, offset
4853 ldmia rd1, {rd1, rd2}
4855 produces worse code -- '3 cycles + any stalls on rd2' instead of
4856 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4857 access per cycle, the first sequence could never complete in less
4858 than 6 cycles, whereas the ldm sequence would only take 5 and
4859 would make better use of sequential accesses if not hitting the
4862 We cheat here and test 'arm_ld_sched' which we currently know to
4863 only be true for the ARM8, ARM9 and StrongARM. If this ever
4864 changes, then the test below needs to be reworked. */
4865 if (nops == 2 && arm_ld_sched)
4868 /* Can't do it without setting up the offset, only do this if it takes
4869 no more than one insn. */
4870 return (const_ok_for_arm (unsorted_offsets[order[0]])
4871 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4875 emit_ldm_seq (operands, nops)
4881 HOST_WIDE_INT offset;
4885 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4888 strcpy (buf, "ldm%?ia\t");
4892 strcpy (buf, "ldm%?ib\t");
4896 strcpy (buf, "ldm%?da\t");
4900 strcpy (buf, "ldm%?db\t");
4905 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4906 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4909 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4910 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4912 output_asm_insn (buf, operands);
4914 strcpy (buf, "ldm%?ia\t");
4921 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4922 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4924 for (i = 1; i < nops; i++)
4925 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4926 reg_names[regs[i]]);
4928 strcat (buf, "}\t%@ phole ldm");
4930 output_asm_insn (buf, operands);
4935 store_multiple_sequence (operands, nops, regs, base, load_offset)
4940 HOST_WIDE_INT * load_offset;
4942 int unsorted_regs[4];
4943 HOST_WIDE_INT unsorted_offsets[4];
4948 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4949 extended if required. */
4950 if (nops < 2 || nops > 4)
4953 /* Loop over the operands and check that the memory references are
4954 suitable (ie immediate offsets from the same base register). At
4955 the same time, extract the target register, and the memory
4957 for (i = 0; i < nops; i++)
4962 /* Convert a subreg of a mem into the mem itself. */
4963 if (GET_CODE (operands[nops + i]) == SUBREG)
4964 operands[nops + i] = alter_subreg (operands + (nops + i));
4966 if (GET_CODE (operands[nops + i]) != MEM)
4969 /* Don't reorder volatile memory references; it doesn't seem worth
4970 looking for the case where the order is ok anyway. */
4971 if (MEM_VOLATILE_P (operands[nops + i]))
4974 offset = const0_rtx;
4976 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4977 || (GET_CODE (reg) == SUBREG
4978 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4979 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4980 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4982 || (GET_CODE (reg) == SUBREG
4983 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4984 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4989 base_reg = REGNO (reg);
4990 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4991 ? REGNO (operands[i])
4992 : REGNO (SUBREG_REG (operands[i])));
4997 if (base_reg != (int) REGNO (reg))
4998 /* Not addressed from the same base register. */
5001 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5002 ? REGNO (operands[i])
5003 : REGNO (SUBREG_REG (operands[i])));
5004 if (unsorted_regs[i] < unsorted_regs[order[0]])
5008 /* If it isn't an integer register, then we can't do this. */
5009 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5012 unsorted_offsets[i] = INTVAL (offset);
5015 /* Not a suitable memory address. */
5019 /* All the useful information has now been extracted from the
5020 operands into unsorted_regs and unsorted_offsets; additionally,
5021 order[0] has been set to the lowest numbered register in the
5022 list. Sort the registers into order, and check that the memory
5023 offsets are ascending and adjacent. */
5025 for (i = 1; i < nops; i++)
5029 order[i] = order[i - 1];
5030 for (j = 0; j < nops; j++)
5031 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5032 && (order[i] == order[i - 1]
5033 || unsorted_regs[j] < unsorted_regs[order[i]]))
5036 /* Have we found a suitable register? if not, one must be used more
5038 if (order[i] == order[i - 1])
5041 /* Is the memory address adjacent and ascending? */
5042 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5050 for (i = 0; i < nops; i++)
5051 regs[i] = unsorted_regs[order[i]];
5053 *load_offset = unsorted_offsets[order[0]];
5056 if (unsorted_offsets[order[0]] == 0)
5057 return 1; /* stmia */
5059 if (unsorted_offsets[order[0]] == 4)
5060 return 2; /* stmib */
5062 if (unsorted_offsets[order[nops - 1]] == 0)
5063 return 3; /* stmda */
5065 if (unsorted_offsets[order[nops - 1]] == -4)
5066 return 4; /* stmdb */
5072 emit_stm_seq (operands, nops)
5078 HOST_WIDE_INT offset;
5082 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5085 strcpy (buf, "stm%?ia\t");
5089 strcpy (buf, "stm%?ib\t");
5093 strcpy (buf, "stm%?da\t");
5097 strcpy (buf, "stm%?db\t");
5104 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5105 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5107 for (i = 1; i < nops; i++)
5108 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5109 reg_names[regs[i]]);
5111 strcat (buf, "}\t%@ phole stm");
5113 output_asm_insn (buf, operands);
5118 multi_register_push (op, mode)
5120 enum machine_mode mode ATTRIBUTE_UNUSED;
5122 if (GET_CODE (op) != PARALLEL
5123 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5124 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5125 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5131 /* Routines for use in generating RTL. */
5134 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
5135 in_struct_p, scalar_p)
5147 int sign = up ? 1 : -1;
5150 /* XScale has load-store double instructions, but they have stricter
5151 alignment requirements than load-store multiple, so we can not
5154 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5155 the pipeline until completion.
5163 An ldr instruction takes 1-3 cycles, but does not block the
5172 Best case ldr will always win. However, the more ldr instructions
5173 we issue, the less likely we are to be able to schedule them well.
5174 Using ldr instructions also increases code size.
5176 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5177 for counts of 3 or 4 regs. */
5178 if (arm_is_xscale && count <= 2 && ! optimize_size)
5184 for (i = 0; i < count; i++)
5186 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5187 RTX_UNCHANGING_P (mem) = unchanging_p;
5188 MEM_IN_STRUCT_P (mem) = in_struct_p;
5189 MEM_SCALAR_P (mem) = scalar_p;
5190 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5194 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5202 result = gen_rtx_PARALLEL (VOIDmode,
5203 rtvec_alloc (count + (write_back ? 1 : 0)));
5206 XVECEXP (result, 0, 0)
5207 = gen_rtx_SET (GET_MODE (from), from,
5208 plus_constant (from, count * 4 * sign));
5213 for (j = 0; i < count; i++, j++)
5215 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5216 RTX_UNCHANGING_P (mem) = unchanging_p;
5217 MEM_IN_STRUCT_P (mem) = in_struct_p;
5218 MEM_SCALAR_P (mem) = scalar_p;
5219 XVECEXP (result, 0, i)
5220 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5227 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
5228 in_struct_p, scalar_p)
5240 int sign = up ? 1 : -1;
5243 /* See arm_gen_load_multiple for discussion of
5244 the pros/cons of ldm/stm usage for XScale. */
5245 if (arm_is_xscale && count <= 2 && ! optimize_size)
5251 for (i = 0; i < count; i++)
5253 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5254 RTX_UNCHANGING_P (mem) = unchanging_p;
5255 MEM_IN_STRUCT_P (mem) = in_struct_p;
5256 MEM_SCALAR_P (mem) = scalar_p;
5257 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5261 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5269 result = gen_rtx_PARALLEL (VOIDmode,
5270 rtvec_alloc (count + (write_back ? 1 : 0)));
5273 XVECEXP (result, 0, 0)
5274 = gen_rtx_SET (GET_MODE (to), to,
5275 plus_constant (to, count * 4 * sign));
5280 for (j = 0; i < count; i++, j++)
5282 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5283 RTX_UNCHANGING_P (mem) = unchanging_p;
5284 MEM_IN_STRUCT_P (mem) = in_struct_p;
5285 MEM_SCALAR_P (mem) = scalar_p;
5287 XVECEXP (result, 0, i)
5288 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5295 arm_gen_movstrqi (operands)
5298 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5301 rtx st_src, st_dst, fin_src, fin_dst;
5302 rtx part_bytes_reg = NULL;
5304 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5305 int dst_scalar_p, src_scalar_p;
5307 if (GET_CODE (operands[2]) != CONST_INT
5308 || GET_CODE (operands[3]) != CONST_INT
5309 || INTVAL (operands[2]) > 64
5310 || INTVAL (operands[3]) & 3)
5313 st_dst = XEXP (operands[0], 0);
5314 st_src = XEXP (operands[1], 0);
5316 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5317 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5318 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5319 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5320 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5321 src_scalar_p = MEM_SCALAR_P (operands[1]);
5323 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5324 fin_src = src = copy_to_mode_reg (SImode, st_src);
5326 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5327 out_words_to_go = INTVAL (operands[2]) / 4;
5328 last_bytes = INTVAL (operands[2]) & 3;
5330 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5331 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5333 for (i = 0; in_words_to_go >= 2; i+=4)
5335 if (in_words_to_go > 4)
5336 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5341 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5342 FALSE, src_unchanging_p,
5343 src_in_struct_p, src_scalar_p));
5345 if (out_words_to_go)
5347 if (out_words_to_go > 4)
5348 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5352 else if (out_words_to_go != 1)
5353 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5362 mem = gen_rtx_MEM (SImode, dst);
5363 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5364 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5365 MEM_SCALAR_P (mem) = dst_scalar_p;
5366 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5367 if (last_bytes != 0)
5368 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5372 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5373 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5376 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5377 if (out_words_to_go)
5381 mem = gen_rtx_MEM (SImode, src);
5382 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5383 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5384 MEM_SCALAR_P (mem) = src_scalar_p;
5385 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5386 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5388 mem = gen_rtx_MEM (SImode, dst);
5389 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5390 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5391 MEM_SCALAR_P (mem) = dst_scalar_p;
5392 emit_move_insn (mem, sreg);
5393 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5396 if (in_words_to_go) /* Sanity check */
5402 if (in_words_to_go < 0)
5405 mem = gen_rtx_MEM (SImode, src);
5406 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5407 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5408 MEM_SCALAR_P (mem) = src_scalar_p;
5409 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5412 if (last_bytes && part_bytes_reg == NULL)
5415 if (BYTES_BIG_ENDIAN && last_bytes)
5417 rtx tmp = gen_reg_rtx (SImode);
5419 /* The bytes we want are in the top end of the word. */
5420 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5421 GEN_INT (8 * (4 - last_bytes))));
5422 part_bytes_reg = tmp;
5426 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5427 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5428 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5429 MEM_SCALAR_P (mem) = dst_scalar_p;
5430 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5434 tmp = gen_reg_rtx (SImode);
5435 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5436 part_bytes_reg = tmp;
5445 mem = gen_rtx_MEM (HImode, dst);
5446 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5447 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5448 MEM_SCALAR_P (mem) = dst_scalar_p;
5449 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5453 rtx tmp = gen_reg_rtx (SImode);
5455 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
5456 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5457 part_bytes_reg = tmp;
5463 mem = gen_rtx_MEM (QImode, dst);
5464 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5465 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5466 MEM_SCALAR_P (mem) = dst_scalar_p;
5467 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5474 /* Generate a memory reference for a half word, such that it will be loaded
5475 into the top 16 bits of the word. We can assume that the address is
5476 known to be alignable and of the form reg, or plus (reg, const). */
5479 arm_gen_rotated_half_load (memref)
5482 HOST_WIDE_INT offset = 0;
5483 rtx base = XEXP (memref, 0);
5485 if (GET_CODE (base) == PLUS)
5487 offset = INTVAL (XEXP (base, 1));
5488 base = XEXP (base, 0);
5491 /* If we aren't allowed to generate unaligned addresses, then fail. */
5492 if (TARGET_MMU_TRAPS
5493 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5496 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5498 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5501 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5504 /* Select a dominance comparison mode if possible. We support three forms.
5505 COND_OR == 0 => (X && Y)
5506 COND_OR == 1 => ((! X( || Y)
5507 COND_OR == 2 => (X || Y)
5508 If we are unable to support a dominance comparison we return CC mode.
5509 This will then fail to match for the RTL expressions that generate this
5512 static enum machine_mode
5513 select_dominance_cc_mode (x, y, cond_or)
5516 HOST_WIDE_INT cond_or;
5518 enum rtx_code cond1, cond2;
5521 /* Currently we will probably get the wrong result if the individual
5522 comparisons are not simple. This also ensures that it is safe to
5523 reverse a comparison if necessary. */
5524 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5526 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5530 /* The if_then_else variant of this tests the second condition if the
5531 first passes, but is true if the first fails. Reverse the first
5532 condition to get a true "inclusive-or" expression. */
5534 cond1 = reverse_condition (cond1);
5536 /* If the comparisons are not equal, and one doesn't dominate the other,
5537 then we can't do this. */
5539 && !comparison_dominates_p (cond1, cond2)
5540 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5545 enum rtx_code temp = cond1;
5553 if (cond2 == EQ || !cond_or)
5558 case LE: return CC_DLEmode;
5559 case LEU: return CC_DLEUmode;
5560 case GE: return CC_DGEmode;
5561 case GEU: return CC_DGEUmode;
5568 if (cond2 == LT || !cond_or)
5577 if (cond2 == GT || !cond_or)
5586 if (cond2 == LTU || !cond_or)
5595 if (cond2 == GTU || !cond_or)
5603 /* The remaining cases only occur when both comparisons are the
5628 arm_select_cc_mode (op, x, y)
5633 /* All floating point compares return CCFP if it is an equality
5634 comparison, and CCFPE otherwise. */
5635 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5664 /* A compare with a shifted operand. Because of canonicalization, the
5665 comparison will have to be swapped when we emit the assembler. */
5666 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5667 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5668 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5669 || GET_CODE (x) == ROTATERT))
5672 /* This is a special case that is used by combine to allow a
5673 comparison of a shifted byte load to be split into a zero-extend
5674 followed by a comparison of the shifted integer (only valid for
5675 equalities and unsigned inequalities). */
5676 if (GET_MODE (x) == SImode
5677 && GET_CODE (x) == ASHIFT
5678 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5679 && GET_CODE (XEXP (x, 0)) == SUBREG
5680 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5681 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5682 && (op == EQ || op == NE
5683 || op == GEU || op == GTU || op == LTU || op == LEU)
5684 && GET_CODE (y) == CONST_INT)
5687 /* A construct for a conditional compare, if the false arm contains
5688 0, then both conditions must be true, otherwise either condition
5689 must be true. Not all conditions are possible, so CCmode is
5690 returned if it can't be done. */
5691 if (GET_CODE (x) == IF_THEN_ELSE
5692 && (XEXP (x, 2) == const0_rtx
5693 || XEXP (x, 2) == const1_rtx)
5694 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5695 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5696 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5697 INTVAL (XEXP (x, 2)));
5699 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5700 if (GET_CODE (x) == AND
5701 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5702 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5703 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
5705 if (GET_CODE (x) == IOR
5706 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5707 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5708 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
5710 /* An operation that sets the condition codes as a side-effect, the
5711 V flag is not set correctly, so we can only use comparisons where
5712 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5714 if (GET_MODE (x) == SImode
5716 && (op == EQ || op == NE || op == LT || op == GE)
5717 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5718 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5719 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5720 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5721 || GET_CODE (x) == LSHIFTRT
5722 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5723 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
5726 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
5729 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
5730 && GET_CODE (x) == PLUS
5731 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
5737 /* X and Y are two things to compare using CODE. Emit the compare insn and
5738 return the rtx for register 0 in the proper mode. FP means this is a
5739 floating point compare: I don't think that it is needed on the arm. */
5742 arm_gen_compare_reg (code, x, y)
5746 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
5747 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
5749 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5750 gen_rtx_COMPARE (mode, x, y)));
5755 /* Generate a sequence of insns that will generate the correct return
5756 address mask depending on the physical architecture that the program
5760 arm_gen_return_addr_mask ()
5762 rtx reg = gen_reg_rtx (Pmode);
5764 emit_insn (gen_return_addr_mask (reg));
5769 arm_reload_in_hi (operands)
5772 rtx ref = operands[1];
5774 HOST_WIDE_INT offset = 0;
5776 if (GET_CODE (ref) == SUBREG)
5778 offset = SUBREG_BYTE (ref);
5779 ref = SUBREG_REG (ref);
5782 if (GET_CODE (ref) == REG)
5784 /* We have a pseudo which has been spilt onto the stack; there
5785 are two cases here: the first where there is a simple
5786 stack-slot replacement and a second where the stack-slot is
5787 out of range, or is used as a subreg. */
5788 if (reg_equiv_mem[REGNO (ref)])
5790 ref = reg_equiv_mem[REGNO (ref)];
5791 base = find_replacement (&XEXP (ref, 0));
5794 /* The slot is out of range, or was dressed up in a SUBREG. */
5795 base = reg_equiv_address[REGNO (ref)];
5798 base = find_replacement (&XEXP (ref, 0));
5800 /* Handle the case where the address is too complex to be offset by 1. */
5801 if (GET_CODE (base) == MINUS
5802 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5804 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5806 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5809 else if (GET_CODE (base) == PLUS)
5811 /* The addend must be CONST_INT, or we would have dealt with it above. */
5812 HOST_WIDE_INT hi, lo;
5814 offset += INTVAL (XEXP (base, 1));
5815 base = XEXP (base, 0);
5817 /* Rework the address into a legal sequence of insns. */
5818 /* Valid range for lo is -4095 -> 4095 */
5821 : -((-offset) & 0xfff));
5823 /* Corner case, if lo is the max offset then we would be out of range
5824 once we have added the additional 1 below, so bump the msb into the
5825 pre-loading insn(s). */
5829 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5830 ^ (HOST_WIDE_INT) 0x80000000)
5831 - (HOST_WIDE_INT) 0x80000000);
5833 if (hi + lo != offset)
5838 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5840 /* Get the base address; addsi3 knows how to handle constants
5841 that require more than one insn. */
5842 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5848 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5849 emit_insn (gen_zero_extendqisi2 (scratch,
5850 gen_rtx_MEM (QImode,
5851 plus_constant (base,
5853 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5854 gen_rtx_MEM (QImode,
5855 plus_constant (base,
5857 if (!BYTES_BIG_ENDIAN)
5858 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5859 gen_rtx_IOR (SImode,
5862 gen_rtx_SUBREG (SImode, operands[0], 0),
5866 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5867 gen_rtx_IOR (SImode,
5868 gen_rtx_ASHIFT (SImode, scratch,
5870 gen_rtx_SUBREG (SImode, operands[0],
5874 /* Handle storing a half-word to memory during reload by synthesising as two
5875 byte stores. Take care not to clobber the input values until after we
5876 have moved them somewhere safe. This code assumes that if the DImode
5877 scratch in operands[2] overlaps either the input value or output address
5878 in some way, then that value must die in this insn (we absolutely need
5879 two scratch registers for some corner cases). */
5882 arm_reload_out_hi (operands)
5885 rtx ref = operands[0];
5886 rtx outval = operands[1];
5888 HOST_WIDE_INT offset = 0;
5890 if (GET_CODE (ref) == SUBREG)
5892 offset = SUBREG_BYTE (ref);
5893 ref = SUBREG_REG (ref);
5896 if (GET_CODE (ref) == REG)
5898 /* We have a pseudo which has been spilt onto the stack; there
5899 are two cases here: the first where there is a simple
5900 stack-slot replacement and a second where the stack-slot is
5901 out of range, or is used as a subreg. */
5902 if (reg_equiv_mem[REGNO (ref)])
5904 ref = reg_equiv_mem[REGNO (ref)];
5905 base = find_replacement (&XEXP (ref, 0));
5908 /* The slot is out of range, or was dressed up in a SUBREG. */
5909 base = reg_equiv_address[REGNO (ref)];
5912 base = find_replacement (&XEXP (ref, 0));
5914 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5916 /* Handle the case where the address is too complex to be offset by 1. */
5917 if (GET_CODE (base) == MINUS
5918 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5920 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5922 /* Be careful not to destroy OUTVAL. */
5923 if (reg_overlap_mentioned_p (base_plus, outval))
5925 /* Updating base_plus might destroy outval, see if we can
5926 swap the scratch and base_plus. */
5927 if (!reg_overlap_mentioned_p (scratch, outval))
5930 scratch = base_plus;
5935 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5937 /* Be conservative and copy OUTVAL into the scratch now,
5938 this should only be necessary if outval is a subreg
5939 of something larger than a word. */
5940 /* XXX Might this clobber base? I can't see how it can,
5941 since scratch is known to overlap with OUTVAL, and
5942 must be wider than a word. */
5943 emit_insn (gen_movhi (scratch_hi, outval));
5944 outval = scratch_hi;
5948 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5951 else if (GET_CODE (base) == PLUS)
5953 /* The addend must be CONST_INT, or we would have dealt with it above. */
5954 HOST_WIDE_INT hi, lo;
5956 offset += INTVAL (XEXP (base, 1));
5957 base = XEXP (base, 0);
5959 /* Rework the address into a legal sequence of insns. */
5960 /* Valid range for lo is -4095 -> 4095 */
5963 : -((-offset) & 0xfff));
5965 /* Corner case, if lo is the max offset then we would be out of range
5966 once we have added the additional 1 below, so bump the msb into the
5967 pre-loading insn(s). */
5971 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5972 ^ (HOST_WIDE_INT) 0x80000000)
5973 - (HOST_WIDE_INT) 0x80000000);
5975 if (hi + lo != offset)
5980 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5982 /* Be careful not to destroy OUTVAL. */
5983 if (reg_overlap_mentioned_p (base_plus, outval))
5985 /* Updating base_plus might destroy outval, see if we
5986 can swap the scratch and base_plus. */
5987 if (!reg_overlap_mentioned_p (scratch, outval))
5990 scratch = base_plus;
5995 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5997 /* Be conservative and copy outval into scratch now,
5998 this should only be necessary if outval is a
5999 subreg of something larger than a word. */
6000 /* XXX Might this clobber base? I can't see how it
6001 can, since scratch is known to overlap with
6003 emit_insn (gen_movhi (scratch_hi, outval));
6004 outval = scratch_hi;
6008 /* Get the base address; addsi3 knows how to handle constants
6009 that require more than one insn. */
6010 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6016 if (BYTES_BIG_ENDIAN)
6018 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6019 plus_constant (base, offset + 1)),
6020 gen_lowpart (QImode, outval)));
6021 emit_insn (gen_lshrsi3 (scratch,
6022 gen_rtx_SUBREG (SImode, outval, 0),
6024 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6025 gen_lowpart (QImode, scratch)));
6029 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6030 gen_lowpart (QImode, outval)));
6031 emit_insn (gen_lshrsi3 (scratch,
6032 gen_rtx_SUBREG (SImode, outval, 0),
6034 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6035 plus_constant (base, offset + 1)),
6036 gen_lowpart (QImode, scratch)));
6040 /* Print a symbolic form of X to the debug file, F. */
6043 arm_print_value (f, x)
6047 switch (GET_CODE (x))
6050 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6054 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6058 fprintf (f, "\"%s\"", XSTR (x, 0));
6062 fprintf (f, "`%s'", XSTR (x, 0));
6066 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6070 arm_print_value (f, XEXP (x, 0));
6074 arm_print_value (f, XEXP (x, 0));
6076 arm_print_value (f, XEXP (x, 1));
6084 fprintf (f, "????");
6089 /* Routines for manipulation of the constant pool. */
6091 /* Arm instructions cannot load a large constant directly into a
6092 register; they have to come from a pc relative load. The constant
6093 must therefore be placed in the addressable range of the pc
6094 relative load. Depending on the precise pc relative load
6095 instruction the range is somewhere between 256 bytes and 4k. This
6096 means that we often have to dump a constant inside a function, and
6097 generate code to branch around it.
6099 It is important to minimize this, since the branches will slow
6100 things down and make the code larger.
6102 Normally we can hide the table after an existing unconditional
6103 branch so that there is no interruption of the flow, but in the
6104 worst case the code looks like this:
6122 We fix this by performing a scan after scheduling, which notices
6123 which instructions need to have their operands fetched from the
6124 constant table and builds the table.
6126 The algorithm starts by building a table of all the constants that
6127 need fixing up and all the natural barriers in the function (places
6128 where a constant table can be dropped without breaking the flow).
6129 For each fixup we note how far the pc-relative replacement will be
6130 able to reach and the offset of the instruction into the function.
6132 Having built the table we then group the fixes together to form
6133 tables that are as large as possible (subject to addressing
6134 constraints) and emit each table of constants after the last
6135 barrier that is within range of all the instructions in the group.
6136 If a group does not contain a barrier, then we forcibly create one
6137 by inserting a jump instruction into the flow. Once the table has
6138 been inserted, the insns are then modified to reference the
6139 relevant entry in the pool.
6141 Possible enhancements to the algorithm (not implemented) are:
6143 1) For some processors and object formats, there may be benefit in
6144 aligning the pools to the start of cache lines; this alignment
6145 would need to be taken into account when calculating addressability
6148 /* These typedefs are located at the start of this file, so that
6149 they can be used in the prototypes there. This comment is to
6150 remind readers of that fact so that the following structures
6151 can be understood more easily.
6153 typedef struct minipool_node Mnode;
6154 typedef struct minipool_fixup Mfix; */
6156 struct minipool_node
6158 /* Doubly linked chain of entries. */
6161 /* The maximum offset into the code that this entry can be placed. While
6162 pushing fixes for forward references, all entries are sorted in order
6163 of increasing max_address. */
6164 HOST_WIDE_INT max_address;
6165 /* Similarly for an entry inserted for a backwards ref. */
6166 HOST_WIDE_INT min_address;
6167 /* The number of fixes referencing this entry. This can become zero
6168 if we "unpush" an entry. In this case we ignore the entry when we
6169 come to emit the code. */
6171 /* The offset from the start of the minipool. */
6172 HOST_WIDE_INT offset;
6173 /* The value in table. */
6175 /* The mode of value. */
6176 enum machine_mode mode;
6180 struct minipool_fixup
6184 HOST_WIDE_INT address;
6186 enum machine_mode mode;
6190 HOST_WIDE_INT forwards;
6191 HOST_WIDE_INT backwards;
6194 /* Fixes less than a word need padding out to a word boundary. */
6195 #define MINIPOOL_FIX_SIZE(mode) \
6196 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6198 static Mnode * minipool_vector_head;
6199 static Mnode * minipool_vector_tail;
6200 static rtx minipool_vector_label;
6202 /* The linked list of all minipool fixes required for this function. */
6203 Mfix * minipool_fix_head;
6204 Mfix * minipool_fix_tail;
6205 /* The fix entry for the current minipool, once it has been placed. */
6206 Mfix * minipool_barrier;
6208 /* Determines if INSN is the start of a jump table. Returns the end
6209 of the TABLE or NULL_RTX. */
6212 is_jump_table (insn)
6217 if (GET_CODE (insn) == JUMP_INSN
6218 && JUMP_LABEL (insn) != NULL
6219 && ((table = next_real_insn (JUMP_LABEL (insn)))
6220 == next_real_insn (insn))
6222 && GET_CODE (table) == JUMP_INSN
6223 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6224 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6230 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6231 #define JUMP_TABLES_IN_TEXT_SECTION 0
6234 static HOST_WIDE_INT
6235 get_jump_table_size (insn)
6238 /* ADDR_VECs only take room if read-only data does into the text
6240 if (JUMP_TABLES_IN_TEXT_SECTION
6241 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6246 rtx body = PATTERN (insn);
6247 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6249 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6255 /* Move a minipool fix MP from its current location to before MAX_MP.
6256 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6257 contrains may need updating. */
6260 move_minipool_fix_forward_ref (mp, max_mp, max_address)
6263 HOST_WIDE_INT max_address;
6265 /* This should never be true and the code below assumes these are
6272 if (max_address < mp->max_address)
6273 mp->max_address = max_address;
6277 if (max_address > max_mp->max_address - mp->fix_size)
6278 mp->max_address = max_mp->max_address - mp->fix_size;
6280 mp->max_address = max_address;
6282 /* Unlink MP from its current position. Since max_mp is non-null,
6283 mp->prev must be non-null. */
6284 mp->prev->next = mp->next;
6285 if (mp->next != NULL)
6286 mp->next->prev = mp->prev;
6288 minipool_vector_tail = mp->prev;
6290 /* Re-insert it before MAX_MP. */
6292 mp->prev = max_mp->prev;
6295 if (mp->prev != NULL)
6296 mp->prev->next = mp;
6298 minipool_vector_head = mp;
6301 /* Save the new entry. */
6304 /* Scan over the preceding entries and adjust their addresses as
6306 while (mp->prev != NULL
6307 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6309 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6316 /* Add a constant to the minipool for a forward reference. Returns the
6317 node added or NULL if the constant will not fit in this pool. */
6320 add_minipool_forward_ref (fix)
6323 /* If set, max_mp is the first pool_entry that has a lower
6324 constraint than the one we are trying to add. */
6325 Mnode * max_mp = NULL;
6326 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6329 /* If this fix's address is greater than the address of the first
6330 entry, then we can't put the fix in this pool. We subtract the
6331 size of the current fix to ensure that if the table is fully
6332 packed we still have enough room to insert this value by suffling
6333 the other fixes forwards. */
6334 if (minipool_vector_head &&
6335 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6338 /* Scan the pool to see if a constant with the same value has
6339 already been added. While we are doing this, also note the
6340 location where we must insert the constant if it doesn't already
6342 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6344 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6345 && fix->mode == mp->mode
6346 && (GET_CODE (fix->value) != CODE_LABEL
6347 || (CODE_LABEL_NUMBER (fix->value)
6348 == CODE_LABEL_NUMBER (mp->value)))
6349 && rtx_equal_p (fix->value, mp->value))
6351 /* More than one fix references this entry. */
6353 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6356 /* Note the insertion point if necessary. */
6358 && mp->max_address > max_address)
6362 /* The value is not currently in the minipool, so we need to create
6363 a new entry for it. If MAX_MP is NULL, the entry will be put on
6364 the end of the list since the placement is less constrained than
6365 any existing entry. Otherwise, we insert the new fix before
6366 MAX_MP and, if necessary, adjust the constraints on the other
6368 mp = xmalloc (sizeof (* mp));
6369 mp->fix_size = fix->fix_size;
6370 mp->mode = fix->mode;
6371 mp->value = fix->value;
6373 /* Not yet required for a backwards ref. */
6374 mp->min_address = -65536;
6378 mp->max_address = max_address;
6380 mp->prev = minipool_vector_tail;
6382 if (mp->prev == NULL)
6384 minipool_vector_head = mp;
6385 minipool_vector_label = gen_label_rtx ();
6388 mp->prev->next = mp;
6390 minipool_vector_tail = mp;
6394 if (max_address > max_mp->max_address - mp->fix_size)
6395 mp->max_address = max_mp->max_address - mp->fix_size;
6397 mp->max_address = max_address;
6400 mp->prev = max_mp->prev;
6402 if (mp->prev != NULL)
6403 mp->prev->next = mp;
6405 minipool_vector_head = mp;
6408 /* Save the new entry. */
6411 /* Scan over the preceding entries and adjust their addresses as
6413 while (mp->prev != NULL
6414 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6416 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6424 move_minipool_fix_backward_ref (mp, min_mp, min_address)
6427 HOST_WIDE_INT min_address;
6429 HOST_WIDE_INT offset;
6431 /* This should never be true, and the code below assumes these are
6438 if (min_address > mp->min_address)
6439 mp->min_address = min_address;
6443 /* We will adjust this below if it is too loose. */
6444 mp->min_address = min_address;
6446 /* Unlink MP from its current position. Since min_mp is non-null,
6447 mp->next must be non-null. */
6448 mp->next->prev = mp->prev;
6449 if (mp->prev != NULL)
6450 mp->prev->next = mp->next;
6452 minipool_vector_head = mp->next;
6454 /* Reinsert it after MIN_MP. */
6456 mp->next = min_mp->next;
6458 if (mp->next != NULL)
6459 mp->next->prev = mp;
6461 minipool_vector_tail = mp;
6467 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6469 mp->offset = offset;
6470 if (mp->refcount > 0)
6471 offset += mp->fix_size;
6473 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6474 mp->next->min_address = mp->min_address + mp->fix_size;
6480 /* Add a constant to the minipool for a backward reference. Returns the
6481 node added or NULL if the constant will not fit in this pool.
6483 Note that the code for insertion for a backwards reference can be
6484 somewhat confusing because the calculated offsets for each fix do
6485 not take into account the size of the pool (which is still under
6489 add_minipool_backward_ref (fix)
6492 /* If set, min_mp is the last pool_entry that has a lower constraint
6493 than the one we are trying to add. */
6494 Mnode * min_mp = NULL;
6495 /* This can be negative, since it is only a constraint. */
6496 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6499 /* If we can't reach the current pool from this insn, or if we can't
6500 insert this entry at the end of the pool without pushing other
6501 fixes out of range, then we don't try. This ensures that we
6502 can't fail later on. */
6503 if (min_address >= minipool_barrier->address
6504 || (minipool_vector_tail->min_address + fix->fix_size
6505 >= minipool_barrier->address))
6508 /* Scan the pool to see if a constant with the same value has
6509 already been added. While we are doing this, also note the
6510 location where we must insert the constant if it doesn't already
6512 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6514 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6515 && fix->mode == mp->mode
6516 && (GET_CODE (fix->value) != CODE_LABEL
6517 || (CODE_LABEL_NUMBER (fix->value)
6518 == CODE_LABEL_NUMBER (mp->value)))
6519 && rtx_equal_p (fix->value, mp->value)
6520 /* Check that there is enough slack to move this entry to the
6521 end of the table (this is conservative). */
6523 > (minipool_barrier->address
6524 + minipool_vector_tail->offset
6525 + minipool_vector_tail->fix_size)))
6528 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6532 mp->min_address += fix->fix_size;
6535 /* Note the insertion point if necessary. */
6536 if (mp->min_address < min_address)
6538 else if (mp->max_address
6539 < minipool_barrier->address + mp->offset + fix->fix_size)
6541 /* Inserting before this entry would push the fix beyond
6542 its maximum address (which can happen if we have
6543 re-located a forwards fix); force the new fix to come
6546 min_address = mp->min_address + fix->fix_size;
6551 /* We need to create a new entry. */
6552 mp = xmalloc (sizeof (* mp));
6553 mp->fix_size = fix->fix_size;
6554 mp->mode = fix->mode;
6555 mp->value = fix->value;
6557 mp->max_address = minipool_barrier->address + 65536;
6559 mp->min_address = min_address;
6564 mp->next = minipool_vector_head;
6566 if (mp->next == NULL)
6568 minipool_vector_tail = mp;
6569 minipool_vector_label = gen_label_rtx ();
6572 mp->next->prev = mp;
6574 minipool_vector_head = mp;
6578 mp->next = min_mp->next;
6582 if (mp->next != NULL)
6583 mp->next->prev = mp;
6585 minipool_vector_tail = mp;
6588 /* Save the new entry. */
6596 /* Scan over the following entries and adjust their offsets. */
6597 while (mp->next != NULL)
6599 if (mp->next->min_address < mp->min_address + mp->fix_size)
6600 mp->next->min_address = mp->min_address + mp->fix_size;
6603 mp->next->offset = mp->offset + mp->fix_size;
6605 mp->next->offset = mp->offset;
6614 assign_minipool_offsets (barrier)
6617 HOST_WIDE_INT offset = 0;
6620 minipool_barrier = barrier;
6622 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6624 mp->offset = offset;
6626 if (mp->refcount > 0)
6627 offset += mp->fix_size;
6631 /* Output the literal table */
6633 dump_minipool (scan)
6640 fprintf (rtl_dump_file,
6641 ";; Emitting minipool after insn %u; address %ld\n",
6642 INSN_UID (scan), (unsigned long) minipool_barrier->address);
6644 scan = emit_label_after (gen_label_rtx (), scan);
6645 scan = emit_insn_after (gen_align_4 (), scan);
6646 scan = emit_label_after (minipool_vector_label, scan);
6648 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6650 if (mp->refcount > 0)
6654 fprintf (rtl_dump_file,
6655 ";; Offset %u, min %ld, max %ld ",
6656 (unsigned) mp->offset, (unsigned long) mp->min_address,
6657 (unsigned long) mp->max_address);
6658 arm_print_value (rtl_dump_file, mp->value);
6659 fputc ('\n', rtl_dump_file);
6662 switch (mp->fix_size)
6664 #ifdef HAVE_consttable_1
6666 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6670 #ifdef HAVE_consttable_2
6672 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6676 #ifdef HAVE_consttable_4
6678 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6682 #ifdef HAVE_consttable_8
6684 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6698 minipool_vector_head = minipool_vector_tail = NULL;
6699 scan = emit_insn_after (gen_consttable_end (), scan);
6700 scan = emit_barrier_after (scan);
6703 /* Return the cost of forcibly inserting a barrier after INSN. */
6706 arm_barrier_cost (insn)
6709 /* Basing the location of the pool on the loop depth is preferable,
6710 but at the moment, the basic block information seems to be
6711 corrupt by this stage of the compilation. */
6713 rtx next = next_nonnote_insn (insn);
6715 if (next != NULL && GET_CODE (next) == CODE_LABEL)
6718 switch (GET_CODE (insn))
6721 /* It will always be better to place the table before the label, rather
6730 return base_cost - 10;
6733 return base_cost + 10;
6737 /* Find the best place in the insn stream in the range
6738 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6739 Create the barrier by inserting a jump and add a new fix entry for
6743 create_fix_barrier (fix, max_address)
6745 HOST_WIDE_INT max_address;
6747 HOST_WIDE_INT count = 0;
6749 rtx from = fix->insn;
6750 rtx selected = from;
6752 HOST_WIDE_INT selected_address;
6754 HOST_WIDE_INT max_count = max_address - fix->address;
6755 rtx label = gen_label_rtx ();
6757 selected_cost = arm_barrier_cost (from);
6758 selected_address = fix->address;
6760 while (from && count < max_count)
6765 /* This code shouldn't have been called if there was a natural barrier
6767 if (GET_CODE (from) == BARRIER)
6770 /* Count the length of this insn. */
6771 count += get_attr_length (from);
6773 /* If there is a jump table, add its length. */
6774 tmp = is_jump_table (from);
6777 count += get_jump_table_size (tmp);
6779 /* Jump tables aren't in a basic block, so base the cost on
6780 the dispatch insn. If we select this location, we will
6781 still put the pool after the table. */
6782 new_cost = arm_barrier_cost (from);
6784 if (count < max_count && new_cost <= selected_cost)
6787 selected_cost = new_cost;
6788 selected_address = fix->address + count;
6791 /* Continue after the dispatch table. */
6792 from = NEXT_INSN (tmp);
6796 new_cost = arm_barrier_cost (from);
6798 if (count < max_count && new_cost <= selected_cost)
6801 selected_cost = new_cost;
6802 selected_address = fix->address + count;
6805 from = NEXT_INSN (from);
6808 /* Create a new JUMP_INSN that branches around a barrier. */
6809 from = emit_jump_insn_after (gen_jump (label), selected);
6810 JUMP_LABEL (from) = label;
6811 barrier = emit_barrier_after (from);
6812 emit_label_after (label, barrier);
6814 /* Create a minipool barrier entry for the new barrier. */
6815 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6816 new_fix->insn = barrier;
6817 new_fix->address = selected_address;
6818 new_fix->next = fix->next;
6819 fix->next = new_fix;
6824 /* Record that there is a natural barrier in the insn stream at
6827 push_minipool_barrier (insn, address)
6829 HOST_WIDE_INT address;
6831 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6834 fix->address = address;
6837 if (minipool_fix_head != NULL)
6838 minipool_fix_tail->next = fix;
6840 minipool_fix_head = fix;
6842 minipool_fix_tail = fix;
6845 /* Record INSN, which will need fixing up to load a value from the
6846 minipool. ADDRESS is the offset of the insn since the start of the
6847 function; LOC is a pointer to the part of the insn which requires
6848 fixing; VALUE is the constant that must be loaded, which is of type
6851 push_minipool_fix (insn, address, loc, mode, value)
6853 HOST_WIDE_INT address;
6855 enum machine_mode mode;
6858 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6860 #ifdef AOF_ASSEMBLER
6861 /* PIC symbol refereneces need to be converted into offsets into the
6863 /* XXX This shouldn't be done here. */
6864 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6865 value = aof_pic_entry (value);
6866 #endif /* AOF_ASSEMBLER */
6869 fix->address = address;
6872 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6874 fix->forwards = get_attr_pool_range (insn);
6875 fix->backwards = get_attr_neg_pool_range (insn);
6876 fix->minipool = NULL;
6878 /* If an insn doesn't have a range defined for it, then it isn't
6879 expecting to be reworked by this code. Better to abort now than
6880 to generate duff assembly code. */
6881 if (fix->forwards == 0 && fix->backwards == 0)
6886 fprintf (rtl_dump_file,
6887 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6888 GET_MODE_NAME (mode),
6889 INSN_UID (insn), (unsigned long) address,
6890 -1 * (long)fix->backwards, (long)fix->forwards);
6891 arm_print_value (rtl_dump_file, fix->value);
6892 fprintf (rtl_dump_file, "\n");
6895 /* Add it to the chain of fixes. */
6898 if (minipool_fix_head != NULL)
6899 minipool_fix_tail->next = fix;
6901 minipool_fix_head = fix;
6903 minipool_fix_tail = fix;
6906 /* Scan INSN and note any of its operands that need fixing. */
6909 note_invalid_constants (insn, address)
6911 HOST_WIDE_INT address;
6915 extract_insn (insn);
6917 if (!constrain_operands (1))
6918 fatal_insn_not_found (insn);
6920 /* Fill in recog_op_alt with information about the constraints of this
6922 preprocess_constraints ();
6924 for (opno = 0; opno < recog_data.n_operands; opno++)
6926 /* Things we need to fix can only occur in inputs. */
6927 if (recog_data.operand_type[opno] != OP_IN)
6930 /* If this alternative is a memory reference, then any mention
6931 of constants in this alternative is really to fool reload
6932 into allowing us to accept one there. We need to fix them up
6933 now so that we output the right code. */
6934 if (recog_op_alt[opno][which_alternative].memory_ok)
6936 rtx op = recog_data.operand[opno];
6938 if (CONSTANT_P (op))
6939 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6940 recog_data.operand_mode[opno], op);
6942 /* RWE: Now we look correctly at the operands for the insn,
6943 this shouldn't be needed any more. */
6944 #ifndef AOF_ASSEMBLER
6945 /* XXX Is this still needed? */
6946 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
6947 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6948 recog_data.operand_mode[opno],
6949 XVECEXP (op, 0, 0));
6952 else if (GET_CODE (op) == MEM
6953 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
6954 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
6955 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6956 recog_data.operand_mode[opno],
6957 get_pool_constant (XEXP (op, 0)));
6967 HOST_WIDE_INT address = 0;
6970 minipool_fix_head = minipool_fix_tail = NULL;
6972 /* The first insn must always be a note, or the code below won't
6973 scan it properly. */
6974 if (GET_CODE (first) != NOTE)
6977 /* Scan all the insns and record the operands that will need fixing. */
6978 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
6980 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6981 && (is_cirrus_insn (insn)
6982 || GET_CODE (insn) == JUMP_INSN
6983 || is_load_address (insn)))
6984 cirrus_reorg (insn);
6986 if (GET_CODE (insn) == BARRIER)
6987 push_minipool_barrier (insn, address);
6988 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
6989 || GET_CODE (insn) == JUMP_INSN)
6993 note_invalid_constants (insn, address);
6994 address += get_attr_length (insn);
6996 /* If the insn is a vector jump, add the size of the table
6997 and skip the table. */
6998 if ((table = is_jump_table (insn)) != NULL)
7000 address += get_jump_table_size (table);
7006 fix = minipool_fix_head;
7008 /* Now scan the fixups and perform the required changes. */
7013 Mfix * last_added_fix;
7014 Mfix * last_barrier = NULL;
7017 /* Skip any further barriers before the next fix. */
7018 while (fix && GET_CODE (fix->insn) == BARRIER)
7021 /* No more fixes. */
7025 last_added_fix = NULL;
7027 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7029 if (GET_CODE (ftmp->insn) == BARRIER)
7031 if (ftmp->address >= minipool_vector_head->max_address)
7034 last_barrier = ftmp;
7036 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7039 last_added_fix = ftmp; /* Keep track of the last fix added. */
7042 /* If we found a barrier, drop back to that; any fixes that we
7043 could have reached but come after the barrier will now go in
7044 the next mini-pool. */
7045 if (last_barrier != NULL)
7047 /* Reduce the refcount for those fixes that won't go into this
7049 for (fdel = last_barrier->next;
7050 fdel && fdel != ftmp;
7053 fdel->minipool->refcount--;
7054 fdel->minipool = NULL;
7057 ftmp = last_barrier;
7061 /* ftmp is first fix that we can't fit into this pool and
7062 there no natural barriers that we could use. Insert a
7063 new barrier in the code somewhere between the previous
7064 fix and this one, and arrange to jump around it. */
7065 HOST_WIDE_INT max_address;
7067 /* The last item on the list of fixes must be a barrier, so
7068 we can never run off the end of the list of fixes without
7069 last_barrier being set. */
7073 max_address = minipool_vector_head->max_address;
7074 /* Check that there isn't another fix that is in range that
7075 we couldn't fit into this pool because the pool was
7076 already too large: we need to put the pool before such an
7078 if (ftmp->address < max_address)
7079 max_address = ftmp->address;
7081 last_barrier = create_fix_barrier (last_added_fix, max_address);
7084 assign_minipool_offsets (last_barrier);
7088 if (GET_CODE (ftmp->insn) != BARRIER
7089 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7096 /* Scan over the fixes we have identified for this pool, fixing them
7097 up and adding the constants to the pool itself. */
7098 for (this_fix = fix; this_fix && ftmp != this_fix;
7099 this_fix = this_fix->next)
7100 if (GET_CODE (this_fix->insn) != BARRIER)
7103 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7104 minipool_vector_label),
7105 this_fix->minipool->offset);
7106 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7109 dump_minipool (last_barrier->insn);
7113 /* From now on we must synthesize any constants that we can't handle
7114 directly. This can happen if the RTL gets split during final
7115 instruction generation. */
7116 after_arm_reorg = 1;
7118 /* Free the minipool memory. */
7119 obstack_free (&minipool_obstack, minipool_startobj);
7122 /* Routines to output assembly language. */
7124 /* If the rtx is the correct value then return the string of the number.
7125 In this way we can ensure that valid double constants are generated even
7126 when cross compiling. */
7129 fp_immediate_constant (x)
7135 if (!fpa_consts_inited)
7138 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7139 for (i = 0; i < 8; i++)
7140 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
7141 return strings_fpa[i];
7146 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7149 fp_const_from_val (r)
7150 REAL_VALUE_TYPE * r;
7154 if (!fpa_consts_inited)
7157 for (i = 0; i < 8; i++)
7158 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
7159 return strings_fpa[i];
7164 /* Output the operands of a LDM/STM instruction to STREAM.
7165 MASK is the ARM register set mask of which only bits 0-15 are important.
7166 REG is the base register, either the frame pointer or the stack pointer,
7167 INSTR is the possibly suffixed load or store instruction. */
7170 print_multi_reg (stream, instr, reg, mask)
7177 int not_first = FALSE;
7179 fputc ('\t', stream);
7180 asm_fprintf (stream, instr, reg);
7181 fputs (", {", stream);
7183 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7184 if (mask & (1 << i))
7187 fprintf (stream, ", ");
7189 asm_fprintf (stream, "%r", i);
7193 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
7196 /* Output a 'call' insn. */
7199 output_call (operands)
7202 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7204 if (REGNO (operands[0]) == LR_REGNUM)
7206 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7207 output_asm_insn ("mov%?\t%0, %|lr", operands);
7210 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7212 if (TARGET_INTERWORK)
7213 output_asm_insn ("bx%?\t%0", operands);
7215 output_asm_insn ("mov%?\t%|pc, %0", operands);
7224 int something_changed = 0;
7226 int code = GET_CODE (x0);
7233 if (REGNO (x0) == LR_REGNUM)
7235 *x = gen_rtx_REG (SImode, IP_REGNUM);
7240 /* Scan through the sub-elements and change any references there. */
7241 fmt = GET_RTX_FORMAT (code);
7243 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7245 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
7246 else if (fmt[i] == 'E')
7247 for (j = 0; j < XVECLEN (x0, i); j++)
7248 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
7250 return something_changed;
7254 /* Output a 'call' insn that is a reference in memory. */
7257 output_call_mem (operands)
7260 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
7261 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
7262 if (eliminate_lr2ip (&operands[0]))
7263 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
7265 if (TARGET_INTERWORK)
7267 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7268 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7269 output_asm_insn ("bx%?\t%|ip", operands);
7273 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7274 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7281 /* Output a move from arm registers to an fpu registers.
7282 OPERANDS[0] is an fpu register.
7283 OPERANDS[1] is the first registers of an arm register pair. */
7286 output_mov_long_double_fpu_from_arm (operands)
7289 int arm_reg0 = REGNO (operands[1]);
7292 if (arm_reg0 == IP_REGNUM)
7295 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7296 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7297 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7299 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7300 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7305 /* Output a move from an fpu register to arm registers.
7306 OPERANDS[0] is the first registers of an arm register pair.
7307 OPERANDS[1] is an fpu register. */
7310 output_mov_long_double_arm_from_fpu (operands)
7313 int arm_reg0 = REGNO (operands[0]);
7316 if (arm_reg0 == IP_REGNUM)
7319 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7320 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7321 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7323 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7324 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7328 /* Output a move from arm registers to arm registers of a long double
7329 OPERANDS[0] is the destination.
7330 OPERANDS[1] is the source. */
7333 output_mov_long_double_arm_from_arm (operands)
7336 /* We have to be careful here because the two might overlap. */
7337 int dest_start = REGNO (operands[0]);
7338 int src_start = REGNO (operands[1]);
7342 if (dest_start < src_start)
7344 for (i = 0; i < 3; i++)
7346 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7347 ops[1] = gen_rtx_REG (SImode, src_start + i);
7348 output_asm_insn ("mov%?\t%0, %1", ops);
7353 for (i = 2; i >= 0; i--)
7355 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7356 ops[1] = gen_rtx_REG (SImode, src_start + i);
7357 output_asm_insn ("mov%?\t%0, %1", ops);
7365 /* Output a move from arm registers to an fpu registers.
7366 OPERANDS[0] is an fpu register.
7367 OPERANDS[1] is the first registers of an arm register pair. */
7370 output_mov_double_fpu_from_arm (operands)
7373 int arm_reg0 = REGNO (operands[1]);
7376 if (arm_reg0 == IP_REGNUM)
7379 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7380 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7381 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7382 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7386 /* Output a move from an fpu register to arm registers.
7387 OPERANDS[0] is the first registers of an arm register pair.
7388 OPERANDS[1] is an fpu register. */
7391 output_mov_double_arm_from_fpu (operands)
7394 int arm_reg0 = REGNO (operands[0]);
7397 if (arm_reg0 == IP_REGNUM)
7400 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7401 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7402 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7403 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7407 /* Output a move between double words.
7408 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7409 or MEM<-REG and all MEMs must be offsettable addresses. */
7412 output_move_double (operands)
7415 enum rtx_code code0 = GET_CODE (operands[0]);
7416 enum rtx_code code1 = GET_CODE (operands[1]);
7421 int reg0 = REGNO (operands[0]);
7423 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7427 int reg1 = REGNO (operands[1]);
7428 if (reg1 == IP_REGNUM)
7431 /* Ensure the second source is not overwritten. */
7432 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7433 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7435 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7437 else if (code1 == CONST_DOUBLE)
7439 if (GET_MODE (operands[1]) == DFmode)
7444 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7445 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7446 otherops[1] = GEN_INT (l[1]);
7447 operands[1] = GEN_INT (l[0]);
7449 else if (GET_MODE (operands[1]) != VOIDmode)
7451 else if (WORDS_BIG_ENDIAN)
7453 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7454 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7458 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7459 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7462 output_mov_immediate (operands);
7463 output_mov_immediate (otherops);
7465 else if (code1 == CONST_INT)
7467 #if HOST_BITS_PER_WIDE_INT > 32
7468 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7469 what the upper word is. */
7470 if (WORDS_BIG_ENDIAN)
7472 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7473 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7477 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7478 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7481 /* Sign extend the intval into the high-order word. */
7482 if (WORDS_BIG_ENDIAN)
7484 otherops[1] = operands[1];
7485 operands[1] = (INTVAL (operands[1]) < 0
7486 ? constm1_rtx : const0_rtx);
7489 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
7491 output_mov_immediate (otherops);
7492 output_mov_immediate (operands);
7494 else if (code1 == MEM)
7496 switch (GET_CODE (XEXP (operands[1], 0)))
7499 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
7503 abort (); /* Should never happen now. */
7507 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
7511 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
7515 abort (); /* Should never happen now. */
7520 output_asm_insn ("adr%?\t%0, %1", operands);
7521 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
7525 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
7526 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
7528 otherops[0] = operands[0];
7529 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
7530 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
7532 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
7534 if (GET_CODE (otherops[2]) == CONST_INT)
7536 switch ((int) INTVAL (otherops[2]))
7539 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
7542 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
7545 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
7549 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
7550 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
7552 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7555 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7558 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
7560 return "ldm%?ia\t%0, %M0";
7564 otherops[1] = adjust_address (operands[1], VOIDmode, 4);
7565 /* Take care of overlapping base/data reg. */
7566 if (reg_mentioned_p (operands[0], operands[1]))
7568 output_asm_insn ("ldr%?\t%0, %1", otherops);
7569 output_asm_insn ("ldr%?\t%0, %1", operands);
7573 output_asm_insn ("ldr%?\t%0, %1", operands);
7574 output_asm_insn ("ldr%?\t%0, %1", otherops);
7580 abort (); /* Constraints should prevent this. */
7582 else if (code0 == MEM && code1 == REG)
7584 if (REGNO (operands[1]) == IP_REGNUM)
7587 switch (GET_CODE (XEXP (operands[0], 0)))
7590 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
7594 abort (); /* Should never happen now. */
7598 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
7602 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
7606 abort (); /* Should never happen now. */
7610 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
7612 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
7615 output_asm_insn ("stm%?db\t%m0, %M1", operands);
7619 output_asm_insn ("stm%?da\t%m0, %M1", operands);
7623 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
7630 otherops[0] = adjust_address (operands[0], VOIDmode, 4);
7631 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
7632 output_asm_insn ("str%?\t%1, %0", operands);
7633 output_asm_insn ("str%?\t%1, %0", otherops);
7637 /* Constraints should prevent this. */
7644 /* Output an arbitrary MOV reg, #n.
7645 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7648 output_mov_immediate (operands)
7651 HOST_WIDE_INT n = INTVAL (operands[1]);
7653 /* Try to use one MOV. */
7654 if (const_ok_for_arm (n))
7655 output_asm_insn ("mov%?\t%0, %1", operands);
7657 /* Try to use one MVN. */
7658 else if (const_ok_for_arm (~n))
7660 operands[1] = GEN_INT (~n);
7661 output_asm_insn ("mvn%?\t%0, %1", operands);
7668 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7669 for (i = 0; i < 32; i ++)
7673 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
7674 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
7676 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
7682 /* Output an ADD r, s, #n where n may be too big for one instruction.
7683 If adding zero to one register, output nothing. */
7686 output_add_immediate (operands)
7689 HOST_WIDE_INT n = INTVAL (operands[2]);
7691 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
7694 output_multi_immediate (operands,
7695 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7698 output_multi_immediate (operands,
7699 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7706 /* Output a multiple immediate operation.
7707 OPERANDS is the vector of operands referred to in the output patterns.
7708 INSTR1 is the output pattern to use for the first constant.
7709 INSTR2 is the output pattern to use for subsequent constants.
7710 IMMED_OP is the index of the constant slot in OPERANDS.
7711 N is the constant value. */
7714 output_multi_immediate (operands, instr1, instr2, immed_op, n)
7716 const char * instr1;
7717 const char * instr2;
7721 #if HOST_BITS_PER_WIDE_INT > 32
7727 /* Quick and easy output. */
7728 operands[immed_op] = const0_rtx;
7729 output_asm_insn (instr1, operands);
7734 const char * instr = instr1;
7736 /* Note that n is never zero here (which would give no output). */
7737 for (i = 0; i < 32; i += 2)
7741 operands[immed_op] = GEN_INT (n & (255 << i));
7742 output_asm_insn (instr, operands);
7752 /* Return the appropriate ARM instruction for the operation code.
7753 The returned result should not be overwritten. OP is the rtx of the
7754 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7758 arithmetic_instr (op, shift_first_arg)
7760 int shift_first_arg;
7762 switch (GET_CODE (op))
7768 return shift_first_arg ? "rsb" : "sub";
7784 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7785 for the operation code. The returned result should not be overwritten.
7786 OP is the rtx code of the shift.
7787 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7791 shift_op (op, amountp)
7793 HOST_WIDE_INT *amountp;
7796 enum rtx_code code = GET_CODE (op);
7798 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
7800 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
7801 *amountp = INTVAL (XEXP (op, 1));
7824 /* We never have to worry about the amount being other than a
7825 power of 2, since this case can never be reloaded from a reg. */
7827 *amountp = int_log2 (*amountp);
7838 /* This is not 100% correct, but follows from the desire to merge
7839 multiplication by a power of 2 with the recognizer for a
7840 shift. >=32 is not a valid shift for "asl", so we must try and
7841 output a shift that produces the correct arithmetical result.
7842 Using lsr #32 is identical except for the fact that the carry bit
7843 is not set correctly if we set the flags; but we never use the
7844 carry bit from such an operation, so we can ignore that. */
7845 if (code == ROTATERT)
7846 /* Rotate is just modulo 32. */
7848 else if (*amountp != (*amountp & 31))
7855 /* Shifts of 0 are no-ops. */
7863 /* Obtain the shift from the POWER of two. */
7865 static HOST_WIDE_INT
7867 HOST_WIDE_INT power;
7869 HOST_WIDE_INT shift = 0;
7871 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7881 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7882 /bin/as is horribly restrictive. */
7883 #define MAX_ASCII_LEN 51
7886 output_ascii_pseudo_op (stream, p, len)
7888 const unsigned char * p;
7894 fputs ("\t.ascii\t\"", stream);
7896 for (i = 0; i < len; i++)
7900 if (len_so_far >= MAX_ASCII_LEN)
7902 fputs ("\"\n\t.ascii\t\"", stream);
7909 fputs ("\\t", stream);
7914 fputs ("\\f", stream);
7919 fputs ("\\b", stream);
7924 fputs ("\\r", stream);
7928 case TARGET_NEWLINE:
7929 fputs ("\\n", stream);
7931 if ((c >= ' ' && c <= '~')
7933 /* This is a good place for a line break. */
7934 len_so_far = MAX_ASCII_LEN;
7941 putc ('\\', stream);
7946 if (c >= ' ' && c <= '~')
7953 fprintf (stream, "\\%03o", c);
7960 fputs ("\"\n", stream);
7963 /* Compute the register sabe mask for registers 0 through 12
7964 inclusive. This code is used by both arm_compute_save_reg_mask
7965 and arm_compute_initial_elimination_offset. */
7967 static unsigned long
7968 arm_compute_save_reg0_reg12_mask ()
7970 unsigned long func_type = arm_current_func_type ();
7971 unsigned int save_reg_mask = 0;
7974 if (IS_INTERRUPT (func_type))
7976 unsigned int max_reg;
7977 /* Interrupt functions must not corrupt any registers,
7978 even call clobbered ones. If this is a leaf function
7979 we can just examine the registers used by the RTL, but
7980 otherwise we have to assume that whatever function is
7981 called might clobber anything, and so we have to save
7982 all the call-clobbered registers as well. */
7983 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7984 /* FIQ handlers have registers r8 - r12 banked, so
7985 we only need to check r0 - r7, Normal ISRs only
7986 bank r14 and r15, so we must check up to r12.
7987 r13 is the stack pointer which is always preserved,
7988 so we do not need to consider it here. */
7993 for (reg = 0; reg <= max_reg; reg++)
7994 if (regs_ever_live[reg]
7995 || (! current_function_is_leaf && call_used_regs [reg]))
7996 save_reg_mask |= (1 << reg);
8000 /* In the normal case we only need to save those registers
8001 which are call saved and which are used by this function. */
8002 for (reg = 0; reg <= 10; reg++)
8003 if (regs_ever_live[reg] && ! call_used_regs [reg])
8004 save_reg_mask |= (1 << reg);
8006 /* Handle the frame pointer as a special case. */
8007 if (! TARGET_APCS_FRAME
8008 && ! frame_pointer_needed
8009 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8010 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8011 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8013 /* If we aren't loading the PIC register,
8014 don't stack it even though it may be live. */
8016 && ! TARGET_SINGLE_PIC_BASE
8017 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8018 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8021 return save_reg_mask;
8024 /* Compute a bit mask of which registers need to be
8025 saved on the stack for the current function. */
8027 static unsigned long
8028 arm_compute_save_reg_mask ()
8030 unsigned int save_reg_mask = 0;
8031 unsigned long func_type = arm_current_func_type ();
8033 if (IS_NAKED (func_type))
8034 /* This should never really happen. */
8037 /* If we are creating a stack frame, then we must save the frame pointer,
8038 IP (which will hold the old stack pointer), LR and the PC. */
8039 if (frame_pointer_needed)
8041 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8046 /* Volatile functions do not return, so there
8047 is no need to save any other registers. */
8048 if (IS_VOLATILE (func_type))
8049 return save_reg_mask;
8051 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8053 /* Decide if we need to save the link register.
8054 Interrupt routines have their own banked link register,
8055 so they never need to save it.
8056 Otherwise if we do not use the link register we do not need to save
8057 it. If we are pushing other registers onto the stack however, we
8058 can save an instruction in the epilogue by pushing the link register
8059 now and then popping it back into the PC. This incurs extra memory
8060 accesses though, so we only do it when optimising for size, and only
8061 if we know that we will not need a fancy return sequence. */
8062 if (regs_ever_live [LR_REGNUM]
8065 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8066 save_reg_mask |= 1 << LR_REGNUM;
8068 if (cfun->machine->lr_save_eliminated)
8069 save_reg_mask &= ~ (1 << LR_REGNUM);
8071 return save_reg_mask;
8074 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
8075 everything bar the final return instruction. */
8078 output_return_instruction (operand, really_return, reverse)
8083 char conditional[10];
8086 unsigned long live_regs_mask;
8087 unsigned long func_type;
8089 func_type = arm_current_func_type ();
8091 if (IS_NAKED (func_type))
8094 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8096 /* If this function was declared non-returning, and we have found a tail
8097 call, then we have to trust that the called function won't return. */
8102 /* Otherwise, trap an attempted return by aborting. */
8104 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8106 assemble_external_libcall (ops[1]);
8107 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8113 if (current_function_calls_alloca && !really_return)
8116 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8118 return_used_this_function = 1;
8120 live_regs_mask = arm_compute_save_reg_mask ();
8124 const char * return_reg;
8126 /* If we do not have any special requirements for function exit
8127 (eg interworking, or ISR) then we can load the return address
8128 directly into the PC. Otherwise we must load it into LR. */
8130 && ! TARGET_INTERWORK)
8131 return_reg = reg_names[PC_REGNUM];
8133 return_reg = reg_names[LR_REGNUM];
8135 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8136 /* There are two possible reasons for the IP register being saved.
8137 Either a stack frame was created, in which case IP contains the
8138 old stack pointer, or an ISR routine corrupted it. If this in an
8139 ISR routine then just restore IP, otherwise restore IP into SP. */
8140 if (! IS_INTERRUPT (func_type))
8142 live_regs_mask &= ~ (1 << IP_REGNUM);
8143 live_regs_mask |= (1 << SP_REGNUM);
8146 /* On some ARM architectures it is faster to use LDR rather than
8147 LDM to load a single register. On other architectures, the
8148 cost is the same. In 26 bit mode, or for exception handlers,
8149 we have to use LDM to load the PC so that the CPSR is also
8151 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8153 if (live_regs_mask == (unsigned int)(1 << reg))
8156 if (reg <= LAST_ARM_REGNUM
8157 && (reg != LR_REGNUM
8159 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8161 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8162 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8169 /* Generate the load multiple instruction to restore the registers. */
8170 if (frame_pointer_needed)
8171 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
8172 else if (live_regs_mask & (1 << SP_REGNUM))
8173 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8175 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8177 p = instr + strlen (instr);
8179 for (reg = 0; reg <= SP_REGNUM; reg++)
8180 if (live_regs_mask & (1 << reg))
8182 int l = strlen (reg_names[reg]);
8188 memcpy (p, ", ", 2);
8192 memcpy (p, "%|", 2);
8193 memcpy (p + 2, reg_names[reg], l);
8197 if (live_regs_mask & (1 << LR_REGNUM))
8199 int l = strlen (return_reg);
8203 memcpy (p, ", ", 2);
8207 memcpy (p, "%|", 2);
8208 memcpy (p + 2, return_reg, l);
8209 strcpy (p + 2 + l, ((TARGET_APCS_32
8210 && !IS_INTERRUPT (func_type))
8218 output_asm_insn (instr, & operand);
8220 /* See if we need to generate an extra instruction to
8221 perform the actual function return. */
8223 && func_type != ARM_FT_INTERWORKED
8224 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8226 /* The return has already been handled
8227 by loading the LR into the PC. */
8234 switch ((int) ARM_FUNC_TYPE (func_type))
8238 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8241 case ARM_FT_INTERWORKED:
8242 sprintf (instr, "bx%s\t%%|lr", conditional);
8245 case ARM_FT_EXCEPTION:
8246 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8250 /* ARMv5 implementations always provide BX, so interworking
8251 is the default unless APCS-26 is in use. */
8252 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8253 sprintf (instr, "bx%s\t%%|lr", conditional);
8255 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8256 conditional, TARGET_APCS_32 ? "" : "s");
8260 output_asm_insn (instr, & operand);
8266 /* Write the function name into the code section, directly preceding
8267 the function prologue.
8269 Code will be output similar to this:
8271 .ascii "arm_poke_function_name", 0
8274 .word 0xff000000 + (t1 - t0)
8275 arm_poke_function_name
8277 stmfd sp!, {fp, ip, lr, pc}
8280 When performing a stack backtrace, code can inspect the value
8281 of 'pc' stored at 'fp' + 0. If the trace function then looks
8282 at location pc - 12 and the top 8 bits are set, then we know
8283 that there is a function name embedded immediately preceding this
8284 location and has length ((pc[-3]) & 0xff000000).
8286 We assume that pc is declared as a pointer to an unsigned long.
8288 It is of no benefit to output the function name if we are assembling
8289 a leaf function. These function types will not contain a stack
8290 backtrace structure, therefore it is not possible to determine the
8294 arm_poke_function_name (stream, name)
8298 unsigned long alignlength;
8299 unsigned long length;
8302 length = strlen (name) + 1;
8303 alignlength = ROUND_UP_WORD (length);
8305 ASM_OUTPUT_ASCII (stream, name, length);
8306 ASM_OUTPUT_ALIGN (stream, 2);
8307 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8308 assemble_aligned_integer (UNITS_PER_WORD, x);
8311 /* Place some comments into the assembler stream
8312 describing the current function. */
8315 arm_output_function_prologue (f, frame_size)
8317 HOST_WIDE_INT frame_size;
8319 unsigned long func_type;
8323 thumb_output_function_prologue (f, frame_size);
8328 if (arm_ccfsm_state || arm_target_insn)
8331 func_type = arm_current_func_type ();
8333 switch ((int) ARM_FUNC_TYPE (func_type))
8338 case ARM_FT_INTERWORKED:
8339 asm_fprintf (f, "\t%@ Function supports interworking.\n");
8341 case ARM_FT_EXCEPTION_HANDLER:
8342 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
8345 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
8348 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
8350 case ARM_FT_EXCEPTION:
8351 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
8355 if (IS_NAKED (func_type))
8356 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8358 if (IS_VOLATILE (func_type))
8359 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
8361 if (IS_NESTED (func_type))
8362 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
8364 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
8365 current_function_args_size,
8366 current_function_pretend_args_size, frame_size);
8368 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8369 frame_pointer_needed,
8370 cfun->machine->uses_anonymous_args);
8372 if (cfun->machine->lr_save_eliminated)
8373 asm_fprintf (f, "\t%@ link register save eliminated.\n");
8375 #ifdef AOF_ASSEMBLER
8377 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
8380 return_used_this_function = 0;
8384 arm_output_epilogue (really_return)
8388 unsigned long saved_regs_mask;
8389 unsigned long func_type;
8390 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8391 frame that is $fp + 4 for a non-variadic function. */
8392 int floats_offset = 0;
8394 int frame_size = arm_get_frame_size ();
8395 FILE * f = asm_out_file;
8396 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
8398 /* If we have already generated the return instruction
8399 then it is futile to generate anything else. */
8400 if (use_return_insn (FALSE) && return_used_this_function)
8403 func_type = arm_current_func_type ();
8405 if (IS_NAKED (func_type))
8406 /* Naked functions don't have epilogues. */
8409 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8413 /* A volatile function should never return. Call abort. */
8414 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
8415 assemble_external_libcall (op);
8416 output_asm_insn ("bl\t%a0", &op);
8421 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
8423 /* If we are throwing an exception, then we really must
8424 be doing a return, so we can't tail-call. */
8427 saved_regs_mask = arm_compute_save_reg_mask ();
8429 /* XXX We should adjust floats_offset for any anonymous args, and then
8430 re-adjust vfp_offset below to compensate. */
8432 /* Compute how far away the floats will be. */
8433 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
8434 if (saved_regs_mask & (1 << reg))
8437 if (frame_pointer_needed)
8441 if (arm_fpu_arch == FP_SOFT2)
8443 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8444 if (regs_ever_live[reg] && !call_used_regs[reg])
8446 floats_offset += 12;
8447 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
8448 reg, FP_REGNUM, floats_offset - vfp_offset);
8453 int start_reg = LAST_ARM_FP_REGNUM;
8455 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8457 if (regs_ever_live[reg] && !call_used_regs[reg])
8459 floats_offset += 12;
8461 /* We can't unstack more than four registers at once. */
8462 if (start_reg - reg == 3)
8464 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
8465 reg, FP_REGNUM, floats_offset - vfp_offset);
8466 start_reg = reg - 1;
8471 if (reg != start_reg)
8472 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8473 reg + 1, start_reg - reg,
8474 FP_REGNUM, floats_offset - vfp_offset);
8475 start_reg = reg - 1;
8479 /* Just in case the last register checked also needs unstacking. */
8480 if (reg != start_reg)
8481 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8482 reg + 1, start_reg - reg,
8483 FP_REGNUM, floats_offset - vfp_offset);
8486 /* saved_regs_mask should contain the IP, which at the time of stack
8487 frame generation actually contains the old stack pointer. So a
8488 quick way to unwind the stack is just pop the IP register directly
8489 into the stack pointer. */
8490 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
8492 saved_regs_mask &= ~ (1 << IP_REGNUM);
8493 saved_regs_mask |= (1 << SP_REGNUM);
8495 /* There are two registers left in saved_regs_mask - LR and PC. We
8496 only need to restore the LR register (the return address), but to
8497 save time we can load it directly into the PC, unless we need a
8498 special function exit sequence, or we are not really returning. */
8499 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
8500 /* Delete the LR from the register mask, so that the LR on
8501 the stack is loaded into the PC in the register mask. */
8502 saved_regs_mask &= ~ (1 << LR_REGNUM);
8504 saved_regs_mask &= ~ (1 << PC_REGNUM);
8506 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
8508 if (IS_INTERRUPT (func_type))
8509 /* Interrupt handlers will have pushed the
8510 IP onto the stack, so restore it now. */
8511 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
8515 /* Restore stack pointer if necessary. */
8516 if (frame_size + current_function_outgoing_args_size != 0)
8518 operands[0] = operands[1] = stack_pointer_rtx;
8519 operands[2] = GEN_INT (frame_size
8520 + current_function_outgoing_args_size);
8521 output_add_immediate (operands);
8524 if (arm_fpu_arch == FP_SOFT2)
8526 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8527 if (regs_ever_live[reg] && !call_used_regs[reg])
8528 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
8533 int start_reg = FIRST_ARM_FP_REGNUM;
8535 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8537 if (regs_ever_live[reg] && !call_used_regs[reg])
8539 if (reg - start_reg == 3)
8541 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
8542 start_reg, SP_REGNUM);
8543 start_reg = reg + 1;
8548 if (reg != start_reg)
8549 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8550 start_reg, reg - start_reg,
8553 start_reg = reg + 1;
8557 /* Just in case the last register checked also needs unstacking. */
8558 if (reg != start_reg)
8559 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8560 start_reg, reg - start_reg, SP_REGNUM);
8563 /* If we can, restore the LR into the PC. */
8564 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8566 && current_function_pretend_args_size == 0
8567 && saved_regs_mask & (1 << LR_REGNUM))
8569 saved_regs_mask &= ~ (1 << LR_REGNUM);
8570 saved_regs_mask |= (1 << PC_REGNUM);
8573 /* Load the registers off the stack. If we only have one register
8574 to load use the LDR instruction - it is faster. */
8575 if (saved_regs_mask == (1 << LR_REGNUM))
8577 /* The exception handler ignores the LR, so we do
8578 not really need to load it off the stack. */
8580 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
8582 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8584 else if (saved_regs_mask)
8586 if (saved_regs_mask & (1 << SP_REGNUM))
8587 /* Note - write back to the stack register is not enabled
8588 (ie "ldmfd sp!..."). We know that the stack pointer is
8589 in the list of registers and if we add writeback the
8590 instruction becomes UNPREDICTABLE. */
8591 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8593 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
8596 if (current_function_pretend_args_size)
8598 /* Unwind the pre-pushed regs. */
8599 operands[0] = operands[1] = stack_pointer_rtx;
8600 operands[2] = GEN_INT (current_function_pretend_args_size);
8601 output_add_immediate (operands);
8606 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
8607 /* Adjust the stack to remove the exception handler stuff. */
8608 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
8613 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8614 && current_function_pretend_args_size == 0
8615 && saved_regs_mask & (1 << PC_REGNUM)))
8618 /* Generate the return instruction. */
8619 switch ((int) ARM_FUNC_TYPE (func_type))
8621 case ARM_FT_EXCEPTION_HANDLER:
8622 /* Even in 26-bit mode we do a mov (rather than a movs)
8623 because we don't have the PSR bits set in the address. */
8624 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
8629 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
8632 case ARM_FT_EXCEPTION:
8633 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8636 case ARM_FT_INTERWORKED:
8637 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
8641 if (frame_pointer_needed)
8642 /* If we used the frame pointer then the return address
8643 will have been loaded off the stack directly into the
8644 PC, so there is no need to issue a MOV instruction
8647 else if (current_function_pretend_args_size == 0
8648 && (saved_regs_mask & (1 << LR_REGNUM)))
8649 /* Similarly we may have been able to load LR into the PC
8650 even if we did not create a stack frame. */
8652 else if (TARGET_APCS_32)
8653 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8655 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8663 arm_output_function_epilogue (file, frame_size)
8664 FILE *file ATTRIBUTE_UNUSED;
8665 HOST_WIDE_INT frame_size;
8669 /* ??? Probably not safe to set this here, since it assumes that a
8670 function will be emitted as assembly immediately after we generate
8671 RTL for it. This does not happen for inline functions. */
8672 return_used_this_function = 0;
8676 /* We need to take into account any stack-frame rounding. */
8677 frame_size = arm_get_frame_size ();
8679 if (use_return_insn (FALSE)
8680 && return_used_this_function
8681 && (frame_size + current_function_outgoing_args_size) != 0
8682 && !frame_pointer_needed)
8685 /* Reset the ARM-specific per-function variables. */
8686 after_arm_reorg = 0;
8690 /* Generate and emit an insn that we will recognize as a push_multi.
8691 Unfortunately, since this insn does not reflect very well the actual
8692 semantics of the operation, we need to annotate the insn for the benefit
8693 of DWARF2 frame unwind information. */
8696 emit_multi_reg_push (mask)
8704 int dwarf_par_index;
8707 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8708 if (mask & (1 << i))
8711 if (num_regs == 0 || num_regs > 16)
8714 /* We don't record the PC in the dwarf frame information. */
8715 num_dwarf_regs = num_regs;
8716 if (mask & (1 << PC_REGNUM))
8719 /* For the body of the insn we are going to generate an UNSPEC in
8720 parallel with several USEs. This allows the insn to be recognized
8721 by the push_multi pattern in the arm.md file. The insn looks
8722 something like this:
8725 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8726 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8727 (use (reg:SI 11 fp))
8728 (use (reg:SI 12 ip))
8729 (use (reg:SI 14 lr))
8730 (use (reg:SI 15 pc))
8733 For the frame note however, we try to be more explicit and actually
8734 show each register being stored into the stack frame, plus a (single)
8735 decrement of the stack pointer. We do it this way in order to be
8736 friendly to the stack unwinding code, which only wants to see a single
8737 stack decrement per instruction. The RTL we generate for the note looks
8738 something like this:
8741 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8742 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8743 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8744 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8745 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8748 This sequence is used both by the code to support stack unwinding for
8749 exceptions handlers and the code to generate dwarf2 frame debugging. */
8751 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
8752 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
8753 dwarf_par_index = 1;
8755 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8757 if (mask & (1 << i))
8759 reg = gen_rtx_REG (SImode, i);
8762 = gen_rtx_SET (VOIDmode,
8763 gen_rtx_MEM (BLKmode,
8764 gen_rtx_PRE_DEC (BLKmode,
8765 stack_pointer_rtx)),
8766 gen_rtx_UNSPEC (BLKmode,
8772 tmp = gen_rtx_SET (VOIDmode,
8773 gen_rtx_MEM (SImode, stack_pointer_rtx),
8775 RTX_FRAME_RELATED_P (tmp) = 1;
8776 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
8784 for (j = 1, i++; j < num_regs; i++)
8786 if (mask & (1 << i))
8788 reg = gen_rtx_REG (SImode, i);
8790 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
8794 tmp = gen_rtx_SET (VOIDmode,
8795 gen_rtx_MEM (SImode,
8796 plus_constant (stack_pointer_rtx,
8799 RTX_FRAME_RELATED_P (tmp) = 1;
8800 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
8807 par = emit_insn (par);
8809 tmp = gen_rtx_SET (SImode,
8811 gen_rtx_PLUS (SImode,
8813 GEN_INT (-4 * num_regs)));
8814 RTX_FRAME_RELATED_P (tmp) = 1;
8815 XVECEXP (dwarf, 0, 0) = tmp;
8817 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8823 emit_sfm (base_reg, count)
8832 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8833 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8835 reg = gen_rtx_REG (XFmode, base_reg++);
8838 = gen_rtx_SET (VOIDmode,
8839 gen_rtx_MEM (BLKmode,
8840 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8841 gen_rtx_UNSPEC (BLKmode,
8845 = gen_rtx_SET (VOIDmode,
8846 gen_rtx_MEM (XFmode,
8847 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8849 RTX_FRAME_RELATED_P (tmp) = 1;
8850 XVECEXP (dwarf, 0, count - 1) = tmp;
8852 for (i = 1; i < count; i++)
8854 reg = gen_rtx_REG (XFmode, base_reg++);
8855 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8857 tmp = gen_rtx_SET (VOIDmode,
8858 gen_rtx_MEM (XFmode,
8859 gen_rtx_PRE_DEC (BLKmode,
8860 stack_pointer_rtx)),
8862 RTX_FRAME_RELATED_P (tmp) = 1;
8863 XVECEXP (dwarf, 0, count - i - 1) = tmp;
8866 par = emit_insn (par);
8867 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8872 /* Compute the distance from register FROM to register TO.
8873 These can be the arg pointer (26), the soft frame pointer (25),
8874 the stack pointer (13) or the hard frame pointer (11).
8875 Typical stack layout looks like this:
8877 old stack pointer -> | |
8880 | | saved arguments for
8881 | | vararg functions
8884 hard FP & arg pointer -> | | \
8892 soft frame pointer -> | | /
8902 current stack pointer -> | | /
8905 For a given function some or all of these stack components
8906 may not be needed, giving rise to the possibility of
8907 eliminating some of the registers.
8909 The values returned by this function must reflect the behavior
8910 of arm_expand_prologue() and arm_compute_save_reg_mask().
8912 The sign of the number returned reflects the direction of stack
8913 growth, so the values are positive for all eliminations except
8914 from the soft frame pointer to the hard frame pointer. */
8917 arm_compute_initial_elimination_offset (from, to)
8921 unsigned int local_vars = arm_get_frame_size ();
8922 unsigned int outgoing_args = current_function_outgoing_args_size;
8923 unsigned int stack_frame;
8924 unsigned int call_saved_registers;
8925 unsigned long func_type;
8927 func_type = arm_current_func_type ();
8929 /* Volatile functions never return, so there is
8930 no need to save call saved registers. */
8931 call_saved_registers = 0;
8932 if (! IS_VOLATILE (func_type))
8934 unsigned int reg_mask;
8937 /* Make sure that we compute which registers will be saved
8938 on the stack using the same algorithm that is used by
8939 arm_compute_save_reg_mask(). */
8940 reg_mask = arm_compute_save_reg0_reg12_mask ();
8942 /* Now count the number of bits set in save_reg_mask.
8943 For each set bit we need 4 bytes of stack space. */
8946 call_saved_registers += 4;
8947 reg_mask = reg_mask & ~ (reg_mask & - reg_mask);
8950 if ((regs_ever_live[LR_REGNUM]
8951 /* If optimizing for size, then we save the link register if
8952 any other integer register is saved. This gives a smaller
8954 || (optimize_size && call_saved_registers > 0))
8955 /* But if a stack frame is going to be created, the LR will
8956 be saved as part of that, so we do not need to allow for
8958 && ! frame_pointer_needed)
8959 call_saved_registers += 4;
8961 /* If the hard floating point registers are going to be
8962 used then they must be saved on the stack as well.
8963 Each register occupies 12 bytes of stack space. */
8964 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++)
8965 if (regs_ever_live[reg] && ! call_used_regs[reg])
8966 call_saved_registers += 12;
8969 /* The stack frame contains 4 registers - the old frame pointer,
8970 the old stack pointer, the return address and PC of the start
8972 stack_frame = frame_pointer_needed ? 16 : 0;
8974 /* OK, now we have enough information to compute the distances.
8975 There must be an entry in these switch tables for each pair
8976 of registers in ELIMINABLE_REGS, even if some of the entries
8977 seem to be redundant or useless. */
8980 case ARG_POINTER_REGNUM:
8983 case THUMB_HARD_FRAME_POINTER_REGNUM:
8986 case FRAME_POINTER_REGNUM:
8987 /* This is the reverse of the soft frame pointer
8988 to hard frame pointer elimination below. */
8989 if (call_saved_registers == 0 && stack_frame == 0)
8991 return (call_saved_registers + stack_frame - 4);
8993 case ARM_HARD_FRAME_POINTER_REGNUM:
8994 /* If there is no stack frame then the hard
8995 frame pointer and the arg pointer coincide. */
8996 if (stack_frame == 0 && call_saved_registers != 0)
8998 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8999 return (frame_pointer_needed
9000 && current_function_needs_context
9001 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9003 case STACK_POINTER_REGNUM:
9004 /* If nothing has been pushed on the stack at all
9005 then this will return -4. This *is* correct! */
9006 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9013 case FRAME_POINTER_REGNUM:
9016 case THUMB_HARD_FRAME_POINTER_REGNUM:
9019 case ARM_HARD_FRAME_POINTER_REGNUM:
9020 /* The hard frame pointer points to the top entry in the
9021 stack frame. The soft frame pointer to the bottom entry
9022 in the stack frame. If there is no stack frame at all,
9023 then they are identical. */
9024 if (call_saved_registers == 0 && stack_frame == 0)
9026 return - (call_saved_registers + stack_frame - 4);
9028 case STACK_POINTER_REGNUM:
9029 return local_vars + outgoing_args;
9037 /* You cannot eliminate from the stack pointer.
9038 In theory you could eliminate from the hard frame
9039 pointer to the stack pointer, but this will never
9040 happen, since if a stack frame is not needed the
9041 hard frame pointer will never be used. */
9046 /* Calculate the size of the stack frame, taking into account any
9047 padding that is required to ensure stack-alignment. */
9050 arm_get_frame_size ()
9054 int base_size = ROUND_UP_WORD (get_frame_size ());
9056 unsigned long func_type = arm_current_func_type ();
9065 /* We need to know if we are a leaf function. Unfortunately, it
9066 is possible to be called after start_sequence has been called,
9067 which causes get_insns to return the insns for the sequence,
9068 not the function, which will cause leaf_function_p to return
9069 the incorrect result.
9071 To work around this, we cache the computed frame size. This
9072 works because we will only be calling RTL expanders that need
9073 to know about leaf functions once reload has completed, and the
9074 frame size cannot be changed after that time, so we can safely
9075 use the cached value. */
9077 if (reload_completed)
9078 return cfun->machine->frame_size;
9080 leaf = leaf_function_p ();
9082 /* A leaf function does not need any stack alignment if it has nothing
9084 if (leaf && base_size == 0)
9086 cfun->machine->frame_size = 0;
9090 /* We know that SP will be word aligned on entry, and we must
9091 preserve that condition at any subroutine call. But those are
9092 the only constraints. */
9094 /* Space for variadic functions. */
9095 if (current_function_pretend_args_size)
9096 entry_size += current_function_pretend_args_size;
9098 /* Space for saved registers. */
9099 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9101 /* Space for saved FPA registers. */
9102 if (! IS_VOLATILE (func_type))
9104 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
9105 if (regs_ever_live[regno] && ! call_used_regs[regno])
9109 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9111 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9114 cfun->machine->frame_size = base_size;
9119 /* Generate the prologue instructions for entry into an ARM function. */
9122 arm_expand_prologue ()
9128 unsigned long live_regs_mask;
9129 unsigned long func_type;
9131 int saved_pretend_args = 0;
9132 unsigned int args_to_push;
9134 func_type = arm_current_func_type ();
9136 /* Naked functions don't have prologues. */
9137 if (IS_NAKED (func_type))
9140 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9141 args_to_push = current_function_pretend_args_size;
9143 /* Compute which register we will have to save onto the stack. */
9144 live_regs_mask = arm_compute_save_reg_mask ();
9146 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9148 if (frame_pointer_needed)
9150 if (IS_INTERRUPT (func_type))
9152 /* Interrupt functions must not corrupt any registers.
9153 Creating a frame pointer however, corrupts the IP
9154 register, so we must push it first. */
9155 insn = emit_multi_reg_push (1 << IP_REGNUM);
9157 /* Do not set RTX_FRAME_RELATED_P on this insn.
9158 The dwarf stack unwinding code only wants to see one
9159 stack decrement per function, and this is not it. If
9160 this instruction is labeled as being part of the frame
9161 creation sequence then dwarf2out_frame_debug_expr will
9162 abort when it encounters the assignment of IP to FP
9163 later on, since the use of SP here establishes SP as
9164 the CFA register and not IP.
9166 Anyway this instruction is not really part of the stack
9167 frame creation although it is part of the prologue. */
9169 else if (IS_NESTED (func_type))
9171 /* The Static chain register is the same as the IP register
9172 used as a scratch register during stack frame creation.
9173 To get around this need to find somewhere to store IP
9174 whilst the frame is being created. We try the following
9177 1. The last argument register.
9178 2. A slot on the stack above the frame. (This only
9179 works if the function is not a varargs function).
9180 3. Register r3, after pushing the argument registers
9183 Note - we only need to tell the dwarf2 backend about the SP
9184 adjustment in the second variant; the static chain register
9185 doesn't need to be unwound, as it doesn't contain a value
9186 inherited from the caller. */
9188 if (regs_ever_live[3] == 0)
9190 insn = gen_rtx_REG (SImode, 3);
9191 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9192 insn = emit_insn (insn);
9194 else if (args_to_push == 0)
9197 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
9198 insn = gen_rtx_MEM (SImode, insn);
9199 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
9200 insn = emit_insn (insn);
9204 /* Just tell the dwarf backend that we adjusted SP. */
9205 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9206 gen_rtx_PLUS (SImode, stack_pointer_rtx,
9207 GEN_INT (-fp_offset)));
9208 RTX_FRAME_RELATED_P (insn) = 1;
9209 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9210 dwarf, REG_NOTES (insn));
9214 /* Store the args on the stack. */
9215 if (cfun->machine->uses_anonymous_args)
9216 insn = emit_multi_reg_push
9217 ((0xf0 >> (args_to_push / 4)) & 0xf);
9220 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9221 GEN_INT (- args_to_push)));
9223 RTX_FRAME_RELATED_P (insn) = 1;
9225 saved_pretend_args = 1;
9226 fp_offset = args_to_push;
9229 /* Now reuse r3 to preserve IP. */
9230 insn = gen_rtx_REG (SImode, 3);
9231 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9232 (void) emit_insn (insn);
9238 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
9239 insn = gen_rtx_SET (SImode, ip_rtx, insn);
9242 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
9244 insn = emit_insn (insn);
9245 RTX_FRAME_RELATED_P (insn) = 1;
9250 /* Push the argument registers, or reserve space for them. */
9251 if (cfun->machine->uses_anonymous_args)
9252 insn = emit_multi_reg_push
9253 ((0xf0 >> (args_to_push / 4)) & 0xf);
9256 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9257 GEN_INT (- args_to_push)));
9258 RTX_FRAME_RELATED_P (insn) = 1;
9261 /* If this is an interrupt service routine, and the link register
9262 is going to be pushed, and we are not creating a stack frame,
9263 (which would involve an extra push of IP and a pop in the epilogue)
9264 subtracting four from LR now will mean that the function return
9265 can be done with a single instruction. */
9266 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
9267 && (live_regs_mask & (1 << LR_REGNUM)) != 0
9268 && ! frame_pointer_needed)
9269 emit_insn (gen_rtx_SET (SImode,
9270 gen_rtx_REG (SImode, LR_REGNUM),
9271 gen_rtx_PLUS (SImode,
9272 gen_rtx_REG (SImode, LR_REGNUM),
9277 insn = emit_multi_reg_push (live_regs_mask);
9278 RTX_FRAME_RELATED_P (insn) = 1;
9281 if (! IS_VOLATILE (func_type))
9283 /* Save any floating point call-saved registers used by this function. */
9284 if (arm_fpu_arch == FP_SOFT2)
9286 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
9287 if (regs_ever_live[reg] && !call_used_regs[reg])
9289 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
9290 insn = gen_rtx_MEM (XFmode, insn);
9291 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9292 gen_rtx_REG (XFmode, reg)));
9293 RTX_FRAME_RELATED_P (insn) = 1;
9298 int start_reg = LAST_ARM_FP_REGNUM;
9300 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
9302 if (regs_ever_live[reg] && !call_used_regs[reg])
9304 if (start_reg - reg == 3)
9306 insn = emit_sfm (reg, 4);
9307 RTX_FRAME_RELATED_P (insn) = 1;
9308 start_reg = reg - 1;
9313 if (start_reg != reg)
9315 insn = emit_sfm (reg + 1, start_reg - reg);
9316 RTX_FRAME_RELATED_P (insn) = 1;
9318 start_reg = reg - 1;
9322 if (start_reg != reg)
9324 insn = emit_sfm (reg + 1, start_reg - reg);
9325 RTX_FRAME_RELATED_P (insn) = 1;
9330 if (frame_pointer_needed)
9332 /* Create the new frame pointer. */
9333 insn = GEN_INT (-(4 + args_to_push + fp_offset));
9334 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
9335 RTX_FRAME_RELATED_P (insn) = 1;
9337 if (IS_NESTED (func_type))
9339 /* Recover the static chain register. */
9340 if (regs_ever_live [3] == 0
9341 || saved_pretend_args)
9342 insn = gen_rtx_REG (SImode, 3);
9343 else /* if (current_function_pretend_args_size == 0) */
9345 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
9346 insn = gen_rtx_MEM (SImode, insn);
9349 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
9350 /* Add a USE to stop propagate_one_insn() from barfing. */
9351 emit_insn (gen_prologue_use (ip_rtx));
9355 amount = GEN_INT (-(arm_get_frame_size ()
9356 + current_function_outgoing_args_size));
9358 if (amount != const0_rtx)
9360 /* This add can produce multiple insns for a large constant, so we
9361 need to get tricky. */
9362 rtx last = get_last_insn ();
9363 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9367 last = last ? NEXT_INSN (last) : get_insns ();
9368 RTX_FRAME_RELATED_P (last) = 1;
9370 while (last != insn);
9372 /* If the frame pointer is needed, emit a special barrier that
9373 will prevent the scheduler from moving stores to the frame
9374 before the stack adjustment. */
9375 if (frame_pointer_needed)
9376 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
9377 hard_frame_pointer_rtx));
9380 /* If we are profiling, make sure no instructions are scheduled before
9381 the call to mcount. Similarly if the user has requested no
9382 scheduling in the prolog. */
9383 if (current_function_profile || TARGET_NO_SCHED_PRO)
9384 emit_insn (gen_blockage ());
9386 /* If the link register is being kept alive, with the return address in it,
9387 then make sure that it does not get reused by the ce2 pass. */
9388 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
9390 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
9391 cfun->machine->lr_save_eliminated = 1;
9395 /* If CODE is 'd', then the X is a condition operand and the instruction
9396 should only be executed if the condition is true.
9397 if CODE is 'D', then the X is a condition operand and the instruction
9398 should only be executed if the condition is false: however, if the mode
9399 of the comparison is CCFPEmode, then always execute the instruction -- we
9400 do this because in these circumstances !GE does not necessarily imply LT;
9401 in these cases the instruction pattern will take care to make sure that
9402 an instruction containing %d will follow, thereby undoing the effects of
9403 doing this instruction unconditionally.
9404 If CODE is 'N' then X is a floating point operand that must be negated
9406 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9407 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9410 arm_print_operand (stream, x, code)
9418 fputs (ASM_COMMENT_START, stream);
9422 fputs (user_label_prefix, stream);
9426 fputs (REGISTER_PREFIX, stream);
9430 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
9432 if (TARGET_THUMB || current_insn_predicate != NULL)
9435 fputs (arm_condition_codes[arm_current_cc], stream);
9437 else if (current_insn_predicate)
9439 enum arm_cond_code code;
9444 code = get_arm_condition_code (current_insn_predicate);
9445 fputs (arm_condition_codes[code], stream);
9452 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9453 r = REAL_VALUE_NEGATE (r);
9454 fprintf (stream, "%s", fp_const_from_val (&r));
9459 if (GET_CODE (x) == CONST_INT)
9462 val = ARM_SIGN_EXTEND (~INTVAL (x));
9463 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9468 output_addr_const (stream, x);
9473 fprintf (stream, "%s", arithmetic_instr (x, 1));
9476 /* Truncate Cirrus shift counts. */
9478 if (GET_CODE (x) == CONST_INT)
9480 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
9483 arm_print_operand (stream, x, 0);
9487 fprintf (stream, "%s", arithmetic_instr (x, 0));
9493 const char * shift = shift_op (x, &val);
9497 fprintf (stream, ", %s ", shift_op (x, &val));
9499 arm_print_operand (stream, XEXP (x, 1), 0);
9502 fputc ('#', stream);
9503 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9509 /* An explanation of the 'Q', 'R' and 'H' register operands:
9511 In a pair of registers containing a DI or DF value the 'Q'
9512 operand returns the register number of the register containing
9513 the least signficant part of the value. The 'R' operand returns
9514 the register number of the register containing the most
9515 significant part of the value.
9517 The 'H' operand returns the higher of the two register numbers.
9518 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9519 same as the 'Q' operand, since the most signficant part of the
9520 value is held in the lower number register. The reverse is true
9521 on systems where WORDS_BIG_ENDIAN is false.
9523 The purpose of these operands is to distinguish between cases
9524 where the endian-ness of the values is important (for example
9525 when they are added together), and cases where the endian-ness
9526 is irrelevant, but the order of register operations is important.
9527 For example when loading a value from memory into a register
9528 pair, the endian-ness does not matter. Provided that the value
9529 from the lower memory address is put into the lower numbered
9530 register, and the value from the higher address is put into the
9531 higher numbered register, the load will work regardless of whether
9532 the value being loaded is big-wordian or little-wordian. The
9533 order of the two register loads can matter however, if the address
9534 of the memory location is actually held in one of the registers
9535 being overwritten by the load. */
9537 if (REGNO (x) > LAST_ARM_REGNUM)
9539 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
9543 if (REGNO (x) > LAST_ARM_REGNUM)
9545 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
9549 if (REGNO (x) > LAST_ARM_REGNUM)
9551 asm_fprintf (stream, "%r", REGNO (x) + 1);
9555 asm_fprintf (stream, "%r",
9556 GET_CODE (XEXP (x, 0)) == REG
9557 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9561 asm_fprintf (stream, "{%r-%r}",
9563 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9567 /* CONST_TRUE_RTX means always -- that's the default. */
9568 if (x == const_true_rtx)
9572 fputs (arm_condition_codes[get_arm_condition_code (x)],
9575 fputs (thumb_condition_code (x, 0), stream);
9579 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9581 if (x == const_true_rtx)
9585 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
9586 (get_arm_condition_code (x))],
9589 fputs (thumb_condition_code (x, 1), stream);
9593 /* Cirrus registers can be accessed in a variety of ways:
9594 single floating point (f)
9595 double floating point (d)
9597 64bit integer (dx). */
9598 case 'W': /* Cirrus register in F mode. */
9599 case 'X': /* Cirrus register in D mode. */
9600 case 'Y': /* Cirrus register in FX mode. */
9601 case 'Z': /* Cirrus register in DX mode. */
9602 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9605 fprintf (stream, "mv%s%s",
9608 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
9612 /* Print cirrus register in the mode specified by the register's mode. */
9615 int mode = GET_MODE (x);
9617 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9620 fprintf (stream, "mv%s%s",
9621 mode == DFmode ? "d"
9622 : mode == SImode ? "fx"
9623 : mode == DImode ? "dx"
9624 : "f", reg_names[REGNO (x)] + 2);
9633 if (GET_CODE (x) == REG)
9634 asm_fprintf (stream, "%r", REGNO (x));
9635 else if (GET_CODE (x) == MEM)
9637 output_memory_reference_mode = GET_MODE (x);
9638 output_address (XEXP (x, 0));
9640 else if (GET_CODE (x) == CONST_DOUBLE)
9641 fprintf (stream, "#%s", fp_immediate_constant (x));
9642 else if (GET_CODE (x) == NEG)
9643 abort (); /* This should never happen now. */
9646 fputc ('#', stream);
9647 output_addr_const (stream, x);
9652 #ifndef AOF_ASSEMBLER
9653 /* Target hook for assembling integer objects. The ARM version needs to
9654 handle word-sized values specially. */
9657 arm_assemble_integer (x, size, aligned_p)
9662 if (size == UNITS_PER_WORD && aligned_p)
9664 fputs ("\t.word\t", asm_out_file);
9665 output_addr_const (asm_out_file, x);
9667 /* Mark symbols as position independent. We only do this in the
9668 .text segment, not in the .data segment. */
9669 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
9670 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
9672 if (GET_CODE (x) == SYMBOL_REF
9673 && (CONSTANT_POOL_ADDRESS_P (x)
9674 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0))))
9675 fputs ("(GOTOFF)", asm_out_file);
9676 else if (GET_CODE (x) == LABEL_REF)
9677 fputs ("(GOTOFF)", asm_out_file);
9679 fputs ("(GOT)", asm_out_file);
9681 fputc ('\n', asm_out_file);
9685 return default_assemble_integer (x, size, aligned_p);
9689 /* A finite state machine takes care of noticing whether or not instructions
9690 can be conditionally executed, and thus decrease execution time and code
9691 size by deleting branch instructions. The fsm is controlled by
9692 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9694 /* The state of the fsm controlling condition codes are:
9695 0: normal, do nothing special
9696 1: make ASM_OUTPUT_OPCODE not output this instruction
9697 2: make ASM_OUTPUT_OPCODE not output this instruction
9698 3: make instructions conditional
9699 4: make instructions conditional
9701 State transitions (state->state by whom under condition):
9702 0 -> 1 final_prescan_insn if the `target' is a label
9703 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9704 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9705 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9706 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9707 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9708 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9709 (the target insn is arm_target_insn).
9711 If the jump clobbers the conditions then we use states 2 and 4.
9713 A similar thing can be done with conditional return insns.
9715 XXX In case the `target' is an unconditional branch, this conditionalising
9716 of the instructions always reduces code size, but not always execution
9717 time. But then, I want to reduce the code size to somewhere near what
9718 /bin/cc produces. */
9720 /* Returns the index of the ARM condition code string in
9721 `arm_condition_codes'. COMPARISON should be an rtx like
9722 `(eq (...) (...))'. */
9724 static enum arm_cond_code
9725 get_arm_condition_code (comparison)
9728 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
9730 enum rtx_code comp_code = GET_CODE (comparison);
9732 if (GET_MODE_CLASS (mode) != MODE_CC)
9733 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
9734 XEXP (comparison, 1));
9738 case CC_DNEmode: code = ARM_NE; goto dominance;
9739 case CC_DEQmode: code = ARM_EQ; goto dominance;
9740 case CC_DGEmode: code = ARM_GE; goto dominance;
9741 case CC_DGTmode: code = ARM_GT; goto dominance;
9742 case CC_DLEmode: code = ARM_LE; goto dominance;
9743 case CC_DLTmode: code = ARM_LT; goto dominance;
9744 case CC_DGEUmode: code = ARM_CS; goto dominance;
9745 case CC_DGTUmode: code = ARM_HI; goto dominance;
9746 case CC_DLEUmode: code = ARM_LS; goto dominance;
9747 case CC_DLTUmode: code = ARM_CC;
9750 if (comp_code != EQ && comp_code != NE)
9753 if (comp_code == EQ)
9754 return ARM_INVERSE_CONDITION_CODE (code);
9760 case NE: return ARM_NE;
9761 case EQ: return ARM_EQ;
9762 case GE: return ARM_PL;
9763 case LT: return ARM_MI;
9770 case NE: return ARM_NE;
9771 case EQ: return ARM_EQ;
9777 /* These encodings assume that AC=1 in the FPA system control
9778 byte. This allows us to handle all cases except UNEQ and
9782 case GE: return ARM_GE;
9783 case GT: return ARM_GT;
9784 case LE: return ARM_LS;
9785 case LT: return ARM_MI;
9786 case NE: return ARM_NE;
9787 case EQ: return ARM_EQ;
9788 case ORDERED: return ARM_VC;
9789 case UNORDERED: return ARM_VS;
9790 case UNLT: return ARM_LT;
9791 case UNLE: return ARM_LE;
9792 case UNGT: return ARM_HI;
9793 case UNGE: return ARM_PL;
9794 /* UNEQ and LTGT do not have a representation. */
9795 case UNEQ: /* Fall through. */
9796 case LTGT: /* Fall through. */
9803 case NE: return ARM_NE;
9804 case EQ: return ARM_EQ;
9805 case GE: return ARM_LE;
9806 case GT: return ARM_LT;
9807 case LE: return ARM_GE;
9808 case LT: return ARM_GT;
9809 case GEU: return ARM_LS;
9810 case GTU: return ARM_CC;
9811 case LEU: return ARM_CS;
9812 case LTU: return ARM_HI;
9819 case LTU: return ARM_CS;
9820 case GEU: return ARM_CC;
9827 case NE: return ARM_NE;
9828 case EQ: return ARM_EQ;
9829 case GE: return ARM_GE;
9830 case GT: return ARM_GT;
9831 case LE: return ARM_LE;
9832 case LT: return ARM_LT;
9833 case GEU: return ARM_CS;
9834 case GTU: return ARM_HI;
9835 case LEU: return ARM_LS;
9836 case LTU: return ARM_CC;
9848 arm_final_prescan_insn (insn)
9851 /* BODY will hold the body of INSN. */
9852 rtx body = PATTERN (insn);
9854 /* This will be 1 if trying to repeat the trick, and things need to be
9855 reversed if it appears to fail. */
9858 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9859 taken are clobbered, even if the rtl suggests otherwise. It also
9860 means that we have to grub around within the jump expression to find
9861 out what the conditions are when the jump isn't taken. */
9862 int jump_clobbers = 0;
9864 /* If we start with a return insn, we only succeed if we find another one. */
9865 int seeking_return = 0;
9867 /* START_INSN will hold the insn from where we start looking. This is the
9868 first insn after the following code_label if REVERSE is true. */
9869 rtx start_insn = insn;
9871 /* If in state 4, check if the target branch is reached, in order to
9872 change back to state 0. */
9873 if (arm_ccfsm_state == 4)
9875 if (insn == arm_target_insn)
9877 arm_target_insn = NULL;
9878 arm_ccfsm_state = 0;
9883 /* If in state 3, it is possible to repeat the trick, if this insn is an
9884 unconditional branch to a label, and immediately following this branch
9885 is the previous target label which is only used once, and the label this
9886 branch jumps to is not too far off. */
9887 if (arm_ccfsm_state == 3)
9889 if (simplejump_p (insn))
9891 start_insn = next_nonnote_insn (start_insn);
9892 if (GET_CODE (start_insn) == BARRIER)
9894 /* XXX Isn't this always a barrier? */
9895 start_insn = next_nonnote_insn (start_insn);
9897 if (GET_CODE (start_insn) == CODE_LABEL
9898 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9899 && LABEL_NUSES (start_insn) == 1)
9904 else if (GET_CODE (body) == RETURN)
9906 start_insn = next_nonnote_insn (start_insn);
9907 if (GET_CODE (start_insn) == BARRIER)
9908 start_insn = next_nonnote_insn (start_insn);
9909 if (GET_CODE (start_insn) == CODE_LABEL
9910 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
9911 && LABEL_NUSES (start_insn) == 1)
9923 if (arm_ccfsm_state != 0 && !reverse)
9925 if (GET_CODE (insn) != JUMP_INSN)
9928 /* This jump might be paralleled with a clobber of the condition codes
9929 the jump should always come first */
9930 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
9931 body = XVECEXP (body, 0, 0);
9934 /* If this is a conditional return then we don't want to know */
9935 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
9936 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
9937 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
9938 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
9943 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
9944 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
9947 int fail = FALSE, succeed = FALSE;
9948 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
9949 int then_not_else = TRUE;
9950 rtx this_insn = start_insn, label = 0;
9952 /* If the jump cannot be done with one instruction, we cannot
9953 conditionally execute the instruction in the inverse case. */
9954 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
9960 /* Register the insn jumped to. */
9963 if (!seeking_return)
9964 label = XEXP (SET_SRC (body), 0);
9966 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
9967 label = XEXP (XEXP (SET_SRC (body), 1), 0);
9968 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
9970 label = XEXP (XEXP (SET_SRC (body), 2), 0);
9971 then_not_else = FALSE;
9973 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
9975 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
9978 then_not_else = FALSE;
9983 /* See how many insns this branch skips, and what kind of insns. If all
9984 insns are okay, and the label or unconditional branch to the same
9985 label is not too far away, succeed. */
9986 for (insns_skipped = 0;
9987 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
9991 this_insn = next_nonnote_insn (this_insn);
9995 switch (GET_CODE (this_insn))
9998 /* Succeed if it is the target label, otherwise fail since
9999 control falls in from somewhere else. */
10000 if (this_insn == label)
10004 arm_ccfsm_state = 2;
10005 this_insn = next_nonnote_insn (this_insn);
10008 arm_ccfsm_state = 1;
10016 /* Succeed if the following insn is the target label.
10018 If return insns are used then the last insn in a function
10019 will be a barrier. */
10020 this_insn = next_nonnote_insn (this_insn);
10021 if (this_insn && this_insn == label)
10025 arm_ccfsm_state = 2;
10026 this_insn = next_nonnote_insn (this_insn);
10029 arm_ccfsm_state = 1;
10037 /* If using 32-bit addresses the cc is not preserved over
10039 if (TARGET_APCS_32)
10041 /* Succeed if the following insn is the target label,
10042 or if the following two insns are a barrier and
10043 the target label. */
10044 this_insn = next_nonnote_insn (this_insn);
10045 if (this_insn && GET_CODE (this_insn) == BARRIER)
10046 this_insn = next_nonnote_insn (this_insn);
10048 if (this_insn && this_insn == label
10049 && insns_skipped < max_insns_skipped)
10053 arm_ccfsm_state = 2;
10054 this_insn = next_nonnote_insn (this_insn);
10057 arm_ccfsm_state = 1;
10066 /* If this is an unconditional branch to the same label, succeed.
10067 If it is to another label, do nothing. If it is conditional,
10069 /* XXX Probably, the tests for SET and the PC are unnecessary. */
10071 scanbody = PATTERN (this_insn);
10072 if (GET_CODE (scanbody) == SET
10073 && GET_CODE (SET_DEST (scanbody)) == PC)
10075 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10076 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10078 arm_ccfsm_state = 2;
10081 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10084 /* Fail if a conditional return is undesirable (eg on a
10085 StrongARM), but still allow this if optimizing for size. */
10086 else if (GET_CODE (scanbody) == RETURN
10087 && !use_return_insn (TRUE)
10090 else if (GET_CODE (scanbody) == RETURN
10093 arm_ccfsm_state = 2;
10096 else if (GET_CODE (scanbody) == PARALLEL)
10098 switch (get_attr_conds (this_insn))
10108 fail = TRUE; /* Unrecognized jump (eg epilogue). */
10113 /* Instructions using or affecting the condition codes make it
10115 scanbody = PATTERN (this_insn);
10116 if (!(GET_CODE (scanbody) == SET
10117 || GET_CODE (scanbody) == PARALLEL)
10118 || get_attr_conds (this_insn) != CONDS_NOCOND)
10121 /* A conditional cirrus instruction must be followed by
10122 a non Cirrus instruction. However, since we
10123 conditionalize instructions in this function and by
10124 the time we get here we can't add instructions
10125 (nops), because shorten_branches() has already been
10126 called, we will disable conditionalizing Cirrus
10127 instructions to be safe. */
10128 if (GET_CODE (scanbody) != USE
10129 && GET_CODE (scanbody) != CLOBBER
10130 && get_attr_cirrus (this_insn) != CIRRUS_NO)
10140 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
10141 arm_target_label = CODE_LABEL_NUMBER (label);
10142 else if (seeking_return || arm_ccfsm_state == 2)
10144 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
10146 this_insn = next_nonnote_insn (this_insn);
10147 if (this_insn && (GET_CODE (this_insn) == BARRIER
10148 || GET_CODE (this_insn) == CODE_LABEL))
10153 /* Oh, dear! we ran off the end.. give up */
10154 recog (PATTERN (insn), insn, NULL);
10155 arm_ccfsm_state = 0;
10156 arm_target_insn = NULL;
10159 arm_target_insn = this_insn;
10168 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
10170 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
10171 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10172 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
10173 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10177 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10180 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
10184 if (reverse || then_not_else)
10185 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10188 /* Restore recog_data (getting the attributes of other insns can
10189 destroy this array, but final.c assumes that it remains intact
10190 across this call; since the insn has been recognized already we
10191 call recog direct). */
10192 recog (PATTERN (insn), insn, NULL);
10196 /* Returns true if REGNO is a valid register
10197 for holding a quantity of tyoe MODE. */
10200 arm_hard_regno_mode_ok (regno, mode)
10201 unsigned int regno;
10202 enum machine_mode mode;
10204 if (GET_MODE_CLASS (mode) == MODE_CC)
10205 return regno == CC_REGNUM;
10208 /* For the Thumb we only allow values bigger than SImode in
10209 registers 0 - 6, so that there is always a second low
10210 register available to hold the upper part of the value.
10211 We probably we ought to ensure that the register is the
10212 start of an even numbered register pair. */
10213 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
10215 if (IS_CIRRUS_REGNUM (regno))
10216 /* We have outlawed SI values in Cirrus registers because they
10217 reside in the lower 32 bits, but SF values reside in the
10218 upper 32 bits. This causes gcc all sorts of grief. We can't
10219 even split the registers into pairs because Cirrus SI values
10220 get sign extended to 64bits-- aldyh. */
10221 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
10223 if (regno <= LAST_ARM_REGNUM)
10224 /* We allow any value to be stored in the general regisetrs. */
10227 if ( regno == FRAME_POINTER_REGNUM
10228 || regno == ARG_POINTER_REGNUM)
10229 /* We only allow integers in the fake hard registers. */
10230 return GET_MODE_CLASS (mode) == MODE_INT;
10232 /* The only registers left are the FPU registers
10233 which we only allow to hold FP values. */
10234 return GET_MODE_CLASS (mode) == MODE_FLOAT
10235 && regno >= FIRST_ARM_FP_REGNUM
10236 && regno <= LAST_ARM_FP_REGNUM;
10240 arm_regno_class (regno)
10245 if (regno == STACK_POINTER_REGNUM)
10247 if (regno == CC_REGNUM)
10254 if ( regno <= LAST_ARM_REGNUM
10255 || regno == FRAME_POINTER_REGNUM
10256 || regno == ARG_POINTER_REGNUM)
10257 return GENERAL_REGS;
10259 if (regno == CC_REGNUM)
10262 if (IS_CIRRUS_REGNUM (regno))
10263 return CIRRUS_REGS;
10268 /* Handle a special case when computing the offset
10269 of an argument from the frame pointer. */
10272 arm_debugger_arg_offset (value, addr)
10278 /* We are only interested if dbxout_parms() failed to compute the offset. */
10282 /* We can only cope with the case where the address is held in a register. */
10283 if (GET_CODE (addr) != REG)
10286 /* If we are using the frame pointer to point at the argument, then
10287 an offset of 0 is correct. */
10288 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
10291 /* If we are using the stack pointer to point at the
10292 argument, then an offset of 0 is correct. */
10293 if ((TARGET_THUMB || !frame_pointer_needed)
10294 && REGNO (addr) == SP_REGNUM)
10297 /* Oh dear. The argument is pointed to by a register rather
10298 than being held in a register, or being stored at a known
10299 offset from the frame pointer. Since GDB only understands
10300 those two kinds of argument we must translate the address
10301 held in the register into an offset from the frame pointer.
10302 We do this by searching through the insns for the function
10303 looking to see where this register gets its value. If the
10304 register is initialized from the frame pointer plus an offset
10305 then we are in luck and we can continue, otherwise we give up.
10307 This code is exercised by producing debugging information
10308 for a function with arguments like this:
10310 double func (double a, double b, int c, double d) {return d;}
10312 Without this code the stab for parameter 'd' will be set to
10313 an offset of 0 from the frame pointer, rather than 8. */
10315 /* The if() statement says:
10317 If the insn is a normal instruction
10318 and if the insn is setting the value in a register
10319 and if the register being set is the register holding the address of the argument
10320 and if the address is computing by an addition
10321 that involves adding to a register
10322 which is the frame pointer
10327 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10329 if ( GET_CODE (insn) == INSN
10330 && GET_CODE (PATTERN (insn)) == SET
10331 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
10332 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
10333 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
10334 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10335 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
10338 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
10347 warning ("unable to compute real location of stacked parameter");
10348 value = 8; /* XXX magic hack */
10354 /* Recursively search through all of the blocks in a function
10355 checking to see if any of the variables created in that
10356 function match the RTX called 'orig'. If they do then
10357 replace them with the RTX called 'new'. */
10360 replace_symbols_in_block (block, orig, new)
10365 for (; block; block = BLOCK_CHAIN (block))
10369 if (!TREE_USED (block))
10372 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
10374 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
10375 || DECL_IGNORED_P (sym)
10376 || TREE_CODE (sym) != VAR_DECL
10377 || DECL_EXTERNAL (sym)
10378 || !rtx_equal_p (DECL_RTL (sym), orig)
10382 SET_DECL_RTL (sym, new);
10385 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
10389 /* Return the number (counting from 0) of
10390 the least significant set bit in MASK. */
10396 number_of_first_bit_set (mask)
10402 (mask & (1 << bit)) == 0;
10409 /* Generate code to return from a thumb function.
10410 If 'reg_containing_return_addr' is -1, then the return address is
10411 actually on the stack, at the stack pointer. */
10413 thumb_exit (f, reg_containing_return_addr, eh_ofs)
10415 int reg_containing_return_addr;
10418 unsigned regs_available_for_popping;
10419 unsigned regs_to_pop;
10421 unsigned available;
10425 int restore_a4 = FALSE;
10427 /* Compute the registers we need to pop. */
10431 /* There is an assumption here, that if eh_ofs is not NULL, the
10432 normal return address will have been pushed. */
10433 if (reg_containing_return_addr == -1 || eh_ofs)
10435 /* When we are generating a return for __builtin_eh_return,
10436 reg_containing_return_addr must specify the return regno. */
10437 if (eh_ofs && reg_containing_return_addr == -1)
10440 regs_to_pop |= 1 << LR_REGNUM;
10444 if (TARGET_BACKTRACE)
10446 /* Restore the (ARM) frame pointer and stack pointer. */
10447 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
10451 /* If there is nothing to pop then just emit the BX instruction and
10453 if (pops_needed == 0)
10456 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
10458 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
10461 /* Otherwise if we are not supporting interworking and we have not created
10462 a backtrace structure and the function was not entered in ARM mode then
10463 just pop the return address straight into the PC. */
10464 else if (!TARGET_INTERWORK
10465 && !TARGET_BACKTRACE
10466 && !is_called_in_ARM_mode (current_function_decl))
10470 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
10471 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
10472 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
10475 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
10480 /* Find out how many of the (return) argument registers we can corrupt. */
10481 regs_available_for_popping = 0;
10483 /* If returning via __builtin_eh_return, the bottom three registers
10484 all contain information needed for the return. */
10490 /* If we can deduce the registers used from the function's
10491 return value. This is more reliable that examining
10492 regs_ever_live[] because that will be set if the register is
10493 ever used in the function, not just if the register is used
10494 to hold a return value. */
10496 if (current_function_return_rtx != 0)
10497 mode = GET_MODE (current_function_return_rtx);
10500 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10502 size = GET_MODE_SIZE (mode);
10506 /* In a void function we can use any argument register.
10507 In a function that returns a structure on the stack
10508 we can use the second and third argument registers. */
10509 if (mode == VOIDmode)
10510 regs_available_for_popping =
10511 (1 << ARG_REGISTER (1))
10512 | (1 << ARG_REGISTER (2))
10513 | (1 << ARG_REGISTER (3));
10515 regs_available_for_popping =
10516 (1 << ARG_REGISTER (2))
10517 | (1 << ARG_REGISTER (3));
10519 else if (size <= 4)
10520 regs_available_for_popping =
10521 (1 << ARG_REGISTER (2))
10522 | (1 << ARG_REGISTER (3));
10523 else if (size <= 8)
10524 regs_available_for_popping =
10525 (1 << ARG_REGISTER (3));
10528 /* Match registers to be popped with registers into which we pop them. */
10529 for (available = regs_available_for_popping,
10530 required = regs_to_pop;
10531 required != 0 && available != 0;
10532 available &= ~(available & - available),
10533 required &= ~(required & - required))
10536 /* If we have any popping registers left over, remove them. */
10538 regs_available_for_popping &= ~available;
10540 /* Otherwise if we need another popping register we can use
10541 the fourth argument register. */
10542 else if (pops_needed)
10544 /* If we have not found any free argument registers and
10545 reg a4 contains the return address, we must move it. */
10546 if (regs_available_for_popping == 0
10547 && reg_containing_return_addr == LAST_ARG_REGNUM)
10549 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
10550 reg_containing_return_addr = LR_REGNUM;
10552 else if (size > 12)
10554 /* Register a4 is being used to hold part of the return value,
10555 but we have dire need of a free, low register. */
10558 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
10561 if (reg_containing_return_addr != LAST_ARG_REGNUM)
10563 /* The fourth argument register is available. */
10564 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
10570 /* Pop as many registers as we can. */
10571 thumb_pushpop (f, regs_available_for_popping, FALSE);
10573 /* Process the registers we popped. */
10574 if (reg_containing_return_addr == -1)
10576 /* The return address was popped into the lowest numbered register. */
10577 regs_to_pop &= ~(1 << LR_REGNUM);
10579 reg_containing_return_addr =
10580 number_of_first_bit_set (regs_available_for_popping);
10582 /* Remove this register for the mask of available registers, so that
10583 the return address will not be corrupted by further pops. */
10584 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
10587 /* If we popped other registers then handle them here. */
10588 if (regs_available_for_popping)
10592 /* Work out which register currently contains the frame pointer. */
10593 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
10595 /* Move it into the correct place. */
10596 asm_fprintf (f, "\tmov\t%r, %r\n",
10597 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
10599 /* (Temporarily) remove it from the mask of popped registers. */
10600 regs_available_for_popping &= ~(1 << frame_pointer);
10601 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
10603 if (regs_available_for_popping)
10607 /* We popped the stack pointer as well,
10608 find the register that contains it. */
10609 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
10611 /* Move it into the stack register. */
10612 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
10614 /* At this point we have popped all necessary registers, so
10615 do not worry about restoring regs_available_for_popping
10616 to its correct value:
10618 assert (pops_needed == 0)
10619 assert (regs_available_for_popping == (1 << frame_pointer))
10620 assert (regs_to_pop == (1 << STACK_POINTER)) */
10624 /* Since we have just move the popped value into the frame
10625 pointer, the popping register is available for reuse, and
10626 we know that we still have the stack pointer left to pop. */
10627 regs_available_for_popping |= (1 << frame_pointer);
10631 /* If we still have registers left on the stack, but we no longer have
10632 any registers into which we can pop them, then we must move the return
10633 address into the link register and make available the register that
10635 if (regs_available_for_popping == 0 && pops_needed > 0)
10637 regs_available_for_popping |= 1 << reg_containing_return_addr;
10639 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
10640 reg_containing_return_addr);
10642 reg_containing_return_addr = LR_REGNUM;
10645 /* If we have registers left on the stack then pop some more.
10646 We know that at most we will want to pop FP and SP. */
10647 if (pops_needed > 0)
10652 thumb_pushpop (f, regs_available_for_popping, FALSE);
10654 /* We have popped either FP or SP.
10655 Move whichever one it is into the correct register. */
10656 popped_into = number_of_first_bit_set (regs_available_for_popping);
10657 move_to = number_of_first_bit_set (regs_to_pop);
10659 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
10661 regs_to_pop &= ~(1 << move_to);
10666 /* If we still have not popped everything then we must have only
10667 had one register available to us and we are now popping the SP. */
10668 if (pops_needed > 0)
10672 thumb_pushpop (f, regs_available_for_popping, FALSE);
10674 popped_into = number_of_first_bit_set (regs_available_for_popping);
10676 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
10678 assert (regs_to_pop == (1 << STACK_POINTER))
10679 assert (pops_needed == 1)
10683 /* If necessary restore the a4 register. */
10686 if (reg_containing_return_addr != LR_REGNUM)
10688 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
10689 reg_containing_return_addr = LR_REGNUM;
10692 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10696 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
10698 /* Return to caller. */
10699 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
10702 /* Emit code to push or pop registers to or from the stack. */
10705 thumb_pushpop (f, mask, push)
10711 int lo_mask = mask & 0xFF;
10713 if (lo_mask == 0 && !push && (mask & (1 << 15)))
10715 /* Special case. Do not generate a POP PC statement here, do it in
10717 thumb_exit (f, -1, NULL_RTX);
10721 fprintf (f, "\t%s\t{", push ? "push" : "pop");
10723 /* Look at the low registers first. */
10724 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
10728 asm_fprintf (f, "%r", regno);
10730 if ((lo_mask & ~1) != 0)
10735 if (push && (mask & (1 << LR_REGNUM)))
10737 /* Catch pushing the LR. */
10741 asm_fprintf (f, "%r", LR_REGNUM);
10743 else if (!push && (mask & (1 << PC_REGNUM)))
10745 /* Catch popping the PC. */
10746 if (TARGET_INTERWORK || TARGET_BACKTRACE)
10748 /* The PC is never poped directly, instead
10749 it is popped into r3 and then BX is used. */
10750 fprintf (f, "}\n");
10752 thumb_exit (f, -1, NULL_RTX);
10761 asm_fprintf (f, "%r", PC_REGNUM);
10765 fprintf (f, "}\n");
10769 thumb_final_prescan_insn (insn)
10772 if (flag_print_asm_name)
10773 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
10774 INSN_ADDRESSES (INSN_UID (insn)));
10778 thumb_shiftable_const (val)
10779 unsigned HOST_WIDE_INT val;
10781 unsigned HOST_WIDE_INT mask = 0xff;
10784 if (val == 0) /* XXX */
10787 for (i = 0; i < 25; i++)
10788 if ((val & (mask << i)) == val)
10794 /* Returns nonzero if the current function contains,
10795 or might contain a far jump. */
10798 thumb_far_jump_used_p (in_prologue)
10803 /* This test is only important for leaf functions. */
10804 /* assert (!leaf_function_p ()); */
10806 /* If we have already decided that far jumps may be used,
10807 do not bother checking again, and always return true even if
10808 it turns out that they are not being used. Once we have made
10809 the decision that far jumps are present (and that hence the link
10810 register will be pushed onto the stack) we cannot go back on it. */
10811 if (cfun->machine->far_jump_used)
10814 /* If this function is not being called from the prologue/epilogue
10815 generation code then it must be being called from the
10816 INITIAL_ELIMINATION_OFFSET macro. */
10819 /* In this case we know that we are being asked about the elimination
10820 of the arg pointer register. If that register is not being used,
10821 then there are no arguments on the stack, and we do not have to
10822 worry that a far jump might force the prologue to push the link
10823 register, changing the stack offsets. In this case we can just
10824 return false, since the presence of far jumps in the function will
10825 not affect stack offsets.
10827 If the arg pointer is live (or if it was live, but has now been
10828 eliminated and so set to dead) then we do have to test to see if
10829 the function might contain a far jump. This test can lead to some
10830 false negatives, since before reload is completed, then length of
10831 branch instructions is not known, so gcc defaults to returning their
10832 longest length, which in turn sets the far jump attribute to true.
10834 A false negative will not result in bad code being generated, but it
10835 will result in a needless push and pop of the link register. We
10836 hope that this does not occur too often. */
10837 if (regs_ever_live [ARG_POINTER_REGNUM])
10838 cfun->machine->arg_pointer_live = 1;
10839 else if (!cfun->machine->arg_pointer_live)
10843 /* Check to see if the function contains a branch
10844 insn with the far jump attribute set. */
10845 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10847 if (GET_CODE (insn) == JUMP_INSN
10848 /* Ignore tablejump patterns. */
10849 && GET_CODE (PATTERN (insn)) != ADDR_VEC
10850 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
10851 && get_attr_far_jump (insn) == FAR_JUMP_YES
10854 /* Record the fact that we have decied that
10855 the function does use far jumps. */
10856 cfun->machine->far_jump_used = 1;
10864 /* Return nonzero if FUNC must be entered in ARM mode. */
10867 is_called_in_ARM_mode (func)
10870 if (TREE_CODE (func) != FUNCTION_DECL)
10873 /* Ignore the problem about functions whoes address is taken. */
10874 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
10878 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
10884 /* The bits which aren't usefully expanded as rtl. */
10887 thumb_unexpanded_epilogue ()
10890 int live_regs_mask = 0;
10891 int high_regs_pushed = 0;
10892 int leaf_function = leaf_function_p ();
10893 int had_to_push_lr;
10894 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
10896 if (return_used_this_function)
10899 if (IS_NAKED (arm_current_func_type ()))
10902 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10903 if (THUMB_REG_PUSHED_P (regno))
10904 live_regs_mask |= 1 << regno;
10906 for (regno = 8; regno < 13; regno++)
10907 if (THUMB_REG_PUSHED_P (regno))
10908 high_regs_pushed++;
10910 /* The prolog may have pushed some high registers to use as
10911 work registers. eg the testuite file:
10912 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
10913 compiles to produce:
10914 push {r4, r5, r6, r7, lr}
10918 as part of the prolog. We have to undo that pushing here. */
10920 if (high_regs_pushed)
10922 int mask = live_regs_mask;
10928 /* If we can deduce the registers used from the function's return value.
10929 This is more reliable that examining regs_ever_live[] because that
10930 will be set if the register is ever used in the function, not just if
10931 the register is used to hold a return value. */
10933 if (current_function_return_rtx != 0)
10934 mode = GET_MODE (current_function_return_rtx);
10937 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10939 size = GET_MODE_SIZE (mode);
10941 /* Unless we are returning a type of size > 12 register r3 is
10947 /* Oh dear! We have no low registers into which we can pop
10950 ("no low registers available for popping high registers");
10952 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
10953 if (THUMB_REG_PUSHED_P (next_hi_reg))
10956 while (high_regs_pushed)
10958 /* Find lo register(s) into which the high register(s) can
10960 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10962 if (mask & (1 << regno))
10963 high_regs_pushed--;
10964 if (high_regs_pushed == 0)
10968 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
10970 /* Pop the values into the low register(s). */
10971 thumb_pushpop (asm_out_file, mask, 0);
10973 /* Move the value(s) into the high registers. */
10974 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10976 if (mask & (1 << regno))
10978 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
10981 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
10982 if (THUMB_REG_PUSHED_P (next_hi_reg))
10989 had_to_push_lr = (live_regs_mask || !leaf_function
10990 || thumb_far_jump_used_p (1));
10992 if (TARGET_BACKTRACE
10993 && ((live_regs_mask & 0xFF) == 0)
10994 && regs_ever_live [LAST_ARG_REGNUM] != 0)
10996 /* The stack backtrace structure creation code had to
10997 push R7 in order to get a work register, so we pop
10999 live_regs_mask |= (1 << LAST_LO_REGNUM);
11002 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
11005 && !is_called_in_ARM_mode (current_function_decl)
11007 live_regs_mask |= 1 << PC_REGNUM;
11009 /* Either no argument registers were pushed or a backtrace
11010 structure was created which includes an adjusted stack
11011 pointer, so just pop everything. */
11012 if (live_regs_mask)
11013 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11016 thumb_exit (asm_out_file, 2, eh_ofs);
11017 /* We have either just popped the return address into the
11018 PC or it is was kept in LR for the entire function or
11019 it is still on the stack because we do not want to
11020 return by doing a pop {pc}. */
11021 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
11022 thumb_exit (asm_out_file,
11024 && is_called_in_ARM_mode (current_function_decl)) ?
11025 -1 : LR_REGNUM, NULL_RTX);
11029 /* Pop everything but the return address. */
11030 live_regs_mask &= ~(1 << PC_REGNUM);
11032 if (live_regs_mask)
11033 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11035 if (had_to_push_lr)
11036 /* Get the return address into a temporary register. */
11037 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
11039 /* Remove the argument registers that were pushed onto the stack. */
11040 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
11041 SP_REGNUM, SP_REGNUM,
11042 current_function_pretend_args_size);
11045 thumb_exit (asm_out_file, 2, eh_ofs);
11047 thumb_exit (asm_out_file,
11048 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
11054 /* Functions to save and restore machine-specific function data. */
11056 static struct machine_function *
11057 arm_init_machine_status ()
11059 struct machine_function *machine;
11060 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
11062 #if ARM_FT_UNKNOWN != 0
11063 machine->func_type = ARM_FT_UNKNOWN;
11068 /* Return an RTX indicating where the return address to the
11069 calling function can be found. */
11072 arm_return_addr (count, frame)
11074 rtx frame ATTRIBUTE_UNUSED;
11079 if (TARGET_APCS_32)
11080 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
11083 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
11084 GEN_INT (RETURN_ADDR_MASK26));
11085 return get_func_hard_reg_initial_val (cfun, lr);
11089 /* Do anything needed before RTL is emitted for each function. */
11092 arm_init_expanders ()
11094 /* Arrange to initialize and mark the machine per-function status. */
11095 init_machine_status = arm_init_machine_status;
11099 thumb_get_frame_size ()
11103 int base_size = ROUND_UP_WORD (get_frame_size ());
11104 int count_regs = 0;
11105 int entry_size = 0;
11108 if (! TARGET_THUMB)
11111 if (! TARGET_ATPCS)
11114 /* We need to know if we are a leaf function. Unfortunately, it
11115 is possible to be called after start_sequence has been called,
11116 which causes get_insns to return the insns for the sequence,
11117 not the function, which will cause leaf_function_p to return
11118 the incorrect result.
11120 To work around this, we cache the computed frame size. This
11121 works because we will only be calling RTL expanders that need
11122 to know about leaf functions once reload has completed, and the
11123 frame size cannot be changed after that time, so we can safely
11124 use the cached value. */
11126 if (reload_completed)
11127 return cfun->machine->frame_size;
11129 leaf = leaf_function_p ();
11131 /* A leaf function does not need any stack alignment if it has nothing
11133 if (leaf && base_size == 0)
11135 cfun->machine->frame_size = 0;
11139 /* We know that SP will be word aligned on entry, and we must
11140 preserve that condition at any subroutine call. But those are
11141 the only constraints. */
11143 /* Space for variadic functions. */
11144 if (current_function_pretend_args_size)
11145 entry_size += current_function_pretend_args_size;
11147 /* Space for pushed lo registers. */
11148 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11149 if (THUMB_REG_PUSHED_P (regno))
11152 /* Space for backtrace structure. */
11153 if (TARGET_BACKTRACE)
11155 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
11161 if (count_regs || !leaf || thumb_far_jump_used_p (1))
11162 count_regs++; /* LR */
11164 entry_size += count_regs * 4;
11167 /* Space for pushed hi regs. */
11168 for (regno = 8; regno < 13; regno++)
11169 if (THUMB_REG_PUSHED_P (regno))
11172 entry_size += count_regs * 4;
11174 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
11176 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
11179 cfun->machine->frame_size = base_size;
11184 /* Generate the rest of a function's prologue. */
11187 thumb_expand_prologue ()
11189 HOST_WIDE_INT amount = (thumb_get_frame_size ()
11190 + current_function_outgoing_args_size);
11191 unsigned long func_type;
11193 func_type = arm_current_func_type ();
11195 /* Naked functions don't have prologues. */
11196 if (IS_NAKED (func_type))
11199 if (IS_INTERRUPT (func_type))
11201 error ("interrupt Service Routines cannot be coded in Thumb mode");
11205 if (frame_pointer_needed)
11206 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
11210 amount = ROUND_UP_WORD (amount);
11213 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11214 GEN_INT (- amount)));
11220 /* The stack decrement is too big for an immediate value in a single
11221 insn. In theory we could issue multiple subtracts, but after
11222 three of them it becomes more space efficient to place the full
11223 value in the constant pool and load into a register. (Also the
11224 ARM debugger really likes to see only one stack decrement per
11225 function). So instead we look for a scratch register into which
11226 we can load the decrement, and then we subtract this from the
11227 stack pointer. Unfortunately on the thumb the only available
11228 scratch registers are the argument registers, and we cannot use
11229 these as they may hold arguments to the function. Instead we
11230 attempt to locate a call preserved register which is used by this
11231 function. If we can find one, then we know that it will have
11232 been pushed at the start of the prologue and so we can corrupt
11234 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
11235 if (THUMB_REG_PUSHED_P (regno)
11236 && !(frame_pointer_needed
11237 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
11240 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
11242 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
11244 /* Choose an arbitrary, non-argument low register. */
11245 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
11247 /* Save it by copying it into a high, scratch register. */
11248 emit_insn (gen_movsi (spare, reg));
11249 /* Add a USE to stop propagate_one_insn() from barfing. */
11250 emit_insn (gen_prologue_use (spare));
11252 /* Decrement the stack. */
11253 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
11254 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11257 /* Restore the low register's original value. */
11258 emit_insn (gen_movsi (reg, spare));
11260 /* Emit a USE of the restored scratch register, so that flow
11261 analysis will not consider the restore redundant. The
11262 register won't be used again in this function and isn't
11263 restored by the epilogue. */
11264 emit_insn (gen_prologue_use (reg));
11268 reg = gen_rtx (REG, SImode, regno);
11270 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
11271 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11277 if (current_function_profile || TARGET_NO_SCHED_PRO)
11278 emit_insn (gen_blockage ());
11282 thumb_expand_epilogue ()
11284 HOST_WIDE_INT amount = (thumb_get_frame_size ()
11285 + current_function_outgoing_args_size);
11287 /* Naked functions don't have prologues. */
11288 if (IS_NAKED (arm_current_func_type ()))
11291 if (frame_pointer_needed)
11292 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
11295 amount = ROUND_UP_WORD (amount);
11298 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11299 GEN_INT (amount)));
11302 /* r3 is always free in the epilogue. */
11303 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
11305 emit_insn (gen_movsi (reg, GEN_INT (amount)));
11306 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
11310 /* Emit a USE (stack_pointer_rtx), so that
11311 the stack adjustment will not be deleted. */
11312 emit_insn (gen_prologue_use (stack_pointer_rtx));
11314 if (current_function_profile || TARGET_NO_SCHED_PRO)
11315 emit_insn (gen_blockage ());
11319 thumb_output_function_prologue (f, size)
11321 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
11323 int live_regs_mask = 0;
11324 int high_regs_pushed = 0;
11327 if (IS_NAKED (arm_current_func_type ()))
11330 if (is_called_in_ARM_mode (current_function_decl))
11334 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
11336 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
11338 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11340 /* Generate code sequence to switch us into Thumb mode. */
11341 /* The .code 32 directive has already been emitted by
11342 ASM_DECLARE_FUNCTION_NAME. */
11343 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
11344 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
11346 /* Generate a label, so that the debugger will notice the
11347 change in instruction sets. This label is also used by
11348 the assembler to bypass the ARM code when this function
11349 is called from a Thumb encoded function elsewhere in the
11350 same file. Hence the definition of STUB_NAME here must
11351 agree with the definition in gas/config/tc-arm.c */
11353 #define STUB_NAME ".real_start_of"
11355 fprintf (f, "\t.code\t16\n");
11357 if (arm_dllexport_name_p (name))
11358 name = arm_strip_name_encoding (name);
11360 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
11361 fprintf (f, "\t.thumb_func\n");
11362 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
11365 if (current_function_pretend_args_size)
11367 if (cfun->machine->uses_anonymous_args)
11371 fprintf (f, "\tpush\t{");
11373 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
11375 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
11376 regno <= LAST_ARG_REGNUM;
11378 asm_fprintf (f, "%r%s", regno,
11379 regno == LAST_ARG_REGNUM ? "" : ", ");
11381 fprintf (f, "}\n");
11384 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
11385 SP_REGNUM, SP_REGNUM,
11386 current_function_pretend_args_size);
11389 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11390 if (THUMB_REG_PUSHED_P (regno))
11391 live_regs_mask |= 1 << regno;
11393 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
11394 live_regs_mask |= 1 << LR_REGNUM;
11396 if (TARGET_BACKTRACE)
11399 int work_register = 0;
11402 /* We have been asked to create a stack backtrace structure.
11403 The code looks like this:
11407 0 sub SP, #16 Reserve space for 4 registers.
11408 2 push {R7} Get a work register.
11409 4 add R7, SP, #20 Get the stack pointer before the push.
11410 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
11411 8 mov R7, PC Get hold of the start of this code plus 12.
11412 10 str R7, [SP, #16] Store it.
11413 12 mov R7, FP Get hold of the current frame pointer.
11414 14 str R7, [SP, #4] Store it.
11415 16 mov R7, LR Get hold of the current return address.
11416 18 str R7, [SP, #12] Store it.
11417 20 add R7, SP, #16 Point at the start of the backtrace structure.
11418 22 mov FP, R7 Put this value into the frame pointer. */
11420 if ((live_regs_mask & 0xFF) == 0)
11422 /* See if the a4 register is free. */
11424 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
11425 work_register = LAST_ARG_REGNUM;
11426 else /* We must push a register of our own */
11427 live_regs_mask |= (1 << LAST_LO_REGNUM);
11430 if (work_register == 0)
11432 /* Select a register from the list that will be pushed to
11433 use as our work register. */
11434 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
11435 if ((1 << work_register) & live_regs_mask)
11440 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
11441 SP_REGNUM, SP_REGNUM);
11443 if (live_regs_mask)
11444 thumb_pushpop (f, live_regs_mask, 1);
11446 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
11447 if (wr & live_regs_mask)
11450 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
11451 offset + 16 + current_function_pretend_args_size);
11453 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11456 /* Make sure that the instruction fetching the PC is in the right place
11457 to calculate "start of backtrace creation code + 12". */
11458 if (live_regs_mask)
11460 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
11461 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11463 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
11464 ARM_HARD_FRAME_POINTER_REGNUM);
11465 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11470 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
11471 ARM_HARD_FRAME_POINTER_REGNUM);
11472 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11474 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
11475 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11479 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
11480 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
11482 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
11484 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
11485 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
11487 else if (live_regs_mask)
11488 thumb_pushpop (f, live_regs_mask, 1);
11490 for (regno = 8; regno < 13; regno++)
11491 if (THUMB_REG_PUSHED_P (regno))
11492 high_regs_pushed++;
11494 if (high_regs_pushed)
11496 int pushable_regs = 0;
11497 int mask = live_regs_mask & 0xff;
11500 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
11501 if (THUMB_REG_PUSHED_P (next_hi_reg))
11504 pushable_regs = mask;
11506 if (pushable_regs == 0)
11508 /* Desperation time -- this probably will never happen. */
11509 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
11510 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
11511 mask = 1 << LAST_ARG_REGNUM;
11514 while (high_regs_pushed > 0)
11516 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
11518 if (mask & (1 << regno))
11520 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
11522 high_regs_pushed--;
11524 if (high_regs_pushed)
11526 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
11528 if (THUMB_REG_PUSHED_P (next_hi_reg))
11533 mask &= ~((1 << regno) - 1);
11539 thumb_pushpop (f, mask, 1);
11542 if (pushable_regs == 0
11543 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
11544 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
11548 /* Handle the case of a double word load into a low register from
11549 a computed memory address. The computed address may involve a
11550 register which is overwritten by the load. */
11553 thumb_load_double_from_address (operands)
11562 if (GET_CODE (operands[0]) != REG)
11565 if (GET_CODE (operands[1]) != MEM)
11568 /* Get the memory address. */
11569 addr = XEXP (operands[1], 0);
11571 /* Work out how the memory address is computed. */
11572 switch (GET_CODE (addr))
11575 operands[2] = gen_rtx (MEM, SImode,
11576 plus_constant (XEXP (operands[1], 0), 4));
11578 if (REGNO (operands[0]) == REGNO (addr))
11580 output_asm_insn ("ldr\t%H0, %2", operands);
11581 output_asm_insn ("ldr\t%0, %1", operands);
11585 output_asm_insn ("ldr\t%0, %1", operands);
11586 output_asm_insn ("ldr\t%H0, %2", operands);
11591 /* Compute <address> + 4 for the high order load. */
11592 operands[2] = gen_rtx (MEM, SImode,
11593 plus_constant (XEXP (operands[1], 0), 4));
11595 output_asm_insn ("ldr\t%0, %1", operands);
11596 output_asm_insn ("ldr\t%H0, %2", operands);
11600 arg1 = XEXP (addr, 0);
11601 arg2 = XEXP (addr, 1);
11603 if (CONSTANT_P (arg1))
11604 base = arg2, offset = arg1;
11606 base = arg1, offset = arg2;
11608 if (GET_CODE (base) != REG)
11611 /* Catch the case of <address> = <reg> + <reg> */
11612 if (GET_CODE (offset) == REG)
11614 int reg_offset = REGNO (offset);
11615 int reg_base = REGNO (base);
11616 int reg_dest = REGNO (operands[0]);
11618 /* Add the base and offset registers together into the
11619 higher destination register. */
11620 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
11621 reg_dest + 1, reg_base, reg_offset);
11623 /* Load the lower destination register from the address in
11624 the higher destination register. */
11625 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
11626 reg_dest, reg_dest + 1);
11628 /* Load the higher destination register from its own address
11630 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
11631 reg_dest + 1, reg_dest + 1);
11635 /* Compute <address> + 4 for the high order load. */
11636 operands[2] = gen_rtx (MEM, SImode,
11637 plus_constant (XEXP (operands[1], 0), 4));
11639 /* If the computed address is held in the low order register
11640 then load the high order register first, otherwise always
11641 load the low order register first. */
11642 if (REGNO (operands[0]) == REGNO (base))
11644 output_asm_insn ("ldr\t%H0, %2", operands);
11645 output_asm_insn ("ldr\t%0, %1", operands);
11649 output_asm_insn ("ldr\t%0, %1", operands);
11650 output_asm_insn ("ldr\t%H0, %2", operands);
11656 /* With no registers to worry about we can just load the value
11658 operands[2] = gen_rtx (MEM, SImode,
11659 plus_constant (XEXP (operands[1], 0), 4));
11661 output_asm_insn ("ldr\t%H0, %2", operands);
11662 output_asm_insn ("ldr\t%0, %1", operands);
11675 thumb_output_move_mem_multiple (n, operands)
11684 if (REGNO (operands[4]) > REGNO (operands[5]))
11687 operands[4] = operands[5];
11690 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
11691 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
11695 if (REGNO (operands[4]) > REGNO (operands[5]))
11698 operands[4] = operands[5];
11701 if (REGNO (operands[5]) > REGNO (operands[6]))
11704 operands[5] = operands[6];
11707 if (REGNO (operands[4]) > REGNO (operands[5]))
11710 operands[4] = operands[5];
11714 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
11715 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
11725 /* Routines for generating rtl. */
11728 thumb_expand_movstrqi (operands)
11731 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
11732 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
11733 HOST_WIDE_INT len = INTVAL (operands[2]);
11734 HOST_WIDE_INT offset = 0;
11738 emit_insn (gen_movmem12b (out, in, out, in));
11744 emit_insn (gen_movmem8b (out, in, out, in));
11750 rtx reg = gen_reg_rtx (SImode);
11751 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
11752 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
11759 rtx reg = gen_reg_rtx (HImode);
11760 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
11761 plus_constant (in, offset))));
11762 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
11770 rtx reg = gen_reg_rtx (QImode);
11771 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
11772 plus_constant (in, offset))));
11773 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
11779 thumb_cmp_operand (op, mode)
11781 enum machine_mode mode;
11783 return ((GET_CODE (op) == CONST_INT
11784 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
11785 || register_operand (op, mode));
11788 static const char *
11789 thumb_condition_code (x, invert)
11793 static const char * const conds[] =
11795 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
11796 "hi", "ls", "ge", "lt", "gt", "le"
11800 switch (GET_CODE (x))
11802 case EQ: val = 0; break;
11803 case NE: val = 1; break;
11804 case GEU: val = 2; break;
11805 case LTU: val = 3; break;
11806 case GTU: val = 8; break;
11807 case LEU: val = 9; break;
11808 case GE: val = 10; break;
11809 case LT: val = 11; break;
11810 case GT: val = 12; break;
11811 case LE: val = 13; break;
11816 return conds[val ^ invert];
11819 /* Handle storing a half-word to memory during reload. */
11822 thumb_reload_out_hi (operands)
11825 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
11828 /* Handle storing a half-word to memory during reload. */
11831 thumb_reload_in_hi (operands)
11832 rtx * operands ATTRIBUTE_UNUSED;
11837 /* Return the length of a function name prefix
11838 that starts with the character 'c'. */
11841 arm_get_strip_length (c)
11846 ARM_NAME_ENCODING_LENGTHS
11851 /* Return a pointer to a function's name with any
11852 and all prefix encodings stripped from it. */
11855 arm_strip_name_encoding (name)
11860 while ((skip = arm_get_strip_length (* name)))
11866 /* If there is a '*' anywhere in the name's prefix, then
11867 emit the stripped name verbatim, otherwise prepend an
11868 underscore if leading underscores are being used. */
11871 arm_asm_output_labelref (stream, name)
11878 while ((skip = arm_get_strip_length (* name)))
11880 verbatim |= (*name == '*');
11885 fputs (name, stream);
11887 asm_fprintf (stream, "%U%s", name);
11892 #ifdef AOF_ASSEMBLER
11893 /* Special functions only needed when producing AOF syntax assembler. */
11897 struct pic_chain * next;
11898 const char * symname;
11901 static struct pic_chain * aof_pic_chain = NULL;
11907 struct pic_chain ** chainp;
11910 if (aof_pic_label == NULL_RTX)
11912 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
11915 for (offset = 0, chainp = &aof_pic_chain; *chainp;
11916 offset += 4, chainp = &(*chainp)->next)
11917 if ((*chainp)->symname == XSTR (x, 0))
11918 return plus_constant (aof_pic_label, offset);
11920 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
11921 (*chainp)->next = NULL;
11922 (*chainp)->symname = XSTR (x, 0);
11923 return plus_constant (aof_pic_label, offset);
11927 aof_dump_pic_table (f)
11930 struct pic_chain * chain;
11932 if (aof_pic_chain == NULL)
11935 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
11936 PIC_OFFSET_TABLE_REGNUM,
11937 PIC_OFFSET_TABLE_REGNUM);
11938 fputs ("|x$adcons|\n", f);
11940 for (chain = aof_pic_chain; chain; chain = chain->next)
11942 fputs ("\tDCD\t", f);
11943 assemble_name (f, chain->symname);
11948 int arm_text_section_count = 1;
11951 aof_text_section ()
11953 static char buf[100];
11954 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
11955 arm_text_section_count++);
11957 strcat (buf, ", PIC, REENTRANT");
11961 static int arm_data_section_count = 1;
11964 aof_data_section ()
11966 static char buf[100];
11967 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
11971 /* The AOF assembler is religiously strict about declarations of
11972 imported and exported symbols, so that it is impossible to declare
11973 a function as imported near the beginning of the file, and then to
11974 export it later on. It is, however, possible to delay the decision
11975 until all the functions in the file have been compiled. To get
11976 around this, we maintain a list of the imports and exports, and
11977 delete from it any that are subsequently defined. At the end of
11978 compilation we spit the remainder of the list out before the END
11983 struct import * next;
11987 static struct import * imports_list = NULL;
11990 aof_add_import (name)
11993 struct import * new;
11995 for (new = imports_list; new; new = new->next)
11996 if (new->name == name)
11999 new = (struct import *) xmalloc (sizeof (struct import));
12000 new->next = imports_list;
12001 imports_list = new;
12006 aof_delete_import (name)
12009 struct import ** old;
12011 for (old = &imports_list; *old; old = & (*old)->next)
12013 if ((*old)->name == name)
12015 *old = (*old)->next;
12021 int arm_main_function = 0;
12024 aof_dump_imports (f)
12027 /* The AOF assembler needs this to cause the startup code to be extracted
12028 from the library. Brining in __main causes the whole thing to work
12030 if (arm_main_function)
12033 fputs ("\tIMPORT __main\n", f);
12034 fputs ("\tDCD __main\n", f);
12037 /* Now dump the remaining imports. */
12038 while (imports_list)
12040 fprintf (f, "\tIMPORT\t");
12041 assemble_name (f, imports_list->name);
12043 imports_list = imports_list->next;
12048 aof_globalize_label (stream, name)
12052 default_globalize_label (stream, name);
12053 if (! strcmp (name, "main"))
12054 arm_main_function = 1;
12056 #endif /* AOF_ASSEMBLER */
12058 #ifdef OBJECT_FORMAT_ELF
12059 /* Switch to an arbitrary section NAME with attributes as specified
12060 by FLAGS. ALIGN specifies any known alignment requirements for
12061 the section; 0 if the default should be used.
12063 Differs from the default elf version only in the prefix character
12064 used before the section type. */
12067 arm_elf_asm_named_section (name, flags)
12069 unsigned int flags;
12071 char flagchars[10], *f = flagchars;
12073 if (! named_section_first_declaration (name))
12075 fprintf (asm_out_file, "\t.section\t%s\n", name);
12079 if (!(flags & SECTION_DEBUG))
12081 if (flags & SECTION_WRITE)
12083 if (flags & SECTION_CODE)
12085 if (flags & SECTION_SMALL)
12087 if (flags & SECTION_MERGE)
12089 if (flags & SECTION_STRINGS)
12091 if (flags & SECTION_TLS)
12095 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
12097 if (!(flags & SECTION_NOTYPE))
12101 if (flags & SECTION_BSS)
12106 fprintf (asm_out_file, ",%%%s", type);
12108 if (flags & SECTION_ENTSIZE)
12109 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
12112 putc ('\n', asm_out_file);
12117 /* Symbols in the text segment can be accessed without indirecting via the
12118 constant pool; it may take an extra binary operation, but this is still
12119 faster than indirecting via memory. Don't do this when not optimizing,
12120 since we won't be calculating al of the offsets necessary to do this
12124 arm_encode_section_info (decl, first)
12128 /* This doesn't work with AOF syntax, since the string table may be in
12129 a different AREA. */
12130 #ifndef AOF_ASSEMBLER
12131 if (optimize > 0 && TREE_CONSTANT (decl)
12132 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
12134 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
12135 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
12136 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
12140 /* If we are referencing a function that is weak then encode a long call
12141 flag in the function name, otherwise if the function is static or
12142 or known to be defined in this file then encode a short call flag. */
12143 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
12145 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
12146 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
12147 else if (! TREE_PUBLIC (decl))
12148 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
12151 #endif /* !ARM_PE */
12154 arm_internal_label (stream, prefix, labelno)
12156 const char *prefix;
12157 unsigned long labelno;
12159 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
12160 && !strcmp (prefix, "L"))
12162 arm_ccfsm_state = 0;
12163 arm_target_insn = NULL;
12165 default_internal_label (stream, prefix, labelno);
12168 /* Output code to add DELTA to the first argument, and then jump
12169 to FUNCTION. Used for C++ multiple inheritance. */
12172 arm_output_mi_thunk (file, thunk, delta, vcall_offset, function)
12174 tree thunk ATTRIBUTE_UNUSED;
12175 HOST_WIDE_INT delta;
12176 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
12179 int mi_delta = delta;
12180 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
12182 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))
12185 mi_delta = - mi_delta;
12186 while (mi_delta != 0)
12188 if ((mi_delta & (3 << shift)) == 0)
12192 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
12193 mi_op, this_regno, this_regno,
12194 mi_delta & (0xff << shift));
12195 mi_delta &= ~(0xff << shift);
12199 fputs ("\tb\t", file);
12200 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
12201 if (NEED_PLT_RELOC)
12202 fputs ("(PLT)", file);
12203 fputc ('\n', file);