1 /* Output routines for GCC for ARM/RISCiX.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 #define MAX_INSNS_SKIPPED 5
46 /* Some function declarations. */
47 extern FILE *asm_out_file;
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char *output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char *fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char *shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
72 /* Define the information needed to generate branch insns. This is
73 stored from the compare operation. */
75 rtx arm_compare_op0, arm_compare_op1;
78 /* What type of cpu are we compiling for? */
79 enum processor_type arm_cpu;
81 /* What type of floating point are we tuning for? */
82 enum floating_point_type arm_fpu;
84 /* What type of floating point instructions are available? */
85 enum floating_point_type arm_fpu_arch;
87 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
88 enum prog_mode_type arm_prgmode;
90 /* Set by the -mfp=... option */
91 char *target_fp_name = NULL;
93 /* Used to parse -mstructure_size_boundary command line option. */
94 char * structure_size_string = NULL;
95 int arm_structure_size_boundary = 32; /* Used to be 8 */
97 /* Nonzero if this is an "M" variant of the processor. */
98 int arm_fast_multiply = 0;
100 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
103 /* Set to the features we should tune the code for (multiply speed etc). */
106 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
107 must report the mode of the memory reference from PRINT_OPERAND to
108 PRINT_OPERAND_ADDRESS. */
109 enum machine_mode output_memory_reference_mode;
111 /* Nonzero if the prologue must setup `fp'. */
112 int current_function_anonymous_args;
114 /* The register number to be used for the PIC offset register. */
115 int arm_pic_register = 9;
117 /* Location counter of .text segment. */
118 int arm_text_location = 0;
120 /* Set to one if we think that lr is only saved because of subroutine calls,
121 but all of these can be `put after' return insns */
122 int lr_save_eliminated;
124 /* Set to 1 when a return insn is output, this means that the epilogue
127 static int return_used_this_function;
129 static int arm_constant_limit = 3;
131 /* For an explanation of these variables, see final_prescan_insn below. */
133 enum arm_cond_code arm_current_cc;
135 int arm_target_label;
137 /* The condition codes of the ARM, and the inverse function. */
138 char *arm_condition_codes[] =
140 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
141 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
144 static enum arm_cond_code get_arm_condition_code ();
147 /* Initialization code */
149 struct arm_cpu_select arm_select[4] =
151 /* switch name, tune arch */
152 { (char *)0, "--with-cpu=", 1, 1 },
153 { (char *)0, "-mcpu=", 1, 1 },
154 { (char *)0, "-march=", 0, 1 },
155 { (char *)0, "-mtune=", 1, 0 },
158 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
159 #define FL_FAST_MULT 0x02 /* Fast multiply */
160 #define FL_MODE26 0x04 /* 26-bit mode support */
161 #define FL_MODE32 0x08 /* 32-bit mode support */
162 #define FL_ARCH4 0x10 /* Architecture rel 4 */
163 #define FL_THUMB 0x20 /* Thumb aware */
168 enum processor_type type;
172 /* Not all of these give usefully different compilation alternatives,
173 but there is no simple way of generalizing them. */
174 static struct processors all_procs[] =
176 {"arm2", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
177 {"arm250", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
178 {"arm3", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
179 {"arm6", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
180 {"arm600", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
181 {"arm610", PROCESSOR_ARM6, FL_MODE32 | FL_MODE26},
182 {"arm7", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
183 /* arm7m doesn't exist on its own, only in conjunction with D, (and I), but
184 those don't alter the code, so it is sometimes known as the arm7m */
185 {"arm7m", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
187 {"arm7dm", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
189 {"arm7dmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
191 {"arm700", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
192 {"arm710", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
193 {"arm7100", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
194 {"arm7500", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
195 /* Doesn't really have an external co-proc, but does have embedded fpu */
196 {"arm7500fe", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
197 {"arm7tdmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
198 | FL_ARCH4 | FL_THUMB)},
199 {"arm8", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
201 {"arm810", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
203 {"strongarm", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
205 {"strongarm110", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
207 {"armv2", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
208 {"armv2a", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
209 {"armv3", PROCESSOR_NONE, FL_CO_PROC | FL_MODE32 | FL_MODE26},
210 {"armv3m", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
212 {"armv4", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
213 | FL_MODE26 | FL_ARCH4)},
214 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
215 implementations that support it, so we will leave it out for now. */
216 {"armv4t", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
221 /* Fix up any incompatible options that the user has specified.
222 This has now turned into a maze. */
224 arm_override_options ()
226 int arm_thumb_aware = 0;
229 struct arm_cpu_select * ptr;
230 static struct cpu_default
237 { TARGET_CPU_arm2, "arm2" },
238 { TARGET_CPU_arm6, "arm6" },
239 { TARGET_CPU_arm610, "arm610" },
240 { TARGET_CPU_arm7dm, "arm7dm" },
241 { TARGET_CPU_arm7500fe, "arm7500fe" },
242 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
243 { TARGET_CPU_arm8, "arm8" },
244 { TARGET_CPU_arm810, "arm810" },
245 { TARGET_CPU_strongarm, "strongarm" },
248 struct cpu_default *def;
250 /* Set the default. */
251 for (def = &cpu_defaults[0]; def->name; ++def)
252 if (def->cpu == TARGET_CPU_DEFAULT)
257 arm_select[0].string = def->name;
259 for (i = 0; i < sizeof (arm_select) / sizeof (arm_select[0]); i++)
261 ptr = &arm_select[i];
262 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
264 struct processors *sel;
266 for (sel = all_procs; sel->name != NULL; sel++)
267 if (! strcmp (ptr->string, sel->name))
269 /* -march= is the only flag that can take an architecture
270 type, so if we match when the tune bit is set, the
271 option was invalid. */
274 if (sel->type == PROCESSOR_NONE)
275 continue; /* Its an architecture, not a cpu */
278 tune_flags = sel->flags;
287 if (sel->name == NULL)
288 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
292 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
293 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
295 if (TARGET_POKE_FUNCTION_NAME)
296 target_flags |= ARM_FLAG_APCS_FRAME;
299 warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
302 warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
304 if (TARGET_APCS_REENT && flag_pic)
305 fatal ("-fpic and -mapcs-reent are incompatible");
307 if (TARGET_APCS_REENT)
308 warning ("APCS reentrant code not supported.");
310 /* If stack checking is disabled, we can use r10 as the PIC register,
311 which keeps r9 available. */
312 if (flag_pic && ! TARGET_APCS_STACK)
313 arm_pic_register = 10;
315 /* Well, I'm about to have a go, but pic is NOT going to be compatible
316 with APCS reentrancy, since that requires too much support in the
317 assembler and linker, and the ARMASM assembler seems to lack some
318 required directives. */
320 warning ("Position independent code not supported");
322 if (TARGET_APCS_FLOAT)
323 warning ("Passing floating point arguments in fp regs not yet supported");
325 if (TARGET_APCS_STACK && ! TARGET_APCS)
327 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
328 target_flags |= ARM_FLAG_APCS_FRAME;
331 /* Default is to tune for an FPA */
334 /* Default value for floating point code... if no co-processor
335 bus, then schedule for emulated floating point. Otherwise,
336 assume the user has an FPA.
337 Note: this does not prevent use of floating point instructions,
338 -msoft-float does that. */
339 if ((tune_flags & FL_CO_PROC) == 0)
342 arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
343 arm_arch4 = (flags & FL_ARCH4) != 0;
344 arm_thumb_aware = (flags & FL_THUMB) != 0;
348 if (strcmp (target_fp_name, "2") == 0)
349 arm_fpu_arch = FP_SOFT2;
350 else if (strcmp (target_fp_name, "3") == 0)
351 arm_fpu_arch = FP_HARD;
353 fatal ("Invalid floating point emulation option: -mfpe=%s",
357 arm_fpu_arch = FP_DEFAULT;
359 if (TARGET_THUMB_INTERWORK && ! arm_thumb_aware)
361 warning ("This processor variant does not support Thumb interworking");
362 target_flags &= ~ARM_FLAG_THUMB;
365 if (TARGET_FPE && arm_fpu != FP_HARD)
368 /* For arm2/3 there is no need to do any scheduling if there is only
369 a floating point emulator, or we are doing software floating-point. */
370 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && arm_cpu == PROCESSOR_ARM2)
371 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
373 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
375 if (structure_size_string != NULL)
377 int size = strtol (structure_size_string, NULL, 0);
379 if (size == 8 || size == 32)
380 arm_structure_size_boundary = size;
382 warning ("Structure size boundary can only be set to 8 or 32");
387 /* Return 1 if it is possible to return using a single instruction */
394 if (!reload_completed ||current_function_pretend_args_size
395 || current_function_anonymous_args
396 || ((get_frame_size () + current_function_outgoing_args_size != 0)
397 && !(TARGET_APCS || frame_pointer_needed)))
400 /* Can't be done if interworking with Thumb, and any registers have been
402 if (TARGET_THUMB_INTERWORK)
403 for (regno = 0; regno < 16; regno++)
404 if (regs_ever_live[regno] && ! call_used_regs[regno])
407 /* Can't be done if any of the FPU regs are pushed, since this also
409 for (regno = 16; regno < 24; regno++)
410 if (regs_ever_live[regno] && ! call_used_regs[regno])
413 /* If a function is naked, don't use the "return" insn. */
414 if (arm_naked_function_p (current_function_decl))
420 /* Return TRUE if int I is a valid immediate ARM constant. */
426 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
428 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
429 be all zero, or all one. */
430 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
431 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
432 != ((~(unsigned HOST_WIDE_INT) 0)
433 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
436 /* Fast return for 0 and powers of 2 */
437 if ((i & (i - 1)) == 0)
442 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
445 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
446 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
447 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
452 /* Return true if I is a valid constant for the operation CODE. */
454 const_ok_for_op (i, code, mode)
457 enum machine_mode mode;
459 if (const_ok_for_arm (i))
465 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
467 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
473 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
480 /* Emit a sequence of insns to handle a large constant.
481 CODE is the code of the operation required, it can be any of SET, PLUS,
482 IOR, AND, XOR, MINUS;
483 MODE is the mode in which the operation is being performed;
484 VAL is the integer to operate on;
485 SOURCE is the other operand (a register, or a null-pointer for SET);
486 SUBTARGETS means it is safe to create scratch registers if that will
487 either produce a simpler sequence, or we will want to cse the values.
488 Return value is the number of insns emitted. */
491 arm_split_constant (code, mode, val, target, source, subtargets)
493 enum machine_mode mode;
499 if (subtargets || code == SET
500 || (GET_CODE (target) == REG && GET_CODE (source) == REG
501 && REGNO (target) != REGNO (source)))
503 if (arm_gen_constant (code, mode, val, target, source, 1, 0)
504 > arm_constant_limit + (code != SET))
508 /* Currently SET is the only monadic value for CODE, all
509 the rest are diadic. */
510 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (val)));
515 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
517 emit_insn (gen_rtx (SET, VOIDmode, temp, GEN_INT (val)));
518 /* For MINUS, the value is subtracted from, since we never
519 have subtraction of a constant. */
521 emit_insn (gen_rtx (SET, VOIDmode, target,
522 gen_rtx (code, mode, temp, source)));
524 emit_insn (gen_rtx (SET, VOIDmode, target,
525 gen_rtx (code, mode, source, temp)));
531 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
534 /* As above, but extra parameter GENERATE which, if clear, suppresses
537 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
539 enum machine_mode mode;
548 int can_negate_initial = 0;
551 int num_bits_set = 0;
552 int set_sign_bit_copies = 0;
553 int clear_sign_bit_copies = 0;
554 int clear_zero_bit_copies = 0;
555 int set_zero_bit_copies = 0;
557 unsigned HOST_WIDE_INT temp1, temp2;
558 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
560 /* find out which operations are safe for a given CODE. Also do a quick
561 check for degenerate cases; these can occur when DImode operations
573 can_negate_initial = 1;
577 if (remainder == 0xffffffff)
580 emit_insn (gen_rtx (SET, VOIDmode, target,
581 GEN_INT (ARM_SIGN_EXTEND (val))));
586 if (reload_completed && rtx_equal_p (target, source))
589 emit_insn (gen_rtx (SET, VOIDmode, target, source));
598 emit_insn (gen_rtx (SET, VOIDmode, target, const0_rtx));
601 if (remainder == 0xffffffff)
603 if (reload_completed && rtx_equal_p (target, source))
606 emit_insn (gen_rtx (SET, VOIDmode, target, source));
615 if (reload_completed && rtx_equal_p (target, source))
618 emit_insn (gen_rtx (SET, VOIDmode, target, source));
621 if (remainder == 0xffffffff)
624 emit_insn (gen_rtx (SET, VOIDmode, target,
625 gen_rtx (NOT, mode, source)));
629 /* We don't know how to handle this yet below. */
633 /* We treat MINUS as (val - source), since (source - val) is always
634 passed as (source + (-val)). */
638 emit_insn (gen_rtx (SET, VOIDmode, target,
639 gen_rtx (NEG, mode, source)));
642 if (const_ok_for_arm (val))
645 emit_insn (gen_rtx (SET, VOIDmode, target,
646 gen_rtx (MINUS, mode, GEN_INT (val), source)));
657 /* If we can do it in one insn get out quickly */
658 if (const_ok_for_arm (val)
659 || (can_negate_initial && const_ok_for_arm (-val))
660 || (can_invert && const_ok_for_arm (~val)))
663 emit_insn (gen_rtx (SET, VOIDmode, target,
664 (source ? gen_rtx (code, mode, source,
671 /* Calculate a few attributes that may be useful for specific
674 for (i = 31; i >= 0; i--)
676 if ((remainder & (1 << i)) == 0)
677 clear_sign_bit_copies++;
682 for (i = 31; i >= 0; i--)
684 if ((remainder & (1 << i)) != 0)
685 set_sign_bit_copies++;
690 for (i = 0; i <= 31; i++)
692 if ((remainder & (1 << i)) == 0)
693 clear_zero_bit_copies++;
698 for (i = 0; i <= 31; i++)
700 if ((remainder & (1 << i)) != 0)
701 set_zero_bit_copies++;
709 /* See if we can do this by sign_extending a constant that is known
710 to be negative. This is a good, way of doing it, since the shift
711 may well merge into a subsequent insn. */
712 if (set_sign_bit_copies > 1)
715 (temp1 = ARM_SIGN_EXTEND (remainder
716 << (set_sign_bit_copies - 1))))
720 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
721 emit_insn (gen_rtx (SET, VOIDmode, new_src,
723 emit_insn (gen_ashrsi3 (target, new_src,
724 GEN_INT (set_sign_bit_copies - 1)));
728 /* For an inverted constant, we will need to set the low bits,
729 these will be shifted out of harm's way. */
730 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
731 if (const_ok_for_arm (~temp1))
735 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
736 emit_insn (gen_rtx (SET, VOIDmode, new_src,
738 emit_insn (gen_ashrsi3 (target, new_src,
739 GEN_INT (set_sign_bit_copies - 1)));
745 /* See if we can generate this by setting the bottom (or the top)
746 16 bits, and then shifting these into the other half of the
747 word. We only look for the simplest cases, to do more would cost
748 too much. Be careful, however, not to generate this when the
749 alternative would take fewer insns. */
750 if (val & 0xffff0000)
752 temp1 = remainder & 0xffff0000;
753 temp2 = remainder & 0x0000ffff;
755 /* Overlaps outside this range are best done using other methods. */
756 for (i = 9; i < 24; i++)
758 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
759 && ! const_ok_for_arm (temp2))
761 rtx new_src = (subtargets
762 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
764 insns = arm_gen_constant (code, mode, temp2, new_src,
765 source, subtargets, generate);
768 emit_insn (gen_rtx (SET, VOIDmode, target,
770 gen_rtx (ASHIFT, mode, source,
777 /* Don't duplicate cases already considered. */
778 for (i = 17; i < 24; i++)
780 if (((temp1 | (temp1 >> i)) == remainder)
781 && ! const_ok_for_arm (temp1))
783 rtx new_src = (subtargets
784 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
786 insns = arm_gen_constant (code, mode, temp1, new_src,
787 source, subtargets, generate);
790 emit_insn (gen_rtx (SET, VOIDmode, target,
792 gen_rtx (LSHIFTRT, mode,
793 source, GEN_INT (i)),
803 /* If we have IOR or XOR, and the constant can be loaded in a
804 single instruction, and we can find a temporary to put it in,
805 then this can be done in two instructions instead of 3-4. */
807 /* TARGET can't be NULL if SUBTARGETS is 0 */
808 || (reload_completed && ! reg_mentioned_p (target, source)))
810 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
814 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
816 emit_insn (gen_rtx (SET, VOIDmode, sub, GEN_INT (val)));
817 emit_insn (gen_rtx (SET, VOIDmode, target,
818 gen_rtx (code, mode, source, sub)));
827 if (set_sign_bit_copies > 8
828 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
832 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
833 rtx shift = GEN_INT (set_sign_bit_copies);
835 emit_insn (gen_rtx (SET, VOIDmode, sub,
837 gen_rtx (ASHIFT, mode, source,
839 emit_insn (gen_rtx (SET, VOIDmode, target,
841 gen_rtx (LSHIFTRT, mode, sub,
847 if (set_zero_bit_copies > 8
848 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
852 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
853 rtx shift = GEN_INT (set_zero_bit_copies);
855 emit_insn (gen_rtx (SET, VOIDmode, sub,
857 gen_rtx (LSHIFTRT, mode, source,
859 emit_insn (gen_rtx (SET, VOIDmode, target,
861 gen_rtx (ASHIFT, mode, sub,
867 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
871 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
872 emit_insn (gen_rtx (SET, VOIDmode, sub,
873 gen_rtx (NOT, mode, source)));
876 sub = gen_reg_rtx (mode);
877 emit_insn (gen_rtx (SET, VOIDmode, sub,
878 gen_rtx (AND, mode, source,
880 emit_insn (gen_rtx (SET, VOIDmode, target,
881 gen_rtx (NOT, mode, sub)));
888 /* See if two shifts will do 2 or more insn's worth of work. */
889 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
891 HOST_WIDE_INT shift_mask = ((0xffffffff
892 << (32 - clear_sign_bit_copies))
895 if ((remainder | shift_mask) != 0xffffffff)
899 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
900 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
901 new_src, source, subtargets, 1);
906 rtx targ = subtargets ? NULL_RTX : target;
907 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
908 targ, source, subtargets, 0);
914 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
915 rtx shift = GEN_INT (clear_sign_bit_copies);
917 emit_insn (gen_ashlsi3 (new_src, source, shift));
918 emit_insn (gen_lshrsi3 (target, new_src, shift));
924 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
926 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
928 if ((remainder | shift_mask) != 0xffffffff)
932 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
934 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
935 new_src, source, subtargets, 1);
940 rtx targ = subtargets ? NULL_RTX : target;
942 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
943 targ, source, subtargets, 0);
949 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
950 rtx shift = GEN_INT (clear_zero_bit_copies);
952 emit_insn (gen_lshrsi3 (new_src, source, shift));
953 emit_insn (gen_ashlsi3 (target, new_src, shift));
965 for (i = 0; i < 32; i++)
966 if (remainder & (1 << i))
969 if (code == AND || (can_invert && num_bits_set > 16))
970 remainder = (~remainder) & 0xffffffff;
971 else if (code == PLUS && num_bits_set > 16)
972 remainder = (-remainder) & 0xffffffff;
979 /* Now try and find a way of doing the job in either two or three
981 We start by looking for the largest block of zeros that are aligned on
982 a 2-bit boundary, we then fill up the temps, wrapping around to the
983 top of the word when we drop off the bottom.
984 In the worst case this code should produce no more than four insns. */
987 int best_consecutive_zeros = 0;
989 for (i = 0; i < 32; i += 2)
991 int consecutive_zeros = 0;
993 if (! (remainder & (3 << i)))
995 while ((i < 32) && ! (remainder & (3 << i)))
997 consecutive_zeros += 2;
1000 if (consecutive_zeros > best_consecutive_zeros)
1002 best_consecutive_zeros = consecutive_zeros;
1003 best_start = i - consecutive_zeros;
1009 /* Now start emitting the insns, starting with the one with the highest
1010 bit set: we do this so that the smallest number will be emitted last;
1011 this is more likely to be combinable with addressing insns. */
1019 if (remainder & (3 << (i - 2)))
1024 temp1 = remainder & ((0x0ff << end)
1025 | ((i < end) ? (0xff >> (32 - end)) : 0));
1026 remainder &= ~temp1;
1033 emit_insn (gen_rtx (SET, VOIDmode,
1034 new_src = (subtargets
1035 ? gen_reg_rtx (mode)
1037 GEN_INT (can_invert ? ~temp1 : temp1)));
1038 else if (code == MINUS)
1039 emit_insn (gen_rtx (SET, VOIDmode,
1040 new_src = (subtargets
1041 ? gen_reg_rtx (mode)
1043 gen_rtx (code, mode, GEN_INT (temp1),
1046 emit_insn (gen_rtx (SET, VOIDmode,
1047 new_src = (remainder
1049 ? gen_reg_rtx (mode)
1052 gen_rtx (code, mode, source,
1053 GEN_INT (can_invert ? ~temp1
1065 else if (code == MINUS)
1072 } while (remainder);
1077 /* Canonicalize a comparison so that we are more likely to recognize it.
1078 This can be done for a few constant compares, where we can make the
1079 immediate value easier to load. */
1081 arm_canonicalize_comparison (code, op1)
1085 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1095 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1097 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1099 *op1 = GEN_INT (i+1);
1100 return code == GT ? GE : LT;
1106 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1107 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1109 *op1 = GEN_INT (i-1);
1110 return code == GE ? GT : LE;
1116 if (i != ~((unsigned HOST_WIDE_INT) 0)
1117 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1119 *op1 = GEN_INT (i + 1);
1120 return code == GTU ? GEU : LTU;
1127 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1129 *op1 = GEN_INT (i - 1);
1130 return code == GEU ? GTU : LEU;
1142 /* Handle aggregates that are not laid out in a BLKmode element.
1143 This is a sub-element of RETURN_IN_MEMORY. */
1145 arm_return_in_memory (type)
1148 if (TREE_CODE (type) == RECORD_TYPE)
1152 /* For a struct, we can return in a register if every element was a
1154 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1155 if (TREE_CODE (field) != FIELD_DECL
1156 || ! DECL_BIT_FIELD_TYPE (field))
1161 else if (TREE_CODE (type) == UNION_TYPE)
1165 /* Unions can be returned in registers if every element is
1166 integral, or can be returned in an integer register. */
1167 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1169 if (TREE_CODE (field) != FIELD_DECL
1170 || (AGGREGATE_TYPE_P (TREE_TYPE (field))
1171 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1172 || FLOAT_TYPE_P (TREE_TYPE (field)))
1177 /* XXX Not sure what should be done for other aggregates, so put them in
1183 legitimate_pic_operand_p (x)
1186 if (CONSTANT_P (x) && flag_pic
1187 && (GET_CODE (x) == SYMBOL_REF
1188 || (GET_CODE (x) == CONST
1189 && GET_CODE (XEXP (x, 0)) == PLUS
1190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1197 legitimize_pic_address (orig, mode, reg)
1199 enum machine_mode mode;
1202 if (GET_CODE (orig) == SYMBOL_REF)
1204 rtx pic_ref, address;
1210 if (reload_in_progress || reload_completed)
1213 reg = gen_reg_rtx (Pmode);
1218 #ifdef AOF_ASSEMBLER
1219 /* The AOF assembler can generate relocations for these directly, and
1220 understands that the PIC register has to be added into the offset.
1222 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1225 address = gen_reg_rtx (Pmode);
1229 emit_insn (gen_pic_load_addr (address, orig));
1231 pic_ref = gen_rtx (MEM, Pmode,
1232 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, address));
1233 RTX_UNCHANGING_P (pic_ref) = 1;
1234 insn = emit_move_insn (reg, pic_ref);
1236 current_function_uses_pic_offset_table = 1;
1237 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1239 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1243 else if (GET_CODE (orig) == CONST)
1247 if (GET_CODE (XEXP (orig, 0)) == PLUS
1248 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1253 if (reload_in_progress || reload_completed)
1256 reg = gen_reg_rtx (Pmode);
1259 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1261 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1262 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1263 base == reg ? 0 : reg);
1268 if (GET_CODE (offset) == CONST_INT)
1270 /* The base register doesn't really matter, we only want to
1271 test the index for the appropriate mode. */
1272 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1274 if (! reload_in_progress && ! reload_completed)
1275 offset = force_reg (Pmode, offset);
1280 if (GET_CODE (offset) == CONST_INT)
1281 return plus_constant_for_output (base, INTVAL (offset));
1284 if (GET_MODE_SIZE (mode) > 4
1285 && (GET_MODE_CLASS (mode) == MODE_INT
1286 || TARGET_SOFT_FLOAT))
1288 emit_insn (gen_addsi3 (reg, base, offset));
1292 return gen_rtx (PLUS, Pmode, base, offset);
1294 else if (GET_CODE (orig) == LABEL_REF)
1295 current_function_uses_pic_offset_table = 1;
1314 #ifndef AOF_ASSEMBLER
1315 rtx l1, pic_tmp, pic_tmp2, seq;
1316 rtx global_offset_table;
1318 if (current_function_uses_pic_offset_table == 0)
1325 l1 = gen_label_rtx ();
1327 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1328 /* The PC contains 'dot'+8, but the label L1 is on the next
1329 instruction, so the offset is only 'dot'+4. */
1330 pic_tmp = gen_rtx (CONST, VOIDmode,
1331 gen_rtx (PLUS, Pmode,
1332 gen_rtx (LABEL_REF, VOIDmode, l1),
1334 pic_tmp2 = gen_rtx (CONST, VOIDmode,
1335 gen_rtx (PLUS, Pmode,
1336 global_offset_table,
1339 pic_rtx = gen_rtx (CONST, Pmode,
1340 gen_rtx (MINUS, Pmode, pic_tmp2, pic_tmp));
1342 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1343 emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx));
1346 seq = gen_sequence ();
1348 emit_insn_after (seq, get_insns ());
1350 /* Need to emit this whether or not we obey regdecls,
1351 since setjmp/longjmp can cause life info to screw up. */
1352 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1353 #endif /* AOF_ASSEMBLER */
1356 #define REG_OR_SUBREG_REG(X) \
1357 (GET_CODE (X) == REG \
1358 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1360 #define REG_OR_SUBREG_RTX(X) \
1361 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1363 #define ARM_FRAME_RTX(X) \
1364 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1365 || (X) == arg_pointer_rtx)
1368 arm_rtx_costs (x, code, outer_code)
1370 enum rtx_code code, outer_code;
1372 enum machine_mode mode = GET_MODE (x);
1373 enum rtx_code subcode;
1379 /* Memory costs quite a lot for the first word, but subsequent words
1380 load at the equivalent of a single insn each. */
1381 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1382 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1389 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1396 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1398 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1399 + ((GET_CODE (XEXP (x, 0)) == REG
1400 || (GET_CODE (XEXP (x, 0)) == SUBREG
1401 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1403 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1404 || (GET_CODE (XEXP (x, 0)) == SUBREG
1405 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1407 + ((GET_CODE (XEXP (x, 1)) == REG
1408 || (GET_CODE (XEXP (x, 1)) == SUBREG
1409 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1410 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1415 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1416 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1417 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1418 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1421 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1422 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1423 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1424 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1426 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1427 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1428 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1431 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1432 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1433 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1434 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1435 || subcode == ASHIFTRT || subcode == LSHIFTRT
1436 || subcode == ROTATE || subcode == ROTATERT
1438 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1439 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1440 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1441 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1442 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1443 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1444 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1449 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1450 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1451 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1452 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1453 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1457 case AND: case XOR: case IOR:
1460 /* Normally the frame registers will be spilt into reg+const during
1461 reload, so it is a bad idea to combine them with other instructions,
1462 since then they might not be moved outside of loops. As a compromise
1463 we allow integration with ops that have a constant as their second
1465 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1466 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1467 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1468 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1469 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1473 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1474 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1475 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1476 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1479 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1480 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1481 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1482 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1483 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1486 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1487 return (1 + extra_cost
1488 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1489 || subcode == LSHIFTRT || subcode == ASHIFTRT
1490 || subcode == ROTATE || subcode == ROTATERT
1492 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1493 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1494 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1495 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1496 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1497 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1503 /* There is no point basing this on the tuning, since it is always the
1504 fast variant if it exists at all */
1505 if (arm_fast_multiply && mode == DImode
1506 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1507 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1508 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1511 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1515 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1517 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1518 & (unsigned HOST_WIDE_INT) 0xffffffff);
1519 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1521 /* Tune as appropriate */
1522 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1524 for (j = 0; i && j < 32; j += booth_unit_size)
1526 i >>= booth_unit_size;
1533 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1534 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1535 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1538 if (arm_fast_multiply && mode == SImode
1539 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1540 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1541 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1542 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1543 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1544 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1549 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1550 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1554 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1556 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1559 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1567 return 4 + (mode == DImode ? 4 : 0);
1570 if (GET_MODE (XEXP (x, 0)) == QImode)
1571 return (4 + (mode == DImode ? 4 : 0)
1572 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1575 switch (GET_MODE (XEXP (x, 0)))
1578 return (1 + (mode == DImode ? 4 : 0)
1579 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1582 return (4 + (mode == DImode ? 4 : 0)
1583 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1586 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1599 arm_adjust_cost (insn, link, dep, cost)
1607 if ((i_pat = single_set (insn)) != NULL
1608 && GET_CODE (SET_SRC (i_pat)) == MEM
1609 && (d_pat = single_set (dep)) != NULL
1610 && GET_CODE (SET_DEST (d_pat)) == MEM)
1612 /* This is a load after a store, there is no conflict if the load reads
1613 from a cached area. Assume that loads from the stack, and from the
1614 constant pool are cached, and that others will miss. This is a
1617 /* debug_rtx (insn);
1620 fprintf (stderr, "costs %d\n", cost); */
1622 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1623 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1624 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1625 || reg_mentioned_p (hard_frame_pointer_rtx,
1626 XEXP (SET_SRC (i_pat), 0)))
1628 /* fprintf (stderr, "***** Now 1\n"); */
1636 /* This code has been fixed for cross compilation. */
1638 static int fpa_consts_inited = 0;
1640 char *strings_fpa[8] = {
1642 "4", "5", "0.5", "10"
1645 static REAL_VALUE_TYPE values_fpa[8];
1653 for (i = 0; i < 8; i++)
1655 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1659 fpa_consts_inited = 1;
1662 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1665 const_double_rtx_ok_for_fpu (x)
1671 if (!fpa_consts_inited)
1674 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1675 if (REAL_VALUE_MINUS_ZERO (r))
1678 for (i = 0; i < 8; i++)
1679 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1685 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1688 neg_const_double_rtx_ok_for_fpu (x)
1694 if (!fpa_consts_inited)
1697 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1698 r = REAL_VALUE_NEGATE (r);
1699 if (REAL_VALUE_MINUS_ZERO (r))
1702 for (i = 0; i < 8; i++)
1703 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1709 /* Predicates for `match_operand' and `match_operator'. */
1711 /* s_register_operand is the same as register_operand, but it doesn't accept
1714 This function exists because at the time it was put in it led to better
1715 code. SUBREG(MEM) always needs a reload in the places where
1716 s_register_operand is used, and this seemed to lead to excessive
1720 s_register_operand (op, mode)
1722 enum machine_mode mode;
1724 if (GET_MODE (op) != mode && mode != VOIDmode)
1727 if (GET_CODE (op) == SUBREG)
1728 op = SUBREG_REG (op);
1730 /* We don't consider registers whose class is NO_REGS
1731 to be a register operand. */
1732 return (GET_CODE (op) == REG
1733 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1734 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1737 /* Only accept reg, subreg(reg), const_int. */
1740 reg_or_int_operand (op, mode)
1742 enum machine_mode mode;
1744 if (GET_CODE (op) == CONST_INT)
1747 if (GET_MODE (op) != mode && mode != VOIDmode)
1750 if (GET_CODE (op) == SUBREG)
1751 op = SUBREG_REG (op);
1753 /* We don't consider registers whose class is NO_REGS
1754 to be a register operand. */
1755 return (GET_CODE (op) == REG
1756 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1757 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1760 /* Return 1 if OP is an item in memory, given that we are in reload. */
1763 reload_memory_operand (op, mode)
1765 enum machine_mode mode;
1767 int regno = true_regnum (op);
1769 return (! CONSTANT_P (op)
1771 || (GET_CODE (op) == REG
1772 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1775 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
1776 memory access (architecture V4) */
1778 bad_signed_byte_operand (op, mode)
1780 enum machine_mode mode;
1782 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
1787 /* A sum of anything more complex than reg + reg or reg + const is bad */
1788 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
1789 && (! s_register_operand (XEXP (op, 0), VOIDmode)
1790 || (! s_register_operand (XEXP (op, 1), VOIDmode)
1791 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
1794 /* Big constants are also bad */
1795 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
1796 && (INTVAL (XEXP (op, 1)) > 0xff
1797 || -INTVAL (XEXP (op, 1)) > 0xff))
1800 /* Everything else is good, or can will automatically be made so. */
1804 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1807 arm_rhs_operand (op, mode)
1809 enum machine_mode mode;
1811 return (s_register_operand (op, mode)
1812 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
1815 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1819 arm_rhsm_operand (op, mode)
1821 enum machine_mode mode;
1823 return (s_register_operand (op, mode)
1824 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
1825 || memory_operand (op, mode));
1828 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1829 constant that is valid when negated. */
1832 arm_add_operand (op, mode)
1834 enum machine_mode mode;
1836 return (s_register_operand (op, mode)
1837 || (GET_CODE (op) == CONST_INT
1838 && (const_ok_for_arm (INTVAL (op))
1839 || const_ok_for_arm (-INTVAL (op)))));
1843 arm_not_operand (op, mode)
1845 enum machine_mode mode;
1847 return (s_register_operand (op, mode)
1848 || (GET_CODE (op) == CONST_INT
1849 && (const_ok_for_arm (INTVAL (op))
1850 || const_ok_for_arm (~INTVAL (op)))));
1853 /* Return TRUE if the operand is a memory reference which contains an
1854 offsettable address. */
1856 offsettable_memory_operand (op, mode)
1858 enum machine_mode mode;
1860 if (mode == VOIDmode)
1861 mode = GET_MODE (op);
1863 return (mode == GET_MODE (op)
1864 && GET_CODE (op) == MEM
1865 && offsettable_address_p (reload_completed | reload_in_progress,
1866 mode, XEXP (op, 0)));
1869 /* Return TRUE if the operand is a memory reference which is, or can be
1870 made word aligned by adjusting the offset. */
1872 alignable_memory_operand (op, mode)
1874 enum machine_mode mode;
1878 if (mode == VOIDmode)
1879 mode = GET_MODE (op);
1881 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
1886 return ((GET_CODE (reg = op) == REG
1887 || (GET_CODE (op) == SUBREG
1888 && GET_CODE (reg = SUBREG_REG (op)) == REG)
1889 || (GET_CODE (op) == PLUS
1890 && GET_CODE (XEXP (op, 1)) == CONST_INT
1891 && (GET_CODE (reg = XEXP (op, 0)) == REG
1892 || (GET_CODE (XEXP (op, 0)) == SUBREG
1893 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
1894 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
1897 /* Similar to s_register_operand, but does not allow hard integer
1900 f_register_operand (op, mode)
1902 enum machine_mode mode;
1904 if (GET_MODE (op) != mode && mode != VOIDmode)
1907 if (GET_CODE (op) == SUBREG)
1908 op = SUBREG_REG (op);
1910 /* We don't consider registers whose class is NO_REGS
1911 to be a register operand. */
1912 return (GET_CODE (op) == REG
1913 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1914 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
1917 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
1920 fpu_rhs_operand (op, mode)
1922 enum machine_mode mode;
1924 if (s_register_operand (op, mode))
1926 else if (GET_CODE (op) == CONST_DOUBLE)
1927 return (const_double_rtx_ok_for_fpu (op));
1933 fpu_add_operand (op, mode)
1935 enum machine_mode mode;
1937 if (s_register_operand (op, mode))
1939 else if (GET_CODE (op) == CONST_DOUBLE)
1940 return (const_double_rtx_ok_for_fpu (op)
1941 || neg_const_double_rtx_ok_for_fpu (op));
1946 /* Return nonzero if OP is a constant power of two. */
1949 power_of_two_operand (op, mode)
1951 enum machine_mode mode;
1953 if (GET_CODE (op) == CONST_INT)
1955 HOST_WIDE_INT value = INTVAL(op);
1956 return value != 0 && (value & (value - 1)) == 0;
1961 /* Return TRUE for a valid operand of a DImode operation.
1962 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1963 Note that this disallows MEM(REG+REG), but allows
1964 MEM(PRE/POST_INC/DEC(REG)). */
1967 di_operand (op, mode)
1969 enum machine_mode mode;
1971 if (s_register_operand (op, mode))
1974 switch (GET_CODE (op))
1981 return memory_address_p (DImode, XEXP (op, 0));
1988 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
1989 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1990 Note that this disallows MEM(REG+REG), but allows
1991 MEM(PRE/POST_INC/DEC(REG)). */
1994 soft_df_operand (op, mode)
1996 enum machine_mode mode;
1998 if (s_register_operand (op, mode))
2001 switch (GET_CODE (op))
2007 return memory_address_p (DFmode, XEXP (op, 0));
2014 /* Return TRUE for valid index operands. */
2017 index_operand (op, mode)
2019 enum machine_mode mode;
2021 return (s_register_operand(op, mode)
2022 || (immediate_operand (op, mode)
2023 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2026 /* Return TRUE for valid shifts by a constant. This also accepts any
2027 power of two on the (somewhat overly relaxed) assumption that the
2028 shift operator in this case was a mult. */
2031 const_shift_operand (op, mode)
2033 enum machine_mode mode;
2035 return (power_of_two_operand (op, mode)
2036 || (immediate_operand (op, mode)
2037 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2040 /* Return TRUE for arithmetic operators which can be combined with a multiply
2044 shiftable_operator (x, mode)
2046 enum machine_mode mode;
2048 if (GET_MODE (x) != mode)
2052 enum rtx_code code = GET_CODE (x);
2054 return (code == PLUS || code == MINUS
2055 || code == IOR || code == XOR || code == AND);
2059 /* Return TRUE for shift operators. */
2062 shift_operator (x, mode)
2064 enum machine_mode mode;
2066 if (GET_MODE (x) != mode)
2070 enum rtx_code code = GET_CODE (x);
2073 return power_of_two_operand (XEXP (x, 1));
2075 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2076 || code == ROTATERT);
2080 int equality_operator (x, mode)
2082 enum machine_mode mode;
2084 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2087 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2090 minmax_operator (x, mode)
2092 enum machine_mode mode;
2094 enum rtx_code code = GET_CODE (x);
2096 if (GET_MODE (x) != mode)
2099 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2102 /* return TRUE if x is EQ or NE */
2104 /* Return TRUE if this is the condition code register, if we aren't given
2105 a mode, accept any class CCmode register */
2108 cc_register (x, mode)
2110 enum machine_mode mode;
2112 if (mode == VOIDmode)
2114 mode = GET_MODE (x);
2115 if (GET_MODE_CLASS (mode) != MODE_CC)
2119 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2125 /* Return TRUE if this is the condition code register, if we aren't given
2126 a mode, accept any class CCmode register which indicates a dominance
2130 dominant_cc_register (x, mode)
2132 enum machine_mode mode;
2134 if (mode == VOIDmode)
2136 mode = GET_MODE (x);
2137 if (GET_MODE_CLASS (mode) != MODE_CC)
2141 if (mode != CC_DNEmode && mode != CC_DEQmode
2142 && mode != CC_DLEmode && mode != CC_DLTmode
2143 && mode != CC_DGEmode && mode != CC_DGTmode
2144 && mode != CC_DLEUmode && mode != CC_DLTUmode
2145 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2148 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2154 /* Return TRUE if X references a SYMBOL_REF. */
2156 symbol_mentioned_p (x)
2162 if (GET_CODE (x) == SYMBOL_REF)
2165 fmt = GET_RTX_FORMAT (GET_CODE (x));
2166 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2172 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2173 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2176 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2183 /* Return TRUE if X references a LABEL_REF. */
2185 label_mentioned_p (x)
2191 if (GET_CODE (x) == LABEL_REF)
2194 fmt = GET_RTX_FORMAT (GET_CODE (x));
2195 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2201 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2202 if (label_mentioned_p (XVECEXP (x, i, j)))
2205 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2216 enum rtx_code code = GET_CODE (x);
2220 else if (code == SMIN)
2222 else if (code == UMIN)
2224 else if (code == UMAX)
2230 /* Return 1 if memory locations are adjacent */
2233 adjacent_mem_locations (a, b)
2236 int val0 = 0, val1 = 0;
2239 if ((GET_CODE (XEXP (a, 0)) == REG
2240 || (GET_CODE (XEXP (a, 0)) == PLUS
2241 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2242 && (GET_CODE (XEXP (b, 0)) == REG
2243 || (GET_CODE (XEXP (b, 0)) == PLUS
2244 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2246 if (GET_CODE (XEXP (a, 0)) == PLUS)
2248 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2249 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2252 reg0 = REGNO (XEXP (a, 0));
2253 if (GET_CODE (XEXP (b, 0)) == PLUS)
2255 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2256 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2259 reg1 = REGNO (XEXP (b, 0));
2260 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2265 /* Return 1 if OP is a load multiple operation. It is known to be
2266 parallel and the first section will be tested. */
2269 load_multiple_operation (op, mode)
2271 enum machine_mode mode;
2273 HOST_WIDE_INT count = XVECLEN (op, 0);
2276 HOST_WIDE_INT i = 1, base = 0;
2280 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2283 /* Check to see if this might be a write-back */
2284 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2289 /* Now check it more carefully */
2290 if (GET_CODE (SET_DEST (elt)) != REG
2291 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2292 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2293 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2294 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2295 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2296 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2297 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2298 != REGNO (SET_DEST (elt)))
2304 /* Perform a quick check so we don't blow up below. */
2306 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2307 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2308 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2311 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2312 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2314 for (; i < count; i++)
2316 elt = XVECEXP (op, 0, i);
2318 if (GET_CODE (elt) != SET
2319 || GET_CODE (SET_DEST (elt)) != REG
2320 || GET_MODE (SET_DEST (elt)) != SImode
2321 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2322 || GET_CODE (SET_SRC (elt)) != MEM
2323 || GET_MODE (SET_SRC (elt)) != SImode
2324 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2325 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2326 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2327 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2334 /* Return 1 if OP is a store multiple operation. It is known to be
2335 parallel and the first section will be tested. */
2338 store_multiple_operation (op, mode)
2340 enum machine_mode mode;
2342 HOST_WIDE_INT count = XVECLEN (op, 0);
2345 HOST_WIDE_INT i = 1, base = 0;
2349 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2352 /* Check to see if this might be a write-back */
2353 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2358 /* Now check it more carefully */
2359 if (GET_CODE (SET_DEST (elt)) != REG
2360 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2361 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2362 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2363 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2364 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2365 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2366 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2367 != REGNO (SET_DEST (elt)))
2373 /* Perform a quick check so we don't blow up below. */
2375 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2376 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2377 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2380 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2381 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2383 for (; i < count; i++)
2385 elt = XVECEXP (op, 0, i);
2387 if (GET_CODE (elt) != SET
2388 || GET_CODE (SET_SRC (elt)) != REG
2389 || GET_MODE (SET_SRC (elt)) != SImode
2390 || REGNO (SET_SRC (elt)) != src_regno + i - base
2391 || GET_CODE (SET_DEST (elt)) != MEM
2392 || GET_MODE (SET_DEST (elt)) != SImode
2393 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2394 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2395 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2396 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2404 load_multiple_sequence (operands, nops, regs, base, load_offset)
2409 HOST_WIDE_INT *load_offset;
2411 int unsorted_regs[4];
2412 HOST_WIDE_INT unsorted_offsets[4];
2417 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2418 extended if required. */
2419 if (nops < 2 || nops > 4)
2422 /* Loop over the operands and check that the memory references are
2423 suitable (ie immediate offsets from the same base register). At
2424 the same time, extract the target register, and the memory
2426 for (i = 0; i < nops; i++)
2431 /* Convert a subreg of a mem into the mem itself. */
2432 if (GET_CODE (operands[nops + i]) == SUBREG)
2433 operands[nops + i] = alter_subreg(operands[nops + i]);
2435 if (GET_CODE (operands[nops + i]) != MEM)
2438 /* Don't reorder volatile memory references; it doesn't seem worth
2439 looking for the case where the order is ok anyway. */
2440 if (MEM_VOLATILE_P (operands[nops + i]))
2443 offset = const0_rtx;
2445 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2446 || (GET_CODE (reg) == SUBREG
2447 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2448 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2449 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2451 || (GET_CODE (reg) == SUBREG
2452 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2453 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2458 base_reg = REGNO(reg);
2459 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2460 ? REGNO (operands[i])
2461 : REGNO (SUBREG_REG (operands[i])));
2466 if (base_reg != REGNO (reg))
2467 /* Not addressed from the same base register. */
2470 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2471 ? REGNO (operands[i])
2472 : REGNO (SUBREG_REG (operands[i])));
2473 if (unsorted_regs[i] < unsorted_regs[order[0]])
2477 /* If it isn't an integer register, or if it overwrites the
2478 base register but isn't the last insn in the list, then
2479 we can't do this. */
2480 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2481 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2484 unsorted_offsets[i] = INTVAL (offset);
2487 /* Not a suitable memory address. */
2491 /* All the useful information has now been extracted from the
2492 operands into unsorted_regs and unsorted_offsets; additionally,
2493 order[0] has been set to the lowest numbered register in the
2494 list. Sort the registers into order, and check that the memory
2495 offsets are ascending and adjacent. */
2497 for (i = 1; i < nops; i++)
2501 order[i] = order[i - 1];
2502 for (j = 0; j < nops; j++)
2503 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2504 && (order[i] == order[i - 1]
2505 || unsorted_regs[j] < unsorted_regs[order[i]]))
2508 /* Have we found a suitable register? if not, one must be used more
2510 if (order[i] == order[i - 1])
2513 /* Is the memory address adjacent and ascending? */
2514 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2522 for (i = 0; i < nops; i++)
2523 regs[i] = unsorted_regs[order[i]];
2525 *load_offset = unsorted_offsets[order[0]];
2528 if (unsorted_offsets[order[0]] == 0)
2529 return 1; /* ldmia */
2531 if (unsorted_offsets[order[0]] == 4)
2532 return 2; /* ldmib */
2534 if (unsorted_offsets[order[nops - 1]] == 0)
2535 return 3; /* ldmda */
2537 if (unsorted_offsets[order[nops - 1]] == -4)
2538 return 4; /* ldmdb */
2540 /* Can't do it without setting up the offset, only do this if it takes
2541 no more than one insn. */
2542 return (const_ok_for_arm (unsorted_offsets[order[0]])
2543 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2547 emit_ldm_seq (operands, nops)
2553 HOST_WIDE_INT offset;
2557 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2560 strcpy (buf, "ldm%?ia\t");
2564 strcpy (buf, "ldm%?ib\t");
2568 strcpy (buf, "ldm%?da\t");
2572 strcpy (buf, "ldm%?db\t");
2577 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2578 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2581 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2582 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2584 output_asm_insn (buf, operands);
2586 strcpy (buf, "ldm%?ia\t");
2593 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2594 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2596 for (i = 1; i < nops; i++)
2597 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2598 reg_names[regs[i]]);
2600 strcat (buf, "}\t%@ phole ldm");
2602 output_asm_insn (buf, operands);
2607 store_multiple_sequence (operands, nops, regs, base, load_offset)
2612 HOST_WIDE_INT *load_offset;
2614 int unsorted_regs[4];
2615 HOST_WIDE_INT unsorted_offsets[4];
2620 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2621 extended if required. */
2622 if (nops < 2 || nops > 4)
2625 /* Loop over the operands and check that the memory references are
2626 suitable (ie immediate offsets from the same base register). At
2627 the same time, extract the target register, and the memory
2629 for (i = 0; i < nops; i++)
2634 /* Convert a subreg of a mem into the mem itself. */
2635 if (GET_CODE (operands[nops + i]) == SUBREG)
2636 operands[nops + i] = alter_subreg(operands[nops + i]);
2638 if (GET_CODE (operands[nops + i]) != MEM)
2641 /* Don't reorder volatile memory references; it doesn't seem worth
2642 looking for the case where the order is ok anyway. */
2643 if (MEM_VOLATILE_P (operands[nops + i]))
2646 offset = const0_rtx;
2648 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2649 || (GET_CODE (reg) == SUBREG
2650 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2651 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2652 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2654 || (GET_CODE (reg) == SUBREG
2655 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2656 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2661 base_reg = REGNO(reg);
2662 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2663 ? REGNO (operands[i])
2664 : REGNO (SUBREG_REG (operands[i])));
2669 if (base_reg != REGNO (reg))
2670 /* Not addressed from the same base register. */
2673 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2674 ? REGNO (operands[i])
2675 : REGNO (SUBREG_REG (operands[i])));
2676 if (unsorted_regs[i] < unsorted_regs[order[0]])
2680 /* If it isn't an integer register, then we can't do this. */
2681 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2684 unsorted_offsets[i] = INTVAL (offset);
2687 /* Not a suitable memory address. */
2691 /* All the useful information has now been extracted from the
2692 operands into unsorted_regs and unsorted_offsets; additionally,
2693 order[0] has been set to the lowest numbered register in the
2694 list. Sort the registers into order, and check that the memory
2695 offsets are ascending and adjacent. */
2697 for (i = 1; i < nops; i++)
2701 order[i] = order[i - 1];
2702 for (j = 0; j < nops; j++)
2703 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2704 && (order[i] == order[i - 1]
2705 || unsorted_regs[j] < unsorted_regs[order[i]]))
2708 /* Have we found a suitable register? if not, one must be used more
2710 if (order[i] == order[i - 1])
2713 /* Is the memory address adjacent and ascending? */
2714 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2722 for (i = 0; i < nops; i++)
2723 regs[i] = unsorted_regs[order[i]];
2725 *load_offset = unsorted_offsets[order[0]];
2728 if (unsorted_offsets[order[0]] == 0)
2729 return 1; /* stmia */
2731 if (unsorted_offsets[order[0]] == 4)
2732 return 2; /* stmib */
2734 if (unsorted_offsets[order[nops - 1]] == 0)
2735 return 3; /* stmda */
2737 if (unsorted_offsets[order[nops - 1]] == -4)
2738 return 4; /* stmdb */
2744 emit_stm_seq (operands, nops)
2750 HOST_WIDE_INT offset;
2754 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2757 strcpy (buf, "stm%?ia\t");
2761 strcpy (buf, "stm%?ib\t");
2765 strcpy (buf, "stm%?da\t");
2769 strcpy (buf, "stm%?db\t");
2776 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2777 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2779 for (i = 1; i < nops; i++)
2780 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2781 reg_names[regs[i]]);
2783 strcat (buf, "}\t%@ phole stm");
2785 output_asm_insn (buf, operands);
2790 multi_register_push (op, mode)
2792 enum machine_mode mode;
2794 if (GET_CODE (op) != PARALLEL
2795 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
2796 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
2797 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
2804 /* Routines for use with attributes */
2806 /* Return nonzero if ATTR is a valid attribute for DECL.
2807 ATTRIBUTES are any existing attributes and ARGS are the arguments
2810 Supported attributes:
2812 naked: don't output any prologue or epilogue code, the user is assumed
2813 to do the right thing. */
2816 arm_valid_machine_decl_attribute (decl, attributes, attr, args)
2822 if (args != NULL_TREE)
2825 if (is_attribute_p ("naked", attr))
2826 return TREE_CODE (decl) == FUNCTION_DECL;
2830 /* Return non-zero if FUNC is a naked function. */
2833 arm_naked_function_p (func)
2838 if (TREE_CODE (func) != FUNCTION_DECL)
2841 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
2842 return a != NULL_TREE;
2845 /* Routines for use in generating RTL */
2848 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
2860 int sign = up ? 1 : -1;
2863 result = gen_rtx (PARALLEL, VOIDmode,
2864 rtvec_alloc (count + (write_back ? 2 : 0)));
2867 XVECEXP (result, 0, 0)
2868 = gen_rtx (SET, GET_MODE (from), from,
2869 plus_constant (from, count * 4 * sign));
2874 for (j = 0; i < count; i++, j++)
2876 mem = gen_rtx (MEM, SImode, plus_constant (from, j * 4 * sign));
2877 RTX_UNCHANGING_P (mem) = unchanging_p;
2878 MEM_IN_STRUCT_P (mem) = in_struct_p;
2880 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode,
2881 gen_rtx (REG, SImode, base_regno + j),
2886 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from);
2892 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
2904 int sign = up ? 1 : -1;
2907 result = gen_rtx (PARALLEL, VOIDmode,
2908 rtvec_alloc (count + (write_back ? 2 : 0)));
2911 XVECEXP (result, 0, 0)
2912 = gen_rtx (SET, GET_MODE (to), to,
2913 plus_constant (to, count * 4 * sign));
2918 for (j = 0; i < count; i++, j++)
2920 mem = gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign));
2921 RTX_UNCHANGING_P (mem) = unchanging_p;
2922 MEM_IN_STRUCT_P (mem) = in_struct_p;
2924 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, mem,
2925 gen_rtx (REG, SImode, base_regno + j));
2929 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to);
2935 arm_gen_movstrqi (operands)
2938 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
2941 rtx st_src, st_dst, fin_src, fin_dst;
2942 rtx part_bytes_reg = NULL;
2944 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
2946 if (GET_CODE (operands[2]) != CONST_INT
2947 || GET_CODE (operands[3]) != CONST_INT
2948 || INTVAL (operands[2]) > 64
2949 || INTVAL (operands[3]) & 3)
2952 st_dst = XEXP (operands[0], 0);
2953 st_src = XEXP (operands[1], 0);
2955 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
2956 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
2957 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
2958 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
2960 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
2961 fin_src = src = copy_to_mode_reg (SImode, st_src);
2963 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
2964 out_words_to_go = INTVAL (operands[2]) / 4;
2965 last_bytes = INTVAL (operands[2]) & 3;
2967 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
2968 part_bytes_reg = gen_rtx (REG, SImode, (in_words_to_go - 1) & 3);
2970 for (i = 0; in_words_to_go >= 2; i+=4)
2972 if (in_words_to_go > 4)
2973 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
2974 src_unchanging_p, src_in_struct_p));
2976 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
2977 FALSE, src_unchanging_p,
2980 if (out_words_to_go)
2982 if (out_words_to_go > 4)
2983 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
2986 else if (out_words_to_go != 1)
2987 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
2995 mem = gen_rtx (MEM, SImode, dst);
2996 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
2997 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
2998 emit_move_insn (mem, gen_rtx (REG, SImode, 0));
2999 if (last_bytes != 0)
3000 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3004 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3005 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3008 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3009 if (out_words_to_go)
3013 mem = gen_rtx (MEM, SImode, src);
3014 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3015 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3016 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3017 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3019 mem = gen_rtx (MEM, SImode, dst);
3020 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3021 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3022 emit_move_insn (mem, sreg);
3023 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3026 if (in_words_to_go) /* Sanity check */
3032 if (in_words_to_go < 0)
3035 mem = gen_rtx (MEM, SImode, src);
3036 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3037 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3038 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3041 if (BYTES_BIG_ENDIAN && last_bytes)
3043 rtx tmp = gen_reg_rtx (SImode);
3045 if (part_bytes_reg == NULL)
3048 /* The bytes we want are in the top end of the word */
3049 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3050 GEN_INT (8 * (4 - last_bytes))));
3051 part_bytes_reg = tmp;
3055 mem = gen_rtx (MEM, QImode, plus_constant (dst, last_bytes - 1));
3056 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3057 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3058 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3061 tmp = gen_reg_rtx (SImode);
3062 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3063 part_bytes_reg = tmp;
3072 if (part_bytes_reg == NULL)
3075 mem = gen_rtx (MEM, QImode, dst);
3076 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3077 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3078 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3081 rtx tmp = gen_reg_rtx (SImode);
3083 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3084 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3085 part_bytes_reg = tmp;
3093 /* Generate a memory reference for a half word, such that it will be loaded
3094 into the top 16 bits of the word. We can assume that the address is
3095 known to be alignable and of the form reg, or plus (reg, const). */
3097 gen_rotated_half_load (memref)
3100 HOST_WIDE_INT offset = 0;
3101 rtx base = XEXP (memref, 0);
3103 if (GET_CODE (base) == PLUS)
3105 offset = INTVAL (XEXP (base, 1));
3106 base = XEXP (base, 0);
3109 /* If we aren't allowed to generate unaligned addresses, then fail. */
3110 if (TARGET_SHORT_BY_BYTES
3111 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3114 base = gen_rtx (MEM, SImode, plus_constant (base, offset & ~2));
3116 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3119 return gen_rtx (ROTATE, SImode, base, GEN_INT (16));
3122 static enum machine_mode
3123 select_dominance_cc_mode (op, x, y, cond_or)
3127 HOST_WIDE_INT cond_or;
3129 enum rtx_code cond1, cond2;
3132 /* Currently we will probably get the wrong result if the individual
3133 comparisons are not simple. This also ensures that it is safe to
3134 reverse a comparison if necessary. */
3135 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3137 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3142 cond1 = reverse_condition (cond1);
3144 /* If the comparisons are not equal, and one doesn't dominate the other,
3145 then we can't do this. */
3147 && ! comparison_dominates_p (cond1, cond2)
3148 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3153 enum rtx_code temp = cond1;
3161 if (cond2 == EQ || ! cond_or)
3166 case LE: return CC_DLEmode;
3167 case LEU: return CC_DLEUmode;
3168 case GE: return CC_DGEmode;
3169 case GEU: return CC_DGEUmode;
3176 if (cond2 == LT || ! cond_or)
3185 if (cond2 == GT || ! cond_or)
3194 if (cond2 == LTU || ! cond_or)
3203 if (cond2 == GTU || ! cond_or)
3211 /* The remaining cases only occur when both comparisons are the
3236 arm_select_cc_mode (op, x, y)
3241 /* All floating point compares return CCFP if it is an equality
3242 comparison, and CCFPE otherwise. */
3243 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3244 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3246 /* A compare with a shifted operand. Because of canonicalization, the
3247 comparison will have to be swapped when we emit the assembler. */
3248 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3249 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3250 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3251 || GET_CODE (x) == ROTATERT))
3254 /* This is a special case that is used by combine to allow a
3255 comparison of a shifted byte load to be split into a zero-extend
3256 followed by a comparison of the shifted integer (only valid for
3257 equalities and unsigned inequalities). */
3258 if (GET_MODE (x) == SImode
3259 && GET_CODE (x) == ASHIFT
3260 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3261 && GET_CODE (XEXP (x, 0)) == SUBREG
3262 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3263 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3264 && (op == EQ || op == NE
3265 || op == GEU || op == GTU || op == LTU || op == LEU)
3266 && GET_CODE (y) == CONST_INT)
3269 /* An operation that sets the condition codes as a side-effect, the
3270 V flag is not set correctly, so we can only use comparisons where
3271 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3273 if (GET_MODE (x) == SImode
3275 && (op == EQ || op == NE || op == LT || op == GE)
3276 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3277 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3278 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3279 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3280 || GET_CODE (x) == LSHIFTRT
3281 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3282 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3285 /* A construct for a conditional compare, if the false arm contains
3286 0, then both conditions must be true, otherwise either condition
3287 must be true. Not all conditions are possible, so CCmode is
3288 returned if it can't be done. */
3289 if (GET_CODE (x) == IF_THEN_ELSE
3290 && (XEXP (x, 2) == const0_rtx
3291 || XEXP (x, 2) == const1_rtx)
3292 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3293 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3294 return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
3295 INTVAL (XEXP (x, 2)));
3297 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3300 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3301 && GET_CODE (x) == PLUS
3302 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3308 /* X and Y are two things to compare using CODE. Emit the compare insn and
3309 return the rtx for register 0 in the proper mode. FP means this is a
3310 floating point compare: I don't think that it is needed on the arm. */
3313 gen_compare_reg (code, x, y, fp)
3318 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3319 rtx cc_reg = gen_rtx (REG, mode, 24);
3321 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
3322 gen_rtx (COMPARE, mode, x, y)));
3328 arm_reload_in_hi (operands)
3331 rtx base = find_replacement (&XEXP (operands[1], 0));
3333 emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx (MEM, QImode, base)));
3334 /* Handle the case where the address is too complex to be offset by 1. */
3335 if (GET_CODE (base) == MINUS
3336 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3338 rtx base_plus = gen_rtx (REG, SImode, REGNO (operands[0]));
3340 emit_insn (gen_rtx (SET, VOIDmode, base_plus, base));
3344 emit_insn (gen_zero_extendqisi2 (gen_rtx (SUBREG, SImode, operands[0], 0),
3345 gen_rtx (MEM, QImode,
3346 plus_constant (base, 1))));
3347 if (BYTES_BIG_ENDIAN)
3348 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3350 gen_rtx (IOR, SImode,
3351 gen_rtx (ASHIFT, SImode,
3352 gen_rtx (SUBREG, SImode,
3357 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3359 gen_rtx (IOR, SImode,
3360 gen_rtx (ASHIFT, SImode,
3363 gen_rtx (SUBREG, SImode, operands[0], 0))));
3367 arm_reload_out_hi (operands)
3370 rtx base = find_replacement (&XEXP (operands[0], 0));
3372 if (BYTES_BIG_ENDIAN)
3374 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3375 gen_rtx (SUBREG, QImode, operands[1], 0)));
3376 emit_insn (gen_lshrsi3 (operands[2],
3377 gen_rtx (SUBREG, SImode, operands[1], 0),
3379 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3380 gen_rtx (SUBREG, QImode, operands[2], 0)));
3384 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3385 gen_rtx (SUBREG, QImode, operands[1], 0)));
3386 emit_insn (gen_lshrsi3 (operands[2],
3387 gen_rtx (SUBREG, SImode, operands[1], 0),
3389 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3390 gen_rtx (SUBREG, QImode, operands[2], 0)));
3394 /* Routines for manipulation of the constant pool. */
3395 /* This is unashamedly hacked from the version in sh.c, since the problem is
3396 extremely similar. */
3398 /* Arm instructions cannot load a large constant into a register,
3399 constants have to come from a pc relative load. The reference of a pc
3400 relative load instruction must be less than 1k infront of the instruction.
3401 This means that we often have to dump a constant inside a function, and
3402 generate code to branch around it.
3404 It is important to minimize this, since the branches will slow things
3405 down and make things bigger.
3407 Worst case code looks like:
3423 We fix this by performing a scan before scheduling, which notices which
3424 instructions need to have their operands fetched from the constant table
3425 and builds the table.
3430 scan, find an instruction which needs a pcrel move. Look forward, find th
3431 last barrier which is within MAX_COUNT bytes of the requirement.
3432 If there isn't one, make one. Process all the instructions between
3433 the find and the barrier.
3435 In the above example, we can tell that L3 is within 1k of L1, so
3436 the first move can be shrunk from the 2 insn+constant sequence into
3437 just 1 insn, and the constant moved to L3 to make:
3448 Then the second move becomes the target for the shortening process.
3454 rtx value; /* Value in table */
3455 HOST_WIDE_INT next_offset;
3456 enum machine_mode mode; /* Mode of value */
3459 /* The maximum number of constants that can fit into one pool, since
3460 the pc relative range is 0...1020 bytes and constants are at least 4
3463 #define MAX_POOL_SIZE (1020/4)
3464 static pool_node pool_vector[MAX_POOL_SIZE];
3465 static int pool_size;
3466 static rtx pool_vector_label;
3468 /* Add a constant to the pool and return its offset within the current
3471 X is the rtx we want to replace. MODE is its mode. On return,
3472 ADDRESS_ONLY will be non-zero if we really want the address of such
3473 a constant, not the constant itself. */
3474 static HOST_WIDE_INT
3475 add_constant (x, mode, address_only)
3477 enum machine_mode mode;
3481 HOST_WIDE_INT offset;
3485 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3486 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3487 x = get_pool_constant (XEXP (x, 0));
3488 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3491 x = get_pool_constant (x);
3493 #ifndef AOF_ASSEMBLER
3494 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3495 x = XVECEXP (x, 0, 0);
3498 #ifdef AOF_ASSEMBLER
3499 /* PIC Symbol references need to be converted into offsets into the
3501 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
3502 x = aof_pic_entry (x);
3503 #endif /* AOF_ASSEMBLER */
3505 /* First see if we've already got it */
3506 for (i = 0; i < pool_size; i++)
3508 if (GET_CODE (x) == pool_vector[i].value->code
3509 && mode == pool_vector[i].mode)
3511 if (GET_CODE (x) == CODE_LABEL)
3513 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3516 if (rtx_equal_p (x, pool_vector[i].value))
3517 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
3521 /* Need a new one */
3522 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
3525 pool_vector_label = gen_label_rtx ();
3527 pool_vector[pool_size].next_offset
3528 += (offset = pool_vector[pool_size - 1].next_offset);
3530 pool_vector[pool_size].value = x;
3531 pool_vector[pool_size].mode = mode;
3536 /* Output the literal table */
3543 scan = emit_label_after (gen_label_rtx (), scan);
3544 scan = emit_insn_after (gen_align_4 (), scan);
3545 scan = emit_label_after (pool_vector_label, scan);
3547 for (i = 0; i < pool_size; i++)
3549 pool_node *p = pool_vector + i;
3551 switch (GET_MODE_SIZE (p->mode))
3554 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
3558 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
3567 scan = emit_insn_after (gen_consttable_end (), scan);
3568 scan = emit_barrier_after (scan);
3572 /* Non zero if the src operand needs to be fixed up */
3574 fixit (src, mode, destreg)
3576 enum machine_mode mode;
3579 if (CONSTANT_P (src))
3581 if (GET_CODE (src) == CONST_INT)
3582 return (! const_ok_for_arm (INTVAL (src))
3583 && ! const_ok_for_arm (~INTVAL (src)));
3584 if (GET_CODE (src) == CONST_DOUBLE)
3585 return (GET_MODE (src) == VOIDmode
3587 || (! const_double_rtx_ok_for_fpu (src)
3588 && ! neg_const_double_rtx_ok_for_fpu (src)));
3589 return symbol_mentioned_p (src);
3591 #ifndef AOF_ASSEMBLER
3592 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
3596 return (mode == SImode && GET_CODE (src) == MEM
3597 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
3598 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
3601 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3603 find_barrier (from, max_count)
3608 rtx found_barrier = 0;
3611 while (from && count < max_count)
3615 if (GET_CODE (from) == BARRIER)
3616 found_barrier = from;
3618 /* Count the length of this insn */
3619 if (GET_CODE (from) == INSN
3620 && GET_CODE (PATTERN (from)) == SET
3621 && CONSTANT_P (SET_SRC (PATTERN (from)))
3622 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
3624 /* Handle table jumps as a single entity. */
3625 else if (GET_CODE (from) == JUMP_INSN
3626 && JUMP_LABEL (from) != 0
3627 && ((tmp = next_real_insn (JUMP_LABEL (from)))
3628 == next_real_insn (from))
3630 && GET_CODE (tmp) == JUMP_INSN
3631 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
3632 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
3634 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
3635 count += (get_attr_length (from)
3636 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
3637 /* Continue after the dispatch table. */
3639 from = NEXT_INSN (tmp);
3643 count += get_attr_length (from);
3646 from = NEXT_INSN (from);
3649 if (! found_barrier)
3651 /* We didn't find a barrier in time to
3652 dump our stuff, so we'll make one. */
3653 rtx label = gen_label_rtx ();
3656 from = PREV_INSN (last);
3658 from = get_last_insn ();
3660 /* Walk back to be just before any jump. */
3661 while (GET_CODE (from) == JUMP_INSN
3662 || GET_CODE (from) == NOTE
3663 || GET_CODE (from) == CODE_LABEL)
3664 from = PREV_INSN (from);
3666 from = emit_jump_insn_after (gen_jump (label), from);
3667 JUMP_LABEL (from) = label;
3668 found_barrier = emit_barrier_after (from);
3669 emit_label_after (label, found_barrier);
3672 return found_barrier;
3675 /* Non zero if the insn is a move instruction which needs to be fixed. */
3680 if (!INSN_DELETED_P (insn)
3681 && GET_CODE (insn) == INSN
3682 && GET_CODE (PATTERN (insn)) == SET)
3684 rtx pat = PATTERN (insn);
3685 rtx src = SET_SRC (pat);
3686 rtx dst = SET_DEST (pat);
3688 enum machine_mode mode = GET_MODE (dst);
3693 if (GET_CODE (dst) == REG)
3694 destreg = REGNO (dst);
3695 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
3696 destreg = REGNO (SUBREG_REG (dst));
3700 return fixit (src, mode, destreg);
3713 /* The ldr instruction can work with up to a 4k offset, and most constants
3714 will be loaded with one of these instructions; however, the adr
3715 instruction and the ldf instructions only work with a 1k offset. This
3716 code needs to be rewritten to use the 4k offset when possible, and to
3717 adjust when a 1k offset is needed. For now we just use a 1k offset
3721 /* Floating point operands can't work further than 1024 bytes from the
3722 PC, so to make things simple we restrict all loads for such functions.
3724 if (TARGET_HARD_FLOAT)
3728 for (regno = 16; regno < 24; regno++)
3729 if (regs_ever_live[regno])
3739 for (insn = first; insn; insn = NEXT_INSN (insn))
3741 if (broken_move (insn))
3743 /* This is a broken move instruction, scan ahead looking for
3744 a barrier to stick the constant table behind */
3746 rtx barrier = find_barrier (insn, count_size);
3748 /* Now find all the moves between the points and modify them */
3749 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3751 if (broken_move (scan))
3753 /* This is a broken move instruction, add it to the pool */
3754 rtx pat = PATTERN (scan);
3755 rtx src = SET_SRC (pat);
3756 rtx dst = SET_DEST (pat);
3757 enum machine_mode mode = GET_MODE (dst);
3758 HOST_WIDE_INT offset;
3765 /* If this is an HImode constant load, convert it into
3766 an SImode constant load. Since the register is always
3767 32 bits this is safe. We have to do this, since the
3768 load pc-relative instruction only does a 32-bit load. */
3772 if (GET_CODE (dst) != REG)
3774 PUT_MODE (dst, SImode);
3777 offset = add_constant (src, mode, &address_only);
3778 addr = plus_constant (gen_rtx (LABEL_REF, VOIDmode,
3782 /* If we only want the address of the pool entry, or
3783 for wide moves to integer regs we need to split
3784 the address calculation off into a separate insn.
3785 If necessary, the load can then be done with a
3786 load-multiple. This is safe, since we have
3787 already noted the length of such insns to be 8,
3788 and we are immediately over-writing the scratch
3789 we have grabbed with the final result. */
3790 if ((address_only || GET_MODE_SIZE (mode) > 4)
3791 && (scratch = REGNO (dst)) < 16)
3798 reg = gen_rtx (REG, SImode, scratch);
3800 newinsn = emit_insn_after (gen_movaddr (reg, addr),
3807 newsrc = gen_rtx (MEM, mode, addr);
3809 /* XXX Fixme -- I think the following is bogus. */
3810 /* Build a jump insn wrapper around the move instead
3811 of an ordinary insn, because we want to have room for
3812 the target label rtx in fld[7], which an ordinary
3813 insn doesn't have. */
3814 newinsn = emit_jump_insn_after
3815 (gen_rtx (SET, VOIDmode, dst, newsrc), newinsn);
3816 JUMP_LABEL (newinsn) = pool_vector_label;
3818 /* But it's still an ordinary insn */
3819 PUT_CODE (newinsn, INSN);
3827 dump_table (barrier);
3834 /* Routines to output assembly language. */
3836 /* If the rtx is the correct value then return the string of the number.
3837 In this way we can ensure that valid double constants are generated even
3838 when cross compiling. */
3840 fp_immediate_constant (x)
3846 if (!fpa_consts_inited)
3849 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3850 for (i = 0; i < 8; i++)
3851 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3852 return strings_fpa[i];
3857 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
3859 fp_const_from_val (r)
3864 if (! fpa_consts_inited)
3867 for (i = 0; i < 8; i++)
3868 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
3869 return strings_fpa[i];
3874 /* Output the operands of a LDM/STM instruction to STREAM.
3875 MASK is the ARM register set mask of which only bits 0-15 are important.
3876 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
3877 must follow the register list. */
3880 print_multi_reg (stream, instr, mask, hat)
3886 int not_first = FALSE;
3888 fputc ('\t', stream);
3889 fprintf (stream, instr, REGISTER_PREFIX);
3890 fputs (", {", stream);
3891 for (i = 0; i < 16; i++)
3892 if (mask & (1 << i))
3895 fprintf (stream, ", ");
3896 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
3900 fprintf (stream, "}%s\n", hat ? "^" : "");
3903 /* Output a 'call' insn. */
3906 output_call (operands)
3909 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
3911 if (REGNO (operands[0]) == 14)
3913 operands[0] = gen_rtx (REG, SImode, 12);
3914 output_asm_insn ("mov%?\t%0, %|lr", operands);
3916 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3918 if (TARGET_THUMB_INTERWORK)
3919 output_asm_insn ("bx%?\t%0", operands);
3921 output_asm_insn ("mov%?\t%|pc, %0", operands);
3930 int something_changed = 0;
3932 int code = GET_CODE (x0);
3939 if (REGNO (x0) == 14)
3941 *x = gen_rtx (REG, SImode, 12);
3946 /* Scan through the sub-elements and change any references there */
3947 fmt = GET_RTX_FORMAT (code);
3948 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3950 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
3951 else if (fmt[i] == 'E')
3952 for (j = 0; j < XVECLEN (x0, i); j++)
3953 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
3954 return something_changed;
3958 /* Output a 'call' insn that is a reference in memory. */
3961 output_call_mem (operands)
3964 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
3965 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
3967 if (eliminate_lr2ip (&operands[0]))
3968 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
3970 if (TARGET_THUMB_INTERWORK)
3972 output_asm_insn ("ldr%?\t%|ip, %0", operands);
3973 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3974 output_asm_insn ("bx%?\t%|ip", operands);
3978 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3979 output_asm_insn ("ldr%?\t%|pc, %0", operands);
3986 /* Output a move from arm registers to an fpu registers.
3987 OPERANDS[0] is an fpu register.
3988 OPERANDS[1] is the first registers of an arm register pair. */
3991 output_mov_long_double_fpu_from_arm (operands)
3994 int arm_reg0 = REGNO (operands[1]);
4000 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4001 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4002 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
4004 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4005 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4009 /* Output a move from an fpu register to arm registers.
4010 OPERANDS[0] is the first registers of an arm register pair.
4011 OPERANDS[1] is an fpu register. */
4014 output_mov_long_double_arm_from_fpu (operands)
4017 int arm_reg0 = REGNO (operands[0]);
4023 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4024 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4025 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
4027 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4028 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4032 /* Output a move from arm registers to arm registers of a long double
4033 OPERANDS[0] is the destination.
4034 OPERANDS[1] is the source. */
4036 output_mov_long_double_arm_from_arm (operands)
4039 /* We have to be careful here because the two might overlap */
4040 int dest_start = REGNO (operands[0]);
4041 int src_start = REGNO (operands[1]);
4045 if (dest_start < src_start)
4047 for (i = 0; i < 3; i++)
4049 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4050 ops[1] = gen_rtx (REG, SImode, src_start + i);
4051 output_asm_insn ("mov%?\t%0, %1", ops);
4056 for (i = 2; i >= 0; i--)
4058 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4059 ops[1] = gen_rtx (REG, SImode, src_start + i);
4060 output_asm_insn ("mov%?\t%0, %1", ops);
4068 /* Output a move from arm registers to an fpu registers.
4069 OPERANDS[0] is an fpu register.
4070 OPERANDS[1] is the first registers of an arm register pair. */
4073 output_mov_double_fpu_from_arm (operands)
4076 int arm_reg0 = REGNO (operands[1]);
4081 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4082 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4083 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4084 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4088 /* Output a move from an fpu register to arm registers.
4089 OPERANDS[0] is the first registers of an arm register pair.
4090 OPERANDS[1] is an fpu register. */
4093 output_mov_double_arm_from_fpu (operands)
4096 int arm_reg0 = REGNO (operands[0]);
4102 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4103 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4104 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4105 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4109 /* Output a move between double words.
4110 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4111 or MEM<-REG and all MEMs must be offsettable addresses. */
4114 output_move_double (operands)
4117 enum rtx_code code0 = GET_CODE (operands[0]);
4118 enum rtx_code code1 = GET_CODE (operands[1]);
4123 int reg0 = REGNO (operands[0]);
4125 otherops[0] = gen_rtx (REG, SImode, 1 + reg0);
4128 int reg1 = REGNO (operands[1]);
4132 /* Ensure the second source is not overwritten */
4133 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4134 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4136 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4138 else if (code1 == CONST_DOUBLE)
4140 if (GET_MODE (operands[1]) == DFmode)
4143 union real_extract u;
4145 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4147 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4148 otherops[1] = GEN_INT(l[1]);
4149 operands[1] = GEN_INT(l[0]);
4151 else if (GET_MODE (operands[1]) != VOIDmode)
4153 else if (WORDS_BIG_ENDIAN)
4156 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4157 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4162 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4163 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4165 output_mov_immediate (operands);
4166 output_mov_immediate (otherops);
4168 else if (code1 == CONST_INT)
4170 #if HOST_BITS_PER_WIDE_INT > 32
4171 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4172 what the upper word is. */
4173 if (WORDS_BIG_ENDIAN)
4175 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4176 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4180 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4181 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4184 /* Sign extend the intval into the high-order word */
4185 if (WORDS_BIG_ENDIAN)
4187 otherops[1] = operands[1];
4188 operands[1] = (INTVAL (operands[1]) < 0
4189 ? constm1_rtx : const0_rtx);
4192 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4194 output_mov_immediate (otherops);
4195 output_mov_immediate (operands);
4197 else if (code1 == MEM)
4199 switch (GET_CODE (XEXP (operands[1], 0)))
4202 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4206 abort (); /* Should never happen now */
4210 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4214 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4218 abort (); /* Should never happen now */
4223 output_asm_insn ("adr%?\t%0, %1", operands);
4224 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4228 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
4230 otherops[0] = operands[0];
4231 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4232 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4233 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4235 if (GET_CODE (otherops[2]) == CONST_INT)
4237 switch (INTVAL (otherops[2]))
4240 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4243 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4246 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4249 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4250 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4252 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4255 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4258 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4259 return "ldm%?ia\t%0, %M0";
4263 otherops[1] = adj_offsettable_operand (operands[1], 4);
4264 /* Take care of overlapping base/data reg. */
4265 if (reg_mentioned_p (operands[0], operands[1]))
4267 output_asm_insn ("ldr%?\t%0, %1", otherops);
4268 output_asm_insn ("ldr%?\t%0, %1", operands);
4272 output_asm_insn ("ldr%?\t%0, %1", operands);
4273 output_asm_insn ("ldr%?\t%0, %1", otherops);
4279 abort(); /* Constraints should prevent this */
4281 else if (code0 == MEM && code1 == REG)
4283 if (REGNO (operands[1]) == 12)
4286 switch (GET_CODE (XEXP (operands[0], 0)))
4289 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4293 abort (); /* Should never happen now */
4297 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4301 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4305 abort (); /* Should never happen now */
4309 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4311 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4314 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4318 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4322 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4329 otherops[0] = adj_offsettable_operand (operands[0], 4);
4330 otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1]));
4331 output_asm_insn ("str%?\t%1, %0", operands);
4332 output_asm_insn ("str%?\t%1, %0", otherops);
4336 abort(); /* Constraints should prevent this */
4342 /* Output an arbitrary MOV reg, #n.
4343 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4346 output_mov_immediate (operands)
4349 HOST_WIDE_INT n = INTVAL (operands[1]);
4353 /* Try to use one MOV */
4354 if (const_ok_for_arm (n))
4356 output_asm_insn ("mov%?\t%0, %1", operands);
4360 /* Try to use one MVN */
4361 if (const_ok_for_arm (~n))
4363 operands[1] = GEN_INT (~n);
4364 output_asm_insn ("mvn%?\t%0, %1", operands);
4368 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4370 for (i=0; i < 32; i++)
4374 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4375 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4378 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4385 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4386 adding zero to one register, output nothing. */
4389 output_add_immediate (operands)
4392 HOST_WIDE_INT n = INTVAL (operands[2]);
4394 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4397 output_multi_immediate (operands,
4398 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4401 output_multi_immediate (operands,
4402 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4409 /* Output a multiple immediate operation.
4410 OPERANDS is the vector of operands referred to in the output patterns.
4411 INSTR1 is the output pattern to use for the first constant.
4412 INSTR2 is the output pattern to use for subsequent constants.
4413 IMMED_OP is the index of the constant slot in OPERANDS.
4414 N is the constant value. */
4417 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4419 char *instr1, *instr2;
4423 #if HOST_BITS_PER_WIDE_INT > 32
4429 operands[immed_op] = const0_rtx;
4430 output_asm_insn (instr1, operands); /* Quick and easy output */
4435 char *instr = instr1;
4437 /* Note that n is never zero here (which would give no output) */
4438 for (i = 0; i < 32; i += 2)
4442 operands[immed_op] = GEN_INT (n & (255 << i));
4443 output_asm_insn (instr, operands);
4453 /* Return the appropriate ARM instruction for the operation code.
4454 The returned result should not be overwritten. OP is the rtx of the
4455 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4459 arithmetic_instr (op, shift_first_arg)
4461 int shift_first_arg;
4463 switch (GET_CODE (op))
4469 return shift_first_arg ? "rsb" : "sub";
4486 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4487 for the operation code. The returned result should not be overwritten.
4488 OP is the rtx code of the shift.
4489 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4493 shift_op (op, amountp)
4495 HOST_WIDE_INT *amountp;
4498 enum rtx_code code = GET_CODE (op);
4500 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
4502 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
4503 *amountp = INTVAL (XEXP (op, 1));
4526 /* We never have to worry about the amount being other than a
4527 power of 2, since this case can never be reloaded from a reg. */
4529 *amountp = int_log2 (*amountp);
4540 /* This is not 100% correct, but follows from the desire to merge
4541 multiplication by a power of 2 with the recognizer for a
4542 shift. >=32 is not a valid shift for "asl", so we must try and
4543 output a shift that produces the correct arithmetical result.
4544 Using lsr #32 is identical except for the fact that the carry bit
4545 is not set correctly if we set the flags; but we never use the
4546 carry bit from such an operation, so we can ignore that. */
4547 if (code == ROTATERT)
4548 *amountp &= 31; /* Rotate is just modulo 32 */
4549 else if (*amountp != (*amountp & 31))
4556 /* Shifts of 0 are no-ops. */
4565 /* Obtain the shift from the POWER of two. */
4567 static HOST_WIDE_INT
4569 HOST_WIDE_INT power;
4571 HOST_WIDE_INT shift = 0;
4573 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
4583 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4584 /bin/as is horribly restrictive. */
4587 output_ascii_pseudo_op (stream, p, len)
4593 int len_so_far = 1000;
4594 int chars_so_far = 0;
4596 for (i = 0; i < len; i++)
4598 register int c = p[i];
4600 if (len_so_far > 50)
4603 fputs ("\"\n", stream);
4604 fputs ("\t.ascii\t\"", stream);
4609 if (c == '\"' || c == '\\')
4615 if (c >= ' ' && c < 0177)
4622 fprintf (stream, "\\%03o", c);
4629 fputs ("\"\n", stream);
4633 /* Try to determine whether a pattern really clobbers the link register.
4634 This information is useful when peepholing, so that lr need not be pushed
4635 if we combine a call followed by a return.
4636 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4637 such a check should not be needed because these only update an existing
4638 value within a register; the register must still be set elsewhere within
4642 pattern_really_clobbers_lr (x)
4647 switch (GET_CODE (x))
4650 switch (GET_CODE (SET_DEST (x)))
4653 return REGNO (SET_DEST (x)) == 14;
4656 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
4657 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
4659 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
4668 for (i = 0; i < XVECLEN (x, 0); i++)
4669 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
4674 switch (GET_CODE (XEXP (x, 0)))
4677 return REGNO (XEXP (x, 0)) == 14;
4680 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
4681 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
4697 function_really_clobbers_lr (first)
4702 for (insn = first; insn; insn = next_nonnote_insn (insn))
4704 switch (GET_CODE (insn))
4709 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
4714 if (pattern_really_clobbers_lr (PATTERN (insn)))
4719 /* Don't yet know how to handle those calls that are not to a
4721 if (GET_CODE (PATTERN (insn)) != PARALLEL)
4724 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
4727 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
4733 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
4739 default: /* Don't recognize it, be safe */
4743 /* A call can be made (by peepholing) not to clobber lr iff it is
4744 followed by a return. There may, however, be a use insn iff
4745 we are returning the result of the call.
4746 If we run off the end of the insn chain, then that means the
4747 call was at the end of the function. Unfortunately we don't
4748 have a return insn for the peephole to recognize, so we
4749 must reject this. (Can this be fixed by adding our own insn?) */
4750 if ((next = next_nonnote_insn (insn)) == NULL)
4753 /* No need to worry about lr if the call never returns */
4754 if (GET_CODE (next) == BARRIER)
4757 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
4758 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4759 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
4760 == REGNO (XEXP (PATTERN (next), 0))))
4761 if ((next = next_nonnote_insn (next)) == NULL)
4764 if (GET_CODE (next) == JUMP_INSN
4765 && GET_CODE (PATTERN (next)) == RETURN)
4774 /* We have reached the end of the chain so lr was _not_ clobbered */
4779 output_return_instruction (operand, really_return, reverse)
4785 int reg, live_regs = 0;
4786 int volatile_func = (optimize > 0
4787 && TREE_THIS_VOLATILE (current_function_decl));
4789 return_used_this_function = 1;
4794 /* If this function was declared non-returning, and we have found a tail
4795 call, then we have to trust that the called function won't return. */
4796 if (! really_return)
4799 /* Otherwise, trap an attempted return by aborting. */
4801 ops[1] = gen_rtx (SYMBOL_REF, Pmode, "abort");
4802 assemble_external_libcall (ops[1]);
4803 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
4807 if (current_function_calls_alloca && ! really_return)
4810 for (reg = 0; reg <= 10; reg++)
4811 if (regs_ever_live[reg] && ! call_used_regs[reg])
4814 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
4817 if (frame_pointer_needed)
4822 if (lr_save_eliminated || ! regs_ever_live[14])
4825 if (frame_pointer_needed)
4827 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
4830 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
4832 for (reg = 0; reg <= 10; reg++)
4833 if (regs_ever_live[reg] && ! call_used_regs[reg])
4835 strcat (instr, "%|");
4836 strcat (instr, reg_names[reg]);
4838 strcat (instr, ", ");
4841 if (frame_pointer_needed)
4843 strcat (instr, "%|");
4844 strcat (instr, reg_names[11]);
4845 strcat (instr, ", ");
4846 strcat (instr, "%|");
4847 strcat (instr, reg_names[13]);
4848 strcat (instr, ", ");
4849 strcat (instr, "%|");
4850 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
4851 ? reg_names[14] : reg_names[15] );
4855 strcat (instr, "%|");
4856 if (TARGET_THUMB_INTERWORK && really_return)
4857 strcat (instr, reg_names[12]);
4859 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4861 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
4862 output_asm_insn (instr, &operand);
4864 if (TARGET_THUMB_INTERWORK && really_return)
4866 strcpy (instr, "bx%?");
4867 strcat (instr, reverse ? "%D0" : "%d0");
4868 strcat (instr, "\t%|");
4869 strcat (instr, frame_pointer_needed ? "lr" : "ip");
4871 output_asm_insn (instr, & operand);
4874 else if (really_return)
4876 if (TARGET_THUMB_INTERWORK)
4877 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
4879 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
4880 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
4882 output_asm_insn (instr, & operand);
4888 /* Return nonzero if optimizing and the current function is volatile.
4889 Such functions never return, and many memory cycles can be saved
4890 by not storing register values that will never be needed again.
4891 This optimization was added to speed up context switching in a
4892 kernel application. */
4895 arm_volatile_func ()
4897 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
4900 /* The amount of stack adjustment that happens here, in output_return and in
4901 output_epilogue must be exactly the same as was calculated during reload,
4902 or things will point to the wrong place. The only time we can safely
4903 ignore this constraint is when a function has no arguments on the stack,
4904 no stack frame requirement and no live registers execpt for `lr'. If we
4905 can guarantee that by making all function calls into tail calls and that
4906 lr is not clobbered in any other way, then there is no need to push lr
4910 output_func_prologue (f, frame_size)
4914 int reg, live_regs_mask = 0;
4915 int volatile_func = (optimize > 0
4916 && TREE_THIS_VOLATILE (current_function_decl));
4918 /* Nonzero if we must stuff some register arguments onto the stack as if
4919 they were passed there. */
4920 int store_arg_regs = 0;
4922 if (arm_ccfsm_state || arm_target_insn)
4923 abort (); /* Sanity check */
4925 if (arm_naked_function_p (current_function_decl))
4928 return_used_this_function = 0;
4929 lr_save_eliminated = 0;
4931 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
4932 ASM_COMMENT_START, current_function_args_size,
4933 current_function_pretend_args_size, frame_size);
4934 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
4935 ASM_COMMENT_START, frame_pointer_needed,
4936 current_function_anonymous_args);
4939 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
4941 if (current_function_anonymous_args && current_function_pretend_args_size)
4944 for (reg = 0; reg <= 10; reg++)
4945 if (regs_ever_live[reg] && ! call_used_regs[reg])
4946 live_regs_mask |= (1 << reg);
4948 if (frame_pointer_needed)
4949 live_regs_mask |= 0xD800;
4950 else if (regs_ever_live[14])
4952 if (! current_function_args_size
4953 && ! function_really_clobbers_lr (get_insns ()))
4954 lr_save_eliminated = 1;
4956 live_regs_mask |= 0x4000;
4961 /* if a di mode load/store multiple is used, and the base register
4962 is r3, then r4 can become an ever live register without lr
4963 doing so, in this case we need to push lr as well, or we
4964 will fail to get a proper return. */
4966 live_regs_mask |= 0x4000;
4967 lr_save_eliminated = 0;
4971 if (lr_save_eliminated)
4972 fprintf (f,"\t%s I don't think this function clobbers lr\n",
4975 #ifdef AOF_ASSEMBLER
4977 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
4978 reg_names[PIC_OFFSET_TABLE_REGNUM]);
4984 output_func_epilogue (f, frame_size)
4988 int reg, live_regs_mask = 0;
4989 /* If we need this then it will always be at least this much */
4990 int floats_offset = 12;
4992 int volatile_func = (optimize > 0
4993 && TREE_THIS_VOLATILE (current_function_decl));
4995 if (use_return_insn() && return_used_this_function)
4997 if ((frame_size + current_function_outgoing_args_size) != 0
4998 && !(frame_pointer_needed || TARGET_APCS))
5003 /* Naked functions don't have epilogues. */
5004 if (arm_naked_function_p (current_function_decl))
5007 /* A volatile function should never return. Call abort. */
5010 rtx op = gen_rtx (SYMBOL_REF, Pmode, "abort");
5011 assemble_external_libcall (op);
5012 output_asm_insn ("bl\t%a0", &op);
5016 for (reg = 0; reg <= 10; reg++)
5017 if (regs_ever_live[reg] && ! call_used_regs[reg])
5019 live_regs_mask |= (1 << reg);
5023 if (frame_pointer_needed)
5025 if (arm_fpu_arch == FP_SOFT2)
5027 for (reg = 23; reg > 15; reg--)
5028 if (regs_ever_live[reg] && ! call_used_regs[reg])
5030 floats_offset += 12;
5031 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
5032 reg_names[reg], REGISTER_PREFIX, floats_offset);
5039 for (reg = 23; reg > 15; reg--)
5041 if (regs_ever_live[reg] && ! call_used_regs[reg])
5043 floats_offset += 12;
5044 /* We can't unstack more than four registers at once */
5045 if (start_reg - reg == 3)
5047 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
5048 REGISTER_PREFIX, reg_names[reg],
5049 REGISTER_PREFIX, floats_offset);
5050 start_reg = reg - 1;
5055 if (reg != start_reg)
5056 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5057 REGISTER_PREFIX, reg_names[reg + 1],
5058 start_reg - reg, REGISTER_PREFIX, floats_offset);
5060 start_reg = reg - 1;
5064 /* Just in case the last register checked also needs unstacking. */
5065 if (reg != start_reg)
5066 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5067 REGISTER_PREFIX, reg_names[reg + 1],
5068 start_reg - reg, REGISTER_PREFIX, floats_offset);
5071 if (TARGET_THUMB_INTERWORK)
5073 live_regs_mask |= 0x6800;
5074 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5075 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5079 live_regs_mask |= 0xA800;
5080 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5081 TARGET_APCS_32 ? FALSE : TRUE);
5086 /* Restore stack pointer if necessary. */
5087 if (frame_size + current_function_outgoing_args_size != 0)
5089 operands[0] = operands[1] = stack_pointer_rtx;
5090 operands[2] = GEN_INT (frame_size
5091 + current_function_outgoing_args_size);
5092 output_add_immediate (operands);
5095 if (arm_fpu_arch == FP_SOFT2)
5097 for (reg = 16; reg < 24; reg++)
5098 if (regs_ever_live[reg] && ! call_used_regs[reg])
5099 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5100 reg_names[reg], REGISTER_PREFIX);
5106 for (reg = 16; reg < 24; reg++)
5108 if (regs_ever_live[reg] && ! call_used_regs[reg])
5110 if (reg - start_reg == 3)
5112 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5113 REGISTER_PREFIX, reg_names[start_reg],
5115 start_reg = reg + 1;
5120 if (reg != start_reg)
5121 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5122 REGISTER_PREFIX, reg_names[start_reg],
5123 reg - start_reg, REGISTER_PREFIX);
5125 start_reg = reg + 1;
5129 /* Just in case the last register checked also needs unstacking. */
5130 if (reg != start_reg)
5131 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5132 REGISTER_PREFIX, reg_names[start_reg],
5133 reg - start_reg, REGISTER_PREFIX);
5136 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5138 if (TARGET_THUMB_INTERWORK)
5140 if (! lr_save_eliminated)
5141 print_multi_reg(f, "ldmfd\t%ssp!", live_regs_mask | 0x4000,
5144 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5146 else if (lr_save_eliminated)
5147 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5148 : "\tmovs\t%spc, %slr\n"),
5149 REGISTER_PREFIX, REGISTER_PREFIX, f);
5151 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5152 TARGET_APCS_32 ? FALSE : TRUE);
5156 if (live_regs_mask || regs_ever_live[14])
5158 /* Restore the integer regs, and the return address into lr */
5159 if (! lr_save_eliminated)
5160 live_regs_mask |= 0x4000;
5162 if (live_regs_mask != 0)
5163 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5166 if (current_function_pretend_args_size)
5168 /* Unwind the pre-pushed regs */
5169 operands[0] = operands[1] = stack_pointer_rtx;
5170 operands[2] = GEN_INT (current_function_pretend_args_size);
5171 output_add_immediate (operands);
5173 /* And finally, go home */
5174 if (TARGET_THUMB_INTERWORK)
5175 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5176 else if (TARGET_APCS_32)
5177 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5179 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5185 current_function_anonymous_args = 0;
5189 emit_multi_reg_push (mask)
5196 for (i = 0; i < 16; i++)
5197 if (mask & (1 << i))
5200 if (num_regs == 0 || num_regs > 16)
5203 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num_regs));
5205 for (i = 0; i < 16; i++)
5207 if (mask & (1 << i))
5210 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, BLKmode,
5211 gen_rtx (PRE_DEC, BLKmode,
5212 stack_pointer_rtx)),
5213 gen_rtx (UNSPEC, BLKmode,
5214 gen_rtvec (1, gen_rtx (REG, SImode, i)),
5220 for (j = 1, i++; j < num_regs; i++)
5222 if (mask & (1 << i))
5225 = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, i));
5234 emit_sfm (base_reg, count)
5241 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5243 XVECEXP (par, 0, 0) = gen_rtx (SET, VOIDmode,
5244 gen_rtx (MEM, BLKmode,
5245 gen_rtx (PRE_DEC, BLKmode,
5246 stack_pointer_rtx)),
5247 gen_rtx (UNSPEC, BLKmode,
5248 gen_rtvec (1, gen_rtx (REG, XFmode,
5251 for (i = 1; i < count; i++)
5252 XVECEXP (par, 0, i) = gen_rtx (USE, VOIDmode,
5253 gen_rtx (REG, XFmode, base_reg++));
5259 arm_expand_prologue ()
5262 rtx amount = GEN_INT (-(get_frame_size ()
5263 + current_function_outgoing_args_size));
5264 int live_regs_mask = 0;
5265 int store_arg_regs = 0;
5266 int volatile_func = (optimize > 0
5267 && TREE_THIS_VOLATILE (current_function_decl));
5269 /* Naked functions don't have prologues. */
5270 if (arm_naked_function_p (current_function_decl))
5273 if (current_function_anonymous_args && current_function_pretend_args_size)
5276 if (! volatile_func)
5277 for (reg = 0; reg <= 10; reg++)
5278 if (regs_ever_live[reg] && ! call_used_regs[reg])
5279 live_regs_mask |= 1 << reg;
5281 if (! volatile_func && regs_ever_live[14])
5282 live_regs_mask |= 0x4000;
5284 if (frame_pointer_needed)
5286 live_regs_mask |= 0xD800;
5287 emit_insn (gen_movsi (gen_rtx (REG, SImode, 12),
5288 stack_pointer_rtx));
5291 if (current_function_pretend_args_size)
5294 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5297 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5298 GEN_INT (-current_function_pretend_args_size)));
5303 /* If we have to push any regs, then we must push lr as well, or
5304 we won't get a proper return. */
5305 live_regs_mask |= 0x4000;
5306 emit_multi_reg_push (live_regs_mask);
5309 /* For now the integer regs are still pushed in output_func_epilogue (). */
5311 if (! volatile_func)
5313 if (arm_fpu_arch == FP_SOFT2)
5315 for (reg = 23; reg > 15; reg--)
5316 if (regs_ever_live[reg] && ! call_used_regs[reg])
5317 emit_insn (gen_rtx (SET, VOIDmode,
5318 gen_rtx (MEM, XFmode,
5319 gen_rtx (PRE_DEC, XFmode,
5320 stack_pointer_rtx)),
5321 gen_rtx (REG, XFmode, reg)));
5327 for (reg = 23; reg > 15; reg--)
5329 if (regs_ever_live[reg] && ! call_used_regs[reg])
5331 if (start_reg - reg == 3)
5334 start_reg = reg - 1;
5339 if (start_reg != reg)
5340 emit_sfm (reg + 1, start_reg - reg);
5341 start_reg = reg - 1;
5345 if (start_reg != reg)
5346 emit_sfm (reg + 1, start_reg - reg);
5350 if (frame_pointer_needed)
5351 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx (REG, SImode, 12),
5353 (-(4 + current_function_pretend_args_size)))));
5355 if (amount != const0_rtx)
5357 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5358 emit_insn (gen_rtx (CLOBBER, VOIDmode,
5359 gen_rtx (MEM, BLKmode, stack_pointer_rtx)));
5362 /* If we are profiling, make sure no instructions are scheduled before
5363 the call to mcount. */
5364 if (profile_flag || profile_block_flag)
5365 emit_insn (gen_blockage ());
5369 /* If CODE is 'd', then the X is a condition operand and the instruction
5370 should only be executed if the condition is true.
5371 if CODE is 'D', then the X is a condition operand and the instruction
5372 should only be executed if the condition is false: however, if the mode
5373 of the comparison is CCFPEmode, then always execute the instruction -- we
5374 do this because in these circumstances !GE does not necessarily imply LT;
5375 in these cases the instruction pattern will take care to make sure that
5376 an instruction containing %d will follow, thereby undoing the effects of
5377 doing this instruction unconditionally.
5378 If CODE is 'N' then X is a floating point operand that must be negated
5380 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5381 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5384 arm_print_operand (stream, x, code)
5392 fputs (ASM_COMMENT_START, stream);
5396 fputs (REGISTER_PREFIX, stream);
5400 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5401 fputs (arm_condition_codes[arm_current_cc], stream);
5407 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5408 r = REAL_VALUE_NEGATE (r);
5409 fprintf (stream, "%s", fp_const_from_val (&r));
5414 if (GET_CODE (x) == CONST_INT)
5416 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5421 ARM_SIGN_EXTEND (~ INTVAL (x)));
5425 output_addr_const (stream, x);
5430 fprintf (stream, "%s", arithmetic_instr (x, 1));
5434 fprintf (stream, "%s", arithmetic_instr (x, 0));
5440 char *shift = shift_op (x, &val);
5444 fprintf (stream, ", %s ", shift_op (x, &val));
5446 arm_print_operand (stream, XEXP (x, 1), 0);
5449 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5462 fputs (REGISTER_PREFIX, stream);
5463 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
5469 fputs (REGISTER_PREFIX, stream);
5470 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
5474 fputs (REGISTER_PREFIX, stream);
5475 if (GET_CODE (XEXP (x, 0)) == REG)
5476 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
5478 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
5482 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
5483 REGISTER_PREFIX, reg_names[REGNO (x) - 1
5484 + ((GET_MODE_SIZE (GET_MODE (x))
5485 + GET_MODE_SIZE (SImode) - 1)
5486 / GET_MODE_SIZE (SImode))]);
5491 fputs (arm_condition_codes[get_arm_condition_code (x)],
5497 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
5498 (get_arm_condition_code (x))],
5506 if (GET_CODE (x) == REG)
5508 fputs (REGISTER_PREFIX, stream);
5509 fputs (reg_names[REGNO (x)], stream);
5511 else if (GET_CODE (x) == MEM)
5513 output_memory_reference_mode = GET_MODE (x);
5514 output_address (XEXP (x, 0));
5516 else if (GET_CODE (x) == CONST_DOUBLE)
5517 fprintf (stream, "#%s", fp_immediate_constant (x));
5518 else if (GET_CODE (x) == NEG)
5519 abort (); /* This should never happen now. */
5522 fputc ('#', stream);
5523 output_addr_const (stream, x);
5529 /* A finite state machine takes care of noticing whether or not instructions
5530 can be conditionally executed, and thus decrease execution time and code
5531 size by deleting branch instructions. The fsm is controlled by
5532 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
5534 /* The state of the fsm controlling condition codes are:
5535 0: normal, do nothing special
5536 1: make ASM_OUTPUT_OPCODE not output this instruction
5537 2: make ASM_OUTPUT_OPCODE not output this instruction
5538 3: make instructions conditional
5539 4: make instructions conditional
5541 State transitions (state->state by whom under condition):
5542 0 -> 1 final_prescan_insn if the `target' is a label
5543 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
5544 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
5545 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
5546 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
5547 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
5548 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
5549 (the target insn is arm_target_insn).
5551 If the jump clobbers the conditions then we use states 2 and 4.
5553 A similar thing can be done with conditional return insns.
5555 XXX In case the `target' is an unconditional branch, this conditionalising
5556 of the instructions always reduces code size, but not always execution
5557 time. But then, I want to reduce the code size to somewhere near what
5558 /bin/cc produces. */
5560 /* Returns the index of the ARM condition code string in
5561 `arm_condition_codes'. COMPARISON should be an rtx like
5562 `(eq (...) (...))'. */
5564 static enum arm_cond_code
5565 get_arm_condition_code (comparison)
5568 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
5570 register enum rtx_code comp_code = GET_CODE (comparison);
5572 if (GET_MODE_CLASS (mode) != MODE_CC)
5573 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
5574 XEXP (comparison, 1));
5578 case CC_DNEmode: code = ARM_NE; goto dominance;
5579 case CC_DEQmode: code = ARM_EQ; goto dominance;
5580 case CC_DGEmode: code = ARM_GE; goto dominance;
5581 case CC_DGTmode: code = ARM_GT; goto dominance;
5582 case CC_DLEmode: code = ARM_LE; goto dominance;
5583 case CC_DLTmode: code = ARM_LT; goto dominance;
5584 case CC_DGEUmode: code = ARM_CS; goto dominance;
5585 case CC_DGTUmode: code = ARM_HI; goto dominance;
5586 case CC_DLEUmode: code = ARM_LS; goto dominance;
5587 case CC_DLTUmode: code = ARM_CC;
5590 if (comp_code != EQ && comp_code != NE)
5593 if (comp_code == EQ)
5594 return ARM_INVERSE_CONDITION_CODE (code);
5600 case NE: return ARM_NE;
5601 case EQ: return ARM_EQ;
5602 case GE: return ARM_PL;
5603 case LT: return ARM_MI;
5611 case NE: return ARM_NE;
5612 case EQ: return ARM_EQ;
5619 case GE: return ARM_GE;
5620 case GT: return ARM_GT;
5621 case LE: return ARM_LS;
5622 case LT: return ARM_MI;
5629 case NE: return ARM_NE;
5630 case EQ: return ARM_EQ;
5631 case GE: return ARM_LE;
5632 case GT: return ARM_LT;
5633 case LE: return ARM_GE;
5634 case LT: return ARM_GT;
5635 case GEU: return ARM_LS;
5636 case GTU: return ARM_CC;
5637 case LEU: return ARM_CS;
5638 case LTU: return ARM_HI;
5645 case LTU: return ARM_CS;
5646 case GEU: return ARM_CC;
5653 case NE: return ARM_NE;
5654 case EQ: return ARM_EQ;
5655 case GE: return ARM_GE;
5656 case GT: return ARM_GT;
5657 case LE: return ARM_LE;
5658 case LT: return ARM_LT;
5659 case GEU: return ARM_CS;
5660 case GTU: return ARM_HI;
5661 case LEU: return ARM_LS;
5662 case LTU: return ARM_CC;
5674 final_prescan_insn (insn, opvec, noperands)
5679 /* BODY will hold the body of INSN. */
5680 register rtx body = PATTERN (insn);
5682 /* This will be 1 if trying to repeat the trick, and things need to be
5683 reversed if it appears to fail. */
5686 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5687 taken are clobbered, even if the rtl suggests otherwise. It also
5688 means that we have to grub around within the jump expression to find
5689 out what the conditions are when the jump isn't taken. */
5690 int jump_clobbers = 0;
5692 /* If we start with a return insn, we only succeed if we find another one. */
5693 int seeking_return = 0;
5695 /* START_INSN will hold the insn from where we start looking. This is the
5696 first insn after the following code_label if REVERSE is true. */
5697 rtx start_insn = insn;
5699 /* If in state 4, check if the target branch is reached, in order to
5700 change back to state 0. */
5701 if (arm_ccfsm_state == 4)
5703 if (insn == arm_target_insn)
5705 arm_target_insn = NULL;
5706 arm_ccfsm_state = 0;
5711 /* If in state 3, it is possible to repeat the trick, if this insn is an
5712 unconditional branch to a label, and immediately following this branch
5713 is the previous target label which is only used once, and the label this
5714 branch jumps to is not too far off. */
5715 if (arm_ccfsm_state == 3)
5717 if (simplejump_p (insn))
5719 start_insn = next_nonnote_insn (start_insn);
5720 if (GET_CODE (start_insn) == BARRIER)
5722 /* XXX Isn't this always a barrier? */
5723 start_insn = next_nonnote_insn (start_insn);
5725 if (GET_CODE (start_insn) == CODE_LABEL
5726 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5727 && LABEL_NUSES (start_insn) == 1)
5732 else if (GET_CODE (body) == RETURN)
5734 start_insn = next_nonnote_insn (start_insn);
5735 if (GET_CODE (start_insn) == BARRIER)
5736 start_insn = next_nonnote_insn (start_insn);
5737 if (GET_CODE (start_insn) == CODE_LABEL
5738 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5739 && LABEL_NUSES (start_insn) == 1)
5751 if (arm_ccfsm_state != 0 && !reverse)
5753 if (GET_CODE (insn) != JUMP_INSN)
5756 /* This jump might be paralleled with a clobber of the condition codes
5757 the jump should always come first */
5758 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5759 body = XVECEXP (body, 0, 0);
5762 /* If this is a conditional return then we don't want to know */
5763 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5764 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
5765 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
5766 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
5771 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5772 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
5775 int fail = FALSE, succeed = FALSE;
5776 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5777 int then_not_else = TRUE;
5778 rtx this_insn = start_insn, label = 0;
5780 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5782 /* The code below is wrong for these, and I haven't time to
5783 fix it now. So we just do the safe thing and return. This
5784 whole function needs re-writing anyway. */
5789 /* Register the insn jumped to. */
5792 if (!seeking_return)
5793 label = XEXP (SET_SRC (body), 0);
5795 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
5796 label = XEXP (XEXP (SET_SRC (body), 1), 0);
5797 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
5799 label = XEXP (XEXP (SET_SRC (body), 2), 0);
5800 then_not_else = FALSE;
5802 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
5804 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
5807 then_not_else = FALSE;
5812 /* See how many insns this branch skips, and what kind of insns. If all
5813 insns are okay, and the label or unconditional branch to the same
5814 label is not too far away, succeed. */
5815 for (insns_skipped = 0;
5816 !fail && !succeed && insns_skipped++ < MAX_INSNS_SKIPPED;)
5820 this_insn = next_nonnote_insn (this_insn);
5824 switch (GET_CODE (this_insn))
5827 /* Succeed if it is the target label, otherwise fail since
5828 control falls in from somewhere else. */
5829 if (this_insn == label)
5833 arm_ccfsm_state = 2;
5834 this_insn = next_nonnote_insn (this_insn);
5837 arm_ccfsm_state = 1;
5845 /* Succeed if the following insn is the target label.
5847 If return insns are used then the last insn in a function
5848 will be a barrier. */
5849 this_insn = next_nonnote_insn (this_insn);
5850 if (this_insn && this_insn == label)
5854 arm_ccfsm_state = 2;
5855 this_insn = next_nonnote_insn (this_insn);
5858 arm_ccfsm_state = 1;
5866 /* If using 32-bit addresses the cc is not preserved over
5870 /* Succeed if the following insn is the target label,
5871 or if the following two insns are a barrier and
5872 the target label. */
5873 this_insn = next_nonnote_insn (this_insn);
5874 if (this_insn && GET_CODE (this_insn) == BARRIER)
5875 this_insn = next_nonnote_insn (this_insn);
5877 if (this_insn && this_insn == label
5878 && insns_skipped < MAX_INSNS_SKIPPED)
5882 arm_ccfsm_state = 2;
5883 this_insn = next_nonnote_insn (this_insn);
5886 arm_ccfsm_state = 1;
5895 /* If this is an unconditional branch to the same label, succeed.
5896 If it is to another label, do nothing. If it is conditional,
5898 /* XXX Probably, the tests for SET and the PC are unnecessary. */
5900 scanbody = PATTERN (this_insn);
5901 if (GET_CODE (scanbody) == SET
5902 && GET_CODE (SET_DEST (scanbody)) == PC)
5904 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
5905 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
5907 arm_ccfsm_state = 2;
5910 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
5913 else if (GET_CODE (scanbody) == RETURN
5916 arm_ccfsm_state = 2;
5919 else if (GET_CODE (scanbody) == PARALLEL)
5921 switch (get_attr_conds (this_insn))
5933 /* Instructions using or affecting the condition codes make it
5935 scanbody = PATTERN (this_insn);
5936 if ((GET_CODE (scanbody) == SET
5937 || GET_CODE (scanbody) == PARALLEL)
5938 && get_attr_conds (this_insn) != CONDS_NOCOND)
5948 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
5949 arm_target_label = CODE_LABEL_NUMBER (label);
5950 else if (seeking_return || arm_ccfsm_state == 2)
5952 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
5954 this_insn = next_nonnote_insn (this_insn);
5955 if (this_insn && (GET_CODE (this_insn) == BARRIER
5956 || GET_CODE (this_insn) == CODE_LABEL))
5961 /* Oh, dear! we ran off the end.. give up */
5962 recog (PATTERN (insn), insn, NULL_PTR);
5963 arm_ccfsm_state = 0;
5964 arm_target_insn = NULL;
5967 arm_target_insn = this_insn;
5976 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
5978 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
5979 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5980 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
5981 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5985 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
5988 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
5992 if (reverse || then_not_else)
5993 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5995 /* restore recog_operand (getting the attributes of other insns can
5996 destroy this array, but final.c assumes that it remains intact
5997 across this call; since the insn has been recognized already we
5998 call recog direct). */
5999 recog (PATTERN (insn), insn, NULL_PTR);
6003 #ifdef AOF_ASSEMBLER
6004 /* Special functions only needed when producing AOF syntax assembler. */
6006 rtx aof_pic_label = NULL_RTX;
6009 struct pic_chain *next;
6013 static struct pic_chain *aof_pic_chain = NULL;
6019 struct pic_chain **chainp;
6022 if (aof_pic_label == NULL_RTX)
6024 /* This needs to persist throughout the compilation. */
6025 end_temporary_allocation ();
6026 aof_pic_label = gen_rtx (SYMBOL_REF, Pmode, "x$adcons");
6027 resume_temporary_allocation ();
6030 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6031 offset += 4, chainp = &(*chainp)->next)
6032 if ((*chainp)->symname == XSTR (x, 0))
6033 return plus_constant (aof_pic_label, offset);
6035 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6036 (*chainp)->next = NULL;
6037 (*chainp)->symname = XSTR (x, 0);
6038 return plus_constant (aof_pic_label, offset);
6042 aof_dump_pic_table (f)
6045 struct pic_chain *chain;
6047 if (aof_pic_chain == NULL)
6050 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
6051 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
6052 reg_names[PIC_OFFSET_TABLE_REGNUM]);
6053 fputs ("|x$adcons|\n", f);
6055 for (chain = aof_pic_chain; chain; chain = chain->next)
6057 fputs ("\tDCD\t", f);
6058 assemble_name (f, chain->symname);
6063 int arm_text_section_count = 1;
6068 static char buf[100];
6069 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6070 arm_text_section_count++);
6072 strcat (buf, ", PIC, REENTRANT");
6076 static int arm_data_section_count = 1;
6081 static char buf[100];
6082 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6086 /* The AOF assembler is religiously strict about declarations of
6087 imported and exported symbols, so that it is impossible to declare
6088 a function as imported near the beginning of the file, and then to
6089 export it later on. It is, however, possible to delay the decision
6090 until all the functions in the file have been compiled. To get
6091 around this, we maintain a list of the imports and exports, and
6092 delete from it any that are subsequently defined. At the end of
6093 compilation we spit the remainder of the list out before the END
6098 struct import *next;
6102 static struct import *imports_list = NULL;
6105 aof_add_import (name)
6110 for (new = imports_list; new; new = new->next)
6111 if (new->name == name)
6114 new = (struct import *) xmalloc (sizeof (struct import));
6115 new->next = imports_list;
6121 aof_delete_import (name)
6124 struct import **old;
6126 for (old = &imports_list; *old; old = & (*old)->next)
6128 if ((*old)->name == name)
6130 *old = (*old)->next;
6136 int arm_main_function = 0;
6139 aof_dump_imports (f)
6142 /* The AOF assembler needs this to cause the startup code to be extracted
6143 from the library. Brining in __main causes the whole thing to work
6145 if (arm_main_function)
6148 fputs ("\tIMPORT __main\n", f);
6149 fputs ("\tDCD __main\n", f);
6152 /* Now dump the remaining imports. */
6153 while (imports_list)
6155 fprintf (f, "\tIMPORT\t");
6156 assemble_name (f, imports_list->name);
6158 imports_list = imports_list->next;
6161 #endif /* AOF_ASSEMBLER */