1 /* Output routines for GCC for ARM/RISCiX.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 #define MAX_INSNS_SKIPPED 5
46 /* Some function declarations. */
47 extern FILE *asm_out_file;
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char *output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char *fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char *shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
72 /* Define the information needed to generate branch insns. This is
73 stored from the compare operation. */
75 rtx arm_compare_op0, arm_compare_op1;
78 /* What type of cpu are we compiling for? */
79 enum processor_type arm_cpu;
81 /* What type of floating point are we tuning for? */
82 enum floating_point_type arm_fpu;
84 /* What type of floating point instructions are available? */
85 enum floating_point_type arm_fpu_arch;
87 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
88 enum prog_mode_type arm_prgmode;
90 /* Set by the -mfp=... option */
91 char *target_fp_name = NULL;
93 /* Nonzero if this is an "M" variant of the processor. */
94 int arm_fast_multiply = 0;
96 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
99 /* Set to the features we should tune the code for (multiply speed etc). */
102 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
103 must report the mode of the memory reference from PRINT_OPERAND to
104 PRINT_OPERAND_ADDRESS. */
105 enum machine_mode output_memory_reference_mode;
107 /* Nonzero if the prologue must setup `fp'. */
108 int current_function_anonymous_args;
110 /* The register number to be used for the PIC offset register. */
111 int arm_pic_register = 9;
113 /* Location counter of .text segment. */
114 int arm_text_location = 0;
116 /* Set to one if we think that lr is only saved because of subroutine calls,
117 but all of these can be `put after' return insns */
118 int lr_save_eliminated;
120 /* Set to 1 when a return insn is output, this means that the epilogue
123 static int return_used_this_function;
125 static int arm_constant_limit = 3;
127 /* For an explanation of these variables, see final_prescan_insn below. */
129 enum arm_cond_code arm_current_cc;
131 int arm_target_label;
133 /* The condition codes of the ARM, and the inverse function. */
134 char *arm_condition_codes[] =
136 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
137 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
140 static enum arm_cond_code get_arm_condition_code ();
143 /* Initialization code */
145 struct arm_cpu_select arm_select[4] =
147 /* switch name, tune arch */
148 { (char *)0, "--with-cpu=", 1, 1 },
149 { (char *)0, "-mcpu=", 1, 1 },
150 { (char *)0, "-march=", 0, 1 },
151 { (char *)0, "-mtune=", 1, 0 },
154 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
155 #define FL_FAST_MULT 0x02 /* Fast multiply */
156 #define FL_MODE26 0x04 /* 26-bit mode support */
157 #define FL_MODE32 0x08 /* 32-bit mode support */
158 #define FL_ARCH4 0x10 /* Architecture rel 4 */
159 #define FL_THUMB 0x20 /* Thumb aware */
164 enum processor_type type;
168 /* Not all of these give usefully different compilation alternatives,
169 but there is no simple way of generalizing them. */
170 static struct processors all_procs[] =
172 {"arm2", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
173 {"arm250", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
174 {"arm3", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
175 {"arm6", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
176 {"arm600", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
177 {"arm610", PROCESSOR_ARM6, FL_MODE32 | FL_MODE26},
178 {"arm7", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
179 /* arm7m doesn't exist on its own, only in conjunction with D, (and I), but
180 those don't alter the code, so it is sometimes known as the arm7m */
181 {"arm7m", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
183 {"arm7dm", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
185 {"arm7dmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
187 {"arm700", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
188 {"arm710", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
189 {"arm7100", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
190 {"arm7500", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
191 /* Doesn't really have an external co-proc, but does have embedded fpu */
192 {"arm7500fe", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
193 {"arm7tdmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
194 | FL_ARCH4 | FL_THUMB)},
195 {"arm8", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
197 {"arm810", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
199 {"strongarm", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
201 {"strongarm110", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
203 {"armv2", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
204 {"armv2a", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
205 {"armv3", PROCESSOR_NONE, FL_CO_PROC | FL_MODE32 | FL_MODE26},
206 {"armv3m", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
208 {"armv4", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
209 | FL_MODE26 | FL_ARCH4)},
210 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
211 implementations that support it, so we will leave it out for now. */
212 {"armv4t", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
217 /* Fix up any incompatible options that the user has specified.
218 This has now turned into a maze. */
220 arm_override_options ()
222 int arm_thumb_aware = 0;
225 struct arm_cpu_select * ptr;
226 static struct cpu_default
233 { TARGET_CPU_arm2, "arm2" },
234 { TARGET_CPU_arm6, "arm6" },
235 { TARGET_CPU_arm610, "arm610" },
236 { TARGET_CPU_arm7dm, "arm7dm" },
237 { TARGET_CPU_arm7500fe, "arm7500fe" },
238 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
239 { TARGET_CPU_arm8, "arm8" },
240 { TARGET_CPU_arm810, "arm810" },
241 { TARGET_CPU_strongarm, "strongarm" },
244 struct cpu_default *def;
246 /* Set the default. */
247 for (def = &cpu_defaults[0]; def->name; ++def)
248 if (def->cpu == TARGET_CPU_DEFAULT)
253 arm_select[0].string = def->name;
255 for (i = 0; i < sizeof (arm_select) / sizeof (arm_select[0]); i++)
257 ptr = &arm_select[i];
258 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
260 struct processors *sel;
262 for (sel = all_procs; sel->name != NULL; sel++)
263 if (! strcmp (ptr->string, sel->name))
265 /* -march= is the only flag that can take an architecture
266 type, so if we match when the tune bit is set, the
267 option was invalid. */
270 if (sel->type == PROCESSOR_NONE)
271 continue; /* Its an architecture, not a cpu */
274 tune_flags = sel->flags;
283 if (sel->name == NULL)
284 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
288 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
289 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
291 if (TARGET_POKE_FUNCTION_NAME)
292 target_flags |= ARM_FLAG_APCS_FRAME;
295 warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
298 warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
300 if (TARGET_APCS_REENT && flag_pic)
301 fatal ("-fpic and -mapcs-reent are incompatible");
303 if (TARGET_APCS_REENT)
304 warning ("APCS reentrant code not supported.");
306 /* If stack checking is disabled, we can use r10 as the PIC register,
307 which keeps r9 available. */
308 if (flag_pic && ! TARGET_APCS_STACK)
309 arm_pic_register = 10;
311 /* Well, I'm about to have a go, but pic is NOT going to be compatible
312 with APCS reentrancy, since that requires too much support in the
313 assembler and linker, and the ARMASM assembler seems to lack some
314 required directives. */
316 warning ("Position independent code not supported");
318 if (TARGET_APCS_FLOAT)
319 warning ("Passing floating point arguments in fp regs not yet supported");
321 if (TARGET_APCS_STACK && ! TARGET_APCS)
323 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
324 target_flags |= ARM_FLAG_APCS_FRAME;
327 /* Default is to tune for an FPA */
330 /* Default value for floating point code... if no co-processor
331 bus, then schedule for emulated floating point. Otherwise,
332 assume the user has an FPA.
333 Note: this does not prevent use of floating point instructions,
334 -msoft-float does that. */
335 if ((tune_flags & FL_CO_PROC) == 0)
338 arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
339 arm_arch4 = (flags & FL_ARCH4) != 0;
340 arm_thumb_aware = (flags & FL_THUMB) != 0;
344 if (strcmp (target_fp_name, "2") == 0)
345 arm_fpu_arch = FP_SOFT2;
346 else if (strcmp (target_fp_name, "3") == 0)
347 arm_fpu_arch = FP_HARD;
349 fatal ("Invalid floating point emulation option: -mfpe=%s",
353 arm_fpu_arch = FP_DEFAULT;
355 if (TARGET_THUMB_INTERWORK && ! arm_thumb_aware)
357 warning ("This processor variant does not support Thumb interworking");
358 target_flags &= ~ARM_FLAG_THUMB;
361 if (TARGET_FPE && arm_fpu != FP_HARD)
364 /* For arm2/3 there is no need to do any scheduling if there is only
365 a floating point emulator, or we are doing software floating-point. */
366 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && arm_cpu == PROCESSOR_ARM2)
367 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
369 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
373 /* Return 1 if it is possible to return using a single instruction */
380 if (!reload_completed ||current_function_pretend_args_size
381 || current_function_anonymous_args
382 || ((get_frame_size () + current_function_outgoing_args_size != 0)
383 && !(TARGET_APCS || frame_pointer_needed)))
386 /* Can't be done if interworking with Thumb, and any registers have been
388 if (TARGET_THUMB_INTERWORK)
389 for (regno = 0; regno < 16; regno++)
390 if (regs_ever_live[regno] && ! call_used_regs[regno])
393 /* Can't be done if any of the FPU regs are pushed, since this also
395 for (regno = 16; regno < 24; regno++)
396 if (regs_ever_live[regno] && ! call_used_regs[regno])
399 /* If a function is naked, don't use the "return" insn. */
400 if (arm_naked_function_p (current_function_decl))
406 /* Return TRUE if int I is a valid immediate ARM constant. */
412 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
414 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
415 be all zero, or all one. */
416 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
417 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
418 != ((~(unsigned HOST_WIDE_INT) 0)
419 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
422 /* Fast return for 0 and powers of 2 */
423 if ((i & (i - 1)) == 0)
428 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
431 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
432 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
433 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
438 /* Return true if I is a valid constant for the operation CODE. */
440 const_ok_for_op (i, code, mode)
443 enum machine_mode mode;
445 if (const_ok_for_arm (i))
451 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
453 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
459 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
466 /* Emit a sequence of insns to handle a large constant.
467 CODE is the code of the operation required, it can be any of SET, PLUS,
468 IOR, AND, XOR, MINUS;
469 MODE is the mode in which the operation is being performed;
470 VAL is the integer to operate on;
471 SOURCE is the other operand (a register, or a null-pointer for SET);
472 SUBTARGETS means it is safe to create scratch registers if that will
473 either produce a simpler sequence, or we will want to cse the values.
474 Return value is the number of insns emitted. */
477 arm_split_constant (code, mode, val, target, source, subtargets)
479 enum machine_mode mode;
485 if (subtargets || code == SET
486 || (GET_CODE (target) == REG && GET_CODE (source) == REG
487 && REGNO (target) != REGNO (source)))
489 if (arm_gen_constant (code, mode, val, target, source, 1, 0)
490 > arm_constant_limit + (code != SET))
494 /* Currently SET is the only monadic value for CODE, all
495 the rest are diadic. */
496 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (val)));
501 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
503 emit_insn (gen_rtx (SET, VOIDmode, temp, GEN_INT (val)));
504 /* For MINUS, the value is subtracted from, since we never
505 have subtraction of a constant. */
507 emit_insn (gen_rtx (SET, VOIDmode, target,
508 gen_rtx (code, mode, temp, source)));
510 emit_insn (gen_rtx (SET, VOIDmode, target,
511 gen_rtx (code, mode, source, temp)));
517 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
520 /* As above, but extra parameter GENERATE which, if clear, suppresses
523 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
525 enum machine_mode mode;
534 int can_negate_initial = 0;
537 int num_bits_set = 0;
538 int set_sign_bit_copies = 0;
539 int clear_sign_bit_copies = 0;
540 int clear_zero_bit_copies = 0;
541 int set_zero_bit_copies = 0;
543 unsigned HOST_WIDE_INT temp1, temp2;
544 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
546 /* find out which operations are safe for a given CODE. Also do a quick
547 check for degenerate cases; these can occur when DImode operations
559 can_negate_initial = 1;
563 if (remainder == 0xffffffff)
566 emit_insn (gen_rtx (SET, VOIDmode, target,
567 GEN_INT (ARM_SIGN_EXTEND (val))));
572 if (reload_completed && rtx_equal_p (target, source))
575 emit_insn (gen_rtx (SET, VOIDmode, target, source));
584 emit_insn (gen_rtx (SET, VOIDmode, target, const0_rtx));
587 if (remainder == 0xffffffff)
589 if (reload_completed && rtx_equal_p (target, source))
592 emit_insn (gen_rtx (SET, VOIDmode, target, source));
601 if (reload_completed && rtx_equal_p (target, source))
604 emit_insn (gen_rtx (SET, VOIDmode, target, source));
607 if (remainder == 0xffffffff)
610 emit_insn (gen_rtx (SET, VOIDmode, target,
611 gen_rtx (NOT, mode, source)));
615 /* We don't know how to handle this yet below. */
619 /* We treat MINUS as (val - source), since (source - val) is always
620 passed as (source + (-val)). */
624 emit_insn (gen_rtx (SET, VOIDmode, target,
625 gen_rtx (NEG, mode, source)));
628 if (const_ok_for_arm (val))
631 emit_insn (gen_rtx (SET, VOIDmode, target,
632 gen_rtx (MINUS, mode, GEN_INT (val), source)));
643 /* If we can do it in one insn get out quickly */
644 if (const_ok_for_arm (val)
645 || (can_negate_initial && const_ok_for_arm (-val))
646 || (can_invert && const_ok_for_arm (~val)))
649 emit_insn (gen_rtx (SET, VOIDmode, target,
650 (source ? gen_rtx (code, mode, source,
657 /* Calculate a few attributes that may be useful for specific
660 for (i = 31; i >= 0; i--)
662 if ((remainder & (1 << i)) == 0)
663 clear_sign_bit_copies++;
668 for (i = 31; i >= 0; i--)
670 if ((remainder & (1 << i)) != 0)
671 set_sign_bit_copies++;
676 for (i = 0; i <= 31; i++)
678 if ((remainder & (1 << i)) == 0)
679 clear_zero_bit_copies++;
684 for (i = 0; i <= 31; i++)
686 if ((remainder & (1 << i)) != 0)
687 set_zero_bit_copies++;
695 /* See if we can do this by sign_extending a constant that is known
696 to be negative. This is a good, way of doing it, since the shift
697 may well merge into a subsequent insn. */
698 if (set_sign_bit_copies > 1)
701 (temp1 = ARM_SIGN_EXTEND (remainder
702 << (set_sign_bit_copies - 1))))
706 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
707 emit_insn (gen_rtx (SET, VOIDmode, new_src,
709 emit_insn (gen_ashrsi3 (target, new_src,
710 GEN_INT (set_sign_bit_copies - 1)));
714 /* For an inverted constant, we will need to set the low bits,
715 these will be shifted out of harm's way. */
716 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
717 if (const_ok_for_arm (~temp1))
721 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
722 emit_insn (gen_rtx (SET, VOIDmode, new_src,
724 emit_insn (gen_ashrsi3 (target, new_src,
725 GEN_INT (set_sign_bit_copies - 1)));
731 /* See if we can generate this by setting the bottom (or the top)
732 16 bits, and then shifting these into the other half of the
733 word. We only look for the simplest cases, to do more would cost
734 too much. Be careful, however, not to generate this when the
735 alternative would take fewer insns. */
736 if (val & 0xffff0000)
738 temp1 = remainder & 0xffff0000;
739 temp2 = remainder & 0x0000ffff;
741 /* Overlaps outside this range are best done using other methods. */
742 for (i = 9; i < 24; i++)
744 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
745 && ! const_ok_for_arm (temp2))
747 rtx new_src = (subtargets
748 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
750 insns = arm_gen_constant (code, mode, temp2, new_src,
751 source, subtargets, generate);
754 emit_insn (gen_rtx (SET, VOIDmode, target,
756 gen_rtx (ASHIFT, mode, source,
763 /* Don't duplicate cases already considered. */
764 for (i = 17; i < 24; i++)
766 if (((temp1 | (temp1 >> i)) == remainder)
767 && ! const_ok_for_arm (temp1))
769 rtx new_src = (subtargets
770 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
772 insns = arm_gen_constant (code, mode, temp1, new_src,
773 source, subtargets, generate);
776 emit_insn (gen_rtx (SET, VOIDmode, target,
778 gen_rtx (LSHIFTRT, mode,
779 source, GEN_INT (i)),
789 /* If we have IOR or XOR, and the constant can be loaded in a
790 single instruction, and we can find a temporary to put it in,
791 then this can be done in two instructions instead of 3-4. */
793 /* TARGET can't be NULL if SUBTARGETS is 0 */
794 || (reload_completed && ! reg_mentioned_p (target, source)))
796 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
800 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
802 emit_insn (gen_rtx (SET, VOIDmode, sub, GEN_INT (val)));
803 emit_insn (gen_rtx (SET, VOIDmode, target,
804 gen_rtx (code, mode, source, sub)));
813 if (set_sign_bit_copies > 8
814 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
818 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
819 rtx shift = GEN_INT (set_sign_bit_copies);
821 emit_insn (gen_rtx (SET, VOIDmode, sub,
823 gen_rtx (ASHIFT, mode, source,
825 emit_insn (gen_rtx (SET, VOIDmode, target,
827 gen_rtx (LSHIFTRT, mode, sub,
833 if (set_zero_bit_copies > 8
834 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
838 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
839 rtx shift = GEN_INT (set_zero_bit_copies);
841 emit_insn (gen_rtx (SET, VOIDmode, sub,
843 gen_rtx (LSHIFTRT, mode, source,
845 emit_insn (gen_rtx (SET, VOIDmode, target,
847 gen_rtx (ASHIFT, mode, sub,
853 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
857 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
858 emit_insn (gen_rtx (SET, VOIDmode, sub,
859 gen_rtx (NOT, mode, source)));
862 sub = gen_reg_rtx (mode);
863 emit_insn (gen_rtx (SET, VOIDmode, sub,
864 gen_rtx (AND, mode, source,
866 emit_insn (gen_rtx (SET, VOIDmode, target,
867 gen_rtx (NOT, mode, sub)));
874 /* See if two shifts will do 2 or more insn's worth of work. */
875 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
877 HOST_WIDE_INT shift_mask = ((0xffffffff
878 << (32 - clear_sign_bit_copies))
881 if ((remainder | shift_mask) != 0xffffffff)
885 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
886 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
887 new_src, source, subtargets, 1);
892 rtx targ = subtargets ? NULL_RTX : target;
893 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
894 targ, source, subtargets, 0);
900 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
901 rtx shift = GEN_INT (clear_sign_bit_copies);
903 emit_insn (gen_ashlsi3 (new_src, source, shift));
904 emit_insn (gen_lshrsi3 (target, new_src, shift));
910 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
912 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
914 if ((remainder | shift_mask) != 0xffffffff)
918 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
920 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
921 new_src, source, subtargets, 1);
926 rtx targ = subtargets ? NULL_RTX : target;
928 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
929 targ, source, subtargets, 0);
935 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
936 rtx shift = GEN_INT (clear_zero_bit_copies);
938 emit_insn (gen_lshrsi3 (new_src, source, shift));
939 emit_insn (gen_ashlsi3 (target, new_src, shift));
951 for (i = 0; i < 32; i++)
952 if (remainder & (1 << i))
955 if (code == AND || (can_invert && num_bits_set > 16))
956 remainder = (~remainder) & 0xffffffff;
957 else if (code == PLUS && num_bits_set > 16)
958 remainder = (-remainder) & 0xffffffff;
965 /* Now try and find a way of doing the job in either two or three
967 We start by looking for the largest block of zeros that are aligned on
968 a 2-bit boundary, we then fill up the temps, wrapping around to the
969 top of the word when we drop off the bottom.
970 In the worst case this code should produce no more than four insns. */
973 int best_consecutive_zeros = 0;
975 for (i = 0; i < 32; i += 2)
977 int consecutive_zeros = 0;
979 if (! (remainder & (3 << i)))
981 while ((i < 32) && ! (remainder & (3 << i)))
983 consecutive_zeros += 2;
986 if (consecutive_zeros > best_consecutive_zeros)
988 best_consecutive_zeros = consecutive_zeros;
989 best_start = i - consecutive_zeros;
995 /* Now start emitting the insns, starting with the one with the highest
996 bit set: we do this so that the smallest number will be emitted last;
997 this is more likely to be combinable with addressing insns. */
1005 if (remainder & (3 << (i - 2)))
1010 temp1 = remainder & ((0x0ff << end)
1011 | ((i < end) ? (0xff >> (32 - end)) : 0));
1012 remainder &= ~temp1;
1019 emit_insn (gen_rtx (SET, VOIDmode,
1020 new_src = (subtargets
1021 ? gen_reg_rtx (mode)
1023 GEN_INT (can_invert ? ~temp1 : temp1)));
1024 else if (code == MINUS)
1025 emit_insn (gen_rtx (SET, VOIDmode,
1026 new_src = (subtargets
1027 ? gen_reg_rtx (mode)
1029 gen_rtx (code, mode, GEN_INT (temp1),
1032 emit_insn (gen_rtx (SET, VOIDmode,
1033 new_src = (remainder
1035 ? gen_reg_rtx (mode)
1038 gen_rtx (code, mode, source,
1039 GEN_INT (can_invert ? ~temp1
1051 else if (code == MINUS)
1058 } while (remainder);
1063 /* Canonicalize a comparison so that we are more likely to recognize it.
1064 This can be done for a few constant compares, where we can make the
1065 immediate value easier to load. */
1067 arm_canonicalize_comparison (code, op1)
1071 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1081 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1083 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1085 *op1 = GEN_INT (i+1);
1086 return code == GT ? GE : LT;
1092 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1093 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1095 *op1 = GEN_INT (i-1);
1096 return code == GE ? GT : LE;
1102 if (i != ~((unsigned HOST_WIDE_INT) 0)
1103 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1105 *op1 = GEN_INT (i + 1);
1106 return code == GTU ? GEU : LTU;
1113 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1115 *op1 = GEN_INT (i - 1);
1116 return code == GEU ? GTU : LEU;
1128 /* Handle aggregates that are not laid out in a BLKmode element.
1129 This is a sub-element of RETURN_IN_MEMORY. */
1131 arm_return_in_memory (type)
1134 if (TREE_CODE (type) == RECORD_TYPE)
1138 /* For a struct, we can return in a register if every element was a
1140 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1141 if (TREE_CODE (field) != FIELD_DECL
1142 || ! DECL_BIT_FIELD_TYPE (field))
1147 else if (TREE_CODE (type) == UNION_TYPE)
1151 /* Unions can be returned in registers if every element is
1152 integral, or can be returned in an integer register. */
1153 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1155 if (TREE_CODE (field) != FIELD_DECL
1156 || (AGGREGATE_TYPE_P (TREE_TYPE (field))
1157 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1158 || FLOAT_TYPE_P (TREE_TYPE (field)))
1163 /* XXX Not sure what should be done for other aggregates, so put them in
1169 legitimate_pic_operand_p (x)
1172 if (CONSTANT_P (x) && flag_pic
1173 && (GET_CODE (x) == SYMBOL_REF
1174 || (GET_CODE (x) == CONST
1175 && GET_CODE (XEXP (x, 0)) == PLUS
1176 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1183 legitimize_pic_address (orig, mode, reg)
1185 enum machine_mode mode;
1188 if (GET_CODE (orig) == SYMBOL_REF)
1190 rtx pic_ref, address;
1196 if (reload_in_progress || reload_completed)
1199 reg = gen_reg_rtx (Pmode);
1204 #ifdef AOF_ASSEMBLER
1205 /* The AOF assembler can generate relocations for these directly, and
1206 understands that the PIC register has to be added into the offset.
1208 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1211 address = gen_reg_rtx (Pmode);
1215 emit_insn (gen_pic_load_addr (address, orig));
1217 pic_ref = gen_rtx (MEM, Pmode,
1218 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, address));
1219 RTX_UNCHANGING_P (pic_ref) = 1;
1220 insn = emit_move_insn (reg, pic_ref);
1222 current_function_uses_pic_offset_table = 1;
1223 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1225 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1229 else if (GET_CODE (orig) == CONST)
1233 if (GET_CODE (XEXP (orig, 0)) == PLUS
1234 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1239 if (reload_in_progress || reload_completed)
1242 reg = gen_reg_rtx (Pmode);
1245 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1247 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1248 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1249 base == reg ? 0 : reg);
1254 if (GET_CODE (offset) == CONST_INT)
1256 /* The base register doesn't really matter, we only want to
1257 test the index for the appropriate mode. */
1258 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1260 if (! reload_in_progress && ! reload_completed)
1261 offset = force_reg (Pmode, offset);
1266 if (GET_CODE (offset) == CONST_INT)
1267 return plus_constant_for_output (base, INTVAL (offset));
1270 if (GET_MODE_SIZE (mode) > 4
1271 && (GET_MODE_CLASS (mode) == MODE_INT
1272 || TARGET_SOFT_FLOAT))
1274 emit_insn (gen_addsi3 (reg, base, offset));
1278 return gen_rtx (PLUS, Pmode, base, offset);
1280 else if (GET_CODE (orig) == LABEL_REF)
1281 current_function_uses_pic_offset_table = 1;
1300 #ifndef AOF_ASSEMBLER
1301 rtx l1, pic_tmp, pic_tmp2, seq;
1302 rtx global_offset_table;
1304 if (current_function_uses_pic_offset_table == 0)
1311 l1 = gen_label_rtx ();
1313 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1314 /* The PC contains 'dot'+8, but the label L1 is on the next
1315 instruction, so the offset is only 'dot'+4. */
1316 pic_tmp = gen_rtx (CONST, VOIDmode,
1317 gen_rtx (PLUS, Pmode,
1318 gen_rtx (LABEL_REF, VOIDmode, l1),
1320 pic_tmp2 = gen_rtx (CONST, VOIDmode,
1321 gen_rtx (PLUS, Pmode,
1322 global_offset_table,
1325 pic_rtx = gen_rtx (CONST, Pmode,
1326 gen_rtx (MINUS, Pmode, pic_tmp2, pic_tmp));
1328 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1329 emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx));
1332 seq = gen_sequence ();
1334 emit_insn_after (seq, get_insns ());
1336 /* Need to emit this whether or not we obey regdecls,
1337 since setjmp/longjmp can cause life info to screw up. */
1338 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1339 #endif /* AOF_ASSEMBLER */
1342 #define REG_OR_SUBREG_REG(X) \
1343 (GET_CODE (X) == REG \
1344 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1346 #define REG_OR_SUBREG_RTX(X) \
1347 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1349 #define ARM_FRAME_RTX(X) \
1350 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1351 || (X) == arg_pointer_rtx)
1354 arm_rtx_costs (x, code, outer_code)
1356 enum rtx_code code, outer_code;
1358 enum machine_mode mode = GET_MODE (x);
1359 enum rtx_code subcode;
1365 /* Memory costs quite a lot for the first word, but subsequent words
1366 load at the equivalent of a single insn each. */
1367 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1368 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1375 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1382 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1384 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1385 + ((GET_CODE (XEXP (x, 0)) == REG
1386 || (GET_CODE (XEXP (x, 0)) == SUBREG
1387 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1389 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1390 || (GET_CODE (XEXP (x, 0)) == SUBREG
1391 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1393 + ((GET_CODE (XEXP (x, 1)) == REG
1394 || (GET_CODE (XEXP (x, 1)) == SUBREG
1395 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1396 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1401 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1402 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1403 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1404 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1407 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1408 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1409 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1410 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1412 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1413 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1414 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1417 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1418 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1419 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1420 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1421 || subcode == ASHIFTRT || subcode == LSHIFTRT
1422 || subcode == ROTATE || subcode == ROTATERT
1424 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1425 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1426 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1427 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1428 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1429 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1430 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1435 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1436 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1437 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1438 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1439 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1443 case AND: case XOR: case IOR:
1446 /* Normally the frame registers will be spilt into reg+const during
1447 reload, so it is a bad idea to combine them with other instructions,
1448 since then they might not be moved outside of loops. As a compromise
1449 we allow integration with ops that have a constant as their second
1451 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1452 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1453 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1454 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1455 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1459 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1460 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1461 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1462 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1465 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1466 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1467 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1468 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1469 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1472 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1473 return (1 + extra_cost
1474 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1475 || subcode == LSHIFTRT || subcode == ASHIFTRT
1476 || subcode == ROTATE || subcode == ROTATERT
1478 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1479 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1480 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1481 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1482 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1483 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1489 /* There is no point basing this on the tuning, since it is always the
1490 fast variant if it exists at all */
1491 if (arm_fast_multiply && mode == DImode
1492 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1493 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1494 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1497 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1501 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1503 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1504 & (unsigned HOST_WIDE_INT) 0xffffffff);
1505 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1507 /* Tune as appropriate */
1508 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1510 for (j = 0; i && j < 32; j += booth_unit_size)
1512 i >>= booth_unit_size;
1519 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1520 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1521 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1524 if (arm_fast_multiply && mode == SImode
1525 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1526 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1527 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1528 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1529 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1530 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1535 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1536 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1540 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1542 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1545 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1553 return 4 + (mode == DImode ? 4 : 0);
1556 if (GET_MODE (XEXP (x, 0)) == QImode)
1557 return (4 + (mode == DImode ? 4 : 0)
1558 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1561 switch (GET_MODE (XEXP (x, 0)))
1564 return (1 + (mode == DImode ? 4 : 0)
1565 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1568 return (4 + (mode == DImode ? 4 : 0)
1569 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1572 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1585 arm_adjust_cost (insn, link, dep, cost)
1593 if ((i_pat = single_set (insn)) != NULL
1594 && GET_CODE (SET_SRC (i_pat)) == MEM
1595 && (d_pat = single_set (dep)) != NULL
1596 && GET_CODE (SET_DEST (d_pat)) == MEM)
1598 /* This is a load after a store, there is no conflict if the load reads
1599 from a cached area. Assume that loads from the stack, and from the
1600 constant pool are cached, and that others will miss. This is a
1603 /* debug_rtx (insn);
1606 fprintf (stderr, "costs %d\n", cost); */
1608 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1609 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1610 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1611 || reg_mentioned_p (hard_frame_pointer_rtx,
1612 XEXP (SET_SRC (i_pat), 0)))
1614 /* fprintf (stderr, "***** Now 1\n"); */
1622 /* This code has been fixed for cross compilation. */
1624 static int fpa_consts_inited = 0;
1626 char *strings_fpa[8] = {
1628 "4", "5", "0.5", "10"
1631 static REAL_VALUE_TYPE values_fpa[8];
1639 for (i = 0; i < 8; i++)
1641 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1645 fpa_consts_inited = 1;
1648 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1651 const_double_rtx_ok_for_fpu (x)
1657 if (!fpa_consts_inited)
1660 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1661 if (REAL_VALUE_MINUS_ZERO (r))
1664 for (i = 0; i < 8; i++)
1665 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1671 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1674 neg_const_double_rtx_ok_for_fpu (x)
1680 if (!fpa_consts_inited)
1683 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1684 r = REAL_VALUE_NEGATE (r);
1685 if (REAL_VALUE_MINUS_ZERO (r))
1688 for (i = 0; i < 8; i++)
1689 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1695 /* Predicates for `match_operand' and `match_operator'. */
1697 /* s_register_operand is the same as register_operand, but it doesn't accept
1700 This function exists because at the time it was put in it led to better
1701 code. SUBREG(MEM) always needs a reload in the places where
1702 s_register_operand is used, and this seemed to lead to excessive
1706 s_register_operand (op, mode)
1708 enum machine_mode mode;
1710 if (GET_MODE (op) != mode && mode != VOIDmode)
1713 if (GET_CODE (op) == SUBREG)
1714 op = SUBREG_REG (op);
1716 /* We don't consider registers whose class is NO_REGS
1717 to be a register operand. */
1718 return (GET_CODE (op) == REG
1719 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1720 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1723 /* Only accept reg, subreg(reg), const_int. */
1726 reg_or_int_operand (op, mode)
1728 enum machine_mode mode;
1730 if (GET_CODE (op) == CONST_INT)
1733 if (GET_MODE (op) != mode && mode != VOIDmode)
1736 if (GET_CODE (op) == SUBREG)
1737 op = SUBREG_REG (op);
1739 /* We don't consider registers whose class is NO_REGS
1740 to be a register operand. */
1741 return (GET_CODE (op) == REG
1742 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1743 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1746 /* Return 1 if OP is an item in memory, given that we are in reload. */
1749 reload_memory_operand (op, mode)
1751 enum machine_mode mode;
1753 int regno = true_regnum (op);
1755 return (! CONSTANT_P (op)
1757 || (GET_CODE (op) == REG
1758 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1761 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
1762 memory access (architecture V4) */
1764 bad_signed_byte_operand (op, mode)
1766 enum machine_mode mode;
1768 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
1773 /* A sum of anything more complex than reg + reg or reg + const is bad */
1774 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
1775 && (! s_register_operand (XEXP (op, 0), VOIDmode)
1776 || (! s_register_operand (XEXP (op, 1), VOIDmode)
1777 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
1780 /* Big constants are also bad */
1781 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
1782 && (INTVAL (XEXP (op, 1)) > 0xff
1783 || -INTVAL (XEXP (op, 1)) > 0xff))
1786 /* Everything else is good, or can will automatically be made so. */
1790 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1793 arm_rhs_operand (op, mode)
1795 enum machine_mode mode;
1797 return (s_register_operand (op, mode)
1798 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
1801 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1805 arm_rhsm_operand (op, mode)
1807 enum machine_mode mode;
1809 return (s_register_operand (op, mode)
1810 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
1811 || memory_operand (op, mode));
1814 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1815 constant that is valid when negated. */
1818 arm_add_operand (op, mode)
1820 enum machine_mode mode;
1822 return (s_register_operand (op, mode)
1823 || (GET_CODE (op) == CONST_INT
1824 && (const_ok_for_arm (INTVAL (op))
1825 || const_ok_for_arm (-INTVAL (op)))));
1829 arm_not_operand (op, mode)
1831 enum machine_mode mode;
1833 return (s_register_operand (op, mode)
1834 || (GET_CODE (op) == CONST_INT
1835 && (const_ok_for_arm (INTVAL (op))
1836 || const_ok_for_arm (~INTVAL (op)))));
1839 /* Return TRUE if the operand is a memory reference which contains an
1840 offsettable address. */
1842 offsettable_memory_operand (op, mode)
1844 enum machine_mode mode;
1846 if (mode == VOIDmode)
1847 mode = GET_MODE (op);
1849 return (mode == GET_MODE (op)
1850 && GET_CODE (op) == MEM
1851 && offsettable_address_p (reload_completed | reload_in_progress,
1852 mode, XEXP (op, 0)));
1855 /* Return TRUE if the operand is a memory reference which is, or can be
1856 made word aligned by adjusting the offset. */
1858 alignable_memory_operand (op, mode)
1860 enum machine_mode mode;
1864 if (mode == VOIDmode)
1865 mode = GET_MODE (op);
1867 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
1872 return ((GET_CODE (reg = op) == REG
1873 || (GET_CODE (op) == SUBREG
1874 && GET_CODE (reg = SUBREG_REG (op)) == REG)
1875 || (GET_CODE (op) == PLUS
1876 && GET_CODE (XEXP (op, 1)) == CONST_INT
1877 && (GET_CODE (reg = XEXP (op, 0)) == REG
1878 || (GET_CODE (XEXP (op, 0)) == SUBREG
1879 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
1880 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
1883 /* Similar to s_register_operand, but does not allow hard integer
1886 f_register_operand (op, mode)
1888 enum machine_mode mode;
1890 if (GET_MODE (op) != mode && mode != VOIDmode)
1893 if (GET_CODE (op) == SUBREG)
1894 op = SUBREG_REG (op);
1896 /* We don't consider registers whose class is NO_REGS
1897 to be a register operand. */
1898 return (GET_CODE (op) == REG
1899 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1900 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
1903 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
1906 fpu_rhs_operand (op, mode)
1908 enum machine_mode mode;
1910 if (s_register_operand (op, mode))
1912 else if (GET_CODE (op) == CONST_DOUBLE)
1913 return (const_double_rtx_ok_for_fpu (op));
1919 fpu_add_operand (op, mode)
1921 enum machine_mode mode;
1923 if (s_register_operand (op, mode))
1925 else if (GET_CODE (op) == CONST_DOUBLE)
1926 return (const_double_rtx_ok_for_fpu (op)
1927 || neg_const_double_rtx_ok_for_fpu (op));
1932 /* Return nonzero if OP is a constant power of two. */
1935 power_of_two_operand (op, mode)
1937 enum machine_mode mode;
1939 if (GET_CODE (op) == CONST_INT)
1941 HOST_WIDE_INT value = INTVAL(op);
1942 return value != 0 && (value & (value - 1)) == 0;
1947 /* Return TRUE for a valid operand of a DImode operation.
1948 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1949 Note that this disallows MEM(REG+REG), but allows
1950 MEM(PRE/POST_INC/DEC(REG)). */
1953 di_operand (op, mode)
1955 enum machine_mode mode;
1957 if (s_register_operand (op, mode))
1960 switch (GET_CODE (op))
1967 return memory_address_p (DImode, XEXP (op, 0));
1974 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
1975 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1976 Note that this disallows MEM(REG+REG), but allows
1977 MEM(PRE/POST_INC/DEC(REG)). */
1980 soft_df_operand (op, mode)
1982 enum machine_mode mode;
1984 if (s_register_operand (op, mode))
1987 switch (GET_CODE (op))
1993 return memory_address_p (DFmode, XEXP (op, 0));
2000 /* Return TRUE for valid index operands. */
2003 index_operand (op, mode)
2005 enum machine_mode mode;
2007 return (s_register_operand(op, mode)
2008 || (immediate_operand (op, mode)
2009 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2012 /* Return TRUE for valid shifts by a constant. This also accepts any
2013 power of two on the (somewhat overly relaxed) assumption that the
2014 shift operator in this case was a mult. */
2017 const_shift_operand (op, mode)
2019 enum machine_mode mode;
2021 return (power_of_two_operand (op, mode)
2022 || (immediate_operand (op, mode)
2023 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2026 /* Return TRUE for arithmetic operators which can be combined with a multiply
2030 shiftable_operator (x, mode)
2032 enum machine_mode mode;
2034 if (GET_MODE (x) != mode)
2038 enum rtx_code code = GET_CODE (x);
2040 return (code == PLUS || code == MINUS
2041 || code == IOR || code == XOR || code == AND);
2045 /* Return TRUE for shift operators. */
2048 shift_operator (x, mode)
2050 enum machine_mode mode;
2052 if (GET_MODE (x) != mode)
2056 enum rtx_code code = GET_CODE (x);
2059 return power_of_two_operand (XEXP (x, 1));
2061 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2062 || code == ROTATERT);
2066 int equality_operator (x, mode)
2068 enum machine_mode mode;
2070 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2073 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2076 minmax_operator (x, mode)
2078 enum machine_mode mode;
2080 enum rtx_code code = GET_CODE (x);
2082 if (GET_MODE (x) != mode)
2085 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2088 /* return TRUE if x is EQ or NE */
2090 /* Return TRUE if this is the condition code register, if we aren't given
2091 a mode, accept any class CCmode register */
2094 cc_register (x, mode)
2096 enum machine_mode mode;
2098 if (mode == VOIDmode)
2100 mode = GET_MODE (x);
2101 if (GET_MODE_CLASS (mode) != MODE_CC)
2105 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2111 /* Return TRUE if this is the condition code register, if we aren't given
2112 a mode, accept any class CCmode register which indicates a dominance
2116 dominant_cc_register (x, mode)
2118 enum machine_mode mode;
2120 if (mode == VOIDmode)
2122 mode = GET_MODE (x);
2123 if (GET_MODE_CLASS (mode) != MODE_CC)
2127 if (mode != CC_DNEmode && mode != CC_DEQmode
2128 && mode != CC_DLEmode && mode != CC_DLTmode
2129 && mode != CC_DGEmode && mode != CC_DGTmode
2130 && mode != CC_DLEUmode && mode != CC_DLTUmode
2131 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2134 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2140 /* Return TRUE if X references a SYMBOL_REF. */
2142 symbol_mentioned_p (x)
2148 if (GET_CODE (x) == SYMBOL_REF)
2151 fmt = GET_RTX_FORMAT (GET_CODE (x));
2152 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2159 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2162 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2169 /* Return TRUE if X references a LABEL_REF. */
2171 label_mentioned_p (x)
2177 if (GET_CODE (x) == LABEL_REF)
2180 fmt = GET_RTX_FORMAT (GET_CODE (x));
2181 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2187 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2188 if (label_mentioned_p (XVECEXP (x, i, j)))
2191 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2202 enum rtx_code code = GET_CODE (x);
2206 else if (code == SMIN)
2208 else if (code == UMIN)
2210 else if (code == UMAX)
2216 /* Return 1 if memory locations are adjacent */
2219 adjacent_mem_locations (a, b)
2222 int val0 = 0, val1 = 0;
2225 if ((GET_CODE (XEXP (a, 0)) == REG
2226 || (GET_CODE (XEXP (a, 0)) == PLUS
2227 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2228 && (GET_CODE (XEXP (b, 0)) == REG
2229 || (GET_CODE (XEXP (b, 0)) == PLUS
2230 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2232 if (GET_CODE (XEXP (a, 0)) == PLUS)
2234 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2235 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2238 reg0 = REGNO (XEXP (a, 0));
2239 if (GET_CODE (XEXP (b, 0)) == PLUS)
2241 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2242 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2245 reg1 = REGNO (XEXP (b, 0));
2246 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2251 /* Return 1 if OP is a load multiple operation. It is known to be
2252 parallel and the first section will be tested. */
2255 load_multiple_operation (op, mode)
2257 enum machine_mode mode;
2259 HOST_WIDE_INT count = XVECLEN (op, 0);
2262 HOST_WIDE_INT i = 1, base = 0;
2266 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2269 /* Check to see if this might be a write-back */
2270 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2275 /* Now check it more carefully */
2276 if (GET_CODE (SET_DEST (elt)) != REG
2277 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2278 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2279 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2280 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2281 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2282 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2283 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2284 != REGNO (SET_DEST (elt)))
2290 /* Perform a quick check so we don't blow up below. */
2292 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2293 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2294 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2297 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2298 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2300 for (; i < count; i++)
2302 elt = XVECEXP (op, 0, i);
2304 if (GET_CODE (elt) != SET
2305 || GET_CODE (SET_DEST (elt)) != REG
2306 || GET_MODE (SET_DEST (elt)) != SImode
2307 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2308 || GET_CODE (SET_SRC (elt)) != MEM
2309 || GET_MODE (SET_SRC (elt)) != SImode
2310 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2311 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2312 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2313 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2320 /* Return 1 if OP is a store multiple operation. It is known to be
2321 parallel and the first section will be tested. */
2324 store_multiple_operation (op, mode)
2326 enum machine_mode mode;
2328 HOST_WIDE_INT count = XVECLEN (op, 0);
2331 HOST_WIDE_INT i = 1, base = 0;
2335 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2338 /* Check to see if this might be a write-back */
2339 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2344 /* Now check it more carefully */
2345 if (GET_CODE (SET_DEST (elt)) != REG
2346 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2347 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2348 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2349 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2350 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2351 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2352 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2353 != REGNO (SET_DEST (elt)))
2359 /* Perform a quick check so we don't blow up below. */
2361 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2362 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2363 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2366 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2367 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2369 for (; i < count; i++)
2371 elt = XVECEXP (op, 0, i);
2373 if (GET_CODE (elt) != SET
2374 || GET_CODE (SET_SRC (elt)) != REG
2375 || GET_MODE (SET_SRC (elt)) != SImode
2376 || REGNO (SET_SRC (elt)) != src_regno + i - base
2377 || GET_CODE (SET_DEST (elt)) != MEM
2378 || GET_MODE (SET_DEST (elt)) != SImode
2379 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2380 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2381 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2382 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2390 load_multiple_sequence (operands, nops, regs, base, load_offset)
2395 HOST_WIDE_INT *load_offset;
2397 int unsorted_regs[4];
2398 HOST_WIDE_INT unsorted_offsets[4];
2403 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2404 extended if required. */
2405 if (nops < 2 || nops > 4)
2408 /* Loop over the operands and check that the memory references are
2409 suitable (ie immediate offsets from the same base register). At
2410 the same time, extract the target register, and the memory
2412 for (i = 0; i < nops; i++)
2417 /* Convert a subreg of a mem into the mem itself. */
2418 if (GET_CODE (operands[nops + i]) == SUBREG)
2419 operands[nops + i] = alter_subreg(operands[nops + i]);
2421 if (GET_CODE (operands[nops + i]) != MEM)
2424 /* Don't reorder volatile memory references; it doesn't seem worth
2425 looking for the case where the order is ok anyway. */
2426 if (MEM_VOLATILE_P (operands[nops + i]))
2429 offset = const0_rtx;
2431 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2432 || (GET_CODE (reg) == SUBREG
2433 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2434 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2435 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2437 || (GET_CODE (reg) == SUBREG
2438 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2439 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2444 base_reg = REGNO(reg);
2445 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2446 ? REGNO (operands[i])
2447 : REGNO (SUBREG_REG (operands[i])));
2452 if (base_reg != REGNO (reg))
2453 /* Not addressed from the same base register. */
2456 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2457 ? REGNO (operands[i])
2458 : REGNO (SUBREG_REG (operands[i])));
2459 if (unsorted_regs[i] < unsorted_regs[order[0]])
2463 /* If it isn't an integer register, or if it overwrites the
2464 base register but isn't the last insn in the list, then
2465 we can't do this. */
2466 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2467 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2470 unsorted_offsets[i] = INTVAL (offset);
2473 /* Not a suitable memory address. */
2477 /* All the useful information has now been extracted from the
2478 operands into unsorted_regs and unsorted_offsets; additionally,
2479 order[0] has been set to the lowest numbered register in the
2480 list. Sort the registers into order, and check that the memory
2481 offsets are ascending and adjacent. */
2483 for (i = 1; i < nops; i++)
2487 order[i] = order[i - 1];
2488 for (j = 0; j < nops; j++)
2489 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2490 && (order[i] == order[i - 1]
2491 || unsorted_regs[j] < unsorted_regs[order[i]]))
2494 /* Have we found a suitable register? if not, one must be used more
2496 if (order[i] == order[i - 1])
2499 /* Is the memory address adjacent and ascending? */
2500 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2508 for (i = 0; i < nops; i++)
2509 regs[i] = unsorted_regs[order[i]];
2511 *load_offset = unsorted_offsets[order[0]];
2514 if (unsorted_offsets[order[0]] == 0)
2515 return 1; /* ldmia */
2517 if (unsorted_offsets[order[0]] == 4)
2518 return 2; /* ldmib */
2520 if (unsorted_offsets[order[nops - 1]] == 0)
2521 return 3; /* ldmda */
2523 if (unsorted_offsets[order[nops - 1]] == -4)
2524 return 4; /* ldmdb */
2526 /* Can't do it without setting up the offset, only do this if it takes
2527 no more than one insn. */
2528 return (const_ok_for_arm (unsorted_offsets[order[0]])
2529 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2533 emit_ldm_seq (operands, nops)
2539 HOST_WIDE_INT offset;
2543 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2546 strcpy (buf, "ldm%?ia\t");
2550 strcpy (buf, "ldm%?ib\t");
2554 strcpy (buf, "ldm%?da\t");
2558 strcpy (buf, "ldm%?db\t");
2563 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2564 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2567 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2568 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2570 output_asm_insn (buf, operands);
2572 strcpy (buf, "ldm%?ia\t");
2579 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2580 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2582 for (i = 1; i < nops; i++)
2583 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2584 reg_names[regs[i]]);
2586 strcat (buf, "}\t%@ phole ldm");
2588 output_asm_insn (buf, operands);
2593 store_multiple_sequence (operands, nops, regs, base, load_offset)
2598 HOST_WIDE_INT *load_offset;
2600 int unsorted_regs[4];
2601 HOST_WIDE_INT unsorted_offsets[4];
2606 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2607 extended if required. */
2608 if (nops < 2 || nops > 4)
2611 /* Loop over the operands and check that the memory references are
2612 suitable (ie immediate offsets from the same base register). At
2613 the same time, extract the target register, and the memory
2615 for (i = 0; i < nops; i++)
2620 /* Convert a subreg of a mem into the mem itself. */
2621 if (GET_CODE (operands[nops + i]) == SUBREG)
2622 operands[nops + i] = alter_subreg(operands[nops + i]);
2624 if (GET_CODE (operands[nops + i]) != MEM)
2627 /* Don't reorder volatile memory references; it doesn't seem worth
2628 looking for the case where the order is ok anyway. */
2629 if (MEM_VOLATILE_P (operands[nops + i]))
2632 offset = const0_rtx;
2634 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2635 || (GET_CODE (reg) == SUBREG
2636 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2637 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2638 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2640 || (GET_CODE (reg) == SUBREG
2641 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2642 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2647 base_reg = REGNO(reg);
2648 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2649 ? REGNO (operands[i])
2650 : REGNO (SUBREG_REG (operands[i])));
2655 if (base_reg != REGNO (reg))
2656 /* Not addressed from the same base register. */
2659 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2660 ? REGNO (operands[i])
2661 : REGNO (SUBREG_REG (operands[i])));
2662 if (unsorted_regs[i] < unsorted_regs[order[0]])
2666 /* If it isn't an integer register, then we can't do this. */
2667 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2670 unsorted_offsets[i] = INTVAL (offset);
2673 /* Not a suitable memory address. */
2677 /* All the useful information has now been extracted from the
2678 operands into unsorted_regs and unsorted_offsets; additionally,
2679 order[0] has been set to the lowest numbered register in the
2680 list. Sort the registers into order, and check that the memory
2681 offsets are ascending and adjacent. */
2683 for (i = 1; i < nops; i++)
2687 order[i] = order[i - 1];
2688 for (j = 0; j < nops; j++)
2689 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2690 && (order[i] == order[i - 1]
2691 || unsorted_regs[j] < unsorted_regs[order[i]]))
2694 /* Have we found a suitable register? if not, one must be used more
2696 if (order[i] == order[i - 1])
2699 /* Is the memory address adjacent and ascending? */
2700 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2708 for (i = 0; i < nops; i++)
2709 regs[i] = unsorted_regs[order[i]];
2711 *load_offset = unsorted_offsets[order[0]];
2714 if (unsorted_offsets[order[0]] == 0)
2715 return 1; /* stmia */
2717 if (unsorted_offsets[order[0]] == 4)
2718 return 2; /* stmib */
2720 if (unsorted_offsets[order[nops - 1]] == 0)
2721 return 3; /* stmda */
2723 if (unsorted_offsets[order[nops - 1]] == -4)
2724 return 4; /* stmdb */
2730 emit_stm_seq (operands, nops)
2736 HOST_WIDE_INT offset;
2740 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2743 strcpy (buf, "stm%?ia\t");
2747 strcpy (buf, "stm%?ib\t");
2751 strcpy (buf, "stm%?da\t");
2755 strcpy (buf, "stm%?db\t");
2762 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2763 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2765 for (i = 1; i < nops; i++)
2766 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2767 reg_names[regs[i]]);
2769 strcat (buf, "}\t%@ phole stm");
2771 output_asm_insn (buf, operands);
2776 multi_register_push (op, mode)
2778 enum machine_mode mode;
2780 if (GET_CODE (op) != PARALLEL
2781 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
2782 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
2783 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
2790 /* Routines for use with attributes */
2792 /* Return nonzero if ATTR is a valid attribute for DECL.
2793 ATTRIBUTES are any existing attributes and ARGS are the arguments
2796 Supported attributes:
2798 naked: don't output any prologue or epilogue code, the user is assumed
2799 to do the right thing. */
2802 arm_valid_machine_decl_attribute (decl, attributes, attr, args)
2808 if (args != NULL_TREE)
2811 if (is_attribute_p ("naked", attr))
2812 return TREE_CODE (decl) == FUNCTION_DECL;
2816 /* Return non-zero if FUNC is a naked function. */
2819 arm_naked_function_p (func)
2824 if (TREE_CODE (func) != FUNCTION_DECL)
2827 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
2828 return a != NULL_TREE;
2831 /* Routines for use in generating RTL */
2834 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
2846 int sign = up ? 1 : -1;
2849 result = gen_rtx (PARALLEL, VOIDmode,
2850 rtvec_alloc (count + (write_back ? 2 : 0)));
2853 XVECEXP (result, 0, 0)
2854 = gen_rtx (SET, GET_MODE (from), from,
2855 plus_constant (from, count * 4 * sign));
2860 for (j = 0; i < count; i++, j++)
2862 mem = gen_rtx (MEM, SImode, plus_constant (from, j * 4 * sign));
2863 RTX_UNCHANGING_P (mem) = unchanging_p;
2864 MEM_IN_STRUCT_P (mem) = in_struct_p;
2866 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode,
2867 gen_rtx (REG, SImode, base_regno + j),
2872 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from);
2878 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
2890 int sign = up ? 1 : -1;
2893 result = gen_rtx (PARALLEL, VOIDmode,
2894 rtvec_alloc (count + (write_back ? 2 : 0)));
2897 XVECEXP (result, 0, 0)
2898 = gen_rtx (SET, GET_MODE (to), to,
2899 plus_constant (to, count * 4 * sign));
2904 for (j = 0; i < count; i++, j++)
2906 mem = gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign));
2907 RTX_UNCHANGING_P (mem) = unchanging_p;
2908 MEM_IN_STRUCT_P (mem) = in_struct_p;
2910 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, mem,
2911 gen_rtx (REG, SImode, base_regno + j));
2915 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to);
2921 arm_gen_movstrqi (operands)
2924 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
2927 rtx st_src, st_dst, fin_src, fin_dst;
2928 rtx part_bytes_reg = NULL;
2930 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
2932 if (GET_CODE (operands[2]) != CONST_INT
2933 || GET_CODE (operands[3]) != CONST_INT
2934 || INTVAL (operands[2]) > 64
2935 || INTVAL (operands[3]) & 3)
2938 st_dst = XEXP (operands[0], 0);
2939 st_src = XEXP (operands[1], 0);
2941 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
2942 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
2943 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
2944 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
2946 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
2947 fin_src = src = copy_to_mode_reg (SImode, st_src);
2949 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
2950 out_words_to_go = INTVAL (operands[2]) / 4;
2951 last_bytes = INTVAL (operands[2]) & 3;
2953 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
2954 part_bytes_reg = gen_rtx (REG, SImode, (in_words_to_go - 1) & 3);
2956 for (i = 0; in_words_to_go >= 2; i+=4)
2958 if (in_words_to_go > 4)
2959 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
2960 src_unchanging_p, src_in_struct_p));
2962 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
2963 FALSE, src_unchanging_p,
2966 if (out_words_to_go)
2968 if (out_words_to_go > 4)
2969 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
2972 else if (out_words_to_go != 1)
2973 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
2981 mem = gen_rtx (MEM, SImode, dst);
2982 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
2983 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
2984 emit_move_insn (mem, gen_rtx (REG, SImode, 0));
2985 if (last_bytes != 0)
2986 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
2990 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
2991 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
2994 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
2995 if (out_words_to_go)
2999 mem = gen_rtx (MEM, SImode, src);
3000 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3001 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3002 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3003 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3005 mem = gen_rtx (MEM, SImode, dst);
3006 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3007 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3008 emit_move_insn (mem, sreg);
3009 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3012 if (in_words_to_go) /* Sanity check */
3018 if (in_words_to_go < 0)
3021 mem = gen_rtx (MEM, SImode, src);
3022 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3023 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3024 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3027 if (BYTES_BIG_ENDIAN && last_bytes)
3029 rtx tmp = gen_reg_rtx (SImode);
3031 if (part_bytes_reg == NULL)
3034 /* The bytes we want are in the top end of the word */
3035 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3036 GEN_INT (8 * (4 - last_bytes))));
3037 part_bytes_reg = tmp;
3041 mem = gen_rtx (MEM, QImode, plus_constant (dst, last_bytes - 1));
3042 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3043 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3044 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3047 tmp = gen_reg_rtx (SImode);
3048 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3049 part_bytes_reg = tmp;
3058 if (part_bytes_reg == NULL)
3061 mem = gen_rtx (MEM, QImode, dst);
3062 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3063 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3064 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3067 rtx tmp = gen_reg_rtx (SImode);
3069 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3070 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3071 part_bytes_reg = tmp;
3079 /* Generate a memory reference for a half word, such that it will be loaded
3080 into the top 16 bits of the word. We can assume that the address is
3081 known to be alignable and of the form reg, or plus (reg, const). */
3083 gen_rotated_half_load (memref)
3086 HOST_WIDE_INT offset = 0;
3087 rtx base = XEXP (memref, 0);
3089 if (GET_CODE (base) == PLUS)
3091 offset = INTVAL (XEXP (base, 1));
3092 base = XEXP (base, 0);
3095 /* If we aren't allowed to generate unaligned addresses, then fail. */
3096 if (TARGET_SHORT_BY_BYTES
3097 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3100 base = gen_rtx (MEM, SImode, plus_constant (base, offset & ~2));
3102 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3105 return gen_rtx (ROTATE, SImode, base, GEN_INT (16));
3108 static enum machine_mode
3109 select_dominance_cc_mode (op, x, y, cond_or)
3113 HOST_WIDE_INT cond_or;
3115 enum rtx_code cond1, cond2;
3118 /* Currently we will probably get the wrong result if the individual
3119 comparisons are not simple. This also ensures that it is safe to
3120 reverse a comparison if necessary. */
3121 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3123 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3128 cond1 = reverse_condition (cond1);
3130 /* If the comparisons are not equal, and one doesn't dominate the other,
3131 then we can't do this. */
3133 && ! comparison_dominates_p (cond1, cond2)
3134 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3139 enum rtx_code temp = cond1;
3147 if (cond2 == EQ || ! cond_or)
3152 case LE: return CC_DLEmode;
3153 case LEU: return CC_DLEUmode;
3154 case GE: return CC_DGEmode;
3155 case GEU: return CC_DGEUmode;
3162 if (cond2 == LT || ! cond_or)
3171 if (cond2 == GT || ! cond_or)
3180 if (cond2 == LTU || ! cond_or)
3189 if (cond2 == GTU || ! cond_or)
3197 /* The remaining cases only occur when both comparisons are the
3222 arm_select_cc_mode (op, x, y)
3227 /* All floating point compares return CCFP if it is an equality
3228 comparison, and CCFPE otherwise. */
3229 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3230 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3232 /* A compare with a shifted operand. Because of canonicalization, the
3233 comparison will have to be swapped when we emit the assembler. */
3234 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3235 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3236 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3237 || GET_CODE (x) == ROTATERT))
3240 /* This is a special case that is used by combine to allow a
3241 comparison of a shifted byte load to be split into a zero-extend
3242 followed by a comparison of the shifted integer (only valid for
3243 equalities and unsigned inequalities). */
3244 if (GET_MODE (x) == SImode
3245 && GET_CODE (x) == ASHIFT
3246 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3247 && GET_CODE (XEXP (x, 0)) == SUBREG
3248 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3249 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3250 && (op == EQ || op == NE
3251 || op == GEU || op == GTU || op == LTU || op == LEU)
3252 && GET_CODE (y) == CONST_INT)
3255 /* An operation that sets the condition codes as a side-effect, the
3256 V flag is not set correctly, so we can only use comparisons where
3257 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3259 if (GET_MODE (x) == SImode
3261 && (op == EQ || op == NE || op == LT || op == GE)
3262 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3263 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3264 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3265 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3266 || GET_CODE (x) == LSHIFTRT
3267 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3268 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3271 /* A construct for a conditional compare, if the false arm contains
3272 0, then both conditions must be true, otherwise either condition
3273 must be true. Not all conditions are possible, so CCmode is
3274 returned if it can't be done. */
3275 if (GET_CODE (x) == IF_THEN_ELSE
3276 && (XEXP (x, 2) == const0_rtx
3277 || XEXP (x, 2) == const1_rtx)
3278 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3279 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3280 return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
3281 INTVAL (XEXP (x, 2)));
3283 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3286 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3287 && GET_CODE (x) == PLUS
3288 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3294 /* X and Y are two things to compare using CODE. Emit the compare insn and
3295 return the rtx for register 0 in the proper mode. FP means this is a
3296 floating point compare: I don't think that it is needed on the arm. */
3299 gen_compare_reg (code, x, y, fp)
3304 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3305 rtx cc_reg = gen_rtx (REG, mode, 24);
3307 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
3308 gen_rtx (COMPARE, mode, x, y)));
3314 arm_reload_in_hi (operands)
3317 rtx base = find_replacement (&XEXP (operands[1], 0));
3319 emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx (MEM, QImode, base)));
3320 /* Handle the case where the address is too complex to be offset by 1. */
3321 if (GET_CODE (base) == MINUS
3322 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3324 rtx base_plus = gen_rtx (REG, SImode, REGNO (operands[0]));
3326 emit_insn (gen_rtx (SET, VOIDmode, base_plus, base));
3330 emit_insn (gen_zero_extendqisi2 (gen_rtx (SUBREG, SImode, operands[0], 0),
3331 gen_rtx (MEM, QImode,
3332 plus_constant (base, 1))));
3333 if (BYTES_BIG_ENDIAN)
3334 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3336 gen_rtx (IOR, SImode,
3337 gen_rtx (ASHIFT, SImode,
3338 gen_rtx (SUBREG, SImode,
3343 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3345 gen_rtx (IOR, SImode,
3346 gen_rtx (ASHIFT, SImode,
3349 gen_rtx (SUBREG, SImode, operands[0], 0))));
3353 arm_reload_out_hi (operands)
3356 rtx base = find_replacement (&XEXP (operands[0], 0));
3358 if (BYTES_BIG_ENDIAN)
3360 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3361 gen_rtx (SUBREG, QImode, operands[1], 0)));
3362 emit_insn (gen_lshrsi3 (operands[2],
3363 gen_rtx (SUBREG, SImode, operands[1], 0),
3365 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3366 gen_rtx (SUBREG, QImode, operands[2], 0)));
3370 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3371 gen_rtx (SUBREG, QImode, operands[1], 0)));
3372 emit_insn (gen_lshrsi3 (operands[2],
3373 gen_rtx (SUBREG, SImode, operands[1], 0),
3375 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3376 gen_rtx (SUBREG, QImode, operands[2], 0)));
3380 /* Routines for manipulation of the constant pool. */
3381 /* This is unashamedly hacked from the version in sh.c, since the problem is
3382 extremely similar. */
3384 /* Arm instructions cannot load a large constant into a register,
3385 constants have to come from a pc relative load. The reference of a pc
3386 relative load instruction must be less than 1k infront of the instruction.
3387 This means that we often have to dump a constant inside a function, and
3388 generate code to branch around it.
3390 It is important to minimize this, since the branches will slow things
3391 down and make things bigger.
3393 Worst case code looks like:
3409 We fix this by performing a scan before scheduling, which notices which
3410 instructions need to have their operands fetched from the constant table
3411 and builds the table.
3416 scan, find an instruction which needs a pcrel move. Look forward, find th
3417 last barrier which is within MAX_COUNT bytes of the requirement.
3418 If there isn't one, make one. Process all the instructions between
3419 the find and the barrier.
3421 In the above example, we can tell that L3 is within 1k of L1, so
3422 the first move can be shrunk from the 2 insn+constant sequence into
3423 just 1 insn, and the constant moved to L3 to make:
3434 Then the second move becomes the target for the shortening process.
3440 rtx value; /* Value in table */
3441 HOST_WIDE_INT next_offset;
3442 enum machine_mode mode; /* Mode of value */
3445 /* The maximum number of constants that can fit into one pool, since
3446 the pc relative range is 0...1020 bytes and constants are at least 4
3449 #define MAX_POOL_SIZE (1020/4)
3450 static pool_node pool_vector[MAX_POOL_SIZE];
3451 static int pool_size;
3452 static rtx pool_vector_label;
3454 /* Add a constant to the pool and return its offset within the current
3457 X is the rtx we want to replace. MODE is its mode. On return,
3458 ADDRESS_ONLY will be non-zero if we really want the address of such
3459 a constant, not the constant itself. */
3460 static HOST_WIDE_INT
3461 add_constant (x, mode, address_only)
3463 enum machine_mode mode;
3467 HOST_WIDE_INT offset;
3471 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3472 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3473 x = get_pool_constant (XEXP (x, 0));
3474 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3477 x = get_pool_constant (x);
3479 #ifndef AOF_ASSEMBLER
3480 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3481 x = XVECEXP (x, 0, 0);
3484 #ifdef AOF_ASSEMBLER
3485 /* PIC Symbol references need to be converted into offsets into the
3487 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
3488 x = aof_pic_entry (x);
3489 #endif /* AOF_ASSEMBLER */
3491 /* First see if we've already got it */
3492 for (i = 0; i < pool_size; i++)
3494 if (GET_CODE (x) == pool_vector[i].value->code
3495 && mode == pool_vector[i].mode)
3497 if (GET_CODE (x) == CODE_LABEL)
3499 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3502 if (rtx_equal_p (x, pool_vector[i].value))
3503 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
3507 /* Need a new one */
3508 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
3511 pool_vector_label = gen_label_rtx ();
3513 pool_vector[pool_size].next_offset
3514 += (offset = pool_vector[pool_size - 1].next_offset);
3516 pool_vector[pool_size].value = x;
3517 pool_vector[pool_size].mode = mode;
3522 /* Output the literal table */
3529 scan = emit_label_after (gen_label_rtx (), scan);
3530 scan = emit_insn_after (gen_align_4 (), scan);
3531 scan = emit_label_after (pool_vector_label, scan);
3533 for (i = 0; i < pool_size; i++)
3535 pool_node *p = pool_vector + i;
3537 switch (GET_MODE_SIZE (p->mode))
3540 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
3544 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
3553 scan = emit_insn_after (gen_consttable_end (), scan);
3554 scan = emit_barrier_after (scan);
3558 /* Non zero if the src operand needs to be fixed up */
3560 fixit (src, mode, destreg)
3562 enum machine_mode mode;
3565 if (CONSTANT_P (src))
3567 if (GET_CODE (src) == CONST_INT)
3568 return (! const_ok_for_arm (INTVAL (src))
3569 && ! const_ok_for_arm (~INTVAL (src)));
3570 if (GET_CODE (src) == CONST_DOUBLE)
3571 return (GET_MODE (src) == VOIDmode
3573 || (! const_double_rtx_ok_for_fpu (src)
3574 && ! neg_const_double_rtx_ok_for_fpu (src)));
3575 return symbol_mentioned_p (src);
3577 #ifndef AOF_ASSEMBLER
3578 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
3582 return (mode == SImode && GET_CODE (src) == MEM
3583 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
3584 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
3587 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3589 find_barrier (from, max_count)
3594 rtx found_barrier = 0;
3597 while (from && count < max_count)
3601 if (GET_CODE (from) == BARRIER)
3602 found_barrier = from;
3604 /* Count the length of this insn */
3605 if (GET_CODE (from) == INSN
3606 && GET_CODE (PATTERN (from)) == SET
3607 && CONSTANT_P (SET_SRC (PATTERN (from)))
3608 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
3610 /* Handle table jumps as a single entity. */
3611 else if (GET_CODE (from) == JUMP_INSN
3612 && JUMP_LABEL (from) != 0
3613 && ((tmp = next_real_insn (JUMP_LABEL (from)))
3614 == next_real_insn (from))
3616 && GET_CODE (tmp) == JUMP_INSN
3617 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
3618 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
3620 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
3621 count += (get_attr_length (from)
3622 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
3623 /* Continue after the dispatch table. */
3625 from = NEXT_INSN (tmp);
3629 count += get_attr_length (from);
3632 from = NEXT_INSN (from);
3635 if (! found_barrier)
3637 /* We didn't find a barrier in time to
3638 dump our stuff, so we'll make one. */
3639 rtx label = gen_label_rtx ();
3642 from = PREV_INSN (last);
3644 from = get_last_insn ();
3646 /* Walk back to be just before any jump. */
3647 while (GET_CODE (from) == JUMP_INSN
3648 || GET_CODE (from) == NOTE
3649 || GET_CODE (from) == CODE_LABEL)
3650 from = PREV_INSN (from);
3652 from = emit_jump_insn_after (gen_jump (label), from);
3653 JUMP_LABEL (from) = label;
3654 found_barrier = emit_barrier_after (from);
3655 emit_label_after (label, found_barrier);
3658 return found_barrier;
3661 /* Non zero if the insn is a move instruction which needs to be fixed. */
3666 if (!INSN_DELETED_P (insn)
3667 && GET_CODE (insn) == INSN
3668 && GET_CODE (PATTERN (insn)) == SET)
3670 rtx pat = PATTERN (insn);
3671 rtx src = SET_SRC (pat);
3672 rtx dst = SET_DEST (pat);
3674 enum machine_mode mode = GET_MODE (dst);
3679 if (GET_CODE (dst) == REG)
3680 destreg = REGNO (dst);
3681 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
3682 destreg = REGNO (SUBREG_REG (dst));
3686 return fixit (src, mode, destreg);
3699 /* The ldr instruction can work with up to a 4k offset, and most constants
3700 will be loaded with one of these instructions; however, the adr
3701 instruction and the ldf instructions only work with a 1k offset. This
3702 code needs to be rewritten to use the 4k offset when possible, and to
3703 adjust when a 1k offset is needed. For now we just use a 1k offset
3707 /* Floating point operands can't work further than 1024 bytes from the
3708 PC, so to make things simple we restrict all loads for such functions.
3710 if (TARGET_HARD_FLOAT)
3714 for (regno = 16; regno < 24; regno++)
3715 if (regs_ever_live[regno])
3725 for (insn = first; insn; insn = NEXT_INSN (insn))
3727 if (broken_move (insn))
3729 /* This is a broken move instruction, scan ahead looking for
3730 a barrier to stick the constant table behind */
3732 rtx barrier = find_barrier (insn, count_size);
3734 /* Now find all the moves between the points and modify them */
3735 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3737 if (broken_move (scan))
3739 /* This is a broken move instruction, add it to the pool */
3740 rtx pat = PATTERN (scan);
3741 rtx src = SET_SRC (pat);
3742 rtx dst = SET_DEST (pat);
3743 enum machine_mode mode = GET_MODE (dst);
3744 HOST_WIDE_INT offset;
3751 /* If this is an HImode constant load, convert it into
3752 an SImode constant load. Since the register is always
3753 32 bits this is safe. We have to do this, since the
3754 load pc-relative instruction only does a 32-bit load. */
3758 if (GET_CODE (dst) != REG)
3760 PUT_MODE (dst, SImode);
3763 offset = add_constant (src, mode, &address_only);
3764 addr = plus_constant (gen_rtx (LABEL_REF, VOIDmode,
3768 /* If we only want the address of the pool entry, or
3769 for wide moves to integer regs we need to split
3770 the address calculation off into a separate insn.
3771 If necessary, the load can then be done with a
3772 load-multiple. This is safe, since we have
3773 already noted the length of such insns to be 8,
3774 and we are immediately over-writing the scratch
3775 we have grabbed with the final result. */
3776 if ((address_only || GET_MODE_SIZE (mode) > 4)
3777 && (scratch = REGNO (dst)) < 16)
3784 reg = gen_rtx (REG, SImode, scratch);
3786 newinsn = emit_insn_after (gen_movaddr (reg, addr),
3793 newsrc = gen_rtx (MEM, mode, addr);
3795 /* XXX Fixme -- I think the following is bogus. */
3796 /* Build a jump insn wrapper around the move instead
3797 of an ordinary insn, because we want to have room for
3798 the target label rtx in fld[7], which an ordinary
3799 insn doesn't have. */
3800 newinsn = emit_jump_insn_after
3801 (gen_rtx (SET, VOIDmode, dst, newsrc), newinsn);
3802 JUMP_LABEL (newinsn) = pool_vector_label;
3804 /* But it's still an ordinary insn */
3805 PUT_CODE (newinsn, INSN);
3813 dump_table (barrier);
3820 /* Routines to output assembly language. */
3822 /* If the rtx is the correct value then return the string of the number.
3823 In this way we can ensure that valid double constants are generated even
3824 when cross compiling. */
3826 fp_immediate_constant (x)
3832 if (!fpa_consts_inited)
3835 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3836 for (i = 0; i < 8; i++)
3837 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3838 return strings_fpa[i];
3843 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
3845 fp_const_from_val (r)
3850 if (! fpa_consts_inited)
3853 for (i = 0; i < 8; i++)
3854 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
3855 return strings_fpa[i];
3860 /* Output the operands of a LDM/STM instruction to STREAM.
3861 MASK is the ARM register set mask of which only bits 0-15 are important.
3862 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
3863 must follow the register list. */
3866 print_multi_reg (stream, instr, mask, hat)
3872 int not_first = FALSE;
3874 fputc ('\t', stream);
3875 fprintf (stream, instr, REGISTER_PREFIX);
3876 fputs (", {", stream);
3877 for (i = 0; i < 16; i++)
3878 if (mask & (1 << i))
3881 fprintf (stream, ", ");
3882 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
3886 fprintf (stream, "}%s\n", hat ? "^" : "");
3889 /* Output a 'call' insn. */
3892 output_call (operands)
3895 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
3897 if (REGNO (operands[0]) == 14)
3899 operands[0] = gen_rtx (REG, SImode, 12);
3900 output_asm_insn ("mov%?\t%0, %|lr", operands);
3902 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3904 if (TARGET_THUMB_INTERWORK)
3905 output_asm_insn ("bx%?\t%0", operands);
3907 output_asm_insn ("mov%?\t%|pc, %0", operands);
3916 int something_changed = 0;
3918 int code = GET_CODE (x0);
3925 if (REGNO (x0) == 14)
3927 *x = gen_rtx (REG, SImode, 12);
3932 /* Scan through the sub-elements and change any references there */
3933 fmt = GET_RTX_FORMAT (code);
3934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3936 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
3937 else if (fmt[i] == 'E')
3938 for (j = 0; j < XVECLEN (x0, i); j++)
3939 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
3940 return something_changed;
3944 /* Output a 'call' insn that is a reference in memory. */
3947 output_call_mem (operands)
3950 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
3951 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
3953 if (eliminate_lr2ip (&operands[0]))
3954 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
3956 if (TARGET_THUMB_INTERWORK)
3958 output_asm_insn ("ldr%?\t%|ip, %0", operands);
3959 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3960 output_asm_insn ("bx%?\t%|ip", operands);
3964 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3965 output_asm_insn ("ldr%?\t%|pc, %0", operands);
3972 /* Output a move from arm registers to an fpu registers.
3973 OPERANDS[0] is an fpu register.
3974 OPERANDS[1] is the first registers of an arm register pair. */
3977 output_mov_long_double_fpu_from_arm (operands)
3980 int arm_reg0 = REGNO (operands[1]);
3986 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3987 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3988 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
3990 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
3991 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
3995 /* Output a move from an fpu register to arm registers.
3996 OPERANDS[0] is the first registers of an arm register pair.
3997 OPERANDS[1] is an fpu register. */
4000 output_mov_long_double_arm_from_fpu (operands)
4003 int arm_reg0 = REGNO (operands[0]);
4009 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4010 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4011 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
4013 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4014 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4018 /* Output a move from arm registers to arm registers of a long double
4019 OPERANDS[0] is the destination.
4020 OPERANDS[1] is the source. */
4022 output_mov_long_double_arm_from_arm (operands)
4025 /* We have to be careful here because the two might overlap */
4026 int dest_start = REGNO (operands[0]);
4027 int src_start = REGNO (operands[1]);
4031 if (dest_start < src_start)
4033 for (i = 0; i < 3; i++)
4035 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4036 ops[1] = gen_rtx (REG, SImode, src_start + i);
4037 output_asm_insn ("mov%?\t%0, %1", ops);
4042 for (i = 2; i >= 0; i--)
4044 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4045 ops[1] = gen_rtx (REG, SImode, src_start + i);
4046 output_asm_insn ("mov%?\t%0, %1", ops);
4054 /* Output a move from arm registers to an fpu registers.
4055 OPERANDS[0] is an fpu register.
4056 OPERANDS[1] is the first registers of an arm register pair. */
4059 output_mov_double_fpu_from_arm (operands)
4062 int arm_reg0 = REGNO (operands[1]);
4067 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4068 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4069 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4070 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4074 /* Output a move from an fpu register to arm registers.
4075 OPERANDS[0] is the first registers of an arm register pair.
4076 OPERANDS[1] is an fpu register. */
4079 output_mov_double_arm_from_fpu (operands)
4082 int arm_reg0 = REGNO (operands[0]);
4088 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4089 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4090 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4091 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4095 /* Output a move between double words.
4096 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4097 or MEM<-REG and all MEMs must be offsettable addresses. */
4100 output_move_double (operands)
4103 enum rtx_code code0 = GET_CODE (operands[0]);
4104 enum rtx_code code1 = GET_CODE (operands[1]);
4109 int reg0 = REGNO (operands[0]);
4111 otherops[0] = gen_rtx (REG, SImode, 1 + reg0);
4114 int reg1 = REGNO (operands[1]);
4118 /* Ensure the second source is not overwritten */
4119 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4120 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4122 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4124 else if (code1 == CONST_DOUBLE)
4126 if (GET_MODE (operands[1]) == DFmode)
4129 union real_extract u;
4131 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4133 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4134 otherops[1] = GEN_INT(l[1]);
4135 operands[1] = GEN_INT(l[0]);
4137 else if (GET_MODE (operands[1]) != VOIDmode)
4139 else if (WORDS_BIG_ENDIAN)
4142 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4143 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4148 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4149 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4151 output_mov_immediate (operands);
4152 output_mov_immediate (otherops);
4154 else if (code1 == CONST_INT)
4156 #if HOST_BITS_PER_WIDE_INT > 32
4157 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4158 what the upper word is. */
4159 if (WORDS_BIG_ENDIAN)
4161 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4162 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4166 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4167 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4170 /* Sign extend the intval into the high-order word */
4171 if (WORDS_BIG_ENDIAN)
4173 otherops[1] = operands[1];
4174 operands[1] = (INTVAL (operands[1]) < 0
4175 ? constm1_rtx : const0_rtx);
4178 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4180 output_mov_immediate (otherops);
4181 output_mov_immediate (operands);
4183 else if (code1 == MEM)
4185 switch (GET_CODE (XEXP (operands[1], 0)))
4188 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4192 abort (); /* Should never happen now */
4196 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4200 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4204 abort (); /* Should never happen now */
4209 output_asm_insn ("adr%?\t%0, %1", operands);
4210 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4214 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
4216 otherops[0] = operands[0];
4217 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4218 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4219 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4221 if (GET_CODE (otherops[2]) == CONST_INT)
4223 switch (INTVAL (otherops[2]))
4226 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4229 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4232 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4235 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4236 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4238 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4241 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4244 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4245 return "ldm%?ia\t%0, %M0";
4249 otherops[1] = adj_offsettable_operand (operands[1], 4);
4250 /* Take care of overlapping base/data reg. */
4251 if (reg_mentioned_p (operands[0], operands[1]))
4253 output_asm_insn ("ldr%?\t%0, %1", otherops);
4254 output_asm_insn ("ldr%?\t%0, %1", operands);
4258 output_asm_insn ("ldr%?\t%0, %1", operands);
4259 output_asm_insn ("ldr%?\t%0, %1", otherops);
4265 abort(); /* Constraints should prevent this */
4267 else if (code0 == MEM && code1 == REG)
4269 if (REGNO (operands[1]) == 12)
4272 switch (GET_CODE (XEXP (operands[0], 0)))
4275 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4279 abort (); /* Should never happen now */
4283 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4287 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4291 abort (); /* Should never happen now */
4295 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4297 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4300 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4304 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4308 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4315 otherops[0] = adj_offsettable_operand (operands[0], 4);
4316 otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1]));
4317 output_asm_insn ("str%?\t%1, %0", operands);
4318 output_asm_insn ("str%?\t%1, %0", otherops);
4322 abort(); /* Constraints should prevent this */
4328 /* Output an arbitrary MOV reg, #n.
4329 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4332 output_mov_immediate (operands)
4335 HOST_WIDE_INT n = INTVAL (operands[1]);
4339 /* Try to use one MOV */
4340 if (const_ok_for_arm (n))
4342 output_asm_insn ("mov%?\t%0, %1", operands);
4346 /* Try to use one MVN */
4347 if (const_ok_for_arm (~n))
4349 operands[1] = GEN_INT (~n);
4350 output_asm_insn ("mvn%?\t%0, %1", operands);
4354 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4356 for (i=0; i < 32; i++)
4360 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4361 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4364 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4371 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4372 adding zero to one register, output nothing. */
4375 output_add_immediate (operands)
4378 HOST_WIDE_INT n = INTVAL (operands[2]);
4380 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4383 output_multi_immediate (operands,
4384 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4387 output_multi_immediate (operands,
4388 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4395 /* Output a multiple immediate operation.
4396 OPERANDS is the vector of operands referred to in the output patterns.
4397 INSTR1 is the output pattern to use for the first constant.
4398 INSTR2 is the output pattern to use for subsequent constants.
4399 IMMED_OP is the index of the constant slot in OPERANDS.
4400 N is the constant value. */
4403 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4405 char *instr1, *instr2;
4409 #if HOST_BITS_PER_WIDE_INT > 32
4415 operands[immed_op] = const0_rtx;
4416 output_asm_insn (instr1, operands); /* Quick and easy output */
4421 char *instr = instr1;
4423 /* Note that n is never zero here (which would give no output) */
4424 for (i = 0; i < 32; i += 2)
4428 operands[immed_op] = GEN_INT (n & (255 << i));
4429 output_asm_insn (instr, operands);
4439 /* Return the appropriate ARM instruction for the operation code.
4440 The returned result should not be overwritten. OP is the rtx of the
4441 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4445 arithmetic_instr (op, shift_first_arg)
4447 int shift_first_arg;
4449 switch (GET_CODE (op))
4455 return shift_first_arg ? "rsb" : "sub";
4472 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4473 for the operation code. The returned result should not be overwritten.
4474 OP is the rtx code of the shift.
4475 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4479 shift_op (op, amountp)
4481 HOST_WIDE_INT *amountp;
4484 enum rtx_code code = GET_CODE (op);
4486 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
4488 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
4489 *amountp = INTVAL (XEXP (op, 1));
4512 /* We never have to worry about the amount being other than a
4513 power of 2, since this case can never be reloaded from a reg. */
4515 *amountp = int_log2 (*amountp);
4526 /* This is not 100% correct, but follows from the desire to merge
4527 multiplication by a power of 2 with the recognizer for a
4528 shift. >=32 is not a valid shift for "asl", so we must try and
4529 output a shift that produces the correct arithmetical result.
4530 Using lsr #32 is identical except for the fact that the carry bit
4531 is not set correctly if we set the flags; but we never use the
4532 carry bit from such an operation, so we can ignore that. */
4533 if (code == ROTATERT)
4534 *amountp &= 31; /* Rotate is just modulo 32 */
4535 else if (*amountp != (*amountp & 31))
4542 /* Shifts of 0 are no-ops. */
4551 /* Obtain the shift from the POWER of two. */
4553 static HOST_WIDE_INT
4555 HOST_WIDE_INT power;
4557 HOST_WIDE_INT shift = 0;
4559 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
4569 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4570 /bin/as is horribly restrictive. */
4573 output_ascii_pseudo_op (stream, p, len)
4579 int len_so_far = 1000;
4580 int chars_so_far = 0;
4582 for (i = 0; i < len; i++)
4584 register int c = p[i];
4586 if (len_so_far > 50)
4589 fputs ("\"\n", stream);
4590 fputs ("\t.ascii\t\"", stream);
4595 if (c == '\"' || c == '\\')
4601 if (c >= ' ' && c < 0177)
4608 fprintf (stream, "\\%03o", c);
4615 fputs ("\"\n", stream);
4619 /* Try to determine whether a pattern really clobbers the link register.
4620 This information is useful when peepholing, so that lr need not be pushed
4621 if we combine a call followed by a return.
4622 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4623 such a check should not be needed because these only update an existing
4624 value within a register; the register must still be set elsewhere within
4628 pattern_really_clobbers_lr (x)
4633 switch (GET_CODE (x))
4636 switch (GET_CODE (SET_DEST (x)))
4639 return REGNO (SET_DEST (x)) == 14;
4642 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
4643 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
4645 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
4654 for (i = 0; i < XVECLEN (x, 0); i++)
4655 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
4660 switch (GET_CODE (XEXP (x, 0)))
4663 return REGNO (XEXP (x, 0)) == 14;
4666 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
4667 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
4683 function_really_clobbers_lr (first)
4688 for (insn = first; insn; insn = next_nonnote_insn (insn))
4690 switch (GET_CODE (insn))
4695 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
4700 if (pattern_really_clobbers_lr (PATTERN (insn)))
4705 /* Don't yet know how to handle those calls that are not to a
4707 if (GET_CODE (PATTERN (insn)) != PARALLEL)
4710 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
4713 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
4719 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
4725 default: /* Don't recognize it, be safe */
4729 /* A call can be made (by peepholing) not to clobber lr iff it is
4730 followed by a return. There may, however, be a use insn iff
4731 we are returning the result of the call.
4732 If we run off the end of the insn chain, then that means the
4733 call was at the end of the function. Unfortunately we don't
4734 have a return insn for the peephole to recognize, so we
4735 must reject this. (Can this be fixed by adding our own insn?) */
4736 if ((next = next_nonnote_insn (insn)) == NULL)
4739 /* No need to worry about lr if the call never returns */
4740 if (GET_CODE (next) == BARRIER)
4743 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
4744 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4745 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
4746 == REGNO (XEXP (PATTERN (next), 0))))
4747 if ((next = next_nonnote_insn (next)) == NULL)
4750 if (GET_CODE (next) == JUMP_INSN
4751 && GET_CODE (PATTERN (next)) == RETURN)
4760 /* We have reached the end of the chain so lr was _not_ clobbered */
4765 output_return_instruction (operand, really_return, reverse)
4771 int reg, live_regs = 0;
4772 int volatile_func = (optimize > 0
4773 && TREE_THIS_VOLATILE (current_function_decl));
4775 return_used_this_function = 1;
4780 /* If this function was declared non-returning, and we have found a tail
4781 call, then we have to trust that the called function won't return. */
4782 if (! really_return)
4785 /* Otherwise, trap an attempted return by aborting. */
4787 ops[1] = gen_rtx (SYMBOL_REF, Pmode, "abort");
4788 assemble_external_libcall (ops[1]);
4789 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
4793 if (current_function_calls_alloca && ! really_return)
4796 for (reg = 0; reg <= 10; reg++)
4797 if (regs_ever_live[reg] && ! call_used_regs[reg])
4800 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
4803 if (frame_pointer_needed)
4808 if (lr_save_eliminated || ! regs_ever_live[14])
4811 if (frame_pointer_needed)
4813 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
4816 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
4818 for (reg = 0; reg <= 10; reg++)
4819 if (regs_ever_live[reg] && ! call_used_regs[reg])
4821 strcat (instr, "%|");
4822 strcat (instr, reg_names[reg]);
4824 strcat (instr, ", ");
4827 if (frame_pointer_needed)
4829 strcat (instr, "%|");
4830 strcat (instr, reg_names[11]);
4831 strcat (instr, ", ");
4832 strcat (instr, "%|");
4833 strcat (instr, reg_names[13]);
4834 strcat (instr, ", ");
4835 strcat (instr, "%|");
4836 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
4837 ? reg_names[14] : reg_names[15] );
4841 strcat (instr, "%|");
4842 if (TARGET_THUMB_INTERWORK && really_return)
4843 strcat (instr, reg_names[12]);
4845 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4847 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
4848 output_asm_insn (instr, &operand);
4850 if (TARGET_THUMB_INTERWORK && really_return)
4852 strcpy (instr, "bx%?");
4853 strcat (instr, reverse ? "%D0" : "%d0");
4854 strcat (instr, "\t%|");
4855 strcat (instr, frame_pointer_needed ? "lr" : "ip");
4857 output_asm_insn (instr, & operand);
4860 else if (really_return)
4862 if (TARGET_THUMB_INTERWORK)
4863 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
4865 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
4866 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
4868 output_asm_insn (instr, & operand);
4874 /* Return nonzero if optimizing and the current function is volatile.
4875 Such functions never return, and many memory cycles can be saved
4876 by not storing register values that will never be needed again.
4877 This optimization was added to speed up context switching in a
4878 kernel application. */
4881 arm_volatile_func ()
4883 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
4886 /* The amount of stack adjustment that happens here, in output_return and in
4887 output_epilogue must be exactly the same as was calculated during reload,
4888 or things will point to the wrong place. The only time we can safely
4889 ignore this constraint is when a function has no arguments on the stack,
4890 no stack frame requirement and no live registers execpt for `lr'. If we
4891 can guarantee that by making all function calls into tail calls and that
4892 lr is not clobbered in any other way, then there is no need to push lr
4896 output_func_prologue (f, frame_size)
4900 int reg, live_regs_mask = 0;
4901 int volatile_func = (optimize > 0
4902 && TREE_THIS_VOLATILE (current_function_decl));
4904 /* Nonzero if we must stuff some register arguments onto the stack as if
4905 they were passed there. */
4906 int store_arg_regs = 0;
4908 if (arm_ccfsm_state || arm_target_insn)
4909 abort (); /* Sanity check */
4911 if (arm_naked_function_p (current_function_decl))
4914 return_used_this_function = 0;
4915 lr_save_eliminated = 0;
4917 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
4918 ASM_COMMENT_START, current_function_args_size,
4919 current_function_pretend_args_size, frame_size);
4920 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
4921 ASM_COMMENT_START, frame_pointer_needed,
4922 current_function_anonymous_args);
4925 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
4927 if (current_function_anonymous_args && current_function_pretend_args_size)
4930 for (reg = 0; reg <= 10; reg++)
4931 if (regs_ever_live[reg] && ! call_used_regs[reg])
4932 live_regs_mask |= (1 << reg);
4934 if (frame_pointer_needed)
4935 live_regs_mask |= 0xD800;
4936 else if (regs_ever_live[14])
4938 if (! current_function_args_size
4939 && ! function_really_clobbers_lr (get_insns ()))
4940 lr_save_eliminated = 1;
4942 live_regs_mask |= 0x4000;
4947 /* if a di mode load/store multiple is used, and the base register
4948 is r3, then r4 can become an ever live register without lr
4949 doing so, in this case we need to push lr as well, or we
4950 will fail to get a proper return. */
4952 live_regs_mask |= 0x4000;
4953 lr_save_eliminated = 0;
4957 if (lr_save_eliminated)
4958 fprintf (f,"\t%s I don't think this function clobbers lr\n",
4961 #ifdef AOF_ASSEMBLER
4963 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
4964 reg_names[PIC_OFFSET_TABLE_REGNUM]);
4970 output_func_epilogue (f, frame_size)
4974 int reg, live_regs_mask = 0;
4975 /* If we need this then it will always be at least this much */
4976 int floats_offset = 12;
4978 int volatile_func = (optimize > 0
4979 && TREE_THIS_VOLATILE (current_function_decl));
4981 if (use_return_insn() && return_used_this_function)
4983 if ((frame_size + current_function_outgoing_args_size) != 0
4984 && !(frame_pointer_needed || TARGET_APCS))
4989 /* Naked functions don't have epilogues. */
4990 if (arm_naked_function_p (current_function_decl))
4993 /* A volatile function should never return. Call abort. */
4996 rtx op = gen_rtx (SYMBOL_REF, Pmode, "abort");
4997 assemble_external_libcall (op);
4998 output_asm_insn ("bl\t%a0", &op);
5002 for (reg = 0; reg <= 10; reg++)
5003 if (regs_ever_live[reg] && ! call_used_regs[reg])
5005 live_regs_mask |= (1 << reg);
5009 if (frame_pointer_needed)
5011 if (arm_fpu_arch == FP_SOFT2)
5013 for (reg = 23; reg > 15; reg--)
5014 if (regs_ever_live[reg] && ! call_used_regs[reg])
5016 floats_offset += 12;
5017 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
5018 reg_names[reg], REGISTER_PREFIX, floats_offset);
5025 for (reg = 23; reg > 15; reg--)
5027 if (regs_ever_live[reg] && ! call_used_regs[reg])
5029 floats_offset += 12;
5030 /* We can't unstack more than four registers at once */
5031 if (start_reg - reg == 3)
5033 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
5034 REGISTER_PREFIX, reg_names[reg],
5035 REGISTER_PREFIX, floats_offset);
5036 start_reg = reg - 1;
5041 if (reg != start_reg)
5042 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5043 REGISTER_PREFIX, reg_names[reg + 1],
5044 start_reg - reg, REGISTER_PREFIX, floats_offset);
5046 start_reg = reg - 1;
5050 /* Just in case the last register checked also needs unstacking. */
5051 if (reg != start_reg)
5052 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5053 REGISTER_PREFIX, reg_names[reg + 1],
5054 start_reg - reg, REGISTER_PREFIX, floats_offset);
5057 if (TARGET_THUMB_INTERWORK)
5059 live_regs_mask |= 0x6800;
5060 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5061 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5065 live_regs_mask |= 0xA800;
5066 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5067 TARGET_APCS_32 ? FALSE : TRUE);
5072 /* Restore stack pointer if necessary. */
5073 if (frame_size + current_function_outgoing_args_size != 0)
5075 operands[0] = operands[1] = stack_pointer_rtx;
5076 operands[2] = GEN_INT (frame_size
5077 + current_function_outgoing_args_size);
5078 output_add_immediate (operands);
5081 if (arm_fpu_arch == FP_SOFT2)
5083 for (reg = 16; reg < 24; reg++)
5084 if (regs_ever_live[reg] && ! call_used_regs[reg])
5085 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5086 reg_names[reg], REGISTER_PREFIX);
5092 for (reg = 16; reg < 24; reg++)
5094 if (regs_ever_live[reg] && ! call_used_regs[reg])
5096 if (reg - start_reg == 3)
5098 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5099 REGISTER_PREFIX, reg_names[start_reg],
5101 start_reg = reg + 1;
5106 if (reg != start_reg)
5107 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5108 REGISTER_PREFIX, reg_names[start_reg],
5109 reg - start_reg, REGISTER_PREFIX);
5111 start_reg = reg + 1;
5115 /* Just in case the last register checked also needs unstacking. */
5116 if (reg != start_reg)
5117 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5118 REGISTER_PREFIX, reg_names[start_reg],
5119 reg - start_reg, REGISTER_PREFIX);
5122 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5124 if (TARGET_THUMB_INTERWORK)
5126 if (! lr_save_eliminated)
5127 print_multi_reg(f, "ldmfd\t%ssp!", live_regs_mask | 0x4000,
5130 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5132 else if (lr_save_eliminated)
5133 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5134 : "\tmovs\t%spc, %slr\n"),
5135 REGISTER_PREFIX, REGISTER_PREFIX, f);
5137 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5138 TARGET_APCS_32 ? FALSE : TRUE);
5142 if (live_regs_mask || regs_ever_live[14])
5144 /* Restore the integer regs, and the return address into lr */
5145 if (! lr_save_eliminated)
5146 live_regs_mask |= 0x4000;
5148 if (live_regs_mask != 0)
5149 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5152 if (current_function_pretend_args_size)
5154 /* Unwind the pre-pushed regs */
5155 operands[0] = operands[1] = stack_pointer_rtx;
5156 operands[2] = GEN_INT (current_function_pretend_args_size);
5157 output_add_immediate (operands);
5159 /* And finally, go home */
5160 if (TARGET_THUMB_INTERWORK)
5161 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5162 else if (TARGET_APCS_32)
5163 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5165 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5171 current_function_anonymous_args = 0;
5175 emit_multi_reg_push (mask)
5182 for (i = 0; i < 16; i++)
5183 if (mask & (1 << i))
5186 if (num_regs == 0 || num_regs > 16)
5189 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num_regs));
5191 for (i = 0; i < 16; i++)
5193 if (mask & (1 << i))
5196 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, BLKmode,
5197 gen_rtx (PRE_DEC, BLKmode,
5198 stack_pointer_rtx)),
5199 gen_rtx (UNSPEC, BLKmode,
5200 gen_rtvec (1, gen_rtx (REG, SImode, i)),
5206 for (j = 1, i++; j < num_regs; i++)
5208 if (mask & (1 << i))
5211 = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, i));
5220 emit_sfm (base_reg, count)
5227 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5229 XVECEXP (par, 0, 0) = gen_rtx (SET, VOIDmode,
5230 gen_rtx (MEM, BLKmode,
5231 gen_rtx (PRE_DEC, BLKmode,
5232 stack_pointer_rtx)),
5233 gen_rtx (UNSPEC, BLKmode,
5234 gen_rtvec (1, gen_rtx (REG, XFmode,
5237 for (i = 1; i < count; i++)
5238 XVECEXP (par, 0, i) = gen_rtx (USE, VOIDmode,
5239 gen_rtx (REG, XFmode, base_reg++));
5245 arm_expand_prologue ()
5248 rtx amount = GEN_INT (-(get_frame_size ()
5249 + current_function_outgoing_args_size));
5250 int live_regs_mask = 0;
5251 int store_arg_regs = 0;
5252 int volatile_func = (optimize > 0
5253 && TREE_THIS_VOLATILE (current_function_decl));
5255 /* Naked functions don't have prologues. */
5256 if (arm_naked_function_p (current_function_decl))
5259 if (current_function_anonymous_args && current_function_pretend_args_size)
5262 if (! volatile_func)
5263 for (reg = 0; reg <= 10; reg++)
5264 if (regs_ever_live[reg] && ! call_used_regs[reg])
5265 live_regs_mask |= 1 << reg;
5267 if (! volatile_func && regs_ever_live[14])
5268 live_regs_mask |= 0x4000;
5270 if (frame_pointer_needed)
5272 live_regs_mask |= 0xD800;
5273 emit_insn (gen_movsi (gen_rtx (REG, SImode, 12),
5274 stack_pointer_rtx));
5277 if (current_function_pretend_args_size)
5280 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5283 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5284 GEN_INT (-current_function_pretend_args_size)));
5289 /* If we have to push any regs, then we must push lr as well, or
5290 we won't get a proper return. */
5291 live_regs_mask |= 0x4000;
5292 emit_multi_reg_push (live_regs_mask);
5295 /* For now the integer regs are still pushed in output_func_epilogue (). */
5297 if (! volatile_func)
5299 if (arm_fpu_arch == FP_SOFT2)
5301 for (reg = 23; reg > 15; reg--)
5302 if (regs_ever_live[reg] && ! call_used_regs[reg])
5303 emit_insn (gen_rtx (SET, VOIDmode,
5304 gen_rtx (MEM, XFmode,
5305 gen_rtx (PRE_DEC, XFmode,
5306 stack_pointer_rtx)),
5307 gen_rtx (REG, XFmode, reg)));
5313 for (reg = 23; reg > 15; reg--)
5315 if (regs_ever_live[reg] && ! call_used_regs[reg])
5317 if (start_reg - reg == 3)
5320 start_reg = reg - 1;
5325 if (start_reg != reg)
5326 emit_sfm (reg + 1, start_reg - reg);
5327 start_reg = reg - 1;
5331 if (start_reg != reg)
5332 emit_sfm (reg + 1, start_reg - reg);
5336 if (frame_pointer_needed)
5337 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx (REG, SImode, 12),
5339 (-(4 + current_function_pretend_args_size)))));
5341 if (amount != const0_rtx)
5343 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5344 emit_insn (gen_rtx (CLOBBER, VOIDmode,
5345 gen_rtx (MEM, BLKmode, stack_pointer_rtx)));
5348 /* If we are profiling, make sure no instructions are scheduled before
5349 the call to mcount. */
5350 if (profile_flag || profile_block_flag)
5351 emit_insn (gen_blockage ());
5355 /* If CODE is 'd', then the X is a condition operand and the instruction
5356 should only be executed if the condition is true.
5357 if CODE is 'D', then the X is a condition operand and the instruction
5358 should only be executed if the condition is false: however, if the mode
5359 of the comparison is CCFPEmode, then always execute the instruction -- we
5360 do this because in these circumstances !GE does not necessarily imply LT;
5361 in these cases the instruction pattern will take care to make sure that
5362 an instruction containing %d will follow, thereby undoing the effects of
5363 doing this instruction unconditionally.
5364 If CODE is 'N' then X is a floating point operand that must be negated
5366 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5367 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5370 arm_print_operand (stream, x, code)
5378 fputs (ASM_COMMENT_START, stream);
5382 fputs (REGISTER_PREFIX, stream);
5386 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5387 fputs (arm_condition_codes[arm_current_cc], stream);
5393 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5394 r = REAL_VALUE_NEGATE (r);
5395 fprintf (stream, "%s", fp_const_from_val (&r));
5400 if (GET_CODE (x) == CONST_INT)
5402 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5407 ARM_SIGN_EXTEND (~ INTVAL (x)));
5411 output_addr_const (stream, x);
5416 fprintf (stream, "%s", arithmetic_instr (x, 1));
5420 fprintf (stream, "%s", arithmetic_instr (x, 0));
5426 char *shift = shift_op (x, &val);
5430 fprintf (stream, ", %s ", shift_op (x, &val));
5432 arm_print_operand (stream, XEXP (x, 1), 0);
5435 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5448 fputs (REGISTER_PREFIX, stream);
5449 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
5455 fputs (REGISTER_PREFIX, stream);
5456 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
5460 fputs (REGISTER_PREFIX, stream);
5461 if (GET_CODE (XEXP (x, 0)) == REG)
5462 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
5464 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
5468 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
5469 REGISTER_PREFIX, reg_names[REGNO (x) - 1
5470 + ((GET_MODE_SIZE (GET_MODE (x))
5471 + GET_MODE_SIZE (SImode) - 1)
5472 / GET_MODE_SIZE (SImode))]);
5477 fputs (arm_condition_codes[get_arm_condition_code (x)],
5483 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
5484 (get_arm_condition_code (x))],
5492 if (GET_CODE (x) == REG)
5494 fputs (REGISTER_PREFIX, stream);
5495 fputs (reg_names[REGNO (x)], stream);
5497 else if (GET_CODE (x) == MEM)
5499 output_memory_reference_mode = GET_MODE (x);
5500 output_address (XEXP (x, 0));
5502 else if (GET_CODE (x) == CONST_DOUBLE)
5503 fprintf (stream, "#%s", fp_immediate_constant (x));
5504 else if (GET_CODE (x) == NEG)
5505 abort (); /* This should never happen now. */
5508 fputc ('#', stream);
5509 output_addr_const (stream, x);
5515 /* A finite state machine takes care of noticing whether or not instructions
5516 can be conditionally executed, and thus decrease execution time and code
5517 size by deleting branch instructions. The fsm is controlled by
5518 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
5520 /* The state of the fsm controlling condition codes are:
5521 0: normal, do nothing special
5522 1: make ASM_OUTPUT_OPCODE not output this instruction
5523 2: make ASM_OUTPUT_OPCODE not output this instruction
5524 3: make instructions conditional
5525 4: make instructions conditional
5527 State transitions (state->state by whom under condition):
5528 0 -> 1 final_prescan_insn if the `target' is a label
5529 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
5530 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
5531 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
5532 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
5533 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
5534 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
5535 (the target insn is arm_target_insn).
5537 If the jump clobbers the conditions then we use states 2 and 4.
5539 A similar thing can be done with conditional return insns.
5541 XXX In case the `target' is an unconditional branch, this conditionalising
5542 of the instructions always reduces code size, but not always execution
5543 time. But then, I want to reduce the code size to somewhere near what
5544 /bin/cc produces. */
5546 /* Returns the index of the ARM condition code string in
5547 `arm_condition_codes'. COMPARISON should be an rtx like
5548 `(eq (...) (...))'. */
5550 static enum arm_cond_code
5551 get_arm_condition_code (comparison)
5554 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
5556 register enum rtx_code comp_code = GET_CODE (comparison);
5558 if (GET_MODE_CLASS (mode) != MODE_CC)
5559 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
5560 XEXP (comparison, 1));
5564 case CC_DNEmode: code = ARM_NE; goto dominance;
5565 case CC_DEQmode: code = ARM_EQ; goto dominance;
5566 case CC_DGEmode: code = ARM_GE; goto dominance;
5567 case CC_DGTmode: code = ARM_GT; goto dominance;
5568 case CC_DLEmode: code = ARM_LE; goto dominance;
5569 case CC_DLTmode: code = ARM_LT; goto dominance;
5570 case CC_DGEUmode: code = ARM_CS; goto dominance;
5571 case CC_DGTUmode: code = ARM_HI; goto dominance;
5572 case CC_DLEUmode: code = ARM_LS; goto dominance;
5573 case CC_DLTUmode: code = ARM_CC;
5576 if (comp_code != EQ && comp_code != NE)
5579 if (comp_code == EQ)
5580 return ARM_INVERSE_CONDITION_CODE (code);
5586 case NE: return ARM_NE;
5587 case EQ: return ARM_EQ;
5588 case GE: return ARM_PL;
5589 case LT: return ARM_MI;
5597 case NE: return ARM_NE;
5598 case EQ: return ARM_EQ;
5605 case GE: return ARM_GE;
5606 case GT: return ARM_GT;
5607 case LE: return ARM_LS;
5608 case LT: return ARM_MI;
5615 case NE: return ARM_NE;
5616 case EQ: return ARM_EQ;
5617 case GE: return ARM_LE;
5618 case GT: return ARM_LT;
5619 case LE: return ARM_GE;
5620 case LT: return ARM_GT;
5621 case GEU: return ARM_LS;
5622 case GTU: return ARM_CC;
5623 case LEU: return ARM_CS;
5624 case LTU: return ARM_HI;
5631 case LTU: return ARM_CS;
5632 case GEU: return ARM_CC;
5639 case NE: return ARM_NE;
5640 case EQ: return ARM_EQ;
5641 case GE: return ARM_GE;
5642 case GT: return ARM_GT;
5643 case LE: return ARM_LE;
5644 case LT: return ARM_LT;
5645 case GEU: return ARM_CS;
5646 case GTU: return ARM_HI;
5647 case LEU: return ARM_LS;
5648 case LTU: return ARM_CC;
5660 final_prescan_insn (insn, opvec, noperands)
5665 /* BODY will hold the body of INSN. */
5666 register rtx body = PATTERN (insn);
5668 /* This will be 1 if trying to repeat the trick, and things need to be
5669 reversed if it appears to fail. */
5672 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5673 taken are clobbered, even if the rtl suggests otherwise. It also
5674 means that we have to grub around within the jump expression to find
5675 out what the conditions are when the jump isn't taken. */
5676 int jump_clobbers = 0;
5678 /* If we start with a return insn, we only succeed if we find another one. */
5679 int seeking_return = 0;
5681 /* START_INSN will hold the insn from where we start looking. This is the
5682 first insn after the following code_label if REVERSE is true. */
5683 rtx start_insn = insn;
5685 /* If in state 4, check if the target branch is reached, in order to
5686 change back to state 0. */
5687 if (arm_ccfsm_state == 4)
5689 if (insn == arm_target_insn)
5691 arm_target_insn = NULL;
5692 arm_ccfsm_state = 0;
5697 /* If in state 3, it is possible to repeat the trick, if this insn is an
5698 unconditional branch to a label, and immediately following this branch
5699 is the previous target label which is only used once, and the label this
5700 branch jumps to is not too far off. */
5701 if (arm_ccfsm_state == 3)
5703 if (simplejump_p (insn))
5705 start_insn = next_nonnote_insn (start_insn);
5706 if (GET_CODE (start_insn) == BARRIER)
5708 /* XXX Isn't this always a barrier? */
5709 start_insn = next_nonnote_insn (start_insn);
5711 if (GET_CODE (start_insn) == CODE_LABEL
5712 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5713 && LABEL_NUSES (start_insn) == 1)
5718 else if (GET_CODE (body) == RETURN)
5720 start_insn = next_nonnote_insn (start_insn);
5721 if (GET_CODE (start_insn) == BARRIER)
5722 start_insn = next_nonnote_insn (start_insn);
5723 if (GET_CODE (start_insn) == CODE_LABEL
5724 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5725 && LABEL_NUSES (start_insn) == 1)
5737 if (arm_ccfsm_state != 0 && !reverse)
5739 if (GET_CODE (insn) != JUMP_INSN)
5742 /* This jump might be paralleled with a clobber of the condition codes
5743 the jump should always come first */
5744 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5745 body = XVECEXP (body, 0, 0);
5748 /* If this is a conditional return then we don't want to know */
5749 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5750 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
5751 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
5752 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
5757 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5758 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
5761 int fail = FALSE, succeed = FALSE;
5762 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5763 int then_not_else = TRUE;
5764 rtx this_insn = start_insn, label = 0;
5766 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5768 /* The code below is wrong for these, and I haven't time to
5769 fix it now. So we just do the safe thing and return. This
5770 whole function needs re-writing anyway. */
5775 /* Register the insn jumped to. */
5778 if (!seeking_return)
5779 label = XEXP (SET_SRC (body), 0);
5781 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
5782 label = XEXP (XEXP (SET_SRC (body), 1), 0);
5783 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
5785 label = XEXP (XEXP (SET_SRC (body), 2), 0);
5786 then_not_else = FALSE;
5788 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
5790 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
5793 then_not_else = FALSE;
5798 /* See how many insns this branch skips, and what kind of insns. If all
5799 insns are okay, and the label or unconditional branch to the same
5800 label is not too far away, succeed. */
5801 for (insns_skipped = 0;
5802 !fail && !succeed && insns_skipped++ < MAX_INSNS_SKIPPED;)
5806 this_insn = next_nonnote_insn (this_insn);
5810 switch (GET_CODE (this_insn))
5813 /* Succeed if it is the target label, otherwise fail since
5814 control falls in from somewhere else. */
5815 if (this_insn == label)
5819 arm_ccfsm_state = 2;
5820 this_insn = next_nonnote_insn (this_insn);
5823 arm_ccfsm_state = 1;
5831 /* Succeed if the following insn is the target label.
5833 If return insns are used then the last insn in a function
5834 will be a barrier. */
5835 this_insn = next_nonnote_insn (this_insn);
5836 if (this_insn && this_insn == label)
5840 arm_ccfsm_state = 2;
5841 this_insn = next_nonnote_insn (this_insn);
5844 arm_ccfsm_state = 1;
5852 /* If using 32-bit addresses the cc is not preserved over
5856 /* Succeed if the following insn is the target label,
5857 or if the following two insns are a barrier and
5858 the target label. */
5859 this_insn = next_nonnote_insn (this_insn);
5860 if (this_insn && GET_CODE (this_insn) == BARRIER)
5861 this_insn = next_nonnote_insn (this_insn);
5863 if (this_insn && this_insn == label
5864 && insns_skipped < MAX_INSNS_SKIPPED)
5868 arm_ccfsm_state = 2;
5869 this_insn = next_nonnote_insn (this_insn);
5872 arm_ccfsm_state = 1;
5881 /* If this is an unconditional branch to the same label, succeed.
5882 If it is to another label, do nothing. If it is conditional,
5884 /* XXX Probably, the tests for SET and the PC are unnecessary. */
5886 scanbody = PATTERN (this_insn);
5887 if (GET_CODE (scanbody) == SET
5888 && GET_CODE (SET_DEST (scanbody)) == PC)
5890 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
5891 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
5893 arm_ccfsm_state = 2;
5896 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
5899 else if (GET_CODE (scanbody) == RETURN
5902 arm_ccfsm_state = 2;
5905 else if (GET_CODE (scanbody) == PARALLEL)
5907 switch (get_attr_conds (this_insn))
5919 /* Instructions using or affecting the condition codes make it
5921 scanbody = PATTERN (this_insn);
5922 if ((GET_CODE (scanbody) == SET
5923 || GET_CODE (scanbody) == PARALLEL)
5924 && get_attr_conds (this_insn) != CONDS_NOCOND)
5934 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
5935 arm_target_label = CODE_LABEL_NUMBER (label);
5936 else if (seeking_return || arm_ccfsm_state == 2)
5938 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
5940 this_insn = next_nonnote_insn (this_insn);
5941 if (this_insn && (GET_CODE (this_insn) == BARRIER
5942 || GET_CODE (this_insn) == CODE_LABEL))
5947 /* Oh, dear! we ran off the end.. give up */
5948 recog (PATTERN (insn), insn, NULL_PTR);
5949 arm_ccfsm_state = 0;
5950 arm_target_insn = NULL;
5953 arm_target_insn = this_insn;
5962 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
5964 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
5965 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5966 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
5967 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5971 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
5974 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
5978 if (reverse || then_not_else)
5979 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5981 /* restore recog_operand (getting the attributes of other insns can
5982 destroy this array, but final.c assumes that it remains intact
5983 across this call; since the insn has been recognized already we
5984 call recog direct). */
5985 recog (PATTERN (insn), insn, NULL_PTR);
5989 #ifdef AOF_ASSEMBLER
5990 /* Special functions only needed when producing AOF syntax assembler. */
5992 rtx aof_pic_label = NULL_RTX;
5995 struct pic_chain *next;
5999 static struct pic_chain *aof_pic_chain = NULL;
6005 struct pic_chain **chainp;
6008 if (aof_pic_label == NULL_RTX)
6010 /* This needs to persist throughout the compilation. */
6011 end_temporary_allocation ();
6012 aof_pic_label = gen_rtx (SYMBOL_REF, Pmode, "x$adcons");
6013 resume_temporary_allocation ();
6016 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6017 offset += 4, chainp = &(*chainp)->next)
6018 if ((*chainp)->symname == XSTR (x, 0))
6019 return plus_constant (aof_pic_label, offset);
6021 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6022 (*chainp)->next = NULL;
6023 (*chainp)->symname = XSTR (x, 0);
6024 return plus_constant (aof_pic_label, offset);
6028 aof_dump_pic_table (f)
6031 struct pic_chain *chain;
6033 if (aof_pic_chain == NULL)
6036 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
6037 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
6038 reg_names[PIC_OFFSET_TABLE_REGNUM]);
6039 fputs ("|x$adcons|\n", f);
6041 for (chain = aof_pic_chain; chain; chain = chain->next)
6043 fputs ("\tDCD\t", f);
6044 assemble_name (f, chain->symname);
6049 int arm_text_section_count = 1;
6054 static char buf[100];
6055 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6056 arm_text_section_count++);
6058 strcat (buf, ", PIC, REENTRANT");
6062 static int arm_data_section_count = 1;
6067 static char buf[100];
6068 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6072 /* The AOF assembler is religiously strict about declarations of
6073 imported and exported symbols, so that it is impossible to declare
6074 a function as imported near the beginning of the file, and then to
6075 export it later on. It is, however, possible to delay the decision
6076 until all the functions in the file have been compiled. To get
6077 around this, we maintain a list of the imports and exports, and
6078 delete from it any that are subsequently defined. At the end of
6079 compilation we spit the remainder of the list out before the END
6084 struct import *next;
6088 static struct import *imports_list = NULL;
6091 aof_add_import (name)
6096 for (new = imports_list; new; new = new->next)
6097 if (new->name == name)
6100 new = (struct import *) xmalloc (sizeof (struct import));
6101 new->next = imports_list;
6107 aof_delete_import (name)
6110 struct import **old;
6112 for (old = &imports_list; *old; old = & (*old)->next)
6114 if ((*old)->name == name)
6116 *old = (*old)->next;
6122 int arm_main_function = 0;
6125 aof_dump_imports (f)
6128 /* The AOF assembler needs this to cause the startup code to be extracted
6129 from the library. Brining in __main causes the whole thing to work
6131 if (arm_main_function)
6134 fputs ("\tIMPORT __main\n", f);
6135 fputs ("\tDCD __main\n", f);
6138 /* Now dump the remaining imports. */
6139 while (imports_list)
6141 fprintf (f, "\tIMPORT\t");
6142 assemble_name (f, imports_list->name);
6144 imports_list = imports_list->next;
6147 #endif /* AOF_ASSEMBLER */