1 /* Output routines for GCC for ARM/RISCiX.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 #define MAX_INSNS_SKIPPED 5
46 /* Some function declarations. */
47 extern FILE *asm_out_file;
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char *output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char *fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char *shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
72 /* Define the information needed to generate branch insns. This is
73 stored from the compare operation. */
75 rtx arm_compare_op0, arm_compare_op1;
78 /* What type of cpu are we compiling for? */
79 enum processor_type arm_cpu;
81 /* What type of floating point are we tuning for? */
82 enum floating_point_type arm_fpu;
84 /* What type of floating point instructions are available? */
85 enum floating_point_type arm_fpu_arch;
87 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
88 enum prog_mode_type arm_prgmode;
90 /* Set by the -mfp=... option */
91 char *target_fp_name = NULL;
93 /* Nonzero if this is an "M" variant of the processor. */
94 int arm_fast_multiply = 0;
96 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
99 /* Set to the features we should tune the code for (multiply speed etc). */
102 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
103 must report the mode of the memory reference from PRINT_OPERAND to
104 PRINT_OPERAND_ADDRESS. */
105 enum machine_mode output_memory_reference_mode;
107 /* Nonzero if the prologue must setup `fp'. */
108 int current_function_anonymous_args;
110 /* The register number to be used for the PIC offset register. */
111 int arm_pic_register = 9;
113 /* Location counter of .text segment. */
114 int arm_text_location = 0;
116 /* Set to one if we think that lr is only saved because of subroutine calls,
117 but all of these can be `put after' return insns */
118 int lr_save_eliminated;
120 /* Set to 1 when a return insn is output, this means that the epilogue
123 static int return_used_this_function;
125 static int arm_constant_limit = 3;
127 /* For an explanation of these variables, see final_prescan_insn below. */
129 enum arm_cond_code arm_current_cc;
131 int arm_target_label;
133 /* The condition codes of the ARM, and the inverse function. */
134 char *arm_condition_codes[] =
136 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
137 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
140 static enum arm_cond_code get_arm_condition_code ();
143 /* Initialization code */
145 struct arm_cpu_select arm_select[4] =
147 /* switch name, tune arch */
148 { (char *)0, "--with-cpu=", 1, 1 },
149 { (char *)0, "-mcpu=", 1, 1 },
150 { (char *)0, "-march=", 0, 1 },
151 { (char *)0, "-mtune=", 1, 0 },
154 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
155 #define FL_FAST_MULT 0x02 /* Fast multiply */
156 #define FL_MODE26 0x04 /* 26-bit mode support */
157 #define FL_MODE32 0x08 /* 32-bit mode support */
158 #define FL_ARCH4 0x10 /* Architecture rel 4 */
159 #define FL_THUMB 0x20 /* Thumb aware */
164 enum processor_type type;
168 /* Not all of these give usefully different compilation alternatives,
169 but there is no simple way of generalizing them. */
170 static struct processors all_procs[] =
172 {"arm2", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
173 {"arm250", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
174 {"arm3", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
175 {"arm6", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
176 {"arm600", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
177 {"arm610", PROCESSOR_ARM6, FL_MODE32 | FL_MODE26},
178 {"arm7", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
179 /* arm7m doesn't exist on its own, only in conjunction with D, (and I), but
180 those don't alter the code, so it is sometimes known as the arm7m */
181 {"arm7m", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
183 {"arm7dm", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
185 {"arm7dmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
187 {"arm700", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
188 {"arm710", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
189 {"arm7100", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
190 {"arm7500", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
191 /* Doesn't really have an external co-proc, but does have embedded fpu */
192 {"arm7500fe", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
193 {"arm7tdmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
194 | FL_ARCH4 | FL_THUMB)},
195 {"arm8", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
197 {"arm810", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
199 {"strongarm", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
201 {"strongarm110", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
203 {"armv2", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
204 {"armv2a", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
205 {"armv3", PROCESSOR_NONE, FL_CO_PROC | FL_MODE32 | FL_MODE26},
206 {"armv3m", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
208 {"armv4", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
209 | FL_MODE26 | FL_ARCH4)},
210 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
211 implementations that support it, so we will leave it out for now. */
212 {"armv4t", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
217 /* Fix up any incompatible options that the user has specified.
218 This has now turned into a maze. */
220 arm_override_options ()
222 int arm_thumb_aware = 0;
225 struct arm_cpu_select *ptr;
226 static struct cpu_default {
230 { TARGET_CPU_arm2, "arm2" },
231 { TARGET_CPU_arm6, "arm6" },
232 { TARGET_CPU_arm610, "arm610" },
233 { TARGET_CPU_arm7dm, "arm7dm" },
234 { TARGET_CPU_arm7500fe, "arm7500fe" },
235 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
236 { TARGET_CPU_arm8, "arm8" },
237 { TARGET_CPU_arm810, "arm810" },
238 { TARGET_CPU_strongarm, "strongarm" },
241 struct cpu_default *def;
243 /* Set the default. */
244 for (def = &cpu_defaults[0]; def->name; ++def)
245 if (def->cpu == TARGET_CPU_DEFAULT)
250 arm_select[0].string = def->name;
252 for (i = 0; i < sizeof (arm_select) / sizeof (arm_select[0]); i++)
254 ptr = &arm_select[i];
255 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
257 struct processors *sel;
259 for (sel = all_procs; sel->name != NULL; sel++)
260 if (! strcmp (ptr->string, sel->name))
262 /* -march= is the only flag that can take an architecture
263 type, so if we match when the tune bit is set, the
264 option was invalid. */
267 if (sel->type == PROCESSOR_NONE)
268 continue; /* Its an architecture, not a cpu */
271 tune_flags = sel->flags;
280 if (sel->name == NULL)
281 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
285 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
286 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
288 if (TARGET_POKE_FUNCTION_NAME)
289 target_flags |= ARM_FLAG_APCS_FRAME;
292 warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
295 warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
297 if (TARGET_APCS_REENT && flag_pic)
298 fatal ("-fpic and -mapcs-reent are incompatible");
300 if (TARGET_APCS_REENT)
301 warning ("APCS reentrant code not supported.");
303 /* If stack checking is disabled, we can use r10 as the PIC register,
304 which keeps r9 available. */
305 if (flag_pic && ! TARGET_APCS_STACK)
306 arm_pic_register = 10;
308 /* Well, I'm about to have a go, but pic is NOT going to be compatible
309 with APCS reentrancy, since that requires too much support in the
310 assembler and linker, and the ARMASM assembler seems to lack some
311 required directives. */
313 warning ("Position independent code not supported");
315 if (TARGET_APCS_FLOAT)
316 warning ("Passing floating point arguments in fp regs not yet supported");
318 if (TARGET_APCS_STACK && ! TARGET_APCS)
320 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
321 target_flags |= ARM_FLAG_APCS_FRAME;
324 /* Default is to tune for an FPA */
327 /* Default value for floating point code... if no co-processor
328 bus, then schedule for emulated floating point. Otherwise,
329 assume the user has an FPA.
330 Note: this does not prevent use of floating point instructions,
331 -msoft-float does that. */
332 if ((tune_flags & FL_CO_PROC) == 0)
335 arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
336 arm_arch4 = (flags & FL_ARCH4) != 0;
337 arm_thumb_aware = (flags & FL_THUMB) != 0;
341 if (strcmp (target_fp_name, "2") == 0)
342 arm_fpu_arch = FP_SOFT2;
343 else if (strcmp (target_fp_name, "3") == 0)
344 arm_fpu_arch = FP_HARD;
346 fatal ("Invalid floating point emulation option: -mfpe=%s",
350 arm_fpu_arch = FP_DEFAULT;
352 if (TARGET_THUMB_INTERWORK && ! arm_thumb_aware)
354 warning ("This processor variant does not support Thumb interworking");
355 target_flags &= ~ARM_FLAG_THUMB;
358 if (TARGET_FPE && arm_fpu != FP_HARD)
361 /* For arm2/3 there is no need to do any scheduling if there is only
362 a floating point emulator, or we are doing software floating-point. */
363 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && arm_cpu == PROCESSOR_ARM2)
364 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
366 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
370 /* Return 1 if it is possible to return using a single instruction */
377 if (!reload_completed ||current_function_pretend_args_size
378 || current_function_anonymous_args
379 || ((get_frame_size () + current_function_outgoing_args_size != 0)
380 && !(TARGET_APCS || frame_pointer_needed)))
383 /* Can't be done if interworking with Thumb, and any registers have been
385 if (TARGET_THUMB_INTERWORK)
386 for (regno = 0; regno < 16; regno++)
387 if (regs_ever_live[regno] && ! call_used_regs[regno])
390 /* Can't be done if any of the FPU regs are pushed, since this also
392 for (regno = 16; regno < 24; regno++)
393 if (regs_ever_live[regno] && ! call_used_regs[regno])
396 /* If a function is naked, don't use the "return" insn. */
397 if (arm_naked_function_p (current_function_decl))
403 /* Return TRUE if int I is a valid immediate ARM constant. */
409 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
411 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
412 be all zero, or all one. */
413 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
414 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
415 != ((~(unsigned HOST_WIDE_INT) 0)
416 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
419 /* Fast return for 0 and powers of 2 */
420 if ((i & (i - 1)) == 0)
425 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
428 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
429 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
430 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
435 /* Return true if I is a valid constant for the operation CODE. */
437 const_ok_for_op (i, code, mode)
440 enum machine_mode mode;
442 if (const_ok_for_arm (i))
448 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
450 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
456 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
463 /* Emit a sequence of insns to handle a large constant.
464 CODE is the code of the operation required, it can be any of SET, PLUS,
465 IOR, AND, XOR, MINUS;
466 MODE is the mode in which the operation is being performed;
467 VAL is the integer to operate on;
468 SOURCE is the other operand (a register, or a null-pointer for SET);
469 SUBTARGETS means it is safe to create scratch registers if that will
470 either produce a simpler sequence, or we will want to cse the values.
471 Return value is the number of insns emitted. */
474 arm_split_constant (code, mode, val, target, source, subtargets)
476 enum machine_mode mode;
482 if (subtargets || code == SET
483 || (GET_CODE (target) == REG && GET_CODE (source) == REG
484 && REGNO (target) != REGNO (source)))
486 if (arm_gen_constant (code, mode, val, target, source, 1, 0)
487 > arm_constant_limit + (code != SET))
491 /* Currently SET is the only monadic value for CODE, all
492 the rest are diadic. */
493 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (val)));
498 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
500 emit_insn (gen_rtx (SET, VOIDmode, temp, GEN_INT (val)));
501 /* For MINUS, the value is subtracted from, since we never
502 have subtraction of a constant. */
504 emit_insn (gen_rtx (SET, VOIDmode, target,
505 gen_rtx (code, mode, temp, source)));
507 emit_insn (gen_rtx (SET, VOIDmode, target,
508 gen_rtx (code, mode, source, temp)));
514 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
517 /* As above, but extra parameter GENERATE which, if clear, suppresses
520 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
522 enum machine_mode mode;
531 int can_negate_initial = 0;
534 int num_bits_set = 0;
535 int set_sign_bit_copies = 0;
536 int clear_sign_bit_copies = 0;
537 int clear_zero_bit_copies = 0;
538 int set_zero_bit_copies = 0;
540 unsigned HOST_WIDE_INT temp1, temp2;
541 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
543 /* find out which operations are safe for a given CODE. Also do a quick
544 check for degenerate cases; these can occur when DImode operations
556 can_negate_initial = 1;
560 if (remainder == 0xffffffff)
563 emit_insn (gen_rtx (SET, VOIDmode, target,
564 GEN_INT (ARM_SIGN_EXTEND (val))));
569 if (reload_completed && rtx_equal_p (target, source))
572 emit_insn (gen_rtx (SET, VOIDmode, target, source));
581 emit_insn (gen_rtx (SET, VOIDmode, target, const0_rtx));
584 if (remainder == 0xffffffff)
586 if (reload_completed && rtx_equal_p (target, source))
589 emit_insn (gen_rtx (SET, VOIDmode, target, source));
598 if (reload_completed && rtx_equal_p (target, source))
601 emit_insn (gen_rtx (SET, VOIDmode, target, source));
604 if (remainder == 0xffffffff)
607 emit_insn (gen_rtx (SET, VOIDmode, target,
608 gen_rtx (NOT, mode, source)));
612 /* We don't know how to handle this yet below. */
616 /* We treat MINUS as (val - source), since (source - val) is always
617 passed as (source + (-val)). */
621 emit_insn (gen_rtx (SET, VOIDmode, target,
622 gen_rtx (NEG, mode, source)));
625 if (const_ok_for_arm (val))
628 emit_insn (gen_rtx (SET, VOIDmode, target,
629 gen_rtx (MINUS, mode, GEN_INT (val), source)));
640 /* If we can do it in one insn get out quickly */
641 if (const_ok_for_arm (val)
642 || (can_negate_initial && const_ok_for_arm (-val))
643 || (can_invert && const_ok_for_arm (~val)))
646 emit_insn (gen_rtx (SET, VOIDmode, target,
647 (source ? gen_rtx (code, mode, source,
654 /* Calculate a few attributes that may be useful for specific
657 for (i = 31; i >= 0; i--)
659 if ((remainder & (1 << i)) == 0)
660 clear_sign_bit_copies++;
665 for (i = 31; i >= 0; i--)
667 if ((remainder & (1 << i)) != 0)
668 set_sign_bit_copies++;
673 for (i = 0; i <= 31; i++)
675 if ((remainder & (1 << i)) == 0)
676 clear_zero_bit_copies++;
681 for (i = 0; i <= 31; i++)
683 if ((remainder & (1 << i)) != 0)
684 set_zero_bit_copies++;
692 /* See if we can do this by sign_extending a constant that is known
693 to be negative. This is a good, way of doing it, since the shift
694 may well merge into a subsequent insn. */
695 if (set_sign_bit_copies > 1)
698 (temp1 = ARM_SIGN_EXTEND (remainder
699 << (set_sign_bit_copies - 1))))
703 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
704 emit_insn (gen_rtx (SET, VOIDmode, new_src,
706 emit_insn (gen_ashrsi3 (target, new_src,
707 GEN_INT (set_sign_bit_copies - 1)));
711 /* For an inverted constant, we will need to set the low bits,
712 these will be shifted out of harm's way. */
713 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
714 if (const_ok_for_arm (~temp1))
718 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
719 emit_insn (gen_rtx (SET, VOIDmode, new_src,
721 emit_insn (gen_ashrsi3 (target, new_src,
722 GEN_INT (set_sign_bit_copies - 1)));
728 /* See if we can generate this by setting the bottom (or the top)
729 16 bits, and then shifting these into the other half of the
730 word. We only look for the simplest cases, to do more would cost
731 too much. Be careful, however, not to generate this when the
732 alternative would take fewer insns. */
733 if (val & 0xffff0000)
735 temp1 = remainder & 0xffff0000;
736 temp2 = remainder & 0x0000ffff;
738 /* Overlaps outside this range are best done using other methods. */
739 for (i = 9; i < 24; i++)
741 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
742 && ! const_ok_for_arm (temp2))
744 rtx new_src = (subtargets
745 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
747 insns = arm_gen_constant (code, mode, temp2, new_src,
748 source, subtargets, generate);
751 emit_insn (gen_rtx (SET, VOIDmode, target,
753 gen_rtx (ASHIFT, mode, source,
760 /* Don't duplicate cases already considered. */
761 for (i = 17; i < 24; i++)
763 if (((temp1 | (temp1 >> i)) == remainder)
764 && ! const_ok_for_arm (temp1))
766 rtx new_src = (subtargets
767 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
769 insns = arm_gen_constant (code, mode, temp1, new_src,
770 source, subtargets, generate);
773 emit_insn (gen_rtx (SET, VOIDmode, target,
775 gen_rtx (LSHIFTRT, mode,
776 source, GEN_INT (i)),
786 /* If we have IOR or XOR, and the constant can be loaded in a
787 single instruction, and we can find a temporary to put it in,
788 then this can be done in two instructions instead of 3-4. */
790 /* TARGET can't be NULL if SUBTARGETS is 0 */
791 || (reload_completed && ! reg_mentioned_p (target, source)))
793 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
797 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
799 emit_insn (gen_rtx (SET, VOIDmode, sub, GEN_INT (val)));
800 emit_insn (gen_rtx (SET, VOIDmode, target,
801 gen_rtx (code, mode, source, sub)));
810 if (set_sign_bit_copies > 8
811 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
815 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
816 rtx shift = GEN_INT (set_sign_bit_copies);
818 emit_insn (gen_rtx (SET, VOIDmode, sub,
820 gen_rtx (ASHIFT, mode, source,
822 emit_insn (gen_rtx (SET, VOIDmode, target,
824 gen_rtx (LSHIFTRT, mode, sub,
830 if (set_zero_bit_copies > 8
831 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
835 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
836 rtx shift = GEN_INT (set_zero_bit_copies);
838 emit_insn (gen_rtx (SET, VOIDmode, sub,
840 gen_rtx (LSHIFTRT, mode, source,
842 emit_insn (gen_rtx (SET, VOIDmode, target,
844 gen_rtx (ASHIFT, mode, sub,
850 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
854 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
855 emit_insn (gen_rtx (SET, VOIDmode, sub,
856 gen_rtx (NOT, mode, source)));
859 sub = gen_reg_rtx (mode);
860 emit_insn (gen_rtx (SET, VOIDmode, sub,
861 gen_rtx (AND, mode, source,
863 emit_insn (gen_rtx (SET, VOIDmode, target,
864 gen_rtx (NOT, mode, sub)));
871 /* See if two shifts will do 2 or more insn's worth of work. */
872 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
874 HOST_WIDE_INT shift_mask = ((0xffffffff
875 << (32 - clear_sign_bit_copies))
878 if ((remainder | shift_mask) != 0xffffffff)
882 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
883 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
884 new_src, source, subtargets, 1);
889 rtx targ = subtargets ? NULL_RTX : target;
890 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
891 targ, source, subtargets, 0);
897 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
898 rtx shift = GEN_INT (clear_sign_bit_copies);
900 emit_insn (gen_ashlsi3 (new_src, source, shift));
901 emit_insn (gen_lshrsi3 (target, new_src, shift));
907 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
909 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
911 if ((remainder | shift_mask) != 0xffffffff)
915 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
917 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
918 new_src, source, subtargets, 1);
923 rtx targ = subtargets ? NULL_RTX : target;
925 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
926 targ, source, subtargets, 0);
932 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
933 rtx shift = GEN_INT (clear_zero_bit_copies);
935 emit_insn (gen_lshrsi3 (new_src, source, shift));
936 emit_insn (gen_ashlsi3 (target, new_src, shift));
948 for (i = 0; i < 32; i++)
949 if (remainder & (1 << i))
952 if (code == AND || (can_invert && num_bits_set > 16))
953 remainder = (~remainder) & 0xffffffff;
954 else if (code == PLUS && num_bits_set > 16)
955 remainder = (-remainder) & 0xffffffff;
962 /* Now try and find a way of doing the job in either two or three
964 We start by looking for the largest block of zeros that are aligned on
965 a 2-bit boundary, we then fill up the temps, wrapping around to the
966 top of the word when we drop off the bottom.
967 In the worst case this code should produce no more than four insns. */
970 int best_consecutive_zeros = 0;
972 for (i = 0; i < 32; i += 2)
974 int consecutive_zeros = 0;
976 if (! (remainder & (3 << i)))
978 while ((i < 32) && ! (remainder & (3 << i)))
980 consecutive_zeros += 2;
983 if (consecutive_zeros > best_consecutive_zeros)
985 best_consecutive_zeros = consecutive_zeros;
986 best_start = i - consecutive_zeros;
992 /* Now start emitting the insns, starting with the one with the highest
993 bit set: we do this so that the smallest number will be emitted last;
994 this is more likely to be combinable with addressing insns. */
1002 if (remainder & (3 << (i - 2)))
1007 temp1 = remainder & ((0x0ff << end)
1008 | ((i < end) ? (0xff >> (32 - end)) : 0));
1009 remainder &= ~temp1;
1016 emit_insn (gen_rtx (SET, VOIDmode,
1017 new_src = (subtargets
1018 ? gen_reg_rtx (mode)
1020 GEN_INT (can_invert ? ~temp1 : temp1)));
1021 else if (code == MINUS)
1022 emit_insn (gen_rtx (SET, VOIDmode,
1023 new_src = (subtargets
1024 ? gen_reg_rtx (mode)
1026 gen_rtx (code, mode, GEN_INT (temp1),
1029 emit_insn (gen_rtx (SET, VOIDmode,
1030 new_src = (remainder
1032 ? gen_reg_rtx (mode)
1035 gen_rtx (code, mode, source,
1036 GEN_INT (can_invert ? ~temp1
1048 else if (code == MINUS)
1055 } while (remainder);
1060 /* Canonicalize a comparison so that we are more likely to recognize it.
1061 This can be done for a few constant compares, where we can make the
1062 immediate value easier to load. */
1064 arm_canonicalize_comparison (code, op1)
1068 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1078 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1080 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1082 *op1 = GEN_INT (i+1);
1083 return code == GT ? GE : LT;
1089 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1090 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1092 *op1 = GEN_INT (i-1);
1093 return code == GE ? GT : LE;
1099 if (i != ~((unsigned HOST_WIDE_INT) 0)
1100 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1102 *op1 = GEN_INT (i + 1);
1103 return code == GTU ? GEU : LTU;
1110 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1112 *op1 = GEN_INT (i - 1);
1113 return code == GEU ? GTU : LEU;
1125 /* Handle aggregates that are not laid out in a BLKmode element.
1126 This is a sub-element of RETURN_IN_MEMORY. */
1128 arm_return_in_memory (type)
1131 if (TREE_CODE (type) == RECORD_TYPE)
1135 /* For a struct, we can return in a register if every element was a
1137 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1138 if (TREE_CODE (field) != FIELD_DECL
1139 || ! DECL_BIT_FIELD_TYPE (field))
1144 else if (TREE_CODE (type) == UNION_TYPE)
1148 /* Unions can be returned in registers if every element is
1149 integral, or can be returned in an integer register. */
1150 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1152 if (TREE_CODE (field) != FIELD_DECL
1153 || (AGGREGATE_TYPE_P (TREE_TYPE (field))
1154 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1155 || FLOAT_TYPE_P (TREE_TYPE (field)))
1160 /* XXX Not sure what should be done for other aggregates, so put them in
1166 legitimate_pic_operand_p (x)
1169 if (CONSTANT_P (x) && flag_pic
1170 && (GET_CODE (x) == SYMBOL_REF
1171 || (GET_CODE (x) == CONST
1172 && GET_CODE (XEXP (x, 0)) == PLUS
1173 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1180 legitimize_pic_address (orig, mode, reg)
1182 enum machine_mode mode;
1185 if (GET_CODE (orig) == SYMBOL_REF)
1187 rtx pic_ref, address;
1193 if (reload_in_progress || reload_completed)
1196 reg = gen_reg_rtx (Pmode);
1201 #ifdef AOF_ASSEMBLER
1202 /* The AOF assembler can generate relocations for these directly, and
1203 understands that the PIC register has to be added into the offset.
1205 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1208 address = gen_reg_rtx (Pmode);
1212 emit_insn (gen_pic_load_addr (address, orig));
1214 pic_ref = gen_rtx (MEM, Pmode,
1215 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, address));
1216 RTX_UNCHANGING_P (pic_ref) = 1;
1217 insn = emit_move_insn (reg, pic_ref);
1219 current_function_uses_pic_offset_table = 1;
1220 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1222 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1226 else if (GET_CODE (orig) == CONST)
1230 if (GET_CODE (XEXP (orig, 0)) == PLUS
1231 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1236 if (reload_in_progress || reload_completed)
1239 reg = gen_reg_rtx (Pmode);
1242 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1244 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1245 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1246 base == reg ? 0 : reg);
1251 if (GET_CODE (offset) == CONST_INT)
1253 /* The base register doesn't really matter, we only want to
1254 test the index for the appropriate mode. */
1255 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1257 if (! reload_in_progress && ! reload_completed)
1258 offset = force_reg (Pmode, offset);
1263 if (GET_CODE (offset) == CONST_INT)
1264 return plus_constant_for_output (base, INTVAL (offset));
1267 if (GET_MODE_SIZE (mode) > 4
1268 && (GET_MODE_CLASS (mode) == MODE_INT
1269 || TARGET_SOFT_FLOAT))
1271 emit_insn (gen_addsi3 (reg, base, offset));
1275 return gen_rtx (PLUS, Pmode, base, offset);
1277 else if (GET_CODE (orig) == LABEL_REF)
1278 current_function_uses_pic_offset_table = 1;
1297 #ifndef AOF_ASSEMBLER
1298 rtx l1, pic_tmp, pic_tmp2, seq;
1299 rtx global_offset_table;
1301 if (current_function_uses_pic_offset_table == 0)
1308 l1 = gen_label_rtx ();
1310 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1311 /* The PC contains 'dot'+8, but the label L1 is on the next
1312 instruction, so the offset is only 'dot'+4. */
1313 pic_tmp = gen_rtx (CONST, VOIDmode,
1314 gen_rtx (PLUS, Pmode,
1315 gen_rtx (LABEL_REF, VOIDmode, l1),
1317 pic_tmp2 = gen_rtx (CONST, VOIDmode,
1318 gen_rtx (PLUS, Pmode,
1319 global_offset_table,
1322 pic_rtx = gen_rtx (CONST, Pmode,
1323 gen_rtx (MINUS, Pmode, pic_tmp2, pic_tmp));
1325 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1326 emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx));
1329 seq = gen_sequence ();
1331 emit_insn_after (seq, get_insns ());
1333 /* Need to emit this whether or not we obey regdecls,
1334 since setjmp/longjmp can cause life info to screw up. */
1335 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1336 #endif /* AOF_ASSEMBLER */
1339 #define REG_OR_SUBREG_REG(X) \
1340 (GET_CODE (X) == REG \
1341 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1343 #define REG_OR_SUBREG_RTX(X) \
1344 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1346 #define ARM_FRAME_RTX(X) \
1347 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1348 || (X) == arg_pointer_rtx)
1351 arm_rtx_costs (x, code, outer_code)
1353 enum rtx_code code, outer_code;
1355 enum machine_mode mode = GET_MODE (x);
1356 enum rtx_code subcode;
1362 /* Memory costs quite a lot for the first word, but subsequent words
1363 load at the equivalent of a single insn each. */
1364 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1365 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1372 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1379 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1381 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1382 + ((GET_CODE (XEXP (x, 0)) == REG
1383 || (GET_CODE (XEXP (x, 0)) == SUBREG
1384 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1386 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1387 || (GET_CODE (XEXP (x, 0)) == SUBREG
1388 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1390 + ((GET_CODE (XEXP (x, 1)) == REG
1391 || (GET_CODE (XEXP (x, 1)) == SUBREG
1392 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1393 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1398 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1399 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1400 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1401 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1404 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1405 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1406 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1407 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1409 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1410 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1411 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1414 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1415 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1416 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1417 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1418 || subcode == ASHIFTRT || subcode == LSHIFTRT
1419 || subcode == ROTATE || subcode == ROTATERT
1421 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1422 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1423 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1424 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1425 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1426 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1427 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1432 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1433 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1434 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1435 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1436 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1440 case AND: case XOR: case IOR:
1443 /* Normally the frame registers will be spilt into reg+const during
1444 reload, so it is a bad idea to combine them with other instructions,
1445 since then they might not be moved outside of loops. As a compromise
1446 we allow integration with ops that have a constant as their second
1448 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1449 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1450 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1451 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1452 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1456 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1457 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1458 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1459 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1462 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1463 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1464 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1465 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1466 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1469 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1470 return (1 + extra_cost
1471 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1472 || subcode == LSHIFTRT || subcode == ASHIFTRT
1473 || subcode == ROTATE || subcode == ROTATERT
1475 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1476 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1477 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1478 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1479 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1480 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1486 /* There is no point basing this on the tuning, since it is always the
1487 fast variant if it exists at all */
1488 if (arm_fast_multiply && mode == DImode
1489 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1490 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1491 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1494 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1498 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1500 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1501 & (unsigned HOST_WIDE_INT) 0xffffffff);
1502 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1504 /* Tune as appropriate */
1505 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1507 for (j = 0; i && j < 32; j += booth_unit_size)
1509 i >>= booth_unit_size;
1516 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1517 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1518 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1521 if (arm_fast_multiply && mode == SImode
1522 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1523 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1524 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1525 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1526 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1527 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1532 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1533 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1537 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1539 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1542 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1550 return 4 + (mode == DImode ? 4 : 0);
1553 if (GET_MODE (XEXP (x, 0)) == QImode)
1554 return (4 + (mode == DImode ? 4 : 0)
1555 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1558 switch (GET_MODE (XEXP (x, 0)))
1561 return (1 + (mode == DImode ? 4 : 0)
1562 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1565 return (4 + (mode == DImode ? 4 : 0)
1566 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1569 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1582 arm_adjust_cost (insn, link, dep, cost)
1590 if ((i_pat = single_set (insn)) != NULL
1591 && GET_CODE (SET_SRC (i_pat)) == MEM
1592 && (d_pat = single_set (dep)) != NULL
1593 && GET_CODE (SET_DEST (d_pat)) == MEM)
1595 /* This is a load after a store, there is no conflict if the load reads
1596 from a cached area. Assume that loads from the stack, and from the
1597 constant pool are cached, and that others will miss. This is a
1600 /* debug_rtx (insn);
1603 fprintf (stderr, "costs %d\n", cost); */
1605 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1606 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1607 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1608 || reg_mentioned_p (hard_frame_pointer_rtx,
1609 XEXP (SET_SRC (i_pat), 0)))
1611 /* fprintf (stderr, "***** Now 1\n"); */
1619 /* This code has been fixed for cross compilation. */
1621 static int fpa_consts_inited = 0;
1623 char *strings_fpa[8] = {
1625 "4", "5", "0.5", "10"
1628 static REAL_VALUE_TYPE values_fpa[8];
1636 for (i = 0; i < 8; i++)
1638 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1642 fpa_consts_inited = 1;
1645 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1648 const_double_rtx_ok_for_fpu (x)
1654 if (!fpa_consts_inited)
1657 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1658 if (REAL_VALUE_MINUS_ZERO (r))
1661 for (i = 0; i < 8; i++)
1662 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1668 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1671 neg_const_double_rtx_ok_for_fpu (x)
1677 if (!fpa_consts_inited)
1680 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1681 r = REAL_VALUE_NEGATE (r);
1682 if (REAL_VALUE_MINUS_ZERO (r))
1685 for (i = 0; i < 8; i++)
1686 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1692 /* Predicates for `match_operand' and `match_operator'. */
1694 /* s_register_operand is the same as register_operand, but it doesn't accept
1697 This function exists because at the time it was put in it led to better
1698 code. SUBREG(MEM) always needs a reload in the places where
1699 s_register_operand is used, and this seemed to lead to excessive
1703 s_register_operand (op, mode)
1705 enum machine_mode mode;
1707 if (GET_MODE (op) != mode && mode != VOIDmode)
1710 if (GET_CODE (op) == SUBREG)
1711 op = SUBREG_REG (op);
1713 /* We don't consider registers whose class is NO_REGS
1714 to be a register operand. */
1715 return (GET_CODE (op) == REG
1716 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1717 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1720 /* Only accept reg, subreg(reg), const_int. */
1723 reg_or_int_operand (op, mode)
1725 enum machine_mode mode;
1727 if (GET_CODE (op) == CONST_INT)
1730 if (GET_MODE (op) != mode && mode != VOIDmode)
1733 if (GET_CODE (op) == SUBREG)
1734 op = SUBREG_REG (op);
1736 /* We don't consider registers whose class is NO_REGS
1737 to be a register operand. */
1738 return (GET_CODE (op) == REG
1739 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1740 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1743 /* Return 1 if OP is an item in memory, given that we are in reload. */
1746 reload_memory_operand (op, mode)
1748 enum machine_mode mode;
1750 int regno = true_regnum (op);
1752 return (! CONSTANT_P (op)
1754 || (GET_CODE (op) == REG
1755 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1758 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
1759 memory access (architecture V4) */
1761 bad_signed_byte_operand (op, mode)
1763 enum machine_mode mode;
1765 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
1770 /* A sum of anything more complex than reg + reg or reg + const is bad */
1771 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
1772 && ! s_register_operand (XEXP (op, 0), VOIDmode))
1775 /* Big constants are also bad */
1776 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
1777 && (INTVAL (XEXP (op, 1)) > 0xff
1778 || -INTVAL (XEXP (op, 1)) > 0xff))
1781 /* Everything else is good, or can will automatically be made so. */
1785 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1788 arm_rhs_operand (op, mode)
1790 enum machine_mode mode;
1792 return (s_register_operand (op, mode)
1793 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
1796 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1800 arm_rhsm_operand (op, mode)
1802 enum machine_mode mode;
1804 return (s_register_operand (op, mode)
1805 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
1806 || memory_operand (op, mode));
1809 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1810 constant that is valid when negated. */
1813 arm_add_operand (op, mode)
1815 enum machine_mode mode;
1817 return (s_register_operand (op, mode)
1818 || (GET_CODE (op) == CONST_INT
1819 && (const_ok_for_arm (INTVAL (op))
1820 || const_ok_for_arm (-INTVAL (op)))));
1824 arm_not_operand (op, mode)
1826 enum machine_mode mode;
1828 return (s_register_operand (op, mode)
1829 || (GET_CODE (op) == CONST_INT
1830 && (const_ok_for_arm (INTVAL (op))
1831 || const_ok_for_arm (~INTVAL (op)))));
1834 /* Return TRUE if the operand is a memory reference which contains an
1835 offsettable address. */
1837 offsettable_memory_operand (op, mode)
1839 enum machine_mode mode;
1841 if (mode == VOIDmode)
1842 mode = GET_MODE (op);
1844 return (mode == GET_MODE (op)
1845 && GET_CODE (op) == MEM
1846 && offsettable_address_p (reload_completed | reload_in_progress,
1847 mode, XEXP (op, 0)));
1850 /* Return TRUE if the operand is a memory reference which is, or can be
1851 made word aligned by adjusting the offset. */
1853 alignable_memory_operand (op, mode)
1855 enum machine_mode mode;
1859 if (mode == VOIDmode)
1860 mode = GET_MODE (op);
1862 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
1867 return ((GET_CODE (reg = op) == REG
1868 || (GET_CODE (op) == SUBREG
1869 && GET_CODE (reg = SUBREG_REG (op)) == REG)
1870 || (GET_CODE (op) == PLUS
1871 && GET_CODE (XEXP (op, 1)) == CONST_INT
1872 && (GET_CODE (reg = XEXP (op, 0)) == REG
1873 || (GET_CODE (XEXP (op, 0)) == SUBREG
1874 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
1875 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
1878 /* Similar to s_register_operand, but does not allow hard integer
1881 f_register_operand (op, mode)
1883 enum machine_mode mode;
1885 if (GET_MODE (op) != mode && mode != VOIDmode)
1888 if (GET_CODE (op) == SUBREG)
1889 op = SUBREG_REG (op);
1891 /* We don't consider registers whose class is NO_REGS
1892 to be a register operand. */
1893 return (GET_CODE (op) == REG
1894 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1895 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
1898 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
1901 fpu_rhs_operand (op, mode)
1903 enum machine_mode mode;
1905 if (s_register_operand (op, mode))
1907 else if (GET_CODE (op) == CONST_DOUBLE)
1908 return (const_double_rtx_ok_for_fpu (op));
1914 fpu_add_operand (op, mode)
1916 enum machine_mode mode;
1918 if (s_register_operand (op, mode))
1920 else if (GET_CODE (op) == CONST_DOUBLE)
1921 return (const_double_rtx_ok_for_fpu (op)
1922 || neg_const_double_rtx_ok_for_fpu (op));
1927 /* Return nonzero if OP is a constant power of two. */
1930 power_of_two_operand (op, mode)
1932 enum machine_mode mode;
1934 if (GET_CODE (op) == CONST_INT)
1936 HOST_WIDE_INT value = INTVAL(op);
1937 return value != 0 && (value & (value - 1)) == 0;
1942 /* Return TRUE for a valid operand of a DImode operation.
1943 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1944 Note that this disallows MEM(REG+REG), but allows
1945 MEM(PRE/POST_INC/DEC(REG)). */
1948 di_operand (op, mode)
1950 enum machine_mode mode;
1952 if (s_register_operand (op, mode))
1955 switch (GET_CODE (op))
1962 return memory_address_p (DImode, XEXP (op, 0));
1969 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
1970 Either: REG, CONST_DOUBLE or MEM(DImode_address).
1971 Note that this disallows MEM(REG+REG), but allows
1972 MEM(PRE/POST_INC/DEC(REG)). */
1975 soft_df_operand (op, mode)
1977 enum machine_mode mode;
1979 if (s_register_operand (op, mode))
1982 switch (GET_CODE (op))
1988 return memory_address_p (DFmode, XEXP (op, 0));
1995 /* Return TRUE for valid index operands. */
1998 index_operand (op, mode)
2000 enum machine_mode mode;
2002 return (s_register_operand(op, mode)
2003 || (immediate_operand (op, mode)
2004 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2007 /* Return TRUE for valid shifts by a constant. This also accepts any
2008 power of two on the (somewhat overly relaxed) assumption that the
2009 shift operator in this case was a mult. */
2012 const_shift_operand (op, mode)
2014 enum machine_mode mode;
2016 return (power_of_two_operand (op, mode)
2017 || (immediate_operand (op, mode)
2018 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2021 /* Return TRUE for arithmetic operators which can be combined with a multiply
2025 shiftable_operator (x, mode)
2027 enum machine_mode mode;
2029 if (GET_MODE (x) != mode)
2033 enum rtx_code code = GET_CODE (x);
2035 return (code == PLUS || code == MINUS
2036 || code == IOR || code == XOR || code == AND);
2040 /* Return TRUE for shift operators. */
2043 shift_operator (x, mode)
2045 enum machine_mode mode;
2047 if (GET_MODE (x) != mode)
2051 enum rtx_code code = GET_CODE (x);
2054 return power_of_two_operand (XEXP (x, 1));
2056 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2057 || code == ROTATERT);
2061 int equality_operator (x, mode)
2063 enum machine_mode mode;
2065 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2068 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2071 minmax_operator (x, mode)
2073 enum machine_mode mode;
2075 enum rtx_code code = GET_CODE (x);
2077 if (GET_MODE (x) != mode)
2080 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2083 /* return TRUE if x is EQ or NE */
2085 /* Return TRUE if this is the condition code register, if we aren't given
2086 a mode, accept any class CCmode register */
2089 cc_register (x, mode)
2091 enum machine_mode mode;
2093 if (mode == VOIDmode)
2095 mode = GET_MODE (x);
2096 if (GET_MODE_CLASS (mode) != MODE_CC)
2100 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2106 /* Return TRUE if this is the condition code register, if we aren't given
2107 a mode, accept any class CCmode register which indicates a dominance
2111 dominant_cc_register (x, mode)
2113 enum machine_mode mode;
2115 if (mode == VOIDmode)
2117 mode = GET_MODE (x);
2118 if (GET_MODE_CLASS (mode) != MODE_CC)
2122 if (mode != CC_DNEmode && mode != CC_DEQmode
2123 && mode != CC_DLEmode && mode != CC_DLTmode
2124 && mode != CC_DGEmode && mode != CC_DGTmode
2125 && mode != CC_DLEUmode && mode != CC_DLTUmode
2126 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2129 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2135 /* Return TRUE if X references a SYMBOL_REF. */
2137 symbol_mentioned_p (x)
2143 if (GET_CODE (x) == SYMBOL_REF)
2146 fmt = GET_RTX_FORMAT (GET_CODE (x));
2147 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2153 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2154 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2157 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2164 /* Return TRUE if X references a LABEL_REF. */
2166 label_mentioned_p (x)
2172 if (GET_CODE (x) == LABEL_REF)
2175 fmt = GET_RTX_FORMAT (GET_CODE (x));
2176 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2182 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2183 if (label_mentioned_p (XVECEXP (x, i, j)))
2186 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2197 enum rtx_code code = GET_CODE (x);
2201 else if (code == SMIN)
2203 else if (code == UMIN)
2205 else if (code == UMAX)
2211 /* Return 1 if memory locations are adjacent */
2214 adjacent_mem_locations (a, b)
2217 int val0 = 0, val1 = 0;
2220 if ((GET_CODE (XEXP (a, 0)) == REG
2221 || (GET_CODE (XEXP (a, 0)) == PLUS
2222 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2223 && (GET_CODE (XEXP (b, 0)) == REG
2224 || (GET_CODE (XEXP (b, 0)) == PLUS
2225 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2227 if (GET_CODE (XEXP (a, 0)) == PLUS)
2229 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2230 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2233 reg0 = REGNO (XEXP (a, 0));
2234 if (GET_CODE (XEXP (b, 0)) == PLUS)
2236 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2237 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2240 reg1 = REGNO (XEXP (b, 0));
2241 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2246 /* Return 1 if OP is a load multiple operation. It is known to be
2247 parallel and the first section will be tested. */
2250 load_multiple_operation (op, mode)
2252 enum machine_mode mode;
2254 HOST_WIDE_INT count = XVECLEN (op, 0);
2257 HOST_WIDE_INT i = 1, base = 0;
2261 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2264 /* Check to see if this might be a write-back */
2265 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2270 /* Now check it more carefully */
2271 if (GET_CODE (SET_DEST (elt)) != REG
2272 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2273 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2274 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2275 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2276 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2277 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2278 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2279 != REGNO (SET_DEST (elt)))
2285 /* Perform a quick check so we don't blow up below. */
2287 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2288 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2289 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2292 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2293 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2295 for (; i < count; i++)
2297 elt = XVECEXP (op, 0, i);
2299 if (GET_CODE (elt) != SET
2300 || GET_CODE (SET_DEST (elt)) != REG
2301 || GET_MODE (SET_DEST (elt)) != SImode
2302 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2303 || GET_CODE (SET_SRC (elt)) != MEM
2304 || GET_MODE (SET_SRC (elt)) != SImode
2305 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2306 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2307 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2308 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2315 /* Return 1 if OP is a store multiple operation. It is known to be
2316 parallel and the first section will be tested. */
2319 store_multiple_operation (op, mode)
2321 enum machine_mode mode;
2323 HOST_WIDE_INT count = XVECLEN (op, 0);
2326 HOST_WIDE_INT i = 1, base = 0;
2330 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2333 /* Check to see if this might be a write-back */
2334 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2339 /* Now check it more carefully */
2340 if (GET_CODE (SET_DEST (elt)) != REG
2341 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2342 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2343 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2344 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2345 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2346 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2347 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2348 != REGNO (SET_DEST (elt)))
2354 /* Perform a quick check so we don't blow up below. */
2356 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2357 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2358 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2361 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2362 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2364 for (; i < count; i++)
2366 elt = XVECEXP (op, 0, i);
2368 if (GET_CODE (elt) != SET
2369 || GET_CODE (SET_SRC (elt)) != REG
2370 || GET_MODE (SET_SRC (elt)) != SImode
2371 || REGNO (SET_SRC (elt)) != src_regno + i - base
2372 || GET_CODE (SET_DEST (elt)) != MEM
2373 || GET_MODE (SET_DEST (elt)) != SImode
2374 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2375 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2376 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2377 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2385 load_multiple_sequence (operands, nops, regs, base, load_offset)
2390 HOST_WIDE_INT *load_offset;
2392 int unsorted_regs[4];
2393 HOST_WIDE_INT unsorted_offsets[4];
2398 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2399 extended if required. */
2400 if (nops < 2 || nops > 4)
2403 /* Loop over the operands and check that the memory references are
2404 suitable (ie immediate offsets from the same base register). At
2405 the same time, extract the target register, and the memory
2407 for (i = 0; i < nops; i++)
2412 /* Convert a subreg of a mem into the mem itself. */
2413 if (GET_CODE (operands[nops + i]) == SUBREG)
2414 operands[nops + i] = alter_subreg(operands[nops + i]);
2416 if (GET_CODE (operands[nops + i]) != MEM)
2419 /* Don't reorder volatile memory references; it doesn't seem worth
2420 looking for the case where the order is ok anyway. */
2421 if (MEM_VOLATILE_P (operands[nops + i]))
2424 offset = const0_rtx;
2426 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2427 || (GET_CODE (reg) == SUBREG
2428 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2429 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2430 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2432 || (GET_CODE (reg) == SUBREG
2433 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2434 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2439 base_reg = REGNO(reg);
2440 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2441 ? REGNO (operands[i])
2442 : REGNO (SUBREG_REG (operands[i])));
2447 if (base_reg != REGNO (reg))
2448 /* Not addressed from the same base register. */
2451 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2452 ? REGNO (operands[i])
2453 : REGNO (SUBREG_REG (operands[i])));
2454 if (unsorted_regs[i] < unsorted_regs[order[0]])
2458 /* If it isn't an integer register, or if it overwrites the
2459 base register but isn't the last insn in the list, then
2460 we can't do this. */
2461 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2462 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2465 unsorted_offsets[i] = INTVAL (offset);
2468 /* Not a suitable memory address. */
2472 /* All the useful information has now been extracted from the
2473 operands into unsorted_regs and unsorted_offsets; additionally,
2474 order[0] has been set to the lowest numbered register in the
2475 list. Sort the registers into order, and check that the memory
2476 offsets are ascending and adjacent. */
2478 for (i = 1; i < nops; i++)
2482 order[i] = order[i - 1];
2483 for (j = 0; j < nops; j++)
2484 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2485 && (order[i] == order[i - 1]
2486 || unsorted_regs[j] < unsorted_regs[order[i]]))
2489 /* Have we found a suitable register? if not, one must be used more
2491 if (order[i] == order[i - 1])
2494 /* Is the memory address adjacent and ascending? */
2495 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2503 for (i = 0; i < nops; i++)
2504 regs[i] = unsorted_regs[order[i]];
2506 *load_offset = unsorted_offsets[order[0]];
2509 if (unsorted_offsets[order[0]] == 0)
2510 return 1; /* ldmia */
2512 if (unsorted_offsets[order[0]] == 4)
2513 return 2; /* ldmib */
2515 if (unsorted_offsets[order[nops - 1]] == 0)
2516 return 3; /* ldmda */
2518 if (unsorted_offsets[order[nops - 1]] == -4)
2519 return 4; /* ldmdb */
2521 /* Can't do it without setting up the offset, only do this if it takes
2522 no more than one insn. */
2523 return (const_ok_for_arm (unsorted_offsets[order[0]])
2524 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2528 emit_ldm_seq (operands, nops)
2534 HOST_WIDE_INT offset;
2538 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2541 strcpy (buf, "ldm%?ia\t");
2545 strcpy (buf, "ldm%?ib\t");
2549 strcpy (buf, "ldm%?da\t");
2553 strcpy (buf, "ldm%?db\t");
2558 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2559 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2562 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2563 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2565 output_asm_insn (buf, operands);
2567 strcpy (buf, "ldm%?ia\t");
2574 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2575 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2577 for (i = 1; i < nops; i++)
2578 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2579 reg_names[regs[i]]);
2581 strcat (buf, "}\t%@ phole ldm");
2583 output_asm_insn (buf, operands);
2588 store_multiple_sequence (operands, nops, regs, base, load_offset)
2593 HOST_WIDE_INT *load_offset;
2595 int unsorted_regs[4];
2596 HOST_WIDE_INT unsorted_offsets[4];
2601 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2602 extended if required. */
2603 if (nops < 2 || nops > 4)
2606 /* Loop over the operands and check that the memory references are
2607 suitable (ie immediate offsets from the same base register). At
2608 the same time, extract the target register, and the memory
2610 for (i = 0; i < nops; i++)
2615 /* Convert a subreg of a mem into the mem itself. */
2616 if (GET_CODE (operands[nops + i]) == SUBREG)
2617 operands[nops + i] = alter_subreg(operands[nops + i]);
2619 if (GET_CODE (operands[nops + i]) != MEM)
2622 /* Don't reorder volatile memory references; it doesn't seem worth
2623 looking for the case where the order is ok anyway. */
2624 if (MEM_VOLATILE_P (operands[nops + i]))
2627 offset = const0_rtx;
2629 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2630 || (GET_CODE (reg) == SUBREG
2631 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2632 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2633 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2635 || (GET_CODE (reg) == SUBREG
2636 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2637 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2642 base_reg = REGNO(reg);
2643 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2644 ? REGNO (operands[i])
2645 : REGNO (SUBREG_REG (operands[i])));
2650 if (base_reg != REGNO (reg))
2651 /* Not addressed from the same base register. */
2654 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2655 ? REGNO (operands[i])
2656 : REGNO (SUBREG_REG (operands[i])));
2657 if (unsorted_regs[i] < unsorted_regs[order[0]])
2661 /* If it isn't an integer register, then we can't do this. */
2662 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2665 unsorted_offsets[i] = INTVAL (offset);
2668 /* Not a suitable memory address. */
2672 /* All the useful information has now been extracted from the
2673 operands into unsorted_regs and unsorted_offsets; additionally,
2674 order[0] has been set to the lowest numbered register in the
2675 list. Sort the registers into order, and check that the memory
2676 offsets are ascending and adjacent. */
2678 for (i = 1; i < nops; i++)
2682 order[i] = order[i - 1];
2683 for (j = 0; j < nops; j++)
2684 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2685 && (order[i] == order[i - 1]
2686 || unsorted_regs[j] < unsorted_regs[order[i]]))
2689 /* Have we found a suitable register? if not, one must be used more
2691 if (order[i] == order[i - 1])
2694 /* Is the memory address adjacent and ascending? */
2695 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2703 for (i = 0; i < nops; i++)
2704 regs[i] = unsorted_regs[order[i]];
2706 *load_offset = unsorted_offsets[order[0]];
2709 if (unsorted_offsets[order[0]] == 0)
2710 return 1; /* stmia */
2712 if (unsorted_offsets[order[0]] == 4)
2713 return 2; /* stmib */
2715 if (unsorted_offsets[order[nops - 1]] == 0)
2716 return 3; /* stmda */
2718 if (unsorted_offsets[order[nops - 1]] == -4)
2719 return 4; /* stmdb */
2725 emit_stm_seq (operands, nops)
2731 HOST_WIDE_INT offset;
2735 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2738 strcpy (buf, "stm%?ia\t");
2742 strcpy (buf, "stm%?ib\t");
2746 strcpy (buf, "stm%?da\t");
2750 strcpy (buf, "stm%?db\t");
2757 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2758 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2760 for (i = 1; i < nops; i++)
2761 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2762 reg_names[regs[i]]);
2764 strcat (buf, "}\t%@ phole stm");
2766 output_asm_insn (buf, operands);
2771 multi_register_push (op, mode)
2773 enum machine_mode mode;
2775 if (GET_CODE (op) != PARALLEL
2776 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
2777 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
2778 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
2785 /* Routines for use with attributes */
2787 /* Return nonzero if ATTR is a valid attribute for DECL.
2788 ATTRIBUTES are any existing attributes and ARGS are the arguments
2791 Supported attributes:
2793 naked: don't output any prologue or epilogue code, the user is assumed
2794 to do the right thing. */
2797 arm_valid_machine_decl_attribute (decl, attributes, attr, args)
2803 if (args != NULL_TREE)
2806 if (is_attribute_p ("naked", attr))
2807 return TREE_CODE (decl) == FUNCTION_DECL;
2811 /* Return non-zero if FUNC is a naked function. */
2814 arm_naked_function_p (func)
2819 if (TREE_CODE (func) != FUNCTION_DECL)
2822 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
2823 return a != NULL_TREE;
2826 /* Routines for use in generating RTL */
2829 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
2841 int sign = up ? 1 : -1;
2844 result = gen_rtx (PARALLEL, VOIDmode,
2845 rtvec_alloc (count + (write_back ? 2 : 0)));
2848 XVECEXP (result, 0, 0)
2849 = gen_rtx (SET, GET_MODE (from), from,
2850 plus_constant (from, count * 4 * sign));
2855 for (j = 0; i < count; i++, j++)
2857 mem = gen_rtx (MEM, SImode, plus_constant (from, j * 4 * sign));
2858 RTX_UNCHANGING_P (mem) = unchanging_p;
2859 MEM_IN_STRUCT_P (mem) = in_struct_p;
2861 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode,
2862 gen_rtx (REG, SImode, base_regno + j),
2867 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from);
2873 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
2885 int sign = up ? 1 : -1;
2888 result = gen_rtx (PARALLEL, VOIDmode,
2889 rtvec_alloc (count + (write_back ? 2 : 0)));
2892 XVECEXP (result, 0, 0)
2893 = gen_rtx (SET, GET_MODE (to), to,
2894 plus_constant (to, count * 4 * sign));
2899 for (j = 0; i < count; i++, j++)
2901 mem = gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign));
2902 RTX_UNCHANGING_P (mem) = unchanging_p;
2903 MEM_IN_STRUCT_P (mem) = in_struct_p;
2905 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, mem,
2906 gen_rtx (REG, SImode, base_regno + j));
2910 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to);
2916 arm_gen_movstrqi (operands)
2919 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
2922 rtx st_src, st_dst, fin_src, fin_dst;
2923 rtx part_bytes_reg = NULL;
2925 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
2927 if (GET_CODE (operands[2]) != CONST_INT
2928 || GET_CODE (operands[3]) != CONST_INT
2929 || INTVAL (operands[2]) > 64
2930 || INTVAL (operands[3]) & 3)
2933 st_dst = XEXP (operands[0], 0);
2934 st_src = XEXP (operands[1], 0);
2936 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
2937 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
2938 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
2939 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
2941 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
2942 fin_src = src = copy_to_mode_reg (SImode, st_src);
2944 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
2945 out_words_to_go = INTVAL (operands[2]) / 4;
2946 last_bytes = INTVAL (operands[2]) & 3;
2948 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
2949 part_bytes_reg = gen_rtx (REG, SImode, (in_words_to_go - 1) & 3);
2951 for (i = 0; in_words_to_go >= 2; i+=4)
2953 if (in_words_to_go > 4)
2954 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
2955 src_unchanging_p, src_in_struct_p));
2957 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
2958 FALSE, src_unchanging_p,
2961 if (out_words_to_go)
2963 if (out_words_to_go > 4)
2964 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
2967 else if (out_words_to_go != 1)
2968 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
2976 mem = gen_rtx (MEM, SImode, dst);
2977 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
2978 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
2979 emit_move_insn (mem, gen_rtx (REG, SImode, 0));
2980 if (last_bytes != 0)
2981 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
2985 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
2986 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
2989 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
2990 if (out_words_to_go)
2994 mem = gen_rtx (MEM, SImode, src);
2995 RTX_UNCHANGING_P (mem) = src_unchanging_p;
2996 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
2997 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
2998 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3000 mem = gen_rtx (MEM, SImode, dst);
3001 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3002 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3003 emit_move_insn (mem, sreg);
3004 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3007 if (in_words_to_go) /* Sanity check */
3013 if (in_words_to_go < 0)
3016 mem = gen_rtx (MEM, SImode, src);
3017 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3018 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3019 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3022 if (BYTES_BIG_ENDIAN && last_bytes)
3024 rtx tmp = gen_reg_rtx (SImode);
3026 if (part_bytes_reg == NULL)
3029 /* The bytes we want are in the top end of the word */
3030 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3031 GEN_INT (8 * (4 - last_bytes))));
3032 part_bytes_reg = tmp;
3036 mem = gen_rtx (MEM, QImode, plus_constant (dst, last_bytes - 1));
3037 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3038 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3039 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3042 tmp = gen_reg_rtx (SImode);
3043 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3044 part_bytes_reg = tmp;
3053 if (part_bytes_reg == NULL)
3056 mem = gen_rtx (MEM, QImode, dst);
3057 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3058 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3059 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3062 rtx tmp = gen_reg_rtx (SImode);
3064 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3065 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3066 part_bytes_reg = tmp;
3074 /* Generate a memory reference for a half word, such that it will be loaded
3075 into the top 16 bits of the word. We can assume that the address is
3076 known to be alignable and of the form reg, or plus (reg, const). */
3078 gen_rotated_half_load (memref)
3081 HOST_WIDE_INT offset = 0;
3082 rtx base = XEXP (memref, 0);
3084 if (GET_CODE (base) == PLUS)
3086 offset = INTVAL (XEXP (base, 1));
3087 base = XEXP (base, 0);
3090 /* If we aren't allowed to generate unaligned addresses, then fail. */
3091 if (TARGET_SHORT_BY_BYTES
3092 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3095 base = gen_rtx (MEM, SImode, plus_constant (base, offset & ~2));
3097 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3100 return gen_rtx (ROTATE, SImode, base, GEN_INT (16));
3103 static enum machine_mode
3104 select_dominance_cc_mode (op, x, y, cond_or)
3108 HOST_WIDE_INT cond_or;
3110 enum rtx_code cond1, cond2;
3113 /* Currently we will probably get the wrong result if the individual
3114 comparisons are not simple. This also ensures that it is safe to
3115 reverse a comparison if necessary. */
3116 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3118 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3123 cond1 = reverse_condition (cond1);
3125 /* If the comparisons are not equal, and one doesn't dominate the other,
3126 then we can't do this. */
3128 && ! comparison_dominates_p (cond1, cond2)
3129 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3134 enum rtx_code temp = cond1;
3142 if (cond2 == EQ || ! cond_or)
3147 case LE: return CC_DLEmode;
3148 case LEU: return CC_DLEUmode;
3149 case GE: return CC_DGEmode;
3150 case GEU: return CC_DGEUmode;
3157 if (cond2 == LT || ! cond_or)
3166 if (cond2 == GT || ! cond_or)
3175 if (cond2 == LTU || ! cond_or)
3184 if (cond2 == GTU || ! cond_or)
3192 /* The remaining cases only occur when both comparisons are the
3217 arm_select_cc_mode (op, x, y)
3222 /* All floating point compares return CCFP if it is an equality
3223 comparison, and CCFPE otherwise. */
3224 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3225 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3227 /* A compare with a shifted operand. Because of canonicalization, the
3228 comparison will have to be swapped when we emit the assembler. */
3229 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3230 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3231 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3232 || GET_CODE (x) == ROTATERT))
3235 /* This is a special case that is used by combine to allow a
3236 comparison of a shifted byte load to be split into a zero-extend
3237 followed by a comparison of the shifted integer (only valid for
3238 equalities and unsigned inequalities). */
3239 if (GET_MODE (x) == SImode
3240 && GET_CODE (x) == ASHIFT
3241 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3242 && GET_CODE (XEXP (x, 0)) == SUBREG
3243 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3244 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3245 && (op == EQ || op == NE
3246 || op == GEU || op == GTU || op == LTU || op == LEU)
3247 && GET_CODE (y) == CONST_INT)
3250 /* An operation that sets the condition codes as a side-effect, the
3251 V flag is not set correctly, so we can only use comparisons where
3252 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3254 if (GET_MODE (x) == SImode
3256 && (op == EQ || op == NE || op == LT || op == GE)
3257 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3258 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3259 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3260 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3261 || GET_CODE (x) == LSHIFTRT
3262 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3263 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3266 /* A construct for a conditional compare, if the false arm contains
3267 0, then both conditions must be true, otherwise either condition
3268 must be true. Not all conditions are possible, so CCmode is
3269 returned if it can't be done. */
3270 if (GET_CODE (x) == IF_THEN_ELSE
3271 && (XEXP (x, 2) == const0_rtx
3272 || XEXP (x, 2) == const1_rtx)
3273 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3274 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3275 return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
3276 INTVAL (XEXP (x, 2)));
3278 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3281 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3282 && GET_CODE (x) == PLUS
3283 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3289 /* X and Y are two things to compare using CODE. Emit the compare insn and
3290 return the rtx for register 0 in the proper mode. FP means this is a
3291 floating point compare: I don't think that it is needed on the arm. */
3294 gen_compare_reg (code, x, y, fp)
3299 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3300 rtx cc_reg = gen_rtx (REG, mode, 24);
3302 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
3303 gen_rtx (COMPARE, mode, x, y)));
3309 arm_reload_in_hi (operands)
3312 rtx base = find_replacement (&XEXP (operands[1], 0));
3314 emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx (MEM, QImode, base)));
3315 /* Handle the case where the address is too complex to be offset by 1. */
3316 if (GET_CODE (base) == MINUS
3317 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3319 rtx base_plus = gen_rtx (REG, SImode, REGNO (operands[0]));
3321 emit_insn (gen_rtx (SET, VOIDmode, base_plus, base));
3325 emit_insn (gen_zero_extendqisi2 (gen_rtx (SUBREG, SImode, operands[0], 0),
3326 gen_rtx (MEM, QImode,
3327 plus_constant (base, 1))));
3328 if (BYTES_BIG_ENDIAN)
3329 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3331 gen_rtx (IOR, SImode,
3332 gen_rtx (ASHIFT, SImode,
3333 gen_rtx (SUBREG, SImode,
3338 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3340 gen_rtx (IOR, SImode,
3341 gen_rtx (ASHIFT, SImode,
3344 gen_rtx (SUBREG, SImode, operands[0], 0))));
3348 arm_reload_out_hi (operands)
3351 rtx base = find_replacement (&XEXP (operands[0], 0));
3353 if (BYTES_BIG_ENDIAN)
3355 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3356 gen_rtx (SUBREG, QImode, operands[1], 0)));
3357 emit_insn (gen_lshrsi3 (operands[2],
3358 gen_rtx (SUBREG, SImode, operands[1], 0),
3360 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3361 gen_rtx (SUBREG, QImode, operands[2], 0)));
3365 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3366 gen_rtx (SUBREG, QImode, operands[1], 0)));
3367 emit_insn (gen_lshrsi3 (operands[2],
3368 gen_rtx (SUBREG, SImode, operands[1], 0),
3370 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3371 gen_rtx (SUBREG, QImode, operands[2], 0)));
3375 /* Routines for manipulation of the constant pool. */
3376 /* This is unashamedly hacked from the version in sh.c, since the problem is
3377 extremely similar. */
3379 /* Arm instructions cannot load a large constant into a register,
3380 constants have to come from a pc relative load. The reference of a pc
3381 relative load instruction must be less than 1k infront of the instruction.
3382 This means that we often have to dump a constant inside a function, and
3383 generate code to branch around it.
3385 It is important to minimize this, since the branches will slow things
3386 down and make things bigger.
3388 Worst case code looks like:
3404 We fix this by performing a scan before scheduling, which notices which
3405 instructions need to have their operands fetched from the constant table
3406 and builds the table.
3411 scan, find an instruction which needs a pcrel move. Look forward, find th
3412 last barrier which is within MAX_COUNT bytes of the requirement.
3413 If there isn't one, make one. Process all the instructions between
3414 the find and the barrier.
3416 In the above example, we can tell that L3 is within 1k of L1, so
3417 the first move can be shrunk from the 2 insn+constant sequence into
3418 just 1 insn, and the constant moved to L3 to make:
3429 Then the second move becomes the target for the shortening process.
3435 rtx value; /* Value in table */
3436 HOST_WIDE_INT next_offset;
3437 enum machine_mode mode; /* Mode of value */
3440 /* The maximum number of constants that can fit into one pool, since
3441 the pc relative range is 0...1020 bytes and constants are at least 4
3444 #define MAX_POOL_SIZE (1020/4)
3445 static pool_node pool_vector[MAX_POOL_SIZE];
3446 static int pool_size;
3447 static rtx pool_vector_label;
3449 /* Add a constant to the pool and return its offset within the current
3452 X is the rtx we want to replace. MODE is its mode. On return,
3453 ADDRESS_ONLY will be non-zero if we really want the address of such
3454 a constant, not the constant itself. */
3455 static HOST_WIDE_INT
3456 add_constant (x, mode, address_only)
3458 enum machine_mode mode;
3462 HOST_WIDE_INT offset;
3465 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3466 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3467 x = get_pool_constant (XEXP (x, 0));
3468 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3471 x = get_pool_constant (x);
3473 #ifndef AOF_ASSEMBLER
3474 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3475 x = XVECEXP (x, 0, 0);
3478 #ifdef AOF_ASSEMBLER
3479 /* PIC Symbol references need to be converted into offsets into the
3481 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
3482 x = aof_pic_entry (x);
3483 #endif /* AOF_ASSEMBLER */
3485 /* First see if we've already got it */
3486 for (i = 0; i < pool_size; i++)
3488 if (GET_CODE (x) == pool_vector[i].value->code
3489 && mode == pool_vector[i].mode)
3491 if (GET_CODE (x) == CODE_LABEL)
3493 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3496 if (rtx_equal_p (x, pool_vector[i].value))
3497 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
3501 /* Need a new one */
3502 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
3505 pool_vector_label = gen_label_rtx ();
3507 pool_vector[pool_size].next_offset
3508 += (offset = pool_vector[pool_size - 1].next_offset);
3510 pool_vector[pool_size].value = x;
3511 pool_vector[pool_size].mode = mode;
3516 /* Output the literal table */
3523 scan = emit_label_after (gen_label_rtx (), scan);
3524 scan = emit_insn_after (gen_align_4 (), scan);
3525 scan = emit_label_after (pool_vector_label, scan);
3527 for (i = 0; i < pool_size; i++)
3529 pool_node *p = pool_vector + i;
3531 switch (GET_MODE_SIZE (p->mode))
3534 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
3538 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
3547 scan = emit_insn_after (gen_consttable_end (), scan);
3548 scan = emit_barrier_after (scan);
3552 /* Non zero if the src operand needs to be fixed up */
3554 fixit (src, mode, destreg)
3556 enum machine_mode mode;
3559 if (CONSTANT_P (src))
3561 if (GET_CODE (src) == CONST_INT)
3562 return (! const_ok_for_arm (INTVAL (src))
3563 && ! const_ok_for_arm (~INTVAL (src)));
3564 if (GET_CODE (src) == CONST_DOUBLE)
3565 return (GET_MODE (src) == VOIDmode
3567 || (! const_double_rtx_ok_for_fpu (src)
3568 && ! neg_const_double_rtx_ok_for_fpu (src)));
3569 return symbol_mentioned_p (src);
3571 #ifndef AOF_ASSEMBLER
3572 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
3576 return (mode == SImode && GET_CODE (src) == MEM
3577 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
3578 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
3581 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3583 find_barrier (from, max_count)
3588 rtx found_barrier = 0;
3591 while (from && count < max_count)
3593 if (GET_CODE (from) == BARRIER)
3596 /* Count the length of this insn */
3597 if (GET_CODE (from) == INSN
3598 && GET_CODE (PATTERN (from)) == SET
3599 && CONSTANT_P (SET_SRC (PATTERN (from)))
3600 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
3603 count += get_attr_length (from);
3606 from = NEXT_INSN (from);
3611 /* We didn't find a barrier in time to
3612 dump our stuff, so we'll make one */
3613 rtx label = gen_label_rtx ();
3616 from = PREV_INSN (last);
3618 from = get_last_insn ();
3620 /* Walk back to be just before any jump */
3621 while (GET_CODE (from) == JUMP_INSN
3622 || GET_CODE (from) == NOTE
3623 || GET_CODE (from) == CODE_LABEL)
3624 from = PREV_INSN (from);
3626 from = emit_jump_insn_after (gen_jump (label), from);
3627 JUMP_LABEL (from) = label;
3628 found_barrier = emit_barrier_after (from);
3629 emit_label_after (label, found_barrier);
3630 return found_barrier;
3633 return found_barrier;
3636 /* Non zero if the insn is a move instruction which needs to be fixed. */
3641 if (!INSN_DELETED_P (insn)
3642 && GET_CODE (insn) == INSN
3643 && GET_CODE (PATTERN (insn)) == SET)
3645 rtx pat = PATTERN (insn);
3646 rtx src = SET_SRC (pat);
3647 rtx dst = SET_DEST (pat);
3649 enum machine_mode mode = GET_MODE (dst);
3654 if (GET_CODE (dst) == REG)
3655 destreg = REGNO (dst);
3656 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
3657 destreg = REGNO (SUBREG_REG (dst));
3661 return fixit (src, mode, destreg);
3674 /* The ldr instruction can work with up to a 4k offset, and most constants
3675 will be loaded with one of these instructions; however, the adr
3676 instruction and the ldf instructions only work with a 1k offset. This
3677 code needs to be rewritten to use the 4k offset when possible, and to
3678 adjust when a 1k offset is needed. For now we just use a 1k offset
3682 /* Floating point operands can't work further than 1024 bytes from the
3683 PC, so to make things simple we restrict all loads for such functions.
3685 if (TARGET_HARD_FLOAT)
3689 for (regno = 16; regno < 24; regno++)
3690 if (regs_ever_live[regno])
3700 for (insn = first; insn; insn = NEXT_INSN (insn))
3702 if (broken_move (insn))
3704 /* This is a broken move instruction, scan ahead looking for
3705 a barrier to stick the constant table behind */
3707 rtx barrier = find_barrier (insn, count_size);
3709 /* Now find all the moves between the points and modify them */
3710 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3712 if (broken_move (scan))
3714 /* This is a broken move instruction, add it to the pool */
3715 rtx pat = PATTERN (scan);
3716 rtx src = SET_SRC (pat);
3717 rtx dst = SET_DEST (pat);
3718 enum machine_mode mode = GET_MODE (dst);
3719 HOST_WIDE_INT offset;
3726 /* If this is an HImode constant load, convert it into
3727 an SImode constant load. Since the register is always
3728 32 bits this is safe. We have to do this, since the
3729 load pc-relative instruction only does a 32-bit load. */
3733 if (GET_CODE (dst) != REG)
3735 PUT_MODE (dst, SImode);
3738 offset = add_constant (src, mode, &address_only);
3739 addr = plus_constant (gen_rtx (LABEL_REF, VOIDmode,
3743 /* If we only want the address of the pool entry, or
3744 for wide moves to integer regs we need to split
3745 the address calculation off into a separate insn.
3746 If necessary, the load can then be done with a
3747 load-multiple. This is safe, since we have
3748 already noted the length of such insns to be 8,
3749 and we are immediately over-writing the scratch
3750 we have grabbed with the final result. */
3751 if ((address_only || GET_MODE_SIZE (mode) > 4)
3752 && (scratch = REGNO (dst)) < 16)
3759 reg = gen_rtx (REG, SImode, scratch);
3761 newinsn = emit_insn_after (gen_movaddr (reg, addr),
3768 newsrc = gen_rtx (MEM, mode, addr);
3770 /* XXX Fixme -- I think the following is bogus. */
3771 /* Build a jump insn wrapper around the move instead
3772 of an ordinary insn, because we want to have room for
3773 the target label rtx in fld[7], which an ordinary
3774 insn doesn't have. */
3775 newinsn = emit_jump_insn_after
3776 (gen_rtx (SET, VOIDmode, dst, newsrc), newinsn);
3777 JUMP_LABEL (newinsn) = pool_vector_label;
3779 /* But it's still an ordinary insn */
3780 PUT_CODE (newinsn, INSN);
3788 dump_table (barrier);
3795 /* Routines to output assembly language. */
3797 /* If the rtx is the correct value then return the string of the number.
3798 In this way we can ensure that valid double constants are generated even
3799 when cross compiling. */
3801 fp_immediate_constant (x)
3807 if (!fpa_consts_inited)
3810 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3811 for (i = 0; i < 8; i++)
3812 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3813 return strings_fpa[i];
3818 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
3820 fp_const_from_val (r)
3825 if (! fpa_consts_inited)
3828 for (i = 0; i < 8; i++)
3829 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
3830 return strings_fpa[i];
3835 /* Output the operands of a LDM/STM instruction to STREAM.
3836 MASK is the ARM register set mask of which only bits 0-15 are important.
3837 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
3838 must follow the register list. */
3841 print_multi_reg (stream, instr, mask, hat)
3847 int not_first = FALSE;
3849 fputc ('\t', stream);
3850 fprintf (stream, instr, REGISTER_PREFIX);
3851 fputs (", {", stream);
3852 for (i = 0; i < 16; i++)
3853 if (mask & (1 << i))
3856 fprintf (stream, ", ");
3857 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
3861 fprintf (stream, "}%s\n", hat ? "^" : "");
3864 /* Output a 'call' insn. */
3867 output_call (operands)
3870 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
3872 if (REGNO (operands[0]) == 14)
3874 operands[0] = gen_rtx (REG, SImode, 12);
3875 output_asm_insn ("mov%?\t%0, %|lr", operands);
3877 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3878 output_asm_insn ("mov%?\t%|pc, %0", operands);
3886 int something_changed = 0;
3888 int code = GET_CODE (x0);
3895 if (REGNO (x0) == 14)
3897 *x = gen_rtx (REG, SImode, 12);
3902 /* Scan through the sub-elements and change any references there */
3903 fmt = GET_RTX_FORMAT (code);
3904 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3906 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
3907 else if (fmt[i] == 'E')
3908 for (j = 0; j < XVECLEN (x0, i); j++)
3909 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
3910 return something_changed;
3914 /* Output a 'call' insn that is a reference in memory. */
3917 output_call_mem (operands)
3920 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
3921 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
3923 if (eliminate_lr2ip (&operands[0]))
3924 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
3926 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3927 output_asm_insn ("ldr%?\t%|pc, %0", operands);
3932 /* Output a move from arm registers to an fpu registers.
3933 OPERANDS[0] is an fpu register.
3934 OPERANDS[1] is the first registers of an arm register pair. */
3937 output_mov_long_double_fpu_from_arm (operands)
3940 int arm_reg0 = REGNO (operands[1]);
3946 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3947 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3948 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
3950 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
3951 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
3955 /* Output a move from an fpu register to arm registers.
3956 OPERANDS[0] is the first registers of an arm register pair.
3957 OPERANDS[1] is an fpu register. */
3960 output_mov_long_double_arm_from_fpu (operands)
3963 int arm_reg0 = REGNO (operands[0]);
3969 ops[0] = gen_rtx (REG, SImode, arm_reg0);
3970 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
3971 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
3973 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
3974 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
3978 /* Output a move from arm registers to arm registers of a long double
3979 OPERANDS[0] is the destination.
3980 OPERANDS[1] is the source. */
3982 output_mov_long_double_arm_from_arm (operands)
3985 /* We have to be careful here because the two might overlap */
3986 int dest_start = REGNO (operands[0]);
3987 int src_start = REGNO (operands[1]);
3991 if (dest_start < src_start)
3993 for (i = 0; i < 3; i++)
3995 ops[0] = gen_rtx (REG, SImode, dest_start + i);
3996 ops[1] = gen_rtx (REG, SImode, src_start + i);
3997 output_asm_insn ("mov%?\t%0, %1", ops);
4002 for (i = 2; i >= 0; i--)
4004 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4005 ops[1] = gen_rtx (REG, SImode, src_start + i);
4006 output_asm_insn ("mov%?\t%0, %1", ops);
4014 /* Output a move from arm registers to an fpu registers.
4015 OPERANDS[0] is an fpu register.
4016 OPERANDS[1] is the first registers of an arm register pair. */
4019 output_mov_double_fpu_from_arm (operands)
4022 int arm_reg0 = REGNO (operands[1]);
4027 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4028 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4029 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4030 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4034 /* Output a move from an fpu register to arm registers.
4035 OPERANDS[0] is the first registers of an arm register pair.
4036 OPERANDS[1] is an fpu register. */
4039 output_mov_double_arm_from_fpu (operands)
4042 int arm_reg0 = REGNO (operands[0]);
4048 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4049 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4050 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4051 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4055 /* Output a move between double words.
4056 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4057 or MEM<-REG and all MEMs must be offsettable addresses. */
4060 output_move_double (operands)
4063 enum rtx_code code0 = GET_CODE (operands[0]);
4064 enum rtx_code code1 = GET_CODE (operands[1]);
4069 int reg0 = REGNO (operands[0]);
4071 otherops[0] = gen_rtx (REG, SImode, 1 + reg0);
4074 int reg1 = REGNO (operands[1]);
4078 /* Ensure the second source is not overwritten */
4079 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4080 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4082 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4084 else if (code1 == CONST_DOUBLE)
4086 if (GET_MODE (operands[1]) == DFmode)
4089 union real_extract u;
4091 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4093 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4094 otherops[1] = GEN_INT(l[1]);
4095 operands[1] = GEN_INT(l[0]);
4097 else if (GET_MODE (operands[1]) != VOIDmode)
4099 else if (WORDS_BIG_ENDIAN)
4102 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4103 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4108 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4109 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4111 output_mov_immediate (operands);
4112 output_mov_immediate (otherops);
4114 else if (code1 == CONST_INT)
4116 #if HOST_BITS_PER_WIDE_INT > 32
4117 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4118 what the upper word is. */
4119 if (WORDS_BIG_ENDIAN)
4121 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4122 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4126 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4127 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4130 /* Sign extend the intval into the high-order word */
4131 if (WORDS_BIG_ENDIAN)
4133 otherops[1] = operands[1];
4134 operands[1] = (INTVAL (operands[1]) < 0
4135 ? constm1_rtx : const0_rtx);
4138 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4140 output_mov_immediate (otherops);
4141 output_mov_immediate (operands);
4143 else if (code1 == MEM)
4145 switch (GET_CODE (XEXP (operands[1], 0)))
4148 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4152 abort (); /* Should never happen now */
4156 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4160 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4164 abort (); /* Should never happen now */
4169 output_asm_insn ("adr%?\t%0, %1", operands);
4170 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4174 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
4176 otherops[0] = operands[0];
4177 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4178 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4179 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4181 if (GET_CODE (otherops[2]) == CONST_INT)
4183 switch (INTVAL (otherops[2]))
4186 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4189 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4192 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4195 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4196 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4198 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4201 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4204 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4205 return "ldm%?ia\t%0, %M0";
4209 otherops[1] = adj_offsettable_operand (operands[1], 4);
4210 /* Take care of overlapping base/data reg. */
4211 if (reg_mentioned_p (operands[0], operands[1]))
4213 output_asm_insn ("ldr%?\t%0, %1", otherops);
4214 output_asm_insn ("ldr%?\t%0, %1", operands);
4218 output_asm_insn ("ldr%?\t%0, %1", operands);
4219 output_asm_insn ("ldr%?\t%0, %1", otherops);
4225 abort(); /* Constraints should prevent this */
4227 else if (code0 == MEM && code1 == REG)
4229 if (REGNO (operands[1]) == 12)
4232 switch (GET_CODE (XEXP (operands[0], 0)))
4235 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4239 abort (); /* Should never happen now */
4243 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4247 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4251 abort (); /* Should never happen now */
4255 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4257 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4260 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4264 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4268 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4275 otherops[0] = adj_offsettable_operand (operands[0], 4);
4276 otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1]));
4277 output_asm_insn ("str%?\t%1, %0", operands);
4278 output_asm_insn ("str%?\t%1, %0", otherops);
4282 abort(); /* Constraints should prevent this */
4288 /* Output an arbitrary MOV reg, #n.
4289 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4292 output_mov_immediate (operands)
4295 HOST_WIDE_INT n = INTVAL (operands[1]);
4299 /* Try to use one MOV */
4300 if (const_ok_for_arm (n))
4302 output_asm_insn ("mov%?\t%0, %1", operands);
4306 /* Try to use one MVN */
4307 if (const_ok_for_arm (~n))
4309 operands[1] = GEN_INT (~n);
4310 output_asm_insn ("mvn%?\t%0, %1", operands);
4314 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4316 for (i=0; i < 32; i++)
4320 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4321 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4324 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4331 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4332 adding zero to one register, output nothing. */
4335 output_add_immediate (operands)
4338 HOST_WIDE_INT n = INTVAL (operands[2]);
4340 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4343 output_multi_immediate (operands,
4344 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4347 output_multi_immediate (operands,
4348 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4355 /* Output a multiple immediate operation.
4356 OPERANDS is the vector of operands referred to in the output patterns.
4357 INSTR1 is the output pattern to use for the first constant.
4358 INSTR2 is the output pattern to use for subsequent constants.
4359 IMMED_OP is the index of the constant slot in OPERANDS.
4360 N is the constant value. */
4363 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4365 char *instr1, *instr2;
4369 #if HOST_BITS_PER_WIDE_INT > 32
4375 operands[immed_op] = const0_rtx;
4376 output_asm_insn (instr1, operands); /* Quick and easy output */
4381 char *instr = instr1;
4383 /* Note that n is never zero here (which would give no output) */
4384 for (i = 0; i < 32; i += 2)
4388 operands[immed_op] = GEN_INT (n & (255 << i));
4389 output_asm_insn (instr, operands);
4399 /* Return the appropriate ARM instruction for the operation code.
4400 The returned result should not be overwritten. OP is the rtx of the
4401 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4405 arithmetic_instr (op, shift_first_arg)
4407 int shift_first_arg;
4409 switch (GET_CODE (op))
4415 return shift_first_arg ? "rsb" : "sub";
4432 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4433 for the operation code. The returned result should not be overwritten.
4434 OP is the rtx code of the shift.
4435 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4439 shift_op (op, amountp)
4441 HOST_WIDE_INT *amountp;
4444 enum rtx_code code = GET_CODE (op);
4446 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
4448 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
4449 *amountp = INTVAL (XEXP (op, 1));
4472 /* We never have to worry about the amount being other than a
4473 power of 2, since this case can never be reloaded from a reg. */
4475 *amountp = int_log2 (*amountp);
4486 /* This is not 100% correct, but follows from the desire to merge
4487 multiplication by a power of 2 with the recognizer for a
4488 shift. >=32 is not a valid shift for "asl", so we must try and
4489 output a shift that produces the correct arithmetical result.
4490 Using lsr #32 is identical except for the fact that the carry bit
4491 is not set correctly if we set the flags; but we never use the
4492 carry bit from such an operation, so we can ignore that. */
4493 if (code == ROTATERT)
4494 *amountp &= 31; /* Rotate is just modulo 32 */
4495 else if (*amountp != (*amountp & 31))
4502 /* Shifts of 0 are no-ops. */
4511 /* Obtain the shift from the POWER of two. */
4513 static HOST_WIDE_INT
4515 HOST_WIDE_INT power;
4517 HOST_WIDE_INT shift = 0;
4519 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
4529 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4530 /bin/as is horribly restrictive. */
4533 output_ascii_pseudo_op (stream, p, len)
4539 int len_so_far = 1000;
4540 int chars_so_far = 0;
4542 for (i = 0; i < len; i++)
4544 register int c = p[i];
4546 if (len_so_far > 50)
4549 fputs ("\"\n", stream);
4550 fputs ("\t.ascii\t\"", stream);
4555 if (c == '\"' || c == '\\')
4561 if (c >= ' ' && c < 0177)
4568 fprintf (stream, "\\%03o", c);
4575 fputs ("\"\n", stream);
4579 /* Try to determine whether a pattern really clobbers the link register.
4580 This information is useful when peepholing, so that lr need not be pushed
4581 if we combine a call followed by a return.
4582 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4583 such a check should not be needed because these only update an existing
4584 value within a register; the register must still be set elsewhere within
4588 pattern_really_clobbers_lr (x)
4593 switch (GET_CODE (x))
4596 switch (GET_CODE (SET_DEST (x)))
4599 return REGNO (SET_DEST (x)) == 14;
4602 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
4603 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
4605 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
4614 for (i = 0; i < XVECLEN (x, 0); i++)
4615 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
4620 switch (GET_CODE (XEXP (x, 0)))
4623 return REGNO (XEXP (x, 0)) == 14;
4626 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
4627 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
4643 function_really_clobbers_lr (first)
4648 for (insn = first; insn; insn = next_nonnote_insn (insn))
4650 switch (GET_CODE (insn))
4655 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
4660 if (pattern_really_clobbers_lr (PATTERN (insn)))
4665 /* Don't yet know how to handle those calls that are not to a
4667 if (GET_CODE (PATTERN (insn)) != PARALLEL)
4670 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
4673 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
4679 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
4685 default: /* Don't recognize it, be safe */
4689 /* A call can be made (by peepholing) not to clobber lr iff it is
4690 followed by a return. There may, however, be a use insn iff
4691 we are returning the result of the call.
4692 If we run off the end of the insn chain, then that means the
4693 call was at the end of the function. Unfortunately we don't
4694 have a return insn for the peephole to recognize, so we
4695 must reject this. (Can this be fixed by adding our own insn?) */
4696 if ((next = next_nonnote_insn (insn)) == NULL)
4699 /* No need to worry about lr if the call never returns */
4700 if (GET_CODE (next) == BARRIER)
4703 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
4704 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4705 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
4706 == REGNO (XEXP (PATTERN (next), 0))))
4707 if ((next = next_nonnote_insn (next)) == NULL)
4710 if (GET_CODE (next) == JUMP_INSN
4711 && GET_CODE (PATTERN (next)) == RETURN)
4720 /* We have reached the end of the chain so lr was _not_ clobbered */
4725 output_return_instruction (operand, really_return, reverse)
4731 int reg, live_regs = 0;
4732 int volatile_func = (optimize > 0
4733 && TREE_THIS_VOLATILE (current_function_decl));
4735 return_used_this_function = 1;
4740 /* If this function was declared non-returning, and we have found a tail
4741 call, then we have to trust that the called function won't return. */
4742 if (! really_return)
4745 /* Otherwise, trap an attempted return by aborting. */
4747 ops[1] = gen_rtx (SYMBOL_REF, Pmode, "abort");
4748 assemble_external_libcall (ops[1]);
4749 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
4753 if (current_function_calls_alloca && ! really_return)
4756 for (reg = 0; reg <= 10; reg++)
4757 if (regs_ever_live[reg] && ! call_used_regs[reg])
4760 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
4763 if (frame_pointer_needed)
4768 if (lr_save_eliminated || ! regs_ever_live[14])
4771 if (frame_pointer_needed)
4773 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
4776 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
4778 for (reg = 0; reg <= 10; reg++)
4779 if (regs_ever_live[reg] && ! call_used_regs[reg])
4781 strcat (instr, "%|");
4782 strcat (instr, reg_names[reg]);
4784 strcat (instr, ", ");
4787 if (frame_pointer_needed)
4789 strcat (instr, "%|");
4790 strcat (instr, reg_names[11]);
4791 strcat (instr, ", ");
4792 strcat (instr, "%|");
4793 strcat (instr, reg_names[13]);
4794 strcat (instr, ", ");
4795 strcat (instr, "%|");
4796 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4800 strcat (instr, "%|");
4801 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4803 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
4804 output_asm_insn (instr, &operand);
4806 else if (really_return)
4808 if (TARGET_THUMB_INTERWORK)
4809 sprintf (instr, "bx%%?%%%s\t%%|lr", reverse ? "D" : "d");
4811 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
4812 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
4813 output_asm_insn (instr, &operand);
4819 /* Return nonzero if optimizing and the current function is volatile.
4820 Such functions never return, and many memory cycles can be saved
4821 by not storing register values that will never be needed again.
4822 This optimization was added to speed up context switching in a
4823 kernel application. */
4826 arm_volatile_func ()
4828 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
4831 /* The amount of stack adjustment that happens here, in output_return and in
4832 output_epilogue must be exactly the same as was calculated during reload,
4833 or things will point to the wrong place. The only time we can safely
4834 ignore this constraint is when a function has no arguments on the stack,
4835 no stack frame requirement and no live registers execpt for `lr'. If we
4836 can guarantee that by making all function calls into tail calls and that
4837 lr is not clobbered in any other way, then there is no need to push lr
4841 output_func_prologue (f, frame_size)
4845 int reg, live_regs_mask = 0;
4846 int volatile_func = (optimize > 0
4847 && TREE_THIS_VOLATILE (current_function_decl));
4849 /* Nonzero if we must stuff some register arguments onto the stack as if
4850 they were passed there. */
4851 int store_arg_regs = 0;
4853 if (arm_ccfsm_state || arm_target_insn)
4854 abort (); /* Sanity check */
4856 if (arm_naked_function_p (current_function_decl))
4859 return_used_this_function = 0;
4860 lr_save_eliminated = 0;
4862 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
4863 ASM_COMMENT_START, current_function_args_size,
4864 current_function_pretend_args_size, frame_size);
4865 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
4866 ASM_COMMENT_START, frame_pointer_needed,
4867 current_function_anonymous_args);
4870 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
4872 if (current_function_anonymous_args && current_function_pretend_args_size)
4875 for (reg = 0; reg <= 10; reg++)
4876 if (regs_ever_live[reg] && ! call_used_regs[reg])
4877 live_regs_mask |= (1 << reg);
4879 if (frame_pointer_needed)
4880 live_regs_mask |= 0xD800;
4881 else if (regs_ever_live[14])
4883 if (! current_function_args_size
4884 && ! function_really_clobbers_lr (get_insns ()))
4885 lr_save_eliminated = 1;
4887 live_regs_mask |= 0x4000;
4892 /* if a di mode load/store multiple is used, and the base register
4893 is r3, then r4 can become an ever live register without lr
4894 doing so, in this case we need to push lr as well, or we
4895 will fail to get a proper return. */
4897 live_regs_mask |= 0x4000;
4898 lr_save_eliminated = 0;
4902 if (lr_save_eliminated)
4903 fprintf (f,"\t%s I don't think this function clobbers lr\n",
4906 #ifdef AOF_ASSEMBLER
4908 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
4909 reg_names[PIC_OFFSET_TABLE_REGNUM]);
4915 output_func_epilogue (f, frame_size)
4919 int reg, live_regs_mask = 0;
4920 /* If we need this then it will always be at least this much */
4921 int floats_offset = 12;
4923 int volatile_func = (optimize > 0
4924 && TREE_THIS_VOLATILE (current_function_decl));
4926 if (use_return_insn() && return_used_this_function)
4928 if ((frame_size + current_function_outgoing_args_size) != 0
4929 && !(frame_pointer_needed || TARGET_APCS))
4934 /* Naked functions don't have epilogues. */
4935 if (arm_naked_function_p (current_function_decl))
4938 /* A volatile function should never return. Call abort. */
4941 rtx op = gen_rtx (SYMBOL_REF, Pmode, "abort");
4942 assemble_external_libcall (op);
4943 output_asm_insn ("bl\t%a0", &op);
4947 for (reg = 0; reg <= 10; reg++)
4948 if (regs_ever_live[reg] && ! call_used_regs[reg])
4950 live_regs_mask |= (1 << reg);
4954 if (frame_pointer_needed)
4956 if (arm_fpu_arch == FP_SOFT2)
4958 for (reg = 23; reg > 15; reg--)
4959 if (regs_ever_live[reg] && ! call_used_regs[reg])
4961 floats_offset += 12;
4962 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
4963 reg_names[reg], REGISTER_PREFIX, floats_offset);
4970 for (reg = 23; reg > 15; reg--)
4972 if (regs_ever_live[reg] && ! call_used_regs[reg])
4974 floats_offset += 12;
4975 /* We can't unstack more than four registers at once */
4976 if (start_reg - reg == 3)
4978 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
4979 REGISTER_PREFIX, reg_names[reg],
4980 REGISTER_PREFIX, floats_offset);
4981 start_reg = reg - 1;
4986 if (reg != start_reg)
4987 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
4988 REGISTER_PREFIX, reg_names[reg + 1],
4989 start_reg - reg, REGISTER_PREFIX, floats_offset);
4991 start_reg = reg - 1;
4995 /* Just in case the last register checked also needs unstacking. */
4996 if (reg != start_reg)
4997 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
4998 REGISTER_PREFIX, reg_names[reg + 1],
4999 start_reg - reg, REGISTER_PREFIX, floats_offset);
5002 if (TARGET_THUMB_INTERWORK)
5004 live_regs_mask |= 0x6800;
5005 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5006 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5010 live_regs_mask |= 0xA800;
5011 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5012 TARGET_APCS_32 ? FALSE : TRUE);
5017 /* Restore stack pointer if necessary. */
5018 if (frame_size + current_function_outgoing_args_size != 0)
5020 operands[0] = operands[1] = stack_pointer_rtx;
5021 operands[2] = GEN_INT (frame_size
5022 + current_function_outgoing_args_size);
5023 output_add_immediate (operands);
5026 if (arm_fpu_arch == FP_SOFT2)
5028 for (reg = 16; reg < 24; reg++)
5029 if (regs_ever_live[reg] && ! call_used_regs[reg])
5030 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5031 reg_names[reg], REGISTER_PREFIX);
5037 for (reg = 16; reg < 24; reg++)
5039 if (regs_ever_live[reg] && ! call_used_regs[reg])
5041 if (reg - start_reg == 3)
5043 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5044 REGISTER_PREFIX, reg_names[start_reg],
5046 start_reg = reg + 1;
5051 if (reg != start_reg)
5052 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5053 REGISTER_PREFIX, reg_names[start_reg],
5054 reg - start_reg, REGISTER_PREFIX);
5056 start_reg = reg + 1;
5060 /* Just in case the last register checked also needs unstacking. */
5061 if (reg != start_reg)
5062 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5063 REGISTER_PREFIX, reg_names[start_reg],
5064 reg - start_reg, REGISTER_PREFIX);
5067 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5069 if (TARGET_THUMB_INTERWORK)
5071 if (! lr_save_eliminated)
5072 print_multi_reg(f, "ldmfd\t%ssp!", live_regs_mask | 0x4000,
5075 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5077 else if (lr_save_eliminated)
5078 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5079 : "\tmovs\t%spc, %slr\n"),
5080 REGISTER_PREFIX, REGISTER_PREFIX, f);
5082 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5083 TARGET_APCS_32 ? FALSE : TRUE);
5087 if (live_regs_mask || regs_ever_live[14])
5089 /* Restore the integer regs, and the return address into lr */
5090 if (! lr_save_eliminated)
5091 live_regs_mask |= 0x4000;
5093 if (live_regs_mask != 0)
5094 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5097 if (current_function_pretend_args_size)
5099 /* Unwind the pre-pushed regs */
5100 operands[0] = operands[1] = stack_pointer_rtx;
5101 operands[2] = GEN_INT (current_function_pretend_args_size);
5102 output_add_immediate (operands);
5104 /* And finally, go home */
5105 if (TARGET_THUMB_INTERWORK)
5106 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5108 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5109 : "\tmovs\t%spc, %slr\n"),
5110 REGISTER_PREFIX, REGISTER_PREFIX, f);
5116 current_function_anonymous_args = 0;
5120 emit_multi_reg_push (mask)
5127 for (i = 0; i < 16; i++)
5128 if (mask & (1 << i))
5131 if (num_regs == 0 || num_regs > 16)
5134 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num_regs));
5136 for (i = 0; i < 16; i++)
5138 if (mask & (1 << i))
5141 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, BLKmode,
5142 gen_rtx (PRE_DEC, BLKmode,
5143 stack_pointer_rtx)),
5144 gen_rtx (UNSPEC, BLKmode,
5145 gen_rtvec (1, gen_rtx (REG, SImode, i)),
5151 for (j = 1, i++; j < num_regs; i++)
5153 if (mask & (1 << i))
5156 = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, i));
5165 emit_sfm (base_reg, count)
5172 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5174 XVECEXP (par, 0, 0) = gen_rtx (SET, VOIDmode,
5175 gen_rtx (MEM, BLKmode,
5176 gen_rtx (PRE_DEC, BLKmode,
5177 stack_pointer_rtx)),
5178 gen_rtx (UNSPEC, BLKmode,
5179 gen_rtvec (1, gen_rtx (REG, XFmode,
5182 for (i = 1; i < count; i++)
5183 XVECEXP (par, 0, i) = gen_rtx (USE, VOIDmode,
5184 gen_rtx (REG, XFmode, base_reg++));
5190 arm_expand_prologue ()
5193 rtx amount = GEN_INT (-(get_frame_size ()
5194 + current_function_outgoing_args_size));
5195 int live_regs_mask = 0;
5196 int store_arg_regs = 0;
5197 int volatile_func = (optimize > 0
5198 && TREE_THIS_VOLATILE (current_function_decl));
5200 /* Naked functions don't have prologues. */
5201 if (arm_naked_function_p (current_function_decl))
5204 if (current_function_anonymous_args && current_function_pretend_args_size)
5207 if (! volatile_func)
5208 for (reg = 0; reg <= 10; reg++)
5209 if (regs_ever_live[reg] && ! call_used_regs[reg])
5210 live_regs_mask |= 1 << reg;
5212 if (! volatile_func && regs_ever_live[14])
5213 live_regs_mask |= 0x4000;
5215 if (frame_pointer_needed)
5217 live_regs_mask |= 0xD800;
5218 emit_insn (gen_movsi (gen_rtx (REG, SImode, 12),
5219 stack_pointer_rtx));
5222 if (current_function_pretend_args_size)
5225 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5228 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5229 GEN_INT (-current_function_pretend_args_size)));
5234 /* If we have to push any regs, then we must push lr as well, or
5235 we won't get a proper return. */
5236 live_regs_mask |= 0x4000;
5237 emit_multi_reg_push (live_regs_mask);
5240 /* For now the integer regs are still pushed in output_func_epilogue (). */
5242 if (! volatile_func)
5244 if (arm_fpu_arch == FP_SOFT2)
5246 for (reg = 23; reg > 15; reg--)
5247 if (regs_ever_live[reg] && ! call_used_regs[reg])
5248 emit_insn (gen_rtx (SET, VOIDmode,
5249 gen_rtx (MEM, XFmode,
5250 gen_rtx (PRE_DEC, XFmode,
5251 stack_pointer_rtx)),
5252 gen_rtx (REG, XFmode, reg)));
5258 for (reg = 23; reg > 15; reg--)
5260 if (regs_ever_live[reg] && ! call_used_regs[reg])
5262 if (start_reg - reg == 3)
5265 start_reg = reg - 1;
5270 if (start_reg != reg)
5271 emit_sfm (reg + 1, start_reg - reg);
5272 start_reg = reg - 1;
5276 if (start_reg != reg)
5277 emit_sfm (reg + 1, start_reg - reg);
5281 if (frame_pointer_needed)
5282 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx (REG, SImode, 12),
5284 (-(4 + current_function_pretend_args_size)))));
5286 if (amount != const0_rtx)
5288 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5289 emit_insn (gen_rtx (CLOBBER, VOIDmode,
5290 gen_rtx (MEM, BLKmode, stack_pointer_rtx)));
5293 /* If we are profiling, make sure no instructions are scheduled before
5294 the call to mcount. */
5295 if (profile_flag || profile_block_flag)
5296 emit_insn (gen_blockage ());
5300 /* If CODE is 'd', then the X is a condition operand and the instruction
5301 should only be executed if the condition is true.
5302 if CODE is 'D', then the X is a condition operand and the instruction
5303 should only be executed if the condition is false: however, if the mode
5304 of the comparison is CCFPEmode, then always execute the instruction -- we
5305 do this because in these circumstances !GE does not necessarily imply LT;
5306 in these cases the instruction pattern will take care to make sure that
5307 an instruction containing %d will follow, thereby undoing the effects of
5308 doing this instruction unconditionally.
5309 If CODE is 'N' then X is a floating point operand that must be negated
5311 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5312 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5315 arm_print_operand (stream, x, code)
5323 fputs (ASM_COMMENT_START, stream);
5327 fputs (REGISTER_PREFIX, stream);
5331 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5332 fputs (arm_condition_codes[arm_current_cc], stream);
5338 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5339 r = REAL_VALUE_NEGATE (r);
5340 fprintf (stream, "%s", fp_const_from_val (&r));
5345 if (GET_CODE (x) == CONST_INT)
5347 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5352 ARM_SIGN_EXTEND (~ INTVAL (x)));
5356 output_addr_const (stream, x);
5361 fprintf (stream, "%s", arithmetic_instr (x, 1));
5365 fprintf (stream, "%s", arithmetic_instr (x, 0));
5371 char *shift = shift_op (x, &val);
5375 fprintf (stream, ", %s ", shift_op (x, &val));
5377 arm_print_operand (stream, XEXP (x, 1), 0);
5380 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5393 fputs (REGISTER_PREFIX, stream);
5394 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
5400 fputs (REGISTER_PREFIX, stream);
5401 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
5405 fputs (REGISTER_PREFIX, stream);
5406 if (GET_CODE (XEXP (x, 0)) == REG)
5407 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
5409 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
5413 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
5414 REGISTER_PREFIX, reg_names[REGNO (x) - 1
5415 + ((GET_MODE_SIZE (GET_MODE (x))
5416 + GET_MODE_SIZE (SImode) - 1)
5417 / GET_MODE_SIZE (SImode))]);
5422 fputs (arm_condition_codes[get_arm_condition_code (x)],
5428 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
5429 (get_arm_condition_code (x))],
5437 if (GET_CODE (x) == REG)
5439 fputs (REGISTER_PREFIX, stream);
5440 fputs (reg_names[REGNO (x)], stream);
5442 else if (GET_CODE (x) == MEM)
5444 output_memory_reference_mode = GET_MODE (x);
5445 output_address (XEXP (x, 0));
5447 else if (GET_CODE (x) == CONST_DOUBLE)
5448 fprintf (stream, "#%s", fp_immediate_constant (x));
5449 else if (GET_CODE (x) == NEG)
5450 abort (); /* This should never happen now. */
5453 fputc ('#', stream);
5454 output_addr_const (stream, x);
5460 /* A finite state machine takes care of noticing whether or not instructions
5461 can be conditionally executed, and thus decrease execution time and code
5462 size by deleting branch instructions. The fsm is controlled by
5463 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
5465 /* The state of the fsm controlling condition codes are:
5466 0: normal, do nothing special
5467 1: make ASM_OUTPUT_OPCODE not output this instruction
5468 2: make ASM_OUTPUT_OPCODE not output this instruction
5469 3: make instructions conditional
5470 4: make instructions conditional
5472 State transitions (state->state by whom under condition):
5473 0 -> 1 final_prescan_insn if the `target' is a label
5474 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
5475 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
5476 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
5477 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
5478 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
5479 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
5480 (the target insn is arm_target_insn).
5482 If the jump clobbers the conditions then we use states 2 and 4.
5484 A similar thing can be done with conditional return insns.
5486 XXX In case the `target' is an unconditional branch, this conditionalising
5487 of the instructions always reduces code size, but not always execution
5488 time. But then, I want to reduce the code size to somewhere near what
5489 /bin/cc produces. */
5491 /* Returns the index of the ARM condition code string in
5492 `arm_condition_codes'. COMPARISON should be an rtx like
5493 `(eq (...) (...))'. */
5495 static enum arm_cond_code
5496 get_arm_condition_code (comparison)
5499 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
5501 register enum rtx_code comp_code = GET_CODE (comparison);
5503 if (GET_MODE_CLASS (mode) != MODE_CC)
5504 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
5505 XEXP (comparison, 1));
5509 case CC_DNEmode: code = ARM_NE; goto dominance;
5510 case CC_DEQmode: code = ARM_EQ; goto dominance;
5511 case CC_DGEmode: code = ARM_GE; goto dominance;
5512 case CC_DGTmode: code = ARM_GT; goto dominance;
5513 case CC_DLEmode: code = ARM_LE; goto dominance;
5514 case CC_DLTmode: code = ARM_LT; goto dominance;
5515 case CC_DGEUmode: code = ARM_CS; goto dominance;
5516 case CC_DGTUmode: code = ARM_HI; goto dominance;
5517 case CC_DLEUmode: code = ARM_LS; goto dominance;
5518 case CC_DLTUmode: code = ARM_CC;
5521 if (comp_code != EQ && comp_code != NE)
5524 if (comp_code == EQ)
5525 return ARM_INVERSE_CONDITION_CODE (code);
5531 case NE: return ARM_NE;
5532 case EQ: return ARM_EQ;
5533 case GE: return ARM_PL;
5534 case LT: return ARM_MI;
5542 case NE: return ARM_NE;
5543 case EQ: return ARM_EQ;
5550 case GE: return ARM_GE;
5551 case GT: return ARM_GT;
5552 case LE: return ARM_LS;
5553 case LT: return ARM_MI;
5560 case NE: return ARM_NE;
5561 case EQ: return ARM_EQ;
5562 case GE: return ARM_LE;
5563 case GT: return ARM_LT;
5564 case LE: return ARM_GE;
5565 case LT: return ARM_GT;
5566 case GEU: return ARM_LS;
5567 case GTU: return ARM_CC;
5568 case LEU: return ARM_CS;
5569 case LTU: return ARM_HI;
5576 case LTU: return ARM_CS;
5577 case GEU: return ARM_CC;
5584 case NE: return ARM_NE;
5585 case EQ: return ARM_EQ;
5586 case GE: return ARM_GE;
5587 case GT: return ARM_GT;
5588 case LE: return ARM_LE;
5589 case LT: return ARM_LT;
5590 case GEU: return ARM_CS;
5591 case GTU: return ARM_HI;
5592 case LEU: return ARM_LS;
5593 case LTU: return ARM_CC;
5605 final_prescan_insn (insn, opvec, noperands)
5610 /* BODY will hold the body of INSN. */
5611 register rtx body = PATTERN (insn);
5613 /* This will be 1 if trying to repeat the trick, and things need to be
5614 reversed if it appears to fail. */
5617 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5618 taken are clobbered, even if the rtl suggests otherwise. It also
5619 means that we have to grub around within the jump expression to find
5620 out what the conditions are when the jump isn't taken. */
5621 int jump_clobbers = 0;
5623 /* If we start with a return insn, we only succeed if we find another one. */
5624 int seeking_return = 0;
5626 /* START_INSN will hold the insn from where we start looking. This is the
5627 first insn after the following code_label if REVERSE is true. */
5628 rtx start_insn = insn;
5630 /* If in state 4, check if the target branch is reached, in order to
5631 change back to state 0. */
5632 if (arm_ccfsm_state == 4)
5634 if (insn == arm_target_insn)
5636 arm_target_insn = NULL;
5637 arm_ccfsm_state = 0;
5642 /* If in state 3, it is possible to repeat the trick, if this insn is an
5643 unconditional branch to a label, and immediately following this branch
5644 is the previous target label which is only used once, and the label this
5645 branch jumps to is not too far off. */
5646 if (arm_ccfsm_state == 3)
5648 if (simplejump_p (insn))
5650 start_insn = next_nonnote_insn (start_insn);
5651 if (GET_CODE (start_insn) == BARRIER)
5653 /* XXX Isn't this always a barrier? */
5654 start_insn = next_nonnote_insn (start_insn);
5656 if (GET_CODE (start_insn) == CODE_LABEL
5657 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5658 && LABEL_NUSES (start_insn) == 1)
5663 else if (GET_CODE (body) == RETURN)
5665 start_insn = next_nonnote_insn (start_insn);
5666 if (GET_CODE (start_insn) == BARRIER)
5667 start_insn = next_nonnote_insn (start_insn);
5668 if (GET_CODE (start_insn) == CODE_LABEL
5669 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5670 && LABEL_NUSES (start_insn) == 1)
5682 if (arm_ccfsm_state != 0 && !reverse)
5684 if (GET_CODE (insn) != JUMP_INSN)
5687 /* This jump might be paralleled with a clobber of the condition codes
5688 the jump should always come first */
5689 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5690 body = XVECEXP (body, 0, 0);
5693 /* If this is a conditional return then we don't want to know */
5694 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5695 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
5696 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
5697 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
5702 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5703 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
5706 int fail = FALSE, succeed = FALSE;
5707 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5708 int then_not_else = TRUE;
5709 rtx this_insn = start_insn, label = 0;
5711 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5713 /* The code below is wrong for these, and I haven't time to
5714 fix it now. So we just do the safe thing and return. This
5715 whole function needs re-writing anyway. */
5720 /* Register the insn jumped to. */
5723 if (!seeking_return)
5724 label = XEXP (SET_SRC (body), 0);
5726 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
5727 label = XEXP (XEXP (SET_SRC (body), 1), 0);
5728 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
5730 label = XEXP (XEXP (SET_SRC (body), 2), 0);
5731 then_not_else = FALSE;
5733 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
5735 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
5738 then_not_else = FALSE;
5743 /* See how many insns this branch skips, and what kind of insns. If all
5744 insns are okay, and the label or unconditional branch to the same
5745 label is not too far away, succeed. */
5746 for (insns_skipped = 0;
5747 !fail && !succeed && insns_skipped++ < MAX_INSNS_SKIPPED;)
5751 this_insn = next_nonnote_insn (this_insn);
5755 switch (GET_CODE (this_insn))
5758 /* Succeed if it is the target label, otherwise fail since
5759 control falls in from somewhere else. */
5760 if (this_insn == label)
5764 arm_ccfsm_state = 2;
5765 this_insn = next_nonnote_insn (this_insn);
5768 arm_ccfsm_state = 1;
5776 /* Succeed if the following insn is the target label.
5778 If return insns are used then the last insn in a function
5779 will be a barrier. */
5780 this_insn = next_nonnote_insn (this_insn);
5781 if (this_insn && this_insn == label)
5785 arm_ccfsm_state = 2;
5786 this_insn = next_nonnote_insn (this_insn);
5789 arm_ccfsm_state = 1;
5797 /* If using 32-bit addresses the cc is not preserved over
5801 /* Succeed if the following insn is the target label,
5802 or if the following two insns are a barrier and
5803 the target label. */
5804 this_insn = next_nonnote_insn (this_insn);
5805 if (this_insn && GET_CODE (this_insn) == BARRIER)
5806 this_insn = next_nonnote_insn (this_insn);
5808 if (this_insn && this_insn == label
5809 && insns_skipped < MAX_INSNS_SKIPPED)
5813 arm_ccfsm_state = 2;
5814 this_insn = next_nonnote_insn (this_insn);
5817 arm_ccfsm_state = 1;
5826 /* If this is an unconditional branch to the same label, succeed.
5827 If it is to another label, do nothing. If it is conditional,
5829 /* XXX Probably, the tests for SET and the PC are unnecessary. */
5831 scanbody = PATTERN (this_insn);
5832 if (GET_CODE (scanbody) == SET
5833 && GET_CODE (SET_DEST (scanbody)) == PC)
5835 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
5836 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
5838 arm_ccfsm_state = 2;
5841 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
5844 else if (GET_CODE (scanbody) == RETURN
5847 arm_ccfsm_state = 2;
5850 else if (GET_CODE (scanbody) == PARALLEL)
5852 switch (get_attr_conds (this_insn))
5864 /* Instructions using or affecting the condition codes make it
5866 scanbody = PATTERN (this_insn);
5867 if ((GET_CODE (scanbody) == SET
5868 || GET_CODE (scanbody) == PARALLEL)
5869 && get_attr_conds (this_insn) != CONDS_NOCOND)
5879 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
5880 arm_target_label = CODE_LABEL_NUMBER (label);
5881 else if (seeking_return || arm_ccfsm_state == 2)
5883 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
5885 this_insn = next_nonnote_insn (this_insn);
5886 if (this_insn && (GET_CODE (this_insn) == BARRIER
5887 || GET_CODE (this_insn) == CODE_LABEL))
5892 /* Oh, dear! we ran off the end.. give up */
5893 recog (PATTERN (insn), insn, NULL_PTR);
5894 arm_ccfsm_state = 0;
5895 arm_target_insn = NULL;
5898 arm_target_insn = this_insn;
5907 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
5909 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
5910 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5911 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
5912 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5916 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
5919 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
5923 if (reverse || then_not_else)
5924 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
5926 /* restore recog_operand (getting the attributes of other insns can
5927 destroy this array, but final.c assumes that it remains intact
5928 across this call; since the insn has been recognized already we
5929 call recog direct). */
5930 recog (PATTERN (insn), insn, NULL_PTR);
5934 #ifdef AOF_ASSEMBLER
5935 /* Special functions only needed when producing AOF syntax assembler. */
5937 rtx aof_pic_label = NULL_RTX;
5940 struct pic_chain *next;
5944 static struct pic_chain *aof_pic_chain = NULL;
5950 struct pic_chain **chainp;
5953 if (aof_pic_label == NULL_RTX)
5955 /* This needs to persist throughout the compilation. */
5956 end_temporary_allocation ();
5957 aof_pic_label = gen_rtx (SYMBOL_REF, Pmode, "x$adcons");
5958 resume_temporary_allocation ();
5961 for (offset = 0, chainp = &aof_pic_chain; *chainp;
5962 offset += 4, chainp = &(*chainp)->next)
5963 if ((*chainp)->symname == XSTR (x, 0))
5964 return plus_constant (aof_pic_label, offset);
5966 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
5967 (*chainp)->next = NULL;
5968 (*chainp)->symname = XSTR (x, 0);
5969 return plus_constant (aof_pic_label, offset);
5973 aof_dump_pic_table (f)
5976 struct pic_chain *chain;
5978 if (aof_pic_chain == NULL)
5981 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
5982 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
5983 reg_names[PIC_OFFSET_TABLE_REGNUM]);
5984 fputs ("|x$adcons|\n", f);
5986 for (chain = aof_pic_chain; chain; chain = chain->next)
5988 fputs ("\tDCD\t", f);
5989 assemble_name (f, chain->symname);
5994 int arm_text_section_count = 1;
5999 static char buf[100];
6000 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6001 arm_text_section_count++);
6003 strcat (buf, ", PIC, REENTRANT");
6007 static int arm_data_section_count = 1;
6012 static char buf[100];
6013 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6017 /* The AOF assembler is religiously strict about declarations of
6018 imported and exported symbols, so that it is impossible to declare
6019 a function as imported near the beginning of the file, and then to
6020 export it later on. It is, however, possible to delay the decision
6021 until all the functions in the file have been compiled. To get
6022 around this, we maintain a list of the imports and exports, and
6023 delete from it any that are subsequently defined. At the end of
6024 compilation we spit the remainder of the list out before the END
6029 struct import *next;
6033 static struct import *imports_list = NULL;
6036 aof_add_import (name)
6041 for (new = imports_list; new; new = new->next)
6042 if (new->name == name)
6045 new = (struct import *) xmalloc (sizeof (struct import));
6046 new->next = imports_list;
6052 aof_delete_import (name)
6055 struct import **old;
6057 for (old = &imports_list; *old; old = & (*old)->next)
6059 if ((*old)->name == name)
6061 *old = (*old)->next;
6067 int arm_main_function = 0;
6070 aof_dump_imports (f)
6073 /* The AOF assembler needs this to cause the startup code to be extracted
6074 from the library. Brining in __main causes the whole thing to work
6076 if (arm_main_function)
6079 fputs ("\tIMPORT __main\n", f);
6080 fputs ("\tDCD __main\n", f);
6083 /* Now dump the remaining imports. */
6084 while (imports_list)
6086 fprintf (f, "\tIMPORT\t");
6087 assemble_name (f, imports_list->name);
6089 imports_list = imports_list->next;
6092 #endif /* AOF_ASSEMBLER */