1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
75 static rtx emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
81 static arm_cc get_arm_condition_code (rtx);
82 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
83 static rtx is_jump_table (rtx);
84 static const char *output_multi_immediate (rtx *, const char *, const char *,
86 static const char *shift_op (rtx, HOST_WIDE_INT *);
87 static struct machine_function *arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static int arm_comp_type_attributes (tree, tree);
119 static void arm_set_default_type_attributes (tree);
120 static int arm_adjust_cost (rtx, rtx, rtx, int);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_size_rtx_costs (rtx, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx, int, int, int *);
133 static int arm_address_cost (rtx);
134 static bool arm_memory_load_p (rtx);
135 static bool arm_cirrus_insn_p (rtx);
136 static void cirrus_reorg (rtx);
137 static void arm_init_builtins (void);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx safe_vector_operand (rtx, enum machine_mode);
141 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
142 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void emit_constant_insn (rtx cond, rtx pattern);
145 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_constructor (rtx, int);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void arm_file_end (void);
158 static void aof_globalize_label (FILE *, const char *);
159 static void aof_dump_imports (FILE *);
160 static void aof_dump_pic_table (FILE *);
161 static void aof_file_start (void);
162 static void aof_file_end (void);
164 static rtx arm_struct_value_rtx (tree, int);
165 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
167 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
168 enum machine_mode, tree, bool);
169 static bool arm_promote_prototypes (tree);
170 static bool arm_default_short_enums (void);
171 static bool arm_align_anon_bitfield (void);
172 static bool arm_return_in_msb (tree);
173 static bool arm_must_pass_in_stack (enum machine_mode, tree);
174 #ifdef TARGET_UNWIND_INFO
175 static void arm_unwind_emit (FILE *, rtx);
176 static bool arm_output_ttype (rtx);
179 static tree arm_cxx_guard_type (void);
180 static bool arm_cxx_guard_mask_bit (void);
181 static tree arm_get_cookie_size (tree);
182 static bool arm_cookie_has_size (void);
183 static bool arm_cxx_cdtor_returns_this (void);
184 static bool arm_cxx_key_method_may_be_inline (void);
185 static void arm_cxx_determine_class_data_visibility (tree);
186 static bool arm_cxx_class_data_always_comdat (void);
187 static bool arm_cxx_use_aeabi_atexit (void);
188 static void arm_init_libfuncs (void);
189 static bool arm_handle_option (size_t, const char *, int);
190 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
192 /* Initialize the GCC target structure. */
193 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
194 #undef TARGET_MERGE_DECL_ATTRIBUTES
195 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
198 #undef TARGET_ATTRIBUTE_TABLE
199 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
201 #undef TARGET_ASM_FILE_END
202 #define TARGET_ASM_FILE_END arm_file_end
205 #undef TARGET_ASM_BYTE_OP
206 #define TARGET_ASM_BYTE_OP "\tDCB\t"
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
211 #undef TARGET_ASM_GLOBALIZE_LABEL
212 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
213 #undef TARGET_ASM_FILE_START
214 #define TARGET_ASM_FILE_START aof_file_start
215 #undef TARGET_ASM_FILE_END
216 #define TARGET_ASM_FILE_END aof_file_end
218 #undef TARGET_ASM_ALIGNED_SI_OP
219 #define TARGET_ASM_ALIGNED_SI_OP NULL
220 #undef TARGET_ASM_INTEGER
221 #define TARGET_ASM_INTEGER arm_assemble_integer
224 #undef TARGET_ASM_FUNCTION_PROLOGUE
225 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
230 #undef TARGET_DEFAULT_TARGET_FLAGS
231 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
232 #undef TARGET_HANDLE_OPTION
233 #define TARGET_HANDLE_OPTION arm_handle_option
235 #undef TARGET_COMP_TYPE_ATTRIBUTES
236 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
238 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
239 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
241 #undef TARGET_SCHED_ADJUST_COST
242 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
244 #undef TARGET_ENCODE_SECTION_INFO
246 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
248 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
251 #undef TARGET_STRIP_NAME_ENCODING
252 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
254 #undef TARGET_ASM_INTERNAL_LABEL
255 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
260 #undef TARGET_ASM_OUTPUT_MI_THUNK
261 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
262 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
263 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
265 /* This will be overridden in arm_override_options. */
266 #undef TARGET_RTX_COSTS
267 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
268 #undef TARGET_ADDRESS_COST
269 #define TARGET_ADDRESS_COST arm_address_cost
271 #undef TARGET_SHIFT_TRUNCATION_MASK
272 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
273 #undef TARGET_VECTOR_MODE_SUPPORTED_P
274 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
276 #undef TARGET_MACHINE_DEPENDENT_REORG
277 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
279 #undef TARGET_INIT_BUILTINS
280 #define TARGET_INIT_BUILTINS arm_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
287 #undef TARGET_PROMOTE_FUNCTION_ARGS
288 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
289 #undef TARGET_PROMOTE_FUNCTION_RETURN
290 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
291 #undef TARGET_PROMOTE_PROTOTYPES
292 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
293 #undef TARGET_PASS_BY_REFERENCE
294 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
295 #undef TARGET_ARG_PARTIAL_BYTES
296 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
298 #undef TARGET_STRUCT_VALUE_RTX
299 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
301 #undef TARGET_SETUP_INCOMING_VARARGS
302 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
304 #undef TARGET_DEFAULT_SHORT_ENUMS
305 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
307 #undef TARGET_ALIGN_ANON_BITFIELD
308 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
310 #undef TARGET_CXX_GUARD_TYPE
311 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
313 #undef TARGET_CXX_GUARD_MASK_BIT
314 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
316 #undef TARGET_CXX_GET_COOKIE_SIZE
317 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
319 #undef TARGET_CXX_COOKIE_HAS_SIZE
320 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
322 #undef TARGET_CXX_CDTOR_RETURNS_THIS
323 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
325 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
326 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
328 #undef TARGET_CXX_USE_AEABI_ATEXIT
329 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
331 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
332 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
333 arm_cxx_determine_class_data_visibility
335 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
336 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
338 #undef TARGET_RETURN_IN_MSB
339 #define TARGET_RETURN_IN_MSB arm_return_in_msb
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
344 #ifdef TARGET_UNWIND_INFO
345 #undef TARGET_UNWIND_EMIT
346 #define TARGET_UNWIND_EMIT arm_unwind_emit
348 /* EABI unwinding tables use a different format for the typeinfo tables. */
349 #undef TARGET_ASM_TTYPE
350 #define TARGET_ASM_TTYPE arm_output_ttype
352 #undef TARGET_ARM_EABI_UNWINDER
353 #define TARGET_ARM_EABI_UNWINDER true
354 #endif /* TARGET_UNWIND_INFO */
356 struct gcc_target targetm = TARGET_INITIALIZER;
358 /* Obstack for minipool constant handling. */
359 static struct obstack minipool_obstack;
360 static char * minipool_startobj;
362 /* The maximum number of insns skipped which
363 will be conditionalised if possible. */
364 static int max_insns_skipped = 5;
366 extern FILE * asm_out_file;
368 /* True if we are currently building a constant table. */
369 int making_const_table;
371 /* Define the information needed to generate branch insns. This is
372 stored from the compare operation. */
373 rtx arm_compare_op0, arm_compare_op1;
375 /* The processor for which instructions should be scheduled. */
376 enum processor_type arm_tune = arm_none;
378 /* Which floating point model to use. */
379 enum arm_fp_model arm_fp_model;
381 /* Which floating point hardware is available. */
382 enum fputype arm_fpu_arch;
384 /* Which floating point hardware to schedule for. */
385 enum fputype arm_fpu_tune;
387 /* Whether to use floating point hardware. */
388 enum float_abi_type arm_float_abi;
390 /* Which ABI to use. */
391 enum arm_abi_type arm_abi;
393 /* Used to parse -mstructure_size_boundary command line option. */
394 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
396 /* Used for Thumb call_via trampolines. */
397 rtx thumb_call_via_label[14];
398 static int thumb_call_reg_needed;
400 /* Bit values used to identify processor capabilities. */
401 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
402 #define FL_ARCH3M (1 << 1) /* Extended multiply */
403 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
404 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
405 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
406 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
407 #define FL_THUMB (1 << 6) /* Thumb aware */
408 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
409 #define FL_STRONG (1 << 8) /* StrongARM */
410 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
411 #define FL_XSCALE (1 << 10) /* XScale */
412 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
413 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
414 media instructions. */
415 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
416 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
417 Note: ARM6 & 7 derivatives only. */
419 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
421 #define FL_FOR_ARCH2 0
422 #define FL_FOR_ARCH3 FL_MODE32
423 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
424 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
425 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
426 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
427 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
428 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
429 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
430 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
431 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
432 #define FL_FOR_ARCH6J FL_FOR_ARCH6
433 #define FL_FOR_ARCH6K FL_FOR_ARCH6
434 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
435 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
437 /* The bits in this mask specify which
438 instructions we are allowed to generate. */
439 static unsigned long insn_flags = 0;
441 /* The bits in this mask specify which instruction scheduling options should
443 static unsigned long tune_flags = 0;
445 /* The following are used in the arm.md file as equivalents to bits
446 in the above two flag variables. */
448 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
451 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
454 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
457 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
460 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
463 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
466 /* Nonzero if this chip can benefit from load scheduling. */
467 int arm_ld_sched = 0;
469 /* Nonzero if this chip is a StrongARM. */
470 int arm_tune_strongarm = 0;
472 /* Nonzero if this chip is a Cirrus variant. */
473 int arm_arch_cirrus = 0;
475 /* Nonzero if this chip supports Intel Wireless MMX technology. */
476 int arm_arch_iwmmxt = 0;
478 /* Nonzero if this chip is an XScale. */
479 int arm_arch_xscale = 0;
481 /* Nonzero if tuning for XScale */
482 int arm_tune_xscale = 0;
484 /* Nonzero if we want to tune for stores that access the write-buffer.
485 This typically means an ARM6 or ARM7 with MMU or MPU. */
486 int arm_tune_wbuf = 0;
488 /* Nonzero if generating Thumb instructions. */
491 /* Nonzero if we should define __THUMB_INTERWORK__ in the
493 XXX This is a bit of a hack, it's intended to help work around
494 problems in GLD which doesn't understand that armv5t code is
495 interworking clean. */
496 int arm_cpp_interwork = 0;
498 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
499 must report the mode of the memory reference from PRINT_OPERAND to
500 PRINT_OPERAND_ADDRESS. */
501 enum machine_mode output_memory_reference_mode;
503 /* The register number to be used for the PIC offset register. */
504 int arm_pic_register = INVALID_REGNUM;
506 /* Set to 1 when a return insn is output, this means that the epilogue
508 int return_used_this_function;
510 /* Set to 1 after arm_reorg has started. Reset to start at the start of
511 the next function. */
512 static int after_arm_reorg = 0;
514 /* The maximum number of insns to be used when loading a constant. */
515 static int arm_constant_limit = 3;
517 /* For an explanation of these variables, see final_prescan_insn below. */
519 enum arm_cond_code arm_current_cc;
521 int arm_target_label;
523 /* The condition codes of the ARM, and the inverse function. */
524 static const char * const arm_condition_codes[] =
526 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
527 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
530 #define streq(string1, string2) (strcmp (string1, string2) == 0)
532 /* Initialization code. */
536 const char *const name;
537 enum processor_type core;
539 const unsigned long flags;
540 bool (* rtx_costs) (rtx, int, int, int *);
543 /* Not all of these give usefully different compilation alternatives,
544 but there is no simple way of generalizing them. */
545 static const struct processors all_cores[] =
548 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
549 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
550 #include "arm-cores.def"
552 {NULL, arm_none, NULL, 0, NULL}
555 static const struct processors all_architectures[] =
557 /* ARM Architectures */
558 /* We don't specify rtx_costs here as it will be figured out
561 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
562 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
563 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
564 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
565 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
566 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
567 implementations that support it, so we will leave it out for now. */
568 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
569 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
570 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
571 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
572 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
573 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
574 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
575 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
576 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
577 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
578 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
579 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
580 {NULL, arm_none, NULL, 0 , NULL}
583 struct arm_cpu_select
587 const struct processors * processors;
590 /* This is a magic structure. The 'string' field is magically filled in
591 with a pointer to the value specified by the user on the command line
592 assuming that the user has specified such a value. */
594 static struct arm_cpu_select arm_select[] =
596 /* string name processors */
597 { NULL, "-mcpu=", all_cores },
598 { NULL, "-march=", all_architectures },
599 { NULL, "-mtune=", all_cores }
602 /* Defines representing the indexes into the above table. */
603 #define ARM_OPT_SET_CPU 0
604 #define ARM_OPT_SET_ARCH 1
605 #define ARM_OPT_SET_TUNE 2
607 /* The name of the proprocessor macro to define for this architecture. */
609 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
618 /* Available values for for -mfpu=. */
620 static const struct fpu_desc all_fpus[] =
622 {"fpa", FPUTYPE_FPA},
623 {"fpe2", FPUTYPE_FPA_EMU2},
624 {"fpe3", FPUTYPE_FPA_EMU2},
625 {"maverick", FPUTYPE_MAVERICK},
630 /* Floating point models used by the different hardware.
631 See fputype in arm.h. */
633 static const enum fputype fp_model_for_fpu[] =
635 /* No FP hardware. */
636 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
637 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
638 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
639 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
640 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
641 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
648 enum float_abi_type abi_type;
652 /* Available values for -mfloat-abi=. */
654 static const struct float_abi all_float_abis[] =
656 {"soft", ARM_FLOAT_ABI_SOFT},
657 {"softfp", ARM_FLOAT_ABI_SOFTFP},
658 {"hard", ARM_FLOAT_ABI_HARD}
665 enum arm_abi_type abi_type;
669 /* Available values for -mabi=. */
671 static const struct abi_name arm_all_abis[] =
673 {"apcs-gnu", ARM_ABI_APCS},
674 {"atpcs", ARM_ABI_ATPCS},
675 {"aapcs", ARM_ABI_AAPCS},
676 {"iwmmxt", ARM_ABI_IWMMXT}
679 /* Return the number of bits set in VALUE. */
681 bit_count (unsigned long value)
683 unsigned long count = 0;
688 value &= value - 1; /* Clear the least-significant set bit. */
694 /* Set up library functions unique to ARM. */
697 arm_init_libfuncs (void)
699 /* There are no special library functions unless we are using the
704 /* The functions below are described in Section 4 of the "Run-Time
705 ABI for the ARM architecture", Version 1.0. */
707 /* Double-precision floating-point arithmetic. Table 2. */
708 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
709 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
710 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
711 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
712 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
714 /* Double-precision comparisons. Table 3. */
715 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
716 set_optab_libfunc (ne_optab, DFmode, NULL);
717 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
718 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
719 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
720 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
721 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
723 /* Single-precision floating-point arithmetic. Table 4. */
724 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
725 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
726 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
727 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
728 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
730 /* Single-precision comparisons. Table 5. */
731 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
732 set_optab_libfunc (ne_optab, SFmode, NULL);
733 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
734 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
735 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
736 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
737 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
739 /* Floating-point to integer conversions. Table 6. */
740 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
741 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
742 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
743 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
744 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
745 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
746 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
747 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
749 /* Conversions between floating types. Table 7. */
750 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
751 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
753 /* Integer to floating-point conversions. Table 8. */
754 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
755 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
756 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
757 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
758 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
759 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
760 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
761 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
763 /* Long long. Table 9. */
764 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
765 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
766 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
767 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
768 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
769 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
770 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
771 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
773 /* Integer (32/32->32) division. \S 4.3.1. */
774 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
775 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
777 /* The divmod functions are designed so that they can be used for
778 plain division, even though they return both the quotient and the
779 remainder. The quotient is returned in the usual location (i.e.,
780 r0 for SImode, {r0, r1} for DImode), just as would be expected
781 for an ordinary division routine. Because the AAPCS calling
782 conventions specify that all of { r0, r1, r2, r3 } are
783 callee-saved registers, there is no need to tell the compiler
784 explicitly that those registers are clobbered by these
786 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
787 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
788 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
789 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
791 /* We don't have mod libcalls. Fortunately gcc knows how to use the
792 divmod libcalls instead. */
793 set_optab_libfunc (smod_optab, DImode, NULL);
794 set_optab_libfunc (umod_optab, DImode, NULL);
795 set_optab_libfunc (smod_optab, SImode, NULL);
796 set_optab_libfunc (umod_optab, SImode, NULL);
799 /* Implement TARGET_HANDLE_OPTION. */
802 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
807 arm_select[1].string = arg;
811 arm_select[0].string = arg;
814 case OPT_mhard_float:
815 target_float_abi_name = "hard";
818 case OPT_msoft_float:
819 target_float_abi_name = "soft";
823 arm_select[2].string = arg;
831 /* Fix up any incompatible options that the user has specified.
832 This has now turned into a maze. */
834 arm_override_options (void)
837 enum processor_type target_arch_cpu = arm_none;
839 /* Set up the flags based on the cpu/architecture selected by the user. */
840 for (i = ARRAY_SIZE (arm_select); i--;)
842 struct arm_cpu_select * ptr = arm_select + i;
844 if (ptr->string != NULL && ptr->string[0] != '\0')
846 const struct processors * sel;
848 for (sel = ptr->processors; sel->name != NULL; sel++)
849 if (streq (ptr->string, sel->name))
851 /* Set the architecture define. */
852 if (i != ARM_OPT_SET_TUNE)
853 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
855 /* Determine the processor core for which we should
856 tune code-generation. */
857 if (/* -mcpu= is a sensible default. */
859 /* -mtune= overrides -mcpu= and -march=. */
860 || i == ARM_OPT_SET_TUNE)
861 arm_tune = (enum processor_type) (sel - ptr->processors);
863 /* Remember the CPU associated with this architecture.
864 If no other option is used to set the CPU type,
865 we'll use this to guess the most suitable tuning
867 if (i == ARM_OPT_SET_ARCH)
868 target_arch_cpu = sel->core;
870 if (i != ARM_OPT_SET_TUNE)
872 /* If we have been given an architecture and a processor
873 make sure that they are compatible. We only generate
874 a warning though, and we prefer the CPU over the
876 if (insn_flags != 0 && (insn_flags ^ sel->flags))
877 warning (0, "switch -mcpu=%s conflicts with -march= switch",
880 insn_flags = sel->flags;
886 if (sel->name == NULL)
887 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
891 /* Guess the tuning options from the architecture if necessary. */
892 if (arm_tune == arm_none)
893 arm_tune = target_arch_cpu;
895 /* If the user did not specify a processor, choose one for them. */
898 const struct processors * sel;
900 enum processor_type cpu;
902 cpu = TARGET_CPU_DEFAULT;
905 #ifdef SUBTARGET_CPU_DEFAULT
906 /* Use the subtarget default CPU if none was specified by
908 cpu = SUBTARGET_CPU_DEFAULT;
910 /* Default to ARM6. */
914 sel = &all_cores[cpu];
916 insn_flags = sel->flags;
918 /* Now check to see if the user has specified some command line
919 switch that require certain abilities from the cpu. */
922 if (TARGET_INTERWORK || TARGET_THUMB)
924 sought |= (FL_THUMB | FL_MODE32);
926 /* There are no ARM processors that support both APCS-26 and
927 interworking. Therefore we force FL_MODE26 to be removed
928 from insn_flags here (if it was set), so that the search
929 below will always be able to find a compatible processor. */
930 insn_flags &= ~FL_MODE26;
933 if (sought != 0 && ((sought & insn_flags) != sought))
935 /* Try to locate a CPU type that supports all of the abilities
936 of the default CPU, plus the extra abilities requested by
938 for (sel = all_cores; sel->name != NULL; sel++)
939 if ((sel->flags & sought) == (sought | insn_flags))
942 if (sel->name == NULL)
944 unsigned current_bit_count = 0;
945 const struct processors * best_fit = NULL;
947 /* Ideally we would like to issue an error message here
948 saying that it was not possible to find a CPU compatible
949 with the default CPU, but which also supports the command
950 line options specified by the programmer, and so they
951 ought to use the -mcpu=<name> command line option to
952 override the default CPU type.
954 If we cannot find a cpu that has both the
955 characteristics of the default cpu and the given
956 command line options we scan the array again looking
958 for (sel = all_cores; sel->name != NULL; sel++)
959 if ((sel->flags & sought) == sought)
963 count = bit_count (sel->flags & insn_flags);
965 if (count >= current_bit_count)
968 current_bit_count = count;
972 gcc_assert (best_fit);
976 insn_flags = sel->flags;
978 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
979 if (arm_tune == arm_none)
980 arm_tune = (enum processor_type) (sel - all_cores);
983 /* The processor for which we should tune should now have been
985 gcc_assert (arm_tune != arm_none);
987 tune_flags = all_cores[(int)arm_tune].flags;
989 targetm.rtx_costs = arm_size_rtx_costs;
991 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
993 /* Make sure that the processor choice does not conflict with any of the
994 other command line choices. */
995 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
997 warning (0, "target CPU does not support interworking" );
998 target_flags &= ~MASK_INTERWORK;
1001 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1003 warning (0, "target CPU does not support THUMB instructions");
1004 target_flags &= ~MASK_THUMB;
1007 if (TARGET_APCS_FRAME && TARGET_THUMB)
1009 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1010 target_flags &= ~MASK_APCS_FRAME;
1013 /* Callee super interworking implies thumb interworking. Adding
1014 this to the flags here simplifies the logic elsewhere. */
1015 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1016 target_flags |= MASK_INTERWORK;
1018 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1019 from here where no function is being compiled currently. */
1020 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1021 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1023 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1024 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1026 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1027 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1029 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1031 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1032 target_flags |= MASK_APCS_FRAME;
1035 if (TARGET_POKE_FUNCTION_NAME)
1036 target_flags |= MASK_APCS_FRAME;
1038 if (TARGET_APCS_REENT && flag_pic)
1039 error ("-fpic and -mapcs-reent are incompatible");
1041 if (TARGET_APCS_REENT)
1042 warning (0, "APCS reentrant code not supported. Ignored");
1044 /* If this target is normally configured to use APCS frames, warn if they
1045 are turned off and debugging is turned on. */
1047 && write_symbols != NO_DEBUG
1048 && !TARGET_APCS_FRAME
1049 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1050 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1052 /* If stack checking is disabled, we can use r10 as the PIC register,
1053 which keeps r9 available. */
1055 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1057 if (TARGET_APCS_FLOAT)
1058 warning (0, "passing floating point arguments in fp regs not yet supported");
1060 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1061 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1062 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1063 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1064 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1065 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1066 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1067 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1068 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1070 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1071 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1072 thumb_code = (TARGET_ARM == 0);
1073 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1074 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1075 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1077 /* V5 code we generate is completely interworking capable, so we turn off
1078 TARGET_INTERWORK here to avoid many tests later on. */
1080 /* XXX However, we must pass the right pre-processor defines to CPP
1081 or GLD can get confused. This is a hack. */
1082 if (TARGET_INTERWORK)
1083 arm_cpp_interwork = 1;
1086 target_flags &= ~MASK_INTERWORK;
1088 if (target_abi_name)
1090 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1092 if (streq (arm_all_abis[i].name, target_abi_name))
1094 arm_abi = arm_all_abis[i].abi_type;
1098 if (i == ARRAY_SIZE (arm_all_abis))
1099 error ("invalid ABI option: -mabi=%s", target_abi_name);
1102 arm_abi = ARM_DEFAULT_ABI;
1104 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1105 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1107 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1108 error ("iwmmxt abi requires an iwmmxt capable cpu");
1110 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1111 if (target_fpu_name == NULL && target_fpe_name != NULL)
1113 if (streq (target_fpe_name, "2"))
1114 target_fpu_name = "fpe2";
1115 else if (streq (target_fpe_name, "3"))
1116 target_fpu_name = "fpe3";
1118 error ("invalid floating point emulation option: -mfpe=%s",
1121 if (target_fpu_name != NULL)
1123 /* The user specified a FPU. */
1124 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1126 if (streq (all_fpus[i].name, target_fpu_name))
1128 arm_fpu_arch = all_fpus[i].fpu;
1129 arm_fpu_tune = arm_fpu_arch;
1130 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1134 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1135 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1139 #ifdef FPUTYPE_DEFAULT
1140 /* Use the default if it is specified for this platform. */
1141 arm_fpu_arch = FPUTYPE_DEFAULT;
1142 arm_fpu_tune = FPUTYPE_DEFAULT;
1144 /* Pick one based on CPU type. */
1145 /* ??? Some targets assume FPA is the default.
1146 if ((insn_flags & FL_VFP) != 0)
1147 arm_fpu_arch = FPUTYPE_VFP;
1150 if (arm_arch_cirrus)
1151 arm_fpu_arch = FPUTYPE_MAVERICK;
1153 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1155 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1156 arm_fpu_tune = FPUTYPE_FPA;
1158 arm_fpu_tune = arm_fpu_arch;
1159 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1160 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1163 if (target_float_abi_name != NULL)
1165 /* The user specified a FP ABI. */
1166 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1168 if (streq (all_float_abis[i].name, target_float_abi_name))
1170 arm_float_abi = all_float_abis[i].abi_type;
1174 if (i == ARRAY_SIZE (all_float_abis))
1175 error ("invalid floating point abi: -mfloat-abi=%s",
1176 target_float_abi_name);
1179 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1181 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1182 sorry ("-mfloat-abi=hard and VFP");
1184 /* If soft-float is specified then don't use FPU. */
1185 if (TARGET_SOFT_FLOAT)
1186 arm_fpu_arch = FPUTYPE_NONE;
1188 /* For arm2/3 there is no need to do any scheduling if there is only
1189 a floating point emulator, or we are doing software floating-point. */
1190 if ((TARGET_SOFT_FLOAT
1191 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1192 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1193 && (tune_flags & FL_MODE32) == 0)
1194 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1196 /* Override the default structure alignment for AAPCS ABI. */
1197 if (arm_abi == ARM_ABI_AAPCS)
1198 arm_structure_size_boundary = 8;
1200 if (structure_size_string != NULL)
1202 int size = strtol (structure_size_string, NULL, 0);
1204 if (size == 8 || size == 32
1205 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1206 arm_structure_size_boundary = size;
1208 warning (0, "structure size boundary can only be set to %s",
1209 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1212 if (arm_pic_register_string != NULL)
1214 int pic_register = decode_reg_name (arm_pic_register_string);
1217 warning (0, "-mpic-register= is useless without -fpic");
1219 /* Prevent the user from choosing an obviously stupid PIC register. */
1220 else if (pic_register < 0 || call_used_regs[pic_register]
1221 || pic_register == HARD_FRAME_POINTER_REGNUM
1222 || pic_register == STACK_POINTER_REGNUM
1223 || pic_register >= PC_REGNUM)
1224 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1226 arm_pic_register = pic_register;
1229 if (TARGET_THUMB && flag_schedule_insns)
1231 /* Don't warn since it's on by default in -O2. */
1232 flag_schedule_insns = 0;
1237 /* There's some dispute as to whether this should be 1 or 2. However,
1238 experiments seem to show that in pathological cases a setting of
1239 1 degrades less severely than a setting of 2. This could change if
1240 other parts of the compiler change their behavior. */
1241 arm_constant_limit = 1;
1243 /* If optimizing for size, bump the number of instructions that we
1244 are prepared to conditionally execute (even on a StrongARM). */
1245 max_insns_skipped = 6;
1249 /* For processors with load scheduling, it never costs more than
1250 2 cycles to load a constant, and the load scheduler may well
1251 reduce that to 1. */
1253 arm_constant_limit = 1;
1255 /* On XScale the longer latency of a load makes it more difficult
1256 to achieve a good schedule, so it's faster to synthesize
1257 constants that can be done in two insns. */
1258 if (arm_tune_xscale)
1259 arm_constant_limit = 2;
1261 /* StrongARM has early execution of branches, so a sequence
1262 that is worth skipping is shorter. */
1263 if (arm_tune_strongarm)
1264 max_insns_skipped = 3;
1267 /* Register global variables with the garbage collector. */
1268 arm_add_gc_roots ();
1272 arm_add_gc_roots (void)
1274 gcc_obstack_init(&minipool_obstack);
1275 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1278 /* A table of known ARM exception types.
1279 For use with the interrupt function attribute. */
1283 const char *const arg;
1284 const unsigned long return_value;
1288 static const isr_attribute_arg isr_attribute_args [] =
1290 { "IRQ", ARM_FT_ISR },
1291 { "irq", ARM_FT_ISR },
1292 { "FIQ", ARM_FT_FIQ },
1293 { "fiq", ARM_FT_FIQ },
1294 { "ABORT", ARM_FT_ISR },
1295 { "abort", ARM_FT_ISR },
1296 { "ABORT", ARM_FT_ISR },
1297 { "abort", ARM_FT_ISR },
1298 { "UNDEF", ARM_FT_EXCEPTION },
1299 { "undef", ARM_FT_EXCEPTION },
1300 { "SWI", ARM_FT_EXCEPTION },
1301 { "swi", ARM_FT_EXCEPTION },
1302 { NULL, ARM_FT_NORMAL }
1305 /* Returns the (interrupt) function type of the current
1306 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1308 static unsigned long
1309 arm_isr_value (tree argument)
1311 const isr_attribute_arg * ptr;
1314 /* No argument - default to IRQ. */
1315 if (argument == NULL_TREE)
1318 /* Get the value of the argument. */
1319 if (TREE_VALUE (argument) == NULL_TREE
1320 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1321 return ARM_FT_UNKNOWN;
1323 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1325 /* Check it against the list of known arguments. */
1326 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1327 if (streq (arg, ptr->arg))
1328 return ptr->return_value;
1330 /* An unrecognized interrupt type. */
1331 return ARM_FT_UNKNOWN;
1334 /* Computes the type of the current function. */
1336 static unsigned long
1337 arm_compute_func_type (void)
1339 unsigned long type = ARM_FT_UNKNOWN;
1343 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1345 /* Decide if the current function is volatile. Such functions
1346 never return, and many memory cycles can be saved by not storing
1347 register values that will never be needed again. This optimization
1348 was added to speed up context switching in a kernel application. */
1350 && TREE_NOTHROW (current_function_decl)
1351 && TREE_THIS_VOLATILE (current_function_decl))
1352 type |= ARM_FT_VOLATILE;
1354 if (cfun->static_chain_decl != NULL)
1355 type |= ARM_FT_NESTED;
1357 attr = DECL_ATTRIBUTES (current_function_decl);
1359 a = lookup_attribute ("naked", attr);
1361 type |= ARM_FT_NAKED;
1363 a = lookup_attribute ("isr", attr);
1365 a = lookup_attribute ("interrupt", attr);
1368 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1370 type |= arm_isr_value (TREE_VALUE (a));
1375 /* Returns the type of the current function. */
1378 arm_current_func_type (void)
1380 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1381 cfun->machine->func_type = arm_compute_func_type ();
1383 return cfun->machine->func_type;
1386 /* Return 1 if it is possible to return using a single instruction.
1387 If SIBLING is non-null, this is a test for a return before a sibling
1388 call. SIBLING is the call insn, so we can examine its register usage. */
1391 use_return_insn (int iscond, rtx sibling)
1394 unsigned int func_type;
1395 unsigned long saved_int_regs;
1396 unsigned HOST_WIDE_INT stack_adjust;
1397 arm_stack_offsets *offsets;
1399 /* Never use a return instruction before reload has run. */
1400 if (!reload_completed)
1403 func_type = arm_current_func_type ();
1405 /* Naked functions and volatile functions need special
1407 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1410 /* So do interrupt functions that use the frame pointer. */
1411 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1414 offsets = arm_get_frame_offsets ();
1415 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1417 /* As do variadic functions. */
1418 if (current_function_pretend_args_size
1419 || cfun->machine->uses_anonymous_args
1420 /* Or if the function calls __builtin_eh_return () */
1421 || current_function_calls_eh_return
1422 /* Or if the function calls alloca */
1423 || current_function_calls_alloca
1424 /* Or if there is a stack adjustment. However, if the stack pointer
1425 is saved on the stack, we can use a pre-incrementing stack load. */
1426 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1429 saved_int_regs = arm_compute_save_reg_mask ();
1431 /* Unfortunately, the insn
1433 ldmib sp, {..., sp, ...}
1435 triggers a bug on most SA-110 based devices, such that the stack
1436 pointer won't be correctly restored if the instruction takes a
1437 page fault. We work around this problem by popping r3 along with
1438 the other registers, since that is never slower than executing
1439 another instruction.
1441 We test for !arm_arch5 here, because code for any architecture
1442 less than this could potentially be run on one of the buggy
1444 if (stack_adjust == 4 && !arm_arch5)
1446 /* Validate that r3 is a call-clobbered register (always true in
1447 the default abi) ... */
1448 if (!call_used_regs[3])
1451 /* ... that it isn't being used for a return value ... */
1452 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1455 /* ... or for a tail-call argument ... */
1458 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1460 if (find_regno_fusage (sibling, USE, 3))
1464 /* ... and that there are no call-saved registers in r0-r2
1465 (always true in the default ABI). */
1466 if (saved_int_regs & 0x7)
1470 /* Can't be done if interworking with Thumb, and any registers have been
1472 if (TARGET_INTERWORK && saved_int_regs != 0)
1475 /* On StrongARM, conditional returns are expensive if they aren't
1476 taken and multiple registers have been stacked. */
1477 if (iscond && arm_tune_strongarm)
1479 /* Conditional return when just the LR is stored is a simple
1480 conditional-load instruction, that's not expensive. */
1481 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1484 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1488 /* If there are saved registers but the LR isn't saved, then we need
1489 two instructions for the return. */
1490 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1493 /* Can't be done if any of the FPA regs are pushed,
1494 since this also requires an insn. */
1495 if (TARGET_HARD_FLOAT && TARGET_FPA)
1496 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1497 if (regs_ever_live[regno] && !call_used_regs[regno])
1500 /* Likewise VFP regs. */
1501 if (TARGET_HARD_FLOAT && TARGET_VFP)
1502 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1503 if (regs_ever_live[regno] && !call_used_regs[regno])
1506 if (TARGET_REALLY_IWMMXT)
1507 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1508 if (regs_ever_live[regno] && ! call_used_regs [regno])
1514 /* Return TRUE if int I is a valid immediate ARM constant. */
1517 const_ok_for_arm (HOST_WIDE_INT i)
1521 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1522 be all zero, or all one. */
1523 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1524 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1525 != ((~(unsigned HOST_WIDE_INT) 0)
1526 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1529 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1531 /* Fast return for 0 and small values. We must do this for zero, since
1532 the code below can't handle that one case. */
1533 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1536 /* Get the number of trailing zeros, rounded down to the nearest even
1538 lowbit = (ffs ((int) i) - 1) & ~1;
1540 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1542 else if (lowbit <= 4
1543 && ((i & ~0xc000003f) == 0
1544 || (i & ~0xf000000f) == 0
1545 || (i & ~0xfc000003) == 0))
1551 /* Return true if I is a valid constant for the operation CODE. */
1553 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1555 if (const_ok_for_arm (i))
1561 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1563 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1569 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1576 /* Emit a sequence of insns to handle a large constant.
1577 CODE is the code of the operation required, it can be any of SET, PLUS,
1578 IOR, AND, XOR, MINUS;
1579 MODE is the mode in which the operation is being performed;
1580 VAL is the integer to operate on;
1581 SOURCE is the other operand (a register, or a null-pointer for SET);
1582 SUBTARGETS means it is safe to create scratch registers if that will
1583 either produce a simpler sequence, or we will want to cse the values.
1584 Return value is the number of insns emitted. */
1587 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1588 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1592 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1593 cond = COND_EXEC_TEST (PATTERN (insn));
1597 if (subtargets || code == SET
1598 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1599 && REGNO (target) != REGNO (source)))
1601 /* After arm_reorg has been called, we can't fix up expensive
1602 constants by pushing them into memory so we must synthesize
1603 them in-line, regardless of the cost. This is only likely to
1604 be more costly on chips that have load delay slots and we are
1605 compiling without running the scheduler (so no splitting
1606 occurred before the final instruction emission).
1608 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1610 if (!after_arm_reorg
1612 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1614 > arm_constant_limit + (code != SET)))
1618 /* Currently SET is the only monadic value for CODE, all
1619 the rest are diadic. */
1620 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1625 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1627 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1628 /* For MINUS, the value is subtracted from, since we never
1629 have subtraction of a constant. */
1631 emit_insn (gen_rtx_SET (VOIDmode, target,
1632 gen_rtx_MINUS (mode, temp, source)));
1634 emit_insn (gen_rtx_SET (VOIDmode, target,
1635 gen_rtx_fmt_ee (code, mode, source, temp)));
1641 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1646 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1648 HOST_WIDE_INT temp1;
1656 if (remainder & (3 << (i - 2)))
1661 temp1 = remainder & ((0x0ff << end)
1662 | ((i < end) ? (0xff >> (32 - end)) : 0));
1663 remainder &= ~temp1;
1668 } while (remainder);
1672 /* Emit an instruction with the indicated PATTERN. If COND is
1673 non-NULL, conditionalize the execution of the instruction on COND
1677 emit_constant_insn (rtx cond, rtx pattern)
1680 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1681 emit_insn (pattern);
1684 /* As above, but extra parameter GENERATE which, if clear, suppresses
1688 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1689 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1694 int can_negate_initial = 0;
1697 int num_bits_set = 0;
1698 int set_sign_bit_copies = 0;
1699 int clear_sign_bit_copies = 0;
1700 int clear_zero_bit_copies = 0;
1701 int set_zero_bit_copies = 0;
1703 unsigned HOST_WIDE_INT temp1, temp2;
1704 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1706 /* Find out which operations are safe for a given CODE. Also do a quick
1707 check for degenerate cases; these can occur when DImode operations
1719 can_negate_initial = 1;
1723 if (remainder == 0xffffffff)
1726 emit_constant_insn (cond,
1727 gen_rtx_SET (VOIDmode, target,
1728 GEN_INT (ARM_SIGN_EXTEND (val))));
1733 if (reload_completed && rtx_equal_p (target, source))
1736 emit_constant_insn (cond,
1737 gen_rtx_SET (VOIDmode, target, source));
1746 emit_constant_insn (cond,
1747 gen_rtx_SET (VOIDmode, target, const0_rtx));
1750 if (remainder == 0xffffffff)
1752 if (reload_completed && rtx_equal_p (target, source))
1755 emit_constant_insn (cond,
1756 gen_rtx_SET (VOIDmode, target, source));
1765 if (reload_completed && rtx_equal_p (target, source))
1768 emit_constant_insn (cond,
1769 gen_rtx_SET (VOIDmode, target, source));
1773 /* We don't know how to handle other cases yet. */
1774 gcc_assert (remainder == 0xffffffff);
1777 emit_constant_insn (cond,
1778 gen_rtx_SET (VOIDmode, target,
1779 gen_rtx_NOT (mode, source)));
1783 /* We treat MINUS as (val - source), since (source - val) is always
1784 passed as (source + (-val)). */
1788 emit_constant_insn (cond,
1789 gen_rtx_SET (VOIDmode, target,
1790 gen_rtx_NEG (mode, source)));
1793 if (const_ok_for_arm (val))
1796 emit_constant_insn (cond,
1797 gen_rtx_SET (VOIDmode, target,
1798 gen_rtx_MINUS (mode, GEN_INT (val),
1810 /* If we can do it in one insn get out quickly. */
1811 if (const_ok_for_arm (val)
1812 || (can_negate_initial && const_ok_for_arm (-val))
1813 || (can_invert && const_ok_for_arm (~val)))
1816 emit_constant_insn (cond,
1817 gen_rtx_SET (VOIDmode, target,
1819 ? gen_rtx_fmt_ee (code, mode, source,
1825 /* Calculate a few attributes that may be useful for specific
1827 for (i = 31; i >= 0; i--)
1829 if ((remainder & (1 << i)) == 0)
1830 clear_sign_bit_copies++;
1835 for (i = 31; i >= 0; i--)
1837 if ((remainder & (1 << i)) != 0)
1838 set_sign_bit_copies++;
1843 for (i = 0; i <= 31; i++)
1845 if ((remainder & (1 << i)) == 0)
1846 clear_zero_bit_copies++;
1851 for (i = 0; i <= 31; i++)
1853 if ((remainder & (1 << i)) != 0)
1854 set_zero_bit_copies++;
1862 /* See if we can do this by sign_extending a constant that is known
1863 to be negative. This is a good, way of doing it, since the shift
1864 may well merge into a subsequent insn. */
1865 if (set_sign_bit_copies > 1)
1867 if (const_ok_for_arm
1868 (temp1 = ARM_SIGN_EXTEND (remainder
1869 << (set_sign_bit_copies - 1))))
1873 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1874 emit_constant_insn (cond,
1875 gen_rtx_SET (VOIDmode, new_src,
1877 emit_constant_insn (cond,
1878 gen_ashrsi3 (target, new_src,
1879 GEN_INT (set_sign_bit_copies - 1)));
1883 /* For an inverted constant, we will need to set the low bits,
1884 these will be shifted out of harm's way. */
1885 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1886 if (const_ok_for_arm (~temp1))
1890 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1891 emit_constant_insn (cond,
1892 gen_rtx_SET (VOIDmode, new_src,
1894 emit_constant_insn (cond,
1895 gen_ashrsi3 (target, new_src,
1896 GEN_INT (set_sign_bit_copies - 1)));
1902 /* See if we can calculate the value as the difference between two
1903 valid immediates. */
1904 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
1906 int topshift = clear_sign_bit_copies & ~1;
1908 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
1909 & (0xff000000 >> topshift));
1911 /* If temp1 is zero, then that means the 9 most significant
1912 bits of remainder were 1 and we've caused it to overflow.
1913 When topshift is 0 we don't need to do anything since we
1914 can borrow from 'bit 32'. */
1915 if (temp1 == 0 && topshift != 0)
1916 temp1 = 0x80000000 >> (topshift - 1);
1918 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
1920 if (const_ok_for_arm (temp2))
1924 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1925 emit_constant_insn (cond,
1926 gen_rtx_SET (VOIDmode, new_src,
1928 emit_constant_insn (cond,
1929 gen_addsi3 (target, new_src,
1937 /* See if we can generate this by setting the bottom (or the top)
1938 16 bits, and then shifting these into the other half of the
1939 word. We only look for the simplest cases, to do more would cost
1940 too much. Be careful, however, not to generate this when the
1941 alternative would take fewer insns. */
1942 if (val & 0xffff0000)
1944 temp1 = remainder & 0xffff0000;
1945 temp2 = remainder & 0x0000ffff;
1947 /* Overlaps outside this range are best done using other methods. */
1948 for (i = 9; i < 24; i++)
1950 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1951 && !const_ok_for_arm (temp2))
1953 rtx new_src = (subtargets
1954 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1956 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1957 source, subtargets, generate);
1965 gen_rtx_ASHIFT (mode, source,
1972 /* Don't duplicate cases already considered. */
1973 for (i = 17; i < 24; i++)
1975 if (((temp1 | (temp1 >> i)) == remainder)
1976 && !const_ok_for_arm (temp1))
1978 rtx new_src = (subtargets
1979 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1981 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1982 source, subtargets, generate);
1987 gen_rtx_SET (VOIDmode, target,
1990 gen_rtx_LSHIFTRT (mode, source,
2001 /* If we have IOR or XOR, and the constant can be loaded in a
2002 single instruction, and we can find a temporary to put it in,
2003 then this can be done in two instructions instead of 3-4. */
2005 /* TARGET can't be NULL if SUBTARGETS is 0 */
2006 || (reload_completed && !reg_mentioned_p (target, source)))
2008 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2012 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2014 emit_constant_insn (cond,
2015 gen_rtx_SET (VOIDmode, sub,
2017 emit_constant_insn (cond,
2018 gen_rtx_SET (VOIDmode, target,
2019 gen_rtx_fmt_ee (code, mode,
2029 if (set_sign_bit_copies > 8
2030 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2034 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2035 rtx shift = GEN_INT (set_sign_bit_copies);
2039 gen_rtx_SET (VOIDmode, sub,
2041 gen_rtx_ASHIFT (mode,
2046 gen_rtx_SET (VOIDmode, target,
2048 gen_rtx_LSHIFTRT (mode, sub,
2054 if (set_zero_bit_copies > 8
2055 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2059 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2060 rtx shift = GEN_INT (set_zero_bit_copies);
2064 gen_rtx_SET (VOIDmode, sub,
2066 gen_rtx_LSHIFTRT (mode,
2071 gen_rtx_SET (VOIDmode, target,
2073 gen_rtx_ASHIFT (mode, sub,
2079 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2083 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2084 emit_constant_insn (cond,
2085 gen_rtx_SET (VOIDmode, sub,
2086 gen_rtx_NOT (mode, source)));
2089 sub = gen_reg_rtx (mode);
2090 emit_constant_insn (cond,
2091 gen_rtx_SET (VOIDmode, sub,
2092 gen_rtx_AND (mode, source,
2094 emit_constant_insn (cond,
2095 gen_rtx_SET (VOIDmode, target,
2096 gen_rtx_NOT (mode, sub)));
2103 /* See if two shifts will do 2 or more insn's worth of work. */
2104 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2106 HOST_WIDE_INT shift_mask = ((0xffffffff
2107 << (32 - clear_sign_bit_copies))
2110 if ((remainder | shift_mask) != 0xffffffff)
2114 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2115 insns = arm_gen_constant (AND, mode, cond,
2116 remainder | shift_mask,
2117 new_src, source, subtargets, 1);
2122 rtx targ = subtargets ? NULL_RTX : target;
2123 insns = arm_gen_constant (AND, mode, cond,
2124 remainder | shift_mask,
2125 targ, source, subtargets, 0);
2131 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2132 rtx shift = GEN_INT (clear_sign_bit_copies);
2134 emit_insn (gen_ashlsi3 (new_src, source, shift));
2135 emit_insn (gen_lshrsi3 (target, new_src, shift));
2141 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2143 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2145 if ((remainder | shift_mask) != 0xffffffff)
2149 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2151 insns = arm_gen_constant (AND, mode, cond,
2152 remainder | shift_mask,
2153 new_src, source, subtargets, 1);
2158 rtx targ = subtargets ? NULL_RTX : target;
2160 insns = arm_gen_constant (AND, mode, cond,
2161 remainder | shift_mask,
2162 targ, source, subtargets, 0);
2168 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2169 rtx shift = GEN_INT (clear_zero_bit_copies);
2171 emit_insn (gen_lshrsi3 (new_src, source, shift));
2172 emit_insn (gen_ashlsi3 (target, new_src, shift));
2184 for (i = 0; i < 32; i++)
2185 if (remainder & (1 << i))
2188 if (code == AND || (can_invert && num_bits_set > 16))
2189 remainder = (~remainder) & 0xffffffff;
2190 else if (code == PLUS && num_bits_set > 16)
2191 remainder = (-remainder) & 0xffffffff;
2198 /* Now try and find a way of doing the job in either two or three
2200 We start by looking for the largest block of zeros that are aligned on
2201 a 2-bit boundary, we then fill up the temps, wrapping around to the
2202 top of the word when we drop off the bottom.
2203 In the worst case this code should produce no more than four insns. */
2206 int best_consecutive_zeros = 0;
2208 for (i = 0; i < 32; i += 2)
2210 int consecutive_zeros = 0;
2212 if (!(remainder & (3 << i)))
2214 while ((i < 32) && !(remainder & (3 << i)))
2216 consecutive_zeros += 2;
2219 if (consecutive_zeros > best_consecutive_zeros)
2221 best_consecutive_zeros = consecutive_zeros;
2222 best_start = i - consecutive_zeros;
2228 /* So long as it won't require any more insns to do so, it's
2229 desirable to emit a small constant (in bits 0...9) in the last
2230 insn. This way there is more chance that it can be combined with
2231 a later addressing insn to form a pre-indexed load or store
2232 operation. Consider:
2234 *((volatile int *)0xe0000100) = 1;
2235 *((volatile int *)0xe0000110) = 2;
2237 We want this to wind up as:
2241 str rB, [rA, #0x100]
2243 str rB, [rA, #0x110]
2245 rather than having to synthesize both large constants from scratch.
2247 Therefore, we calculate how many insns would be required to emit
2248 the constant starting from `best_start', and also starting from
2249 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2250 yield a shorter sequence, we may as well use zero. */
2252 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2253 && (count_insns_for_constant (remainder, 0) <=
2254 count_insns_for_constant (remainder, best_start)))
2257 /* Now start emitting the insns. */
2265 if (remainder & (3 << (i - 2)))
2270 temp1 = remainder & ((0x0ff << end)
2271 | ((i < end) ? (0xff >> (32 - end)) : 0));
2272 remainder &= ~temp1;
2276 rtx new_src, temp1_rtx;
2278 if (code == SET || code == MINUS)
2280 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2281 if (can_invert && code != MINUS)
2286 if (remainder && subtargets)
2287 new_src = gen_reg_rtx (mode);
2292 else if (can_negate)
2296 temp1 = trunc_int_for_mode (temp1, mode);
2297 temp1_rtx = GEN_INT (temp1);
2301 else if (code == MINUS)
2302 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2304 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2306 emit_constant_insn (cond,
2307 gen_rtx_SET (VOIDmode, new_src,
2317 else if (code == MINUS)
2331 /* Canonicalize a comparison so that we are more likely to recognize it.
2332 This can be done for a few constant compares, where we can make the
2333 immediate value easier to load. */
2336 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2339 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2340 unsigned HOST_WIDE_INT maxval;
2341 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2352 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2354 *op1 = GEN_INT (i + 1);
2355 return code == GT ? GE : LT;
2362 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2364 *op1 = GEN_INT (i - 1);
2365 return code == GE ? GT : LE;
2371 if (i != ~((unsigned HOST_WIDE_INT) 0)
2372 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2374 *op1 = GEN_INT (i + 1);
2375 return code == GTU ? GEU : LTU;
2382 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2384 *op1 = GEN_INT (i - 1);
2385 return code == GEU ? GTU : LEU;
2397 /* Define how to find the value returned by a function. */
2400 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2402 enum machine_mode mode;
2403 int unsignedp ATTRIBUTE_UNUSED;
2404 rtx r ATTRIBUTE_UNUSED;
2406 mode = TYPE_MODE (type);
2407 /* Promote integer types. */
2408 if (INTEGRAL_TYPE_P (type))
2409 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2411 /* Promotes small structs returned in a register to full-word size
2412 for big-endian AAPCS. */
2413 if (arm_return_in_msb (type))
2415 HOST_WIDE_INT size = int_size_in_bytes (type);
2416 if (size % UNITS_PER_WORD != 0)
2418 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2419 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2423 return LIBCALL_VALUE(mode);
2426 /* Determine the amount of memory needed to store the possible return
2427 registers of an untyped call. */
2429 arm_apply_result_size (void)
2435 if (TARGET_HARD_FLOAT_ABI)
2439 if (TARGET_MAVERICK)
2442 if (TARGET_IWMMXT_ABI)
2449 /* Decide whether a type should be returned in memory (true)
2450 or in a register (false). This is called by the macro
2451 RETURN_IN_MEMORY. */
2453 arm_return_in_memory (tree type)
2457 if (!AGGREGATE_TYPE_P (type) &&
2458 (TREE_CODE (type) != VECTOR_TYPE) &&
2459 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2460 /* All simple types are returned in registers.
2461 For AAPCS, complex types are treated the same as aggregates. */
2464 size = int_size_in_bytes (type);
2466 if (arm_abi != ARM_ABI_APCS)
2468 /* ATPCS and later return aggregate types in memory only if they are
2469 larger than a word (or are variable size). */
2470 return (size < 0 || size > UNITS_PER_WORD);
2473 /* To maximize backwards compatibility with previous versions of gcc,
2474 return vectors up to 4 words in registers. */
2475 if (TREE_CODE (type) == VECTOR_TYPE)
2476 return (size < 0 || size > (4 * UNITS_PER_WORD));
2478 /* For the arm-wince targets we choose to be compatible with Microsoft's
2479 ARM and Thumb compilers, which always return aggregates in memory. */
2481 /* All structures/unions bigger than one word are returned in memory.
2482 Also catch the case where int_size_in_bytes returns -1. In this case
2483 the aggregate is either huge or of variable size, and in either case
2484 we will want to return it via memory and not in a register. */
2485 if (size < 0 || size > UNITS_PER_WORD)
2488 if (TREE_CODE (type) == RECORD_TYPE)
2492 /* For a struct the APCS says that we only return in a register
2493 if the type is 'integer like' and every addressable element
2494 has an offset of zero. For practical purposes this means
2495 that the structure can have at most one non bit-field element
2496 and that this element must be the first one in the structure. */
2498 /* Find the first field, ignoring non FIELD_DECL things which will
2499 have been created by C++. */
2500 for (field = TYPE_FIELDS (type);
2501 field && TREE_CODE (field) != FIELD_DECL;
2502 field = TREE_CHAIN (field))
2506 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2508 /* Check that the first field is valid for returning in a register. */
2510 /* ... Floats are not allowed */
2511 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2514 /* ... Aggregates that are not themselves valid for returning in
2515 a register are not allowed. */
2516 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2519 /* Now check the remaining fields, if any. Only bitfields are allowed,
2520 since they are not addressable. */
2521 for (field = TREE_CHAIN (field);
2523 field = TREE_CHAIN (field))
2525 if (TREE_CODE (field) != FIELD_DECL)
2528 if (!DECL_BIT_FIELD_TYPE (field))
2535 if (TREE_CODE (type) == UNION_TYPE)
2539 /* Unions can be returned in registers if every element is
2540 integral, or can be returned in an integer register. */
2541 for (field = TYPE_FIELDS (type);
2543 field = TREE_CHAIN (field))
2545 if (TREE_CODE (field) != FIELD_DECL)
2548 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2551 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2557 #endif /* not ARM_WINCE */
2559 /* Return all other types in memory. */
2563 /* Indicate whether or not words of a double are in big-endian order. */
2566 arm_float_words_big_endian (void)
2568 if (TARGET_MAVERICK)
2571 /* For FPA, float words are always big-endian. For VFP, floats words
2572 follow the memory system mode. */
2580 return (TARGET_BIG_END ? 1 : 0);
2585 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2586 for a call to a function whose data type is FNTYPE.
2587 For a library call, FNTYPE is NULL. */
2589 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2590 rtx libname ATTRIBUTE_UNUSED,
2591 tree fndecl ATTRIBUTE_UNUSED)
2593 /* On the ARM, the offset starts at 0. */
2594 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2595 pcum->iwmmxt_nregs = 0;
2596 pcum->can_split = true;
2598 pcum->call_cookie = CALL_NORMAL;
2600 if (TARGET_LONG_CALLS)
2601 pcum->call_cookie = CALL_LONG;
2603 /* Check for long call/short call attributes. The attributes
2604 override any command line option. */
2607 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2608 pcum->call_cookie = CALL_SHORT;
2609 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2610 pcum->call_cookie = CALL_LONG;
2613 /* Varargs vectors are treated the same as long long.
2614 named_count avoids having to change the way arm handles 'named' */
2615 pcum->named_count = 0;
2618 if (TARGET_REALLY_IWMMXT && fntype)
2622 for (fn_arg = TYPE_ARG_TYPES (fntype);
2624 fn_arg = TREE_CHAIN (fn_arg))
2625 pcum->named_count += 1;
2627 if (! pcum->named_count)
2628 pcum->named_count = INT_MAX;
2633 /* Return true if mode/type need doubleword alignment. */
2635 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2637 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2638 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2642 /* Determine where to put an argument to a function.
2643 Value is zero to push the argument on the stack,
2644 or a hard register in which to store the argument.
2646 MODE is the argument's machine mode.
2647 TYPE is the data type of the argument (as a tree).
2648 This is null for libcalls where that information may
2650 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2651 the preceding args and about the function being called.
2652 NAMED is nonzero if this argument is a named parameter
2653 (otherwise it is an extra parameter matching an ellipsis). */
2656 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2657 tree type, int named)
2661 /* Varargs vectors are treated the same as long long.
2662 named_count avoids having to change the way arm handles 'named' */
2663 if (TARGET_IWMMXT_ABI
2664 && arm_vector_mode_supported_p (mode)
2665 && pcum->named_count > pcum->nargs + 1)
2667 if (pcum->iwmmxt_nregs <= 9)
2668 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2671 pcum->can_split = false;
2676 /* Put doubleword aligned quantities in even register pairs. */
2678 && ARM_DOUBLEWORD_ALIGN
2679 && arm_needs_doubleword_align (mode, type))
2682 if (mode == VOIDmode)
2683 /* Compute operand 2 of the call insn. */
2684 return GEN_INT (pcum->call_cookie);
2686 /* Only allow splitting an arg between regs and memory if all preceding
2687 args were allocated to regs. For args passed by reference we only count
2688 the reference pointer. */
2689 if (pcum->can_split)
2692 nregs = ARM_NUM_REGS2 (mode, type);
2694 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2697 return gen_rtx_REG (mode, pcum->nregs);
2701 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2702 tree type, bool named ATTRIBUTE_UNUSED)
2704 int nregs = pcum->nregs;
2706 if (arm_vector_mode_supported_p (mode))
2709 if (NUM_ARG_REGS > nregs
2710 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2712 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2717 /* Variable sized types are passed by reference. This is a GCC
2718 extension to the ARM ABI. */
2721 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2722 enum machine_mode mode ATTRIBUTE_UNUSED,
2723 tree type, bool named ATTRIBUTE_UNUSED)
2725 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2728 /* Encode the current state of the #pragma [no_]long_calls. */
2731 OFF, /* No #pramgma [no_]long_calls is in effect. */
2732 LONG, /* #pragma long_calls is in effect. */
2733 SHORT /* #pragma no_long_calls is in effect. */
2736 static arm_pragma_enum arm_pragma_long_calls = OFF;
2739 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2741 arm_pragma_long_calls = LONG;
2745 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2747 arm_pragma_long_calls = SHORT;
2751 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2753 arm_pragma_long_calls = OFF;
2756 /* Table of machine attributes. */
2757 const struct attribute_spec arm_attribute_table[] =
2759 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2760 /* Function calls made to this symbol must be done indirectly, because
2761 it may lie outside of the 26 bit addressing range of a normal function
2763 { "long_call", 0, 0, false, true, true, NULL },
2764 /* Whereas these functions are always known to reside within the 26 bit
2765 addressing range. */
2766 { "short_call", 0, 0, false, true, true, NULL },
2767 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2768 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2769 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2770 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2772 /* ARM/PE has three new attributes:
2774 dllexport - for exporting a function/variable that will live in a dll
2775 dllimport - for importing a function/variable from a dll
2777 Microsoft allows multiple declspecs in one __declspec, separating
2778 them with spaces. We do NOT support this. Instead, use __declspec
2781 { "dllimport", 0, 0, true, false, false, NULL },
2782 { "dllexport", 0, 0, true, false, false, NULL },
2783 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2784 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2785 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2786 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2787 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2789 { NULL, 0, 0, false, false, false, NULL }
2792 /* Handle an attribute requiring a FUNCTION_DECL;
2793 arguments as in struct attribute_spec.handler. */
2795 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2796 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2798 if (TREE_CODE (*node) != FUNCTION_DECL)
2800 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2801 IDENTIFIER_POINTER (name));
2802 *no_add_attrs = true;
2808 /* Handle an "interrupt" or "isr" attribute;
2809 arguments as in struct attribute_spec.handler. */
2811 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2816 if (TREE_CODE (*node) != FUNCTION_DECL)
2818 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2819 IDENTIFIER_POINTER (name));
2820 *no_add_attrs = true;
2822 /* FIXME: the argument if any is checked for type attributes;
2823 should it be checked for decl ones? */
2827 if (TREE_CODE (*node) == FUNCTION_TYPE
2828 || TREE_CODE (*node) == METHOD_TYPE)
2830 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2832 warning (OPT_Wattributes, "%qs attribute ignored",
2833 IDENTIFIER_POINTER (name));
2834 *no_add_attrs = true;
2837 else if (TREE_CODE (*node) == POINTER_TYPE
2838 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2839 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2840 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2842 *node = build_variant_type_copy (*node);
2843 TREE_TYPE (*node) = build_type_attribute_variant
2845 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2846 *no_add_attrs = true;
2850 /* Possibly pass this attribute on from the type to a decl. */
2851 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2852 | (int) ATTR_FLAG_FUNCTION_NEXT
2853 | (int) ATTR_FLAG_ARRAY_NEXT))
2855 *no_add_attrs = true;
2856 return tree_cons (name, args, NULL_TREE);
2860 warning (OPT_Wattributes, "%qs attribute ignored",
2861 IDENTIFIER_POINTER (name));
2869 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2870 /* Handle the "notshared" attribute. This attribute is another way of
2871 requesting hidden visibility. ARM's compiler supports
2872 "__declspec(notshared)"; we support the same thing via an
2876 arm_handle_notshared_attribute (tree *node,
2877 tree name ATTRIBUTE_UNUSED,
2878 tree args ATTRIBUTE_UNUSED,
2879 int flags ATTRIBUTE_UNUSED,
2882 tree decl = TYPE_NAME (*node);
2886 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2887 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2888 *no_add_attrs = false;
2894 /* Return 0 if the attributes for two types are incompatible, 1 if they
2895 are compatible, and 2 if they are nearly compatible (which causes a
2896 warning to be generated). */
2898 arm_comp_type_attributes (tree type1, tree type2)
2902 /* Check for mismatch of non-default calling convention. */
2903 if (TREE_CODE (type1) != FUNCTION_TYPE)
2906 /* Check for mismatched call attributes. */
2907 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2908 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2909 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2910 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2912 /* Only bother to check if an attribute is defined. */
2913 if (l1 | l2 | s1 | s2)
2915 /* If one type has an attribute, the other must have the same attribute. */
2916 if ((l1 != l2) || (s1 != s2))
2919 /* Disallow mixed attributes. */
2920 if ((l1 & s2) || (l2 & s1))
2924 /* Check for mismatched ISR attribute. */
2925 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2927 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2928 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2930 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2937 /* Encode long_call or short_call attribute by prefixing
2938 symbol name in DECL with a special character FLAG. */
2940 arm_encode_call_attribute (tree decl, int flag)
2942 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2943 int len = strlen (str);
2946 /* Do not allow weak functions to be treated as short call. */
2947 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2950 newstr = alloca (len + 2);
2952 strcpy (newstr + 1, str);
2954 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2955 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2958 /* Assigns default attributes to newly defined type. This is used to
2959 set short_call/long_call attributes for function types of
2960 functions defined inside corresponding #pragma scopes. */
2962 arm_set_default_type_attributes (tree type)
2964 /* Add __attribute__ ((long_call)) to all functions, when
2965 inside #pragma long_calls or __attribute__ ((short_call)),
2966 when inside #pragma no_long_calls. */
2967 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2969 tree type_attr_list, attr_name;
2970 type_attr_list = TYPE_ATTRIBUTES (type);
2972 if (arm_pragma_long_calls == LONG)
2973 attr_name = get_identifier ("long_call");
2974 else if (arm_pragma_long_calls == SHORT)
2975 attr_name = get_identifier ("short_call");
2979 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2980 TYPE_ATTRIBUTES (type) = type_attr_list;
2984 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2985 defined within the current compilation unit. If this cannot be
2986 determined, then 0 is returned. */
2988 current_file_function_operand (rtx sym_ref)
2990 /* This is a bit of a fib. A function will have a short call flag
2991 applied to its name if it has the short call attribute, or it has
2992 already been defined within the current compilation unit. */
2993 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2996 /* The current function is always defined within the current compilation
2997 unit. If it s a weak definition however, then this may not be the real
2998 definition of the function, and so we have to say no. */
2999 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3000 && !DECL_WEAK (current_function_decl))
3003 /* We cannot make the determination - default to returning 0. */
3007 /* Return nonzero if a 32 bit "long_call" should be generated for
3008 this call. We generate a long_call if the function:
3010 a. has an __attribute__((long call))
3011 or b. is within the scope of a #pragma long_calls
3012 or c. the -mlong-calls command line switch has been specified
3014 1. -ffunction-sections is in effect
3015 or 2. the current function has __attribute__ ((section))
3016 or 3. the target function has __attribute__ ((section))
3018 However we do not generate a long call if the function:
3020 d. has an __attribute__ ((short_call))
3021 or e. is inside the scope of a #pragma no_long_calls
3022 or f. is defined within the current compilation unit.
3024 This function will be called by C fragments contained in the machine
3025 description file. SYM_REF and CALL_COOKIE correspond to the matched
3026 rtl operands. CALL_SYMBOL is used to distinguish between
3027 two different callers of the function. It is set to 1 in the
3028 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3029 and "call_value" patterns. This is because of the difference in the
3030 SYM_REFs passed by these patterns. */
3032 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3036 if (GET_CODE (sym_ref) != MEM)
3039 sym_ref = XEXP (sym_ref, 0);
3042 if (GET_CODE (sym_ref) != SYMBOL_REF)
3045 if (call_cookie & CALL_SHORT)
3048 if (TARGET_LONG_CALLS)
3050 if (flag_function_sections
3051 || DECL_SECTION_NAME (current_function_decl))
3052 /* c.3 is handled by the definition of the
3053 ARM_DECLARE_FUNCTION_SIZE macro. */
3057 if (current_file_function_operand (sym_ref))
3060 return (call_cookie & CALL_LONG)
3061 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3062 || TARGET_LONG_CALLS;
3065 /* Return nonzero if it is ok to make a tail-call to DECL. */
3067 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3069 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3071 if (cfun->machine->sibcall_blocked)
3074 /* Never tailcall something for which we have no decl, or if we
3075 are in Thumb mode. */
3076 if (decl == NULL || TARGET_THUMB)
3079 /* Get the calling method. */
3080 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3081 call_type = CALL_SHORT;
3082 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3083 call_type = CALL_LONG;
3085 /* Cannot tail-call to long calls, since these are out of range of
3086 a branch instruction. However, if not compiling PIC, we know
3087 we can reach the symbol if it is in this compilation unit. */
3088 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3091 /* If we are interworking and the function is not declared static
3092 then we can't tail-call it unless we know that it exists in this
3093 compilation unit (since it might be a Thumb routine). */
3094 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3097 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3098 if (IS_INTERRUPT (arm_current_func_type ()))
3101 /* Everything else is ok. */
3106 /* Addressing mode support functions. */
3108 /* Return nonzero if X is a legitimate immediate operand when compiling
3111 legitimate_pic_operand_p (rtx x)
3115 && (GET_CODE (x) == SYMBOL_REF
3116 || (GET_CODE (x) == CONST
3117 && GET_CODE (XEXP (x, 0)) == PLUS
3118 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
3125 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3127 if (GET_CODE (orig) == SYMBOL_REF
3128 || GET_CODE (orig) == LABEL_REF)
3130 #ifndef AOF_ASSEMBLER
3131 rtx pic_ref, address;
3138 gcc_assert (!no_new_pseudos);
3139 reg = gen_reg_rtx (Pmode);
3144 #ifdef AOF_ASSEMBLER
3145 /* The AOF assembler can generate relocations for these directly, and
3146 understands that the PIC register has to be added into the offset. */
3147 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3150 address = gen_reg_rtx (Pmode);
3155 emit_insn (gen_pic_load_addr_arm (address, orig));
3157 emit_insn (gen_pic_load_addr_thumb (address, orig));
3159 if ((GET_CODE (orig) == LABEL_REF
3160 || (GET_CODE (orig) == SYMBOL_REF &&
3161 SYMBOL_REF_LOCAL_P (orig)))
3163 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
3166 pic_ref = gen_const_mem (Pmode,
3167 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3171 insn = emit_move_insn (reg, pic_ref);
3173 current_function_uses_pic_offset_table = 1;
3174 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3176 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3180 else if (GET_CODE (orig) == CONST)
3184 if (GET_CODE (XEXP (orig, 0)) == PLUS
3185 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3190 gcc_assert (!no_new_pseudos);
3191 reg = gen_reg_rtx (Pmode);
3194 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3196 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3197 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3198 base == reg ? 0 : reg);
3200 if (GET_CODE (offset) == CONST_INT)
3202 /* The base register doesn't really matter, we only want to
3203 test the index for the appropriate mode. */
3204 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3206 gcc_assert (!no_new_pseudos);
3207 offset = force_reg (Pmode, offset);
3210 if (GET_CODE (offset) == CONST_INT)
3211 return plus_constant (base, INTVAL (offset));
3214 if (GET_MODE_SIZE (mode) > 4
3215 && (GET_MODE_CLASS (mode) == MODE_INT
3216 || TARGET_SOFT_FLOAT))
3218 emit_insn (gen_addsi3 (reg, base, offset));
3222 return gen_rtx_PLUS (Pmode, base, offset);
3229 /* Find a spare low register to use during the prolog of a function. */
3232 thumb_find_work_register (unsigned long pushed_regs_mask)
3236 /* Check the argument registers first as these are call-used. The
3237 register allocation order means that sometimes r3 might be used
3238 but earlier argument registers might not, so check them all. */
3239 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3240 if (!regs_ever_live[reg])
3243 /* Before going on to check the call-saved registers we can try a couple
3244 more ways of deducing that r3 is available. The first is when we are
3245 pushing anonymous arguments onto the stack and we have less than 4
3246 registers worth of fixed arguments(*). In this case r3 will be part of
3247 the variable argument list and so we can be sure that it will be
3248 pushed right at the start of the function. Hence it will be available
3249 for the rest of the prologue.
3250 (*): ie current_function_pretend_args_size is greater than 0. */
3251 if (cfun->machine->uses_anonymous_args
3252 && current_function_pretend_args_size > 0)
3253 return LAST_ARG_REGNUM;
3255 /* The other case is when we have fixed arguments but less than 4 registers
3256 worth. In this case r3 might be used in the body of the function, but
3257 it is not being used to convey an argument into the function. In theory
3258 we could just check current_function_args_size to see how many bytes are
3259 being passed in argument registers, but it seems that it is unreliable.
3260 Sometimes it will have the value 0 when in fact arguments are being
3261 passed. (See testcase execute/20021111-1.c for an example). So we also
3262 check the args_info.nregs field as well. The problem with this field is
3263 that it makes no allowances for arguments that are passed to the
3264 function but which are not used. Hence we could miss an opportunity
3265 when a function has an unused argument in r3. But it is better to be
3266 safe than to be sorry. */
3267 if (! cfun->machine->uses_anonymous_args
3268 && current_function_args_size >= 0
3269 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3270 && cfun->args_info.nregs < 4)
3271 return LAST_ARG_REGNUM;
3273 /* Otherwise look for a call-saved register that is going to be pushed. */
3274 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3275 if (pushed_regs_mask & (1 << reg))
3278 /* Something went wrong - thumb_compute_save_reg_mask()
3279 should have arranged for a suitable register to be pushed. */
3284 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3288 arm_load_pic_register (unsigned int scratch)
3290 #ifndef AOF_ASSEMBLER
3291 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3292 rtx global_offset_table;
3294 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3297 gcc_assert (flag_pic);
3299 l1 = gen_label_rtx ();
3301 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3302 /* On the ARM the PC register contains 'dot + 8' at the time of the
3303 addition, on the Thumb it is 'dot + 4'. */
3304 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3306 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3307 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3309 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3311 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3315 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3316 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3320 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3322 /* We will have pushed the pic register, so should always be
3323 able to find a work register. */
3324 pic_tmp = gen_rtx_REG (SImode, scratch);
3325 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3326 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3329 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3330 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3333 /* Need to emit this whether or not we obey regdecls,
3334 since setjmp/longjmp can cause life info to screw up. */
3335 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3336 #endif /* AOF_ASSEMBLER */
3340 /* Return nonzero if X is valid as an ARM state addressing register. */
3342 arm_address_register_rtx_p (rtx x, int strict_p)
3346 if (GET_CODE (x) != REG)
3352 return ARM_REGNO_OK_FOR_BASE_P (regno);
3354 return (regno <= LAST_ARM_REGNUM
3355 || regno >= FIRST_PSEUDO_REGISTER
3356 || regno == FRAME_POINTER_REGNUM
3357 || regno == ARG_POINTER_REGNUM);
3360 /* Return nonzero if X is a valid ARM state address operand. */
3362 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3366 enum rtx_code code = GET_CODE (x);
3368 if (arm_address_register_rtx_p (x, strict_p))
3371 use_ldrd = (TARGET_LDRD
3373 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3375 if (code == POST_INC || code == PRE_DEC
3376 || ((code == PRE_INC || code == POST_DEC)
3377 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3378 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3380 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3381 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3382 && GET_CODE (XEXP (x, 1)) == PLUS
3383 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3385 rtx addend = XEXP (XEXP (x, 1), 1);
3387 /* Don't allow ldrd post increment by register because it's hard
3388 to fixup invalid register choices. */
3390 && GET_CODE (x) == POST_MODIFY
3391 && GET_CODE (addend) == REG)
3394 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3395 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3398 /* After reload constants split into minipools will have addresses
3399 from a LABEL_REF. */
3400 else if (reload_completed
3401 && (code == LABEL_REF
3403 && GET_CODE (XEXP (x, 0)) == PLUS
3404 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3405 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3408 else if (mode == TImode)
3411 else if (code == PLUS)
3413 rtx xop0 = XEXP (x, 0);
3414 rtx xop1 = XEXP (x, 1);
3416 return ((arm_address_register_rtx_p (xop0, strict_p)
3417 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3418 || (arm_address_register_rtx_p (xop1, strict_p)
3419 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3423 /* Reload currently can't handle MINUS, so disable this for now */
3424 else if (GET_CODE (x) == MINUS)
3426 rtx xop0 = XEXP (x, 0);
3427 rtx xop1 = XEXP (x, 1);
3429 return (arm_address_register_rtx_p (xop0, strict_p)
3430 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3434 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3435 && code == SYMBOL_REF
3436 && CONSTANT_POOL_ADDRESS_P (x)
3438 && symbol_mentioned_p (get_pool_constant (x))))
3444 /* Return nonzero if INDEX is valid for an address index operand in
3447 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3450 HOST_WIDE_INT range;
3451 enum rtx_code code = GET_CODE (index);
3453 /* Standard coprocessor addressing modes. */
3454 if (TARGET_HARD_FLOAT
3455 && (TARGET_FPA || TARGET_MAVERICK)
3456 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3457 || (TARGET_MAVERICK && mode == DImode)))
3458 return (code == CONST_INT && INTVAL (index) < 1024
3459 && INTVAL (index) > -1024
3460 && (INTVAL (index) & 3) == 0);
3462 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3463 return (code == CONST_INT
3464 && INTVAL (index) < 1024
3465 && INTVAL (index) > -1024
3466 && (INTVAL (index) & 3) == 0);
3468 if (arm_address_register_rtx_p (index, strict_p)
3469 && (GET_MODE_SIZE (mode) <= 4))
3472 if (mode == DImode || mode == DFmode)
3474 if (code == CONST_INT)
3476 HOST_WIDE_INT val = INTVAL (index);
3479 return val > -256 && val < 256;
3481 return val > -4096 && val < 4092;
3484 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3487 if (GET_MODE_SIZE (mode) <= 4
3490 || (mode == QImode && outer == SIGN_EXTEND))))
3494 rtx xiop0 = XEXP (index, 0);
3495 rtx xiop1 = XEXP (index, 1);
3497 return ((arm_address_register_rtx_p (xiop0, strict_p)
3498 && power_of_two_operand (xiop1, SImode))
3499 || (arm_address_register_rtx_p (xiop1, strict_p)
3500 && power_of_two_operand (xiop0, SImode)));
3502 else if (code == LSHIFTRT || code == ASHIFTRT
3503 || code == ASHIFT || code == ROTATERT)
3505 rtx op = XEXP (index, 1);
3507 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3508 && GET_CODE (op) == CONST_INT
3510 && INTVAL (op) <= 31);
3514 /* For ARM v4 we may be doing a sign-extend operation during the
3518 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3524 range = (mode == HImode) ? 4095 : 4096;
3526 return (code == CONST_INT
3527 && INTVAL (index) < range
3528 && INTVAL (index) > -range);
3531 /* Return nonzero if X is valid as a Thumb state base register. */
3533 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3537 if (GET_CODE (x) != REG)
3543 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3545 return (regno <= LAST_LO_REGNUM
3546 || regno > LAST_VIRTUAL_REGISTER
3547 || regno == FRAME_POINTER_REGNUM
3548 || (GET_MODE_SIZE (mode) >= 4
3549 && (regno == STACK_POINTER_REGNUM
3550 || regno >= FIRST_PSEUDO_REGISTER
3551 || x == hard_frame_pointer_rtx
3552 || x == arg_pointer_rtx)));
3555 /* Return nonzero if x is a legitimate index register. This is the case
3556 for any base register that can access a QImode object. */
3558 thumb_index_register_rtx_p (rtx x, int strict_p)
3560 return thumb_base_register_rtx_p (x, QImode, strict_p);
3563 /* Return nonzero if x is a legitimate Thumb-state address.
3565 The AP may be eliminated to either the SP or the FP, so we use the
3566 least common denominator, e.g. SImode, and offsets from 0 to 64.
3568 ??? Verify whether the above is the right approach.
3570 ??? Also, the FP may be eliminated to the SP, so perhaps that
3571 needs special handling also.
3573 ??? Look at how the mips16 port solves this problem. It probably uses
3574 better ways to solve some of these problems.
3576 Although it is not incorrect, we don't accept QImode and HImode
3577 addresses based on the frame pointer or arg pointer until the
3578 reload pass starts. This is so that eliminating such addresses
3579 into stack based ones won't produce impossible code. */
3581 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3583 /* ??? Not clear if this is right. Experiment. */
3584 if (GET_MODE_SIZE (mode) < 4
3585 && !(reload_in_progress || reload_completed)
3586 && (reg_mentioned_p (frame_pointer_rtx, x)
3587 || reg_mentioned_p (arg_pointer_rtx, x)
3588 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3589 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3590 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3591 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3594 /* Accept any base register. SP only in SImode or larger. */
3595 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3598 /* This is PC relative data before arm_reorg runs. */
3599 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3600 && GET_CODE (x) == SYMBOL_REF
3601 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3604 /* This is PC relative data after arm_reorg runs. */
3605 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3606 && (GET_CODE (x) == LABEL_REF
3607 || (GET_CODE (x) == CONST
3608 && GET_CODE (XEXP (x, 0)) == PLUS
3609 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3610 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3613 /* Post-inc indexing only supported for SImode and larger. */
3614 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3615 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3618 else if (GET_CODE (x) == PLUS)
3620 /* REG+REG address can be any two index registers. */
3621 /* We disallow FRAME+REG addressing since we know that FRAME
3622 will be replaced with STACK, and SP relative addressing only
3623 permits SP+OFFSET. */
3624 if (GET_MODE_SIZE (mode) <= 4
3625 && XEXP (x, 0) != frame_pointer_rtx
3626 && XEXP (x, 1) != frame_pointer_rtx
3627 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3628 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3631 /* REG+const has 5-7 bit offset for non-SP registers. */
3632 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3633 || XEXP (x, 0) == arg_pointer_rtx)
3634 && GET_CODE (XEXP (x, 1)) == CONST_INT
3635 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3638 /* REG+const has 10 bit offset for SP, but only SImode and
3639 larger is supported. */
3640 /* ??? Should probably check for DI/DFmode overflow here
3641 just like GO_IF_LEGITIMATE_OFFSET does. */
3642 else if (GET_CODE (XEXP (x, 0)) == REG
3643 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3644 && GET_MODE_SIZE (mode) >= 4
3645 && GET_CODE (XEXP (x, 1)) == CONST_INT
3646 && INTVAL (XEXP (x, 1)) >= 0
3647 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3648 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3651 else if (GET_CODE (XEXP (x, 0)) == REG
3652 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3653 && GET_MODE_SIZE (mode) >= 4
3654 && GET_CODE (XEXP (x, 1)) == CONST_INT
3655 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3659 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3660 && GET_MODE_SIZE (mode) == 4
3661 && GET_CODE (x) == SYMBOL_REF
3662 && CONSTANT_POOL_ADDRESS_P (x)
3664 && symbol_mentioned_p (get_pool_constant (x))))
3670 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3671 instruction of mode MODE. */
3673 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3675 switch (GET_MODE_SIZE (mode))
3678 return val >= 0 && val < 32;
3681 return val >= 0 && val < 64 && (val & 1) == 0;
3685 && (val + GET_MODE_SIZE (mode)) <= 128
3690 /* Try machine-dependent ways of modifying an illegitimate address
3691 to be legitimate. If we find one, return the new, valid address. */
3693 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3695 if (GET_CODE (x) == PLUS)
3697 rtx xop0 = XEXP (x, 0);
3698 rtx xop1 = XEXP (x, 1);
3700 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3701 xop0 = force_reg (SImode, xop0);
3703 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3704 xop1 = force_reg (SImode, xop1);
3706 if (ARM_BASE_REGISTER_RTX_P (xop0)
3707 && GET_CODE (xop1) == CONST_INT)
3709 HOST_WIDE_INT n, low_n;
3713 /* VFP addressing modes actually allow greater offsets, but for
3714 now we just stick with the lowest common denominator. */
3716 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3728 low_n = ((mode) == TImode ? 0
3729 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3733 base_reg = gen_reg_rtx (SImode);
3734 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3735 GEN_INT (n)), NULL_RTX);
3736 emit_move_insn (base_reg, val);
3737 x = (low_n == 0 ? base_reg
3738 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3740 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3741 x = gen_rtx_PLUS (SImode, xop0, xop1);
3744 /* XXX We don't allow MINUS any more -- see comment in
3745 arm_legitimate_address_p (). */
3746 else if (GET_CODE (x) == MINUS)
3748 rtx xop0 = XEXP (x, 0);
3749 rtx xop1 = XEXP (x, 1);
3751 if (CONSTANT_P (xop0))
3752 xop0 = force_reg (SImode, xop0);
3754 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3755 xop1 = force_reg (SImode, xop1);
3757 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3758 x = gen_rtx_MINUS (SImode, xop0, xop1);
3763 /* We need to find and carefully transform any SYMBOL and LABEL
3764 references; so go back to the original address expression. */
3765 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3767 if (new_x != orig_x)
3775 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3776 to be legitimate. If we find one, return the new, valid address. */
3778 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3780 if (GET_CODE (x) == PLUS
3781 && GET_CODE (XEXP (x, 1)) == CONST_INT
3782 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3783 || INTVAL (XEXP (x, 1)) < 0))
3785 rtx xop0 = XEXP (x, 0);
3786 rtx xop1 = XEXP (x, 1);
3787 HOST_WIDE_INT offset = INTVAL (xop1);
3789 /* Try and fold the offset into a biasing of the base register and
3790 then offsetting that. Don't do this when optimizing for space
3791 since it can cause too many CSEs. */
3792 if (optimize_size && offset >= 0
3793 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3795 HOST_WIDE_INT delta;
3798 delta = offset - (256 - GET_MODE_SIZE (mode));
3799 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3800 delta = 31 * GET_MODE_SIZE (mode);
3802 delta = offset & (~31 * GET_MODE_SIZE (mode));
3804 xop0 = force_operand (plus_constant (xop0, offset - delta),
3806 x = plus_constant (xop0, delta);
3808 else if (offset < 0 && offset > -256)
3809 /* Small negative offsets are best done with a subtract before the
3810 dereference, forcing these into a register normally takes two
3812 x = force_operand (x, NULL_RTX);
3815 /* For the remaining cases, force the constant into a register. */
3816 xop1 = force_reg (SImode, xop1);
3817 x = gen_rtx_PLUS (SImode, xop0, xop1);
3820 else if (GET_CODE (x) == PLUS
3821 && s_register_operand (XEXP (x, 1), SImode)
3822 && !s_register_operand (XEXP (x, 0), SImode))
3824 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3826 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3831 /* We need to find and carefully transform any SYMBOL and LABEL
3832 references; so go back to the original address expression. */
3833 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3835 if (new_x != orig_x)
3843 thumb_legitimize_reload_address(rtx *x_p,
3844 enum machine_mode mode,
3845 int opnum, int type,
3846 int ind_levels ATTRIBUTE_UNUSED)
3850 if (GET_CODE (x) == PLUS
3851 && GET_MODE_SIZE (mode) < 4
3852 && REG_P (XEXP (x, 0))
3853 && XEXP (x, 0) == stack_pointer_rtx
3854 && GET_CODE (XEXP (x, 1)) == CONST_INT
3855 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3860 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
3861 Pmode, VOIDmode, 0, 0, opnum, type);
3865 /* If both registers are hi-regs, then it's better to reload the
3866 entire expression rather than each register individually. That
3867 only requires one reload register rather than two. */
3868 if (GET_CODE (x) == PLUS
3869 && REG_P (XEXP (x, 0))
3870 && REG_P (XEXP (x, 1))
3871 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
3872 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
3877 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
3878 Pmode, VOIDmode, 0, 0, opnum, type);
3887 #define REG_OR_SUBREG_REG(X) \
3888 (GET_CODE (X) == REG \
3889 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3891 #define REG_OR_SUBREG_RTX(X) \
3892 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3894 #ifndef COSTS_N_INSNS
3895 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3898 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3900 enum machine_mode mode = GET_MODE (x);
3913 return COSTS_N_INSNS (1);
3916 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3919 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3926 return COSTS_N_INSNS (2) + cycles;
3928 return COSTS_N_INSNS (1) + 16;
3931 return (COSTS_N_INSNS (1)
3932 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3933 + GET_CODE (SET_DEST (x)) == MEM));
3938 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3940 if (thumb_shiftable_const (INTVAL (x)))
3941 return COSTS_N_INSNS (2);
3942 return COSTS_N_INSNS (3);
3944 else if ((outer == PLUS || outer == COMPARE)
3945 && INTVAL (x) < 256 && INTVAL (x) > -256)
3947 else if (outer == AND
3948 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3949 return COSTS_N_INSNS (1);
3950 else if (outer == ASHIFT || outer == ASHIFTRT
3951 || outer == LSHIFTRT)
3953 return COSTS_N_INSNS (2);
3959 return COSTS_N_INSNS (3);
3977 /* XXX another guess. */
3978 /* Memory costs quite a lot for the first word, but subsequent words
3979 load at the equivalent of a single insn each. */
3980 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3981 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3986 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3991 /* XXX still guessing. */
3992 switch (GET_MODE (XEXP (x, 0)))
3995 return (1 + (mode == DImode ? 4 : 0)
3996 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3999 return (4 + (mode == DImode ? 4 : 0)
4000 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4003 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4015 /* Worker routine for arm_rtx_costs. */
4017 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4019 enum machine_mode mode = GET_MODE (x);
4020 enum rtx_code subcode;
4026 /* Memory costs quite a lot for the first word, but subsequent words
4027 load at the equivalent of a single insn each. */
4028 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4029 + (GET_CODE (x) == SYMBOL_REF
4030 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4036 return optimize_size ? COSTS_N_INSNS (2) : 100;
4039 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4046 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4048 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4049 + ((GET_CODE (XEXP (x, 0)) == REG
4050 || (GET_CODE (XEXP (x, 0)) == SUBREG
4051 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4053 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4054 || (GET_CODE (XEXP (x, 0)) == SUBREG
4055 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4057 + ((GET_CODE (XEXP (x, 1)) == REG
4058 || (GET_CODE (XEXP (x, 1)) == SUBREG
4059 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4060 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4065 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4066 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4067 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4068 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4071 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4072 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4073 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4074 && arm_const_double_rtx (XEXP (x, 1))))
4076 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4077 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4078 && arm_const_double_rtx (XEXP (x, 0))))
4081 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4082 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4083 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4084 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4085 || subcode == ASHIFTRT || subcode == LSHIFTRT
4086 || subcode == ROTATE || subcode == ROTATERT
4088 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4089 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4090 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4091 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4092 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4093 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4094 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4099 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4100 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4101 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4102 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4103 && arm_const_double_rtx (XEXP (x, 1))))
4107 case AND: case XOR: case IOR:
4110 /* Normally the frame registers will be spilt into reg+const during
4111 reload, so it is a bad idea to combine them with other instructions,
4112 since then they might not be moved outside of loops. As a compromise
4113 we allow integration with ops that have a constant as their second
4115 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4116 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4117 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4118 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4119 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4123 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4124 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4125 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4126 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4129 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4130 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4131 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4132 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4133 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4136 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4137 return (1 + extra_cost
4138 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4139 || subcode == LSHIFTRT || subcode == ASHIFTRT
4140 || subcode == ROTATE || subcode == ROTATERT
4142 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4143 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4144 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4145 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4146 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4147 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4153 /* This should have been handled by the CPU specific routines. */
4157 if (arm_arch3m && mode == SImode
4158 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4159 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4160 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4161 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4162 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4163 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4168 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4169 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4173 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4175 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4178 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4186 return 4 + (mode == DImode ? 4 : 0);
4189 if (GET_MODE (XEXP (x, 0)) == QImode)
4190 return (4 + (mode == DImode ? 4 : 0)
4191 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4194 switch (GET_MODE (XEXP (x, 0)))
4197 return (1 + (mode == DImode ? 4 : 0)
4198 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4201 return (4 + (mode == DImode ? 4 : 0)
4202 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4205 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4220 if (const_ok_for_arm (INTVAL (x)))
4221 return outer == SET ? 2 : -1;
4222 else if (outer == AND
4223 && const_ok_for_arm (~INTVAL (x)))
4225 else if ((outer == COMPARE
4226 || outer == PLUS || outer == MINUS)
4227 && const_ok_for_arm (-INTVAL (x)))
4238 if (arm_const_double_rtx (x))
4239 return outer == SET ? 2 : -1;
4240 else if ((outer == COMPARE || outer == PLUS)
4241 && neg_const_double_rtx_ok_for_fpa (x))
4250 /* RTX costs when optimizing for size. */
4252 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4254 enum machine_mode mode = GET_MODE (x);
4258 /* XXX TBD. For now, use the standard costs. */
4259 *total = thumb_rtx_costs (x, code, outer_code);
4266 /* A memory access costs 1 insn if the mode is small, or the address is
4267 a single register, otherwise it costs one insn per word. */
4268 if (REG_P (XEXP (x, 0)))
4269 *total = COSTS_N_INSNS (1);
4271 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4278 /* Needs a libcall, so it costs about this. */
4279 *total = COSTS_N_INSNS (2);
4283 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4285 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4293 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4295 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4298 else if (mode == SImode)
4300 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4301 /* Slightly disparage register shifts, but not by much. */
4302 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4303 *total += 1 + rtx_cost (XEXP (x, 1), code);
4307 /* Needs a libcall. */
4308 *total = COSTS_N_INSNS (2);
4312 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4314 *total = COSTS_N_INSNS (1);
4320 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4321 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4323 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4324 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4325 || subcode1 == ROTATE || subcode1 == ROTATERT
4326 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4327 || subcode1 == ASHIFTRT)
4329 /* It's just the cost of the two operands. */
4334 *total = COSTS_N_INSNS (1);
4338 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4342 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4344 *total = COSTS_N_INSNS (1);
4349 case AND: case XOR: case IOR:
4352 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4354 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4355 || subcode == LSHIFTRT || subcode == ASHIFTRT
4356 || (code == AND && subcode == NOT))
4358 /* It's just the cost of the two operands. */
4364 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4368 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4372 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4373 *total = COSTS_N_INSNS (1);
4376 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4385 if (cc_register (XEXP (x, 0), VOIDmode))
4388 *total = COSTS_N_INSNS (1);
4392 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4393 *total = COSTS_N_INSNS (1);
4395 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4400 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4402 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4403 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4406 *total += COSTS_N_INSNS (1);
4411 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4413 switch (GET_MODE (XEXP (x, 0)))
4416 *total += COSTS_N_INSNS (1);
4420 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4426 *total += COSTS_N_INSNS (2);
4431 *total += COSTS_N_INSNS (1);
4436 if (const_ok_for_arm (INTVAL (x)))
4437 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4438 else if (const_ok_for_arm (~INTVAL (x)))
4439 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4440 else if (const_ok_for_arm (-INTVAL (x)))
4442 if (outer_code == COMPARE || outer_code == PLUS
4443 || outer_code == MINUS)
4446 *total = COSTS_N_INSNS (1);
4449 *total = COSTS_N_INSNS (2);
4455 *total = COSTS_N_INSNS (2);
4459 *total = COSTS_N_INSNS (4);
4463 if (mode != VOIDmode)
4464 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4466 *total = COSTS_N_INSNS (4); /* How knows? */
4471 /* RTX costs for cores with a slow MUL implementation. */
4474 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4476 enum machine_mode mode = GET_MODE (x);
4480 *total = thumb_rtx_costs (x, code, outer_code);
4487 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4494 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4496 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4497 & (unsigned HOST_WIDE_INT) 0xffffffff);
4498 int cost, const_ok = const_ok_for_arm (i);
4499 int j, booth_unit_size;
4501 /* Tune as appropriate. */
4502 cost = const_ok ? 4 : 8;
4503 booth_unit_size = 2;
4504 for (j = 0; i && j < 32; j += booth_unit_size)
4506 i >>= booth_unit_size;
4514 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4515 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4519 *total = arm_rtx_costs_1 (x, code, outer_code);
4525 /* RTX cost for cores with a fast multiply unit (M variants). */
4528 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4530 enum machine_mode mode = GET_MODE (x);
4534 *total = thumb_rtx_costs (x, code, outer_code);
4541 /* There is no point basing this on the tuning, since it is always the
4542 fast variant if it exists at all. */
4544 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4545 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4546 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4553 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4560 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4562 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4563 & (unsigned HOST_WIDE_INT) 0xffffffff);
4564 int cost, const_ok = const_ok_for_arm (i);
4565 int j, booth_unit_size;
4567 /* Tune as appropriate. */
4568 cost = const_ok ? 4 : 8;
4569 booth_unit_size = 8;
4570 for (j = 0; i && j < 32; j += booth_unit_size)
4572 i >>= booth_unit_size;
4580 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4581 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4585 *total = arm_rtx_costs_1 (x, code, outer_code);
4591 /* RTX cost for XScale CPUs. */
4594 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4596 enum machine_mode mode = GET_MODE (x);
4600 *total = thumb_rtx_costs (x, code, outer_code);
4607 /* There is no point basing this on the tuning, since it is always the
4608 fast variant if it exists at all. */
4610 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4611 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4612 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4619 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4626 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4628 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4629 & (unsigned HOST_WIDE_INT) 0xffffffff);
4630 int cost, const_ok = const_ok_for_arm (i);
4631 unsigned HOST_WIDE_INT masked_const;
4633 /* The cost will be related to two insns.
4634 First a load of the constant (MOV or LDR), then a multiply. */
4637 cost += 1; /* LDR is probably more expensive because
4638 of longer result latency. */
4639 masked_const = i & 0xffff8000;
4640 if (masked_const != 0 && masked_const != 0xffff8000)
4642 masked_const = i & 0xf8000000;
4643 if (masked_const == 0 || masked_const == 0xf8000000)
4652 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4653 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4657 /* A COMPARE of a MULT is slow on XScale; the muls instruction
4658 will stall until the multiplication is complete. */
4659 if (GET_CODE (XEXP (x, 0)) == MULT)
4660 *total = 4 + rtx_cost (XEXP (x, 0), code);
4662 *total = arm_rtx_costs_1 (x, code, outer_code);
4666 *total = arm_rtx_costs_1 (x, code, outer_code);
4672 /* RTX costs for 9e (and later) cores. */
4675 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4677 enum machine_mode mode = GET_MODE (x);
4686 *total = COSTS_N_INSNS (3);
4690 *total = thumb_rtx_costs (x, code, outer_code);
4698 /* There is no point basing this on the tuning, since it is always the
4699 fast variant if it exists at all. */
4701 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4702 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4703 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4710 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4727 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4728 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4732 *total = arm_rtx_costs_1 (x, code, outer_code);
4736 /* All address computations that can be done are free, but rtx cost returns
4737 the same for practically all of them. So we weight the different types
4738 of address here in the order (most pref first):
4739 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4741 arm_arm_address_cost (rtx x)
4743 enum rtx_code c = GET_CODE (x);
4745 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4747 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4750 if (c == PLUS || c == MINUS)
4752 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4755 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4765 arm_thumb_address_cost (rtx x)
4767 enum rtx_code c = GET_CODE (x);
4772 && GET_CODE (XEXP (x, 0)) == REG
4773 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4780 arm_address_cost (rtx x)
4782 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4786 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4790 /* Some true dependencies can have a higher cost depending
4791 on precisely how certain input operands are used. */
4793 && REG_NOTE_KIND (link) == 0
4794 && recog_memoized (insn) >= 0
4795 && recog_memoized (dep) >= 0)
4797 int shift_opnum = get_attr_shift (insn);
4798 enum attr_type attr_type = get_attr_type (dep);
4800 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4801 operand for INSN. If we have a shifted input operand and the
4802 instruction we depend on is another ALU instruction, then we may
4803 have to account for an additional stall. */
4804 if (shift_opnum != 0
4805 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4807 rtx shifted_operand;
4810 /* Get the shifted operand. */
4811 extract_insn (insn);
4812 shifted_operand = recog_data.operand[shift_opnum];
4814 /* Iterate over all the operands in DEP. If we write an operand
4815 that overlaps with SHIFTED_OPERAND, then we have increase the
4816 cost of this dependency. */
4818 preprocess_constraints ();
4819 for (opno = 0; opno < recog_data.n_operands; opno++)
4821 /* We can ignore strict inputs. */
4822 if (recog_data.operand_type[opno] == OP_IN)
4825 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4832 /* XXX This is not strictly true for the FPA. */
4833 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4834 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4837 /* Call insns don't incur a stall, even if they follow a load. */
4838 if (REG_NOTE_KIND (link) == 0
4839 && GET_CODE (insn) == CALL_INSN)
4842 if ((i_pat = single_set (insn)) != NULL
4843 && GET_CODE (SET_SRC (i_pat)) == MEM
4844 && (d_pat = single_set (dep)) != NULL
4845 && GET_CODE (SET_DEST (d_pat)) == MEM)
4847 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4848 /* This is a load after a store, there is no conflict if the load reads
4849 from a cached area. Assume that loads from the stack, and from the
4850 constant pool are cached, and that others will miss. This is a
4853 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4854 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4855 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4856 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4863 static int fp_consts_inited = 0;
4865 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4866 static const char * const strings_fp[8] =
4869 "4", "5", "0.5", "10"
4872 static REAL_VALUE_TYPE values_fp[8];
4875 init_fp_table (void)
4881 fp_consts_inited = 1;
4883 fp_consts_inited = 8;
4885 for (i = 0; i < fp_consts_inited; i++)
4887 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4892 /* Return TRUE if rtx X is a valid immediate FP constant. */
4894 arm_const_double_rtx (rtx x)
4899 if (!fp_consts_inited)
4902 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4903 if (REAL_VALUE_MINUS_ZERO (r))
4906 for (i = 0; i < fp_consts_inited; i++)
4907 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4913 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4915 neg_const_double_rtx_ok_for_fpa (rtx x)
4920 if (!fp_consts_inited)
4923 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4924 r = REAL_VALUE_NEGATE (r);
4925 if (REAL_VALUE_MINUS_ZERO (r))
4928 for (i = 0; i < 8; i++)
4929 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4935 /* Predicates for `match_operand' and `match_operator'. */
4937 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4939 cirrus_memory_offset (rtx op)
4941 /* Reject eliminable registers. */
4942 if (! (reload_in_progress || reload_completed)
4943 && ( reg_mentioned_p (frame_pointer_rtx, op)
4944 || reg_mentioned_p (arg_pointer_rtx, op)
4945 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4946 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4947 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4948 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4951 if (GET_CODE (op) == MEM)
4957 /* Match: (mem (reg)). */
4958 if (GET_CODE (ind) == REG)
4964 if (GET_CODE (ind) == PLUS
4965 && GET_CODE (XEXP (ind, 0)) == REG
4966 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4967 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4974 /* Return TRUE if OP is a valid coprocessor memory address pattern.
4975 WB if true if writeback address modes are allowed. */
4978 arm_coproc_mem_operand (rtx op, bool wb)
4982 /* Reject eliminable registers. */
4983 if (! (reload_in_progress || reload_completed)
4984 && ( reg_mentioned_p (frame_pointer_rtx, op)
4985 || reg_mentioned_p (arg_pointer_rtx, op)
4986 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4987 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4988 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4989 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4992 /* Constants are converted into offsets from labels. */
4993 if (GET_CODE (op) != MEM)
4998 if (reload_completed
4999 && (GET_CODE (ind) == LABEL_REF
5000 || (GET_CODE (ind) == CONST
5001 && GET_CODE (XEXP (ind, 0)) == PLUS
5002 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5003 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5006 /* Match: (mem (reg)). */
5007 if (GET_CODE (ind) == REG)
5008 return arm_address_register_rtx_p (ind, 0);
5010 /* Autoincremment addressing modes. */
5012 && (GET_CODE (ind) == PRE_INC
5013 || GET_CODE (ind) == POST_INC
5014 || GET_CODE (ind) == PRE_DEC
5015 || GET_CODE (ind) == POST_DEC))
5016 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5019 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5020 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5021 && GET_CODE (XEXP (ind, 1)) == PLUS
5022 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5023 ind = XEXP (ind, 1);
5028 if (GET_CODE (ind) == PLUS
5029 && GET_CODE (XEXP (ind, 0)) == REG
5030 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5031 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5032 && INTVAL (XEXP (ind, 1)) > -1024
5033 && INTVAL (XEXP (ind, 1)) < 1024
5034 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5040 /* Return true if X is a register that will be eliminated later on. */
5042 arm_eliminable_register (rtx x)
5044 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5045 || REGNO (x) == ARG_POINTER_REGNUM
5046 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5047 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5050 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5051 VFP registers. Otherwise return NO_REGS. */
5054 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
5056 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
5059 return GENERAL_REGS;
5062 /* Values which must be returned in the most-significant end of the return
5066 arm_return_in_msb (tree valtype)
5068 return (TARGET_AAPCS_BASED
5070 && (AGGREGATE_TYPE_P (valtype)
5071 || TREE_CODE (valtype) == COMPLEX_TYPE));
5074 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5075 Use by the Cirrus Maverick code which has to workaround
5076 a hardware bug triggered by such instructions. */
5078 arm_memory_load_p (rtx insn)
5080 rtx body, lhs, rhs;;
5082 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5085 body = PATTERN (insn);
5087 if (GET_CODE (body) != SET)
5090 lhs = XEXP (body, 0);
5091 rhs = XEXP (body, 1);
5093 lhs = REG_OR_SUBREG_RTX (lhs);
5095 /* If the destination is not a general purpose
5096 register we do not have to worry. */
5097 if (GET_CODE (lhs) != REG
5098 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5101 /* As well as loads from memory we also have to react
5102 to loads of invalid constants which will be turned
5103 into loads from the minipool. */
5104 return (GET_CODE (rhs) == MEM
5105 || GET_CODE (rhs) == SYMBOL_REF
5106 || note_invalid_constants (insn, -1, false));
5109 /* Return TRUE if INSN is a Cirrus instruction. */
5111 arm_cirrus_insn_p (rtx insn)
5113 enum attr_cirrus attr;
5115 /* get_attr cannot accept USE or CLOBBER. */
5117 || GET_CODE (insn) != INSN
5118 || GET_CODE (PATTERN (insn)) == USE
5119 || GET_CODE (PATTERN (insn)) == CLOBBER)
5122 attr = get_attr_cirrus (insn);
5124 return attr != CIRRUS_NOT;
5127 /* Cirrus reorg for invalid instruction combinations. */
5129 cirrus_reorg (rtx first)
5131 enum attr_cirrus attr;
5132 rtx body = PATTERN (first);
5136 /* Any branch must be followed by 2 non Cirrus instructions. */
5137 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5140 t = next_nonnote_insn (first);
5142 if (arm_cirrus_insn_p (t))
5145 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5149 emit_insn_after (gen_nop (), first);
5154 /* (float (blah)) is in parallel with a clobber. */
5155 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5156 body = XVECEXP (body, 0, 0);
5158 if (GET_CODE (body) == SET)
5160 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5162 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5163 be followed by a non Cirrus insn. */
5164 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5166 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5167 emit_insn_after (gen_nop (), first);
5171 else if (arm_memory_load_p (first))
5173 unsigned int arm_regno;
5175 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5176 ldr/cfmv64hr combination where the Rd field is the same
5177 in both instructions must be split with a non Cirrus
5184 /* Get Arm register number for ldr insn. */
5185 if (GET_CODE (lhs) == REG)
5186 arm_regno = REGNO (lhs);
5189 gcc_assert (GET_CODE (rhs) == REG);
5190 arm_regno = REGNO (rhs);
5194 first = next_nonnote_insn (first);
5196 if (! arm_cirrus_insn_p (first))
5199 body = PATTERN (first);
5201 /* (float (blah)) is in parallel with a clobber. */
5202 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5203 body = XVECEXP (body, 0, 0);
5205 if (GET_CODE (body) == FLOAT)
5206 body = XEXP (body, 0);
5208 if (get_attr_cirrus (first) == CIRRUS_MOVE
5209 && GET_CODE (XEXP (body, 1)) == REG
5210 && arm_regno == REGNO (XEXP (body, 1)))
5211 emit_insn_after (gen_nop (), first);
5217 /* get_attr cannot accept USE or CLOBBER. */
5219 || GET_CODE (first) != INSN
5220 || GET_CODE (PATTERN (first)) == USE
5221 || GET_CODE (PATTERN (first)) == CLOBBER)
5224 attr = get_attr_cirrus (first);
5226 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5227 must be followed by a non-coprocessor instruction. */
5228 if (attr == CIRRUS_COMPARE)
5232 t = next_nonnote_insn (first);
5234 if (arm_cirrus_insn_p (t))
5237 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5241 emit_insn_after (gen_nop (), first);
5247 /* Return TRUE if X references a SYMBOL_REF. */
5249 symbol_mentioned_p (rtx x)
5254 if (GET_CODE (x) == SYMBOL_REF)
5257 fmt = GET_RTX_FORMAT (GET_CODE (x));
5259 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5265 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5266 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5269 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5276 /* Return TRUE if X references a LABEL_REF. */
5278 label_mentioned_p (rtx x)
5283 if (GET_CODE (x) == LABEL_REF)
5286 fmt = GET_RTX_FORMAT (GET_CODE (x));
5287 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5293 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5294 if (label_mentioned_p (XVECEXP (x, i, j)))
5297 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5307 enum rtx_code code = GET_CODE (x);
5324 /* Return 1 if memory locations are adjacent. */
5326 adjacent_mem_locations (rtx a, rtx b)
5328 /* We don't guarantee to preserve the order of these memory refs. */
5329 if (volatile_refs_p (a) || volatile_refs_p (b))
5332 if ((GET_CODE (XEXP (a, 0)) == REG
5333 || (GET_CODE (XEXP (a, 0)) == PLUS
5334 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5335 && (GET_CODE (XEXP (b, 0)) == REG
5336 || (GET_CODE (XEXP (b, 0)) == PLUS
5337 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5339 HOST_WIDE_INT val0 = 0, val1 = 0;
5343 if (GET_CODE (XEXP (a, 0)) == PLUS)
5345 reg0 = XEXP (XEXP (a, 0), 0);
5346 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5351 if (GET_CODE (XEXP (b, 0)) == PLUS)
5353 reg1 = XEXP (XEXP (b, 0), 0);
5354 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5359 /* Don't accept any offset that will require multiple
5360 instructions to handle, since this would cause the
5361 arith_adjacentmem pattern to output an overlong sequence. */
5362 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5365 /* Don't allow an eliminable register: register elimination can make
5366 the offset too large. */
5367 if (arm_eliminable_register (reg0))
5370 val_diff = val1 - val0;
5374 /* If the target has load delay slots, then there's no benefit
5375 to using an ldm instruction unless the offset is zero and
5376 we are optimizing for size. */
5377 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
5378 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
5379 && (val_diff == 4 || val_diff == -4));
5382 return ((REGNO (reg0) == REGNO (reg1))
5383 && (val_diff == 4 || val_diff == -4));
5390 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5391 HOST_WIDE_INT *load_offset)
5393 int unsorted_regs[4];
5394 HOST_WIDE_INT unsorted_offsets[4];
5399 /* Can only handle 2, 3, or 4 insns at present,
5400 though could be easily extended if required. */
5401 gcc_assert (nops >= 2 && nops <= 4);
5403 /* Loop over the operands and check that the memory references are
5404 suitable (i.e. immediate offsets from the same base register). At
5405 the same time, extract the target register, and the memory
5407 for (i = 0; i < nops; i++)
5412 /* Convert a subreg of a mem into the mem itself. */
5413 if (GET_CODE (operands[nops + i]) == SUBREG)
5414 operands[nops + i] = alter_subreg (operands + (nops + i));
5416 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5418 /* Don't reorder volatile memory references; it doesn't seem worth
5419 looking for the case where the order is ok anyway. */
5420 if (MEM_VOLATILE_P (operands[nops + i]))
5423 offset = const0_rtx;
5425 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5426 || (GET_CODE (reg) == SUBREG
5427 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5428 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5429 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5431 || (GET_CODE (reg) == SUBREG
5432 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5433 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5438 base_reg = REGNO (reg);
5439 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5440 ? REGNO (operands[i])
5441 : REGNO (SUBREG_REG (operands[i])));
5446 if (base_reg != (int) REGNO (reg))
5447 /* Not addressed from the same base register. */
5450 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5451 ? REGNO (operands[i])
5452 : REGNO (SUBREG_REG (operands[i])));
5453 if (unsorted_regs[i] < unsorted_regs[order[0]])
5457 /* If it isn't an integer register, or if it overwrites the
5458 base register but isn't the last insn in the list, then
5459 we can't do this. */
5460 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5461 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5464 unsorted_offsets[i] = INTVAL (offset);
5467 /* Not a suitable memory address. */
5471 /* All the useful information has now been extracted from the
5472 operands into unsorted_regs and unsorted_offsets; additionally,
5473 order[0] has been set to the lowest numbered register in the
5474 list. Sort the registers into order, and check that the memory
5475 offsets are ascending and adjacent. */
5477 for (i = 1; i < nops; i++)
5481 order[i] = order[i - 1];
5482 for (j = 0; j < nops; j++)
5483 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5484 && (order[i] == order[i - 1]
5485 || unsorted_regs[j] < unsorted_regs[order[i]]))
5488 /* Have we found a suitable register? if not, one must be used more
5490 if (order[i] == order[i - 1])
5493 /* Is the memory address adjacent and ascending? */
5494 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5502 for (i = 0; i < nops; i++)
5503 regs[i] = unsorted_regs[order[i]];
5505 *load_offset = unsorted_offsets[order[0]];
5508 if (unsorted_offsets[order[0]] == 0)
5509 return 1; /* ldmia */
5511 if (unsorted_offsets[order[0]] == 4)
5512 return 2; /* ldmib */
5514 if (unsorted_offsets[order[nops - 1]] == 0)
5515 return 3; /* ldmda */
5517 if (unsorted_offsets[order[nops - 1]] == -4)
5518 return 4; /* ldmdb */
5520 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5521 if the offset isn't small enough. The reason 2 ldrs are faster
5522 is because these ARMs are able to do more than one cache access
5523 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5524 whilst the ARM8 has a double bandwidth cache. This means that
5525 these cores can do both an instruction fetch and a data fetch in
5526 a single cycle, so the trick of calculating the address into a
5527 scratch register (one of the result regs) and then doing a load
5528 multiple actually becomes slower (and no smaller in code size).
5529 That is the transformation
5531 ldr rd1, [rbase + offset]
5532 ldr rd2, [rbase + offset + 4]
5536 add rd1, rbase, offset
5537 ldmia rd1, {rd1, rd2}
5539 produces worse code -- '3 cycles + any stalls on rd2' instead of
5540 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5541 access per cycle, the first sequence could never complete in less
5542 than 6 cycles, whereas the ldm sequence would only take 5 and
5543 would make better use of sequential accesses if not hitting the
5546 We cheat here and test 'arm_ld_sched' which we currently know to
5547 only be true for the ARM8, ARM9 and StrongARM. If this ever
5548 changes, then the test below needs to be reworked. */
5549 if (nops == 2 && arm_ld_sched)
5552 /* Can't do it without setting up the offset, only do this if it takes
5553 no more than one insn. */
5554 return (const_ok_for_arm (unsorted_offsets[order[0]])
5555 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5559 emit_ldm_seq (rtx *operands, int nops)
5563 HOST_WIDE_INT offset;
5567 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5570 strcpy (buf, "ldm%?ia\t");
5574 strcpy (buf, "ldm%?ib\t");
5578 strcpy (buf, "ldm%?da\t");
5582 strcpy (buf, "ldm%?db\t");
5587 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5588 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5591 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5592 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5594 output_asm_insn (buf, operands);
5596 strcpy (buf, "ldm%?ia\t");
5603 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5604 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5606 for (i = 1; i < nops; i++)
5607 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5608 reg_names[regs[i]]);
5610 strcat (buf, "}\t%@ phole ldm");
5612 output_asm_insn (buf, operands);
5617 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5618 HOST_WIDE_INT * load_offset)
5620 int unsorted_regs[4];
5621 HOST_WIDE_INT unsorted_offsets[4];
5626 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5627 extended if required. */
5628 gcc_assert (nops >= 2 && nops <= 4);
5630 /* Loop over the operands and check that the memory references are
5631 suitable (i.e. immediate offsets from the same base register). At
5632 the same time, extract the target register, and the memory
5634 for (i = 0; i < nops; i++)
5639 /* Convert a subreg of a mem into the mem itself. */
5640 if (GET_CODE (operands[nops + i]) == SUBREG)
5641 operands[nops + i] = alter_subreg (operands + (nops + i));
5643 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5645 /* Don't reorder volatile memory references; it doesn't seem worth
5646 looking for the case where the order is ok anyway. */
5647 if (MEM_VOLATILE_P (operands[nops + i]))
5650 offset = const0_rtx;
5652 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5653 || (GET_CODE (reg) == SUBREG
5654 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5655 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5656 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5658 || (GET_CODE (reg) == SUBREG
5659 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5660 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5665 base_reg = REGNO (reg);
5666 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5667 ? REGNO (operands[i])
5668 : REGNO (SUBREG_REG (operands[i])));
5673 if (base_reg != (int) REGNO (reg))
5674 /* Not addressed from the same base register. */
5677 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5678 ? REGNO (operands[i])
5679 : REGNO (SUBREG_REG (operands[i])));
5680 if (unsorted_regs[i] < unsorted_regs[order[0]])
5684 /* If it isn't an integer register, then we can't do this. */
5685 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5688 unsorted_offsets[i] = INTVAL (offset);
5691 /* Not a suitable memory address. */
5695 /* All the useful information has now been extracted from the
5696 operands into unsorted_regs and unsorted_offsets; additionally,
5697 order[0] has been set to the lowest numbered register in the
5698 list. Sort the registers into order, and check that the memory
5699 offsets are ascending and adjacent. */
5701 for (i = 1; i < nops; i++)
5705 order[i] = order[i - 1];
5706 for (j = 0; j < nops; j++)
5707 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5708 && (order[i] == order[i - 1]
5709 || unsorted_regs[j] < unsorted_regs[order[i]]))
5712 /* Have we found a suitable register? if not, one must be used more
5714 if (order[i] == order[i - 1])
5717 /* Is the memory address adjacent and ascending? */
5718 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5726 for (i = 0; i < nops; i++)
5727 regs[i] = unsorted_regs[order[i]];
5729 *load_offset = unsorted_offsets[order[0]];
5732 if (unsorted_offsets[order[0]] == 0)
5733 return 1; /* stmia */
5735 if (unsorted_offsets[order[0]] == 4)
5736 return 2; /* stmib */
5738 if (unsorted_offsets[order[nops - 1]] == 0)
5739 return 3; /* stmda */
5741 if (unsorted_offsets[order[nops - 1]] == -4)
5742 return 4; /* stmdb */
5748 emit_stm_seq (rtx *operands, int nops)
5752 HOST_WIDE_INT offset;
5756 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5759 strcpy (buf, "stm%?ia\t");
5763 strcpy (buf, "stm%?ib\t");
5767 strcpy (buf, "stm%?da\t");
5771 strcpy (buf, "stm%?db\t");
5778 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5779 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5781 for (i = 1; i < nops; i++)
5782 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5783 reg_names[regs[i]]);
5785 strcat (buf, "}\t%@ phole stm");
5787 output_asm_insn (buf, operands);
5792 /* Routines for use in generating RTL. */
5795 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5796 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5798 HOST_WIDE_INT offset = *offsetp;
5801 int sign = up ? 1 : -1;
5804 /* XScale has load-store double instructions, but they have stricter
5805 alignment requirements than load-store multiple, so we cannot
5808 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5809 the pipeline until completion.
5817 An ldr instruction takes 1-3 cycles, but does not block the
5826 Best case ldr will always win. However, the more ldr instructions
5827 we issue, the less likely we are to be able to schedule them well.
5828 Using ldr instructions also increases code size.
5830 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5831 for counts of 3 or 4 regs. */
5832 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5838 for (i = 0; i < count; i++)
5840 addr = plus_constant (from, i * 4 * sign);
5841 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5842 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5848 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5858 result = gen_rtx_PARALLEL (VOIDmode,
5859 rtvec_alloc (count + (write_back ? 1 : 0)));
5862 XVECEXP (result, 0, 0)
5863 = gen_rtx_SET (GET_MODE (from), from,
5864 plus_constant (from, count * 4 * sign));
5869 for (j = 0; i < count; i++, j++)
5871 addr = plus_constant (from, j * 4 * sign);
5872 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5873 XVECEXP (result, 0, i)
5874 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5885 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5886 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5888 HOST_WIDE_INT offset = *offsetp;
5891 int sign = up ? 1 : -1;
5894 /* See arm_gen_load_multiple for discussion of
5895 the pros/cons of ldm/stm usage for XScale. */
5896 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5902 for (i = 0; i < count; i++)
5904 addr = plus_constant (to, i * 4 * sign);
5905 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5906 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5912 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5922 result = gen_rtx_PARALLEL (VOIDmode,
5923 rtvec_alloc (count + (write_back ? 1 : 0)));
5926 XVECEXP (result, 0, 0)
5927 = gen_rtx_SET (GET_MODE (to), to,
5928 plus_constant (to, count * 4 * sign));
5933 for (j = 0; i < count; i++, j++)
5935 addr = plus_constant (to, j * 4 * sign);
5936 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5937 XVECEXP (result, 0, i)
5938 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5949 arm_gen_movmemqi (rtx *operands)
5951 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5952 HOST_WIDE_INT srcoffset, dstoffset;
5954 rtx src, dst, srcbase, dstbase;
5955 rtx part_bytes_reg = NULL;
5958 if (GET_CODE (operands[2]) != CONST_INT
5959 || GET_CODE (operands[3]) != CONST_INT
5960 || INTVAL (operands[2]) > 64
5961 || INTVAL (operands[3]) & 3)
5964 dstbase = operands[0];
5965 srcbase = operands[1];
5967 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5968 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5970 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5971 out_words_to_go = INTVAL (operands[2]) / 4;
5972 last_bytes = INTVAL (operands[2]) & 3;
5973 dstoffset = srcoffset = 0;
5975 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5976 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5978 for (i = 0; in_words_to_go >= 2; i+=4)
5980 if (in_words_to_go > 4)
5981 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5982 srcbase, &srcoffset));
5984 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5985 FALSE, srcbase, &srcoffset));
5987 if (out_words_to_go)
5989 if (out_words_to_go > 4)
5990 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5991 dstbase, &dstoffset));
5992 else if (out_words_to_go != 1)
5993 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5997 dstbase, &dstoffset));
6000 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6001 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6002 if (last_bytes != 0)
6004 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6010 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6011 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6014 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6015 if (out_words_to_go)
6019 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6020 sreg = copy_to_reg (mem);
6022 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6023 emit_move_insn (mem, sreg);
6026 gcc_assert (!in_words_to_go); /* Sanity check */
6031 gcc_assert (in_words_to_go > 0);
6033 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6034 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6037 gcc_assert (!last_bytes || part_bytes_reg);
6039 if (BYTES_BIG_ENDIAN && last_bytes)
6041 rtx tmp = gen_reg_rtx (SImode);
6043 /* The bytes we want are in the top end of the word. */
6044 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6045 GEN_INT (8 * (4 - last_bytes))));
6046 part_bytes_reg = tmp;
6050 mem = adjust_automodify_address (dstbase, QImode,
6051 plus_constant (dst, last_bytes - 1),
6052 dstoffset + last_bytes - 1);
6053 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6057 tmp = gen_reg_rtx (SImode);
6058 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6059 part_bytes_reg = tmp;
6068 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6069 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6073 rtx tmp = gen_reg_rtx (SImode);
6074 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6075 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6076 part_bytes_reg = tmp;
6083 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6084 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6091 /* Generate a memory reference for a half word, such that it will be loaded
6092 into the top 16 bits of the word. We can assume that the address is
6093 known to be alignable and of the form reg, or plus (reg, const). */
6096 arm_gen_rotated_half_load (rtx memref)
6098 HOST_WIDE_INT offset = 0;
6099 rtx base = XEXP (memref, 0);
6101 if (GET_CODE (base) == PLUS)
6103 offset = INTVAL (XEXP (base, 1));
6104 base = XEXP (base, 0);
6107 /* If we aren't allowed to generate unaligned addresses, then fail. */
6108 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6111 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6113 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6116 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6119 /* Select a dominance comparison mode if possible for a test of the general
6120 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6121 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6122 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6123 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6124 In all cases OP will be either EQ or NE, but we don't need to know which
6125 here. If we are unable to support a dominance comparison we return
6126 CC mode. This will then fail to match for the RTL expressions that
6127 generate this call. */
6129 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6131 enum rtx_code cond1, cond2;
6134 /* Currently we will probably get the wrong result if the individual
6135 comparisons are not simple. This also ensures that it is safe to
6136 reverse a comparison if necessary. */
6137 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6139 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6143 /* The if_then_else variant of this tests the second condition if the
6144 first passes, but is true if the first fails. Reverse the first
6145 condition to get a true "inclusive-or" expression. */
6146 if (cond_or == DOM_CC_NX_OR_Y)
6147 cond1 = reverse_condition (cond1);
6149 /* If the comparisons are not equal, and one doesn't dominate the other,
6150 then we can't do this. */
6152 && !comparison_dominates_p (cond1, cond2)
6153 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6158 enum rtx_code temp = cond1;
6166 if (cond_or == DOM_CC_X_AND_Y)
6171 case EQ: return CC_DEQmode;
6172 case LE: return CC_DLEmode;
6173 case LEU: return CC_DLEUmode;
6174 case GE: return CC_DGEmode;
6175 case GEU: return CC_DGEUmode;
6176 default: gcc_unreachable ();
6180 if (cond_or == DOM_CC_X_AND_Y)
6196 if (cond_or == DOM_CC_X_AND_Y)
6212 if (cond_or == DOM_CC_X_AND_Y)
6228 if (cond_or == DOM_CC_X_AND_Y)
6243 /* The remaining cases only occur when both comparisons are the
6246 gcc_assert (cond1 == cond2);
6250 gcc_assert (cond1 == cond2);
6254 gcc_assert (cond1 == cond2);
6258 gcc_assert (cond1 == cond2);
6262 gcc_assert (cond1 == cond2);
6271 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6273 /* All floating point compares return CCFP if it is an equality
6274 comparison, and CCFPE otherwise. */
6275 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6295 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6304 /* A compare with a shifted operand. Because of canonicalization, the
6305 comparison will have to be swapped when we emit the assembler. */
6306 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6307 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6308 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6309 || GET_CODE (x) == ROTATERT))
6312 /* This operation is performed swapped, but since we only rely on the Z
6313 flag we don't need an additional mode. */
6314 if (GET_MODE (y) == SImode && REG_P (y)
6315 && GET_CODE (x) == NEG
6316 && (op == EQ || op == NE))
6319 /* This is a special case that is used by combine to allow a
6320 comparison of a shifted byte load to be split into a zero-extend
6321 followed by a comparison of the shifted integer (only valid for
6322 equalities and unsigned inequalities). */
6323 if (GET_MODE (x) == SImode
6324 && GET_CODE (x) == ASHIFT
6325 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6326 && GET_CODE (XEXP (x, 0)) == SUBREG
6327 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6328 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6329 && (op == EQ || op == NE
6330 || op == GEU || op == GTU || op == LTU || op == LEU)
6331 && GET_CODE (y) == CONST_INT)
6334 /* A construct for a conditional compare, if the false arm contains
6335 0, then both conditions must be true, otherwise either condition
6336 must be true. Not all conditions are possible, so CCmode is
6337 returned if it can't be done. */
6338 if (GET_CODE (x) == IF_THEN_ELSE
6339 && (XEXP (x, 2) == const0_rtx
6340 || XEXP (x, 2) == const1_rtx)
6341 && COMPARISON_P (XEXP (x, 0))
6342 && COMPARISON_P (XEXP (x, 1)))
6343 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6344 INTVAL (XEXP (x, 2)));
6346 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6347 if (GET_CODE (x) == AND
6348 && COMPARISON_P (XEXP (x, 0))
6349 && COMPARISON_P (XEXP (x, 1)))
6350 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6353 if (GET_CODE (x) == IOR
6354 && COMPARISON_P (XEXP (x, 0))
6355 && COMPARISON_P (XEXP (x, 1)))
6356 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6359 /* An operation (on Thumb) where we want to test for a single bit.
6360 This is done by shifting that bit up into the top bit of a
6361 scratch register; we can then branch on the sign bit. */
6363 && GET_MODE (x) == SImode
6364 && (op == EQ || op == NE)
6365 && (GET_CODE (x) == ZERO_EXTRACT))
6368 /* An operation that sets the condition codes as a side-effect, the
6369 V flag is not set correctly, so we can only use comparisons where
6370 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6372 if (GET_MODE (x) == SImode
6374 && (op == EQ || op == NE || op == LT || op == GE)
6375 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6376 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6377 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6378 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6379 || GET_CODE (x) == LSHIFTRT
6380 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6381 || GET_CODE (x) == ROTATERT
6382 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6385 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6388 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6389 && GET_CODE (x) == PLUS
6390 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6396 /* X and Y are two things to compare using CODE. Emit the compare insn and
6397 return the rtx for register 0 in the proper mode. FP means this is a
6398 floating point compare: I don't think that it is needed on the arm. */
6400 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6402 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6403 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6405 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6406 gen_rtx_COMPARE (mode, x, y)));
6411 /* Generate a sequence of insns that will generate the correct return
6412 address mask depending on the physical architecture that the program
6415 arm_gen_return_addr_mask (void)
6417 rtx reg = gen_reg_rtx (Pmode);
6419 emit_insn (gen_return_addr_mask (reg));
6424 arm_reload_in_hi (rtx *operands)
6426 rtx ref = operands[1];
6428 HOST_WIDE_INT offset = 0;
6430 if (GET_CODE (ref) == SUBREG)
6432 offset = SUBREG_BYTE (ref);
6433 ref = SUBREG_REG (ref);
6436 if (GET_CODE (ref) == REG)
6438 /* We have a pseudo which has been spilt onto the stack; there
6439 are two cases here: the first where there is a simple
6440 stack-slot replacement and a second where the stack-slot is
6441 out of range, or is used as a subreg. */
6442 if (reg_equiv_mem[REGNO (ref)])
6444 ref = reg_equiv_mem[REGNO (ref)];
6445 base = find_replacement (&XEXP (ref, 0));
6448 /* The slot is out of range, or was dressed up in a SUBREG. */
6449 base = reg_equiv_address[REGNO (ref)];
6452 base = find_replacement (&XEXP (ref, 0));
6454 /* Handle the case where the address is too complex to be offset by 1. */
6455 if (GET_CODE (base) == MINUS
6456 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6458 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6460 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6463 else if (GET_CODE (base) == PLUS)
6465 /* The addend must be CONST_INT, or we would have dealt with it above. */
6466 HOST_WIDE_INT hi, lo;
6468 offset += INTVAL (XEXP (base, 1));
6469 base = XEXP (base, 0);
6471 /* Rework the address into a legal sequence of insns. */
6472 /* Valid range for lo is -4095 -> 4095 */
6475 : -((-offset) & 0xfff));
6477 /* Corner case, if lo is the max offset then we would be out of range
6478 once we have added the additional 1 below, so bump the msb into the
6479 pre-loading insn(s). */
6483 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6484 ^ (HOST_WIDE_INT) 0x80000000)
6485 - (HOST_WIDE_INT) 0x80000000);
6487 gcc_assert (hi + lo == offset);
6491 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6493 /* Get the base address; addsi3 knows how to handle constants
6494 that require more than one insn. */
6495 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6501 /* Operands[2] may overlap operands[0] (though it won't overlap
6502 operands[1]), that's why we asked for a DImode reg -- so we can
6503 use the bit that does not overlap. */
6504 if (REGNO (operands[2]) == REGNO (operands[0]))
6505 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6507 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6509 emit_insn (gen_zero_extendqisi2 (scratch,
6510 gen_rtx_MEM (QImode,
6511 plus_constant (base,
6513 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6514 gen_rtx_MEM (QImode,
6515 plus_constant (base,
6517 if (!BYTES_BIG_ENDIAN)
6518 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6519 gen_rtx_IOR (SImode,
6522 gen_rtx_SUBREG (SImode, operands[0], 0),
6526 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6527 gen_rtx_IOR (SImode,
6528 gen_rtx_ASHIFT (SImode, scratch,
6530 gen_rtx_SUBREG (SImode, operands[0],
6534 /* Handle storing a half-word to memory during reload by synthesizing as two
6535 byte stores. Take care not to clobber the input values until after we
6536 have moved them somewhere safe. This code assumes that if the DImode
6537 scratch in operands[2] overlaps either the input value or output address
6538 in some way, then that value must die in this insn (we absolutely need
6539 two scratch registers for some corner cases). */
6541 arm_reload_out_hi (rtx *operands)
6543 rtx ref = operands[0];
6544 rtx outval = operands[1];
6546 HOST_WIDE_INT offset = 0;
6548 if (GET_CODE (ref) == SUBREG)
6550 offset = SUBREG_BYTE (ref);
6551 ref = SUBREG_REG (ref);
6554 if (GET_CODE (ref) == REG)
6556 /* We have a pseudo which has been spilt onto the stack; there
6557 are two cases here: the first where there is a simple
6558 stack-slot replacement and a second where the stack-slot is
6559 out of range, or is used as a subreg. */
6560 if (reg_equiv_mem[REGNO (ref)])
6562 ref = reg_equiv_mem[REGNO (ref)];
6563 base = find_replacement (&XEXP (ref, 0));
6566 /* The slot is out of range, or was dressed up in a SUBREG. */
6567 base = reg_equiv_address[REGNO (ref)];
6570 base = find_replacement (&XEXP (ref, 0));
6572 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6574 /* Handle the case where the address is too complex to be offset by 1. */
6575 if (GET_CODE (base) == MINUS
6576 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6578 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6580 /* Be careful not to destroy OUTVAL. */
6581 if (reg_overlap_mentioned_p (base_plus, outval))
6583 /* Updating base_plus might destroy outval, see if we can
6584 swap the scratch and base_plus. */
6585 if (!reg_overlap_mentioned_p (scratch, outval))
6588 scratch = base_plus;
6593 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6595 /* Be conservative and copy OUTVAL into the scratch now,
6596 this should only be necessary if outval is a subreg
6597 of something larger than a word. */
6598 /* XXX Might this clobber base? I can't see how it can,
6599 since scratch is known to overlap with OUTVAL, and
6600 must be wider than a word. */
6601 emit_insn (gen_movhi (scratch_hi, outval));
6602 outval = scratch_hi;
6606 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6609 else if (GET_CODE (base) == PLUS)
6611 /* The addend must be CONST_INT, or we would have dealt with it above. */
6612 HOST_WIDE_INT hi, lo;
6614 offset += INTVAL (XEXP (base, 1));
6615 base = XEXP (base, 0);
6617 /* Rework the address into a legal sequence of insns. */
6618 /* Valid range for lo is -4095 -> 4095 */
6621 : -((-offset) & 0xfff));
6623 /* Corner case, if lo is the max offset then we would be out of range
6624 once we have added the additional 1 below, so bump the msb into the
6625 pre-loading insn(s). */
6629 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6630 ^ (HOST_WIDE_INT) 0x80000000)
6631 - (HOST_WIDE_INT) 0x80000000);
6633 gcc_assert (hi + lo == offset);
6637 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6639 /* Be careful not to destroy OUTVAL. */
6640 if (reg_overlap_mentioned_p (base_plus, outval))
6642 /* Updating base_plus might destroy outval, see if we
6643 can swap the scratch and base_plus. */
6644 if (!reg_overlap_mentioned_p (scratch, outval))
6647 scratch = base_plus;
6652 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6654 /* Be conservative and copy outval into scratch now,
6655 this should only be necessary if outval is a
6656 subreg of something larger than a word. */
6657 /* XXX Might this clobber base? I can't see how it
6658 can, since scratch is known to overlap with
6660 emit_insn (gen_movhi (scratch_hi, outval));
6661 outval = scratch_hi;
6665 /* Get the base address; addsi3 knows how to handle constants
6666 that require more than one insn. */
6667 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6673 if (BYTES_BIG_ENDIAN)
6675 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6676 plus_constant (base, offset + 1)),
6677 gen_lowpart (QImode, outval)));
6678 emit_insn (gen_lshrsi3 (scratch,
6679 gen_rtx_SUBREG (SImode, outval, 0),
6681 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6682 gen_lowpart (QImode, scratch)));
6686 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6687 gen_lowpart (QImode, outval)));
6688 emit_insn (gen_lshrsi3 (scratch,
6689 gen_rtx_SUBREG (SImode, outval, 0),
6691 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6692 plus_constant (base, offset + 1)),
6693 gen_lowpart (QImode, scratch)));
6697 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
6698 (padded to the size of a word) should be passed in a register. */
6701 arm_must_pass_in_stack (enum machine_mode mode, tree type)
6703 if (TARGET_AAPCS_BASED)
6704 return must_pass_in_stack_var_size (mode, type);
6706 return must_pass_in_stack_var_size_or_pad (mode, type);
6710 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
6711 Return true if an argument passed on the stack should be padded upwards,
6712 i.e. if the least-significant byte has useful data.
6713 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
6714 aggregate types are placed in the lowest memory address. */
6717 arm_pad_arg_upward (enum machine_mode mode, tree type)
6719 if (!TARGET_AAPCS_BASED)
6720 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
6722 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
6729 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6730 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
6731 byte of the register has useful data, and return the opposite if the
6732 most significant byte does.
6733 For AAPCS, small aggregates and small complex types are always padded
6737 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
6738 tree type, int first ATTRIBUTE_UNUSED)
6740 if (TARGET_AAPCS_BASED
6742 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
6743 && int_size_in_bytes (type) <= 4)
6746 /* Otherwise, use default padding. */
6747 return !BYTES_BIG_ENDIAN;
6752 /* Print a symbolic form of X to the debug file, F. */
6754 arm_print_value (FILE *f, rtx x)
6756 switch (GET_CODE (x))
6759 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6763 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6771 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6773 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6774 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6782 fprintf (f, "\"%s\"", XSTR (x, 0));
6786 fprintf (f, "`%s'", XSTR (x, 0));
6790 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6794 arm_print_value (f, XEXP (x, 0));
6798 arm_print_value (f, XEXP (x, 0));
6800 arm_print_value (f, XEXP (x, 1));
6808 fprintf (f, "????");
6813 /* Routines for manipulation of the constant pool. */
6815 /* Arm instructions cannot load a large constant directly into a
6816 register; they have to come from a pc relative load. The constant
6817 must therefore be placed in the addressable range of the pc
6818 relative load. Depending on the precise pc relative load
6819 instruction the range is somewhere between 256 bytes and 4k. This
6820 means that we often have to dump a constant inside a function, and
6821 generate code to branch around it.
6823 It is important to minimize this, since the branches will slow
6824 things down and make the code larger.
6826 Normally we can hide the table after an existing unconditional
6827 branch so that there is no interruption of the flow, but in the
6828 worst case the code looks like this:
6846 We fix this by performing a scan after scheduling, which notices
6847 which instructions need to have their operands fetched from the
6848 constant table and builds the table.
6850 The algorithm starts by building a table of all the constants that
6851 need fixing up and all the natural barriers in the function (places
6852 where a constant table can be dropped without breaking the flow).
6853 For each fixup we note how far the pc-relative replacement will be
6854 able to reach and the offset of the instruction into the function.
6856 Having built the table we then group the fixes together to form
6857 tables that are as large as possible (subject to addressing
6858 constraints) and emit each table of constants after the last
6859 barrier that is within range of all the instructions in the group.
6860 If a group does not contain a barrier, then we forcibly create one
6861 by inserting a jump instruction into the flow. Once the table has
6862 been inserted, the insns are then modified to reference the
6863 relevant entry in the pool.
6865 Possible enhancements to the algorithm (not implemented) are:
6867 1) For some processors and object formats, there may be benefit in
6868 aligning the pools to the start of cache lines; this alignment
6869 would need to be taken into account when calculating addressability
6872 /* These typedefs are located at the start of this file, so that
6873 they can be used in the prototypes there. This comment is to
6874 remind readers of that fact so that the following structures
6875 can be understood more easily.
6877 typedef struct minipool_node Mnode;
6878 typedef struct minipool_fixup Mfix; */
6880 struct minipool_node
6882 /* Doubly linked chain of entries. */
6885 /* The maximum offset into the code that this entry can be placed. While
6886 pushing fixes for forward references, all entries are sorted in order
6887 of increasing max_address. */
6888 HOST_WIDE_INT max_address;
6889 /* Similarly for an entry inserted for a backwards ref. */
6890 HOST_WIDE_INT min_address;
6891 /* The number of fixes referencing this entry. This can become zero
6892 if we "unpush" an entry. In this case we ignore the entry when we
6893 come to emit the code. */
6895 /* The offset from the start of the minipool. */
6896 HOST_WIDE_INT offset;
6897 /* The value in table. */
6899 /* The mode of value. */
6900 enum machine_mode mode;
6901 /* The size of the value. With iWMMXt enabled
6902 sizes > 4 also imply an alignment of 8-bytes. */
6906 struct minipool_fixup
6910 HOST_WIDE_INT address;
6912 enum machine_mode mode;
6916 HOST_WIDE_INT forwards;
6917 HOST_WIDE_INT backwards;
6920 /* Fixes less than a word need padding out to a word boundary. */
6921 #define MINIPOOL_FIX_SIZE(mode) \
6922 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6924 static Mnode * minipool_vector_head;
6925 static Mnode * minipool_vector_tail;
6926 static rtx minipool_vector_label;
6928 /* The linked list of all minipool fixes required for this function. */
6929 Mfix * minipool_fix_head;
6930 Mfix * minipool_fix_tail;
6931 /* The fix entry for the current minipool, once it has been placed. */
6932 Mfix * minipool_barrier;
6934 /* Determines if INSN is the start of a jump table. Returns the end
6935 of the TABLE or NULL_RTX. */
6937 is_jump_table (rtx insn)
6941 if (GET_CODE (insn) == JUMP_INSN
6942 && JUMP_LABEL (insn) != NULL
6943 && ((table = next_real_insn (JUMP_LABEL (insn)))
6944 == next_real_insn (insn))
6946 && GET_CODE (table) == JUMP_INSN
6947 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6948 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6954 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6955 #define JUMP_TABLES_IN_TEXT_SECTION 0
6958 static HOST_WIDE_INT
6959 get_jump_table_size (rtx insn)
6961 /* ADDR_VECs only take room if read-only data does into the text
6963 if (JUMP_TABLES_IN_TEXT_SECTION
6964 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6969 rtx body = PATTERN (insn);
6970 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6972 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6978 /* Move a minipool fix MP from its current location to before MAX_MP.
6979 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6980 constraints may need updating. */
6982 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6983 HOST_WIDE_INT max_address)
6985 /* The code below assumes these are different. */
6986 gcc_assert (mp != max_mp);
6990 if (max_address < mp->max_address)
6991 mp->max_address = max_address;
6995 if (max_address > max_mp->max_address - mp->fix_size)
6996 mp->max_address = max_mp->max_address - mp->fix_size;
6998 mp->max_address = max_address;
7000 /* Unlink MP from its current position. Since max_mp is non-null,
7001 mp->prev must be non-null. */
7002 mp->prev->next = mp->next;
7003 if (mp->next != NULL)
7004 mp->next->prev = mp->prev;
7006 minipool_vector_tail = mp->prev;
7008 /* Re-insert it before MAX_MP. */
7010 mp->prev = max_mp->prev;
7013 if (mp->prev != NULL)
7014 mp->prev->next = mp;
7016 minipool_vector_head = mp;
7019 /* Save the new entry. */
7022 /* Scan over the preceding entries and adjust their addresses as
7024 while (mp->prev != NULL
7025 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7027 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7034 /* Add a constant to the minipool for a forward reference. Returns the
7035 node added or NULL if the constant will not fit in this pool. */
7037 add_minipool_forward_ref (Mfix *fix)
7039 /* If set, max_mp is the first pool_entry that has a lower
7040 constraint than the one we are trying to add. */
7041 Mnode * max_mp = NULL;
7042 HOST_WIDE_INT max_address = fix->address + fix->forwards;
7045 /* If this fix's address is greater than the address of the first
7046 entry, then we can't put the fix in this pool. We subtract the
7047 size of the current fix to ensure that if the table is fully
7048 packed we still have enough room to insert this value by shuffling
7049 the other fixes forwards. */
7050 if (minipool_vector_head &&
7051 fix->address >= minipool_vector_head->max_address - fix->fix_size)
7054 /* Scan the pool to see if a constant with the same value has
7055 already been added. While we are doing this, also note the
7056 location where we must insert the constant if it doesn't already
7058 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7060 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7061 && fix->mode == mp->mode
7062 && (GET_CODE (fix->value) != CODE_LABEL
7063 || (CODE_LABEL_NUMBER (fix->value)
7064 == CODE_LABEL_NUMBER (mp->value)))
7065 && rtx_equal_p (fix->value, mp->value))
7067 /* More than one fix references this entry. */
7069 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7072 /* Note the insertion point if necessary. */
7074 && mp->max_address > max_address)
7077 /* If we are inserting an 8-bytes aligned quantity and
7078 we have not already found an insertion point, then
7079 make sure that all such 8-byte aligned quantities are
7080 placed at the start of the pool. */
7081 if (ARM_DOUBLEWORD_ALIGN
7083 && fix->fix_size == 8
7084 && mp->fix_size != 8)
7087 max_address = mp->max_address;
7091 /* The value is not currently in the minipool, so we need to create
7092 a new entry for it. If MAX_MP is NULL, the entry will be put on
7093 the end of the list since the placement is less constrained than
7094 any existing entry. Otherwise, we insert the new fix before
7095 MAX_MP and, if necessary, adjust the constraints on the other
7097 mp = xmalloc (sizeof (* mp));
7098 mp->fix_size = fix->fix_size;
7099 mp->mode = fix->mode;
7100 mp->value = fix->value;
7102 /* Not yet required for a backwards ref. */
7103 mp->min_address = -65536;
7107 mp->max_address = max_address;
7109 mp->prev = minipool_vector_tail;
7111 if (mp->prev == NULL)
7113 minipool_vector_head = mp;
7114 minipool_vector_label = gen_label_rtx ();
7117 mp->prev->next = mp;
7119 minipool_vector_tail = mp;
7123 if (max_address > max_mp->max_address - mp->fix_size)
7124 mp->max_address = max_mp->max_address - mp->fix_size;
7126 mp->max_address = max_address;
7129 mp->prev = max_mp->prev;
7131 if (mp->prev != NULL)
7132 mp->prev->next = mp;
7134 minipool_vector_head = mp;
7137 /* Save the new entry. */
7140 /* Scan over the preceding entries and adjust their addresses as
7142 while (mp->prev != NULL
7143 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7145 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7153 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7154 HOST_WIDE_INT min_address)
7156 HOST_WIDE_INT offset;
7158 /* The code below assumes these are different. */
7159 gcc_assert (mp != min_mp);
7163 if (min_address > mp->min_address)
7164 mp->min_address = min_address;
7168 /* We will adjust this below if it is too loose. */
7169 mp->min_address = min_address;
7171 /* Unlink MP from its current position. Since min_mp is non-null,
7172 mp->next must be non-null. */
7173 mp->next->prev = mp->prev;
7174 if (mp->prev != NULL)
7175 mp->prev->next = mp->next;
7177 minipool_vector_head = mp->next;
7179 /* Reinsert it after MIN_MP. */
7181 mp->next = min_mp->next;
7183 if (mp->next != NULL)
7184 mp->next->prev = mp;
7186 minipool_vector_tail = mp;
7192 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7194 mp->offset = offset;
7195 if (mp->refcount > 0)
7196 offset += mp->fix_size;
7198 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7199 mp->next->min_address = mp->min_address + mp->fix_size;
7205 /* Add a constant to the minipool for a backward reference. Returns the
7206 node added or NULL if the constant will not fit in this pool.
7208 Note that the code for insertion for a backwards reference can be
7209 somewhat confusing because the calculated offsets for each fix do
7210 not take into account the size of the pool (which is still under
7213 add_minipool_backward_ref (Mfix *fix)
7215 /* If set, min_mp is the last pool_entry that has a lower constraint
7216 than the one we are trying to add. */
7217 Mnode *min_mp = NULL;
7218 /* This can be negative, since it is only a constraint. */
7219 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7222 /* If we can't reach the current pool from this insn, or if we can't
7223 insert this entry at the end of the pool without pushing other
7224 fixes out of range, then we don't try. This ensures that we
7225 can't fail later on. */
7226 if (min_address >= minipool_barrier->address
7227 || (minipool_vector_tail->min_address + fix->fix_size
7228 >= minipool_barrier->address))
7231 /* Scan the pool to see if a constant with the same value has
7232 already been added. While we are doing this, also note the
7233 location where we must insert the constant if it doesn't already
7235 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7237 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7238 && fix->mode == mp->mode
7239 && (GET_CODE (fix->value) != CODE_LABEL
7240 || (CODE_LABEL_NUMBER (fix->value)
7241 == CODE_LABEL_NUMBER (mp->value)))
7242 && rtx_equal_p (fix->value, mp->value)
7243 /* Check that there is enough slack to move this entry to the
7244 end of the table (this is conservative). */
7246 > (minipool_barrier->address
7247 + minipool_vector_tail->offset
7248 + minipool_vector_tail->fix_size)))
7251 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7255 mp->min_address += fix->fix_size;
7258 /* Note the insertion point if necessary. */
7259 if (mp->min_address < min_address)
7261 /* For now, we do not allow the insertion of 8-byte alignment
7262 requiring nodes anywhere but at the start of the pool. */
7263 if (ARM_DOUBLEWORD_ALIGN
7264 && fix->fix_size == 8 && mp->fix_size != 8)
7269 else if (mp->max_address
7270 < minipool_barrier->address + mp->offset + fix->fix_size)
7272 /* Inserting before this entry would push the fix beyond
7273 its maximum address (which can happen if we have
7274 re-located a forwards fix); force the new fix to come
7277 min_address = mp->min_address + fix->fix_size;
7279 /* If we are inserting an 8-bytes aligned quantity and
7280 we have not already found an insertion point, then
7281 make sure that all such 8-byte aligned quantities are
7282 placed at the start of the pool. */
7283 else if (ARM_DOUBLEWORD_ALIGN
7285 && fix->fix_size == 8
7286 && mp->fix_size < 8)
7289 min_address = mp->min_address + fix->fix_size;
7294 /* We need to create a new entry. */
7295 mp = xmalloc (sizeof (* mp));
7296 mp->fix_size = fix->fix_size;
7297 mp->mode = fix->mode;
7298 mp->value = fix->value;
7300 mp->max_address = minipool_barrier->address + 65536;
7302 mp->min_address = min_address;
7307 mp->next = minipool_vector_head;
7309 if (mp->next == NULL)
7311 minipool_vector_tail = mp;
7312 minipool_vector_label = gen_label_rtx ();
7315 mp->next->prev = mp;
7317 minipool_vector_head = mp;
7321 mp->next = min_mp->next;
7325 if (mp->next != NULL)
7326 mp->next->prev = mp;
7328 minipool_vector_tail = mp;
7331 /* Save the new entry. */
7339 /* Scan over the following entries and adjust their offsets. */
7340 while (mp->next != NULL)
7342 if (mp->next->min_address < mp->min_address + mp->fix_size)
7343 mp->next->min_address = mp->min_address + mp->fix_size;
7346 mp->next->offset = mp->offset + mp->fix_size;
7348 mp->next->offset = mp->offset;
7357 assign_minipool_offsets (Mfix *barrier)
7359 HOST_WIDE_INT offset = 0;
7362 minipool_barrier = barrier;
7364 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7366 mp->offset = offset;
7368 if (mp->refcount > 0)
7369 offset += mp->fix_size;
7373 /* Output the literal table */
7375 dump_minipool (rtx scan)
7381 if (ARM_DOUBLEWORD_ALIGN)
7382 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7383 if (mp->refcount > 0 && mp->fix_size == 8)
7391 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7392 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7394 scan = emit_label_after (gen_label_rtx (), scan);
7395 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7396 scan = emit_label_after (minipool_vector_label, scan);
7398 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7400 if (mp->refcount > 0)
7405 ";; Offset %u, min %ld, max %ld ",
7406 (unsigned) mp->offset, (unsigned long) mp->min_address,
7407 (unsigned long) mp->max_address);
7408 arm_print_value (dump_file, mp->value);
7409 fputc ('\n', dump_file);
7412 switch (mp->fix_size)
7414 #ifdef HAVE_consttable_1
7416 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7420 #ifdef HAVE_consttable_2
7422 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7426 #ifdef HAVE_consttable_4
7428 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7432 #ifdef HAVE_consttable_8
7434 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7447 minipool_vector_head = minipool_vector_tail = NULL;
7448 scan = emit_insn_after (gen_consttable_end (), scan);
7449 scan = emit_barrier_after (scan);
7452 /* Return the cost of forcibly inserting a barrier after INSN. */
7454 arm_barrier_cost (rtx insn)
7456 /* Basing the location of the pool on the loop depth is preferable,
7457 but at the moment, the basic block information seems to be
7458 corrupt by this stage of the compilation. */
7460 rtx next = next_nonnote_insn (insn);
7462 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7465 switch (GET_CODE (insn))
7468 /* It will always be better to place the table before the label, rather
7477 return base_cost - 10;
7480 return base_cost + 10;
7484 /* Find the best place in the insn stream in the range
7485 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7486 Create the barrier by inserting a jump and add a new fix entry for
7489 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7491 HOST_WIDE_INT count = 0;
7493 rtx from = fix->insn;
7494 rtx selected = from;
7496 HOST_WIDE_INT selected_address;
7498 HOST_WIDE_INT max_count = max_address - fix->address;
7499 rtx label = gen_label_rtx ();
7501 selected_cost = arm_barrier_cost (from);
7502 selected_address = fix->address;
7504 while (from && count < max_count)
7509 /* This code shouldn't have been called if there was a natural barrier
7511 gcc_assert (GET_CODE (from) != BARRIER);
7513 /* Count the length of this insn. */
7514 count += get_attr_length (from);
7516 /* If there is a jump table, add its length. */
7517 tmp = is_jump_table (from);
7520 count += get_jump_table_size (tmp);
7522 /* Jump tables aren't in a basic block, so base the cost on
7523 the dispatch insn. If we select this location, we will
7524 still put the pool after the table. */
7525 new_cost = arm_barrier_cost (from);
7527 if (count < max_count && new_cost <= selected_cost)
7530 selected_cost = new_cost;
7531 selected_address = fix->address + count;
7534 /* Continue after the dispatch table. */
7535 from = NEXT_INSN (tmp);
7539 new_cost = arm_barrier_cost (from);
7541 if (count < max_count && new_cost <= selected_cost)
7544 selected_cost = new_cost;
7545 selected_address = fix->address + count;
7548 from = NEXT_INSN (from);
7551 /* Create a new JUMP_INSN that branches around a barrier. */
7552 from = emit_jump_insn_after (gen_jump (label), selected);
7553 JUMP_LABEL (from) = label;
7554 barrier = emit_barrier_after (from);
7555 emit_label_after (label, barrier);
7557 /* Create a minipool barrier entry for the new barrier. */
7558 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7559 new_fix->insn = barrier;
7560 new_fix->address = selected_address;
7561 new_fix->next = fix->next;
7562 fix->next = new_fix;
7567 /* Record that there is a natural barrier in the insn stream at
7570 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7572 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7575 fix->address = address;
7578 if (minipool_fix_head != NULL)
7579 minipool_fix_tail->next = fix;
7581 minipool_fix_head = fix;
7583 minipool_fix_tail = fix;
7586 /* Record INSN, which will need fixing up to load a value from the
7587 minipool. ADDRESS is the offset of the insn since the start of the
7588 function; LOC is a pointer to the part of the insn which requires
7589 fixing; VALUE is the constant that must be loaded, which is of type
7592 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7593 enum machine_mode mode, rtx value)
7595 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7597 #ifdef AOF_ASSEMBLER
7598 /* PIC symbol references need to be converted into offsets into the
7600 /* XXX This shouldn't be done here. */
7601 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7602 value = aof_pic_entry (value);
7603 #endif /* AOF_ASSEMBLER */
7606 fix->address = address;
7609 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7611 fix->forwards = get_attr_pool_range (insn);
7612 fix->backwards = get_attr_neg_pool_range (insn);
7613 fix->minipool = NULL;
7615 /* If an insn doesn't have a range defined for it, then it isn't
7616 expecting to be reworked by this code. Better to stop now than
7617 to generate duff assembly code. */
7618 gcc_assert (fix->forwards || fix->backwards);
7620 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7621 So there might be an empty word before the start of the pool.
7622 Hence we reduce the forward range by 4 to allow for this
7624 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7630 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7631 GET_MODE_NAME (mode),
7632 INSN_UID (insn), (unsigned long) address,
7633 -1 * (long)fix->backwards, (long)fix->forwards);
7634 arm_print_value (dump_file, fix->value);
7635 fprintf (dump_file, "\n");
7638 /* Add it to the chain of fixes. */
7641 if (minipool_fix_head != NULL)
7642 minipool_fix_tail->next = fix;
7644 minipool_fix_head = fix;
7646 minipool_fix_tail = fix;
7649 /* Return the cost of synthesizing a 64-bit constant VAL inline.
7650 Returns the number of insns needed, or 99 if we don't know how to
7653 arm_const_double_inline_cost (rtx val)
7655 rtx lowpart, highpart;
7656 enum machine_mode mode;
7658 mode = GET_MODE (val);
7660 if (mode == VOIDmode)
7663 gcc_assert (GET_MODE_SIZE (mode) == 8);
7665 lowpart = gen_lowpart (SImode, val);
7666 highpart = gen_highpart_mode (SImode, mode, val);
7668 gcc_assert (GET_CODE (lowpart) == CONST_INT);
7669 gcc_assert (GET_CODE (highpart) == CONST_INT);
7671 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
7672 NULL_RTX, NULL_RTX, 0, 0)
7673 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
7674 NULL_RTX, NULL_RTX, 0, 0));
7677 /* Return true if it is worthwhile to split a 64-bit constant into two
7678 32-bit operations. This is the case if optimizing for size, or
7679 if we have load delay slots, or if one 32-bit part can be done with
7680 a single data operation. */
7682 arm_const_double_by_parts (rtx val)
7684 enum machine_mode mode = GET_MODE (val);
7687 if (optimize_size || arm_ld_sched)
7690 if (mode == VOIDmode)
7693 part = gen_highpart_mode (SImode, mode, val);
7695 gcc_assert (GET_CODE (part) == CONST_INT);
7697 if (const_ok_for_arm (INTVAL (part))
7698 || const_ok_for_arm (~INTVAL (part)))
7701 part = gen_lowpart (SImode, val);
7703 gcc_assert (GET_CODE (part) == CONST_INT);
7705 if (const_ok_for_arm (INTVAL (part))
7706 || const_ok_for_arm (~INTVAL (part)))
7712 /* Scan INSN and note any of its operands that need fixing.
7713 If DO_PUSHES is false we do not actually push any of the fixups
7714 needed. The function returns TRUE if any fixups were needed/pushed.
7715 This is used by arm_memory_load_p() which needs to know about loads
7716 of constants that will be converted into minipool loads. */
7718 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7720 bool result = false;
7723 extract_insn (insn);
7725 if (!constrain_operands (1))
7726 fatal_insn_not_found (insn);
7728 if (recog_data.n_alternatives == 0)
7731 /* Fill in recog_op_alt with information about the constraints of
7733 preprocess_constraints ();
7735 for (opno = 0; opno < recog_data.n_operands; opno++)
7737 /* Things we need to fix can only occur in inputs. */
7738 if (recog_data.operand_type[opno] != OP_IN)
7741 /* If this alternative is a memory reference, then any mention
7742 of constants in this alternative is really to fool reload
7743 into allowing us to accept one there. We need to fix them up
7744 now so that we output the right code. */
7745 if (recog_op_alt[opno][which_alternative].memory_ok)
7747 rtx op = recog_data.operand[opno];
7749 if (CONSTANT_P (op))
7752 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7753 recog_data.operand_mode[opno], op);
7756 else if (GET_CODE (op) == MEM
7757 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7758 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7762 rtx cop = avoid_constant_pool_reference (op);
7764 /* Casting the address of something to a mode narrower
7765 than a word can cause avoid_constant_pool_reference()
7766 to return the pool reference itself. That's no good to
7767 us here. Lets just hope that we can use the
7768 constant pool value directly. */
7770 cop = get_pool_constant (XEXP (op, 0));
7772 push_minipool_fix (insn, address,
7773 recog_data.operand_loc[opno],
7774 recog_data.operand_mode[opno], cop);
7785 /* Gcc puts the pool in the wrong place for ARM, since we can only
7786 load addresses a limited distance around the pc. We do some
7787 special munging to move the constant pool values to the correct
7788 point in the code. */
7793 HOST_WIDE_INT address = 0;
7796 minipool_fix_head = minipool_fix_tail = NULL;
7798 /* The first insn must always be a note, or the code below won't
7799 scan it properly. */
7800 insn = get_insns ();
7801 gcc_assert (GET_CODE (insn) == NOTE);
7803 /* Scan all the insns and record the operands that will need fixing. */
7804 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7806 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7807 && (arm_cirrus_insn_p (insn)
7808 || GET_CODE (insn) == JUMP_INSN
7809 || arm_memory_load_p (insn)))
7810 cirrus_reorg (insn);
7812 if (GET_CODE (insn) == BARRIER)
7813 push_minipool_barrier (insn, address);
7814 else if (INSN_P (insn))
7818 note_invalid_constants (insn, address, true);
7819 address += get_attr_length (insn);
7821 /* If the insn is a vector jump, add the size of the table
7822 and skip the table. */
7823 if ((table = is_jump_table (insn)) != NULL)
7825 address += get_jump_table_size (table);
7831 fix = minipool_fix_head;
7833 /* Now scan the fixups and perform the required changes. */
7838 Mfix * last_added_fix;
7839 Mfix * last_barrier = NULL;
7842 /* Skip any further barriers before the next fix. */
7843 while (fix && GET_CODE (fix->insn) == BARRIER)
7846 /* No more fixes. */
7850 last_added_fix = NULL;
7852 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7854 if (GET_CODE (ftmp->insn) == BARRIER)
7856 if (ftmp->address >= minipool_vector_head->max_address)
7859 last_barrier = ftmp;
7861 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7864 last_added_fix = ftmp; /* Keep track of the last fix added. */
7867 /* If we found a barrier, drop back to that; any fixes that we
7868 could have reached but come after the barrier will now go in
7869 the next mini-pool. */
7870 if (last_barrier != NULL)
7872 /* Reduce the refcount for those fixes that won't go into this
7874 for (fdel = last_barrier->next;
7875 fdel && fdel != ftmp;
7878 fdel->minipool->refcount--;
7879 fdel->minipool = NULL;
7882 ftmp = last_barrier;
7886 /* ftmp is first fix that we can't fit into this pool and
7887 there no natural barriers that we could use. Insert a
7888 new barrier in the code somewhere between the previous
7889 fix and this one, and arrange to jump around it. */
7890 HOST_WIDE_INT max_address;
7892 /* The last item on the list of fixes must be a barrier, so
7893 we can never run off the end of the list of fixes without
7894 last_barrier being set. */
7897 max_address = minipool_vector_head->max_address;
7898 /* Check that there isn't another fix that is in range that
7899 we couldn't fit into this pool because the pool was
7900 already too large: we need to put the pool before such an
7902 if (ftmp->address < max_address)
7903 max_address = ftmp->address;
7905 last_barrier = create_fix_barrier (last_added_fix, max_address);
7908 assign_minipool_offsets (last_barrier);
7912 if (GET_CODE (ftmp->insn) != BARRIER
7913 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7920 /* Scan over the fixes we have identified for this pool, fixing them
7921 up and adding the constants to the pool itself. */
7922 for (this_fix = fix; this_fix && ftmp != this_fix;
7923 this_fix = this_fix->next)
7924 if (GET_CODE (this_fix->insn) != BARRIER)
7927 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7928 minipool_vector_label),
7929 this_fix->minipool->offset);
7930 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7933 dump_minipool (last_barrier->insn);
7937 /* From now on we must synthesize any constants that we can't handle
7938 directly. This can happen if the RTL gets split during final
7939 instruction generation. */
7940 after_arm_reorg = 1;
7942 /* Free the minipool memory. */
7943 obstack_free (&minipool_obstack, minipool_startobj);
7946 /* Routines to output assembly language. */
7948 /* If the rtx is the correct value then return the string of the number.
7949 In this way we can ensure that valid double constants are generated even
7950 when cross compiling. */
7952 fp_immediate_constant (rtx x)
7957 if (!fp_consts_inited)
7960 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7961 for (i = 0; i < 8; i++)
7962 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7963 return strings_fp[i];
7968 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7970 fp_const_from_val (REAL_VALUE_TYPE *r)
7974 if (!fp_consts_inited)
7977 for (i = 0; i < 8; i++)
7978 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7979 return strings_fp[i];
7984 /* Output the operands of a LDM/STM instruction to STREAM.
7985 MASK is the ARM register set mask of which only bits 0-15 are important.
7986 REG is the base register, either the frame pointer or the stack pointer,
7987 INSTR is the possibly suffixed load or store instruction. */
7990 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
7994 bool not_first = FALSE;
7996 fputc ('\t', stream);
7997 asm_fprintf (stream, instr, reg);
7998 fputs (", {", stream);
8000 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8001 if (mask & (1 << i))
8004 fprintf (stream, ", ");
8006 asm_fprintf (stream, "%r", i);
8010 fprintf (stream, "}\n");
8014 /* Output a FLDMX instruction to STREAM.
8015 BASE if the register containing the address.
8016 REG and COUNT specify the register range.
8017 Extra registers may be added to avoid hardware bugs. */
8020 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8024 /* Workaround ARM10 VFPr1 bug. */
8025 if (count == 2 && !arm_arch6)
8032 fputc ('\t', stream);
8033 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8035 for (i = reg; i < reg + count; i++)
8038 fputs (", ", stream);
8039 asm_fprintf (stream, "d%d", i);
8041 fputs ("}\n", stream);
8046 /* Output the assembly for a store multiple. */
8049 vfp_output_fstmx (rtx * operands)
8056 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8057 p = strlen (pattern);
8059 gcc_assert (GET_CODE (operands[1]) == REG);
8061 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8062 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8064 p += sprintf (&pattern[p], ", d%d", base + i);
8066 strcpy (&pattern[p], "}");
8068 output_asm_insn (pattern, operands);
8073 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8074 number of bytes pushed. */
8077 vfp_emit_fstmx (int base_reg, int count)
8084 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8085 register pairs are stored by a store multiple insn. We avoid this
8086 by pushing an extra pair. */
8087 if (count == 2 && !arm_arch6)
8089 if (base_reg == LAST_VFP_REGNUM - 3)
8094 /* ??? The frame layout is implementation defined. We describe
8095 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8096 We really need some way of representing the whole block so that the
8097 unwinder can figure it out at runtime. */
8098 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8099 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8101 reg = gen_rtx_REG (DFmode, base_reg);
8105 = gen_rtx_SET (VOIDmode,
8106 gen_rtx_MEM (BLKmode,
8107 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8108 gen_rtx_UNSPEC (BLKmode,
8112 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8113 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8114 GEN_INT (-(count * 8 + 4))));
8115 RTX_FRAME_RELATED_P (tmp) = 1;
8116 XVECEXP (dwarf, 0, 0) = tmp;
8118 tmp = gen_rtx_SET (VOIDmode,
8119 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8121 RTX_FRAME_RELATED_P (tmp) = 1;
8122 XVECEXP (dwarf, 0, 1) = tmp;
8124 for (i = 1; i < count; i++)
8126 reg = gen_rtx_REG (DFmode, base_reg);
8128 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8130 tmp = gen_rtx_SET (VOIDmode,
8131 gen_rtx_MEM (DFmode,
8132 gen_rtx_PLUS (SImode,
8136 RTX_FRAME_RELATED_P (tmp) = 1;
8137 XVECEXP (dwarf, 0, i + 1) = tmp;
8140 par = emit_insn (par);
8141 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8143 RTX_FRAME_RELATED_P (par) = 1;
8145 return count * 8 + 4;
8149 /* Output a 'call' insn. */
8151 output_call (rtx *operands)
8153 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8155 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8156 if (REGNO (operands[0]) == LR_REGNUM)
8158 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8159 output_asm_insn ("mov%?\t%0, %|lr", operands);
8162 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8164 if (TARGET_INTERWORK || arm_arch4t)
8165 output_asm_insn ("bx%?\t%0", operands);
8167 output_asm_insn ("mov%?\t%|pc, %0", operands);
8172 /* Output a 'call' insn that is a reference in memory. */
8174 output_call_mem (rtx *operands)
8176 if (TARGET_INTERWORK && !arm_arch5)
8178 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8179 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8180 output_asm_insn ("bx%?\t%|ip", operands);
8182 else if (regno_use_in (LR_REGNUM, operands[0]))
8184 /* LR is used in the memory address. We load the address in the
8185 first instruction. It's safe to use IP as the target of the
8186 load since the call will kill it anyway. */
8187 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8189 output_asm_insn ("blx%?\t%|ip", operands);
8192 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8194 output_asm_insn ("bx%?\t%|ip", operands);
8196 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8201 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8202 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8209 /* Output a move from arm registers to an fpa registers.
8210 OPERANDS[0] is an fpa register.
8211 OPERANDS[1] is the first registers of an arm register pair. */
8213 output_mov_long_double_fpa_from_arm (rtx *operands)
8215 int arm_reg0 = REGNO (operands[1]);
8218 gcc_assert (arm_reg0 != IP_REGNUM);
8220 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8221 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8222 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8224 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8225 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8230 /* Output a move from an fpa register to arm registers.
8231 OPERANDS[0] is the first registers of an arm register pair.
8232 OPERANDS[1] is an fpa register. */
8234 output_mov_long_double_arm_from_fpa (rtx *operands)
8236 int arm_reg0 = REGNO (operands[0]);
8239 gcc_assert (arm_reg0 != IP_REGNUM);
8241 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8242 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8243 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8245 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8246 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8250 /* Output a move from arm registers to arm registers of a long double
8251 OPERANDS[0] is the destination.
8252 OPERANDS[1] is the source. */
8254 output_mov_long_double_arm_from_arm (rtx *operands)
8256 /* We have to be careful here because the two might overlap. */
8257 int dest_start = REGNO (operands[0]);
8258 int src_start = REGNO (operands[1]);
8262 if (dest_start < src_start)
8264 for (i = 0; i < 3; i++)
8266 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8267 ops[1] = gen_rtx_REG (SImode, src_start + i);
8268 output_asm_insn ("mov%?\t%0, %1", ops);
8273 for (i = 2; i >= 0; i--)
8275 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8276 ops[1] = gen_rtx_REG (SImode, src_start + i);
8277 output_asm_insn ("mov%?\t%0, %1", ops);
8285 /* Output a move from arm registers to an fpa registers.
8286 OPERANDS[0] is an fpa register.
8287 OPERANDS[1] is the first registers of an arm register pair. */
8289 output_mov_double_fpa_from_arm (rtx *operands)
8291 int arm_reg0 = REGNO (operands[1]);
8294 gcc_assert (arm_reg0 != IP_REGNUM);
8296 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8297 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8298 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8299 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8303 /* Output a move from an fpa register to arm registers.
8304 OPERANDS[0] is the first registers of an arm register pair.
8305 OPERANDS[1] is an fpa register. */
8307 output_mov_double_arm_from_fpa (rtx *operands)
8309 int arm_reg0 = REGNO (operands[0]);
8312 gcc_assert (arm_reg0 != IP_REGNUM);
8314 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8315 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8316 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8317 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8321 /* Output a move between double words.
8322 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8323 or MEM<-REG and all MEMs must be offsettable addresses. */
8325 output_move_double (rtx *operands)
8327 enum rtx_code code0 = GET_CODE (operands[0]);
8328 enum rtx_code code1 = GET_CODE (operands[1]);
8333 int reg0 = REGNO (operands[0]);
8335 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8337 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
8339 switch (GET_CODE (XEXP (operands[1], 0)))
8342 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8346 gcc_assert (TARGET_LDRD);
8347 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8351 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8355 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8359 gcc_assert (TARGET_LDRD);
8360 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8365 otherops[0] = operands[0];
8366 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8367 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8369 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8371 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8373 /* Registers overlap so split out the increment. */
8374 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8375 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8378 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8382 /* We only allow constant increments, so this is safe. */
8383 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8389 output_asm_insn ("adr%?\t%0, %1", operands);
8390 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8394 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8395 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8397 otherops[0] = operands[0];
8398 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8399 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8401 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8403 if (GET_CODE (otherops[2]) == CONST_INT)
8405 switch ((int) INTVAL (otherops[2]))
8408 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8411 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8414 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8419 && (GET_CODE (otherops[2]) == REG
8420 || (GET_CODE (otherops[2]) == CONST_INT
8421 && INTVAL (otherops[2]) > -256
8422 && INTVAL (otherops[2]) < 256)))
8424 if (reg_overlap_mentioned_p (otherops[0],
8427 /* Swap base and index registers over to
8428 avoid a conflict. */
8429 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8430 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8433 /* If both registers conflict, it will usually
8434 have been fixed by a splitter. */
8435 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8437 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8438 output_asm_insn ("ldr%?d\t%0, [%1]",
8442 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
8446 if (GET_CODE (otherops[2]) == CONST_INT)
8448 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8449 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8451 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8454 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8457 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8459 return "ldm%?ia\t%0, %M0";
8463 otherops[1] = adjust_address (operands[1], SImode, 4);
8464 /* Take care of overlapping base/data reg. */
8465 if (reg_mentioned_p (operands[0], operands[1]))
8467 output_asm_insn ("ldr%?\t%0, %1", otherops);
8468 output_asm_insn ("ldr%?\t%0, %1", operands);
8472 output_asm_insn ("ldr%?\t%0, %1", operands);
8473 output_asm_insn ("ldr%?\t%0, %1", otherops);
8480 /* Constraints should ensure this. */
8481 gcc_assert (code0 == MEM && code1 == REG);
8482 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
8484 switch (GET_CODE (XEXP (operands[0], 0)))
8487 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8491 gcc_assert (TARGET_LDRD);
8492 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8496 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8500 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8504 gcc_assert (TARGET_LDRD);
8505 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8510 otherops[0] = operands[1];
8511 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8512 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8514 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8515 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8517 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8521 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8522 if (GET_CODE (otherops[2]) == CONST_INT)
8524 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8527 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8531 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8535 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8540 && (GET_CODE (otherops[2]) == REG
8541 || (GET_CODE (otherops[2]) == CONST_INT
8542 && INTVAL (otherops[2]) > -256
8543 && INTVAL (otherops[2]) < 256)))
8545 otherops[0] = operands[1];
8546 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8547 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8553 otherops[0] = adjust_address (operands[0], SImode, 4);
8554 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8555 output_asm_insn ("str%?\t%1, %0", operands);
8556 output_asm_insn ("str%?\t%1, %0", otherops);
8563 /* Output an ADD r, s, #n where n may be too big for one instruction.
8564 If adding zero to one register, output nothing. */
8566 output_add_immediate (rtx *operands)
8568 HOST_WIDE_INT n = INTVAL (operands[2]);
8570 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8573 output_multi_immediate (operands,
8574 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8577 output_multi_immediate (operands,
8578 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8585 /* Output a multiple immediate operation.
8586 OPERANDS is the vector of operands referred to in the output patterns.
8587 INSTR1 is the output pattern to use for the first constant.
8588 INSTR2 is the output pattern to use for subsequent constants.
8589 IMMED_OP is the index of the constant slot in OPERANDS.
8590 N is the constant value. */
8592 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8593 int immed_op, HOST_WIDE_INT n)
8595 #if HOST_BITS_PER_WIDE_INT > 32
8601 /* Quick and easy output. */
8602 operands[immed_op] = const0_rtx;
8603 output_asm_insn (instr1, operands);
8608 const char * instr = instr1;
8610 /* Note that n is never zero here (which would give no output). */
8611 for (i = 0; i < 32; i += 2)
8615 operands[immed_op] = GEN_INT (n & (255 << i));
8616 output_asm_insn (instr, operands);
8626 /* Return the appropriate ARM instruction for the operation code.
8627 The returned result should not be overwritten. OP is the rtx of the
8628 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8631 arithmetic_instr (rtx op, int shift_first_arg)
8633 switch (GET_CODE (op))
8639 return shift_first_arg ? "rsb" : "sub";
8655 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8656 for the operation code. The returned result should not be overwritten.
8657 OP is the rtx code of the shift.
8658 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8661 shift_op (rtx op, HOST_WIDE_INT *amountp)
8664 enum rtx_code code = GET_CODE (op);
8666 switch (GET_CODE (XEXP (op, 1)))
8674 *amountp = INTVAL (XEXP (op, 1));
8696 gcc_assert (*amountp != -1);
8697 *amountp = 32 - *amountp;
8706 /* We never have to worry about the amount being other than a
8707 power of 2, since this case can never be reloaded from a reg. */
8708 gcc_assert (*amountp != -1);
8709 *amountp = int_log2 (*amountp);
8718 /* This is not 100% correct, but follows from the desire to merge
8719 multiplication by a power of 2 with the recognizer for a
8720 shift. >=32 is not a valid shift for "asl", so we must try and
8721 output a shift that produces the correct arithmetical result.
8722 Using lsr #32 is identical except for the fact that the carry bit
8723 is not set correctly if we set the flags; but we never use the
8724 carry bit from such an operation, so we can ignore that. */
8725 if (code == ROTATERT)
8726 /* Rotate is just modulo 32. */
8728 else if (*amountp != (*amountp & 31))
8735 /* Shifts of 0 are no-ops. */
8743 /* Obtain the shift from the POWER of two. */
8745 static HOST_WIDE_INT
8746 int_log2 (HOST_WIDE_INT power)
8748 HOST_WIDE_INT shift = 0;
8750 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8752 gcc_assert (shift <= 31);
8759 /* Output a .ascii pseudo-op, keeping track of lengths. This is
8760 because /bin/as is horribly restrictive. The judgement about
8761 whether or not each character is 'printable' (and can be output as
8762 is) or not (and must be printed with an octal escape) must be made
8763 with reference to the *host* character set -- the situation is
8764 similar to that discussed in the comments above pp_c_char in
8765 c-pretty-print.c. */
8767 #define MAX_ASCII_LEN 51
8770 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8775 fputs ("\t.ascii\t\"", stream);
8777 for (i = 0; i < len; i++)
8781 if (len_so_far >= MAX_ASCII_LEN)
8783 fputs ("\"\n\t.ascii\t\"", stream);
8789 if (c == '\\' || c == '\"')
8791 putc ('\\', stream);
8799 fprintf (stream, "\\%03o", c);
8804 fputs ("\"\n", stream);
8807 /* Compute the register save mask for registers 0 through 12
8808 inclusive. This code is used by arm_compute_save_reg_mask. */
8810 static unsigned long
8811 arm_compute_save_reg0_reg12_mask (void)
8813 unsigned long func_type = arm_current_func_type ();
8814 unsigned long save_reg_mask = 0;
8817 if (IS_INTERRUPT (func_type))
8819 unsigned int max_reg;
8820 /* Interrupt functions must not corrupt any registers,
8821 even call clobbered ones. If this is a leaf function
8822 we can just examine the registers used by the RTL, but
8823 otherwise we have to assume that whatever function is
8824 called might clobber anything, and so we have to save
8825 all the call-clobbered registers as well. */
8826 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8827 /* FIQ handlers have registers r8 - r12 banked, so
8828 we only need to check r0 - r7, Normal ISRs only
8829 bank r14 and r15, so we must check up to r12.
8830 r13 is the stack pointer which is always preserved,
8831 so we do not need to consider it here. */
8836 for (reg = 0; reg <= max_reg; reg++)
8837 if (regs_ever_live[reg]
8838 || (! current_function_is_leaf && call_used_regs [reg]))
8839 save_reg_mask |= (1 << reg);
8841 /* Also save the pic base register if necessary. */
8843 && !TARGET_SINGLE_PIC_BASE
8844 && current_function_uses_pic_offset_table)
8845 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8849 /* In the normal case we only need to save those registers
8850 which are call saved and which are used by this function. */
8851 for (reg = 0; reg <= 10; reg++)
8852 if (regs_ever_live[reg] && ! call_used_regs [reg])
8853 save_reg_mask |= (1 << reg);
8855 /* Handle the frame pointer as a special case. */
8856 if (! TARGET_APCS_FRAME
8857 && ! frame_pointer_needed
8858 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8859 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8860 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8862 /* If we aren't loading the PIC register,
8863 don't stack it even though it may be live. */
8865 && !TARGET_SINGLE_PIC_BASE
8866 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
8867 || current_function_uses_pic_offset_table))
8868 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8871 /* Save registers so the exception handler can modify them. */
8872 if (current_function_calls_eh_return)
8878 reg = EH_RETURN_DATA_REGNO (i);
8879 if (reg == INVALID_REGNUM)
8881 save_reg_mask |= 1 << reg;
8885 return save_reg_mask;
8888 /* Compute a bit mask of which registers need to be
8889 saved on the stack for the current function. */
8891 static unsigned long
8892 arm_compute_save_reg_mask (void)
8894 unsigned int save_reg_mask = 0;
8895 unsigned long func_type = arm_current_func_type ();
8897 if (IS_NAKED (func_type))
8898 /* This should never really happen. */
8901 /* If we are creating a stack frame, then we must save the frame pointer,
8902 IP (which will hold the old stack pointer), LR and the PC. */
8903 if (frame_pointer_needed)
8905 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8910 /* Volatile functions do not return, so there
8911 is no need to save any other registers. */
8912 if (IS_VOLATILE (func_type))
8913 return save_reg_mask;
8915 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8917 /* Decide if we need to save the link register.
8918 Interrupt routines have their own banked link register,
8919 so they never need to save it.
8920 Otherwise if we do not use the link register we do not need to save
8921 it. If we are pushing other registers onto the stack however, we
8922 can save an instruction in the epilogue by pushing the link register
8923 now and then popping it back into the PC. This incurs extra memory
8924 accesses though, so we only do it when optimizing for size, and only
8925 if we know that we will not need a fancy return sequence. */
8926 if (regs_ever_live [LR_REGNUM]
8929 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8930 && !current_function_calls_eh_return))
8931 save_reg_mask |= 1 << LR_REGNUM;
8933 if (cfun->machine->lr_save_eliminated)
8934 save_reg_mask &= ~ (1 << LR_REGNUM);
8936 if (TARGET_REALLY_IWMMXT
8937 && ((bit_count (save_reg_mask)
8938 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8942 /* The total number of registers that are going to be pushed
8943 onto the stack is odd. We need to ensure that the stack
8944 is 64-bit aligned before we start to save iWMMXt registers,
8945 and also before we start to create locals. (A local variable
8946 might be a double or long long which we will load/store using
8947 an iWMMXt instruction). Therefore we need to push another
8948 ARM register, so that the stack will be 64-bit aligned. We
8949 try to avoid using the arg registers (r0 -r3) as they might be
8950 used to pass values in a tail call. */
8951 for (reg = 4; reg <= 12; reg++)
8952 if ((save_reg_mask & (1 << reg)) == 0)
8956 save_reg_mask |= (1 << reg);
8959 cfun->machine->sibcall_blocked = 1;
8960 save_reg_mask |= (1 << 3);
8964 return save_reg_mask;
8968 /* Compute a bit mask of which registers need to be
8969 saved on the stack for the current function. */
8970 static unsigned long
8971 thumb_compute_save_reg_mask (void)
8977 for (reg = 0; reg < 12; reg ++)
8978 if (regs_ever_live[reg] && !call_used_regs[reg])
8982 && !TARGET_SINGLE_PIC_BASE
8983 && current_function_uses_pic_offset_table)
8984 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8986 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8987 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
8988 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
8990 /* LR will also be pushed if any lo regs are pushed. */
8991 if (mask & 0xff || thumb_force_lr_save ())
8992 mask |= (1 << LR_REGNUM);
8994 /* Make sure we have a low work register if we need one.
8995 We will need one if we are going to push a high register,
8996 but we are not currently intending to push a low register. */
8997 if ((mask & 0xff) == 0
8998 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9000 /* Use thumb_find_work_register to choose which register
9001 we will use. If the register is live then we will
9002 have to push it. Use LAST_LO_REGNUM as our fallback
9003 choice for the register to select. */
9004 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9006 if (! call_used_regs[reg])
9014 /* Return the number of bytes required to save VFP registers. */
9016 arm_get_vfp_saved_size (void)
9023 /* Space for saved VFP registers. */
9024 if (TARGET_HARD_FLOAT && TARGET_VFP)
9027 for (regno = FIRST_VFP_REGNUM;
9028 regno < LAST_VFP_REGNUM;
9031 if ((!regs_ever_live[regno] || call_used_regs[regno])
9032 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9036 /* Workaround ARM10 VFPr1 bug. */
9037 if (count == 2 && !arm_arch6)
9039 saved += count * 8 + 4;
9048 if (count == 2 && !arm_arch6)
9050 saved += count * 8 + 4;
9057 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9058 everything bar the final return instruction. */
9060 output_return_instruction (rtx operand, int really_return, int reverse)
9062 char conditional[10];
9065 unsigned long live_regs_mask;
9066 unsigned long func_type;
9067 arm_stack_offsets *offsets;
9069 func_type = arm_current_func_type ();
9071 if (IS_NAKED (func_type))
9074 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9076 /* If this function was declared non-returning, and we have
9077 found a tail call, then we have to trust that the called
9078 function won't return. */
9083 /* Otherwise, trap an attempted return by aborting. */
9085 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9087 assemble_external_libcall (ops[1]);
9088 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9094 gcc_assert (!current_function_calls_alloca || really_return);
9096 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9098 return_used_this_function = 1;
9100 live_regs_mask = arm_compute_save_reg_mask ();
9104 const char * return_reg;
9106 /* If we do not have any special requirements for function exit
9107 (e.g. interworking, or ISR) then we can load the return address
9108 directly into the PC. Otherwise we must load it into LR. */
9110 && ! TARGET_INTERWORK)
9111 return_reg = reg_names[PC_REGNUM];
9113 return_reg = reg_names[LR_REGNUM];
9115 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9117 /* There are three possible reasons for the IP register
9118 being saved. 1) a stack frame was created, in which case
9119 IP contains the old stack pointer, or 2) an ISR routine
9120 corrupted it, or 3) it was saved to align the stack on
9121 iWMMXt. In case 1, restore IP into SP, otherwise just
9123 if (frame_pointer_needed)
9125 live_regs_mask &= ~ (1 << IP_REGNUM);
9126 live_regs_mask |= (1 << SP_REGNUM);
9129 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
9132 /* On some ARM architectures it is faster to use LDR rather than
9133 LDM to load a single register. On other architectures, the
9134 cost is the same. In 26 bit mode, or for exception handlers,
9135 we have to use LDM to load the PC so that the CPSR is also
9137 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9138 if (live_regs_mask == (1U << reg))
9141 if (reg <= LAST_ARM_REGNUM
9142 && (reg != LR_REGNUM
9144 || ! IS_INTERRUPT (func_type)))
9146 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9147 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9154 /* Generate the load multiple instruction to restore the
9155 registers. Note we can get here, even if
9156 frame_pointer_needed is true, but only if sp already
9157 points to the base of the saved core registers. */
9158 if (live_regs_mask & (1 << SP_REGNUM))
9160 unsigned HOST_WIDE_INT stack_adjust;
9162 offsets = arm_get_frame_offsets ();
9163 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9164 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
9166 if (stack_adjust && arm_arch5)
9167 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9170 /* If we can't use ldmib (SA110 bug),
9171 then try to pop r3 instead. */
9173 live_regs_mask |= 1 << 3;
9174 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9178 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9180 p = instr + strlen (instr);
9182 for (reg = 0; reg <= SP_REGNUM; reg++)
9183 if (live_regs_mask & (1 << reg))
9185 int l = strlen (reg_names[reg]);
9191 memcpy (p, ", ", 2);
9195 memcpy (p, "%|", 2);
9196 memcpy (p + 2, reg_names[reg], l);
9200 if (live_regs_mask & (1 << LR_REGNUM))
9202 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9203 /* If returning from an interrupt, restore the CPSR. */
9204 if (IS_INTERRUPT (func_type))
9211 output_asm_insn (instr, & operand);
9213 /* See if we need to generate an extra instruction to
9214 perform the actual function return. */
9216 && func_type != ARM_FT_INTERWORKED
9217 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9219 /* The return has already been handled
9220 by loading the LR into the PC. */
9227 switch ((int) ARM_FUNC_TYPE (func_type))
9231 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9234 case ARM_FT_INTERWORKED:
9235 sprintf (instr, "bx%s\t%%|lr", conditional);
9238 case ARM_FT_EXCEPTION:
9239 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9243 /* Use bx if it's available. */
9244 if (arm_arch5 || arm_arch4t)
9245 sprintf (instr, "bx%s\t%%|lr", conditional);
9247 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9251 output_asm_insn (instr, & operand);
9257 /* Write the function name into the code section, directly preceding
9258 the function prologue.
9260 Code will be output similar to this:
9262 .ascii "arm_poke_function_name", 0
9265 .word 0xff000000 + (t1 - t0)
9266 arm_poke_function_name
9268 stmfd sp!, {fp, ip, lr, pc}
9271 When performing a stack backtrace, code can inspect the value
9272 of 'pc' stored at 'fp' + 0. If the trace function then looks
9273 at location pc - 12 and the top 8 bits are set, then we know
9274 that there is a function name embedded immediately preceding this
9275 location and has length ((pc[-3]) & 0xff000000).
9277 We assume that pc is declared as a pointer to an unsigned long.
9279 It is of no benefit to output the function name if we are assembling
9280 a leaf function. These function types will not contain a stack
9281 backtrace structure, therefore it is not possible to determine the
9284 arm_poke_function_name (FILE *stream, const char *name)
9286 unsigned long alignlength;
9287 unsigned long length;
9290 length = strlen (name) + 1;
9291 alignlength = ROUND_UP_WORD (length);
9293 ASM_OUTPUT_ASCII (stream, name, length);
9294 ASM_OUTPUT_ALIGN (stream, 2);
9295 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9296 assemble_aligned_integer (UNITS_PER_WORD, x);
9299 /* Place some comments into the assembler stream
9300 describing the current function. */
9302 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9304 unsigned long func_type;
9308 thumb_output_function_prologue (f, frame_size);
9313 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9315 func_type = arm_current_func_type ();
9317 switch ((int) ARM_FUNC_TYPE (func_type))
9322 case ARM_FT_INTERWORKED:
9323 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9326 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9329 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9331 case ARM_FT_EXCEPTION:
9332 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9336 if (IS_NAKED (func_type))
9337 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9339 if (IS_VOLATILE (func_type))
9340 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9342 if (IS_NESTED (func_type))
9343 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9345 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9346 current_function_args_size,
9347 current_function_pretend_args_size, frame_size);
9349 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9350 frame_pointer_needed,
9351 cfun->machine->uses_anonymous_args);
9353 if (cfun->machine->lr_save_eliminated)
9354 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9356 if (current_function_calls_eh_return)
9357 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9359 #ifdef AOF_ASSEMBLER
9361 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9364 return_used_this_function = 0;
9368 arm_output_epilogue (rtx sibling)
9371 unsigned long saved_regs_mask;
9372 unsigned long func_type;
9373 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9374 frame that is $fp + 4 for a non-variadic function. */
9375 int floats_offset = 0;
9377 FILE * f = asm_out_file;
9378 unsigned int lrm_count = 0;
9379 int really_return = (sibling == NULL);
9381 arm_stack_offsets *offsets;
9383 /* If we have already generated the return instruction
9384 then it is futile to generate anything else. */
9385 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9388 func_type = arm_current_func_type ();
9390 if (IS_NAKED (func_type))
9391 /* Naked functions don't have epilogues. */
9394 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9398 /* A volatile function should never return. Call abort. */
9399 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9400 assemble_external_libcall (op);
9401 output_asm_insn ("bl\t%a0", &op);
9406 /* If we are throwing an exception, then we really must be doing a
9407 return, so we can't tail-call. */
9408 gcc_assert (!current_function_calls_eh_return || really_return);
9410 offsets = arm_get_frame_offsets ();
9411 saved_regs_mask = arm_compute_save_reg_mask ();
9414 lrm_count = bit_count (saved_regs_mask);
9416 floats_offset = offsets->saved_args;
9417 /* Compute how far away the floats will be. */
9418 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9419 if (saved_regs_mask & (1 << reg))
9422 if (frame_pointer_needed)
9424 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9425 int vfp_offset = offsets->frame;
9427 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9429 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9430 if (regs_ever_live[reg] && !call_used_regs[reg])
9432 floats_offset += 12;
9433 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9434 reg, FP_REGNUM, floats_offset - vfp_offset);
9439 start_reg = LAST_FPA_REGNUM;
9441 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9443 if (regs_ever_live[reg] && !call_used_regs[reg])
9445 floats_offset += 12;
9447 /* We can't unstack more than four registers at once. */
9448 if (start_reg - reg == 3)
9450 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9451 reg, FP_REGNUM, floats_offset - vfp_offset);
9452 start_reg = reg - 1;
9457 if (reg != start_reg)
9458 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9459 reg + 1, start_reg - reg,
9460 FP_REGNUM, floats_offset - vfp_offset);
9461 start_reg = reg - 1;
9465 /* Just in case the last register checked also needs unstacking. */
9466 if (reg != start_reg)
9467 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9468 reg + 1, start_reg - reg,
9469 FP_REGNUM, floats_offset - vfp_offset);
9472 if (TARGET_HARD_FLOAT && TARGET_VFP)
9476 /* The fldmx insn does not have base+offset addressing modes,
9477 so we use IP to hold the address. */
9478 saved_size = arm_get_vfp_saved_size ();
9482 floats_offset += saved_size;
9483 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9484 FP_REGNUM, floats_offset - vfp_offset);
9486 start_reg = FIRST_VFP_REGNUM;
9487 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9489 if ((!regs_ever_live[reg] || call_used_regs[reg])
9490 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9492 if (start_reg != reg)
9493 arm_output_fldmx (f, IP_REGNUM,
9494 (start_reg - FIRST_VFP_REGNUM) / 2,
9495 (reg - start_reg) / 2);
9496 start_reg = reg + 2;
9499 if (start_reg != reg)
9500 arm_output_fldmx (f, IP_REGNUM,
9501 (start_reg - FIRST_VFP_REGNUM) / 2,
9502 (reg - start_reg) / 2);
9507 /* The frame pointer is guaranteed to be non-double-word aligned.
9508 This is because it is set to (old_stack_pointer - 4) and the
9509 old_stack_pointer was double word aligned. Thus the offset to
9510 the iWMMXt registers to be loaded must also be non-double-word
9511 sized, so that the resultant address *is* double-word aligned.
9512 We can ignore floats_offset since that was already included in
9513 the live_regs_mask. */
9514 lrm_count += (lrm_count % 2 ? 2 : 1);
9516 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9517 if (regs_ever_live[reg] && !call_used_regs[reg])
9519 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9520 reg, FP_REGNUM, lrm_count * 4);
9525 /* saved_regs_mask should contain the IP, which at the time of stack
9526 frame generation actually contains the old stack pointer. So a
9527 quick way to unwind the stack is just pop the IP register directly
9528 into the stack pointer. */
9529 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
9530 saved_regs_mask &= ~ (1 << IP_REGNUM);
9531 saved_regs_mask |= (1 << SP_REGNUM);
9533 /* There are two registers left in saved_regs_mask - LR and PC. We
9534 only need to restore the LR register (the return address), but to
9535 save time we can load it directly into the PC, unless we need a
9536 special function exit sequence, or we are not really returning. */
9538 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9539 && !current_function_calls_eh_return)
9540 /* Delete the LR from the register mask, so that the LR on
9541 the stack is loaded into the PC in the register mask. */
9542 saved_regs_mask &= ~ (1 << LR_REGNUM);
9544 saved_regs_mask &= ~ (1 << PC_REGNUM);
9546 /* We must use SP as the base register, because SP is one of the
9547 registers being restored. If an interrupt or page fault
9548 happens in the ldm instruction, the SP might or might not
9549 have been restored. That would be bad, as then SP will no
9550 longer indicate the safe area of stack, and we can get stack
9551 corruption. Using SP as the base register means that it will
9552 be reset correctly to the original value, should an interrupt
9553 occur. If the stack pointer already points at the right
9554 place, then omit the subtraction. */
9555 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9556 || current_function_calls_alloca)
9557 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9558 4 * bit_count (saved_regs_mask));
9559 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9561 if (IS_INTERRUPT (func_type))
9562 /* Interrupt handlers will have pushed the
9563 IP onto the stack, so restore it now. */
9564 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9568 /* Restore stack pointer if necessary. */
9569 if (offsets->outgoing_args != offsets->saved_regs)
9571 operands[0] = operands[1] = stack_pointer_rtx;
9572 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9573 output_add_immediate (operands);
9576 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9578 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9579 if (regs_ever_live[reg] && !call_used_regs[reg])
9580 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9585 start_reg = FIRST_FPA_REGNUM;
9587 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9589 if (regs_ever_live[reg] && !call_used_regs[reg])
9591 if (reg - start_reg == 3)
9593 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9594 start_reg, SP_REGNUM);
9595 start_reg = reg + 1;
9600 if (reg != start_reg)
9601 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9602 start_reg, reg - start_reg,
9605 start_reg = reg + 1;
9609 /* Just in case the last register checked also needs unstacking. */
9610 if (reg != start_reg)
9611 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9612 start_reg, reg - start_reg, SP_REGNUM);
9615 if (TARGET_HARD_FLOAT && TARGET_VFP)
9617 start_reg = FIRST_VFP_REGNUM;
9618 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9620 if ((!regs_ever_live[reg] || call_used_regs[reg])
9621 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9623 if (start_reg != reg)
9624 arm_output_fldmx (f, SP_REGNUM,
9625 (start_reg - FIRST_VFP_REGNUM) / 2,
9626 (reg - start_reg) / 2);
9627 start_reg = reg + 2;
9630 if (start_reg != reg)
9631 arm_output_fldmx (f, SP_REGNUM,
9632 (start_reg - FIRST_VFP_REGNUM) / 2,
9633 (reg - start_reg) / 2);
9636 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9637 if (regs_ever_live[reg] && !call_used_regs[reg])
9638 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9640 /* If we can, restore the LR into the PC. */
9641 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9643 && current_function_pretend_args_size == 0
9644 && saved_regs_mask & (1 << LR_REGNUM)
9645 && !current_function_calls_eh_return)
9647 saved_regs_mask &= ~ (1 << LR_REGNUM);
9648 saved_regs_mask |= (1 << PC_REGNUM);
9651 /* Load the registers off the stack. If we only have one register
9652 to load use the LDR instruction - it is faster. */
9653 if (saved_regs_mask == (1 << LR_REGNUM))
9655 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9657 else if (saved_regs_mask)
9659 if (saved_regs_mask & (1 << SP_REGNUM))
9660 /* Note - write back to the stack register is not enabled
9661 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9662 in the list of registers and if we add writeback the
9663 instruction becomes UNPREDICTABLE. */
9664 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9666 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9669 if (current_function_pretend_args_size)
9671 /* Unwind the pre-pushed regs. */
9672 operands[0] = operands[1] = stack_pointer_rtx;
9673 operands[2] = GEN_INT (current_function_pretend_args_size);
9674 output_add_immediate (operands);
9678 /* We may have already restored PC directly from the stack. */
9679 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9682 /* Stack adjustment for exception handler. */
9683 if (current_function_calls_eh_return)
9684 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9685 ARM_EH_STACKADJ_REGNUM);
9687 /* Generate the return instruction. */
9688 switch ((int) ARM_FUNC_TYPE (func_type))
9692 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9695 case ARM_FT_EXCEPTION:
9696 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9699 case ARM_FT_INTERWORKED:
9700 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9704 if (arm_arch5 || arm_arch4t)
9705 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9707 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9715 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9716 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9718 arm_stack_offsets *offsets;
9724 /* Emit any call-via-reg trampolines that are needed for v4t support
9725 of call_reg and call_value_reg type insns. */
9726 for (regno = 0; regno < LR_REGNUM; regno++)
9728 rtx label = cfun->machine->call_via[regno];
9732 function_section (current_function_decl);
9733 targetm.asm_out.internal_label (asm_out_file, "L",
9734 CODE_LABEL_NUMBER (label));
9735 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
9739 /* ??? Probably not safe to set this here, since it assumes that a
9740 function will be emitted as assembly immediately after we generate
9741 RTL for it. This does not happen for inline functions. */
9742 return_used_this_function = 0;
9746 /* We need to take into account any stack-frame rounding. */
9747 offsets = arm_get_frame_offsets ();
9749 gcc_assert (!use_return_insn (FALSE, NULL)
9750 || !return_used_this_function
9751 || offsets->saved_regs == offsets->outgoing_args
9752 || frame_pointer_needed);
9754 /* Reset the ARM-specific per-function variables. */
9755 after_arm_reorg = 0;
9759 /* Generate and emit an insn that we will recognize as a push_multi.
9760 Unfortunately, since this insn does not reflect very well the actual
9761 semantics of the operation, we need to annotate the insn for the benefit
9762 of DWARF2 frame unwind information. */
9764 emit_multi_reg_push (unsigned long mask)
9771 int dwarf_par_index;
9774 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9775 if (mask & (1 << i))
9778 gcc_assert (num_regs && num_regs <= 16);
9780 /* We don't record the PC in the dwarf frame information. */
9781 num_dwarf_regs = num_regs;
9782 if (mask & (1 << PC_REGNUM))
9785 /* For the body of the insn we are going to generate an UNSPEC in
9786 parallel with several USEs. This allows the insn to be recognized
9787 by the push_multi pattern in the arm.md file. The insn looks
9788 something like this:
9791 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9792 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9793 (use (reg:SI 11 fp))
9794 (use (reg:SI 12 ip))
9795 (use (reg:SI 14 lr))
9796 (use (reg:SI 15 pc))
9799 For the frame note however, we try to be more explicit and actually
9800 show each register being stored into the stack frame, plus a (single)
9801 decrement of the stack pointer. We do it this way in order to be
9802 friendly to the stack unwinding code, which only wants to see a single
9803 stack decrement per instruction. The RTL we generate for the note looks
9804 something like this:
9807 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9808 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9809 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9810 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9811 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9814 This sequence is used both by the code to support stack unwinding for
9815 exceptions handlers and the code to generate dwarf2 frame debugging. */
9817 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9818 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9819 dwarf_par_index = 1;
9821 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9823 if (mask & (1 << i))
9825 reg = gen_rtx_REG (SImode, i);
9828 = gen_rtx_SET (VOIDmode,
9829 gen_rtx_MEM (BLKmode,
9830 gen_rtx_PRE_DEC (BLKmode,
9831 stack_pointer_rtx)),
9832 gen_rtx_UNSPEC (BLKmode,
9838 tmp = gen_rtx_SET (VOIDmode,
9839 gen_rtx_MEM (SImode, stack_pointer_rtx),
9841 RTX_FRAME_RELATED_P (tmp) = 1;
9842 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9850 for (j = 1, i++; j < num_regs; i++)
9852 if (mask & (1 << i))
9854 reg = gen_rtx_REG (SImode, i);
9856 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9860 tmp = gen_rtx_SET (VOIDmode,
9861 gen_rtx_MEM (SImode,
9862 plus_constant (stack_pointer_rtx,
9865 RTX_FRAME_RELATED_P (tmp) = 1;
9866 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9873 par = emit_insn (par);
9875 tmp = gen_rtx_SET (SImode,
9877 gen_rtx_PLUS (SImode,
9879 GEN_INT (-4 * num_regs)));
9880 RTX_FRAME_RELATED_P (tmp) = 1;
9881 XVECEXP (dwarf, 0, 0) = tmp;
9883 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9888 /* Calculate the size of the return value that is passed in registers. */
9890 arm_size_return_regs (void)
9892 enum machine_mode mode;
9894 if (current_function_return_rtx != 0)
9895 mode = GET_MODE (current_function_return_rtx);
9897 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9899 return GET_MODE_SIZE (mode);
9903 emit_sfm (int base_reg, int count)
9910 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9911 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9913 reg = gen_rtx_REG (XFmode, base_reg++);
9916 = gen_rtx_SET (VOIDmode,
9917 gen_rtx_MEM (BLKmode,
9918 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9919 gen_rtx_UNSPEC (BLKmode,
9922 tmp = gen_rtx_SET (VOIDmode,
9923 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
9924 RTX_FRAME_RELATED_P (tmp) = 1;
9925 XVECEXP (dwarf, 0, 1) = tmp;
9927 for (i = 1; i < count; i++)
9929 reg = gen_rtx_REG (XFmode, base_reg++);
9930 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9932 tmp = gen_rtx_SET (VOIDmode,
9933 gen_rtx_MEM (XFmode,
9934 plus_constant (stack_pointer_rtx,
9937 RTX_FRAME_RELATED_P (tmp) = 1;
9938 XVECEXP (dwarf, 0, i + 1) = tmp;
9941 tmp = gen_rtx_SET (VOIDmode,
9943 gen_rtx_PLUS (SImode,
9945 GEN_INT (-12 * count)));
9946 RTX_FRAME_RELATED_P (tmp) = 1;
9947 XVECEXP (dwarf, 0, 0) = tmp;
9949 par = emit_insn (par);
9950 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9956 /* Return true if the current function needs to save/restore LR. */
9959 thumb_force_lr_save (void)
9961 return !cfun->machine->lr_save_eliminated
9962 && (!leaf_function_p ()
9963 || thumb_far_jump_used_p ()
9964 || regs_ever_live [LR_REGNUM]);
9968 /* Compute the distance from register FROM to register TO.
9969 These can be the arg pointer (26), the soft frame pointer (25),
9970 the stack pointer (13) or the hard frame pointer (11).
9971 In thumb mode r7 is used as the soft frame pointer, if needed.
9972 Typical stack layout looks like this:
9974 old stack pointer -> | |
9977 | | saved arguments for
9978 | | vararg functions
9981 hard FP & arg pointer -> | | \
9989 soft frame pointer -> | | /
9999 current stack pointer -> | | /
10002 For a given function some or all of these stack components
10003 may not be needed, giving rise to the possibility of
10004 eliminating some of the registers.
10006 The values returned by this function must reflect the behavior
10007 of arm_expand_prologue() and arm_compute_save_reg_mask().
10009 The sign of the number returned reflects the direction of stack
10010 growth, so the values are positive for all eliminations except
10011 from the soft frame pointer to the hard frame pointer.
10013 SFP may point just inside the local variables block to ensure correct
10017 /* Calculate stack offsets. These are used to calculate register elimination
10018 offsets and in prologue/epilogue code. */
10020 static arm_stack_offsets *
10021 arm_get_frame_offsets (void)
10023 struct arm_stack_offsets *offsets;
10024 unsigned long func_type;
10027 HOST_WIDE_INT frame_size;
10029 offsets = &cfun->machine->stack_offsets;
10031 /* We need to know if we are a leaf function. Unfortunately, it
10032 is possible to be called after start_sequence has been called,
10033 which causes get_insns to return the insns for the sequence,
10034 not the function, which will cause leaf_function_p to return
10035 the incorrect result.
10037 to know about leaf functions once reload has completed, and the
10038 frame size cannot be changed after that time, so we can safely
10039 use the cached value. */
10041 if (reload_completed)
10044 /* Initially this is the size of the local variables. It will translated
10045 into an offset once we have determined the size of preceding data. */
10046 frame_size = ROUND_UP_WORD (get_frame_size ());
10048 leaf = leaf_function_p ();
10050 /* Space for variadic functions. */
10051 offsets->saved_args = current_function_pretend_args_size;
10053 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10057 unsigned int regno;
10059 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10061 /* We know that SP will be doubleword aligned on entry, and we must
10062 preserve that condition at any subroutine call. We also require the
10063 soft frame pointer to be doubleword aligned. */
10065 if (TARGET_REALLY_IWMMXT)
10067 /* Check for the call-saved iWMMXt registers. */
10068 for (regno = FIRST_IWMMXT_REGNUM;
10069 regno <= LAST_IWMMXT_REGNUM;
10071 if (regs_ever_live [regno] && ! call_used_regs [regno])
10075 func_type = arm_current_func_type ();
10076 if (! IS_VOLATILE (func_type))
10078 /* Space for saved FPA registers. */
10079 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10080 if (regs_ever_live[regno] && ! call_used_regs[regno])
10083 /* Space for saved VFP registers. */
10084 if (TARGET_HARD_FLOAT && TARGET_VFP)
10085 saved += arm_get_vfp_saved_size ();
10088 else /* TARGET_THUMB */
10090 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10091 if (TARGET_BACKTRACE)
10095 /* Saved registers include the stack frame. */
10096 offsets->saved_regs = offsets->saved_args + saved;
10097 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
10098 /* A leaf function does not need any stack alignment if it has nothing
10100 if (leaf && frame_size == 0)
10102 offsets->outgoing_args = offsets->soft_frame;
10106 /* Ensure SFP has the correct alignment. */
10107 if (ARM_DOUBLEWORD_ALIGN
10108 && (offsets->soft_frame & 7))
10109 offsets->soft_frame += 4;
10111 offsets->outgoing_args = offsets->soft_frame + frame_size
10112 + current_function_outgoing_args_size;
10114 if (ARM_DOUBLEWORD_ALIGN)
10116 /* Ensure SP remains doubleword aligned. */
10117 if (offsets->outgoing_args & 7)
10118 offsets->outgoing_args += 4;
10119 gcc_assert (!(offsets->outgoing_args & 7));
10126 /* Calculate the relative offsets for the different stack pointers. Positive
10127 offsets are in the direction of stack growth. */
10130 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10132 arm_stack_offsets *offsets;
10134 offsets = arm_get_frame_offsets ();
10136 /* OK, now we have enough information to compute the distances.
10137 There must be an entry in these switch tables for each pair
10138 of registers in ELIMINABLE_REGS, even if some of the entries
10139 seem to be redundant or useless. */
10142 case ARG_POINTER_REGNUM:
10145 case THUMB_HARD_FRAME_POINTER_REGNUM:
10148 case FRAME_POINTER_REGNUM:
10149 /* This is the reverse of the soft frame pointer
10150 to hard frame pointer elimination below. */
10151 return offsets->soft_frame - offsets->saved_args;
10153 case ARM_HARD_FRAME_POINTER_REGNUM:
10154 /* If there is no stack frame then the hard
10155 frame pointer and the arg pointer coincide. */
10156 if (offsets->frame == offsets->saved_regs)
10158 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10159 return (frame_pointer_needed
10160 && cfun->static_chain_decl != NULL
10161 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10163 case STACK_POINTER_REGNUM:
10164 /* If nothing has been pushed on the stack at all
10165 then this will return -4. This *is* correct! */
10166 return offsets->outgoing_args - (offsets->saved_args + 4);
10169 gcc_unreachable ();
10171 gcc_unreachable ();
10173 case FRAME_POINTER_REGNUM:
10176 case THUMB_HARD_FRAME_POINTER_REGNUM:
10179 case ARM_HARD_FRAME_POINTER_REGNUM:
10180 /* The hard frame pointer points to the top entry in the
10181 stack frame. The soft frame pointer to the bottom entry
10182 in the stack frame. If there is no stack frame at all,
10183 then they are identical. */
10185 return offsets->frame - offsets->soft_frame;
10187 case STACK_POINTER_REGNUM:
10188 return offsets->outgoing_args - offsets->soft_frame;
10191 gcc_unreachable ();
10193 gcc_unreachable ();
10196 /* You cannot eliminate from the stack pointer.
10197 In theory you could eliminate from the hard frame
10198 pointer to the stack pointer, but this will never
10199 happen, since if a stack frame is not needed the
10200 hard frame pointer will never be used. */
10201 gcc_unreachable ();
10206 /* Generate the prologue instructions for entry into an ARM function. */
10208 arm_expand_prologue (void)
10214 unsigned long live_regs_mask;
10215 unsigned long func_type;
10217 int saved_pretend_args = 0;
10218 int saved_regs = 0;
10219 unsigned HOST_WIDE_INT args_to_push;
10220 arm_stack_offsets *offsets;
10222 func_type = arm_current_func_type ();
10224 /* Naked functions don't have prologues. */
10225 if (IS_NAKED (func_type))
10228 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10229 args_to_push = current_function_pretend_args_size;
10231 /* Compute which register we will have to save onto the stack. */
10232 live_regs_mask = arm_compute_save_reg_mask ();
10234 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10236 if (frame_pointer_needed)
10238 if (IS_INTERRUPT (func_type))
10240 /* Interrupt functions must not corrupt any registers.
10241 Creating a frame pointer however, corrupts the IP
10242 register, so we must push it first. */
10243 insn = emit_multi_reg_push (1 << IP_REGNUM);
10245 /* Do not set RTX_FRAME_RELATED_P on this insn.
10246 The dwarf stack unwinding code only wants to see one
10247 stack decrement per function, and this is not it. If
10248 this instruction is labeled as being part of the frame
10249 creation sequence then dwarf2out_frame_debug_expr will
10250 die when it encounters the assignment of IP to FP
10251 later on, since the use of SP here establishes SP as
10252 the CFA register and not IP.
10254 Anyway this instruction is not really part of the stack
10255 frame creation although it is part of the prologue. */
10257 else if (IS_NESTED (func_type))
10259 /* The Static chain register is the same as the IP register
10260 used as a scratch register during stack frame creation.
10261 To get around this need to find somewhere to store IP
10262 whilst the frame is being created. We try the following
10265 1. The last argument register.
10266 2. A slot on the stack above the frame. (This only
10267 works if the function is not a varargs function).
10268 3. Register r3, after pushing the argument registers
10271 Note - we only need to tell the dwarf2 backend about the SP
10272 adjustment in the second variant; the static chain register
10273 doesn't need to be unwound, as it doesn't contain a value
10274 inherited from the caller. */
10276 if (regs_ever_live[3] == 0)
10278 insn = gen_rtx_REG (SImode, 3);
10279 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10280 insn = emit_insn (insn);
10282 else if (args_to_push == 0)
10285 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10286 insn = gen_rtx_MEM (SImode, insn);
10287 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10288 insn = emit_insn (insn);
10292 /* Just tell the dwarf backend that we adjusted SP. */
10293 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10294 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10295 GEN_INT (-fp_offset)));
10296 RTX_FRAME_RELATED_P (insn) = 1;
10297 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10298 dwarf, REG_NOTES (insn));
10302 /* Store the args on the stack. */
10303 if (cfun->machine->uses_anonymous_args)
10304 insn = emit_multi_reg_push
10305 ((0xf0 >> (args_to_push / 4)) & 0xf);
10308 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10309 GEN_INT (- args_to_push)));
10311 RTX_FRAME_RELATED_P (insn) = 1;
10313 saved_pretend_args = 1;
10314 fp_offset = args_to_push;
10317 /* Now reuse r3 to preserve IP. */
10318 insn = gen_rtx_REG (SImode, 3);
10319 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10320 (void) emit_insn (insn);
10326 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10327 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10330 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10332 insn = emit_insn (insn);
10333 RTX_FRAME_RELATED_P (insn) = 1;
10338 /* Push the argument registers, or reserve space for them. */
10339 if (cfun->machine->uses_anonymous_args)
10340 insn = emit_multi_reg_push
10341 ((0xf0 >> (args_to_push / 4)) & 0xf);
10344 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10345 GEN_INT (- args_to_push)));
10346 RTX_FRAME_RELATED_P (insn) = 1;
10349 /* If this is an interrupt service routine, and the link register
10350 is going to be pushed, and we are not creating a stack frame,
10351 (which would involve an extra push of IP and a pop in the epilogue)
10352 subtracting four from LR now will mean that the function return
10353 can be done with a single instruction. */
10354 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10355 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10356 && ! frame_pointer_needed)
10357 emit_insn (gen_rtx_SET (SImode,
10358 gen_rtx_REG (SImode, LR_REGNUM),
10359 gen_rtx_PLUS (SImode,
10360 gen_rtx_REG (SImode, LR_REGNUM),
10363 if (live_regs_mask)
10365 insn = emit_multi_reg_push (live_regs_mask);
10366 saved_regs += bit_count (live_regs_mask) * 4;
10367 RTX_FRAME_RELATED_P (insn) = 1;
10371 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10372 if (regs_ever_live[reg] && ! call_used_regs [reg])
10374 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10375 insn = gen_rtx_MEM (V2SImode, insn);
10376 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10377 gen_rtx_REG (V2SImode, reg)));
10378 RTX_FRAME_RELATED_P (insn) = 1;
10382 if (! IS_VOLATILE (func_type))
10386 /* Save any floating point call-saved registers used by this
10388 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10390 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10391 if (regs_ever_live[reg] && !call_used_regs[reg])
10393 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10394 insn = gen_rtx_MEM (XFmode, insn);
10395 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10396 gen_rtx_REG (XFmode, reg)));
10397 RTX_FRAME_RELATED_P (insn) = 1;
10403 start_reg = LAST_FPA_REGNUM;
10405 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10407 if (regs_ever_live[reg] && !call_used_regs[reg])
10409 if (start_reg - reg == 3)
10411 insn = emit_sfm (reg, 4);
10412 RTX_FRAME_RELATED_P (insn) = 1;
10414 start_reg = reg - 1;
10419 if (start_reg != reg)
10421 insn = emit_sfm (reg + 1, start_reg - reg);
10422 RTX_FRAME_RELATED_P (insn) = 1;
10423 saved_regs += (start_reg - reg) * 12;
10425 start_reg = reg - 1;
10429 if (start_reg != reg)
10431 insn = emit_sfm (reg + 1, start_reg - reg);
10432 saved_regs += (start_reg - reg) * 12;
10433 RTX_FRAME_RELATED_P (insn) = 1;
10436 if (TARGET_HARD_FLOAT && TARGET_VFP)
10438 start_reg = FIRST_VFP_REGNUM;
10440 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10442 if ((!regs_ever_live[reg] || call_used_regs[reg])
10443 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10445 if (start_reg != reg)
10446 saved_regs += vfp_emit_fstmx (start_reg,
10447 (reg - start_reg) / 2);
10448 start_reg = reg + 2;
10451 if (start_reg != reg)
10452 saved_regs += vfp_emit_fstmx (start_reg,
10453 (reg - start_reg) / 2);
10457 if (frame_pointer_needed)
10459 /* Create the new frame pointer. */
10460 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10461 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10462 RTX_FRAME_RELATED_P (insn) = 1;
10464 if (IS_NESTED (func_type))
10466 /* Recover the static chain register. */
10467 if (regs_ever_live [3] == 0
10468 || saved_pretend_args)
10469 insn = gen_rtx_REG (SImode, 3);
10470 else /* if (current_function_pretend_args_size == 0) */
10472 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10474 insn = gen_rtx_MEM (SImode, insn);
10477 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10478 /* Add a USE to stop propagate_one_insn() from barfing. */
10479 emit_insn (gen_prologue_use (ip_rtx));
10483 offsets = arm_get_frame_offsets ();
10484 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10486 /* This add can produce multiple insns for a large constant, so we
10487 need to get tricky. */
10488 rtx last = get_last_insn ();
10490 amount = GEN_INT (offsets->saved_args + saved_regs
10491 - offsets->outgoing_args);
10493 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10497 last = last ? NEXT_INSN (last) : get_insns ();
10498 RTX_FRAME_RELATED_P (last) = 1;
10500 while (last != insn);
10502 /* If the frame pointer is needed, emit a special barrier that
10503 will prevent the scheduler from moving stores to the frame
10504 before the stack adjustment. */
10505 if (frame_pointer_needed)
10506 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10507 hard_frame_pointer_rtx));
10512 arm_load_pic_register (INVALID_REGNUM);
10514 /* If we are profiling, make sure no instructions are scheduled before
10515 the call to mcount. Similarly if the user has requested no
10516 scheduling in the prolog. */
10517 if (current_function_profile || !TARGET_SCHED_PROLOG)
10518 emit_insn (gen_blockage ());
10520 /* If the link register is being kept alive, with the return address in it,
10521 then make sure that it does not get reused by the ce2 pass. */
10522 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10524 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10525 cfun->machine->lr_save_eliminated = 1;
10529 /* If CODE is 'd', then the X is a condition operand and the instruction
10530 should only be executed if the condition is true.
10531 if CODE is 'D', then the X is a condition operand and the instruction
10532 should only be executed if the condition is false: however, if the mode
10533 of the comparison is CCFPEmode, then always execute the instruction -- we
10534 do this because in these circumstances !GE does not necessarily imply LT;
10535 in these cases the instruction pattern will take care to make sure that
10536 an instruction containing %d will follow, thereby undoing the effects of
10537 doing this instruction unconditionally.
10538 If CODE is 'N' then X is a floating point operand that must be negated
10540 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10541 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10543 arm_print_operand (FILE *stream, rtx x, int code)
10548 fputs (ASM_COMMENT_START, stream);
10552 fputs (user_label_prefix, stream);
10556 fputs (REGISTER_PREFIX, stream);
10560 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10564 output_operand_lossage ("predicated Thumb instruction");
10567 if (current_insn_predicate != NULL)
10569 output_operand_lossage
10570 ("predicated instruction in conditional sequence");
10574 fputs (arm_condition_codes[arm_current_cc], stream);
10576 else if (current_insn_predicate)
10578 enum arm_cond_code code;
10582 output_operand_lossage ("predicated Thumb instruction");
10586 code = get_arm_condition_code (current_insn_predicate);
10587 fputs (arm_condition_codes[code], stream);
10594 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10595 r = REAL_VALUE_NEGATE (r);
10596 fprintf (stream, "%s", fp_const_from_val (&r));
10601 if (GET_CODE (x) == CONST_INT)
10604 val = ARM_SIGN_EXTEND (~INTVAL (x));
10605 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10609 putc ('~', stream);
10610 output_addr_const (stream, x);
10615 fprintf (stream, "%s", arithmetic_instr (x, 1));
10618 /* Truncate Cirrus shift counts. */
10620 if (GET_CODE (x) == CONST_INT)
10622 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10625 arm_print_operand (stream, x, 0);
10629 fprintf (stream, "%s", arithmetic_instr (x, 0));
10635 const char * shift = shift_op (x, &val);
10639 fprintf (stream, ", %s ", shift_op (x, &val));
10641 arm_print_operand (stream, XEXP (x, 1), 0);
10643 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10648 /* An explanation of the 'Q', 'R' and 'H' register operands:
10650 In a pair of registers containing a DI or DF value the 'Q'
10651 operand returns the register number of the register containing
10652 the least significant part of the value. The 'R' operand returns
10653 the register number of the register containing the most
10654 significant part of the value.
10656 The 'H' operand returns the higher of the two register numbers.
10657 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10658 same as the 'Q' operand, since the most significant part of the
10659 value is held in the lower number register. The reverse is true
10660 on systems where WORDS_BIG_ENDIAN is false.
10662 The purpose of these operands is to distinguish between cases
10663 where the endian-ness of the values is important (for example
10664 when they are added together), and cases where the endian-ness
10665 is irrelevant, but the order of register operations is important.
10666 For example when loading a value from memory into a register
10667 pair, the endian-ness does not matter. Provided that the value
10668 from the lower memory address is put into the lower numbered
10669 register, and the value from the higher address is put into the
10670 higher numbered register, the load will work regardless of whether
10671 the value being loaded is big-wordian or little-wordian. The
10672 order of the two register loads can matter however, if the address
10673 of the memory location is actually held in one of the registers
10674 being overwritten by the load. */
10676 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10678 output_operand_lossage ("invalid operand for code '%c'", code);
10682 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10686 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10688 output_operand_lossage ("invalid operand for code '%c'", code);
10692 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10696 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10698 output_operand_lossage ("invalid operand for code '%c'", code);
10702 asm_fprintf (stream, "%r", REGNO (x) + 1);
10706 asm_fprintf (stream, "%r",
10707 GET_CODE (XEXP (x, 0)) == REG
10708 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10712 asm_fprintf (stream, "{%r-%r}",
10714 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10718 /* CONST_TRUE_RTX means always -- that's the default. */
10719 if (x == const_true_rtx)
10722 if (!COMPARISON_P (x))
10724 output_operand_lossage ("invalid operand for code '%c'", code);
10728 fputs (arm_condition_codes[get_arm_condition_code (x)],
10733 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10734 want to do that. */
10735 if (x == const_true_rtx)
10737 output_operand_lossage ("instruction never exectued");
10740 if (!COMPARISON_P (x))
10742 output_operand_lossage ("invalid operand for code '%c'", code);
10746 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10747 (get_arm_condition_code (x))],
10751 /* Cirrus registers can be accessed in a variety of ways:
10752 single floating point (f)
10753 double floating point (d)
10755 64bit integer (dx). */
10756 case 'W': /* Cirrus register in F mode. */
10757 case 'X': /* Cirrus register in D mode. */
10758 case 'Y': /* Cirrus register in FX mode. */
10759 case 'Z': /* Cirrus register in DX mode. */
10760 gcc_assert (GET_CODE (x) == REG
10761 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
10763 fprintf (stream, "mv%s%s",
10765 : code == 'X' ? "d"
10766 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10770 /* Print cirrus register in the mode specified by the register's mode. */
10773 int mode = GET_MODE (x);
10775 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10777 output_operand_lossage ("invalid operand for code '%c'", code);
10781 fprintf (stream, "mv%s%s",
10782 mode == DFmode ? "d"
10783 : mode == SImode ? "fx"
10784 : mode == DImode ? "dx"
10785 : "f", reg_names[REGNO (x)] + 2);
10791 if (GET_CODE (x) != REG
10792 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10793 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10794 /* Bad value for wCG register number. */
10796 output_operand_lossage ("invalid operand for code '%c'", code);
10801 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10804 /* Print an iWMMXt control register name. */
10806 if (GET_CODE (x) != CONST_INT
10808 || INTVAL (x) >= 16)
10809 /* Bad value for wC register number. */
10811 output_operand_lossage ("invalid operand for code '%c'", code);
10817 static const char * wc_reg_names [16] =
10819 "wCID", "wCon", "wCSSF", "wCASF",
10820 "wC4", "wC5", "wC6", "wC7",
10821 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10822 "wC12", "wC13", "wC14", "wC15"
10825 fprintf (stream, wc_reg_names [INTVAL (x)]);
10829 /* Print a VFP double precision register name. */
10832 int mode = GET_MODE (x);
10835 if (mode != DImode && mode != DFmode)
10837 output_operand_lossage ("invalid operand for code '%c'", code);
10841 if (GET_CODE (x) != REG
10842 || !IS_VFP_REGNUM (REGNO (x)))
10844 output_operand_lossage ("invalid operand for code '%c'", code);
10848 num = REGNO(x) - FIRST_VFP_REGNUM;
10851 output_operand_lossage ("invalid operand for code '%c'", code);
10855 fprintf (stream, "d%d", num >> 1);
10862 output_operand_lossage ("missing operand");
10866 switch (GET_CODE (x))
10869 asm_fprintf (stream, "%r", REGNO (x));
10873 output_memory_reference_mode = GET_MODE (x);
10874 output_address (XEXP (x, 0));
10878 fprintf (stream, "#%s", fp_immediate_constant (x));
10882 gcc_assert (GET_CODE (x) != NEG);
10883 fputc ('#', stream);
10884 output_addr_const (stream, x);
10890 #ifndef AOF_ASSEMBLER
10891 /* Target hook for assembling integer objects. The ARM version needs to
10892 handle word-sized values specially. */
10894 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10896 if (size == UNITS_PER_WORD && aligned_p)
10898 fputs ("\t.word\t", asm_out_file);
10899 output_addr_const (asm_out_file, x);
10901 /* Mark symbols as position independent. We only do this in the
10902 .text segment, not in the .data segment. */
10903 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10904 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10906 if (GET_CODE (x) == SYMBOL_REF
10907 && (CONSTANT_POOL_ADDRESS_P (x)
10908 || SYMBOL_REF_LOCAL_P (x)))
10909 fputs ("(GOTOFF)", asm_out_file);
10910 else if (GET_CODE (x) == LABEL_REF)
10911 fputs ("(GOTOFF)", asm_out_file);
10913 fputs ("(GOT)", asm_out_file);
10915 fputc ('\n', asm_out_file);
10919 if (arm_vector_mode_supported_p (GET_MODE (x)))
10923 gcc_assert (GET_CODE (x) == CONST_VECTOR);
10925 units = CONST_VECTOR_NUNITS (x);
10927 switch (GET_MODE (x))
10929 case V2SImode: size = 4; break;
10930 case V4HImode: size = 2; break;
10931 case V8QImode: size = 1; break;
10933 gcc_unreachable ();
10936 for (i = 0; i < units; i++)
10940 elt = CONST_VECTOR_ELT (x, i);
10942 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10948 return default_assemble_integer (x, size, aligned_p);
10952 /* Add a function to the list of static constructors. */
10955 arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10957 if (!TARGET_AAPCS_BASED)
10959 default_named_section_asm_out_constructor (symbol, priority);
10963 /* Put these in the .init_array section, using a special relocation. */
10965 assemble_align (POINTER_SIZE);
10966 fputs ("\t.word\t", asm_out_file);
10967 output_addr_const (asm_out_file, symbol);
10968 fputs ("(target1)\n", asm_out_file);
10972 /* A finite state machine takes care of noticing whether or not instructions
10973 can be conditionally executed, and thus decrease execution time and code
10974 size by deleting branch instructions. The fsm is controlled by
10975 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10977 /* The state of the fsm controlling condition codes are:
10978 0: normal, do nothing special
10979 1: make ASM_OUTPUT_OPCODE not output this instruction
10980 2: make ASM_OUTPUT_OPCODE not output this instruction
10981 3: make instructions conditional
10982 4: make instructions conditional
10984 State transitions (state->state by whom under condition):
10985 0 -> 1 final_prescan_insn if the `target' is a label
10986 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10987 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10988 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10989 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10990 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10991 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10992 (the target insn is arm_target_insn).
10994 If the jump clobbers the conditions then we use states 2 and 4.
10996 A similar thing can be done with conditional return insns.
10998 XXX In case the `target' is an unconditional branch, this conditionalising
10999 of the instructions always reduces code size, but not always execution
11000 time. But then, I want to reduce the code size to somewhere near what
11001 /bin/cc produces. */
11003 /* Returns the index of the ARM condition code string in
11004 `arm_condition_codes'. COMPARISON should be an rtx like
11005 `(eq (...) (...))'. */
11006 static enum arm_cond_code
11007 get_arm_condition_code (rtx comparison)
11009 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11011 enum rtx_code comp_code = GET_CODE (comparison);
11013 if (GET_MODE_CLASS (mode) != MODE_CC)
11014 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11015 XEXP (comparison, 1));
11019 case CC_DNEmode: code = ARM_NE; goto dominance;
11020 case CC_DEQmode: code = ARM_EQ; goto dominance;
11021 case CC_DGEmode: code = ARM_GE; goto dominance;
11022 case CC_DGTmode: code = ARM_GT; goto dominance;
11023 case CC_DLEmode: code = ARM_LE; goto dominance;
11024 case CC_DLTmode: code = ARM_LT; goto dominance;
11025 case CC_DGEUmode: code = ARM_CS; goto dominance;
11026 case CC_DGTUmode: code = ARM_HI; goto dominance;
11027 case CC_DLEUmode: code = ARM_LS; goto dominance;
11028 case CC_DLTUmode: code = ARM_CC;
11031 gcc_assert (comp_code == EQ || comp_code == NE);
11033 if (comp_code == EQ)
11034 return ARM_INVERSE_CONDITION_CODE (code);
11040 case NE: return ARM_NE;
11041 case EQ: return ARM_EQ;
11042 case GE: return ARM_PL;
11043 case LT: return ARM_MI;
11044 default: gcc_unreachable ();
11050 case NE: return ARM_NE;
11051 case EQ: return ARM_EQ;
11052 default: gcc_unreachable ();
11058 case NE: return ARM_MI;
11059 case EQ: return ARM_PL;
11060 default: gcc_unreachable ();
11065 /* These encodings assume that AC=1 in the FPA system control
11066 byte. This allows us to handle all cases except UNEQ and
11070 case GE: return ARM_GE;
11071 case GT: return ARM_GT;
11072 case LE: return ARM_LS;
11073 case LT: return ARM_MI;
11074 case NE: return ARM_NE;
11075 case EQ: return ARM_EQ;
11076 case ORDERED: return ARM_VC;
11077 case UNORDERED: return ARM_VS;
11078 case UNLT: return ARM_LT;
11079 case UNLE: return ARM_LE;
11080 case UNGT: return ARM_HI;
11081 case UNGE: return ARM_PL;
11082 /* UNEQ and LTGT do not have a representation. */
11083 case UNEQ: /* Fall through. */
11084 case LTGT: /* Fall through. */
11085 default: gcc_unreachable ();
11091 case NE: return ARM_NE;
11092 case EQ: return ARM_EQ;
11093 case GE: return ARM_LE;
11094 case GT: return ARM_LT;
11095 case LE: return ARM_GE;
11096 case LT: return ARM_GT;
11097 case GEU: return ARM_LS;
11098 case GTU: return ARM_CC;
11099 case LEU: return ARM_CS;
11100 case LTU: return ARM_HI;
11101 default: gcc_unreachable ();
11107 case LTU: return ARM_CS;
11108 case GEU: return ARM_CC;
11109 default: gcc_unreachable ();
11115 case NE: return ARM_NE;
11116 case EQ: return ARM_EQ;
11117 case GE: return ARM_GE;
11118 case GT: return ARM_GT;
11119 case LE: return ARM_LE;
11120 case LT: return ARM_LT;
11121 case GEU: return ARM_CS;
11122 case GTU: return ARM_HI;
11123 case LEU: return ARM_LS;
11124 case LTU: return ARM_CC;
11125 default: gcc_unreachable ();
11128 default: gcc_unreachable ();
11133 arm_final_prescan_insn (rtx insn)
11135 /* BODY will hold the body of INSN. */
11136 rtx body = PATTERN (insn);
11138 /* This will be 1 if trying to repeat the trick, and things need to be
11139 reversed if it appears to fail. */
11142 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11143 taken are clobbered, even if the rtl suggests otherwise. It also
11144 means that we have to grub around within the jump expression to find
11145 out what the conditions are when the jump isn't taken. */
11146 int jump_clobbers = 0;
11148 /* If we start with a return insn, we only succeed if we find another one. */
11149 int seeking_return = 0;
11151 /* START_INSN will hold the insn from where we start looking. This is the
11152 first insn after the following code_label if REVERSE is true. */
11153 rtx start_insn = insn;
11155 /* If in state 4, check if the target branch is reached, in order to
11156 change back to state 0. */
11157 if (arm_ccfsm_state == 4)
11159 if (insn == arm_target_insn)
11161 arm_target_insn = NULL;
11162 arm_ccfsm_state = 0;
11167 /* If in state 3, it is possible to repeat the trick, if this insn is an
11168 unconditional branch to a label, and immediately following this branch
11169 is the previous target label which is only used once, and the label this
11170 branch jumps to is not too far off. */
11171 if (arm_ccfsm_state == 3)
11173 if (simplejump_p (insn))
11175 start_insn = next_nonnote_insn (start_insn);
11176 if (GET_CODE (start_insn) == BARRIER)
11178 /* XXX Isn't this always a barrier? */
11179 start_insn = next_nonnote_insn (start_insn);
11181 if (GET_CODE (start_insn) == CODE_LABEL
11182 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11183 && LABEL_NUSES (start_insn) == 1)
11188 else if (GET_CODE (body) == RETURN)
11190 start_insn = next_nonnote_insn (start_insn);
11191 if (GET_CODE (start_insn) == BARRIER)
11192 start_insn = next_nonnote_insn (start_insn);
11193 if (GET_CODE (start_insn) == CODE_LABEL
11194 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11195 && LABEL_NUSES (start_insn) == 1)
11198 seeking_return = 1;
11207 gcc_assert (!arm_ccfsm_state || reverse);
11208 if (GET_CODE (insn) != JUMP_INSN)
11211 /* This jump might be paralleled with a clobber of the condition codes
11212 the jump should always come first */
11213 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11214 body = XVECEXP (body, 0, 0);
11217 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11218 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11221 int fail = FALSE, succeed = FALSE;
11222 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11223 int then_not_else = TRUE;
11224 rtx this_insn = start_insn, label = 0;
11226 /* If the jump cannot be done with one instruction, we cannot
11227 conditionally execute the instruction in the inverse case. */
11228 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11234 /* Register the insn jumped to. */
11237 if (!seeking_return)
11238 label = XEXP (SET_SRC (body), 0);
11240 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11241 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11242 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11244 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11245 then_not_else = FALSE;
11247 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11248 seeking_return = 1;
11249 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11251 seeking_return = 1;
11252 then_not_else = FALSE;
11255 gcc_unreachable ();
11257 /* See how many insns this branch skips, and what kind of insns. If all
11258 insns are okay, and the label or unconditional branch to the same
11259 label is not too far away, succeed. */
11260 for (insns_skipped = 0;
11261 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11265 this_insn = next_nonnote_insn (this_insn);
11269 switch (GET_CODE (this_insn))
11272 /* Succeed if it is the target label, otherwise fail since
11273 control falls in from somewhere else. */
11274 if (this_insn == label)
11278 arm_ccfsm_state = 2;
11279 this_insn = next_nonnote_insn (this_insn);
11282 arm_ccfsm_state = 1;
11290 /* Succeed if the following insn is the target label.
11292 If return insns are used then the last insn in a function
11293 will be a barrier. */
11294 this_insn = next_nonnote_insn (this_insn);
11295 if (this_insn && this_insn == label)
11299 arm_ccfsm_state = 2;
11300 this_insn = next_nonnote_insn (this_insn);
11303 arm_ccfsm_state = 1;
11311 /* The AAPCS says that conditional calls should not be
11312 used since they make interworking inefficient (the
11313 linker can't transform BL<cond> into BLX). That's
11314 only a problem if the machine has BLX. */
11321 /* Succeed if the following insn is the target label, or
11322 if the following two insns are a barrier and the
11324 this_insn = next_nonnote_insn (this_insn);
11325 if (this_insn && GET_CODE (this_insn) == BARRIER)
11326 this_insn = next_nonnote_insn (this_insn);
11328 if (this_insn && this_insn == label
11329 && insns_skipped < max_insns_skipped)
11333 arm_ccfsm_state = 2;
11334 this_insn = next_nonnote_insn (this_insn);
11337 arm_ccfsm_state = 1;
11345 /* If this is an unconditional branch to the same label, succeed.
11346 If it is to another label, do nothing. If it is conditional,
11348 /* XXX Probably, the tests for SET and the PC are
11351 scanbody = PATTERN (this_insn);
11352 if (GET_CODE (scanbody) == SET
11353 && GET_CODE (SET_DEST (scanbody)) == PC)
11355 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11356 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11358 arm_ccfsm_state = 2;
11361 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11364 /* Fail if a conditional return is undesirable (e.g. on a
11365 StrongARM), but still allow this if optimizing for size. */
11366 else if (GET_CODE (scanbody) == RETURN
11367 && !use_return_insn (TRUE, NULL)
11370 else if (GET_CODE (scanbody) == RETURN
11373 arm_ccfsm_state = 2;
11376 else if (GET_CODE (scanbody) == PARALLEL)
11378 switch (get_attr_conds (this_insn))
11388 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11393 /* Instructions using or affecting the condition codes make it
11395 scanbody = PATTERN (this_insn);
11396 if (!(GET_CODE (scanbody) == SET
11397 || GET_CODE (scanbody) == PARALLEL)
11398 || get_attr_conds (this_insn) != CONDS_NOCOND)
11401 /* A conditional cirrus instruction must be followed by
11402 a non Cirrus instruction. However, since we
11403 conditionalize instructions in this function and by
11404 the time we get here we can't add instructions
11405 (nops), because shorten_branches() has already been
11406 called, we will disable conditionalizing Cirrus
11407 instructions to be safe. */
11408 if (GET_CODE (scanbody) != USE
11409 && GET_CODE (scanbody) != CLOBBER
11410 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11420 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11421 arm_target_label = CODE_LABEL_NUMBER (label);
11424 gcc_assert (seeking_return || arm_ccfsm_state == 2);
11426 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11428 this_insn = next_nonnote_insn (this_insn);
11429 gcc_assert (!this_insn
11430 || (GET_CODE (this_insn) != BARRIER
11431 && GET_CODE (this_insn) != CODE_LABEL));
11435 /* Oh, dear! we ran off the end.. give up. */
11436 recog (PATTERN (insn), insn, NULL);
11437 arm_ccfsm_state = 0;
11438 arm_target_insn = NULL;
11441 arm_target_insn = this_insn;
11445 gcc_assert (!reverse);
11447 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11449 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11450 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11451 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11452 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11456 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11459 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11463 if (reverse || then_not_else)
11464 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11467 /* Restore recog_data (getting the attributes of other insns can
11468 destroy this array, but final.c assumes that it remains intact
11469 across this call; since the insn has been recognized already we
11470 call recog direct). */
11471 recog (PATTERN (insn), insn, NULL);
11475 /* Returns true if REGNO is a valid register
11476 for holding a quantity of type MODE. */
11478 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11480 if (GET_MODE_CLASS (mode) == MODE_CC)
11481 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11484 /* For the Thumb we only allow values bigger than SImode in
11485 registers 0 - 6, so that there is always a second low
11486 register available to hold the upper part of the value.
11487 We probably we ought to ensure that the register is the
11488 start of an even numbered register pair. */
11489 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11491 if (IS_CIRRUS_REGNUM (regno))
11492 /* We have outlawed SI values in Cirrus registers because they
11493 reside in the lower 32 bits, but SF values reside in the
11494 upper 32 bits. This causes gcc all sorts of grief. We can't
11495 even split the registers into pairs because Cirrus SI values
11496 get sign extended to 64bits-- aldyh. */
11497 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11499 if (IS_VFP_REGNUM (regno))
11501 if (mode == SFmode || mode == SImode)
11504 /* DFmode values are only valid in even register pairs. */
11505 if (mode == DFmode)
11506 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11510 if (IS_IWMMXT_GR_REGNUM (regno))
11511 return mode == SImode;
11513 if (IS_IWMMXT_REGNUM (regno))
11514 return VALID_IWMMXT_REG_MODE (mode);
11516 /* We allow any value to be stored in the general registers.
11517 Restrict doubleword quantities to even register pairs so that we can
11519 if (regno <= LAST_ARM_REGNUM)
11520 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11522 if ( regno == FRAME_POINTER_REGNUM
11523 || regno == ARG_POINTER_REGNUM)
11524 /* We only allow integers in the fake hard registers. */
11525 return GET_MODE_CLASS (mode) == MODE_INT;
11527 /* The only registers left are the FPA registers
11528 which we only allow to hold FP values. */
11529 return GET_MODE_CLASS (mode) == MODE_FLOAT
11530 && regno >= FIRST_FPA_REGNUM
11531 && regno <= LAST_FPA_REGNUM;
11535 arm_regno_class (int regno)
11539 if (regno == STACK_POINTER_REGNUM)
11541 if (regno == CC_REGNUM)
11548 if ( regno <= LAST_ARM_REGNUM
11549 || regno == FRAME_POINTER_REGNUM
11550 || regno == ARG_POINTER_REGNUM)
11551 return GENERAL_REGS;
11553 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11556 if (IS_CIRRUS_REGNUM (regno))
11557 return CIRRUS_REGS;
11559 if (IS_VFP_REGNUM (regno))
11562 if (IS_IWMMXT_REGNUM (regno))
11563 return IWMMXT_REGS;
11565 if (IS_IWMMXT_GR_REGNUM (regno))
11566 return IWMMXT_GR_REGS;
11571 /* Handle a special case when computing the offset
11572 of an argument from the frame pointer. */
11574 arm_debugger_arg_offset (int value, rtx addr)
11578 /* We are only interested if dbxout_parms() failed to compute the offset. */
11582 /* We can only cope with the case where the address is held in a register. */
11583 if (GET_CODE (addr) != REG)
11586 /* If we are using the frame pointer to point at the argument, then
11587 an offset of 0 is correct. */
11588 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11591 /* If we are using the stack pointer to point at the
11592 argument, then an offset of 0 is correct. */
11593 if ((TARGET_THUMB || !frame_pointer_needed)
11594 && REGNO (addr) == SP_REGNUM)
11597 /* Oh dear. The argument is pointed to by a register rather
11598 than being held in a register, or being stored at a known
11599 offset from the frame pointer. Since GDB only understands
11600 those two kinds of argument we must translate the address
11601 held in the register into an offset from the frame pointer.
11602 We do this by searching through the insns for the function
11603 looking to see where this register gets its value. If the
11604 register is initialized from the frame pointer plus an offset
11605 then we are in luck and we can continue, otherwise we give up.
11607 This code is exercised by producing debugging information
11608 for a function with arguments like this:
11610 double func (double a, double b, int c, double d) {return d;}
11612 Without this code the stab for parameter 'd' will be set to
11613 an offset of 0 from the frame pointer, rather than 8. */
11615 /* The if() statement says:
11617 If the insn is a normal instruction
11618 and if the insn is setting the value in a register
11619 and if the register being set is the register holding the address of the argument
11620 and if the address is computing by an addition
11621 that involves adding to a register
11622 which is the frame pointer
11627 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11629 if ( GET_CODE (insn) == INSN
11630 && GET_CODE (PATTERN (insn)) == SET
11631 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11632 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11633 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11634 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11635 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11638 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11647 warning (0, "unable to compute real location of stacked parameter");
11648 value = 8; /* XXX magic hack */
11654 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11657 if ((MASK) & insn_flags) \
11658 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11659 BUILT_IN_MD, NULL, NULL_TREE); \
11663 struct builtin_description
11665 const unsigned int mask;
11666 const enum insn_code icode;
11667 const char * const name;
11668 const enum arm_builtins code;
11669 const enum rtx_code comparison;
11670 const unsigned int flag;
11673 static const struct builtin_description bdesc_2arg[] =
11675 #define IWMMXT_BUILTIN(code, string, builtin) \
11676 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11677 ARM_BUILTIN_##builtin, 0, 0 },
11679 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11680 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11681 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11682 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11683 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11684 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11685 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11686 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11687 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11688 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11689 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11690 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11691 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11692 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11693 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11694 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11695 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11696 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11697 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11698 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11699 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11700 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11701 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11702 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11703 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11704 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11705 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11706 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11707 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11708 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11709 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11710 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11711 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11712 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11713 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11714 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11715 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11716 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11717 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11718 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11719 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11720 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11721 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11722 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11723 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11724 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11725 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11726 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11727 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11728 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11729 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11730 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11731 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11732 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11733 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11734 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11735 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11736 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11738 #define IWMMXT_BUILTIN2(code, builtin) \
11739 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11741 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11742 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11743 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11744 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11745 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11746 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11747 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11748 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11749 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11750 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11751 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11752 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11753 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11754 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11755 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11756 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11757 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11758 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11759 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11760 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11761 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11762 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11763 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11764 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11765 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11766 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11767 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11768 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11769 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11770 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11771 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11772 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11775 static const struct builtin_description bdesc_1arg[] =
11777 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11778 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11779 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11780 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11781 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11782 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11783 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11784 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11785 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11786 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11787 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11788 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11789 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11790 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11791 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11792 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11793 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11794 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11797 /* Set up all the iWMMXt builtins. This is
11798 not called if TARGET_IWMMXT is zero. */
11801 arm_init_iwmmxt_builtins (void)
11803 const struct builtin_description * d;
11805 tree endlink = void_list_node;
11807 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11808 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11809 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11812 = build_function_type (integer_type_node,
11813 tree_cons (NULL_TREE, integer_type_node, endlink));
11814 tree v8qi_ftype_v8qi_v8qi_int
11815 = build_function_type (V8QI_type_node,
11816 tree_cons (NULL_TREE, V8QI_type_node,
11817 tree_cons (NULL_TREE, V8QI_type_node,
11818 tree_cons (NULL_TREE,
11821 tree v4hi_ftype_v4hi_int
11822 = build_function_type (V4HI_type_node,
11823 tree_cons (NULL_TREE, V4HI_type_node,
11824 tree_cons (NULL_TREE, integer_type_node,
11826 tree v2si_ftype_v2si_int
11827 = build_function_type (V2SI_type_node,
11828 tree_cons (NULL_TREE, V2SI_type_node,
11829 tree_cons (NULL_TREE, integer_type_node,
11831 tree v2si_ftype_di_di
11832 = build_function_type (V2SI_type_node,
11833 tree_cons (NULL_TREE, long_long_integer_type_node,
11834 tree_cons (NULL_TREE, long_long_integer_type_node,
11836 tree di_ftype_di_int
11837 = build_function_type (long_long_integer_type_node,
11838 tree_cons (NULL_TREE, long_long_integer_type_node,
11839 tree_cons (NULL_TREE, integer_type_node,
11841 tree di_ftype_di_int_int
11842 = build_function_type (long_long_integer_type_node,
11843 tree_cons (NULL_TREE, long_long_integer_type_node,
11844 tree_cons (NULL_TREE, integer_type_node,
11845 tree_cons (NULL_TREE,
11848 tree int_ftype_v8qi
11849 = build_function_type (integer_type_node,
11850 tree_cons (NULL_TREE, V8QI_type_node,
11852 tree int_ftype_v4hi
11853 = build_function_type (integer_type_node,
11854 tree_cons (NULL_TREE, V4HI_type_node,
11856 tree int_ftype_v2si
11857 = build_function_type (integer_type_node,
11858 tree_cons (NULL_TREE, V2SI_type_node,
11860 tree int_ftype_v8qi_int
11861 = build_function_type (integer_type_node,
11862 tree_cons (NULL_TREE, V8QI_type_node,
11863 tree_cons (NULL_TREE, integer_type_node,
11865 tree int_ftype_v4hi_int
11866 = build_function_type (integer_type_node,
11867 tree_cons (NULL_TREE, V4HI_type_node,
11868 tree_cons (NULL_TREE, integer_type_node,
11870 tree int_ftype_v2si_int
11871 = build_function_type (integer_type_node,
11872 tree_cons (NULL_TREE, V2SI_type_node,
11873 tree_cons (NULL_TREE, integer_type_node,
11875 tree v8qi_ftype_v8qi_int_int
11876 = build_function_type (V8QI_type_node,
11877 tree_cons (NULL_TREE, V8QI_type_node,
11878 tree_cons (NULL_TREE, integer_type_node,
11879 tree_cons (NULL_TREE,
11882 tree v4hi_ftype_v4hi_int_int
11883 = build_function_type (V4HI_type_node,
11884 tree_cons (NULL_TREE, V4HI_type_node,
11885 tree_cons (NULL_TREE, integer_type_node,
11886 tree_cons (NULL_TREE,
11889 tree v2si_ftype_v2si_int_int
11890 = build_function_type (V2SI_type_node,
11891 tree_cons (NULL_TREE, V2SI_type_node,
11892 tree_cons (NULL_TREE, integer_type_node,
11893 tree_cons (NULL_TREE,
11896 /* Miscellaneous. */
11897 tree v8qi_ftype_v4hi_v4hi
11898 = build_function_type (V8QI_type_node,
11899 tree_cons (NULL_TREE, V4HI_type_node,
11900 tree_cons (NULL_TREE, V4HI_type_node,
11902 tree v4hi_ftype_v2si_v2si
11903 = build_function_type (V4HI_type_node,
11904 tree_cons (NULL_TREE, V2SI_type_node,
11905 tree_cons (NULL_TREE, V2SI_type_node,
11907 tree v2si_ftype_v4hi_v4hi
11908 = build_function_type (V2SI_type_node,
11909 tree_cons (NULL_TREE, V4HI_type_node,
11910 tree_cons (NULL_TREE, V4HI_type_node,
11912 tree v2si_ftype_v8qi_v8qi
11913 = build_function_type (V2SI_type_node,
11914 tree_cons (NULL_TREE, V8QI_type_node,
11915 tree_cons (NULL_TREE, V8QI_type_node,
11917 tree v4hi_ftype_v4hi_di
11918 = build_function_type (V4HI_type_node,
11919 tree_cons (NULL_TREE, V4HI_type_node,
11920 tree_cons (NULL_TREE,
11921 long_long_integer_type_node,
11923 tree v2si_ftype_v2si_di
11924 = build_function_type (V2SI_type_node,
11925 tree_cons (NULL_TREE, V2SI_type_node,
11926 tree_cons (NULL_TREE,
11927 long_long_integer_type_node,
11929 tree void_ftype_int_int
11930 = build_function_type (void_type_node,
11931 tree_cons (NULL_TREE, integer_type_node,
11932 tree_cons (NULL_TREE, integer_type_node,
11935 = build_function_type (long_long_unsigned_type_node, endlink);
11937 = build_function_type (long_long_integer_type_node,
11938 tree_cons (NULL_TREE, V8QI_type_node,
11941 = build_function_type (long_long_integer_type_node,
11942 tree_cons (NULL_TREE, V4HI_type_node,
11945 = build_function_type (long_long_integer_type_node,
11946 tree_cons (NULL_TREE, V2SI_type_node,
11948 tree v2si_ftype_v4hi
11949 = build_function_type (V2SI_type_node,
11950 tree_cons (NULL_TREE, V4HI_type_node,
11952 tree v4hi_ftype_v8qi
11953 = build_function_type (V4HI_type_node,
11954 tree_cons (NULL_TREE, V8QI_type_node,
11957 tree di_ftype_di_v4hi_v4hi
11958 = build_function_type (long_long_unsigned_type_node,
11959 tree_cons (NULL_TREE,
11960 long_long_unsigned_type_node,
11961 tree_cons (NULL_TREE, V4HI_type_node,
11962 tree_cons (NULL_TREE,
11966 tree di_ftype_v4hi_v4hi
11967 = build_function_type (long_long_unsigned_type_node,
11968 tree_cons (NULL_TREE, V4HI_type_node,
11969 tree_cons (NULL_TREE, V4HI_type_node,
11972 /* Normal vector binops. */
11973 tree v8qi_ftype_v8qi_v8qi
11974 = build_function_type (V8QI_type_node,
11975 tree_cons (NULL_TREE, V8QI_type_node,
11976 tree_cons (NULL_TREE, V8QI_type_node,
11978 tree v4hi_ftype_v4hi_v4hi
11979 = build_function_type (V4HI_type_node,
11980 tree_cons (NULL_TREE, V4HI_type_node,
11981 tree_cons (NULL_TREE, V4HI_type_node,
11983 tree v2si_ftype_v2si_v2si
11984 = build_function_type (V2SI_type_node,
11985 tree_cons (NULL_TREE, V2SI_type_node,
11986 tree_cons (NULL_TREE, V2SI_type_node,
11988 tree di_ftype_di_di
11989 = build_function_type (long_long_unsigned_type_node,
11990 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11991 tree_cons (NULL_TREE,
11992 long_long_unsigned_type_node,
11995 /* Add all builtins that are more or less simple operations on two
11997 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11999 /* Use one of the operands; the target can have a different mode for
12000 mask-generating compares. */
12001 enum machine_mode mode;
12007 mode = insn_data[d->icode].operand[1].mode;
12012 type = v8qi_ftype_v8qi_v8qi;
12015 type = v4hi_ftype_v4hi_v4hi;
12018 type = v2si_ftype_v2si_v2si;
12021 type = di_ftype_di_di;
12025 gcc_unreachable ();
12028 def_mbuiltin (d->mask, d->name, type, d->code);
12031 /* Add the remaining MMX insns with somewhat more complicated types. */
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12040 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12057 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12061 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12064 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12066 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12067 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12068 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12069 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12071 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12072 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12073 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12074 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12075 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12076 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12077 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12078 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12079 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12081 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12082 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12083 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12085 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12086 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12087 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12089 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12090 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12091 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12092 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12093 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12094 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12096 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12097 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12098 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12099 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12100 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12101 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12102 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12103 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12104 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12105 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12106 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12107 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12109 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12110 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12111 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12112 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12114 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12115 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12116 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12117 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12118 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12119 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12120 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12124 arm_init_builtins (void)
12126 if (TARGET_REALLY_IWMMXT)
12127 arm_init_iwmmxt_builtins ();
12130 /* Errors in the source file can cause expand_expr to return const0_rtx
12131 where we expect a vector. To avoid crashing, use one of the vector
12132 clear instructions. */
12135 safe_vector_operand (rtx x, enum machine_mode mode)
12137 if (x != const0_rtx)
12139 x = gen_reg_rtx (mode);
12141 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12142 : gen_rtx_SUBREG (DImode, x, 0)));
12146 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12149 arm_expand_binop_builtin (enum insn_code icode,
12150 tree arglist, rtx target)
12153 tree arg0 = TREE_VALUE (arglist);
12154 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12155 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12156 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12157 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12158 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12159 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12161 if (VECTOR_MODE_P (mode0))
12162 op0 = safe_vector_operand (op0, mode0);
12163 if (VECTOR_MODE_P (mode1))
12164 op1 = safe_vector_operand (op1, mode1);
12167 || GET_MODE (target) != tmode
12168 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12169 target = gen_reg_rtx (tmode);
12171 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
12173 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12174 op0 = copy_to_mode_reg (mode0, op0);
12175 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12176 op1 = copy_to_mode_reg (mode1, op1);
12178 pat = GEN_FCN (icode) (target, op0, op1);
12185 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12188 arm_expand_unop_builtin (enum insn_code icode,
12189 tree arglist, rtx target, int do_load)
12192 tree arg0 = TREE_VALUE (arglist);
12193 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12194 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12195 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12198 || GET_MODE (target) != tmode
12199 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12200 target = gen_reg_rtx (tmode);
12202 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12205 if (VECTOR_MODE_P (mode0))
12206 op0 = safe_vector_operand (op0, mode0);
12208 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12209 op0 = copy_to_mode_reg (mode0, op0);
12212 pat = GEN_FCN (icode) (target, op0);
12219 /* Expand an expression EXP that calls a built-in function,
12220 with result going to TARGET if that's convenient
12221 (and in mode MODE if that's convenient).
12222 SUBTARGET may be used as the target for computing one of EXP's operands.
12223 IGNORE is nonzero if the value is to be ignored. */
12226 arm_expand_builtin (tree exp,
12228 rtx subtarget ATTRIBUTE_UNUSED,
12229 enum machine_mode mode ATTRIBUTE_UNUSED,
12230 int ignore ATTRIBUTE_UNUSED)
12232 const struct builtin_description * d;
12233 enum insn_code icode;
12234 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12235 tree arglist = TREE_OPERAND (exp, 1);
12243 int fcode = DECL_FUNCTION_CODE (fndecl);
12245 enum machine_mode tmode;
12246 enum machine_mode mode0;
12247 enum machine_mode mode1;
12248 enum machine_mode mode2;
12252 case ARM_BUILTIN_TEXTRMSB:
12253 case ARM_BUILTIN_TEXTRMUB:
12254 case ARM_BUILTIN_TEXTRMSH:
12255 case ARM_BUILTIN_TEXTRMUH:
12256 case ARM_BUILTIN_TEXTRMSW:
12257 case ARM_BUILTIN_TEXTRMUW:
12258 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12259 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12260 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12261 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12262 : CODE_FOR_iwmmxt_textrmw);
12264 arg0 = TREE_VALUE (arglist);
12265 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12266 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12267 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12268 tmode = insn_data[icode].operand[0].mode;
12269 mode0 = insn_data[icode].operand[1].mode;
12270 mode1 = insn_data[icode].operand[2].mode;
12272 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12273 op0 = copy_to_mode_reg (mode0, op0);
12274 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12276 /* @@@ better error message */
12277 error ("selector must be an immediate");
12278 return gen_reg_rtx (tmode);
12281 || GET_MODE (target) != tmode
12282 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12283 target = gen_reg_rtx (tmode);
12284 pat = GEN_FCN (icode) (target, op0, op1);
12290 case ARM_BUILTIN_TINSRB:
12291 case ARM_BUILTIN_TINSRH:
12292 case ARM_BUILTIN_TINSRW:
12293 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12294 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12295 : CODE_FOR_iwmmxt_tinsrw);
12296 arg0 = TREE_VALUE (arglist);
12297 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12298 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12299 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12300 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12301 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12302 tmode = insn_data[icode].operand[0].mode;
12303 mode0 = insn_data[icode].operand[1].mode;
12304 mode1 = insn_data[icode].operand[2].mode;
12305 mode2 = insn_data[icode].operand[3].mode;
12307 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12308 op0 = copy_to_mode_reg (mode0, op0);
12309 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12310 op1 = copy_to_mode_reg (mode1, op1);
12311 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12313 /* @@@ better error message */
12314 error ("selector must be an immediate");
12318 || GET_MODE (target) != tmode
12319 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12320 target = gen_reg_rtx (tmode);
12321 pat = GEN_FCN (icode) (target, op0, op1, op2);
12327 case ARM_BUILTIN_SETWCX:
12328 arg0 = TREE_VALUE (arglist);
12329 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12330 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12331 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12332 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12335 case ARM_BUILTIN_GETWCX:
12336 arg0 = TREE_VALUE (arglist);
12337 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12338 target = gen_reg_rtx (SImode);
12339 emit_insn (gen_iwmmxt_tmrc (target, op0));
12342 case ARM_BUILTIN_WSHUFH:
12343 icode = CODE_FOR_iwmmxt_wshufh;
12344 arg0 = TREE_VALUE (arglist);
12345 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12346 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12347 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12348 tmode = insn_data[icode].operand[0].mode;
12349 mode1 = insn_data[icode].operand[1].mode;
12350 mode2 = insn_data[icode].operand[2].mode;
12352 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12353 op0 = copy_to_mode_reg (mode1, op0);
12354 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12356 /* @@@ better error message */
12357 error ("mask must be an immediate");
12361 || GET_MODE (target) != tmode
12362 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12363 target = gen_reg_rtx (tmode);
12364 pat = GEN_FCN (icode) (target, op0, op1);
12370 case ARM_BUILTIN_WSADB:
12371 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12372 case ARM_BUILTIN_WSADH:
12373 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12374 case ARM_BUILTIN_WSADBZ:
12375 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12376 case ARM_BUILTIN_WSADHZ:
12377 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12379 /* Several three-argument builtins. */
12380 case ARM_BUILTIN_WMACS:
12381 case ARM_BUILTIN_WMACU:
12382 case ARM_BUILTIN_WALIGN:
12383 case ARM_BUILTIN_TMIA:
12384 case ARM_BUILTIN_TMIAPH:
12385 case ARM_BUILTIN_TMIATT:
12386 case ARM_BUILTIN_TMIATB:
12387 case ARM_BUILTIN_TMIABT:
12388 case ARM_BUILTIN_TMIABB:
12389 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12390 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12391 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12392 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12393 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12394 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12395 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12396 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12397 : CODE_FOR_iwmmxt_walign);
12398 arg0 = TREE_VALUE (arglist);
12399 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12400 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12401 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12402 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12403 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12404 tmode = insn_data[icode].operand[0].mode;
12405 mode0 = insn_data[icode].operand[1].mode;
12406 mode1 = insn_data[icode].operand[2].mode;
12407 mode2 = insn_data[icode].operand[3].mode;
12409 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12410 op0 = copy_to_mode_reg (mode0, op0);
12411 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12412 op1 = copy_to_mode_reg (mode1, op1);
12413 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12414 op2 = copy_to_mode_reg (mode2, op2);
12416 || GET_MODE (target) != tmode
12417 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12418 target = gen_reg_rtx (tmode);
12419 pat = GEN_FCN (icode) (target, op0, op1, op2);
12425 case ARM_BUILTIN_WZERO:
12426 target = gen_reg_rtx (DImode);
12427 emit_insn (gen_iwmmxt_clrdi (target));
12434 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12435 if (d->code == (const enum arm_builtins) fcode)
12436 return arm_expand_binop_builtin (d->icode, arglist, target);
12438 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12439 if (d->code == (const enum arm_builtins) fcode)
12440 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12442 /* @@@ Should really do something sensible here. */
12446 /* Return the number (counting from 0) of
12447 the least significant set bit in MASK. */
12450 number_of_first_bit_set (unsigned mask)
12455 (mask & (1 << bit)) == 0;
12462 /* Emit code to push or pop registers to or from the stack. F is the
12463 assembly file. MASK is the registers to push or pop. PUSH is
12464 nonzero if we should push, and zero if we should pop. For debugging
12465 output, if pushing, adjust CFA_OFFSET by the amount of space added
12466 to the stack. REAL_REGS should have the same number of bits set as
12467 MASK, and will be used instead (in the same order) to describe which
12468 registers were saved - this is used to mark the save slots when we
12469 push high registers after moving them to low registers. */
12471 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
12472 unsigned long real_regs)
12475 int lo_mask = mask & 0xFF;
12476 int pushed_words = 0;
12480 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12482 /* Special case. Do not generate a POP PC statement here, do it in
12484 thumb_exit (f, -1);
12488 if (ARM_EABI_UNWIND_TABLES && push)
12490 fprintf (f, "\t.save\t{");
12491 for (regno = 0; regno < 15; regno++)
12493 if (real_regs & (1 << regno))
12495 if (real_regs & ((1 << regno) -1))
12497 asm_fprintf (f, "%r", regno);
12500 fprintf (f, "}\n");
12503 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12505 /* Look at the low registers first. */
12506 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12510 asm_fprintf (f, "%r", regno);
12512 if ((lo_mask & ~1) != 0)
12519 if (push && (mask & (1 << LR_REGNUM)))
12521 /* Catch pushing the LR. */
12525 asm_fprintf (f, "%r", LR_REGNUM);
12529 else if (!push && (mask & (1 << PC_REGNUM)))
12531 /* Catch popping the PC. */
12532 if (TARGET_INTERWORK || TARGET_BACKTRACE
12533 || current_function_calls_eh_return)
12535 /* The PC is never poped directly, instead
12536 it is popped into r3 and then BX is used. */
12537 fprintf (f, "}\n");
12539 thumb_exit (f, -1);
12548 asm_fprintf (f, "%r", PC_REGNUM);
12552 fprintf (f, "}\n");
12554 if (push && pushed_words && dwarf2out_do_frame ())
12556 char *l = dwarf2out_cfi_label ();
12557 int pushed_mask = real_regs;
12559 *cfa_offset += pushed_words * 4;
12560 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12563 pushed_mask = real_regs;
12564 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12566 if (pushed_mask & 1)
12567 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12572 /* Generate code to return from a thumb function.
12573 If 'reg_containing_return_addr' is -1, then the return address is
12574 actually on the stack, at the stack pointer. */
12576 thumb_exit (FILE *f, int reg_containing_return_addr)
12578 unsigned regs_available_for_popping;
12579 unsigned regs_to_pop;
12581 unsigned available;
12585 int restore_a4 = FALSE;
12587 /* Compute the registers we need to pop. */
12591 if (reg_containing_return_addr == -1)
12593 regs_to_pop |= 1 << LR_REGNUM;
12597 if (TARGET_BACKTRACE)
12599 /* Restore the (ARM) frame pointer and stack pointer. */
12600 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12604 /* If there is nothing to pop then just emit the BX instruction and
12606 if (pops_needed == 0)
12608 if (current_function_calls_eh_return)
12609 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12611 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12614 /* Otherwise if we are not supporting interworking and we have not created
12615 a backtrace structure and the function was not entered in ARM mode then
12616 just pop the return address straight into the PC. */
12617 else if (!TARGET_INTERWORK
12618 && !TARGET_BACKTRACE
12619 && !is_called_in_ARM_mode (current_function_decl)
12620 && !current_function_calls_eh_return)
12622 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12626 /* Find out how many of the (return) argument registers we can corrupt. */
12627 regs_available_for_popping = 0;
12629 /* If returning via __builtin_eh_return, the bottom three registers
12630 all contain information needed for the return. */
12631 if (current_function_calls_eh_return)
12635 /* If we can deduce the registers used from the function's
12636 return value. This is more reliable that examining
12637 regs_ever_live[] because that will be set if the register is
12638 ever used in the function, not just if the register is used
12639 to hold a return value. */
12641 if (current_function_return_rtx != 0)
12642 mode = GET_MODE (current_function_return_rtx);
12644 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12646 size = GET_MODE_SIZE (mode);
12650 /* In a void function we can use any argument register.
12651 In a function that returns a structure on the stack
12652 we can use the second and third argument registers. */
12653 if (mode == VOIDmode)
12654 regs_available_for_popping =
12655 (1 << ARG_REGISTER (1))
12656 | (1 << ARG_REGISTER (2))
12657 | (1 << ARG_REGISTER (3));
12659 regs_available_for_popping =
12660 (1 << ARG_REGISTER (2))
12661 | (1 << ARG_REGISTER (3));
12663 else if (size <= 4)
12664 regs_available_for_popping =
12665 (1 << ARG_REGISTER (2))
12666 | (1 << ARG_REGISTER (3));
12667 else if (size <= 8)
12668 regs_available_for_popping =
12669 (1 << ARG_REGISTER (3));
12672 /* Match registers to be popped with registers into which we pop them. */
12673 for (available = regs_available_for_popping,
12674 required = regs_to_pop;
12675 required != 0 && available != 0;
12676 available &= ~(available & - available),
12677 required &= ~(required & - required))
12680 /* If we have any popping registers left over, remove them. */
12682 regs_available_for_popping &= ~available;
12684 /* Otherwise if we need another popping register we can use
12685 the fourth argument register. */
12686 else if (pops_needed)
12688 /* If we have not found any free argument registers and
12689 reg a4 contains the return address, we must move it. */
12690 if (regs_available_for_popping == 0
12691 && reg_containing_return_addr == LAST_ARG_REGNUM)
12693 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12694 reg_containing_return_addr = LR_REGNUM;
12696 else if (size > 12)
12698 /* Register a4 is being used to hold part of the return value,
12699 but we have dire need of a free, low register. */
12702 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12705 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12707 /* The fourth argument register is available. */
12708 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12714 /* Pop as many registers as we can. */
12715 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12716 regs_available_for_popping);
12718 /* Process the registers we popped. */
12719 if (reg_containing_return_addr == -1)
12721 /* The return address was popped into the lowest numbered register. */
12722 regs_to_pop &= ~(1 << LR_REGNUM);
12724 reg_containing_return_addr =
12725 number_of_first_bit_set (regs_available_for_popping);
12727 /* Remove this register for the mask of available registers, so that
12728 the return address will not be corrupted by further pops. */
12729 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12732 /* If we popped other registers then handle them here. */
12733 if (regs_available_for_popping)
12737 /* Work out which register currently contains the frame pointer. */
12738 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12740 /* Move it into the correct place. */
12741 asm_fprintf (f, "\tmov\t%r, %r\n",
12742 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12744 /* (Temporarily) remove it from the mask of popped registers. */
12745 regs_available_for_popping &= ~(1 << frame_pointer);
12746 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12748 if (regs_available_for_popping)
12752 /* We popped the stack pointer as well,
12753 find the register that contains it. */
12754 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12756 /* Move it into the stack register. */
12757 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12759 /* At this point we have popped all necessary registers, so
12760 do not worry about restoring regs_available_for_popping
12761 to its correct value:
12763 assert (pops_needed == 0)
12764 assert (regs_available_for_popping == (1 << frame_pointer))
12765 assert (regs_to_pop == (1 << STACK_POINTER)) */
12769 /* Since we have just move the popped value into the frame
12770 pointer, the popping register is available for reuse, and
12771 we know that we still have the stack pointer left to pop. */
12772 regs_available_for_popping |= (1 << frame_pointer);
12776 /* If we still have registers left on the stack, but we no longer have
12777 any registers into which we can pop them, then we must move the return
12778 address into the link register and make available the register that
12780 if (regs_available_for_popping == 0 && pops_needed > 0)
12782 regs_available_for_popping |= 1 << reg_containing_return_addr;
12784 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12785 reg_containing_return_addr);
12787 reg_containing_return_addr = LR_REGNUM;
12790 /* If we have registers left on the stack then pop some more.
12791 We know that at most we will want to pop FP and SP. */
12792 if (pops_needed > 0)
12797 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12798 regs_available_for_popping);
12800 /* We have popped either FP or SP.
12801 Move whichever one it is into the correct register. */
12802 popped_into = number_of_first_bit_set (regs_available_for_popping);
12803 move_to = number_of_first_bit_set (regs_to_pop);
12805 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12807 regs_to_pop &= ~(1 << move_to);
12812 /* If we still have not popped everything then we must have only
12813 had one register available to us and we are now popping the SP. */
12814 if (pops_needed > 0)
12818 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12819 regs_available_for_popping);
12821 popped_into = number_of_first_bit_set (regs_available_for_popping);
12823 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12825 assert (regs_to_pop == (1 << STACK_POINTER))
12826 assert (pops_needed == 1)
12830 /* If necessary restore the a4 register. */
12833 if (reg_containing_return_addr != LR_REGNUM)
12835 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12836 reg_containing_return_addr = LR_REGNUM;
12839 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12842 if (current_function_calls_eh_return)
12843 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12845 /* Return to caller. */
12846 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12851 thumb_final_prescan_insn (rtx insn)
12853 if (flag_print_asm_name)
12854 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12855 INSN_ADDRESSES (INSN_UID (insn)));
12859 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12861 unsigned HOST_WIDE_INT mask = 0xff;
12864 if (val == 0) /* XXX */
12867 for (i = 0; i < 25; i++)
12868 if ((val & (mask << i)) == val)
12874 /* Returns nonzero if the current function contains,
12875 or might contain a far jump. */
12877 thumb_far_jump_used_p (void)
12881 /* This test is only important for leaf functions. */
12882 /* assert (!leaf_function_p ()); */
12884 /* If we have already decided that far jumps may be used,
12885 do not bother checking again, and always return true even if
12886 it turns out that they are not being used. Once we have made
12887 the decision that far jumps are present (and that hence the link
12888 register will be pushed onto the stack) we cannot go back on it. */
12889 if (cfun->machine->far_jump_used)
12892 /* If this function is not being called from the prologue/epilogue
12893 generation code then it must be being called from the
12894 INITIAL_ELIMINATION_OFFSET macro. */
12895 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12897 /* In this case we know that we are being asked about the elimination
12898 of the arg pointer register. If that register is not being used,
12899 then there are no arguments on the stack, and we do not have to
12900 worry that a far jump might force the prologue to push the link
12901 register, changing the stack offsets. In this case we can just
12902 return false, since the presence of far jumps in the function will
12903 not affect stack offsets.
12905 If the arg pointer is live (or if it was live, but has now been
12906 eliminated and so set to dead) then we do have to test to see if
12907 the function might contain a far jump. This test can lead to some
12908 false negatives, since before reload is completed, then length of
12909 branch instructions is not known, so gcc defaults to returning their
12910 longest length, which in turn sets the far jump attribute to true.
12912 A false negative will not result in bad code being generated, but it
12913 will result in a needless push and pop of the link register. We
12914 hope that this does not occur too often.
12916 If we need doubleword stack alignment this could affect the other
12917 elimination offsets so we can't risk getting it wrong. */
12918 if (regs_ever_live [ARG_POINTER_REGNUM])
12919 cfun->machine->arg_pointer_live = 1;
12920 else if (!cfun->machine->arg_pointer_live)
12924 /* Check to see if the function contains a branch
12925 insn with the far jump attribute set. */
12926 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12928 if (GET_CODE (insn) == JUMP_INSN
12929 /* Ignore tablejump patterns. */
12930 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12931 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12932 && get_attr_far_jump (insn) == FAR_JUMP_YES
12935 /* Record the fact that we have decided that
12936 the function does use far jumps. */
12937 cfun->machine->far_jump_used = 1;
12945 /* Return nonzero if FUNC must be entered in ARM mode. */
12947 is_called_in_ARM_mode (tree func)
12949 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
12951 /* Ignore the problem about functions whose address is taken. */
12952 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12956 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12962 /* The bits which aren't usefully expanded as rtl. */
12964 thumb_unexpanded_epilogue (void)
12967 unsigned long live_regs_mask = 0;
12968 int high_regs_pushed = 0;
12969 int had_to_push_lr;
12972 if (return_used_this_function)
12975 if (IS_NAKED (arm_current_func_type ()))
12978 live_regs_mask = thumb_compute_save_reg_mask ();
12979 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
12981 /* If we can deduce the registers used from the function's return value.
12982 This is more reliable that examining regs_ever_live[] because that
12983 will be set if the register is ever used in the function, not just if
12984 the register is used to hold a return value. */
12985 size = arm_size_return_regs ();
12987 /* The prolog may have pushed some high registers to use as
12988 work registers. e.g. the testsuite file:
12989 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12990 compiles to produce:
12991 push {r4, r5, r6, r7, lr}
12995 as part of the prolog. We have to undo that pushing here. */
12997 if (high_regs_pushed)
12999 unsigned long mask = live_regs_mask & 0xff;
13002 /* The available low registers depend on the size of the value we are
13010 /* Oh dear! We have no low registers into which we can pop
13013 ("no low registers available for popping high registers");
13015 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13016 if (live_regs_mask & (1 << next_hi_reg))
13019 while (high_regs_pushed)
13021 /* Find lo register(s) into which the high register(s) can
13023 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13025 if (mask & (1 << regno))
13026 high_regs_pushed--;
13027 if (high_regs_pushed == 0)
13031 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13033 /* Pop the values into the low register(s). */
13034 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13036 /* Move the value(s) into the high registers. */
13037 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13039 if (mask & (1 << regno))
13041 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13044 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13045 if (live_regs_mask & (1 << next_hi_reg))
13050 live_regs_mask &= ~0x0f00;
13053 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13054 live_regs_mask &= 0xff;
13056 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13058 /* Pop the return address into the PC. */
13059 if (had_to_push_lr)
13060 live_regs_mask |= 1 << PC_REGNUM;
13062 /* Either no argument registers were pushed or a backtrace
13063 structure was created which includes an adjusted stack
13064 pointer, so just pop everything. */
13065 if (live_regs_mask)
13066 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13069 /* We have either just popped the return address into the
13070 PC or it is was kept in LR for the entire function. */
13071 if (!had_to_push_lr)
13072 thumb_exit (asm_out_file, LR_REGNUM);
13076 /* Pop everything but the return address. */
13077 if (live_regs_mask)
13078 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13081 if (had_to_push_lr)
13085 /* We have no free low regs, so save one. */
13086 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13090 /* Get the return address into a temporary register. */
13091 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13092 1 << LAST_ARG_REGNUM);
13096 /* Move the return address to lr. */
13097 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13099 /* Restore the low register. */
13100 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13105 regno = LAST_ARG_REGNUM;
13110 /* Remove the argument registers that were pushed onto the stack. */
13111 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13112 SP_REGNUM, SP_REGNUM,
13113 current_function_pretend_args_size);
13115 thumb_exit (asm_out_file, regno);
13121 /* Functions to save and restore machine-specific function data. */
13122 static struct machine_function *
13123 arm_init_machine_status (void)
13125 struct machine_function *machine;
13126 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13128 #if ARM_FT_UNKNOWN != 0
13129 machine->func_type = ARM_FT_UNKNOWN;
13134 /* Return an RTX indicating where the return address to the
13135 calling function can be found. */
13137 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13142 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13145 /* Do anything needed before RTL is emitted for each function. */
13147 arm_init_expanders (void)
13149 /* Arrange to initialize and mark the machine per-function status. */
13150 init_machine_status = arm_init_machine_status;
13152 /* This is to stop the combine pass optimizing away the alignment
13153 adjustment of va_arg. */
13154 /* ??? It is claimed that this should not be necessary. */
13156 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13160 /* Like arm_compute_initial_elimination offset. Simpler because
13161 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13164 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13166 arm_stack_offsets *offsets;
13168 offsets = arm_get_frame_offsets ();
13172 case ARG_POINTER_REGNUM:
13175 case STACK_POINTER_REGNUM:
13176 return offsets->outgoing_args - offsets->saved_args;
13178 case FRAME_POINTER_REGNUM:
13179 return offsets->soft_frame - offsets->saved_args;
13181 case THUMB_HARD_FRAME_POINTER_REGNUM:
13182 case ARM_HARD_FRAME_POINTER_REGNUM:
13183 return offsets->saved_regs - offsets->saved_args;
13186 gcc_unreachable ();
13190 case FRAME_POINTER_REGNUM:
13193 case STACK_POINTER_REGNUM:
13194 return offsets->outgoing_args - offsets->soft_frame;
13196 case THUMB_HARD_FRAME_POINTER_REGNUM:
13197 case ARM_HARD_FRAME_POINTER_REGNUM:
13198 return offsets->saved_regs - offsets->soft_frame;
13201 gcc_unreachable ();
13206 gcc_unreachable ();
13211 /* Generate the rest of a function's prologue. */
13213 thumb_expand_prologue (void)
13217 HOST_WIDE_INT amount;
13218 arm_stack_offsets *offsets;
13219 unsigned long func_type;
13221 unsigned long live_regs_mask;
13223 func_type = arm_current_func_type ();
13225 /* Naked functions don't have prologues. */
13226 if (IS_NAKED (func_type))
13229 if (IS_INTERRUPT (func_type))
13231 error ("interrupt Service Routines cannot be coded in Thumb mode");
13235 live_regs_mask = thumb_compute_save_reg_mask ();
13236 /* Load the pic register before setting the frame pointer,
13237 so we can use r7 as a temporary work register. */
13239 arm_load_pic_register (thumb_find_work_register (live_regs_mask));
13241 offsets = arm_get_frame_offsets ();
13243 if (frame_pointer_needed)
13245 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13246 stack_pointer_rtx));
13247 RTX_FRAME_RELATED_P (insn) = 1;
13249 else if (CALLER_INTERWORKING_SLOT_SIZE > 0)
13250 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13251 stack_pointer_rtx);
13253 amount = offsets->outgoing_args - offsets->saved_regs;
13258 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13259 GEN_INT (- amount)));
13260 RTX_FRAME_RELATED_P (insn) = 1;
13266 /* The stack decrement is too big for an immediate value in a single
13267 insn. In theory we could issue multiple subtracts, but after
13268 three of them it becomes more space efficient to place the full
13269 value in the constant pool and load into a register. (Also the
13270 ARM debugger really likes to see only one stack decrement per
13271 function). So instead we look for a scratch register into which
13272 we can load the decrement, and then we subtract this from the
13273 stack pointer. Unfortunately on the thumb the only available
13274 scratch registers are the argument registers, and we cannot use
13275 these as they may hold arguments to the function. Instead we
13276 attempt to locate a call preserved register which is used by this
13277 function. If we can find one, then we know that it will have
13278 been pushed at the start of the prologue and so we can corrupt
13280 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13281 if (live_regs_mask & (1 << regno)
13282 && !(frame_pointer_needed
13283 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13286 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13288 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13290 /* Choose an arbitrary, non-argument low register. */
13291 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13293 /* Save it by copying it into a high, scratch register. */
13294 emit_insn (gen_movsi (spare, reg));
13295 /* Add a USE to stop propagate_one_insn() from barfing. */
13296 emit_insn (gen_prologue_use (spare));
13298 /* Decrement the stack. */
13299 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13300 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13301 stack_pointer_rtx, reg));
13302 RTX_FRAME_RELATED_P (insn) = 1;
13303 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13304 plus_constant (stack_pointer_rtx,
13306 RTX_FRAME_RELATED_P (dwarf) = 1;
13308 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13311 /* Restore the low register's original value. */
13312 emit_insn (gen_movsi (reg, spare));
13314 /* Emit a USE of the restored scratch register, so that flow
13315 analysis will not consider the restore redundant. The
13316 register won't be used again in this function and isn't
13317 restored by the epilogue. */
13318 emit_insn (gen_prologue_use (reg));
13322 reg = gen_rtx_REG (SImode, regno);
13324 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13326 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13327 stack_pointer_rtx, reg));
13328 RTX_FRAME_RELATED_P (insn) = 1;
13329 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13330 plus_constant (stack_pointer_rtx,
13332 RTX_FRAME_RELATED_P (dwarf) = 1;
13334 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13338 /* If the frame pointer is needed, emit a special barrier that
13339 will prevent the scheduler from moving stores to the frame
13340 before the stack adjustment. */
13341 if (frame_pointer_needed)
13342 emit_insn (gen_stack_tie (stack_pointer_rtx,
13343 hard_frame_pointer_rtx));
13346 if (current_function_profile || !TARGET_SCHED_PROLOG)
13347 emit_insn (gen_blockage ());
13349 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13350 if (live_regs_mask & 0xff)
13351 cfun->machine->lr_save_eliminated = 0;
13353 /* If the link register is being kept alive, with the return address in it,
13354 then make sure that it does not get reused by the ce2 pass. */
13355 if (cfun->machine->lr_save_eliminated)
13356 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13361 thumb_expand_epilogue (void)
13363 HOST_WIDE_INT amount;
13364 arm_stack_offsets *offsets;
13367 /* Naked functions don't have prologues. */
13368 if (IS_NAKED (arm_current_func_type ()))
13371 offsets = arm_get_frame_offsets ();
13372 amount = offsets->outgoing_args - offsets->saved_regs;
13374 if (frame_pointer_needed)
13375 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13379 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13380 GEN_INT (amount)));
13383 /* r3 is always free in the epilogue. */
13384 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13386 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13387 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13391 /* Emit a USE (stack_pointer_rtx), so that
13392 the stack adjustment will not be deleted. */
13393 emit_insn (gen_prologue_use (stack_pointer_rtx));
13395 if (current_function_profile || !TARGET_SCHED_PROLOG)
13396 emit_insn (gen_blockage ());
13398 /* Emit a clobber for each insn that will be restored in the epilogue,
13399 so that flow2 will get register lifetimes correct. */
13400 for (regno = 0; regno < 13; regno++)
13401 if (regs_ever_live[regno] && !call_used_regs[regno])
13402 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13404 if (! regs_ever_live[LR_REGNUM])
13405 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13409 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13411 unsigned long live_regs_mask = 0;
13412 unsigned long l_mask;
13413 unsigned high_regs_pushed = 0;
13414 int cfa_offset = 0;
13417 if (IS_NAKED (arm_current_func_type ()))
13420 if (is_called_in_ARM_mode (current_function_decl))
13424 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
13425 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
13427 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13429 /* Generate code sequence to switch us into Thumb mode. */
13430 /* The .code 32 directive has already been emitted by
13431 ASM_DECLARE_FUNCTION_NAME. */
13432 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13433 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13435 /* Generate a label, so that the debugger will notice the
13436 change in instruction sets. This label is also used by
13437 the assembler to bypass the ARM code when this function
13438 is called from a Thumb encoded function elsewhere in the
13439 same file. Hence the definition of STUB_NAME here must
13440 agree with the definition in gas/config/tc-arm.c. */
13442 #define STUB_NAME ".real_start_of"
13444 fprintf (f, "\t.code\t16\n");
13446 if (arm_dllexport_name_p (name))
13447 name = arm_strip_name_encoding (name);
13449 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13450 fprintf (f, "\t.thumb_func\n");
13451 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13454 if (current_function_pretend_args_size)
13456 /* Output unwind directive for the stack adjustment. */
13457 if (ARM_EABI_UNWIND_TABLES)
13458 fprintf (f, "\t.pad #%d\n",
13459 current_function_pretend_args_size);
13461 if (cfun->machine->uses_anonymous_args)
13465 fprintf (f, "\tpush\t{");
13467 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13469 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13470 regno <= LAST_ARG_REGNUM;
13472 asm_fprintf (f, "%r%s", regno,
13473 regno == LAST_ARG_REGNUM ? "" : ", ");
13475 fprintf (f, "}\n");
13478 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13479 SP_REGNUM, SP_REGNUM,
13480 current_function_pretend_args_size);
13482 /* We don't need to record the stores for unwinding (would it
13483 help the debugger any if we did?), but record the change in
13484 the stack pointer. */
13485 if (dwarf2out_do_frame ())
13487 char *l = dwarf2out_cfi_label ();
13489 cfa_offset = cfa_offset + current_function_pretend_args_size;
13490 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13494 /* Get the registers we are going to push. */
13495 live_regs_mask = thumb_compute_save_reg_mask ();
13496 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13497 l_mask = live_regs_mask & 0x40ff;
13498 /* Then count how many other high registers will need to be pushed. */
13499 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13501 if (TARGET_BACKTRACE)
13504 unsigned work_register;
13506 /* We have been asked to create a stack backtrace structure.
13507 The code looks like this:
13511 0 sub SP, #16 Reserve space for 4 registers.
13512 2 push {R7} Push low registers.
13513 4 add R7, SP, #20 Get the stack pointer before the push.
13514 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13515 8 mov R7, PC Get hold of the start of this code plus 12.
13516 10 str R7, [SP, #16] Store it.
13517 12 mov R7, FP Get hold of the current frame pointer.
13518 14 str R7, [SP, #4] Store it.
13519 16 mov R7, LR Get hold of the current return address.
13520 18 str R7, [SP, #12] Store it.
13521 20 add R7, SP, #16 Point at the start of the backtrace structure.
13522 22 mov FP, R7 Put this value into the frame pointer. */
13524 work_register = thumb_find_work_register (live_regs_mask);
13526 if (ARM_EABI_UNWIND_TABLES)
13527 asm_fprintf (f, "\t.pad #16\n");
13530 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13531 SP_REGNUM, SP_REGNUM);
13533 if (dwarf2out_do_frame ())
13535 char *l = dwarf2out_cfi_label ();
13537 cfa_offset = cfa_offset + 16;
13538 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13543 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13544 offset = bit_count (l_mask) * UNITS_PER_WORD;
13549 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13550 offset + 16 + current_function_pretend_args_size);
13552 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13555 /* Make sure that the instruction fetching the PC is in the right place
13556 to calculate "start of backtrace creation code + 12". */
13559 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13560 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13562 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13563 ARM_HARD_FRAME_POINTER_REGNUM);
13564 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13569 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13570 ARM_HARD_FRAME_POINTER_REGNUM);
13571 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13573 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13574 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13578 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13579 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13581 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13583 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13584 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13586 /* Optimization: If we are not pushing any low registers but we are going
13587 to push some high registers then delay our first push. This will just
13588 be a push of LR and we can combine it with the push of the first high
13590 else if ((l_mask & 0xff) != 0
13591 || (high_regs_pushed == 0 && l_mask))
13592 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13594 if (high_regs_pushed)
13596 unsigned pushable_regs;
13597 unsigned next_hi_reg;
13599 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13600 if (live_regs_mask & (1 << next_hi_reg))
13603 pushable_regs = l_mask & 0xff;
13605 if (pushable_regs == 0)
13606 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13608 while (high_regs_pushed > 0)
13610 unsigned long real_regs_mask = 0;
13612 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
13614 if (pushable_regs & (1 << regno))
13616 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13618 high_regs_pushed --;
13619 real_regs_mask |= (1 << next_hi_reg);
13621 if (high_regs_pushed)
13623 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
13625 if (live_regs_mask & (1 << next_hi_reg))
13630 pushable_regs &= ~((1 << regno) - 1);
13636 /* If we had to find a work register and we have not yet
13637 saved the LR then add it to the list of regs to push. */
13638 if (l_mask == (1 << LR_REGNUM))
13640 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
13642 real_regs_mask | (1 << LR_REGNUM));
13646 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13651 /* Handle the case of a double word load into a low register from
13652 a computed memory address. The computed address may involve a
13653 register which is overwritten by the load. */
13655 thumb_load_double_from_address (rtx *operands)
13663 gcc_assert (GET_CODE (operands[0]) == REG);
13664 gcc_assert (GET_CODE (operands[1]) == MEM);
13666 /* Get the memory address. */
13667 addr = XEXP (operands[1], 0);
13669 /* Work out how the memory address is computed. */
13670 switch (GET_CODE (addr))
13673 operands[2] = gen_rtx_MEM (SImode,
13674 plus_constant (XEXP (operands[1], 0), 4));
13676 if (REGNO (operands[0]) == REGNO (addr))
13678 output_asm_insn ("ldr\t%H0, %2", operands);
13679 output_asm_insn ("ldr\t%0, %1", operands);
13683 output_asm_insn ("ldr\t%0, %1", operands);
13684 output_asm_insn ("ldr\t%H0, %2", operands);
13689 /* Compute <address> + 4 for the high order load. */
13690 operands[2] = gen_rtx_MEM (SImode,
13691 plus_constant (XEXP (operands[1], 0), 4));
13693 output_asm_insn ("ldr\t%0, %1", operands);
13694 output_asm_insn ("ldr\t%H0, %2", operands);
13698 arg1 = XEXP (addr, 0);
13699 arg2 = XEXP (addr, 1);
13701 if (CONSTANT_P (arg1))
13702 base = arg2, offset = arg1;
13704 base = arg1, offset = arg2;
13706 gcc_assert (GET_CODE (base) == REG);
13708 /* Catch the case of <address> = <reg> + <reg> */
13709 if (GET_CODE (offset) == REG)
13711 int reg_offset = REGNO (offset);
13712 int reg_base = REGNO (base);
13713 int reg_dest = REGNO (operands[0]);
13715 /* Add the base and offset registers together into the
13716 higher destination register. */
13717 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13718 reg_dest + 1, reg_base, reg_offset);
13720 /* Load the lower destination register from the address in
13721 the higher destination register. */
13722 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13723 reg_dest, reg_dest + 1);
13725 /* Load the higher destination register from its own address
13727 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13728 reg_dest + 1, reg_dest + 1);
13732 /* Compute <address> + 4 for the high order load. */
13733 operands[2] = gen_rtx_MEM (SImode,
13734 plus_constant (XEXP (operands[1], 0), 4));
13736 /* If the computed address is held in the low order register
13737 then load the high order register first, otherwise always
13738 load the low order register first. */
13739 if (REGNO (operands[0]) == REGNO (base))
13741 output_asm_insn ("ldr\t%H0, %2", operands);
13742 output_asm_insn ("ldr\t%0, %1", operands);
13746 output_asm_insn ("ldr\t%0, %1", operands);
13747 output_asm_insn ("ldr\t%H0, %2", operands);
13753 /* With no registers to worry about we can just load the value
13755 operands[2] = gen_rtx_MEM (SImode,
13756 plus_constant (XEXP (operands[1], 0), 4));
13758 output_asm_insn ("ldr\t%H0, %2", operands);
13759 output_asm_insn ("ldr\t%0, %1", operands);
13763 gcc_unreachable ();
13770 thumb_output_move_mem_multiple (int n, rtx *operands)
13777 if (REGNO (operands[4]) > REGNO (operands[5]))
13780 operands[4] = operands[5];
13783 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13784 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13788 if (REGNO (operands[4]) > REGNO (operands[5]))
13791 operands[4] = operands[5];
13794 if (REGNO (operands[5]) > REGNO (operands[6]))
13797 operands[5] = operands[6];
13800 if (REGNO (operands[4]) > REGNO (operands[5]))
13803 operands[4] = operands[5];
13807 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13808 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13812 gcc_unreachable ();
13818 /* Output a call-via instruction for thumb state. */
13820 thumb_call_via_reg (rtx reg)
13822 int regno = REGNO (reg);
13825 gcc_assert (regno < LR_REGNUM);
13827 /* If we are in the normal text section we can use a single instance
13828 per compilation unit. If we are doing function sections, then we need
13829 an entry per section, since we can't rely on reachability. */
13830 if (in_text_section ())
13832 thumb_call_reg_needed = 1;
13834 if (thumb_call_via_label[regno] == NULL)
13835 thumb_call_via_label[regno] = gen_label_rtx ();
13836 labelp = thumb_call_via_label + regno;
13840 if (cfun->machine->call_via[regno] == NULL)
13841 cfun->machine->call_via[regno] = gen_label_rtx ();
13842 labelp = cfun->machine->call_via + regno;
13845 output_asm_insn ("bl\t%a0", labelp);
13849 /* Routines for generating rtl. */
13851 thumb_expand_movmemqi (rtx *operands)
13853 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13854 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13855 HOST_WIDE_INT len = INTVAL (operands[2]);
13856 HOST_WIDE_INT offset = 0;
13860 emit_insn (gen_movmem12b (out, in, out, in));
13866 emit_insn (gen_movmem8b (out, in, out, in));
13872 rtx reg = gen_reg_rtx (SImode);
13873 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13874 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13881 rtx reg = gen_reg_rtx (HImode);
13882 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13883 plus_constant (in, offset))));
13884 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13892 rtx reg = gen_reg_rtx (QImode);
13893 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13894 plus_constant (in, offset))));
13895 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13901 thumb_reload_out_hi (rtx *operands)
13903 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13906 /* Handle reading a half-word from memory during reload. */
13908 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13910 gcc_unreachable ();
13913 /* Return the length of a function name prefix
13914 that starts with the character 'c'. */
13916 arm_get_strip_length (int c)
13920 ARM_NAME_ENCODING_LENGTHS
13925 /* Return a pointer to a function's name with any
13926 and all prefix encodings stripped from it. */
13928 arm_strip_name_encoding (const char *name)
13932 while ((skip = arm_get_strip_length (* name)))
13938 /* If there is a '*' anywhere in the name's prefix, then
13939 emit the stripped name verbatim, otherwise prepend an
13940 underscore if leading underscores are being used. */
13942 arm_asm_output_labelref (FILE *stream, const char *name)
13947 while ((skip = arm_get_strip_length (* name)))
13949 verbatim |= (*name == '*');
13954 fputs (name, stream);
13956 asm_fprintf (stream, "%U%s", name);
13960 arm_file_end (void)
13964 if (! thumb_call_reg_needed)
13968 asm_fprintf (asm_out_file, "\t.code 16\n");
13969 ASM_OUTPUT_ALIGN (asm_out_file, 1);
13971 for (regno = 0; regno < LR_REGNUM; regno++)
13973 rtx label = thumb_call_via_label[regno];
13977 targetm.asm_out.internal_label (asm_out_file, "L",
13978 CODE_LABEL_NUMBER (label));
13979 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
13986 #ifdef AOF_ASSEMBLER
13987 /* Special functions only needed when producing AOF syntax assembler. */
13991 struct pic_chain * next;
13992 const char * symname;
13995 static struct pic_chain * aof_pic_chain = NULL;
13998 aof_pic_entry (rtx x)
14000 struct pic_chain ** chainp;
14003 if (aof_pic_label == NULL_RTX)
14005 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14008 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14009 offset += 4, chainp = &(*chainp)->next)
14010 if ((*chainp)->symname == XSTR (x, 0))
14011 return plus_constant (aof_pic_label, offset);
14013 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14014 (*chainp)->next = NULL;
14015 (*chainp)->symname = XSTR (x, 0);
14016 return plus_constant (aof_pic_label, offset);
14020 aof_dump_pic_table (FILE *f)
14022 struct pic_chain * chain;
14024 if (aof_pic_chain == NULL)
14027 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14028 PIC_OFFSET_TABLE_REGNUM,
14029 PIC_OFFSET_TABLE_REGNUM);
14030 fputs ("|x$adcons|\n", f);
14032 for (chain = aof_pic_chain; chain; chain = chain->next)
14034 fputs ("\tDCD\t", f);
14035 assemble_name (f, chain->symname);
14040 int arm_text_section_count = 1;
14043 aof_text_section (void )
14045 static char buf[100];
14046 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14047 arm_text_section_count++);
14049 strcat (buf, ", PIC, REENTRANT");
14053 static int arm_data_section_count = 1;
14056 aof_data_section (void)
14058 static char buf[100];
14059 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14063 /* The AOF assembler is religiously strict about declarations of
14064 imported and exported symbols, so that it is impossible to declare
14065 a function as imported near the beginning of the file, and then to
14066 export it later on. It is, however, possible to delay the decision
14067 until all the functions in the file have been compiled. To get
14068 around this, we maintain a list of the imports and exports, and
14069 delete from it any that are subsequently defined. At the end of
14070 compilation we spit the remainder of the list out before the END
14075 struct import * next;
14079 static struct import * imports_list = NULL;
14082 aof_add_import (const char *name)
14084 struct import * new;
14086 for (new = imports_list; new; new = new->next)
14087 if (new->name == name)
14090 new = (struct import *) xmalloc (sizeof (struct import));
14091 new->next = imports_list;
14092 imports_list = new;
14097 aof_delete_import (const char *name)
14099 struct import ** old;
14101 for (old = &imports_list; *old; old = & (*old)->next)
14103 if ((*old)->name == name)
14105 *old = (*old)->next;
14111 int arm_main_function = 0;
14114 aof_dump_imports (FILE *f)
14116 /* The AOF assembler needs this to cause the startup code to be extracted
14117 from the library. Brining in __main causes the whole thing to work
14119 if (arm_main_function)
14122 fputs ("\tIMPORT __main\n", f);
14123 fputs ("\tDCD __main\n", f);
14126 /* Now dump the remaining imports. */
14127 while (imports_list)
14129 fprintf (f, "\tIMPORT\t");
14130 assemble_name (f, imports_list->name);
14132 imports_list = imports_list->next;
14137 aof_globalize_label (FILE *stream, const char *name)
14139 default_globalize_label (stream, name);
14140 if (! strcmp (name, "main"))
14141 arm_main_function = 1;
14145 aof_file_start (void)
14147 fputs ("__r0\tRN\t0\n", asm_out_file);
14148 fputs ("__a1\tRN\t0\n", asm_out_file);
14149 fputs ("__a2\tRN\t1\n", asm_out_file);
14150 fputs ("__a3\tRN\t2\n", asm_out_file);
14151 fputs ("__a4\tRN\t3\n", asm_out_file);
14152 fputs ("__v1\tRN\t4\n", asm_out_file);
14153 fputs ("__v2\tRN\t5\n", asm_out_file);
14154 fputs ("__v3\tRN\t6\n", asm_out_file);
14155 fputs ("__v4\tRN\t7\n", asm_out_file);
14156 fputs ("__v5\tRN\t8\n", asm_out_file);
14157 fputs ("__v6\tRN\t9\n", asm_out_file);
14158 fputs ("__sl\tRN\t10\n", asm_out_file);
14159 fputs ("__fp\tRN\t11\n", asm_out_file);
14160 fputs ("__ip\tRN\t12\n", asm_out_file);
14161 fputs ("__sp\tRN\t13\n", asm_out_file);
14162 fputs ("__lr\tRN\t14\n", asm_out_file);
14163 fputs ("__pc\tRN\t15\n", asm_out_file);
14164 fputs ("__f0\tFN\t0\n", asm_out_file);
14165 fputs ("__f1\tFN\t1\n", asm_out_file);
14166 fputs ("__f2\tFN\t2\n", asm_out_file);
14167 fputs ("__f3\tFN\t3\n", asm_out_file);
14168 fputs ("__f4\tFN\t4\n", asm_out_file);
14169 fputs ("__f5\tFN\t5\n", asm_out_file);
14170 fputs ("__f6\tFN\t6\n", asm_out_file);
14171 fputs ("__f7\tFN\t7\n", asm_out_file);
14176 aof_file_end (void)
14179 aof_dump_pic_table (asm_out_file);
14181 aof_dump_imports (asm_out_file);
14182 fputs ("\tEND\n", asm_out_file);
14184 #endif /* AOF_ASSEMBLER */
14187 /* Symbols in the text segment can be accessed without indirecting via the
14188 constant pool; it may take an extra binary operation, but this is still
14189 faster than indirecting via memory. Don't do this when not optimizing,
14190 since we won't be calculating al of the offsets necessary to do this
14194 arm_encode_section_info (tree decl, rtx rtl, int first)
14196 /* This doesn't work with AOF syntax, since the string table may be in
14197 a different AREA. */
14198 #ifndef AOF_ASSEMBLER
14199 if (optimize > 0 && TREE_CONSTANT (decl))
14200 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14203 /* If we are referencing a function that is weak then encode a long call
14204 flag in the function name, otherwise if the function is static or
14205 or known to be defined in this file then encode a short call flag. */
14206 if (first && DECL_P (decl))
14208 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14209 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14210 else if (! TREE_PUBLIC (decl))
14211 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14214 #endif /* !ARM_PE */
14217 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14219 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14220 && !strcmp (prefix, "L"))
14222 arm_ccfsm_state = 0;
14223 arm_target_insn = NULL;
14225 default_internal_label (stream, prefix, labelno);
14228 /* Output code to add DELTA to the first argument, and then jump
14229 to FUNCTION. Used for C++ multiple inheritance. */
14231 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14232 HOST_WIDE_INT delta,
14233 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14236 static int thunk_label = 0;
14238 int mi_delta = delta;
14239 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14241 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14244 mi_delta = - mi_delta;
14247 int labelno = thunk_label++;
14248 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14249 fputs ("\tldr\tr12, ", file);
14250 assemble_name (file, label);
14251 fputc ('\n', file);
14253 while (mi_delta != 0)
14255 if ((mi_delta & (3 << shift)) == 0)
14259 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14260 mi_op, this_regno, this_regno,
14261 mi_delta & (0xff << shift));
14262 mi_delta &= ~(0xff << shift);
14268 fprintf (file, "\tbx\tr12\n");
14269 ASM_OUTPUT_ALIGN (file, 2);
14270 assemble_name (file, label);
14271 fputs (":\n", file);
14272 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14276 fputs ("\tb\t", file);
14277 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14278 if (NEED_PLT_RELOC)
14279 fputs ("(PLT)", file);
14280 fputc ('\n', file);
14285 arm_emit_vector_const (FILE *file, rtx x)
14288 const char * pattern;
14290 gcc_assert (GET_CODE (x) == CONST_VECTOR);
14292 switch (GET_MODE (x))
14294 case V2SImode: pattern = "%08x"; break;
14295 case V4HImode: pattern = "%04x"; break;
14296 case V8QImode: pattern = "%02x"; break;
14297 default: gcc_unreachable ();
14300 fprintf (file, "0x");
14301 for (i = CONST_VECTOR_NUNITS (x); i--;)
14305 element = CONST_VECTOR_ELT (x, i);
14306 fprintf (file, pattern, INTVAL (element));
14313 arm_output_load_gr (rtx *operands)
14320 if (GET_CODE (operands [1]) != MEM
14321 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14322 || GET_CODE (reg = XEXP (sum, 0)) != REG
14323 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14324 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14325 return "wldrw%?\t%0, %1";
14327 /* Fix up an out-of-range load of a GR register. */
14328 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14329 wcgr = operands[0];
14331 output_asm_insn ("ldr%?\t%0, %1", operands);
14333 operands[0] = wcgr;
14335 output_asm_insn ("tmcr%?\t%0, %1", operands);
14336 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14342 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14343 int incoming ATTRIBUTE_UNUSED)
14346 /* FIXME: The ARM backend has special code to handle structure
14347 returns, and will reserve its own hidden first argument. So
14348 if this macro is enabled a *second* hidden argument will be
14349 reserved, which will break binary compatibility with old
14350 toolchains and also thunk handling. One day this should be
14354 /* Register in which address to store a structure value
14355 is passed to a function. */
14356 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14360 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14362 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14363 named arg and all anonymous args onto the stack.
14364 XXX I know the prologue shouldn't be pushing registers, but it is faster
14368 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14369 enum machine_mode mode ATTRIBUTE_UNUSED,
14370 tree type ATTRIBUTE_UNUSED,
14372 int second_time ATTRIBUTE_UNUSED)
14374 cfun->machine->uses_anonymous_args = 1;
14375 if (cum->nregs < NUM_ARG_REGS)
14376 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14379 /* Return nonzero if the CONSUMER instruction (a store) does not need
14380 PRODUCER's value to calculate the address. */
14383 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14385 rtx value = PATTERN (producer);
14386 rtx addr = PATTERN (consumer);
14388 if (GET_CODE (value) == COND_EXEC)
14389 value = COND_EXEC_CODE (value);
14390 if (GET_CODE (value) == PARALLEL)
14391 value = XVECEXP (value, 0, 0);
14392 value = XEXP (value, 0);
14393 if (GET_CODE (addr) == COND_EXEC)
14394 addr = COND_EXEC_CODE (addr);
14395 if (GET_CODE (addr) == PARALLEL)
14396 addr = XVECEXP (addr, 0, 0);
14397 addr = XEXP (addr, 0);
14399 return !reg_overlap_mentioned_p (value, addr);
14402 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14403 have an early register shift value or amount dependency on the
14404 result of PRODUCER. */
14407 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14409 rtx value = PATTERN (producer);
14410 rtx op = PATTERN (consumer);
14413 if (GET_CODE (value) == COND_EXEC)
14414 value = COND_EXEC_CODE (value);
14415 if (GET_CODE (value) == PARALLEL)
14416 value = XVECEXP (value, 0, 0);
14417 value = XEXP (value, 0);
14418 if (GET_CODE (op) == COND_EXEC)
14419 op = COND_EXEC_CODE (op);
14420 if (GET_CODE (op) == PARALLEL)
14421 op = XVECEXP (op, 0, 0);
14424 early_op = XEXP (op, 0);
14425 /* This is either an actual independent shift, or a shift applied to
14426 the first operand of another operation. We want the whole shift
14428 if (GET_CODE (early_op) == REG)
14431 return !reg_overlap_mentioned_p (value, early_op);
14434 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14435 have an early register shift value dependency on the result of
14439 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14441 rtx value = PATTERN (producer);
14442 rtx op = PATTERN (consumer);
14445 if (GET_CODE (value) == COND_EXEC)
14446 value = COND_EXEC_CODE (value);
14447 if (GET_CODE (value) == PARALLEL)
14448 value = XVECEXP (value, 0, 0);
14449 value = XEXP (value, 0);
14450 if (GET_CODE (op) == COND_EXEC)
14451 op = COND_EXEC_CODE (op);
14452 if (GET_CODE (op) == PARALLEL)
14453 op = XVECEXP (op, 0, 0);
14456 early_op = XEXP (op, 0);
14458 /* This is either an actual independent shift, or a shift applied to
14459 the first operand of another operation. We want the value being
14460 shifted, in either case. */
14461 if (GET_CODE (early_op) != REG)
14462 early_op = XEXP (early_op, 0);
14464 return !reg_overlap_mentioned_p (value, early_op);
14467 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14468 have an early register mult dependency on the result of
14472 arm_no_early_mul_dep (rtx producer, rtx consumer)
14474 rtx value = PATTERN (producer);
14475 rtx op = PATTERN (consumer);
14477 if (GET_CODE (value) == COND_EXEC)
14478 value = COND_EXEC_CODE (value);
14479 if (GET_CODE (value) == PARALLEL)
14480 value = XVECEXP (value, 0, 0);
14481 value = XEXP (value, 0);
14482 if (GET_CODE (op) == COND_EXEC)
14483 op = COND_EXEC_CODE (op);
14484 if (GET_CODE (op) == PARALLEL)
14485 op = XVECEXP (op, 0, 0);
14488 return (GET_CODE (op) == PLUS
14489 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14493 /* We can't rely on the caller doing the proper promotion when
14494 using APCS or ATPCS. */
14497 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14499 return !TARGET_AAPCS_BASED;
14503 /* AAPCS based ABIs use short enums by default. */
14506 arm_default_short_enums (void)
14508 return TARGET_AAPCS_BASED;
14512 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14515 arm_align_anon_bitfield (void)
14517 return TARGET_AAPCS_BASED;
14521 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14524 arm_cxx_guard_type (void)
14526 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14530 /* The EABI says test the least significant bit of a guard variable. */
14533 arm_cxx_guard_mask_bit (void)
14535 return TARGET_AAPCS_BASED;
14539 /* The EABI specifies that all array cookies are 8 bytes long. */
14542 arm_get_cookie_size (tree type)
14546 if (!TARGET_AAPCS_BASED)
14547 return default_cxx_get_cookie_size (type);
14549 size = build_int_cst (sizetype, 8);
14554 /* The EABI says that array cookies should also contain the element size. */
14557 arm_cookie_has_size (void)
14559 return TARGET_AAPCS_BASED;
14563 /* The EABI says constructors and destructors should return a pointer to
14564 the object constructed/destroyed. */
14567 arm_cxx_cdtor_returns_this (void)
14569 return TARGET_AAPCS_BASED;
14572 /* The EABI says that an inline function may never be the key
14576 arm_cxx_key_method_may_be_inline (void)
14578 return !TARGET_AAPCS_BASED;
14582 arm_cxx_determine_class_data_visibility (tree decl)
14584 if (!TARGET_AAPCS_BASED)
14587 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
14588 is exported. However, on systems without dynamic vague linkage,
14589 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
14590 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
14591 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
14593 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
14594 DECL_VISIBILITY_SPECIFIED (decl) = 1;
14598 arm_cxx_class_data_always_comdat (void)
14600 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
14601 vague linkage if the class has no key function. */
14602 return !TARGET_AAPCS_BASED;
14606 /* The EABI says __aeabi_atexit should be used to register static
14610 arm_cxx_use_aeabi_atexit (void)
14612 return TARGET_AAPCS_BASED;
14617 arm_set_return_address (rtx source, rtx scratch)
14619 arm_stack_offsets *offsets;
14620 HOST_WIDE_INT delta;
14622 unsigned long saved_regs;
14624 saved_regs = arm_compute_save_reg_mask ();
14626 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14627 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14630 if (frame_pointer_needed)
14631 addr = plus_constant(hard_frame_pointer_rtx, -4);
14634 /* LR will be the first saved register. */
14635 offsets = arm_get_frame_offsets ();
14636 delta = offsets->outgoing_args - (offsets->frame + 4);
14641 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14642 GEN_INT (delta & ~4095)));
14647 addr = stack_pointer_rtx;
14649 addr = plus_constant (addr, delta);
14651 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14657 thumb_set_return_address (rtx source, rtx scratch)
14659 arm_stack_offsets *offsets;
14660 HOST_WIDE_INT delta;
14663 unsigned long mask;
14665 emit_insn (gen_rtx_USE (VOIDmode, source));
14667 mask = thumb_compute_save_reg_mask ();
14668 if (mask & (1 << LR_REGNUM))
14670 offsets = arm_get_frame_offsets ();
14672 /* Find the saved regs. */
14673 if (frame_pointer_needed)
14675 delta = offsets->soft_frame - offsets->saved_args;
14676 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14680 delta = offsets->outgoing_args - offsets->saved_args;
14683 /* Allow for the stack frame. */
14684 if (TARGET_BACKTRACE)
14686 /* The link register is always the first saved register. */
14689 /* Construct the address. */
14690 addr = gen_rtx_REG (SImode, reg);
14691 if ((reg != SP_REGNUM && delta >= 128)
14694 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14695 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14699 addr = plus_constant (addr, delta);
14701 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14704 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14707 /* Implements target hook vector_mode_supported_p. */
14709 arm_vector_mode_supported_p (enum machine_mode mode)
14711 if ((mode == V2SImode)
14712 || (mode == V4HImode)
14713 || (mode == V8QImode))
14719 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14720 ARM insns and therefore guarantee that the shift count is modulo 256.
14721 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14722 guarantee no particular behavior for out-of-range counts. */
14724 static unsigned HOST_WIDE_INT
14725 arm_shift_truncation_mask (enum machine_mode mode)
14727 return mode == SImode ? 255 : 0;
14731 /* Map internal gcc register numbers to DWARF2 register numbers. */
14734 arm_dbx_register_number (unsigned int regno)
14739 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
14740 compatibility. The EABI defines them as registers 96-103. */
14741 if (IS_FPA_REGNUM (regno))
14742 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
14744 if (IS_VFP_REGNUM (regno))
14745 return 64 + regno - FIRST_VFP_REGNUM;
14747 if (IS_IWMMXT_GR_REGNUM (regno))
14748 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
14750 if (IS_IWMMXT_REGNUM (regno))
14751 return 112 + regno - FIRST_IWMMXT_REGNUM;
14753 gcc_unreachable ();
14757 #ifdef TARGET_UNWIND_INFO
14758 /* Emit unwind directives for a store-multiple instruction. This should
14759 only ever be generated by the function prologue code, so we expect it
14760 to have a particular form. */
14763 arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
14766 HOST_WIDE_INT offset;
14767 HOST_WIDE_INT nregs;
14773 /* First insn will adjust the stack pointer. */
14774 e = XVECEXP (p, 0, 0);
14775 if (GET_CODE (e) != SET
14776 || GET_CODE (XEXP (e, 0)) != REG
14777 || REGNO (XEXP (e, 0)) != SP_REGNUM
14778 || GET_CODE (XEXP (e, 1)) != PLUS)
14781 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
14782 nregs = XVECLEN (p, 0) - 1;
14784 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
14787 /* The function prologue may also push pc, but not annotate it as it is
14788 never restored. We turn this into a stack pointer adjustment. */
14789 if (nregs * 4 == offset - 4)
14791 fprintf (asm_out_file, "\t.pad #4\n");
14796 else if (IS_VFP_REGNUM (reg))
14798 /* FPA register saves use an additional word. */
14802 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
14804 /* FPA registers are done differently. */
14805 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
14809 /* Unknown register type. */
14812 /* If the stack increment doesn't match the size of the saved registers,
14813 something has gone horribly wrong. */
14814 if (offset != nregs * reg_size)
14817 fprintf (asm_out_file, "\t.save {");
14821 /* The remaining insns will describe the stores. */
14822 for (i = 1; i <= nregs; i++)
14824 /* Expect (set (mem <addr>) (reg)).
14825 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
14826 e = XVECEXP (p, 0, i);
14827 if (GET_CODE (e) != SET
14828 || GET_CODE (XEXP (e, 0)) != MEM
14829 || GET_CODE (XEXP (e, 1)) != REG)
14832 reg = REGNO (XEXP (e, 1));
14837 fprintf (asm_out_file, ", ");
14838 /* We can't use %r for vfp because we need to use the
14839 double precision register names. */
14840 if (IS_VFP_REGNUM (reg))
14841 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
14843 asm_fprintf (asm_out_file, "%r", reg);
14845 #ifdef ENABLE_CHECKING
14846 /* Check that the addresses are consecutive. */
14847 e = XEXP (XEXP (e, 0), 0);
14848 if (GET_CODE (e) == PLUS)
14850 offset += reg_size;
14851 if (GET_CODE (XEXP (e, 0)) != REG
14852 || REGNO (XEXP (e, 0)) != SP_REGNUM
14853 || GET_CODE (XEXP (e, 1)) != CONST_INT
14854 || offset != INTVAL (XEXP (e, 1)))
14858 || GET_CODE (e) != REG
14859 || REGNO (e) != SP_REGNUM)
14863 fprintf (asm_out_file, "}\n");
14866 /* Emit unwind directives for a SET. */
14869 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
14876 switch (GET_CODE (e0))
14879 /* Pushing a single register. */
14880 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
14881 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
14882 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
14885 asm_fprintf (asm_out_file, "\t.save ");
14886 if (IS_VFP_REGNUM (REGNO (e1)))
14887 asm_fprintf(asm_out_file, "{d%d}\n",
14888 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
14890 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
14894 if (REGNO (e0) == SP_REGNUM)
14896 /* A stack increment. */
14897 if (GET_CODE (e1) != PLUS
14898 || GET_CODE (XEXP (e1, 0)) != REG
14899 || REGNO (XEXP (e1, 0)) != SP_REGNUM
14900 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14903 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
14904 -INTVAL (XEXP (e1, 1)));
14906 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
14908 HOST_WIDE_INT offset;
14911 if (GET_CODE (e1) == PLUS)
14913 if (GET_CODE (XEXP (e1, 0)) != REG
14914 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
14916 reg = REGNO (XEXP (e1, 0));
14917 offset = INTVAL (XEXP (e1, 1));
14918 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
14919 HARD_FRAME_POINTER_REGNUM, reg,
14920 INTVAL (XEXP (e1, 1)));
14922 else if (GET_CODE (e1) == REG)
14925 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
14926 HARD_FRAME_POINTER_REGNUM, reg);
14931 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
14933 /* Move from sp to reg. */
14934 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
14946 /* Emit unwind directives for the given insn. */
14949 arm_unwind_emit (FILE * asm_out_file, rtx insn)
14953 if (!ARM_EABI_UNWIND_TABLES)
14956 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
14959 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
14961 pat = XEXP (pat, 0);
14963 pat = PATTERN (insn);
14965 switch (GET_CODE (pat))
14968 arm_unwind_emit_set (asm_out_file, pat);
14972 /* Store multiple. */
14973 arm_unwind_emit_stm (asm_out_file, pat);
14982 /* Output a reference from a function exception table to the type_info
14983 object X. The EABI specifies that the symbol should be relocated by
14984 an R_ARM_TARGET2 relocation. */
14987 arm_output_ttype (rtx x)
14989 fputs ("\t.word\t", asm_out_file);
14990 output_addr_const (asm_out_file, x);
14991 /* Use special relocations for symbol references. */
14992 if (GET_CODE (x) != CONST_INT)
14993 fputs ("(TARGET2)", asm_out_file);
14994 fputc ('\n', asm_out_file);
14998 #endif /* TARGET_UNWIND_INFO */
15001 /* Output unwind directives for the start/end of a function. */
15004 arm_output_fn_unwind (FILE * f, bool prologue)
15006 if (!ARM_EABI_UNWIND_TABLES)
15010 fputs ("\t.fnstart\n", f);
15012 fputs ("\t.fnend\n", f);